drivers/net/wireless/b43/phy_a.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11a PHY driver
   5
   6   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
   7   Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
   8   Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
   9   Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
  10   Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  11
  12   This program is free software; you can redistribute it and/or modify
  13   it under the terms of the GNU General Public License as published by
  14   the Free Software Foundation; either version 2 of the License, or
  15   (at your option) any later version.
  16
  17   This program is distributed in the hope that it will be useful,
  18   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20   GNU General Public License for more details.
  21
  22   You should have received a copy of the GNU General Public License
  23   along with this program; see the file COPYING.  If not, write to
  24   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  25   Boston, MA 02110-1301, USA.
  26
  27 */
  28
  29 #include "b43.h"
  30 #include "phy_a.h"
  31 #include "phy_common.h"
  32 #include "wa.h"
  33 #include "tables.h"
  34 #include "main.h"
  35
  36
  37 /* Get the freq, as it has to be written to the device. */
  38 static inline u16 channel2freq_a(u8 channel)
  39 {
  40         B43_WARN_ON(channel > 200);
  41
  42         return (5000 + 5 * channel);
  43 }
  44
  45 static inline u16 freq_r3A_value(u16 frequency)
  46 {
  47         u16 value;
  48
  49         if (frequency < 5091)
  50                 value = 0x0040;
  51         else if (frequency < 5321)
  52                 value = 0x0000;
  53         else if (frequency < 5806)
  54                 value = 0x0080;
  55         else
  56                 value = 0x0040;
  57
  58         return value;
  59 }
  60
  61 #if 0
  62 /* This function converts a TSSI value to dBm in Q5.2 */
  63 static s8 b43_aphy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
  64 {
  65         struct b43_phy *phy = &dev->phy;
  66         struct b43_phy_a *aphy = phy->a;
  67         s8 dbm = 0;
  68         s32 tmp;
  69
  70         tmp = (aphy->tgt_idle_tssi - aphy->cur_idle_tssi + tssi);
  71         tmp += 0x80;
  72         tmp = clamp_val(tmp, 0x00, 0xFF);
  73         dbm = aphy->tssi2dbm[tmp];
  74         //TODO: There's a FIXME on the specs
  75
  76         return dbm;
  77 }
  78 #endif
  79
  80 static void b43_radio_set_tx_iq(struct b43_wldev *dev)
  81 {
  82         static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
  83         static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
  84         u16 tmp = b43_radio_read16(dev, 0x001E);
  85         int i, j;
  86
  87         for (i = 0; i < 5; i++) {
  88                 for (j = 0; j < 5; j++) {
  89                         if (tmp == (data_high[i] << 4 | data_low[j])) {
  90                                 b43_phy_write(dev, 0x0069,
  91                                               (i - j) << 8 | 0x00C0);
  92                                 return;
  93                         }
  94                 }
  95         }
  96 }
  97
  98 static void aphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
  99 {
 100         u16 freq, r8, tmp;
 101
 102         freq = channel2freq_a(channel);
 103
 104         r8 = b43_radio_read16(dev, 0x0008);
 105         b43_write16(dev, 0x03F0, freq);
 106         b43_radio_write16(dev, 0x0008, r8);
 107
 108         //TODO: write max channel TX power? to Radio 0x2D
 109         tmp = b43_radio_read16(dev, 0x002E);
 110         tmp &= 0x0080;
 111         //TODO: OR tmp with the Power out estimation for this channel?
 112         b43_radio_write16(dev, 0x002E, tmp);
 113
 114         if (freq >= 4920 && freq <= 5500) {
 115                 /*
 116                  * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
 117                  *    = (freq * 0.025862069
 118                  */
 119                 r8 = 3 * freq / 116;    /* is equal to r8 = freq * 0.025862 */
 120         }
 121         b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
 122         b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
 123         b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
 124         b43_radio_write16(dev, 0x0022, (b43_radio_read16(dev, 0x0022)
 125                                         & 0x000F) | (r8 << 4));
 126         b43_radio_write16(dev, 0x002A, (r8 << 4));
 127         b43_radio_write16(dev, 0x002B, (r8 << 4));
 128         b43_radio_write16(dev, 0x0008, (b43_radio_read16(dev, 0x0008)
 129                                         & 0x00F0) | (r8 << 4));
 130         b43_radio_write16(dev, 0x0029, (b43_radio_read16(dev, 0x0029)
 131                                         & 0xFF0F) | 0x00B0);
 132         b43_radio_write16(dev, 0x0035, 0x00AA);
 133         b43_radio_write16(dev, 0x0036, 0x0085);
 134         b43_radio_write16(dev, 0x003A, (b43_radio_read16(dev, 0x003A)
 135                                         & 0xFF20) |
 136                           freq_r3A_value(freq));
 137         b43_radio_write16(dev, 0x003D,
 138                           b43_radio_read16(dev, 0x003D) & 0x00FF);
 139         b43_radio_write16(dev, 0x0081, (b43_radio_read16(dev, 0x0081)
 140                                         & 0xFF7F) | 0x0080);
 141         b43_radio_write16(dev, 0x0035,
 142                           b43_radio_read16(dev, 0x0035) & 0xFFEF);
 143         b43_radio_write16(dev, 0x0035, (b43_radio_read16(dev, 0x0035)
 144                                         & 0xFFEF) | 0x0010);
 145         b43_radio_set_tx_iq(dev);
 146         //TODO: TSSI2dbm workaround
 147 //FIXME b43_phy_xmitpower(dev);
 148 }
 149
 150 static void b43_radio_init2060(struct b43_wldev *dev)
 151 {
 152         b43_radio_write16(dev, 0x0004, 0x00C0);
 153         b43_radio_write16(dev, 0x0005, 0x0008);
 154         b43_radio_write16(dev, 0x0009, 0x0040);
 155         b43_radio_write16(dev, 0x0005, 0x00AA);
 156         b43_radio_write16(dev, 0x0032, 0x008F);
 157         b43_radio_write16(dev, 0x0006, 0x008F);
 158         b43_radio_write16(dev, 0x0034, 0x008F);
 159         b43_radio_write16(dev, 0x002C, 0x0007);
 160         b43_radio_write16(dev, 0x0082, 0x0080);
 161         b43_radio_write16(dev, 0x0080, 0x0000);
 162         b43_radio_write16(dev, 0x003F, 0x00DA);
 163         b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
 164         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0010);
 165         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
 166         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
 167         msleep(1);              /* delay 400usec */
 168
 169         b43_radio_write16(dev, 0x0081,
 170                           (b43_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
 171         msleep(1);              /* delay 400usec */
 172
 173         b43_radio_write16(dev, 0x0005,
 174                           (b43_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
 175         b43_radio_write16(dev, 0x0085, b43_radio_read16(dev, 0x0085) & ~0x0010);
 176         b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
 177         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0040);
 178         b43_radio_write16(dev, 0x0081,
 179                           (b43_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
 180         b43_radio_write16(dev, 0x0005,
 181                           (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
 182         b43_phy_write(dev, 0x0063, 0xDDC6);
 183         b43_phy_write(dev, 0x0069, 0x07BE);
 184         b43_phy_write(dev, 0x006A, 0x0000);
 185
 186         aphy_channel_switch(dev, dev->phy.ops->get_default_chan(dev));
 187
 188         msleep(1);
 189 }
 190
 191 static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable)
 192 {
 193         int i;
 194
 195         if (dev->phy.rev < 3) {
 196                 if (enable)
 197                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
 198                                 b43_ofdmtab_write16(dev,
 199                                         B43_OFDMTAB_LNAHPFGAIN1, i, 0xFFF8);
 200                                 b43_ofdmtab_write16(dev,
 201                                         B43_OFDMTAB_WRSSI, i, 0xFFF8);
 202                         }
 203                 else
 204                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
 205                                 b43_ofdmtab_write16(dev,
 206                                         B43_OFDMTAB_LNAHPFGAIN1, i, b43_tab_rssiagc1[i]);
 207                                 b43_ofdmtab_write16(dev,
 208                                         B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc1[i]);
 209                         }
 210         } else {
 211                 if (enable)
 212                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++)
 213                                 b43_ofdmtab_write16(dev,
 214                                         B43_OFDMTAB_WRSSI, i, 0x0820);
 215                 else
 216                         for (i = 0; i < B43_TAB_RSSIAGC2_SIZE; i++)
 217                                 b43_ofdmtab_write16(dev,
 218                                         B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc2[i]);
 219         }
 220 }
 221
 222 static void b43_phy_ww(struct b43_wldev *dev)
 223 {
 224         u16 b, curr_s, best_s = 0xFFFF;
 225         int i;
 226
 227         b43_phy_mask(dev, B43_PHY_CRS0, ~B43_PHY_CRS0_EN);
 228         b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000);
 229         b43_phy_maskset(dev, B43_PHY_OFDM(0x82), 0xF0FF, 0x0300);
 230         b43_radio_write16(dev, 0x0009,
 231                 b43_radio_read16(dev, 0x0009) | 0x0080);
 232         b43_radio_write16(dev, 0x0012,
 233                 (b43_radio_read16(dev, 0x0012) & 0xFFFC) | 0x0002);
 234         b43_wa_initgains(dev);
 235         b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5);
 236         b = b43_phy_read(dev, B43_PHY_PWRDOWN);
 237         b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005);
 238         b43_radio_write16(dev, 0x0004,
 239                 b43_radio_read16(dev, 0x0004) | 0x0004);
 240         for (i = 0x10; i <= 0x20; i++) {
 241                 b43_radio_write16(dev, 0x0013, i);
 242                 curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF;
 243                 if (!curr_s) {
 244                         best_s = 0x0000;
 245                         break;
 246                 } else if (curr_s >= 0x0080)
 247                         curr_s = 0x0100 - curr_s;
 248                 if (curr_s < best_s)
 249                         best_s = curr_s;
 250         }
 251         b43_phy_write(dev, B43_PHY_PWRDOWN, b);
 252         b43_radio_write16(dev, 0x0004,
 253                 b43_radio_read16(dev, 0x0004) & 0xFFFB);
 254         b43_radio_write16(dev, 0x0013, best_s);
 255         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC);
 256         b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80);
 257         b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00);
 258         b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);
 259         b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);
 260         b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);
 261         b43_phy_maskset(dev, B43_PHY_OFDM(0xBB), 0xF000, 0x0053);
 262         b43_phy_maskset(dev, B43_PHY_OFDM61, 0xFE1F, 0x0120);
 263         b43_phy_maskset(dev, B43_PHY_OFDM(0x13), 0x0FFF, 0x3000);
 264         b43_phy_maskset(dev, B43_PHY_OFDM(0x14), 0x0FFF, 0x3000);
 265         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);
 266         for (i = 0; i < 6; i++)
 267                 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);
 268         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E);
 269         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011);
 270         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013);
 271         b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030);
 272         b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);
 273 }
 274
 275 static void hardware_pctl_init_aphy(struct b43_wldev *dev)
 276 {
 277         //TODO
 278 }
 279
 280 void b43_phy_inita(struct b43_wldev *dev)
 281 {
 282         struct ssb_bus *bus = dev->dev->bus;
 283         struct b43_phy *phy = &dev->phy;
 284
 285         /* This lowlevel A-PHY init is also called from G-PHY init.
 286          * So we must not access phy->a, if called from G-PHY code.
 287          */
 288         B43_WARN_ON((phy->type != B43_PHYTYPE_A) &&
 289                     (phy->type != B43_PHYTYPE_G));
 290
 291         might_sleep();
 292
 293         if (phy->rev >= 6) {
 294                 if (phy->type == B43_PHYTYPE_A)
 295                         b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x1000);
 296                 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
 297                         b43_phy_set(dev, B43_PHY_ENCORE, 0x0010);
 298                 else
 299                         b43_phy_mask(dev, B43_PHY_ENCORE, ~0x1010);
 300         }
 301
 302         b43_wa_all(dev);
 303
 304         if (phy->type == B43_PHYTYPE_A) {
 305                 if (phy->gmode && (phy->rev < 3))
 306                         b43_phy_set(dev, 0x0034, 0x0001);
 307                 b43_phy_rssiagc(dev, 0);
 308
 309                 b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);
 310
 311                 b43_radio_init2060(dev);
 312
 313                 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
 314                     ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
 315                      (bus->boardinfo.type == SSB_BOARD_BU4309))) {
 316                         ; //TODO: A PHY LO
 317                 }
 318
 319                 if (phy->rev >= 3)
 320                         b43_phy_ww(dev);
 321
 322                 hardware_pctl_init_aphy(dev);
 323
 324                 //TODO: radar detection
 325         }
 326
 327         if ((phy->type == B43_PHYTYPE_G) &&
 328             (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)) {
 329                 b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF);
 330         }
 331 }
 332
 333 /* Initialise the TSSI->dBm lookup table */
 334 static int b43_aphy_init_tssi2dbm_table(struct b43_wldev *dev)
 335 {
 336         struct b43_phy *phy = &dev->phy;
 337         struct b43_phy_a *aphy = phy->a;
 338         s16 pab0, pab1, pab2;
 339
 340         pab0 = (s16) (dev->dev->bus->sprom.pa1b0);
 341         pab1 = (s16) (dev->dev->bus->sprom.pa1b1);
 342         pab2 = (s16) (dev->dev->bus->sprom.pa1b2);
 343
 344         if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
 345             pab0 != -1 && pab1 != -1 && pab2 != -1) {
 346                 /* The pabX values are set in SPROM. Use them. */
 347                 if ((s8) dev->dev->bus->sprom.itssi_a != 0 &&
 348                     (s8) dev->dev->bus->sprom.itssi_a != -1)
 349                         aphy->tgt_idle_tssi =
 350                             (s8) (dev->dev->bus->sprom.itssi_a);
 351                 else
 352                         aphy->tgt_idle_tssi = 62;
 353                 aphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
 354                                                                pab1, pab2);
 355                 if (!aphy->tssi2dbm)
 356                         return -ENOMEM;
 357         } else {
 358                 /* pabX values not set in SPROM,
 359                  * but APHY needs a generated table. */
 360                 aphy->tssi2dbm = NULL;
 361                 b43err(dev->wl, "Could not generate tssi2dBm "
 362                        "table (wrong SPROM info)!\n");
 363                 return -ENODEV;
 364         }
 365
 366         return 0;
 367 }
 368
 369 static int b43_aphy_op_allocate(struct b43_wldev *dev)
 370 {
 371         struct b43_phy_a *aphy;
 372         int err;
 373
 374         aphy = kzalloc(sizeof(*aphy), GFP_KERNEL);
 375         if (!aphy)
 376                 return -ENOMEM;
 377         dev->phy.a = aphy;
 378
 379         err = b43_aphy_init_tssi2dbm_table(dev);
 380         if (err)
 381                 goto err_free_aphy;
 382
 383         return 0;
 384
 385 err_free_aphy:
 386         kfree(aphy);
 387         dev->phy.a = NULL;
 388
 389         return err;
 390 }
 391
 392 static void b43_aphy_op_prepare_structs(struct b43_wldev *dev)
 393 {
 394         struct b43_phy *phy = &dev->phy;
 395         struct b43_phy_a *aphy = phy->a;
 396         const void *tssi2dbm;
 397         int tgt_idle_tssi;
 398
 399         /* tssi2dbm table is constant, so it is initialized at alloc time.
 400          * Save a copy of the pointer. */
 401         tssi2dbm = aphy->tssi2dbm;
 402         tgt_idle_tssi = aphy->tgt_idle_tssi;
 403
 404         /* Zero out the whole PHY structure. */
 405         memset(aphy, 0, sizeof(*aphy));
 406
 407         aphy->tssi2dbm = tssi2dbm;
 408         aphy->tgt_idle_tssi = tgt_idle_tssi;
 409
 410         //TODO init struct b43_phy_a
 411
 412 }
 413
 414 static void b43_aphy_op_free(struct b43_wldev *dev)
 415 {
 416         struct b43_phy *phy = &dev->phy;
 417         struct b43_phy_a *aphy = phy->a;
 418
 419         kfree(aphy->tssi2dbm);
 420         aphy->tssi2dbm = NULL;
 421
 422         kfree(aphy);
 423         dev->phy.a = NULL;
 424 }
 425
 426 static int b43_aphy_op_init(struct b43_wldev *dev)
 427 {
 428         b43_phy_inita(dev);
 429
 430         return 0;
 431 }
 432
 433 static inline u16 adjust_phyreg(struct b43_wldev *dev, u16 offset)
 434 {
 435         /* OFDM registers are base-registers for the A-PHY. */
 436         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
 437                 offset &= ~B43_PHYROUTE;
 438                 offset |= B43_PHYROUTE_BASE;
 439         }
 440
 441 #if B43_DEBUG
 442         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
 443                 /* Ext-G registers are only available on G-PHYs */
 444                 b43err(dev->wl, "Invalid EXT-G PHY access at "
 445                        "0x%04X on A-PHY\n", offset);
 446                 dump_stack();
 447         }
 448         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) {
 449                 /* N-BMODE registers are only available on N-PHYs */
 450                 b43err(dev->wl, "Invalid N-BMODE PHY access at "
 451                        "0x%04X on A-PHY\n", offset);
 452                 dump_stack();
 453         }
 454 #endif /* B43_DEBUG */
 455
 456         return offset;
 457 }
 458
 459 static u16 b43_aphy_op_read(struct b43_wldev *dev, u16 reg)
 460 {
 461         reg = adjust_phyreg(dev, reg);
 462         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 463         return b43_read16(dev, B43_MMIO_PHY_DATA);
 464 }
 465
 466 static void b43_aphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 467 {
 468         reg = adjust_phyreg(dev, reg);
 469         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 470         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 471 }
 472
 473 static u16 b43_aphy_op_radio_read(struct b43_wldev *dev, u16 reg)
 474 {
 475         /* Register 1 is a 32-bit register. */
 476         B43_WARN_ON(reg == 1);
 477         /* A-PHY needs 0x40 for read access */
 478         reg |= 0x40;
 479
 480         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 481         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
 482 }
 483
 484 static void b43_aphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
 485 {
 486         /* Register 1 is a 32-bit register. */
 487         B43_WARN_ON(reg == 1);
 488
 489         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 490         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
 491 }
 492
 493 static bool b43_aphy_op_supports_hwpctl(struct b43_wldev *dev)
 494 {
 495         return (dev->phy.rev >= 5);
 496 }
 497
 498 static void b43_aphy_op_software_rfkill(struct b43_wldev *dev,
 499                                         enum rfkill_state state)
 500 {
 501         struct b43_phy *phy = &dev->phy;
 502
 503         if (state == RFKILL_STATE_UNBLOCKED) {
 504                 if (phy->radio_on)
 505                         return;
 506                 b43_radio_write16(dev, 0x0004, 0x00C0);
 507                 b43_radio_write16(dev, 0x0005, 0x0008);
 508                 b43_phy_mask(dev, 0x0010, 0xFFF7);
 509                 b43_phy_mask(dev, 0x0011, 0xFFF7);
 510                 b43_radio_init2060(dev);
 511         } else {
 512                 b43_radio_write16(dev, 0x0004, 0x00FF);
 513                 b43_radio_write16(dev, 0x0005, 0x00FB);
 514                 b43_phy_set(dev, 0x0010, 0x0008);
 515                 b43_phy_set(dev, 0x0011, 0x0008);
 516         }
 517 }
 518
 519 static int b43_aphy_op_switch_channel(struct b43_wldev *dev,
 520                                       unsigned int new_channel)
 521 {
 522         if (new_channel > 200)
 523                 return -EINVAL;
 524         aphy_channel_switch(dev, new_channel);
 525
 526         return 0;
 527 }
 528
 529 static unsigned int b43_aphy_op_get_default_chan(struct b43_wldev *dev)
 530 {
 531         return 36; /* Default to channel 36 */
 532 }
 533
 534 static void b43_aphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
 535 {//TODO
 536         struct b43_phy *phy = &dev->phy;
 537         u64 hf;
 538         u16 tmp;
 539         int autodiv = 0;
 540
 541         if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
 542                 autodiv = 1;
 543
 544         hf = b43_hf_read(dev);
 545         hf &= ~B43_HF_ANTDIVHELP;
 546         b43_hf_write(dev, hf);
 547
 548         tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
 549         tmp &= ~B43_PHY_BBANDCFG_RXANT;
 550         tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
 551             << B43_PHY_BBANDCFG_RXANT_SHIFT;
 552         b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
 553
 554         if (autodiv) {
 555                 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
 556                 if (antenna == B43_ANTENNA_AUTO0)
 557                         tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
 558                 else
 559                         tmp |= B43_PHY_ANTDWELL_AUTODIV1;
 560                 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
 561         }
 562         if (phy->rev < 3) {
 563                 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
 564                 tmp = (tmp & 0xFF00) | 0x24;
 565                 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
 566         } else {
 567                 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
 568                 tmp |= 0x10;
 569                 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
 570                 if (phy->analog == 3) {
 571                         b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
 572                                       0x1D);
 573                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
 574                                       8);
 575                 } else {
 576                         b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
 577                                       0x3A);
 578                         tmp =
 579                             b43_phy_read(dev,
 580                                          B43_PHY_ADIVRELATED);
 581                         tmp = (tmp & 0xFF00) | 8;
 582                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
 583                                       tmp);
 584                 }
 585         }
 586
 587         hf |= B43_HF_ANTDIVHELP;
 588         b43_hf_write(dev, hf);
 589 }
 590
 591 static void b43_aphy_op_adjust_txpower(struct b43_wldev *dev)
 592 {//TODO
 593 }
 594
 595 static enum b43_txpwr_result b43_aphy_op_recalc_txpower(struct b43_wldev *dev,
 596                                                         bool ignore_tssi)
 597 {//TODO
 598         return B43_TXPWR_RES_DONE;
 599 }
 600
 601 static void b43_aphy_op_pwork_15sec(struct b43_wldev *dev)
 602 {//TODO
 603 }
 604
 605 static void b43_aphy_op_pwork_60sec(struct b43_wldev *dev)
 606 {//TODO
 607 }
 608
 609 const struct b43_phy_operations b43_phyops_a = {
 610         .allocate               = b43_aphy_op_allocate,
 611         .free                   = b43_aphy_op_free,
 612         .prepare_structs        = b43_aphy_op_prepare_structs,
 613         .init                   = b43_aphy_op_init,
 614         .phy_read               = b43_aphy_op_read,
 615         .phy_write              = b43_aphy_op_write,
 616         .radio_read             = b43_aphy_op_radio_read,
 617         .radio_write            = b43_aphy_op_radio_write,
 618         .supports_hwpctl        = b43_aphy_op_supports_hwpctl,
 619         .software_rfkill        = b43_aphy_op_software_rfkill,
 620         .switch_analog          = b43_phyop_switch_analog_generic,
 621         .switch_channel         = b43_aphy_op_switch_channel,
 622         .get_default_chan       = b43_aphy_op_get_default_chan,
 623         .set_rx_antenna         = b43_aphy_op_set_rx_antenna,
 624         .recalc_txpower         = b43_aphy_op_recalc_txpower,
 625         .adjust_txpower         = b43_aphy_op_adjust_txpower,
 626         .pwork_15sec            = b43_aphy_op_pwork_15sec,
 627         .pwork_60sec            = b43_aphy_op_pwork_60sec,
 628 };