2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 static u16 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
60 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
61 struct ath_tx_status *ts, int nframes, int nbad,
62 int txok, bool update_rc);
63 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
67 struct ath_atx_tid *tid,
77 static int ath_max_4ms_framelen[4][32] = {
79 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
80 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
81 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
82 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
85 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
86 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
87 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
88 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
91 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
92 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
93 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
94 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
97 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
98 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
99 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
100 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
104 /*********************/
105 /* Aggregation logic */
106 /*********************/
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
110 struct ath_atx_ac *ac = tid->ac;
119 list_add_tail(&tid->list, &ac->tid_q);
125 list_add_tail(&ac->list, &txq->axq_acq);
128 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
130 struct ath_txq *txq = tid->ac->txq;
132 WARN_ON(!tid->paused);
134 spin_lock_bh(&txq->axq_lock);
137 if (skb_queue_empty(&tid->buf_q))
140 ath_tx_queue_tid(txq, tid);
141 ath_txq_schedule(sc, txq);
143 spin_unlock_bh(&txq->axq_lock);
146 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
148 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
149 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
150 sizeof(tx_info->rate_driver_data));
151 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
154 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
156 struct ath_txq *txq = tid->ac->txq;
159 struct list_head bf_head;
160 struct ath_tx_status ts;
161 struct ath_frame_info *fi;
163 INIT_LIST_HEAD(&bf_head);
165 memset(&ts, 0, sizeof(ts));
166 spin_lock_bh(&txq->axq_lock);
168 while ((skb = __skb_dequeue(&tid->buf_q))) {
169 fi = get_frame_info(skb);
172 spin_unlock_bh(&txq->axq_lock);
173 if (bf && fi->retries) {
174 list_add_tail(&bf->list, &bf_head);
175 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
176 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
178 ath_tx_send_normal(sc, txq, NULL, skb);
180 spin_lock_bh(&txq->axq_lock);
183 spin_unlock_bh(&txq->axq_lock);
186 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
191 index = ATH_BA_INDEX(tid->seq_start, seqno);
192 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
194 __clear_bit(cindex, tid->tx_buf);
196 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
197 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
198 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
202 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
207 index = ATH_BA_INDEX(tid->seq_start, seqno);
208 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
209 __set_bit(cindex, tid->tx_buf);
211 if (index >= ((tid->baw_tail - tid->baw_head) &
212 (ATH_TID_MAX_BUFS - 1))) {
213 tid->baw_tail = cindex;
214 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
219 * TODO: For frame(s) that are in the retry state, we will reuse the
220 * sequence number(s) without setting the retry bit. The
221 * alternative is to give up on these and BAR the receiver's window
224 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
225 struct ath_atx_tid *tid)
230 struct list_head bf_head;
231 struct ath_tx_status ts;
232 struct ath_frame_info *fi;
234 memset(&ts, 0, sizeof(ts));
235 INIT_LIST_HEAD(&bf_head);
237 while ((skb = __skb_dequeue(&tid->buf_q))) {
238 fi = get_frame_info(skb);
242 spin_unlock(&txq->axq_lock);
243 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
244 spin_lock(&txq->axq_lock);
248 list_add_tail(&bf->list, &bf_head);
251 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
253 spin_unlock(&txq->axq_lock);
254 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
255 spin_lock(&txq->axq_lock);
258 tid->seq_next = tid->seq_start;
259 tid->baw_tail = tid->baw_head;
262 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
265 struct ath_frame_info *fi = get_frame_info(skb);
266 struct ieee80211_hdr *hdr;
268 TX_STAT_INC(txq->axq_qnum, a_retries);
269 if (fi->retries++ > 0)
272 hdr = (struct ieee80211_hdr *)skb->data;
273 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
276 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
278 struct ath_buf *bf = NULL;
280 spin_lock_bh(&sc->tx.txbuflock);
282 if (unlikely(list_empty(&sc->tx.txbuf))) {
283 spin_unlock_bh(&sc->tx.txbuflock);
287 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
290 spin_unlock_bh(&sc->tx.txbuflock);
295 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
297 spin_lock_bh(&sc->tx.txbuflock);
298 list_add_tail(&bf->list, &sc->tx.txbuf);
299 spin_unlock_bh(&sc->tx.txbuflock);
302 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
306 tbf = ath_tx_get_buffer(sc);
310 ATH_TXBUF_RESET(tbf);
312 tbf->bf_mpdu = bf->bf_mpdu;
313 tbf->bf_buf_addr = bf->bf_buf_addr;
314 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
315 tbf->bf_state = bf->bf_state;
320 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
321 struct ath_tx_status *ts, int txok,
322 int *nframes, int *nbad)
324 struct ath_frame_info *fi;
326 u32 ba[WME_BA_BMP_SIZE >> 5];
333 isaggr = bf_isaggr(bf);
335 seq_st = ts->ts_seqnum;
336 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
340 fi = get_frame_info(bf->bf_mpdu);
341 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
344 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
352 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
353 struct ath_buf *bf, struct list_head *bf_q,
354 struct ath_tx_status *ts, int txok, bool retry)
356 struct ath_node *an = NULL;
358 struct ieee80211_sta *sta;
359 struct ieee80211_hw *hw = sc->hw;
360 struct ieee80211_hdr *hdr;
361 struct ieee80211_tx_info *tx_info;
362 struct ath_atx_tid *tid = NULL;
363 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
364 struct list_head bf_head;
365 struct sk_buff_head bf_pending;
366 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
367 u32 ba[WME_BA_BMP_SIZE >> 5];
368 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
369 bool rc_update = true;
370 struct ieee80211_tx_rate rates[4];
371 struct ath_frame_info *fi;
377 hdr = (struct ieee80211_hdr *)skb->data;
379 tx_info = IEEE80211_SKB_CB(skb);
381 memcpy(rates, tx_info->control.rates, sizeof(rates));
385 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
389 INIT_LIST_HEAD(&bf_head);
391 bf_next = bf->bf_next;
393 bf->bf_state.bf_type |= BUF_XRETRY;
394 if (!bf->bf_stale || bf_next != NULL)
395 list_move_tail(&bf->list, &bf_head);
397 ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false);
398 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
406 an = (struct ath_node *)sta->drv_priv;
407 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
408 tid = ATH_AN_2_TID(an, tidno);
411 * The hardware occasionally sends a tx status for the wrong TID.
412 * In this case, the BA status cannot be considered valid and all
413 * subframes need to be retransmitted
415 if (tidno != ts->tid)
418 isaggr = bf_isaggr(bf);
419 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
421 if (isaggr && txok) {
422 if (ts->ts_flags & ATH9K_TX_BA) {
423 seq_st = ts->ts_seqnum;
424 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
427 * AR5416 can become deaf/mute when BA
428 * issue happens. Chip needs to be reset.
429 * But AP code may have sychronization issues
430 * when perform internal reset in this routine.
431 * Only enable reset in STA mode for now.
433 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
438 __skb_queue_head_init(&bf_pending);
440 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
442 u16 seqno = bf->bf_state.seqno;
444 txfail = txpending = sendbar = 0;
445 bf_next = bf->bf_next;
448 tx_info = IEEE80211_SKB_CB(skb);
449 fi = get_frame_info(skb);
451 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
452 /* transmit completion, subframe is
453 * acked by block ack */
455 } else if (!isaggr && txok) {
456 /* transmit completion */
459 if ((tid->state & AGGR_CLEANUP) || !retry) {
461 * cleanup in progress, just fail
462 * the un-acked sub-frames
465 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
466 if (!(ts->ts_status & ATH9K_TXERR_FILT) ||
468 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
473 bf->bf_state.bf_type |= BUF_XRETRY;
481 * Make sure the last desc is reclaimed if it
482 * not a holding desc.
484 INIT_LIST_HEAD(&bf_head);
485 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
486 bf_next != NULL || !bf_last->bf_stale)
487 list_move_tail(&bf->list, &bf_head);
489 if (!txpending || (tid->state & AGGR_CLEANUP)) {
491 * complete the acked-ones/xretried ones; update
494 spin_lock_bh(&txq->axq_lock);
495 ath_tx_update_baw(sc, tid, seqno);
496 spin_unlock_bh(&txq->axq_lock);
498 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
499 memcpy(tx_info->control.rates, rates, sizeof(rates));
500 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, true);
503 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, false);
506 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
509 /* retry the un-acked ones */
510 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, false);
511 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
512 if (bf->bf_next == NULL && bf_last->bf_stale) {
515 tbf = ath_clone_txbuf(sc, bf_last);
517 * Update tx baw and complete the
518 * frame with failed status if we
522 spin_lock_bh(&txq->axq_lock);
523 ath_tx_update_baw(sc, tid, seqno);
524 spin_unlock_bh(&txq->axq_lock);
526 bf->bf_state.bf_type |=
528 ath_tx_rc_status(sc, bf, ts, nframes,
530 ath_tx_complete_buf(sc, bf, txq,
536 ath9k_hw_cleartxdesc(sc->sc_ah,
541 * Clear descriptor status words for
544 ath9k_hw_cleartxdesc(sc->sc_ah,
550 * Put this buffer to the temporary pending
551 * queue to retain ordering
553 __skb_queue_tail(&bf_pending, skb);
559 /* prepend un-acked frames to the beginning of the pending frame queue */
560 if (!skb_queue_empty(&bf_pending)) {
562 ieee80211_sta_set_tim(sta);
564 spin_lock_bh(&txq->axq_lock);
566 tid->ac->clear_ps_filter = true;
567 skb_queue_splice(&bf_pending, &tid->buf_q);
569 ath_tx_queue_tid(txq, tid);
570 spin_unlock_bh(&txq->axq_lock);
573 if (tid->state & AGGR_CLEANUP) {
574 ath_tx_flush_tid(sc, tid);
576 if (tid->baw_head == tid->baw_tail) {
577 tid->state &= ~AGGR_ADDBA_COMPLETE;
578 tid->state &= ~AGGR_CLEANUP;
585 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
588 static bool ath_lookup_legacy(struct ath_buf *bf)
591 struct ieee80211_tx_info *tx_info;
592 struct ieee80211_tx_rate *rates;
596 tx_info = IEEE80211_SKB_CB(skb);
597 rates = tx_info->control.rates;
599 for (i = 0; i < 4; i++) {
600 if (!rates[i].count || rates[i].idx < 0)
603 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
610 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
611 struct ath_atx_tid *tid)
614 struct ieee80211_tx_info *tx_info;
615 struct ieee80211_tx_rate *rates;
616 u32 max_4ms_framelen, frmlen;
617 u16 aggr_limit, legacy = 0;
621 tx_info = IEEE80211_SKB_CB(skb);
622 rates = tx_info->control.rates;
625 * Find the lowest frame length among the rate series that will have a
626 * 4ms transmit duration.
627 * TODO - TXOP limit needs to be considered.
629 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
631 for (i = 0; i < 4; i++) {
632 if (rates[i].count) {
634 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
639 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
644 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
647 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
648 max_4ms_framelen = min(max_4ms_framelen, frmlen);
653 * limit aggregate size by the minimum rate if rate selected is
654 * not a probe rate, if rate selected is a probe rate then
655 * avoid aggregation of this packet.
657 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
660 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
661 aggr_limit = min((max_4ms_framelen * 3) / 8,
662 (u32)ATH_AMPDU_LIMIT_MAX);
664 aggr_limit = min(max_4ms_framelen,
665 (u32)ATH_AMPDU_LIMIT_MAX);
668 * h/w can accept aggregates up to 16 bit lengths (65535).
669 * The IE, however can hold up to 65536, which shows up here
670 * as zero. Ignore 65536 since we are constrained by hw.
672 if (tid->an->maxampdu)
673 aggr_limit = min(aggr_limit, tid->an->maxampdu);
679 * Returns the number of delimiters to be added to
680 * meet the minimum required mpdudensity.
682 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
683 struct ath_buf *bf, u16 frmlen,
686 #define FIRST_DESC_NDELIMS 60
687 struct sk_buff *skb = bf->bf_mpdu;
688 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
689 u32 nsymbits, nsymbols;
692 int width, streams, half_gi, ndelim, mindelim;
693 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
695 /* Select standard number of delimiters based on frame length alone */
696 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
699 * If encryption enabled, hardware requires some more padding between
701 * TODO - this could be improved to be dependent on the rate.
702 * The hardware can keep up at lower rates, but not higher rates
704 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
705 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
706 ndelim += ATH_AGGR_ENCRYPTDELIM;
709 * Add delimiter when using RTS/CTS with aggregation
710 * and non enterprise AR9003 card
712 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
713 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
714 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
717 * Convert desired mpdu density from microeconds to bytes based
718 * on highest rate in rate series (i.e. first rate) to determine
719 * required minimum length for subframe. Take into account
720 * whether high rate is 20 or 40Mhz and half or full GI.
722 * If there is no mpdu density restriction, no further calculation
726 if (tid->an->mpdudensity == 0)
729 rix = tx_info->control.rates[0].idx;
730 flags = tx_info->control.rates[0].flags;
731 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
732 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
735 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
737 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
742 streams = HT_RC_2_STREAMS(rix);
743 nsymbits = bits_per_symbol[rix % 8][width] * streams;
744 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
746 if (frmlen < minlen) {
747 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
748 ndelim = max(mindelim, ndelim);
754 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
756 struct ath_atx_tid *tid,
757 struct list_head *bf_q,
760 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
761 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
762 int rl = 0, nframes = 0, ndelim, prev_al = 0;
763 u16 aggr_limit = 0, al = 0, bpad = 0,
764 al_delta, h_baw = tid->baw_size / 2;
765 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
766 struct ieee80211_tx_info *tx_info;
767 struct ath_frame_info *fi;
772 skb = skb_peek(&tid->buf_q);
773 fi = get_frame_info(skb);
776 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
781 bf->bf_state.bf_type |= BUF_AMPDU;
782 seqno = bf->bf_state.seqno;
786 /* do not step over block-ack window */
787 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
788 status = ATH_AGGR_BAW_CLOSED;
793 aggr_limit = ath_lookup_rate(sc, bf, tid);
797 /* do not exceed aggregation limit */
798 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
801 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
802 ath_lookup_legacy(bf))) {
803 status = ATH_AGGR_LIMITED;
807 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
808 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
809 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
812 /* do not exceed subframe limit */
813 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
814 status = ATH_AGGR_LIMITED;
818 /* add padding for previous frame to aggregation length */
819 al += bpad + al_delta;
822 * Get the delimiters needed to meet the MPDU
823 * density for this node.
825 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
827 bpad = PADBYTES(al_delta) + (ndelim << 2);
831 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
833 /* link buffers of this frame to the aggregate */
835 ath_tx_addto_baw(sc, tid, seqno);
836 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
838 __skb_unlink(skb, &tid->buf_q);
839 list_add_tail(&bf->list, bf_q);
841 bf_prev->bf_next = bf;
842 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
847 } while (!skb_queue_empty(&tid->buf_q));
855 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
856 struct ath_atx_tid *tid)
859 enum ATH_AGGR_STATUS status;
860 struct ath_frame_info *fi;
861 struct list_head bf_q;
865 if (skb_queue_empty(&tid->buf_q))
868 INIT_LIST_HEAD(&bf_q);
870 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
873 * no frames picked up to be aggregated;
874 * block-ack window is not open.
876 if (list_empty(&bf_q))
879 bf = list_first_entry(&bf_q, struct ath_buf, list);
880 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
882 if (tid->ac->clear_ps_filter) {
883 tid->ac->clear_ps_filter = false;
884 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
887 /* if only one frame, send as non-aggregate */
888 if (bf == bf->bf_lastbf) {
889 fi = get_frame_info(bf->bf_mpdu);
891 bf->bf_state.bf_type &= ~BUF_AGGR;
892 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
893 ath_buf_set_rate(sc, bf, fi->framelen);
894 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
898 /* setup first desc of aggregate */
899 bf->bf_state.bf_type |= BUF_AGGR;
900 ath_buf_set_rate(sc, bf, aggr_len);
901 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
903 /* anchor last desc of aggregate */
904 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
906 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
907 TX_STAT_INC(txq->axq_qnum, a_aggr);
909 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
910 status != ATH_AGGR_BAW_CLOSED);
913 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
916 struct ath_atx_tid *txtid;
919 an = (struct ath_node *)sta->drv_priv;
920 txtid = ATH_AN_2_TID(an, tid);
922 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
925 txtid->state |= AGGR_ADDBA_PROGRESS;
926 txtid->paused = true;
927 *ssn = txtid->seq_start = txtid->seq_next;
929 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
930 txtid->baw_head = txtid->baw_tail = 0;
935 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
937 struct ath_node *an = (struct ath_node *)sta->drv_priv;
938 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
939 struct ath_txq *txq = txtid->ac->txq;
941 if (txtid->state & AGGR_CLEANUP)
944 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
945 txtid->state &= ~AGGR_ADDBA_PROGRESS;
949 spin_lock_bh(&txq->axq_lock);
950 txtid->paused = true;
953 * If frames are still being transmitted for this TID, they will be
954 * cleaned up during tx completion. To prevent race conditions, this
955 * TID can only be reused after all in-progress subframes have been
958 if (txtid->baw_head != txtid->baw_tail)
959 txtid->state |= AGGR_CLEANUP;
961 txtid->state &= ~AGGR_ADDBA_COMPLETE;
962 spin_unlock_bh(&txq->axq_lock);
964 ath_tx_flush_tid(sc, txtid);
967 bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an)
969 struct ath_atx_tid *tid;
970 struct ath_atx_ac *ac;
972 bool buffered = false;
975 for (tidno = 0, tid = &an->tid[tidno];
976 tidno < WME_NUM_TID; tidno++, tid++) {
984 spin_lock_bh(&txq->axq_lock);
986 if (!skb_queue_empty(&tid->buf_q))
990 list_del(&tid->list);
997 spin_unlock_bh(&txq->axq_lock);
1003 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1005 struct ath_atx_tid *tid;
1006 struct ath_atx_ac *ac;
1007 struct ath_txq *txq;
1010 for (tidno = 0, tid = &an->tid[tidno];
1011 tidno < WME_NUM_TID; tidno++, tid++) {
1016 spin_lock_bh(&txq->axq_lock);
1017 ac->clear_ps_filter = true;
1019 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1020 ath_tx_queue_tid(txq, tid);
1021 ath_txq_schedule(sc, txq);
1024 spin_unlock_bh(&txq->axq_lock);
1028 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1030 struct ath_atx_tid *txtid;
1031 struct ath_node *an;
1033 an = (struct ath_node *)sta->drv_priv;
1035 if (sc->sc_flags & SC_OP_TXAGGR) {
1036 txtid = ATH_AN_2_TID(an, tid);
1038 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1039 txtid->state |= AGGR_ADDBA_COMPLETE;
1040 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1041 ath_tx_resume_tid(sc, txtid);
1045 /********************/
1046 /* Queue Management */
1047 /********************/
1049 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1050 struct ath_txq *txq)
1052 struct ath_atx_ac *ac, *ac_tmp;
1053 struct ath_atx_tid *tid, *tid_tmp;
1055 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1056 list_del(&ac->list);
1058 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1059 list_del(&tid->list);
1061 ath_tid_drain(sc, txq, tid);
1066 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1068 struct ath_hw *ah = sc->sc_ah;
1069 struct ath_common *common = ath9k_hw_common(ah);
1070 struct ath9k_tx_queue_info qi;
1071 static const int subtype_txq_to_hwq[] = {
1072 [WME_AC_BE] = ATH_TXQ_AC_BE,
1073 [WME_AC_BK] = ATH_TXQ_AC_BK,
1074 [WME_AC_VI] = ATH_TXQ_AC_VI,
1075 [WME_AC_VO] = ATH_TXQ_AC_VO,
1079 memset(&qi, 0, sizeof(qi));
1080 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1081 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1082 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1083 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1084 qi.tqi_physCompBuf = 0;
1087 * Enable interrupts only for EOL and DESC conditions.
1088 * We mark tx descriptors to receive a DESC interrupt
1089 * when a tx queue gets deep; otherwise waiting for the
1090 * EOL to reap descriptors. Note that this is done to
1091 * reduce interrupt load and this only defers reaping
1092 * descriptors, never transmitting frames. Aside from
1093 * reducing interrupts this also permits more concurrency.
1094 * The only potential downside is if the tx queue backs
1095 * up in which case the top half of the kernel may backup
1096 * due to a lack of tx descriptors.
1098 * The UAPSD queue is an exception, since we take a desc-
1099 * based intr on the EOSP frames.
1101 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1102 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1103 TXQ_FLAG_TXERRINT_ENABLE;
1105 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1106 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1108 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1109 TXQ_FLAG_TXDESCINT_ENABLE;
1111 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1112 if (axq_qnum == -1) {
1114 * NB: don't print a message, this happens
1115 * normally on parts with too few tx queues
1119 if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
1120 ath_err(common, "qnum %u out of range, max %zu!\n",
1121 axq_qnum, ARRAY_SIZE(sc->tx.txq));
1122 ath9k_hw_releasetxqueue(ah, axq_qnum);
1125 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1126 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1128 txq->axq_qnum = axq_qnum;
1129 txq->mac80211_qnum = -1;
1130 txq->axq_link = NULL;
1131 INIT_LIST_HEAD(&txq->axq_q);
1132 INIT_LIST_HEAD(&txq->axq_acq);
1133 spin_lock_init(&txq->axq_lock);
1135 txq->axq_ampdu_depth = 0;
1136 txq->axq_tx_inprogress = false;
1137 sc->tx.txqsetup |= 1<<axq_qnum;
1139 txq->txq_headidx = txq->txq_tailidx = 0;
1140 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1141 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1143 return &sc->tx.txq[axq_qnum];
1146 int ath_txq_update(struct ath_softc *sc, int qnum,
1147 struct ath9k_tx_queue_info *qinfo)
1149 struct ath_hw *ah = sc->sc_ah;
1151 struct ath9k_tx_queue_info qi;
1153 if (qnum == sc->beacon.beaconq) {
1155 * XXX: for beacon queue, we just save the parameter.
1156 * It will be picked up by ath_beaconq_config when
1159 sc->beacon.beacon_qi = *qinfo;
1163 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1165 ath9k_hw_get_txq_props(ah, qnum, &qi);
1166 qi.tqi_aifs = qinfo->tqi_aifs;
1167 qi.tqi_cwmin = qinfo->tqi_cwmin;
1168 qi.tqi_cwmax = qinfo->tqi_cwmax;
1169 qi.tqi_burstTime = qinfo->tqi_burstTime;
1170 qi.tqi_readyTime = qinfo->tqi_readyTime;
1172 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1173 ath_err(ath9k_hw_common(sc->sc_ah),
1174 "Unable to update hardware queue %u!\n", qnum);
1177 ath9k_hw_resettxqueue(ah, qnum);
1183 int ath_cabq_update(struct ath_softc *sc)
1185 struct ath9k_tx_queue_info qi;
1186 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1187 int qnum = sc->beacon.cabq->axq_qnum;
1189 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1191 * Ensure the readytime % is within the bounds.
1193 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1194 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1195 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1196 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1198 qi.tqi_readyTime = (cur_conf->beacon_interval *
1199 sc->config.cabqReadytime) / 100;
1200 ath_txq_update(sc, qnum, &qi);
1205 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1207 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1208 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1211 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1212 struct list_head *list, bool retry_tx)
1213 __releases(txq->axq_lock)
1214 __acquires(txq->axq_lock)
1216 struct ath_buf *bf, *lastbf;
1217 struct list_head bf_head;
1218 struct ath_tx_status ts;
1220 memset(&ts, 0, sizeof(ts));
1221 INIT_LIST_HEAD(&bf_head);
1223 while (!list_empty(list)) {
1224 bf = list_first_entry(list, struct ath_buf, list);
1227 list_del(&bf->list);
1229 ath_tx_return_buffer(sc, bf);
1233 lastbf = bf->bf_lastbf;
1234 list_cut_position(&bf_head, list, &lastbf->list);
1237 if (bf_is_ampdu_not_probing(bf))
1238 txq->axq_ampdu_depth--;
1240 spin_unlock_bh(&txq->axq_lock);
1242 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1245 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1246 spin_lock_bh(&txq->axq_lock);
1251 * Drain a given TX queue (could be Beacon or Data)
1253 * This assumes output has been stopped and
1254 * we do not need to block ath_tx_tasklet.
1256 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1258 spin_lock_bh(&txq->axq_lock);
1259 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1260 int idx = txq->txq_tailidx;
1262 while (!list_empty(&txq->txq_fifo[idx])) {
1263 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1266 INCR(idx, ATH_TXFIFO_DEPTH);
1268 txq->txq_tailidx = idx;
1271 txq->axq_link = NULL;
1272 txq->axq_tx_inprogress = false;
1273 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1275 /* flush any pending frames if aggregation is enabled */
1276 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1277 ath_txq_drain_pending_buffers(sc, txq);
1279 spin_unlock_bh(&txq->axq_lock);
1282 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1284 struct ath_hw *ah = sc->sc_ah;
1285 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1286 struct ath_txq *txq;
1289 if (sc->sc_flags & SC_OP_INVALID)
1292 ath9k_hw_abort_tx_dma(ah);
1294 /* Check if any queue remains active */
1295 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1296 if (!ATH_TXQ_SETUP(sc, i))
1299 npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
1303 ath_err(common, "Failed to stop TX DMA!\n");
1305 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1306 if (!ATH_TXQ_SETUP(sc, i))
1310 * The caller will resume queues with ieee80211_wake_queues.
1311 * Mark the queue as not stopped to prevent ath_tx_complete
1312 * from waking the queue too early.
1314 txq = &sc->tx.txq[i];
1315 txq->stopped = false;
1316 ath_draintxq(sc, txq, retry_tx);
1322 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1324 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1325 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1328 /* For each axq_acq entry, for each tid, try to schedule packets
1329 * for transmit until ampdu_depth has reached min Q depth.
1331 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1333 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1334 struct ath_atx_tid *tid, *last_tid;
1336 if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) ||
1337 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1340 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1341 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1343 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1344 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1345 list_del(&ac->list);
1348 while (!list_empty(&ac->tid_q)) {
1349 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1351 list_del(&tid->list);
1357 ath_tx_sched_aggr(sc, txq, tid);
1360 * add tid to round-robin queue if more frames
1361 * are pending for the tid
1363 if (!skb_queue_empty(&tid->buf_q))
1364 ath_tx_queue_tid(txq, tid);
1366 if (tid == last_tid ||
1367 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1371 if (!list_empty(&ac->tid_q)) {
1374 list_add_tail(&ac->list, &txq->axq_acq);
1378 if (ac == last_ac ||
1379 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1389 * Insert a chain of ath_buf (descriptors) on a txq and
1390 * assume the descriptors are already chained together by caller.
1392 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1393 struct list_head *head, bool internal)
1395 struct ath_hw *ah = sc->sc_ah;
1396 struct ath_common *common = ath9k_hw_common(ah);
1397 struct ath_buf *bf, *bf_last;
1398 bool puttxbuf = false;
1402 * Insert the frame on the outbound list and
1403 * pass it on to the hardware.
1406 if (list_empty(head))
1409 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1410 bf = list_first_entry(head, struct ath_buf, list);
1411 bf_last = list_entry(head->prev, struct ath_buf, list);
1413 ath_dbg(common, ATH_DBG_QUEUE,
1414 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1416 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1417 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1418 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1421 list_splice_tail_init(head, &txq->axq_q);
1423 if (txq->axq_link) {
1424 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1425 ath_dbg(common, ATH_DBG_XMIT,
1426 "link[%u] (%p)=%llx (%p)\n",
1427 txq->axq_qnum, txq->axq_link,
1428 ito64(bf->bf_daddr), bf->bf_desc);
1432 txq->axq_link = bf_last->bf_desc;
1436 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1437 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1438 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1439 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1443 TX_STAT_INC(txq->axq_qnum, txstart);
1444 ath9k_hw_txstart(ah, txq->axq_qnum);
1449 if (bf_is_ampdu_not_probing(bf))
1450 txq->axq_ampdu_depth++;
1454 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1455 struct sk_buff *skb, struct ath_tx_control *txctl)
1457 struct ath_frame_info *fi = get_frame_info(skb);
1458 struct list_head bf_head;
1462 * Do not queue to h/w when any of the following conditions is true:
1463 * - there are pending frames in software queue
1464 * - the TID is currently paused for ADDBA/BAR request
1465 * - seqno is not within block-ack window
1466 * - h/w queue depth exceeds low water mark
1468 if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1469 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1470 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1472 * Add this frame to software queue for scheduling later
1475 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1476 __skb_queue_tail(&tid->buf_q, skb);
1477 if (!txctl->an || !txctl->an->sleeping)
1478 ath_tx_queue_tid(txctl->txq, tid);
1482 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1486 bf->bf_state.bf_type |= BUF_AMPDU;
1487 INIT_LIST_HEAD(&bf_head);
1488 list_add(&bf->list, &bf_head);
1490 /* Add sub-frame to BAW */
1491 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1493 /* Queue to h/w without aggregation */
1494 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1496 ath_buf_set_rate(sc, bf, fi->framelen);
1497 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1500 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1501 struct ath_atx_tid *tid, struct sk_buff *skb)
1503 struct ath_frame_info *fi = get_frame_info(skb);
1504 struct list_head bf_head;
1509 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
1514 INIT_LIST_HEAD(&bf_head);
1515 list_add_tail(&bf->list, &bf_head);
1516 bf->bf_state.bf_type &= ~BUF_AMPDU;
1518 /* update starting sequence number for subsequent ADDBA request */
1520 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1523 ath_buf_set_rate(sc, bf, fi->framelen);
1524 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1525 TX_STAT_INC(txq->axq_qnum, queued);
1528 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1530 struct ieee80211_hdr *hdr;
1531 enum ath9k_pkt_type htype;
1534 hdr = (struct ieee80211_hdr *)skb->data;
1535 fc = hdr->frame_control;
1537 if (ieee80211_is_beacon(fc))
1538 htype = ATH9K_PKT_TYPE_BEACON;
1539 else if (ieee80211_is_probe_resp(fc))
1540 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1541 else if (ieee80211_is_atim(fc))
1542 htype = ATH9K_PKT_TYPE_ATIM;
1543 else if (ieee80211_is_pspoll(fc))
1544 htype = ATH9K_PKT_TYPE_PSPOLL;
1546 htype = ATH9K_PKT_TYPE_NORMAL;
1551 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1554 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1555 struct ieee80211_sta *sta = tx_info->control.sta;
1556 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1557 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1558 struct ath_frame_info *fi = get_frame_info(skb);
1559 struct ath_node *an = NULL;
1560 enum ath9k_key_type keytype;
1562 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1565 an = (struct ath_node *) sta->drv_priv;
1567 memset(fi, 0, sizeof(*fi));
1569 fi->keyix = hw_key->hw_key_idx;
1570 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1571 fi->keyix = an->ps_key;
1573 fi->keyix = ATH9K_TXKEYIX_INVALID;
1574 fi->keytype = keytype;
1575 fi->framelen = framelen;
1578 static int setup_tx_flags(struct sk_buff *skb)
1580 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1583 flags |= ATH9K_TXDESC_INTREQ;
1585 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1586 flags |= ATH9K_TXDESC_NOACK;
1588 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1589 flags |= ATH9K_TXDESC_LDPC;
1596 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1597 * width - 0 for 20 MHz, 1 for 40 MHz
1598 * half_gi - to use 4us v/s 3.6 us for symbol time
1600 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1601 int width, int half_gi, bool shortPreamble)
1603 u32 nbits, nsymbits, duration, nsymbols;
1606 /* find number of symbols: PLCP + data */
1607 streams = HT_RC_2_STREAMS(rix);
1608 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1609 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1610 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1613 duration = SYMBOL_TIME(nsymbols);
1615 duration = SYMBOL_TIME_HALFGI(nsymbols);
1617 /* addup duration for legacy/ht training and signal fields */
1618 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1623 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1625 struct ath_hw *ah = sc->sc_ah;
1626 struct ath9k_channel *curchan = ah->curchan;
1627 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1628 (curchan->channelFlags & CHANNEL_5GHZ) &&
1629 (chainmask == 0x7) && (rate < 0x90))
1635 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1637 struct ath_hw *ah = sc->sc_ah;
1638 struct ath9k_11n_rate_series series[4];
1639 struct sk_buff *skb;
1640 struct ieee80211_tx_info *tx_info;
1641 struct ieee80211_tx_rate *rates;
1642 const struct ieee80211_rate *rate;
1643 struct ieee80211_hdr *hdr;
1645 u8 rix = 0, ctsrate = 0;
1648 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1651 tx_info = IEEE80211_SKB_CB(skb);
1652 rates = tx_info->control.rates;
1653 hdr = (struct ieee80211_hdr *)skb->data;
1654 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1657 * We check if Short Preamble is needed for the CTS rate by
1658 * checking the BSS's global flag.
1659 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1661 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1662 ctsrate = rate->hw_value;
1663 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1664 ctsrate |= rate->hw_value_short;
1666 for (i = 0; i < 4; i++) {
1667 bool is_40, is_sgi, is_sp;
1670 if (!rates[i].count || (rates[i].idx < 0))
1674 series[i].Tries = rates[i].count;
1676 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1677 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1678 flags |= ATH9K_TXDESC_RTSENA;
1679 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1680 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1681 flags |= ATH9K_TXDESC_CTSENA;
1684 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1685 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1686 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1687 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1689 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1690 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1691 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1693 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1695 series[i].Rate = rix | 0x80;
1696 series[i].ChSel = ath_txchainmask_reduction(sc,
1697 ah->txchainmask, series[i].Rate);
1698 series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1699 is_40, is_sgi, is_sp);
1700 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1701 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1706 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1707 !(rate->flags & IEEE80211_RATE_ERP_G))
1708 phy = WLAN_RC_PHY_CCK;
1710 phy = WLAN_RC_PHY_OFDM;
1712 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1713 series[i].Rate = rate->hw_value;
1714 if (rate->hw_value_short) {
1715 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1716 series[i].Rate |= rate->hw_value_short;
1721 if (bf->bf_state.bfs_paprd)
1722 series[i].ChSel = ah->txchainmask;
1724 series[i].ChSel = ath_txchainmask_reduction(sc,
1725 ah->txchainmask, series[i].Rate);
1727 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1728 phy, rate->bitrate * 100, len, rix, is_sp);
1731 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1732 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1733 flags &= ~ATH9K_TXDESC_RTSENA;
1735 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1736 if (flags & ATH9K_TXDESC_RTSENA)
1737 flags &= ~ATH9K_TXDESC_CTSENA;
1739 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1740 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1741 bf->bf_lastbf->bf_desc,
1742 !is_pspoll, ctsrate,
1743 0, series, 4, flags);
1748 * Assign a descriptor (and sequence number if necessary,
1749 * and map buffer for DMA. Frees skb on error
1751 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1752 struct ath_txq *txq,
1753 struct ath_atx_tid *tid,
1754 struct sk_buff *skb)
1756 struct ath_hw *ah = sc->sc_ah;
1757 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1758 struct ath_frame_info *fi = get_frame_info(skb);
1759 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1761 struct ath_desc *ds;
1765 bf = ath_tx_get_buffer(sc);
1767 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1771 ATH_TXBUF_RESET(bf);
1774 seqno = tid->seq_next;
1775 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1776 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1777 bf->bf_state.seqno = seqno;
1780 bf->bf_flags = setup_tx_flags(skb);
1783 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1784 skb->len, DMA_TO_DEVICE);
1785 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1787 bf->bf_buf_addr = 0;
1788 ath_err(ath9k_hw_common(sc->sc_ah),
1789 "dma_mapping_error() on TX\n");
1790 ath_tx_return_buffer(sc, bf);
1794 frm_type = get_hw_packet_type(skb);
1797 ath9k_hw_set_desc_link(ah, ds, 0);
1799 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1800 fi->keyix, fi->keytype, bf->bf_flags);
1802 ath9k_hw_filltxdesc(ah, ds,
1803 skb->len, /* segment length */
1804 true, /* first segment */
1805 true, /* last segment */
1806 ds, /* first descriptor */
1815 dev_kfree_skb_any(skb);
1819 /* FIXME: tx power */
1820 static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
1821 struct ath_tx_control *txctl)
1823 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1824 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1825 struct ath_atx_tid *tid = NULL;
1829 spin_lock_bh(&txctl->txq->axq_lock);
1830 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1831 ieee80211_is_data_qos(hdr->frame_control)) {
1832 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1833 IEEE80211_QOS_CTL_TID_MASK;
1834 tid = ATH_AN_2_TID(txctl->an, tidno);
1836 WARN_ON(tid->ac->txq != txctl->txq);
1839 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1841 * Try aggregation if it's a unicast data frame
1842 * and the destination is HT capable.
1844 ath_tx_send_ampdu(sc, tid, skb, txctl);
1846 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1850 bf->bf_state.bfs_paprd = txctl->paprd;
1852 if (bf->bf_state.bfs_paprd)
1853 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1854 bf->bf_state.bfs_paprd);
1857 bf->bf_state.bfs_paprd_timestamp = jiffies;
1859 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1860 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
1862 ath_tx_send_normal(sc, txctl->txq, tid, skb);
1866 spin_unlock_bh(&txctl->txq->axq_lock);
1869 /* Upon failure caller should free skb */
1870 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1871 struct ath_tx_control *txctl)
1873 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1874 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1875 struct ieee80211_sta *sta = info->control.sta;
1876 struct ieee80211_vif *vif = info->control.vif;
1877 struct ath_softc *sc = hw->priv;
1878 struct ath_txq *txq = txctl->txq;
1879 int padpos, padsize;
1880 int frmlen = skb->len + FCS_LEN;
1883 /* NOTE: sta can be NULL according to net/mac80211.h */
1885 txctl->an = (struct ath_node *)sta->drv_priv;
1887 if (info->control.hw_key)
1888 frmlen += info->control.hw_key->icv_len;
1891 * As a temporary workaround, assign seq# here; this will likely need
1892 * to be cleaned up to work better with Beacon transmission and virtual
1895 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1896 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1897 sc->tx.seq_no += 0x10;
1898 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1899 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1902 /* Add the padding after the header if this is not already done */
1903 padpos = ath9k_cmn_padpos(hdr->frame_control);
1904 padsize = padpos & 3;
1905 if (padsize && skb->len > padpos) {
1906 if (skb_headroom(skb) < padsize)
1909 skb_push(skb, padsize);
1910 memmove(skb->data, skb->data + padsize, padpos);
1913 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1914 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1915 !ieee80211_is_data(hdr->frame_control))
1916 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1918 setup_frame_info(hw, skb, frmlen);
1921 * At this point, the vif, hw_key and sta pointers in the tx control
1922 * info are no longer valid (overwritten by the ath_frame_info data.
1925 q = skb_get_queue_mapping(skb);
1926 spin_lock_bh(&txq->axq_lock);
1927 if (txq == sc->tx.txq_map[q] &&
1928 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1929 ieee80211_stop_queue(sc->hw, q);
1932 spin_unlock_bh(&txq->axq_lock);
1934 ath_tx_start_dma(sc, skb, txctl);
1942 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1943 int tx_flags, struct ath_txq *txq)
1945 struct ieee80211_hw *hw = sc->hw;
1946 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1947 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1948 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1949 int q, padpos, padsize;
1951 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1953 if (tx_flags & ATH_TX_BAR)
1954 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1956 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1957 /* Frame was ACKed */
1958 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1961 padpos = ath9k_cmn_padpos(hdr->frame_control);
1962 padsize = padpos & 3;
1963 if (padsize && skb->len>padpos+padsize) {
1965 * Remove MAC header padding before giving the frame back to
1968 memmove(skb->data + padsize, skb->data, padpos);
1969 skb_pull(skb, padsize);
1972 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1973 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1974 ath_dbg(common, ATH_DBG_PS,
1975 "Going back to sleep after having received TX status (0x%lx)\n",
1976 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1978 PS_WAIT_FOR_PSPOLL_DATA |
1979 PS_WAIT_FOR_TX_ACK));
1982 q = skb_get_queue_mapping(skb);
1983 if (txq == sc->tx.txq_map[q]) {
1984 spin_lock_bh(&txq->axq_lock);
1985 if (WARN_ON(--txq->pending_frames < 0))
1986 txq->pending_frames = 0;
1988 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1989 ieee80211_wake_queue(sc->hw, q);
1992 spin_unlock_bh(&txq->axq_lock);
1995 ieee80211_tx_status(hw, skb);
1998 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1999 struct ath_txq *txq, struct list_head *bf_q,
2000 struct ath_tx_status *ts, int txok, int sendbar)
2002 struct sk_buff *skb = bf->bf_mpdu;
2003 unsigned long flags;
2007 tx_flags = ATH_TX_BAR;
2010 tx_flags |= ATH_TX_ERROR;
2012 if (bf_isxretried(bf))
2013 tx_flags |= ATH_TX_XRETRY;
2016 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2017 bf->bf_buf_addr = 0;
2019 if (bf->bf_state.bfs_paprd) {
2020 if (time_after(jiffies,
2021 bf->bf_state.bfs_paprd_timestamp +
2022 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2023 dev_kfree_skb_any(skb);
2025 complete(&sc->paprd_complete);
2027 ath_debug_stat_tx(sc, bf, ts, txq);
2028 ath_tx_complete(sc, skb, tx_flags, txq);
2030 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2031 * accidentally reference it later.
2036 * Return the list of ath_buf of this mpdu to free queue
2038 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2039 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2040 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2043 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2044 struct ath_tx_status *ts, int nframes, int nbad,
2045 int txok, bool update_rc)
2047 struct sk_buff *skb = bf->bf_mpdu;
2048 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2049 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2050 struct ieee80211_hw *hw = sc->hw;
2051 struct ath_hw *ah = sc->sc_ah;
2055 tx_info->status.ack_signal = ts->ts_rssi;
2057 tx_rateindex = ts->ts_rateindex;
2058 WARN_ON(tx_rateindex >= hw->max_rates);
2060 if (ts->ts_status & ATH9K_TXERR_FILT)
2061 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2062 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
2063 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2065 BUG_ON(nbad > nframes);
2067 tx_info->status.ampdu_len = nframes;
2068 tx_info->status.ampdu_ack_len = nframes - nbad;
2071 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2072 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
2074 * If an underrun error is seen assume it as an excessive
2075 * retry only if max frame trigger level has been reached
2076 * (2 KB for single stream, and 4 KB for dual stream).
2077 * Adjust the long retry as if the frame was tried
2078 * hw->max_rate_tries times to affect how rate control updates
2079 * PER for the failed rate.
2080 * In case of congestion on the bus penalizing this type of
2081 * underruns should help hardware actually transmit new frames
2082 * successfully by eventually preferring slower rates.
2083 * This itself should also alleviate congestion on the bus.
2085 if (ieee80211_is_data(hdr->frame_control) &&
2086 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2087 ATH9K_TX_DELIM_UNDERRUN)) &&
2088 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2089 tx_info->status.rates[tx_rateindex].count =
2093 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2094 tx_info->status.rates[i].count = 0;
2095 tx_info->status.rates[i].idx = -1;
2098 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2101 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2102 struct ath_tx_status *ts, struct ath_buf *bf,
2103 struct list_head *bf_head)
2104 __releases(txq->axq_lock)
2105 __acquires(txq->axq_lock)
2110 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2111 txq->axq_tx_inprogress = false;
2112 if (bf_is_ampdu_not_probing(bf))
2113 txq->axq_ampdu_depth--;
2115 spin_unlock_bh(&txq->axq_lock);
2117 if (!bf_isampdu(bf)) {
2119 * This frame is sent out as a single frame.
2120 * Use hardware retry status for this frame.
2122 if (ts->ts_status & ATH9K_TXERR_XRETRY)
2123 bf->bf_state.bf_type |= BUF_XRETRY;
2124 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok, true);
2125 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2127 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2129 spin_lock_bh(&txq->axq_lock);
2131 if (sc->sc_flags & SC_OP_TXAGGR)
2132 ath_txq_schedule(sc, txq);
2135 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2137 struct ath_hw *ah = sc->sc_ah;
2138 struct ath_common *common = ath9k_hw_common(ah);
2139 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2140 struct list_head bf_head;
2141 struct ath_desc *ds;
2142 struct ath_tx_status ts;
2145 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2146 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2149 spin_lock_bh(&txq->axq_lock);
2151 if (work_pending(&sc->hw_reset_work))
2154 if (list_empty(&txq->axq_q)) {
2155 txq->axq_link = NULL;
2156 if (sc->sc_flags & SC_OP_TXAGGR)
2157 ath_txq_schedule(sc, txq);
2160 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2163 * There is a race condition that a BH gets scheduled
2164 * after sw writes TxE and before hw re-load the last
2165 * descriptor to get the newly chained one.
2166 * Software must keep the last DONE descriptor as a
2167 * holding descriptor - software does so by marking
2168 * it with the STALE flag.
2173 if (list_is_last(&bf_held->list, &txq->axq_q))
2176 bf = list_entry(bf_held->list.next, struct ath_buf,
2180 lastbf = bf->bf_lastbf;
2181 ds = lastbf->bf_desc;
2183 memset(&ts, 0, sizeof(ts));
2184 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2185 if (status == -EINPROGRESS)
2188 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2191 * Remove ath_buf's of the same transmit unit from txq,
2192 * however leave the last descriptor back as the holding
2193 * descriptor for hw.
2195 lastbf->bf_stale = true;
2196 INIT_LIST_HEAD(&bf_head);
2197 if (!list_is_singular(&lastbf->list))
2198 list_cut_position(&bf_head,
2199 &txq->axq_q, lastbf->list.prev);
2202 list_del(&bf_held->list);
2203 ath_tx_return_buffer(sc, bf_held);
2206 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2208 spin_unlock_bh(&txq->axq_lock);
2211 static void ath_tx_complete_poll_work(struct work_struct *work)
2213 struct ath_softc *sc = container_of(work, struct ath_softc,
2214 tx_complete_work.work);
2215 struct ath_txq *txq;
2217 bool needreset = false;
2218 #ifdef CONFIG_ATH9K_DEBUGFS
2219 sc->tx_complete_poll_work_seen++;
2222 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2223 if (ATH_TXQ_SETUP(sc, i)) {
2224 txq = &sc->tx.txq[i];
2225 spin_lock_bh(&txq->axq_lock);
2226 if (txq->axq_depth) {
2227 if (txq->axq_tx_inprogress) {
2229 spin_unlock_bh(&txq->axq_lock);
2232 txq->axq_tx_inprogress = true;
2235 spin_unlock_bh(&txq->axq_lock);
2239 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2240 "tx hung, resetting the chip\n");
2241 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2244 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2245 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2250 void ath_tx_tasklet(struct ath_softc *sc)
2253 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2255 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2257 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2258 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2259 ath_tx_processq(sc, &sc->tx.txq[i]);
2263 void ath_tx_edma_tasklet(struct ath_softc *sc)
2265 struct ath_tx_status ts;
2266 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2267 struct ath_hw *ah = sc->sc_ah;
2268 struct ath_txq *txq;
2269 struct ath_buf *bf, *lastbf;
2270 struct list_head bf_head;
2274 if (work_pending(&sc->hw_reset_work))
2277 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2278 if (status == -EINPROGRESS)
2280 if (status == -EIO) {
2281 ath_dbg(common, ATH_DBG_XMIT,
2282 "Error processing tx status\n");
2286 /* Skip beacon completions */
2287 if (ts.qid == sc->beacon.beaconq)
2290 txq = &sc->tx.txq[ts.qid];
2292 spin_lock_bh(&txq->axq_lock);
2294 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2295 spin_unlock_bh(&txq->axq_lock);
2299 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2300 struct ath_buf, list);
2301 lastbf = bf->bf_lastbf;
2303 INIT_LIST_HEAD(&bf_head);
2304 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2307 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2308 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2310 if (!list_empty(&txq->axq_q)) {
2311 struct list_head bf_q;
2313 INIT_LIST_HEAD(&bf_q);
2314 txq->axq_link = NULL;
2315 list_splice_tail_init(&txq->axq_q, &bf_q);
2316 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2320 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2321 spin_unlock_bh(&txq->axq_lock);
2329 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2331 struct ath_descdma *dd = &sc->txsdma;
2332 u8 txs_len = sc->sc_ah->caps.txs_len;
2334 dd->dd_desc_len = size * txs_len;
2335 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2336 &dd->dd_desc_paddr, GFP_KERNEL);
2343 static int ath_tx_edma_init(struct ath_softc *sc)
2347 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2349 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2350 sc->txsdma.dd_desc_paddr,
2351 ATH_TXSTATUS_RING_SIZE);
2356 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2358 struct ath_descdma *dd = &sc->txsdma;
2360 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2364 int ath_tx_init(struct ath_softc *sc, int nbufs)
2366 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2369 spin_lock_init(&sc->tx.txbuflock);
2371 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2375 "Failed to allocate tx descriptors: %d\n", error);
2379 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2380 "beacon", ATH_BCBUF, 1, 1);
2383 "Failed to allocate beacon descriptors: %d\n", error);
2387 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2389 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2390 error = ath_tx_edma_init(sc);
2402 void ath_tx_cleanup(struct ath_softc *sc)
2404 if (sc->beacon.bdma.dd_desc_len != 0)
2405 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2407 if (sc->tx.txdma.dd_desc_len != 0)
2408 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2410 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2411 ath_tx_edma_cleanup(sc);
2414 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2416 struct ath_atx_tid *tid;
2417 struct ath_atx_ac *ac;
2420 for (tidno = 0, tid = &an->tid[tidno];
2421 tidno < WME_NUM_TID;
2425 tid->seq_start = tid->seq_next = 0;
2426 tid->baw_size = WME_MAX_BA;
2427 tid->baw_head = tid->baw_tail = 0;
2429 tid->paused = false;
2430 tid->state &= ~AGGR_CLEANUP;
2431 __skb_queue_head_init(&tid->buf_q);
2432 acno = TID_TO_WME_AC(tidno);
2433 tid->ac = &an->ac[acno];
2434 tid->state &= ~AGGR_ADDBA_COMPLETE;
2435 tid->state &= ~AGGR_ADDBA_PROGRESS;
2438 for (acno = 0, ac = &an->ac[acno];
2439 acno < WME_NUM_AC; acno++, ac++) {
2441 ac->txq = sc->tx.txq_map[acno];
2442 INIT_LIST_HEAD(&ac->tid_q);
2446 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2448 struct ath_atx_ac *ac;
2449 struct ath_atx_tid *tid;
2450 struct ath_txq *txq;
2453 for (tidno = 0, tid = &an->tid[tidno];
2454 tidno < WME_NUM_TID; tidno++, tid++) {
2459 spin_lock_bh(&txq->axq_lock);
2462 list_del(&tid->list);
2467 list_del(&ac->list);
2468 tid->ac->sched = false;
2471 ath_tid_drain(sc, txq, tid);
2472 tid->state &= ~AGGR_ADDBA_COMPLETE;
2473 tid->state &= ~AGGR_CLEANUP;
2475 spin_unlock_bh(&txq->axq_lock);