2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34 #define OFDM_SIFS_TIME 16
36 static u32 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
58 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
59 struct ath_atx_tid *tid,
60 struct list_head *bf_head);
61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
62 struct list_head *bf_q,
63 int txok, int sendbar);
64 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
65 struct list_head *head);
66 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
67 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
69 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
70 int nbad, int txok, bool update_rc);
72 /*********************/
73 /* Aggregation logic */
74 /*********************/
76 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
78 struct ath_atx_ac *ac = tid->ac;
87 list_add_tail(&tid->list, &ac->tid_q);
93 list_add_tail(&ac->list, &txq->axq_acq);
96 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
98 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
100 spin_lock_bh(&txq->axq_lock);
102 spin_unlock_bh(&txq->axq_lock);
105 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
107 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
109 ASSERT(tid->paused > 0);
110 spin_lock_bh(&txq->axq_lock);
117 if (list_empty(&tid->buf_q))
120 ath_tx_queue_tid(txq, tid);
121 ath_txq_schedule(sc, txq);
123 spin_unlock_bh(&txq->axq_lock);
126 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
128 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
130 struct list_head bf_head;
131 INIT_LIST_HEAD(&bf_head);
133 ASSERT(tid->paused > 0);
134 spin_lock_bh(&txq->axq_lock);
138 if (tid->paused > 0) {
139 spin_unlock_bh(&txq->axq_lock);
143 while (!list_empty(&tid->buf_q)) {
144 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
145 ASSERT(!bf_isretried(bf));
146 list_move_tail(&bf->list, &bf_head);
147 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
150 spin_unlock_bh(&txq->axq_lock);
153 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
158 index = ATH_BA_INDEX(tid->seq_start, seqno);
159 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
161 tid->tx_buf[cindex] = NULL;
163 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
164 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
165 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
169 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
174 if (bf_isretried(bf))
177 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
178 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
180 ASSERT(tid->tx_buf[cindex] == NULL);
181 tid->tx_buf[cindex] = bf;
183 if (index >= ((tid->baw_tail - tid->baw_head) &
184 (ATH_TID_MAX_BUFS - 1))) {
185 tid->baw_tail = cindex;
186 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
191 * TODO: For frame(s) that are in the retry state, we will reuse the
192 * sequence number(s) without setting the retry bit. The
193 * alternative is to give up on these and BAR the receiver's window
196 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
197 struct ath_atx_tid *tid)
201 struct list_head bf_head;
202 INIT_LIST_HEAD(&bf_head);
205 if (list_empty(&tid->buf_q))
208 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
209 list_move_tail(&bf->list, &bf_head);
211 if (bf_isretried(bf))
212 ath_tx_update_baw(sc, tid, bf->bf_seqno);
214 spin_unlock(&txq->axq_lock);
215 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
216 spin_lock(&txq->axq_lock);
219 tid->seq_next = tid->seq_start;
220 tid->baw_tail = tid->baw_head;
223 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
226 struct ieee80211_hdr *hdr;
228 bf->bf_state.bf_type |= BUF_RETRY;
232 hdr = (struct ieee80211_hdr *)skb->data;
233 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
236 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
240 spin_lock_bh(&sc->tx.txbuflock);
241 if (WARN_ON(list_empty(&sc->tx.txbuf))) {
242 spin_unlock_bh(&sc->tx.txbuflock);
245 ASSERT(!list_empty((&sc->tx.txbuf)));
246 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
247 list_del(&tbf->list);
248 spin_unlock_bh(&sc->tx.txbuflock);
250 ATH_TXBUF_RESET(tbf);
252 tbf->bf_mpdu = bf->bf_mpdu;
253 tbf->bf_buf_addr = bf->bf_buf_addr;
254 *(tbf->bf_desc) = *(bf->bf_desc);
255 tbf->bf_state = bf->bf_state;
256 tbf->bf_dmacontext = bf->bf_dmacontext;
261 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
262 struct ath_buf *bf, struct list_head *bf_q,
265 struct ath_node *an = NULL;
267 struct ieee80211_sta *sta;
268 struct ieee80211_hdr *hdr;
269 struct ath_atx_tid *tid = NULL;
270 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
271 struct ath_desc *ds = bf_last->bf_desc;
272 struct list_head bf_head, bf_pending;
273 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
274 u32 ba[WME_BA_BMP_SIZE >> 5];
275 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
276 bool rc_update = true;
279 hdr = (struct ieee80211_hdr *)skb->data;
283 sta = ieee80211_find_sta(sc->hw, hdr->addr1);
289 an = (struct ath_node *)sta->drv_priv;
290 tid = ATH_AN_2_TID(an, bf->bf_tidno);
292 isaggr = bf_isaggr(bf);
293 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
295 if (isaggr && txok) {
296 if (ATH_DS_TX_BA(ds)) {
297 seq_st = ATH_DS_BA_SEQ(ds);
298 memcpy(ba, ATH_DS_BA_BITMAP(ds),
299 WME_BA_BMP_SIZE >> 3);
302 * AR5416 can become deaf/mute when BA
303 * issue happens. Chip needs to be reset.
304 * But AP code may have sychronization issues
305 * when perform internal reset in this routine.
306 * Only enable reset in STA mode for now.
308 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
313 INIT_LIST_HEAD(&bf_pending);
314 INIT_LIST_HEAD(&bf_head);
316 nbad = ath_tx_num_badfrms(sc, bf, txok);
318 txfail = txpending = 0;
319 bf_next = bf->bf_next;
321 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
322 /* transmit completion, subframe is
323 * acked by block ack */
325 } else if (!isaggr && txok) {
326 /* transmit completion */
329 if (!(tid->state & AGGR_CLEANUP) &&
330 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
331 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
332 ath_tx_set_retry(sc, bf);
335 bf->bf_state.bf_type |= BUF_XRETRY;
342 * cleanup in progress, just fail
343 * the un-acked sub-frames
349 if (bf_next == NULL) {
351 * Make sure the last desc is reclaimed if it
352 * not a holding desc.
354 if (!bf_last->bf_stale)
355 list_move_tail(&bf->list, &bf_head);
357 INIT_LIST_HEAD(&bf_head);
359 ASSERT(!list_empty(bf_q));
360 list_move_tail(&bf->list, &bf_head);
365 * complete the acked-ones/xretried ones; update
368 spin_lock_bh(&txq->axq_lock);
369 ath_tx_update_baw(sc, tid, bf->bf_seqno);
370 spin_unlock_bh(&txq->axq_lock);
372 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
373 ath_tx_rc_status(bf, ds, nbad, txok, true);
376 ath_tx_rc_status(bf, ds, nbad, txok, false);
379 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
381 /* retry the un-acked ones */
382 if (bf->bf_next == NULL && bf_last->bf_stale) {
385 tbf = ath_clone_txbuf(sc, bf_last);
388 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
389 list_add_tail(&tbf->list, &bf_head);
392 * Clear descriptor status words for
395 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
399 * Put this buffer to the temporary pending
400 * queue to retain ordering
402 list_splice_tail_init(&bf_head, &bf_pending);
408 if (tid->state & AGGR_CLEANUP) {
409 if (tid->baw_head == tid->baw_tail) {
410 tid->state &= ~AGGR_ADDBA_COMPLETE;
411 tid->state &= ~AGGR_CLEANUP;
413 /* send buffered frames as singles */
414 ath_tx_flush_tid(sc, tid);
420 /* prepend un-acked frames to the beginning of the pending frame queue */
421 if (!list_empty(&bf_pending)) {
422 spin_lock_bh(&txq->axq_lock);
423 list_splice(&bf_pending, &tid->buf_q);
424 ath_tx_queue_tid(txq, tid);
425 spin_unlock_bh(&txq->axq_lock);
431 ath_reset(sc, false);
434 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
435 struct ath_atx_tid *tid)
437 const struct ath_rate_table *rate_table = sc->cur_rate_table;
439 struct ieee80211_tx_info *tx_info;
440 struct ieee80211_tx_rate *rates;
441 struct ath_tx_info_priv *tx_info_priv;
442 u32 max_4ms_framelen, frmlen;
443 u16 aggr_limit, legacy = 0, maxampdu;
447 tx_info = IEEE80211_SKB_CB(skb);
448 rates = tx_info->control.rates;
449 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
452 * Find the lowest frame length among the rate series that will have a
453 * 4ms transmit duration.
454 * TODO - TXOP limit needs to be considered.
456 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
458 for (i = 0; i < 4; i++) {
459 if (rates[i].count) {
460 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
465 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen;
466 max_4ms_framelen = min(max_4ms_framelen, frmlen);
471 * limit aggregate size by the minimum rate if rate selected is
472 * not a probe rate, if rate selected is a probe rate then
473 * avoid aggregation of this packet.
475 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
478 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT);
481 * h/w can accept aggregates upto 16 bit lengths (65535).
482 * The IE, however can hold upto 65536, which shows up here
483 * as zero. Ignore 65536 since we are constrained by hw.
485 maxampdu = tid->an->maxampdu;
487 aggr_limit = min(aggr_limit, maxampdu);
493 * Returns the number of delimiters to be added to
494 * meet the minimum required mpdudensity.
495 * caller should make sure that the rate is HT rate .
497 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
498 struct ath_buf *bf, u16 frmlen)
500 const struct ath_rate_table *rt = sc->cur_rate_table;
501 struct sk_buff *skb = bf->bf_mpdu;
502 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
503 u32 nsymbits, nsymbols, mpdudensity;
506 int width, half_gi, ndelim, mindelim;
508 /* Select standard number of delimiters based on frame length alone */
509 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
512 * If encryption enabled, hardware requires some more padding between
514 * TODO - this could be improved to be dependent on the rate.
515 * The hardware can keep up at lower rates, but not higher rates
517 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
518 ndelim += ATH_AGGR_ENCRYPTDELIM;
521 * Convert desired mpdu density from microeconds to bytes based
522 * on highest rate in rate series (i.e. first rate) to determine
523 * required minimum length for subframe. Take into account
524 * whether high rate is 20 or 40Mhz and half or full GI.
526 mpdudensity = tid->an->mpdudensity;
529 * If there is no mpdu density restriction, no further calculation
532 if (mpdudensity == 0)
535 rix = tx_info->control.rates[0].idx;
536 flags = tx_info->control.rates[0].flags;
537 rc = rt->info[rix].ratecode;
538 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
539 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
542 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
544 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
549 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
550 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
552 if (frmlen < minlen) {
553 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
554 ndelim = max(mindelim, ndelim);
560 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
561 struct ath_atx_tid *tid,
562 struct list_head *bf_q)
564 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
565 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
566 int rl = 0, nframes = 0, ndelim, prev_al = 0;
567 u16 aggr_limit = 0, al = 0, bpad = 0,
568 al_delta, h_baw = tid->baw_size / 2;
569 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
571 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
574 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
576 /* do not step over block-ack window */
577 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
578 status = ATH_AGGR_BAW_CLOSED;
583 aggr_limit = ath_lookup_rate(sc, bf, tid);
587 /* do not exceed aggregation limit */
588 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
591 (aggr_limit < (al + bpad + al_delta + prev_al))) {
592 status = ATH_AGGR_LIMITED;
596 /* do not exceed subframe limit */
597 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
598 status = ATH_AGGR_LIMITED;
603 /* add padding for previous frame to aggregation length */
604 al += bpad + al_delta;
607 * Get the delimiters needed to meet the MPDU
608 * density for this node.
610 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
611 bpad = PADBYTES(al_delta) + (ndelim << 2);
614 bf->bf_desc->ds_link = 0;
616 /* link buffers of this frame to the aggregate */
617 ath_tx_addto_baw(sc, tid, bf);
618 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
619 list_move_tail(&bf->list, bf_q);
621 bf_prev->bf_next = bf;
622 bf_prev->bf_desc->ds_link = bf->bf_daddr;
625 } while (!list_empty(&tid->buf_q));
627 bf_first->bf_al = al;
628 bf_first->bf_nframes = nframes;
634 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
635 struct ath_atx_tid *tid)
638 enum ATH_AGGR_STATUS status;
639 struct list_head bf_q;
642 if (list_empty(&tid->buf_q))
645 INIT_LIST_HEAD(&bf_q);
647 status = ath_tx_form_aggr(sc, tid, &bf_q);
650 * no frames picked up to be aggregated;
651 * block-ack window is not open.
653 if (list_empty(&bf_q))
656 bf = list_first_entry(&bf_q, struct ath_buf, list);
657 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
659 /* if only one frame, send as non-aggregate */
660 if (bf->bf_nframes == 1) {
661 bf->bf_state.bf_type &= ~BUF_AGGR;
662 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
663 ath_buf_set_rate(sc, bf);
664 ath_tx_txqaddbuf(sc, txq, &bf_q);
668 /* setup first desc of aggregate */
669 bf->bf_state.bf_type |= BUF_AGGR;
670 ath_buf_set_rate(sc, bf);
671 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
673 /* anchor last desc of aggregate */
674 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
676 txq->axq_aggr_depth++;
677 ath_tx_txqaddbuf(sc, txq, &bf_q);
679 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
680 status != ATH_AGGR_BAW_CLOSED);
683 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
686 struct ath_atx_tid *txtid;
689 an = (struct ath_node *)sta->drv_priv;
691 if (sc->sc_flags & SC_OP_TXAGGR) {
692 txtid = ATH_AN_2_TID(an, tid);
693 txtid->state |= AGGR_ADDBA_PROGRESS;
694 ath_tx_pause_tid(sc, txtid);
695 *ssn = txtid->seq_start;
701 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
703 struct ath_node *an = (struct ath_node *)sta->drv_priv;
704 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
705 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
707 struct list_head bf_head;
708 INIT_LIST_HEAD(&bf_head);
710 if (txtid->state & AGGR_CLEANUP)
713 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
714 txtid->state &= ~AGGR_ADDBA_PROGRESS;
718 ath_tx_pause_tid(sc, txtid);
720 /* drop all software retried frames and mark this TID */
721 spin_lock_bh(&txq->axq_lock);
722 while (!list_empty(&txtid->buf_q)) {
723 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
724 if (!bf_isretried(bf)) {
726 * NB: it's based on the assumption that
727 * software retried frame will always stay
728 * at the head of software queue.
732 list_move_tail(&bf->list, &bf_head);
733 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
734 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
736 spin_unlock_bh(&txq->axq_lock);
738 if (txtid->baw_head != txtid->baw_tail) {
739 txtid->state |= AGGR_CLEANUP;
741 txtid->state &= ~AGGR_ADDBA_COMPLETE;
742 ath_tx_flush_tid(sc, txtid);
748 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
750 struct ath_atx_tid *txtid;
753 an = (struct ath_node *)sta->drv_priv;
755 if (sc->sc_flags & SC_OP_TXAGGR) {
756 txtid = ATH_AN_2_TID(an, tid);
758 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
759 txtid->state |= AGGR_ADDBA_COMPLETE;
760 txtid->state &= ~AGGR_ADDBA_PROGRESS;
761 ath_tx_resume_tid(sc, txtid);
765 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
767 struct ath_atx_tid *txtid;
769 if (!(sc->sc_flags & SC_OP_TXAGGR))
772 txtid = ATH_AN_2_TID(an, tidno);
774 if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
779 /********************/
780 /* Queue Management */
781 /********************/
783 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
786 struct ath_atx_ac *ac, *ac_tmp;
787 struct ath_atx_tid *tid, *tid_tmp;
789 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
792 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
793 list_del(&tid->list);
795 ath_tid_drain(sc, txq, tid);
800 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
802 struct ath_hw *ah = sc->sc_ah;
803 struct ath9k_tx_queue_info qi;
806 memset(&qi, 0, sizeof(qi));
807 qi.tqi_subtype = subtype;
808 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
809 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
810 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
811 qi.tqi_physCompBuf = 0;
814 * Enable interrupts only for EOL and DESC conditions.
815 * We mark tx descriptors to receive a DESC interrupt
816 * when a tx queue gets deep; otherwise waiting for the
817 * EOL to reap descriptors. Note that this is done to
818 * reduce interrupt load and this only defers reaping
819 * descriptors, never transmitting frames. Aside from
820 * reducing interrupts this also permits more concurrency.
821 * The only potential downside is if the tx queue backs
822 * up in which case the top half of the kernel may backup
823 * due to a lack of tx descriptors.
825 * The UAPSD queue is an exception, since we take a desc-
826 * based intr on the EOSP frames.
828 if (qtype == ATH9K_TX_QUEUE_UAPSD)
829 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
831 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
832 TXQ_FLAG_TXDESCINT_ENABLE;
833 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
836 * NB: don't print a message, this happens
837 * normally on parts with too few tx queues
841 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
842 DPRINTF(sc, ATH_DBG_FATAL,
843 "qnum %u out of range, max %u!\n",
844 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
845 ath9k_hw_releasetxqueue(ah, qnum);
848 if (!ATH_TXQ_SETUP(sc, qnum)) {
849 struct ath_txq *txq = &sc->tx.txq[qnum];
851 txq->axq_qnum = qnum;
852 txq->axq_link = NULL;
853 INIT_LIST_HEAD(&txq->axq_q);
854 INIT_LIST_HEAD(&txq->axq_acq);
855 spin_lock_init(&txq->axq_lock);
857 txq->axq_aggr_depth = 0;
858 txq->axq_totalqueued = 0;
859 txq->axq_linkbuf = NULL;
860 txq->axq_tx_inprogress = false;
861 sc->tx.txqsetup |= 1<<qnum;
863 return &sc->tx.txq[qnum];
866 static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
871 case ATH9K_TX_QUEUE_DATA:
872 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
873 DPRINTF(sc, ATH_DBG_FATAL,
874 "HAL AC %u out of range, max %zu!\n",
875 haltype, ARRAY_SIZE(sc->tx.hwq_map));
878 qnum = sc->tx.hwq_map[haltype];
880 case ATH9K_TX_QUEUE_BEACON:
881 qnum = sc->beacon.beaconq;
883 case ATH9K_TX_QUEUE_CAB:
884 qnum = sc->beacon.cabq->axq_qnum;
892 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
894 struct ath_txq *txq = NULL;
897 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
898 txq = &sc->tx.txq[qnum];
900 spin_lock_bh(&txq->axq_lock);
902 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
903 DPRINTF(sc, ATH_DBG_XMIT,
904 "TX queue: %d is full, depth: %d\n",
905 qnum, txq->axq_depth);
906 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
908 spin_unlock_bh(&txq->axq_lock);
912 spin_unlock_bh(&txq->axq_lock);
917 int ath_txq_update(struct ath_softc *sc, int qnum,
918 struct ath9k_tx_queue_info *qinfo)
920 struct ath_hw *ah = sc->sc_ah;
922 struct ath9k_tx_queue_info qi;
924 if (qnum == sc->beacon.beaconq) {
926 * XXX: for beacon queue, we just save the parameter.
927 * It will be picked up by ath_beaconq_config when
930 sc->beacon.beacon_qi = *qinfo;
934 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum);
936 ath9k_hw_get_txq_props(ah, qnum, &qi);
937 qi.tqi_aifs = qinfo->tqi_aifs;
938 qi.tqi_cwmin = qinfo->tqi_cwmin;
939 qi.tqi_cwmax = qinfo->tqi_cwmax;
940 qi.tqi_burstTime = qinfo->tqi_burstTime;
941 qi.tqi_readyTime = qinfo->tqi_readyTime;
943 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
944 DPRINTF(sc, ATH_DBG_FATAL,
945 "Unable to update hardware queue %u!\n", qnum);
948 ath9k_hw_resettxqueue(ah, qnum);
954 int ath_cabq_update(struct ath_softc *sc)
956 struct ath9k_tx_queue_info qi;
957 int qnum = sc->beacon.cabq->axq_qnum;
959 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
961 * Ensure the readytime % is within the bounds.
963 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
964 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
965 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
966 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
968 qi.tqi_readyTime = (sc->beacon_interval *
969 sc->config.cabqReadytime) / 100;
970 ath_txq_update(sc, qnum, &qi);
976 * Drain a given TX queue (could be Beacon or Data)
978 * This assumes output has been stopped and
979 * we do not need to block ath_tx_tasklet.
981 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
983 struct ath_buf *bf, *lastbf;
984 struct list_head bf_head;
986 INIT_LIST_HEAD(&bf_head);
989 spin_lock_bh(&txq->axq_lock);
991 if (list_empty(&txq->axq_q)) {
992 txq->axq_link = NULL;
993 txq->axq_linkbuf = NULL;
994 spin_unlock_bh(&txq->axq_lock);
998 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1001 list_del(&bf->list);
1002 spin_unlock_bh(&txq->axq_lock);
1004 spin_lock_bh(&sc->tx.txbuflock);
1005 list_add_tail(&bf->list, &sc->tx.txbuf);
1006 spin_unlock_bh(&sc->tx.txbuflock);
1010 lastbf = bf->bf_lastbf;
1012 lastbf->bf_desc->ds_txstat.ts_flags =
1013 ATH9K_TX_SW_ABORTED;
1015 /* remove ath_buf's of the same mpdu from txq */
1016 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1019 spin_unlock_bh(&txq->axq_lock);
1022 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0);
1024 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1027 spin_lock_bh(&txq->axq_lock);
1028 txq->axq_tx_inprogress = false;
1029 spin_unlock_bh(&txq->axq_lock);
1031 /* flush any pending frames if aggregation is enabled */
1032 if (sc->sc_flags & SC_OP_TXAGGR) {
1034 spin_lock_bh(&txq->axq_lock);
1035 ath_txq_drain_pending_buffers(sc, txq);
1036 spin_unlock_bh(&txq->axq_lock);
1041 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1043 struct ath_hw *ah = sc->sc_ah;
1044 struct ath_txq *txq;
1047 if (sc->sc_flags & SC_OP_INVALID)
1050 /* Stop beacon queue */
1051 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1053 /* Stop data queues */
1054 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1055 if (ATH_TXQ_SETUP(sc, i)) {
1056 txq = &sc->tx.txq[i];
1057 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1058 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1065 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1067 spin_lock_bh(&sc->sc_resetlock);
1068 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1070 DPRINTF(sc, ATH_DBG_FATAL,
1071 "Unable to reset hardware; reset status %d\n",
1073 spin_unlock_bh(&sc->sc_resetlock);
1076 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1077 if (ATH_TXQ_SETUP(sc, i))
1078 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1082 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1084 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1085 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1088 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1090 struct ath_atx_ac *ac;
1091 struct ath_atx_tid *tid;
1093 if (list_empty(&txq->axq_acq))
1096 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1097 list_del(&ac->list);
1101 if (list_empty(&ac->tid_q))
1104 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1105 list_del(&tid->list);
1111 ath_tx_sched_aggr(sc, txq, tid);
1114 * add tid to round-robin queue if more frames
1115 * are pending for the tid
1117 if (!list_empty(&tid->buf_q))
1118 ath_tx_queue_tid(txq, tid);
1121 } while (!list_empty(&ac->tid_q));
1123 if (!list_empty(&ac->tid_q)) {
1126 list_add_tail(&ac->list, &txq->axq_acq);
1131 int ath_tx_setup(struct ath_softc *sc, int haltype)
1133 struct ath_txq *txq;
1135 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1136 DPRINTF(sc, ATH_DBG_FATAL,
1137 "HAL AC %u out of range, max %zu!\n",
1138 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1141 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1143 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1154 * Insert a chain of ath_buf (descriptors) on a txq and
1155 * assume the descriptors are already chained together by caller.
1157 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1158 struct list_head *head)
1160 struct ath_hw *ah = sc->sc_ah;
1164 * Insert the frame on the outbound list and
1165 * pass it on to the hardware.
1168 if (list_empty(head))
1171 bf = list_first_entry(head, struct ath_buf, list);
1173 list_splice_tail_init(head, &txq->axq_q);
1175 txq->axq_totalqueued++;
1176 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1178 DPRINTF(sc, ATH_DBG_QUEUE,
1179 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1181 if (txq->axq_link == NULL) {
1182 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1183 DPRINTF(sc, ATH_DBG_XMIT,
1184 "TXDP[%u] = %llx (%p)\n",
1185 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1187 *txq->axq_link = bf->bf_daddr;
1188 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1189 txq->axq_qnum, txq->axq_link,
1190 ito64(bf->bf_daddr), bf->bf_desc);
1192 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1193 ath9k_hw_txstart(ah, txq->axq_qnum);
1196 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1198 struct ath_buf *bf = NULL;
1200 spin_lock_bh(&sc->tx.txbuflock);
1202 if (unlikely(list_empty(&sc->tx.txbuf))) {
1203 spin_unlock_bh(&sc->tx.txbuflock);
1207 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1208 list_del(&bf->list);
1210 spin_unlock_bh(&sc->tx.txbuflock);
1215 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1216 struct list_head *bf_head,
1217 struct ath_tx_control *txctl)
1221 bf = list_first_entry(bf_head, struct ath_buf, list);
1222 bf->bf_state.bf_type |= BUF_AMPDU;
1225 * Do not queue to h/w when any of the following conditions is true:
1226 * - there are pending frames in software queue
1227 * - the TID is currently paused for ADDBA/BAR request
1228 * - seqno is not within block-ack window
1229 * - h/w queue depth exceeds low water mark
1231 if (!list_empty(&tid->buf_q) || tid->paused ||
1232 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1233 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1235 * Add this frame to software queue for scheduling later
1238 list_move_tail(&bf->list, &tid->buf_q);
1239 ath_tx_queue_tid(txctl->txq, tid);
1243 /* Add sub-frame to BAW */
1244 ath_tx_addto_baw(sc, tid, bf);
1246 /* Queue to h/w without aggregation */
1249 ath_buf_set_rate(sc, bf);
1250 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1253 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
1254 struct ath_atx_tid *tid,
1255 struct list_head *bf_head)
1259 bf = list_first_entry(bf_head, struct ath_buf, list);
1260 bf->bf_state.bf_type &= ~BUF_AMPDU;
1262 /* update starting sequence number for subsequent ADDBA request */
1263 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1267 ath_buf_set_rate(sc, bf);
1268 ath_tx_txqaddbuf(sc, txq, bf_head);
1271 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1272 struct list_head *bf_head)
1276 bf = list_first_entry(bf_head, struct ath_buf, list);
1280 ath_buf_set_rate(sc, bf);
1281 ath_tx_txqaddbuf(sc, txq, bf_head);
1284 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1286 struct ieee80211_hdr *hdr;
1287 enum ath9k_pkt_type htype;
1290 hdr = (struct ieee80211_hdr *)skb->data;
1291 fc = hdr->frame_control;
1293 if (ieee80211_is_beacon(fc))
1294 htype = ATH9K_PKT_TYPE_BEACON;
1295 else if (ieee80211_is_probe_resp(fc))
1296 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1297 else if (ieee80211_is_atim(fc))
1298 htype = ATH9K_PKT_TYPE_ATIM;
1299 else if (ieee80211_is_pspoll(fc))
1300 htype = ATH9K_PKT_TYPE_PSPOLL;
1302 htype = ATH9K_PKT_TYPE_NORMAL;
1307 static bool is_pae(struct sk_buff *skb)
1309 struct ieee80211_hdr *hdr;
1312 hdr = (struct ieee80211_hdr *)skb->data;
1313 fc = hdr->frame_control;
1315 if (ieee80211_is_data(fc)) {
1316 if (ieee80211_is_nullfunc(fc) ||
1317 /* Port Access Entity (IEEE 802.1X) */
1318 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1326 static int get_hw_crypto_keytype(struct sk_buff *skb)
1328 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1330 if (tx_info->control.hw_key) {
1331 if (tx_info->control.hw_key->alg == ALG_WEP)
1332 return ATH9K_KEY_TYPE_WEP;
1333 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1334 return ATH9K_KEY_TYPE_TKIP;
1335 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1336 return ATH9K_KEY_TYPE_AES;
1339 return ATH9K_KEY_TYPE_CLEAR;
1342 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1345 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1346 struct ieee80211_hdr *hdr;
1347 struct ath_node *an;
1348 struct ath_atx_tid *tid;
1352 if (!tx_info->control.sta)
1355 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1356 hdr = (struct ieee80211_hdr *)skb->data;
1357 fc = hdr->frame_control;
1359 if (ieee80211_is_data_qos(fc)) {
1360 qc = ieee80211_get_qos_ctl(hdr);
1361 bf->bf_tidno = qc[0] & 0xf;
1365 * For HT capable stations, we save tidno for later use.
1366 * We also override seqno set by upper layer with the one
1367 * in tx aggregation state.
1369 * If fragmentation is on, the sequence number is
1370 * not overridden, since it has been
1371 * incremented by the fragmentation routine.
1373 * FIXME: check if the fragmentation threshold exceeds
1376 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1377 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
1378 IEEE80211_SEQ_SEQ_SHIFT);
1379 bf->bf_seqno = tid->seq_next;
1380 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1383 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1384 struct ath_txq *txq)
1386 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1389 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1390 flags |= ATH9K_TXDESC_INTREQ;
1392 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1393 flags |= ATH9K_TXDESC_NOACK;
1400 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1401 * width - 0 for 20 MHz, 1 for 40 MHz
1402 * half_gi - to use 4us v/s 3.6 us for symbol time
1404 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1405 int width, int half_gi, bool shortPreamble)
1407 const struct ath_rate_table *rate_table = sc->cur_rate_table;
1408 u32 nbits, nsymbits, duration, nsymbols;
1410 int streams, pktlen;
1412 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1413 rc = rate_table->info[rix].ratecode;
1415 /* for legacy rates, use old function to compute packet duration */
1416 if (!IS_HT_RATE(rc))
1417 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
1418 rix, shortPreamble);
1420 /* find number of symbols: PLCP + data */
1421 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1422 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1423 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1426 duration = SYMBOL_TIME(nsymbols);
1428 duration = SYMBOL_TIME_HALFGI(nsymbols);
1430 /* addup duration for legacy/ht training and signal fields */
1431 streams = HT_RC_2_STREAMS(rc);
1432 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1437 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1439 const struct ath_rate_table *rt = sc->cur_rate_table;
1440 struct ath9k_11n_rate_series series[4];
1441 struct sk_buff *skb;
1442 struct ieee80211_tx_info *tx_info;
1443 struct ieee80211_tx_rate *rates;
1444 struct ieee80211_hdr *hdr;
1446 u8 rix = 0, ctsrate = 0;
1449 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1452 tx_info = IEEE80211_SKB_CB(skb);
1453 rates = tx_info->control.rates;
1454 hdr = (struct ieee80211_hdr *)skb->data;
1455 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1458 * We check if Short Preamble is needed for the CTS rate by
1459 * checking the BSS's global flag.
1460 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1462 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1463 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode |
1464 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble;
1466 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode;
1469 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1470 * Check the first rate in the series to decide whether RTS/CTS
1471 * or CTS-to-self has to be used.
1473 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1474 flags = ATH9K_TXDESC_CTSENA;
1475 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1476 flags = ATH9K_TXDESC_RTSENA;
1478 /* FIXME: Handle aggregation protection */
1479 if (sc->config.ath_aggr_prot &&
1480 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
1481 flags = ATH9K_TXDESC_RTSENA;
1484 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1485 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1486 flags &= ~(ATH9K_TXDESC_RTSENA);
1488 for (i = 0; i < 4; i++) {
1489 if (!rates[i].count || (rates[i].idx < 0))
1493 series[i].Tries = rates[i].count;
1494 series[i].ChSel = sc->tx_chainmask;
1496 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1497 series[i].Rate = rt->info[rix].ratecode |
1498 rt->info[rix].short_preamble;
1500 series[i].Rate = rt->info[rix].ratecode;
1502 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1503 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1504 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1505 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1506 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1507 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1509 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1510 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
1511 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
1512 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE));
1515 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1516 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1517 bf->bf_lastbf->bf_desc,
1518 !is_pspoll, ctsrate,
1519 0, series, 4, flags);
1521 if (sc->config.ath_aggr_prot && flags)
1522 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1525 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1526 struct sk_buff *skb,
1527 struct ath_tx_control *txctl)
1529 struct ath_wiphy *aphy = hw->priv;
1530 struct ath_softc *sc = aphy->sc;
1531 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1532 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1533 struct ath_tx_info_priv *tx_info_priv;
1537 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
1538 if (unlikely(!tx_info_priv))
1540 tx_info->rate_driver_data[0] = tx_info_priv;
1541 tx_info_priv->aphy = aphy;
1542 tx_info_priv->frame_type = txctl->frame_type;
1543 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1544 fc = hdr->frame_control;
1546 ATH_TXBUF_RESET(bf);
1548 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1550 if (conf_is_ht(&sc->hw->conf) && !is_pae(skb))
1551 bf->bf_state.bf_type |= BUF_HT;
1553 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1555 bf->bf_keytype = get_hw_crypto_keytype(skb);
1556 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1557 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1558 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1560 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1563 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR))
1564 assign_aggr_tid_seqno(skb, bf);
1568 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1569 skb->len, DMA_TO_DEVICE);
1570 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1572 kfree(tx_info_priv);
1573 tx_info->rate_driver_data[0] = NULL;
1574 DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error() on TX\n");
1578 bf->bf_buf_addr = bf->bf_dmacontext;
1582 /* FIXME: tx power */
1583 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1584 struct ath_tx_control *txctl)
1586 struct sk_buff *skb = bf->bf_mpdu;
1587 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1588 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1589 struct ath_node *an = NULL;
1590 struct list_head bf_head;
1591 struct ath_desc *ds;
1592 struct ath_atx_tid *tid;
1593 struct ath_hw *ah = sc->sc_ah;
1597 frm_type = get_hw_packet_type(skb);
1598 fc = hdr->frame_control;
1600 INIT_LIST_HEAD(&bf_head);
1601 list_add_tail(&bf->list, &bf_head);
1605 ds->ds_data = bf->bf_buf_addr;
1607 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1608 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1610 ath9k_hw_filltxdesc(ah, ds,
1611 skb->len, /* segment length */
1612 true, /* first segment */
1613 true, /* last segment */
1614 ds); /* first descriptor */
1616 spin_lock_bh(&txctl->txq->axq_lock);
1618 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1619 tx_info->control.sta) {
1620 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1621 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1623 if (!ieee80211_is_data_qos(fc)) {
1624 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1628 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1630 * Try aggregation if it's a unicast data frame
1631 * and the destination is HT capable.
1633 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1636 * Send this frame as regular when ADDBA
1637 * exchange is neither complete nor pending.
1639 ath_tx_send_ht_normal(sc, txctl->txq,
1643 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1647 spin_unlock_bh(&txctl->txq->axq_lock);
1650 /* Upon failure caller should free skb */
1651 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1652 struct ath_tx_control *txctl)
1654 struct ath_wiphy *aphy = hw->priv;
1655 struct ath_softc *sc = aphy->sc;
1659 bf = ath_tx_get_buffer(sc);
1661 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n");
1665 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1667 struct ath_txq *txq = txctl->txq;
1669 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n");
1671 /* upon ath_tx_processq() this TX queue will be resumed, we
1672 * guarantee this will happen by knowing beforehand that
1673 * we will at least have to run TX completionon one buffer
1675 spin_lock_bh(&txq->axq_lock);
1676 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1677 ieee80211_stop_queue(sc->hw,
1678 skb_get_queue_mapping(skb));
1681 spin_unlock_bh(&txq->axq_lock);
1683 spin_lock_bh(&sc->tx.txbuflock);
1684 list_add_tail(&bf->list, &sc->tx.txbuf);
1685 spin_unlock_bh(&sc->tx.txbuflock);
1690 ath_tx_start_dma(sc, bf, txctl);
1695 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1697 struct ath_wiphy *aphy = hw->priv;
1698 struct ath_softc *sc = aphy->sc;
1699 int hdrlen, padsize;
1700 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1701 struct ath_tx_control txctl;
1703 memset(&txctl, 0, sizeof(struct ath_tx_control));
1706 * As a temporary workaround, assign seq# here; this will likely need
1707 * to be cleaned up to work better with Beacon transmission and virtual
1710 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1711 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1712 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1713 sc->tx.seq_no += 0x10;
1714 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1715 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1718 /* Add the padding after the header if this is not already done */
1719 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1721 padsize = hdrlen % 4;
1722 if (skb_headroom(skb) < padsize) {
1723 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n");
1724 dev_kfree_skb_any(skb);
1727 skb_push(skb, padsize);
1728 memmove(skb->data, skb->data + padsize, hdrlen);
1731 txctl.txq = sc->beacon.cabq;
1733 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
1735 if (ath_tx_start(hw, skb, &txctl) != 0) {
1736 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n");
1742 dev_kfree_skb_any(skb);
1749 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1752 struct ieee80211_hw *hw = sc->hw;
1753 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1754 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1755 int hdrlen, padsize;
1756 int frame_type = ATH9K_NOT_INTERNAL;
1758 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1761 hw = tx_info_priv->aphy->hw;
1762 frame_type = tx_info_priv->frame_type;
1765 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
1766 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
1767 kfree(tx_info_priv);
1768 tx_info->rate_driver_data[0] = NULL;
1771 if (tx_flags & ATH_TX_BAR)
1772 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1774 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1775 /* Frame was ACKed */
1776 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1779 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1780 padsize = hdrlen & 3;
1781 if (padsize && hdrlen >= 24) {
1783 * Remove MAC header padding before giving the frame back to
1786 memmove(skb->data + padsize, skb->data, hdrlen);
1787 skb_pull(skb, padsize);
1790 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) {
1791 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK;
1792 DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having "
1793 "received TX status (0x%x)\n",
1794 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
1795 SC_OP_WAIT_FOR_CAB |
1796 SC_OP_WAIT_FOR_PSPOLL_DATA |
1797 SC_OP_WAIT_FOR_TX_ACK));
1800 if (frame_type == ATH9K_NOT_INTERNAL)
1801 ieee80211_tx_status(hw, skb);
1803 ath9k_tx_status(hw, skb);
1806 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1807 struct list_head *bf_q,
1808 int txok, int sendbar)
1810 struct sk_buff *skb = bf->bf_mpdu;
1811 unsigned long flags;
1816 tx_flags = ATH_TX_BAR;
1819 tx_flags |= ATH_TX_ERROR;
1821 if (bf_isxretried(bf))
1822 tx_flags |= ATH_TX_XRETRY;
1825 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1826 ath_tx_complete(sc, skb, tx_flags);
1829 * Return the list of ath_buf of this mpdu to free queue
1831 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1832 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1833 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1836 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1839 struct ath_buf *bf_last = bf->bf_lastbf;
1840 struct ath_desc *ds = bf_last->bf_desc;
1842 u32 ba[WME_BA_BMP_SIZE >> 5];
1847 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
1850 isaggr = bf_isaggr(bf);
1852 seq_st = ATH_DS_BA_SEQ(ds);
1853 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
1857 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1858 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1867 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1868 int nbad, int txok, bool update_rc)
1870 struct sk_buff *skb = bf->bf_mpdu;
1871 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1872 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1873 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1874 struct ieee80211_hw *hw = tx_info_priv->aphy->hw;
1878 tx_info->status.ack_signal = ds->ds_txstat.ts_rssi;
1880 tx_rateindex = ds->ds_txstat.ts_rateindex;
1881 WARN_ON(tx_rateindex >= hw->max_rates);
1883 tx_info_priv->update_rc = update_rc;
1884 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1885 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1887 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1888 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1889 if (ieee80211_is_data(hdr->frame_control)) {
1890 memcpy(&tx_info_priv->tx, &ds->ds_txstat,
1891 sizeof(tx_info_priv->tx));
1892 tx_info_priv->n_frames = bf->bf_nframes;
1893 tx_info_priv->n_bad_frames = nbad;
1897 for (i = tx_rateindex + 1; i < hw->max_rates; i++)
1898 tx_info->status.rates[i].count = 0;
1900 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
1903 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1907 spin_lock_bh(&txq->axq_lock);
1909 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1910 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1912 ieee80211_wake_queue(sc->hw, qnum);
1916 spin_unlock_bh(&txq->axq_lock);
1919 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1921 struct ath_hw *ah = sc->sc_ah;
1922 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1923 struct list_head bf_head;
1924 struct ath_desc *ds;
1928 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1929 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1933 spin_lock_bh(&txq->axq_lock);
1934 if (list_empty(&txq->axq_q)) {
1935 txq->axq_link = NULL;
1936 txq->axq_linkbuf = NULL;
1937 spin_unlock_bh(&txq->axq_lock);
1940 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1943 * There is a race condition that a BH gets scheduled
1944 * after sw writes TxE and before hw re-load the last
1945 * descriptor to get the newly chained one.
1946 * Software must keep the last DONE descriptor as a
1947 * holding descriptor - software does so by marking
1948 * it with the STALE flag.
1953 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1954 spin_unlock_bh(&txq->axq_lock);
1957 bf = list_entry(bf_held->list.next,
1958 struct ath_buf, list);
1962 lastbf = bf->bf_lastbf;
1963 ds = lastbf->bf_desc;
1965 status = ath9k_hw_txprocdesc(ah, ds);
1966 if (status == -EINPROGRESS) {
1967 spin_unlock_bh(&txq->axq_lock);
1970 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1971 txq->axq_lastdsWithCTS = NULL;
1972 if (ds == txq->axq_gatingds)
1973 txq->axq_gatingds = NULL;
1976 * Remove ath_buf's of the same transmit unit from txq,
1977 * however leave the last descriptor back as the holding
1978 * descriptor for hw.
1980 lastbf->bf_stale = true;
1981 INIT_LIST_HEAD(&bf_head);
1982 if (!list_is_singular(&lastbf->list))
1983 list_cut_position(&bf_head,
1984 &txq->axq_q, lastbf->list.prev);
1988 txq->axq_aggr_depth--;
1990 txok = (ds->ds_txstat.ts_status == 0);
1991 txq->axq_tx_inprogress = false;
1992 spin_unlock_bh(&txq->axq_lock);
1995 spin_lock_bh(&sc->tx.txbuflock);
1996 list_move_tail(&bf_held->list, &sc->tx.txbuf);
1997 spin_unlock_bh(&sc->tx.txbuflock);
2000 if (!bf_isampdu(bf)) {
2002 * This frame is sent out as a single frame.
2003 * Use hardware retry status for this frame.
2005 bf->bf_retries = ds->ds_txstat.ts_longretry;
2006 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
2007 bf->bf_state.bf_type |= BUF_XRETRY;
2008 ath_tx_rc_status(bf, ds, 0, txok, true);
2012 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
2014 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
2016 ath_wake_mac80211_queue(sc, txq);
2018 spin_lock_bh(&txq->axq_lock);
2019 if (sc->sc_flags & SC_OP_TXAGGR)
2020 ath_txq_schedule(sc, txq);
2021 spin_unlock_bh(&txq->axq_lock);
2025 void ath_tx_complete_poll_work(struct work_struct *work)
2027 struct ath_softc *sc = container_of(work, struct ath_softc,
2028 tx_complete_work.work);
2029 struct ath_txq *txq;
2031 bool needreset = false;
2033 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2034 if (ATH_TXQ_SETUP(sc, i)) {
2035 txq = &sc->tx.txq[i];
2036 spin_lock_bh(&txq->axq_lock);
2037 if (txq->axq_depth) {
2038 if (txq->axq_tx_inprogress) {
2040 spin_unlock_bh(&txq->axq_lock);
2043 txq->axq_tx_inprogress = true;
2046 spin_unlock_bh(&txq->axq_lock);
2050 DPRINTF(sc, ATH_DBG_RESET, "tx hung, resetting the chip\n");
2051 ath_reset(sc, false);
2054 queue_delayed_work(sc->hw->workqueue, &sc->tx_complete_work,
2055 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2060 void ath_tx_tasklet(struct ath_softc *sc)
2063 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2065 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2067 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2068 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2069 ath_tx_processq(sc, &sc->tx.txq[i]);
2077 int ath_tx_init(struct ath_softc *sc, int nbufs)
2081 spin_lock_init(&sc->tx.txbuflock);
2083 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2086 DPRINTF(sc, ATH_DBG_FATAL,
2087 "Failed to allocate tx descriptors: %d\n", error);
2091 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2092 "beacon", ATH_BCBUF, 1);
2094 DPRINTF(sc, ATH_DBG_FATAL,
2095 "Failed to allocate beacon descriptors: %d\n", error);
2099 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2108 void ath_tx_cleanup(struct ath_softc *sc)
2110 if (sc->beacon.bdma.dd_desc_len != 0)
2111 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2113 if (sc->tx.txdma.dd_desc_len != 0)
2114 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2117 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2119 struct ath_atx_tid *tid;
2120 struct ath_atx_ac *ac;
2123 for (tidno = 0, tid = &an->tid[tidno];
2124 tidno < WME_NUM_TID;
2128 tid->seq_start = tid->seq_next = 0;
2129 tid->baw_size = WME_MAX_BA;
2130 tid->baw_head = tid->baw_tail = 0;
2132 tid->paused = false;
2133 tid->state &= ~AGGR_CLEANUP;
2134 INIT_LIST_HEAD(&tid->buf_q);
2135 acno = TID_TO_WME_AC(tidno);
2136 tid->ac = &an->ac[acno];
2137 tid->state &= ~AGGR_ADDBA_COMPLETE;
2138 tid->state &= ~AGGR_ADDBA_PROGRESS;
2141 for (acno = 0, ac = &an->ac[acno];
2142 acno < WME_NUM_AC; acno++, ac++) {
2144 INIT_LIST_HEAD(&ac->tid_q);
2148 ac->qnum = ath_tx_get_qnum(sc,
2149 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2152 ac->qnum = ath_tx_get_qnum(sc,
2153 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2156 ac->qnum = ath_tx_get_qnum(sc,
2157 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2160 ac->qnum = ath_tx_get_qnum(sc,
2161 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2167 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2170 struct ath_atx_ac *ac, *ac_tmp;
2171 struct ath_atx_tid *tid, *tid_tmp;
2172 struct ath_txq *txq;
2174 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2175 if (ATH_TXQ_SETUP(sc, i)) {
2176 txq = &sc->tx.txq[i];
2178 spin_lock(&txq->axq_lock);
2180 list_for_each_entry_safe(ac,
2181 ac_tmp, &txq->axq_acq, list) {
2182 tid = list_first_entry(&ac->tid_q,
2183 struct ath_atx_tid, list);
2184 if (tid && tid->an != an)
2186 list_del(&ac->list);
2189 list_for_each_entry_safe(tid,
2190 tid_tmp, &ac->tid_q, list) {
2191 list_del(&tid->list);
2193 ath_tid_drain(sc, txq, tid);
2194 tid->state &= ~AGGR_ADDBA_COMPLETE;
2195 tid->state &= ~AGGR_CLEANUP;
2199 spin_unlock(&txq->axq_lock);