2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
67 static int modparam_all_channels;
68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
86 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110 static const struct ath5k_srev_name srev_names[] = {
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
149 static const struct ieee80211_rate ath5k_rates[] = {
151 .hw_value = ATH5K_RATE_CODE_1M, },
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 .hw_value = ATH5K_RATE_CODE_6M,
168 .hw_value = ATH5K_RATE_CODE_9M,
171 .hw_value = ATH5K_RATE_CODE_12M,
174 .hw_value = ATH5K_RATE_CODE_18M,
177 .hw_value = ATH5K_RATE_CODE_24M,
180 .hw_value = ATH5K_RATE_CODE_36M,
183 .hw_value = ATH5K_RATE_CODE_48M,
186 .hw_value = ATH5K_RATE_CODE_54M,
192 * Prototypes - PCI stack related functions
194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
198 static int ath5k_pci_suspend(struct device *dev);
199 static int ath5k_pci_resume(struct device *dev);
201 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
202 #define ATH5K_PM_OPS (&ath5k_pm_ops)
204 #define ATH5K_PM_OPS NULL
205 #endif /* CONFIG_PM */
207 static struct pci_driver ath5k_pci_driver = {
208 .name = KBUILD_MODNAME,
209 .id_table = ath5k_pci_id_table,
210 .probe = ath5k_pci_probe,
211 .remove = __devexit_p(ath5k_pci_remove),
212 .driver.pm = ATH5K_PM_OPS,
218 * Prototypes - MAC 802.11 stack related functions
220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
221 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
223 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
224 static int ath5k_reset_wake(struct ath5k_softc *sc);
225 static int ath5k_start(struct ieee80211_hw *hw);
226 static void ath5k_stop(struct ieee80211_hw *hw);
227 static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_vif *vif);
229 static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_vif *vif);
231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
232 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
233 int mc_count, struct dev_addr_list *mc_list);
234 static void ath5k_configure_filter(struct ieee80211_hw *hw,
235 unsigned int changed_flags,
236 unsigned int *new_flags,
238 static int ath5k_set_key(struct ieee80211_hw *hw,
239 enum set_key_cmd cmd,
240 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
241 struct ieee80211_key_conf *key);
242 static int ath5k_get_stats(struct ieee80211_hw *hw,
243 struct ieee80211_low_level_stats *stats);
244 static int ath5k_get_survey(struct ieee80211_hw *hw,
245 int idx, struct survey_info *survey);
246 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
247 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
248 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
249 static int ath5k_beacon_update(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif);
251 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
252 struct ieee80211_vif *vif,
253 struct ieee80211_bss_conf *bss_conf,
255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
256 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
257 static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
260 static const struct ieee80211_ops ath5k_hw_ops = {
262 .start = ath5k_start,
264 .add_interface = ath5k_add_interface,
265 .remove_interface = ath5k_remove_interface,
266 .config = ath5k_config,
267 .prepare_multicast = ath5k_prepare_multicast,
268 .configure_filter = ath5k_configure_filter,
269 .set_key = ath5k_set_key,
270 .get_stats = ath5k_get_stats,
271 .get_survey = ath5k_get_survey,
273 .get_tsf = ath5k_get_tsf,
274 .set_tsf = ath5k_set_tsf,
275 .reset_tsf = ath5k_reset_tsf,
276 .bss_info_changed = ath5k_bss_info_changed,
277 .sw_scan_start = ath5k_sw_scan_start,
278 .sw_scan_complete = ath5k_sw_scan_complete,
279 .set_coverage_class = ath5k_set_coverage_class,
283 * Prototypes - Internal functions
286 static int ath5k_attach(struct pci_dev *pdev,
287 struct ieee80211_hw *hw);
288 static void ath5k_detach(struct pci_dev *pdev,
289 struct ieee80211_hw *hw);
290 /* Channel/mode setup */
291 static inline short ath5k_ieee2mhz(short chan);
292 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
293 struct ieee80211_channel *channels,
296 static int ath5k_setup_bands(struct ieee80211_hw *hw);
297 static int ath5k_chan_set(struct ath5k_softc *sc,
298 struct ieee80211_channel *chan);
299 static void ath5k_setcurmode(struct ath5k_softc *sc,
301 static void ath5k_mode_setup(struct ath5k_softc *sc);
303 /* Descriptor setup */
304 static int ath5k_desc_alloc(struct ath5k_softc *sc,
305 struct pci_dev *pdev);
306 static void ath5k_desc_free(struct ath5k_softc *sc,
307 struct pci_dev *pdev);
309 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
310 struct ath5k_buf *bf);
311 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
312 struct ath5k_buf *bf,
313 struct ath5k_txq *txq, int padsize);
314 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
315 struct ath5k_buf *bf)
320 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
322 dev_kfree_skb_any(bf->skb);
326 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
327 struct ath5k_buf *bf)
329 struct ath5k_hw *ah = sc->ah;
330 struct ath_common *common = ath5k_hw_common(ah);
335 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
337 dev_kfree_skb_any(bf->skb);
343 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
344 int qtype, int subtype);
345 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
346 static int ath5k_beaconq_config(struct ath5k_softc *sc);
347 static void ath5k_txq_drainq(struct ath5k_softc *sc,
348 struct ath5k_txq *txq);
349 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
350 static void ath5k_txq_release(struct ath5k_softc *sc);
352 static int ath5k_rx_start(struct ath5k_softc *sc);
353 static void ath5k_rx_stop(struct ath5k_softc *sc);
354 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
355 struct ath5k_desc *ds,
357 struct ath5k_rx_status *rs);
358 static void ath5k_tasklet_rx(unsigned long data);
360 static void ath5k_tx_processq(struct ath5k_softc *sc,
361 struct ath5k_txq *txq);
362 static void ath5k_tasklet_tx(unsigned long data);
363 /* Beacon handling */
364 static int ath5k_beacon_setup(struct ath5k_softc *sc,
365 struct ath5k_buf *bf);
366 static void ath5k_beacon_send(struct ath5k_softc *sc);
367 static void ath5k_beacon_config(struct ath5k_softc *sc);
368 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
369 static void ath5k_tasklet_beacon(unsigned long data);
370 static void ath5k_tasklet_ani(unsigned long data);
372 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
374 u64 tsf = ath5k_hw_get_tsf64(ah);
376 if ((tsf & 0x7fff) < rstamp)
379 return (tsf & ~0x7fff) | rstamp;
382 /* Interrupt handling */
383 static int ath5k_init(struct ath5k_softc *sc);
384 static int ath5k_stop_locked(struct ath5k_softc *sc);
385 static int ath5k_stop_hw(struct ath5k_softc *sc);
386 static irqreturn_t ath5k_intr(int irq, void *dev_id);
387 static void ath5k_tasklet_reset(unsigned long data);
389 static void ath5k_tasklet_calibrate(unsigned long data);
392 * Module init/exit functions
401 ret = pci_register_driver(&ath5k_pci_driver);
403 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
413 pci_unregister_driver(&ath5k_pci_driver);
415 ath5k_debug_finish();
418 module_init(init_ath5k_pci);
419 module_exit(exit_ath5k_pci);
422 /********************\
423 * PCI Initialization *
424 \********************/
427 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
429 const char *name = "xxxxx";
432 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
433 if (srev_names[i].sr_type != type)
436 if ((val & 0xf0) == srev_names[i].sr_val)
437 name = srev_names[i].sr_name;
439 if ((val & 0xff) == srev_names[i].sr_val) {
440 name = srev_names[i].sr_name;
447 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
449 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
450 return ath5k_hw_reg_read(ah, reg_offset);
453 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
455 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
456 ath5k_hw_reg_write(ah, val, reg_offset);
459 static const struct ath_ops ath5k_common_ops = {
460 .read = ath5k_ioread32,
461 .write = ath5k_iowrite32,
465 ath5k_pci_probe(struct pci_dev *pdev,
466 const struct pci_device_id *id)
469 struct ath5k_softc *sc;
470 struct ath_common *common;
471 struct ieee80211_hw *hw;
475 ret = pci_enable_device(pdev);
477 dev_err(&pdev->dev, "can't enable device\n");
481 /* XXX 32-bit addressing only */
482 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
484 dev_err(&pdev->dev, "32-bit DMA not available\n");
489 * Cache line size is used to size and align various
490 * structures used to communicate with the hardware.
492 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
495 * Linux 2.4.18 (at least) writes the cache line size
496 * register as a 16-bit wide register which is wrong.
497 * We must have this setup properly for rx buffer
498 * DMA to work so force a reasonable value here if it
501 csz = L1_CACHE_BYTES >> 2;
502 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
505 * The default setting of latency timer yields poor results,
506 * set it to the value used by other systems. It may be worth
507 * tweaking this setting more.
509 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
511 /* Enable bus mastering */
512 pci_set_master(pdev);
515 * Disable the RETRY_TIMEOUT register (0x41) to keep
516 * PCI Tx retries from interfering with C3 CPU state.
518 pci_write_config_byte(pdev, 0x41, 0);
520 ret = pci_request_region(pdev, 0, "ath5k");
522 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
526 mem = pci_iomap(pdev, 0, 0);
528 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
534 * Allocate hw (mac80211 main struct)
535 * and hw->priv (driver private data)
537 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
539 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
544 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
546 /* Initialize driver private data */
547 SET_IEEE80211_DEV(hw, &pdev->dev);
548 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
549 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
550 IEEE80211_HW_SIGNAL_DBM;
552 hw->wiphy->interface_modes =
553 BIT(NL80211_IFTYPE_AP) |
554 BIT(NL80211_IFTYPE_STATION) |
555 BIT(NL80211_IFTYPE_ADHOC) |
556 BIT(NL80211_IFTYPE_MESH_POINT);
558 hw->extra_tx_headroom = 2;
559 hw->channel_change_time = 5000;
564 ath5k_debug_init_device(sc);
567 * Mark the device as detached to avoid processing
568 * interrupts until setup is complete.
570 __set_bit(ATH_STAT_INVALID, sc->status);
572 sc->iobase = mem; /* So we can unmap it on detach */
573 sc->opmode = NL80211_IFTYPE_STATION;
575 mutex_init(&sc->lock);
576 spin_lock_init(&sc->rxbuflock);
577 spin_lock_init(&sc->txbuflock);
578 spin_lock_init(&sc->block);
580 /* Set private data */
581 pci_set_drvdata(pdev, hw);
583 /* Setup interrupt handler */
584 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
586 ATH5K_ERR(sc, "request_irq failed\n");
590 /*If we passed the test malloc a ath5k_hw struct*/
591 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
594 ATH5K_ERR(sc, "out of memory\n");
599 sc->ah->ah_iobase = sc->iobase;
600 common = ath5k_hw_common(sc->ah);
601 common->ops = &ath5k_common_ops;
604 common->cachelsz = csz << 2; /* convert to bytes */
606 /* Initialize device */
607 ret = ath5k_hw_attach(sc);
612 /* set up multi-rate retry capabilities */
613 if (sc->ah->ah_version == AR5K_AR5212) {
615 hw->max_rate_tries = 11;
618 /* Finish private driver data initialization */
619 ret = ath5k_attach(pdev, hw);
623 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
624 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
626 sc->ah->ah_phy_revision);
628 if (!sc->ah->ah_single_chip) {
629 /* Single chip radio (!RF5111) */
630 if (sc->ah->ah_radio_5ghz_revision &&
631 !sc->ah->ah_radio_2ghz_revision) {
632 /* No 5GHz support -> report 2GHz radio */
633 if (!test_bit(AR5K_MODE_11A,
634 sc->ah->ah_capabilities.cap_mode)) {
635 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
636 ath5k_chip_name(AR5K_VERSION_RAD,
637 sc->ah->ah_radio_5ghz_revision),
638 sc->ah->ah_radio_5ghz_revision);
639 /* No 2GHz support (5110 and some
640 * 5Ghz only cards) -> report 5Ghz radio */
641 } else if (!test_bit(AR5K_MODE_11B,
642 sc->ah->ah_capabilities.cap_mode)) {
643 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
644 ath5k_chip_name(AR5K_VERSION_RAD,
645 sc->ah->ah_radio_5ghz_revision),
646 sc->ah->ah_radio_5ghz_revision);
647 /* Multiband radio */
649 ATH5K_INFO(sc, "RF%s multiband radio found"
651 ath5k_chip_name(AR5K_VERSION_RAD,
652 sc->ah->ah_radio_5ghz_revision),
653 sc->ah->ah_radio_5ghz_revision);
656 /* Multi chip radio (RF5111 - RF2111) ->
657 * report both 2GHz/5GHz radios */
658 else if (sc->ah->ah_radio_5ghz_revision &&
659 sc->ah->ah_radio_2ghz_revision){
660 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
661 ath5k_chip_name(AR5K_VERSION_RAD,
662 sc->ah->ah_radio_5ghz_revision),
663 sc->ah->ah_radio_5ghz_revision);
664 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
665 ath5k_chip_name(AR5K_VERSION_RAD,
666 sc->ah->ah_radio_2ghz_revision),
667 sc->ah->ah_radio_2ghz_revision);
672 /* ready to process interrupts */
673 __clear_bit(ATH_STAT_INVALID, sc->status);
677 ath5k_hw_detach(sc->ah);
679 free_irq(pdev->irq, sc);
683 ieee80211_free_hw(hw);
685 pci_iounmap(pdev, mem);
687 pci_release_region(pdev, 0);
689 pci_disable_device(pdev);
694 static void __devexit
695 ath5k_pci_remove(struct pci_dev *pdev)
697 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
698 struct ath5k_softc *sc = hw->priv;
700 ath5k_debug_finish_device(sc);
701 ath5k_detach(pdev, hw);
702 ath5k_hw_detach(sc->ah);
704 free_irq(pdev->irq, sc);
705 pci_iounmap(pdev, sc->iobase);
706 pci_release_region(pdev, 0);
707 pci_disable_device(pdev);
708 ieee80211_free_hw(hw);
712 static int ath5k_pci_suspend(struct device *dev)
714 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev));
715 struct ath5k_softc *sc = hw->priv;
721 static int ath5k_pci_resume(struct device *dev)
723 struct pci_dev *pdev = to_pci_dev(dev);
724 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
725 struct ath5k_softc *sc = hw->priv;
728 * Suspend/Resume resets the PCI configuration space, so we have to
729 * re-disable the RETRY_TIMEOUT register (0x41) to keep
730 * PCI Tx retries from interfering with C3 CPU state
732 pci_write_config_byte(pdev, 0x41, 0);
734 ath5k_led_enable(sc);
737 #endif /* CONFIG_PM */
740 /***********************\
741 * Driver Initialization *
742 \***********************/
744 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
746 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
747 struct ath5k_softc *sc = hw->priv;
748 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
750 return ath_reg_notifier_apply(wiphy, request, regulatory);
754 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
756 struct ath5k_softc *sc = hw->priv;
757 struct ath5k_hw *ah = sc->ah;
758 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
759 u8 mac[ETH_ALEN] = {};
762 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
765 * Check if the MAC has multi-rate retry support.
766 * We do this by trying to setup a fake extended
767 * descriptor. MAC's that don't have support will
768 * return false w/o doing anything. MAC's that do
769 * support it will return true w/o doing anything.
771 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
775 __set_bit(ATH_STAT_MRRETRY, sc->status);
778 * Collect the channel list. The 802.11 layer
779 * is resposible for filtering this list based
780 * on settings like the phy mode and regulatory
781 * domain restrictions.
783 ret = ath5k_setup_bands(hw);
785 ATH5K_ERR(sc, "can't get channels\n");
789 /* NB: setup here so ath5k_rate_update is happy */
790 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
791 ath5k_setcurmode(sc, AR5K_MODE_11A);
793 ath5k_setcurmode(sc, AR5K_MODE_11B);
796 * Allocate tx+rx descriptors and populate the lists.
798 ret = ath5k_desc_alloc(sc, pdev);
800 ATH5K_ERR(sc, "can't allocate descriptors\n");
805 * Allocate hardware transmit queues: one queue for
806 * beacon frames and one data queue for each QoS
807 * priority. Note that hw functions handle reseting
808 * these queues at the needed time.
810 ret = ath5k_beaconq_setup(ah);
812 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
816 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
817 if (IS_ERR(sc->cabq)) {
818 ATH5K_ERR(sc, "can't setup cab queue\n");
819 ret = PTR_ERR(sc->cabq);
823 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
824 if (IS_ERR(sc->txq)) {
825 ATH5K_ERR(sc, "can't setup xmit queue\n");
826 ret = PTR_ERR(sc->txq);
830 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
831 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
832 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
833 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
834 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
835 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
837 ret = ath5k_eeprom_read_mac(ah, mac);
839 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
844 SET_IEEE80211_PERM_ADDR(hw, mac);
845 /* All MAC address bits matter for ACKs */
846 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
847 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
849 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
850 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
852 ATH5K_ERR(sc, "can't initialize regulatory system\n");
856 ret = ieee80211_register_hw(hw);
858 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
862 if (!ath_is_world_regd(regulatory))
863 regulatory_hint(hw->wiphy, regulatory->alpha2);
869 ath5k_txq_release(sc);
871 ath5k_hw_release_tx_queue(ah, sc->bhalq);
873 ath5k_desc_free(sc, pdev);
879 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
881 struct ath5k_softc *sc = hw->priv;
884 * NB: the order of these is important:
885 * o call the 802.11 layer before detaching ath5k_hw to
886 * insure callbacks into the driver to delete global
887 * key cache entries can be handled
888 * o reclaim the tx queue data structures after calling
889 * the 802.11 layer as we'll get called back to reclaim
890 * node state and potentially want to use them
891 * o to cleanup the tx queues the hal is called, so detach
893 * XXX: ??? detach ath5k_hw ???
894 * Other than that, it's straightforward...
896 ieee80211_unregister_hw(hw);
897 ath5k_desc_free(sc, pdev);
898 ath5k_txq_release(sc);
899 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
900 ath5k_unregister_leds(sc);
903 * NB: can't reclaim these until after ieee80211_ifdetach
904 * returns because we'll get called back to reclaim node
905 * state and potentially want to use them.
912 /********************\
913 * Channel/mode setup *
914 \********************/
917 * Convert IEEE channel number to MHz frequency.
920 ath5k_ieee2mhz(short chan)
922 if (chan <= 14 || chan >= 27)
923 return ieee80211chan2mhz(chan);
925 return 2212 + chan * 20;
929 * Returns true for the channel numbers used without all_channels modparam.
931 static bool ath5k_is_standard_channel(short chan)
933 return ((chan <= 14) ||
935 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
937 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
939 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
943 ath5k_copy_channels(struct ath5k_hw *ah,
944 struct ieee80211_channel *channels,
948 unsigned int i, count, size, chfreq, freq, ch;
950 if (!test_bit(mode, ah->ah_modes))
955 case AR5K_MODE_11A_TURBO:
956 /* 1..220, but 2GHz frequencies are filtered by check_channel */
958 chfreq = CHANNEL_5GHZ;
962 case AR5K_MODE_11G_TURBO:
964 chfreq = CHANNEL_2GHZ;
967 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
971 for (i = 0, count = 0; i < size && max > 0; i++) {
973 freq = ath5k_ieee2mhz(ch);
975 /* Check if channel is supported by the chipset */
976 if (!ath5k_channel_ok(ah, freq, chfreq))
979 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
982 /* Write channel info and increment counter */
983 channels[count].center_freq = freq;
984 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
985 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
989 channels[count].hw_value = chfreq | CHANNEL_OFDM;
991 case AR5K_MODE_11A_TURBO:
992 case AR5K_MODE_11G_TURBO:
993 channels[count].hw_value = chfreq |
994 CHANNEL_OFDM | CHANNEL_TURBO;
997 channels[count].hw_value = CHANNEL_B;
1008 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1012 for (i = 0; i < AR5K_MAX_RATES; i++)
1013 sc->rate_idx[b->band][i] = -1;
1015 for (i = 0; i < b->n_bitrates; i++) {
1016 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1017 if (b->bitrates[i].hw_value_short)
1018 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1023 ath5k_setup_bands(struct ieee80211_hw *hw)
1025 struct ath5k_softc *sc = hw->priv;
1026 struct ath5k_hw *ah = sc->ah;
1027 struct ieee80211_supported_band *sband;
1028 int max_c, count_c = 0;
1031 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1032 max_c = ARRAY_SIZE(sc->channels);
1035 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1036 sband->band = IEEE80211_BAND_2GHZ;
1037 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1039 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1041 memcpy(sband->bitrates, &ath5k_rates[0],
1042 sizeof(struct ieee80211_rate) * 12);
1043 sband->n_bitrates = 12;
1045 sband->channels = sc->channels;
1046 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1047 AR5K_MODE_11G, max_c);
1049 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1050 count_c = sband->n_channels;
1052 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1054 memcpy(sband->bitrates, &ath5k_rates[0],
1055 sizeof(struct ieee80211_rate) * 4);
1056 sband->n_bitrates = 4;
1058 /* 5211 only supports B rates and uses 4bit rate codes
1059 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1062 if (ah->ah_version == AR5K_AR5211) {
1063 for (i = 0; i < 4; i++) {
1064 sband->bitrates[i].hw_value =
1065 sband->bitrates[i].hw_value & 0xF;
1066 sband->bitrates[i].hw_value_short =
1067 sband->bitrates[i].hw_value_short & 0xF;
1071 sband->channels = sc->channels;
1072 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1073 AR5K_MODE_11B, max_c);
1075 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1076 count_c = sband->n_channels;
1079 ath5k_setup_rate_idx(sc, sband);
1081 /* 5GHz band, A mode */
1082 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1083 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1084 sband->band = IEEE80211_BAND_5GHZ;
1085 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1087 memcpy(sband->bitrates, &ath5k_rates[4],
1088 sizeof(struct ieee80211_rate) * 8);
1089 sband->n_bitrates = 8;
1091 sband->channels = &sc->channels[count_c];
1092 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1093 AR5K_MODE_11A, max_c);
1095 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1097 ath5k_setup_rate_idx(sc, sband);
1099 ath5k_debug_dump_bands(sc);
1105 * Set/change channels. We always reset the chip.
1106 * To accomplish this we must first cleanup any pending DMA,
1107 * then restart stuff after a la ath5k_init.
1109 * Called with sc->lock.
1112 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1114 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1115 sc->curchan->center_freq, chan->center_freq);
1118 * To switch channels clear any pending DMA operations;
1119 * wait long enough for the RX fifo to drain, reset the
1120 * hardware at the new frequency, and then re-enable
1121 * the relevant bits of the h/w.
1123 return ath5k_reset(sc, chan);
1127 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1131 if (mode == AR5K_MODE_11A) {
1132 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1134 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1139 ath5k_mode_setup(struct ath5k_softc *sc)
1141 struct ath5k_hw *ah = sc->ah;
1144 /* configure rx filter */
1145 rfilt = sc->filter_flags;
1146 ath5k_hw_set_rx_filter(ah, rfilt);
1148 if (ath5k_hw_hasbssidmask(ah))
1149 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1151 /* configure operational mode */
1152 ath5k_hw_set_opmode(ah, sc->opmode);
1154 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
1155 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1159 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1163 /* return base rate on errors */
1164 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1165 "hw_rix out of bounds: %x\n", hw_rix))
1168 rix = sc->rate_idx[sc->curband->band][hw_rix];
1169 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1180 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1182 struct ath_common *common = ath5k_hw_common(sc->ah);
1183 struct sk_buff *skb;
1186 * Allocate buffer with headroom_needed space for the
1187 * fake physical layer header at the start.
1189 skb = ath_rxbuf_alloc(common,
1194 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1195 common->rx_bufsize);
1199 *skb_addr = pci_map_single(sc->pdev,
1200 skb->data, common->rx_bufsize,
1201 PCI_DMA_FROMDEVICE);
1202 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1203 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1211 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1213 struct ath5k_hw *ah = sc->ah;
1214 struct sk_buff *skb = bf->skb;
1215 struct ath5k_desc *ds;
1218 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1225 * Setup descriptors. For receive we always terminate
1226 * the descriptor list with a self-linked entry so we'll
1227 * not get overrun under high load (as can happen with a
1228 * 5212 when ANI processing enables PHY error frames).
1230 * To insure the last descriptor is self-linked we create
1231 * each descriptor as self-linked and add it to the end. As
1232 * each additional descriptor is added the previous self-linked
1233 * entry is ``fixed'' naturally. This should be safe even
1234 * if DMA is happening. When processing RX interrupts we
1235 * never remove/process the last, self-linked, entry on the
1236 * descriptor list. This insures the hardware always has
1237 * someplace to write a new frame.
1240 ds->ds_link = bf->daddr; /* link to self */
1241 ds->ds_data = bf->skbaddr;
1242 ah->ah_setup_rx_desc(ah, ds,
1243 skb_tailroom(skb), /* buffer size */
1246 if (sc->rxlink != NULL)
1247 *sc->rxlink = bf->daddr;
1248 sc->rxlink = &ds->ds_link;
1252 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1254 struct ieee80211_hdr *hdr;
1255 enum ath5k_pkt_type htype;
1258 hdr = (struct ieee80211_hdr *)skb->data;
1259 fc = hdr->frame_control;
1261 if (ieee80211_is_beacon(fc))
1262 htype = AR5K_PKT_TYPE_BEACON;
1263 else if (ieee80211_is_probe_resp(fc))
1264 htype = AR5K_PKT_TYPE_PROBE_RESP;
1265 else if (ieee80211_is_atim(fc))
1266 htype = AR5K_PKT_TYPE_ATIM;
1267 else if (ieee80211_is_pspoll(fc))
1268 htype = AR5K_PKT_TYPE_PSPOLL;
1270 htype = AR5K_PKT_TYPE_NORMAL;
1276 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1277 struct ath5k_txq *txq, int padsize)
1279 struct ath5k_hw *ah = sc->ah;
1280 struct ath5k_desc *ds = bf->desc;
1281 struct sk_buff *skb = bf->skb;
1282 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1283 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1284 struct ieee80211_rate *rate;
1285 unsigned int mrr_rate[3], mrr_tries[3];
1292 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1294 /* XXX endianness */
1295 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1298 rate = ieee80211_get_tx_rate(sc->hw, info);
1300 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1301 flags |= AR5K_TXDESC_NOACK;
1303 rc_flags = info->control.rates[0].flags;
1304 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1305 rate->hw_value_short : rate->hw_value;
1309 /* FIXME: If we are in g mode and rate is a CCK rate
1310 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1311 * from tx power (value is in dB units already) */
1312 if (info->control.hw_key) {
1313 keyidx = info->control.hw_key->hw_key_idx;
1314 pktlen += info->control.hw_key->icv_len;
1316 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1317 flags |= AR5K_TXDESC_RTSENA;
1318 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1319 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1320 sc->vif, pktlen, info));
1322 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1323 flags |= AR5K_TXDESC_CTSENA;
1324 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1325 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1326 sc->vif, pktlen, info));
1328 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1329 ieee80211_get_hdrlen_from_skb(skb), padsize,
1330 get_hw_packet_type(skb),
1331 (sc->power_level * 2),
1333 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1334 cts_rate, duration);
1338 memset(mrr_rate, 0, sizeof(mrr_rate));
1339 memset(mrr_tries, 0, sizeof(mrr_tries));
1340 for (i = 0; i < 3; i++) {
1341 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1345 mrr_rate[i] = rate->hw_value;
1346 mrr_tries[i] = info->control.rates[i + 1].count;
1349 ah->ah_setup_mrr_tx_desc(ah, ds,
1350 mrr_rate[0], mrr_tries[0],
1351 mrr_rate[1], mrr_tries[1],
1352 mrr_rate[2], mrr_tries[2]);
1355 ds->ds_data = bf->skbaddr;
1357 spin_lock_bh(&txq->lock);
1358 list_add_tail(&bf->list, &txq->q);
1359 if (txq->link == NULL) /* is this first packet? */
1360 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1361 else /* no, so only link it */
1362 *txq->link = bf->daddr;
1364 txq->link = &ds->ds_link;
1365 ath5k_hw_start_tx_dma(ah, txq->qnum);
1367 spin_unlock_bh(&txq->lock);
1371 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1375 /*******************\
1376 * Descriptors setup *
1377 \*******************/
1380 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1382 struct ath5k_desc *ds;
1383 struct ath5k_buf *bf;
1388 /* allocate descriptors */
1389 sc->desc_len = sizeof(struct ath5k_desc) *
1390 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1391 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1392 if (sc->desc == NULL) {
1393 ATH5K_ERR(sc, "can't allocate descriptors\n");
1398 da = sc->desc_daddr;
1399 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1400 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1402 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1403 sizeof(struct ath5k_buf), GFP_KERNEL);
1405 ATH5K_ERR(sc, "can't allocate bufptr\n");
1411 INIT_LIST_HEAD(&sc->rxbuf);
1412 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1415 list_add_tail(&bf->list, &sc->rxbuf);
1418 INIT_LIST_HEAD(&sc->txbuf);
1419 sc->txbuf_len = ATH_TXBUF;
1420 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1421 da += sizeof(*ds)) {
1424 list_add_tail(&bf->list, &sc->txbuf);
1434 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1441 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1443 struct ath5k_buf *bf;
1445 ath5k_txbuf_free(sc, sc->bbuf);
1446 list_for_each_entry(bf, &sc->txbuf, list)
1447 ath5k_txbuf_free(sc, bf);
1448 list_for_each_entry(bf, &sc->rxbuf, list)
1449 ath5k_rxbuf_free(sc, bf);
1451 /* Free memory associated with all descriptors */
1452 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1466 static struct ath5k_txq *
1467 ath5k_txq_setup(struct ath5k_softc *sc,
1468 int qtype, int subtype)
1470 struct ath5k_hw *ah = sc->ah;
1471 struct ath5k_txq *txq;
1472 struct ath5k_txq_info qi = {
1473 .tqi_subtype = subtype,
1474 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1475 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1476 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1481 * Enable interrupts only for EOL and DESC conditions.
1482 * We mark tx descriptors to receive a DESC interrupt
1483 * when a tx queue gets deep; otherwise waiting for the
1484 * EOL to reap descriptors. Note that this is done to
1485 * reduce interrupt load and this only defers reaping
1486 * descriptors, never transmitting frames. Aside from
1487 * reducing interrupts this also permits more concurrency.
1488 * The only potential downside is if the tx queue backs
1489 * up in which case the top half of the kernel may backup
1490 * due to a lack of tx descriptors.
1492 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1493 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1494 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1497 * NB: don't print a message, this happens
1498 * normally on parts with too few tx queues
1500 return ERR_PTR(qnum);
1502 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1503 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1504 qnum, ARRAY_SIZE(sc->txqs));
1505 ath5k_hw_release_tx_queue(ah, qnum);
1506 return ERR_PTR(-EINVAL);
1508 txq = &sc->txqs[qnum];
1512 INIT_LIST_HEAD(&txq->q);
1513 spin_lock_init(&txq->lock);
1516 return &sc->txqs[qnum];
1520 ath5k_beaconq_setup(struct ath5k_hw *ah)
1522 struct ath5k_txq_info qi = {
1523 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1524 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1525 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1526 /* NB: for dynamic turbo, don't enable any other interrupts */
1527 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1530 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1534 ath5k_beaconq_config(struct ath5k_softc *sc)
1536 struct ath5k_hw *ah = sc->ah;
1537 struct ath5k_txq_info qi;
1540 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1544 if (sc->opmode == NL80211_IFTYPE_AP ||
1545 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1547 * Always burst out beacon and CAB traffic
1548 * (aifs = cwmin = cwmax = 0)
1553 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1555 * Adhoc mode; backoff between 0 and (2 * cw_min).
1559 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1562 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1563 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1564 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1566 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1568 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1569 "hardware queue!\n", __func__);
1572 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1576 /* reconfigure cabq with ready time to 80% of beacon_interval */
1577 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1581 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1582 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1586 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1592 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1594 struct ath5k_buf *bf, *bf0;
1597 * NB: this assumes output has been stopped and
1598 * we do not need to block ath5k_tx_tasklet
1600 spin_lock_bh(&txq->lock);
1601 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1602 ath5k_debug_printtxbuf(sc, bf);
1604 ath5k_txbuf_free(sc, bf);
1606 spin_lock_bh(&sc->txbuflock);
1607 list_move_tail(&bf->list, &sc->txbuf);
1609 spin_unlock_bh(&sc->txbuflock);
1612 spin_unlock_bh(&txq->lock);
1616 * Drain the transmit queues and reclaim resources.
1619 ath5k_txq_cleanup(struct ath5k_softc *sc)
1621 struct ath5k_hw *ah = sc->ah;
1624 /* XXX return value */
1625 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1626 /* don't touch the hardware if marked invalid */
1627 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1628 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1629 ath5k_hw_get_txdp(ah, sc->bhalq));
1630 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1631 if (sc->txqs[i].setup) {
1632 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1633 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1636 ath5k_hw_get_txdp(ah,
1642 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1643 if (sc->txqs[i].setup)
1644 ath5k_txq_drainq(sc, &sc->txqs[i]);
1648 ath5k_txq_release(struct ath5k_softc *sc)
1650 struct ath5k_txq *txq = sc->txqs;
1653 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1655 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1668 * Enable the receive h/w following a reset.
1671 ath5k_rx_start(struct ath5k_softc *sc)
1673 struct ath5k_hw *ah = sc->ah;
1674 struct ath_common *common = ath5k_hw_common(ah);
1675 struct ath5k_buf *bf;
1678 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
1680 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1681 common->cachelsz, common->rx_bufsize);
1683 spin_lock_bh(&sc->rxbuflock);
1685 list_for_each_entry(bf, &sc->rxbuf, list) {
1686 ret = ath5k_rxbuf_setup(sc, bf);
1688 spin_unlock_bh(&sc->rxbuflock);
1692 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1693 ath5k_hw_set_rxdp(ah, bf->daddr);
1694 spin_unlock_bh(&sc->rxbuflock);
1696 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1697 ath5k_mode_setup(sc); /* set filters, etc. */
1698 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1706 * Disable the receive h/w in preparation for a reset.
1709 ath5k_rx_stop(struct ath5k_softc *sc)
1711 struct ath5k_hw *ah = sc->ah;
1713 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1714 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1715 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1717 ath5k_debug_printrxbuffs(sc, ah);
1719 sc->rxlink = NULL; /* just in case */
1723 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1724 struct sk_buff *skb, struct ath5k_rx_status *rs)
1726 struct ath5k_hw *ah = sc->ah;
1727 struct ath_common *common = ath5k_hw_common(ah);
1728 struct ieee80211_hdr *hdr = (void *)skb->data;
1729 unsigned int keyix, hlen;
1731 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1732 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1733 return RX_FLAG_DECRYPTED;
1735 /* Apparently when a default key is used to decrypt the packet
1736 the hw does not set the index used to decrypt. In such cases
1737 get the index from the packet. */
1738 hlen = ieee80211_hdrlen(hdr->frame_control);
1739 if (ieee80211_has_protected(hdr->frame_control) &&
1740 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1741 skb->len >= hlen + 4) {
1742 keyix = skb->data[hlen + 3] >> 6;
1744 if (test_bit(keyix, common->keymap))
1745 return RX_FLAG_DECRYPTED;
1753 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1754 struct ieee80211_rx_status *rxs)
1756 struct ath_common *common = ath5k_hw_common(sc->ah);
1759 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1761 if (ieee80211_is_beacon(mgmt->frame_control) &&
1762 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1763 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1765 * Received an IBSS beacon with the same BSSID. Hardware *must*
1766 * have updated the local TSF. We have to work around various
1767 * hardware bugs, though...
1769 tsf = ath5k_hw_get_tsf64(sc->ah);
1770 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1771 hw_tu = TSF_TO_TU(tsf);
1773 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1774 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1775 (unsigned long long)bc_tstamp,
1776 (unsigned long long)rxs->mactime,
1777 (unsigned long long)(rxs->mactime - bc_tstamp),
1778 (unsigned long long)tsf);
1781 * Sometimes the HW will give us a wrong tstamp in the rx
1782 * status, causing the timestamp extension to go wrong.
1783 * (This seems to happen especially with beacon frames bigger
1784 * than 78 byte (incl. FCS))
1785 * But we know that the receive timestamp must be later than the
1786 * timestamp of the beacon since HW must have synced to that.
1788 * NOTE: here we assume mactime to be after the frame was
1789 * received, not like mac80211 which defines it at the start.
1791 if (bc_tstamp > rxs->mactime) {
1792 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1793 "fixing mactime from %llx to %llx\n",
1794 (unsigned long long)rxs->mactime,
1795 (unsigned long long)tsf);
1800 * Local TSF might have moved higher than our beacon timers,
1801 * in that case we have to update them to continue sending
1802 * beacons. This also takes care of synchronizing beacon sending
1803 * times with other stations.
1805 if (hw_tu >= sc->nexttbtt)
1806 ath5k_beacon_update_timers(sc, bc_tstamp);
1811 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1813 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1814 struct ath5k_hw *ah = sc->ah;
1815 struct ath_common *common = ath5k_hw_common(ah);
1817 /* only beacons from our BSSID */
1818 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1819 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1822 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1825 /* in IBSS mode we should keep RSSI statistics per neighbour */
1826 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1830 * Compute padding position. skb must contains an IEEE 802.11 frame
1832 static int ath5k_common_padpos(struct sk_buff *skb)
1834 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1835 __le16 frame_control = hdr->frame_control;
1838 if (ieee80211_has_a4(frame_control)) {
1841 if (ieee80211_is_data_qos(frame_control)) {
1842 padpos += IEEE80211_QOS_CTL_LEN;
1849 * This function expects a 802.11 frame and returns the number of
1850 * bytes added, or -1 if we don't have enought header room.
1853 static int ath5k_add_padding(struct sk_buff *skb)
1855 int padpos = ath5k_common_padpos(skb);
1856 int padsize = padpos & 3;
1858 if (padsize && skb->len>padpos) {
1860 if (skb_headroom(skb) < padsize)
1863 skb_push(skb, padsize);
1864 memmove(skb->data, skb->data+padsize, padpos);
1872 * This function expects a 802.11 frame and returns the number of
1876 static int ath5k_remove_padding(struct sk_buff *skb)
1878 int padpos = ath5k_common_padpos(skb);
1879 int padsize = padpos & 3;
1881 if (padsize && skb->len>=padpos+padsize) {
1882 memmove(skb->data + padsize, skb->data, padpos);
1883 skb_pull(skb, padsize);
1891 ath5k_tasklet_rx(unsigned long data)
1893 struct ieee80211_rx_status *rxs;
1894 struct ath5k_rx_status rs = {};
1895 struct sk_buff *skb, *next_skb;
1896 dma_addr_t next_skb_addr;
1897 struct ath5k_softc *sc = (void *)data;
1898 struct ath5k_hw *ah = sc->ah;
1899 struct ath_common *common = ath5k_hw_common(ah);
1900 struct ath5k_buf *bf;
1901 struct ath5k_desc *ds;
1905 spin_lock(&sc->rxbuflock);
1906 if (list_empty(&sc->rxbuf)) {
1907 ATH5K_WARN(sc, "empty rx buf pool\n");
1913 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1914 BUG_ON(bf->skb == NULL);
1918 /* bail if HW is still using self-linked descriptor */
1919 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1922 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1923 if (unlikely(ret == -EINPROGRESS))
1925 else if (unlikely(ret)) {
1926 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1927 sc->stats.rxerr_proc++;
1928 spin_unlock(&sc->rxbuflock);
1932 sc->stats.rx_all_count++;
1934 if (unlikely(rs.rs_status)) {
1935 if (rs.rs_status & AR5K_RXERR_CRC)
1936 sc->stats.rxerr_crc++;
1937 if (rs.rs_status & AR5K_RXERR_FIFO)
1938 sc->stats.rxerr_fifo++;
1939 if (rs.rs_status & AR5K_RXERR_PHY) {
1940 sc->stats.rxerr_phy++;
1941 if (rs.rs_phyerr > 0 && rs.rs_phyerr < 32)
1942 sc->stats.rxerr_phy_code[rs.rs_phyerr]++;
1945 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1947 * Decrypt error. If the error occurred
1948 * because there was no hardware key, then
1949 * let the frame through so the upper layers
1950 * can process it. This is necessary for 5210
1951 * parts which have no way to setup a ``clear''
1954 * XXX do key cache faulting
1956 sc->stats.rxerr_decrypt++;
1957 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1958 !(rs.rs_status & AR5K_RXERR_CRC))
1961 if (rs.rs_status & AR5K_RXERR_MIC) {
1962 rx_flag |= RX_FLAG_MMIC_ERROR;
1963 sc->stats.rxerr_mic++;
1967 /* let crypto-error packets fall through in MNTR */
1969 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1970 sc->opmode != NL80211_IFTYPE_MONITOR)
1974 if (unlikely(rs.rs_more)) {
1975 sc->stats.rxerr_jumbo++;
1980 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1983 * If we can't replace bf->skb with a new skb under memory
1984 * pressure, just skip this packet
1989 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
1990 PCI_DMA_FROMDEVICE);
1991 skb_put(skb, rs.rs_datalen);
1993 /* The MAC header is padded to have 32-bit boundary if the
1994 * packet payload is non-zero. The general calculation for
1995 * padsize would take into account odd header lengths:
1996 * padsize = (4 - hdrlen % 4) % 4; However, since only
1997 * even-length headers are used, padding can only be 0 or 2
1998 * bytes and we can optimize this a bit. In addition, we must
1999 * not try to remove padding from short control frames that do
2000 * not have payload. */
2001 ath5k_remove_padding(skb);
2003 rxs = IEEE80211_SKB_RXCB(skb);
2006 * always extend the mac timestamp, since this information is
2007 * also needed for proper IBSS merging.
2009 * XXX: it might be too late to do it here, since rs_tstamp is
2010 * 15bit only. that means TSF extension has to be done within
2011 * 32768usec (about 32ms). it might be necessary to move this to
2012 * the interrupt handler, like it is done in madwifi.
2014 * Unfortunately we don't know when the hardware takes the rx
2015 * timestamp (beginning of phy frame, data frame, end of rx?).
2016 * The only thing we know is that it is hardware specific...
2017 * On AR5213 it seems the rx timestamp is at the end of the
2018 * frame, but i'm not sure.
2020 * NOTE: mac80211 defines mactime at the beginning of the first
2021 * data symbol. Since we don't have any time references it's
2022 * impossible to comply to that. This affects IBSS merge only
2023 * right now, so it's not too bad...
2025 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
2026 rxs->flag = rx_flag | RX_FLAG_TSFT;
2028 rxs->freq = sc->curchan->center_freq;
2029 rxs->band = sc->curband->band;
2031 rxs->signal = sc->ah->ah_noise_floor + rs.rs_rssi;
2033 rxs->antenna = rs.rs_antenna;
2035 if (rs.rs_antenna > 0 && rs.rs_antenna < 5)
2036 sc->stats.antenna_rx[rs.rs_antenna]++;
2038 sc->stats.antenna_rx[0]++; /* invalid */
2040 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
2041 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
2043 if (rxs->rate_idx >= 0 && rs.rs_rate ==
2044 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
2045 rxs->flag |= RX_FLAG_SHORTPRE;
2047 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
2049 ath5k_update_beacon_rssi(sc, skb, rs.rs_rssi);
2051 /* check beacons in IBSS mode */
2052 if (sc->opmode == NL80211_IFTYPE_ADHOC)
2053 ath5k_check_ibss_tsf(sc, skb, rxs);
2055 ieee80211_rx(sc->hw, skb);
2058 bf->skbaddr = next_skb_addr;
2060 list_move_tail(&bf->list, &sc->rxbuf);
2061 } while (ath5k_rxbuf_setup(sc, bf) == 0);
2063 spin_unlock(&sc->rxbuflock);
2074 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
2076 struct ath5k_tx_status ts = {};
2077 struct ath5k_buf *bf, *bf0;
2078 struct ath5k_desc *ds;
2079 struct sk_buff *skb;
2080 struct ieee80211_tx_info *info;
2083 spin_lock(&txq->lock);
2084 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
2088 * It's possible that the hardware can say the buffer is
2089 * completed when it hasn't yet loaded the ds_link from
2090 * host memory and moved on. If there are more TX
2091 * descriptors in the queue, wait for TXDP to change
2092 * before processing this one.
2094 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
2095 !list_is_last(&bf->list, &txq->q))
2098 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
2099 if (unlikely(ret == -EINPROGRESS))
2101 else if (unlikely(ret)) {
2102 ATH5K_ERR(sc, "error %d while processing queue %u\n",
2107 sc->stats.tx_all_count++;
2109 info = IEEE80211_SKB_CB(skb);
2112 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
2115 ieee80211_tx_info_clear_status(info);
2116 for (i = 0; i < 4; i++) {
2117 struct ieee80211_tx_rate *r =
2118 &info->status.rates[i];
2120 if (ts.ts_rate[i]) {
2121 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
2122 r->count = ts.ts_retry[i];
2129 /* count the successful attempt as well */
2130 info->status.rates[ts.ts_final_idx].count++;
2132 if (unlikely(ts.ts_status)) {
2133 sc->stats.ack_fail++;
2134 if (ts.ts_status & AR5K_TXERR_FILT) {
2135 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2136 sc->stats.txerr_filt++;
2138 if (ts.ts_status & AR5K_TXERR_XRETRY)
2139 sc->stats.txerr_retry++;
2140 if (ts.ts_status & AR5K_TXERR_FIFO)
2141 sc->stats.txerr_fifo++;
2143 info->flags |= IEEE80211_TX_STAT_ACK;
2144 info->status.ack_signal = ts.ts_rssi;
2148 * Remove MAC header padding before giving the frame
2151 ath5k_remove_padding(skb);
2153 if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
2154 sc->stats.antenna_tx[ts.ts_antenna]++;
2156 sc->stats.antenna_tx[0]++; /* invalid */
2158 ieee80211_tx_status(sc->hw, skb);
2160 spin_lock(&sc->txbuflock);
2161 list_move_tail(&bf->list, &sc->txbuf);
2163 spin_unlock(&sc->txbuflock);
2165 if (likely(list_empty(&txq->q)))
2167 spin_unlock(&txq->lock);
2168 if (sc->txbuf_len > ATH_TXBUF / 5)
2169 ieee80211_wake_queues(sc->hw);
2173 ath5k_tasklet_tx(unsigned long data)
2176 struct ath5k_softc *sc = (void *)data;
2178 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2179 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2180 ath5k_tx_processq(sc, &sc->txqs[i]);
2189 * Setup the beacon frame for transmit.
2192 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2194 struct sk_buff *skb = bf->skb;
2195 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2196 struct ath5k_hw *ah = sc->ah;
2197 struct ath5k_desc *ds;
2201 const int padsize = 0;
2203 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2205 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2206 "skbaddr %llx\n", skb, skb->data, skb->len,
2207 (unsigned long long)bf->skbaddr);
2208 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2209 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2214 antenna = ah->ah_tx_ant;
2216 flags = AR5K_TXDESC_NOACK;
2217 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2218 ds->ds_link = bf->daddr; /* self-linked */
2219 flags |= AR5K_TXDESC_VEOL;
2224 * If we use multiple antennas on AP and use
2225 * the Sectored AP scenario, switch antenna every
2226 * 4 beacons to make sure everybody hears our AP.
2227 * When a client tries to associate, hw will keep
2228 * track of the tx antenna to be used for this client
2229 * automaticaly, based on ACKed packets.
2231 * Note: AP still listens and transmits RTS on the
2232 * default antenna which is supposed to be an omni.
2234 * Note2: On sectored scenarios it's possible to have
2235 * multiple antennas (1omni -the default- and 14 sectors)
2236 * so if we choose to actually support this mode we need
2237 * to allow user to set how many antennas we have and tweak
2238 * the code below to send beacons on all of them.
2240 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2241 antenna = sc->bsent & 4 ? 2 : 1;
2244 /* FIXME: If we are in g mode and rate is a CCK rate
2245 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2246 * from tx power (value is in dB units already) */
2247 ds->ds_data = bf->skbaddr;
2248 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2249 ieee80211_get_hdrlen_from_skb(skb), padsize,
2250 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2251 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2252 1, AR5K_TXKEYIX_INVALID,
2253 antenna, flags, 0, 0);
2259 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2264 * Transmit a beacon frame at SWBA. Dynamic updates to the
2265 * frame contents are done as needed and the slot time is
2266 * also adjusted based on current state.
2268 * This is called from software irq context (beacontq or restq
2269 * tasklets) or user context from ath5k_beacon_config.
2272 ath5k_beacon_send(struct ath5k_softc *sc)
2274 struct ath5k_buf *bf = sc->bbuf;
2275 struct ath5k_hw *ah = sc->ah;
2276 struct sk_buff *skb;
2278 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2280 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2281 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2282 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2286 * Check if the previous beacon has gone out. If
2287 * not don't don't try to post another, skip this
2288 * period and wait for the next. Missed beacons
2289 * indicate a problem and should not occur. If we
2290 * miss too many consecutive beacons reset the device.
2292 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2294 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2295 "missed %u consecutive beacons\n", sc->bmisscount);
2296 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2297 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2298 "stuck beacon time (%u missed)\n",
2300 tasklet_schedule(&sc->restq);
2304 if (unlikely(sc->bmisscount != 0)) {
2305 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2306 "resume beacon xmit after %u misses\n",
2312 * Stop any current dma and put the new frame on the queue.
2313 * This should never fail since we check above that no frames
2314 * are still pending on the queue.
2316 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2317 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2318 /* NB: hw still stops DMA, so proceed */
2321 /* refresh the beacon for AP mode */
2322 if (sc->opmode == NL80211_IFTYPE_AP)
2323 ath5k_beacon_update(sc->hw, sc->vif);
2325 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2326 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2327 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2328 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2330 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2332 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2333 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2341 * ath5k_beacon_update_timers - update beacon timers
2343 * @sc: struct ath5k_softc pointer we are operating on
2344 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2345 * beacon timer update based on the current HW TSF.
2347 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2348 * of a received beacon or the current local hardware TSF and write it to the
2349 * beacon timer registers.
2351 * This is called in a variety of situations, e.g. when a beacon is received,
2352 * when a TSF update has been detected, but also when an new IBSS is created or
2353 * when we otherwise know we have to update the timers, but we keep it in this
2354 * function to have it all together in one place.
2357 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2359 struct ath5k_hw *ah = sc->ah;
2360 u32 nexttbtt, intval, hw_tu, bc_tu;
2363 intval = sc->bintval & AR5K_BEACON_PERIOD;
2364 if (WARN_ON(!intval))
2367 /* beacon TSF converted to TU */
2368 bc_tu = TSF_TO_TU(bc_tsf);
2370 /* current TSF converted to TU */
2371 hw_tsf = ath5k_hw_get_tsf64(ah);
2372 hw_tu = TSF_TO_TU(hw_tsf);
2375 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2378 * no beacons received, called internally.
2379 * just need to refresh timers based on HW TSF.
2381 nexttbtt = roundup(hw_tu + FUDGE, intval);
2382 } else if (bc_tsf == 0) {
2384 * no beacon received, probably called by ath5k_reset_tsf().
2385 * reset TSF to start with 0.
2388 intval |= AR5K_BEACON_RESET_TSF;
2389 } else if (bc_tsf > hw_tsf) {
2391 * beacon received, SW merge happend but HW TSF not yet updated.
2392 * not possible to reconfigure timers yet, but next time we
2393 * receive a beacon with the same BSSID, the hardware will
2394 * automatically update the TSF and then we need to reconfigure
2397 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2398 "need to wait for HW TSF sync\n");
2402 * most important case for beacon synchronization between STA.
2404 * beacon received and HW TSF has been already updated by HW.
2405 * update next TBTT based on the TSF of the beacon, but make
2406 * sure it is ahead of our local TSF timer.
2408 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2412 sc->nexttbtt = nexttbtt;
2414 intval |= AR5K_BEACON_ENA;
2415 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2418 * debugging output last in order to preserve the time critical aspect
2422 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2423 "reconfigured timers based on HW TSF\n");
2424 else if (bc_tsf == 0)
2425 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2426 "reset HW TSF and timers\n");
2428 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2429 "updated timers based on beacon TSF\n");
2431 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2432 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2433 (unsigned long long) bc_tsf,
2434 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2435 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2436 intval & AR5K_BEACON_PERIOD,
2437 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2438 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2443 * ath5k_beacon_config - Configure the beacon queues and interrupts
2445 * @sc: struct ath5k_softc pointer we are operating on
2447 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2448 * interrupts to detect TSF updates only.
2451 ath5k_beacon_config(struct ath5k_softc *sc)
2453 struct ath5k_hw *ah = sc->ah;
2454 unsigned long flags;
2456 spin_lock_irqsave(&sc->block, flags);
2458 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2460 if (sc->enable_beacon) {
2462 * In IBSS mode we use a self-linked tx descriptor and let the
2463 * hardware send the beacons automatically. We have to load it
2465 * We use the SWBA interrupt only to keep track of the beacon
2466 * timers in order to detect automatic TSF updates.
2468 ath5k_beaconq_config(sc);
2470 sc->imask |= AR5K_INT_SWBA;
2472 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2473 if (ath5k_hw_hasveol(ah))
2474 ath5k_beacon_send(sc);
2476 ath5k_beacon_update_timers(sc, -1);
2478 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2481 ath5k_hw_set_imr(ah, sc->imask);
2483 spin_unlock_irqrestore(&sc->block, flags);
2486 static void ath5k_tasklet_beacon(unsigned long data)
2488 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2491 * Software beacon alert--time to send a beacon.
2493 * In IBSS mode we use this interrupt just to
2494 * keep track of the next TBTT (target beacon
2495 * transmission time) in order to detect wether
2496 * automatic TSF updates happened.
2498 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2499 /* XXX: only if VEOL suppported */
2500 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2501 sc->nexttbtt += sc->bintval;
2502 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2503 "SWBA nexttbtt: %x hw_tu: %x "
2507 (unsigned long long) tsf);
2509 spin_lock(&sc->block);
2510 ath5k_beacon_send(sc);
2511 spin_unlock(&sc->block);
2516 /********************\
2517 * Interrupt handling *
2518 \********************/
2521 ath5k_init(struct ath5k_softc *sc)
2523 struct ath5k_hw *ah = sc->ah;
2526 mutex_lock(&sc->lock);
2528 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2531 * Stop anything previously setup. This is safe
2532 * no matter this is the first time through or not.
2534 ath5k_stop_locked(sc);
2537 * The basic interface to setting the hardware in a good
2538 * state is ``reset''. On return the hardware is known to
2539 * be powered up and with interrupts disabled. This must
2540 * be followed by initialization of the appropriate bits
2541 * and then setup of the interrupt mask.
2543 sc->curchan = sc->hw->conf.channel;
2544 sc->curband = &sc->sbands[sc->curchan->band];
2545 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2546 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2547 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2549 ret = ath5k_reset(sc, NULL);
2553 ath5k_rfkill_hw_start(ah);
2556 * Reset the key cache since some parts do not reset the
2557 * contents on initial power up or resume from suspend.
2559 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2560 ath5k_hw_reset_key(ah, i);
2562 ath5k_hw_set_ack_bitrate_high(ah, true);
2566 mutex_unlock(&sc->lock);
2571 ath5k_stop_locked(struct ath5k_softc *sc)
2573 struct ath5k_hw *ah = sc->ah;
2575 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2576 test_bit(ATH_STAT_INVALID, sc->status));
2579 * Shutdown the hardware and driver:
2580 * stop output from above
2581 * disable interrupts
2583 * turn off the radio
2584 * clear transmit machinery
2585 * clear receive machinery
2586 * drain and release tx queues
2587 * reclaim beacon resources
2588 * power down hardware
2590 * Note that some of this work is not possible if the
2591 * hardware is gone (invalid).
2593 ieee80211_stop_queues(sc->hw);
2595 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2597 ath5k_hw_set_imr(ah, 0);
2598 synchronize_irq(sc->pdev->irq);
2600 ath5k_txq_cleanup(sc);
2601 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2603 ath5k_hw_phy_disable(ah);
2611 * Stop the device, grabbing the top-level lock to protect
2612 * against concurrent entry through ath5k_init (which can happen
2613 * if another thread does a system call and the thread doing the
2614 * stop is preempted).
2617 ath5k_stop_hw(struct ath5k_softc *sc)
2621 mutex_lock(&sc->lock);
2622 ret = ath5k_stop_locked(sc);
2623 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2625 * Don't set the card in full sleep mode!
2627 * a) When the device is in this state it must be carefully
2628 * woken up or references to registers in the PCI clock
2629 * domain may freeze the bus (and system). This varies
2630 * by chip and is mostly an issue with newer parts
2631 * (madwifi sources mentioned srev >= 0x78) that go to
2632 * sleep more quickly.
2634 * b) On older chips full sleep results a weird behaviour
2635 * during wakeup. I tested various cards with srev < 0x78
2636 * and they don't wake up after module reload, a second
2637 * module reload is needed to bring the card up again.
2639 * Until we figure out what's going on don't enable
2640 * full chip reset on any chip (this is what Legacy HAL
2641 * and Sam's HAL do anyway). Instead Perform a full reset
2642 * on the device (same as initial state after attach) and
2643 * leave it idle (keep MAC/BB on warm reset) */
2644 ret = ath5k_hw_on_hold(sc->ah);
2646 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2647 "putting device to sleep\n");
2649 ath5k_txbuf_free(sc, sc->bbuf);
2652 mutex_unlock(&sc->lock);
2654 tasklet_kill(&sc->rxtq);
2655 tasklet_kill(&sc->txtq);
2656 tasklet_kill(&sc->restq);
2657 tasklet_kill(&sc->calib);
2658 tasklet_kill(&sc->beacontq);
2659 tasklet_kill(&sc->ani_tasklet);
2661 ath5k_rfkill_hw_stop(sc->ah);
2667 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2669 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2670 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2671 /* run ANI only when full calibration is not active */
2672 ah->ah_cal_next_ani = jiffies +
2673 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2674 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2676 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2677 ah->ah_cal_next_full = jiffies +
2678 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2679 tasklet_schedule(&ah->ah_sc->calib);
2681 /* we could use SWI to generate enough interrupts to meet our
2682 * calibration interval requirements, if necessary:
2683 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2687 ath5k_intr(int irq, void *dev_id)
2689 struct ath5k_softc *sc = dev_id;
2690 struct ath5k_hw *ah = sc->ah;
2691 enum ath5k_int status;
2692 unsigned int counter = 1000;
2694 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2695 !ath5k_hw_is_intr_pending(ah)))
2699 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2700 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2702 if (unlikely(status & AR5K_INT_FATAL)) {
2704 * Fatal errors are unrecoverable.
2705 * Typically these are caused by DMA errors.
2707 tasklet_schedule(&sc->restq);
2708 } else if (unlikely(status & AR5K_INT_RXORN)) {
2710 * Receive buffers are full. Either the bus is busy or
2711 * the CPU is not fast enough to process all received
2713 * Older chipsets need a reset to come out of this
2714 * condition, but we treat it as RX for newer chips.
2715 * We don't know exactly which versions need a reset -
2716 * this guess is copied from the HAL.
2718 sc->stats.rxorn_intr++;
2719 if (ah->ah_mac_srev < AR5K_SREV_AR5212)
2720 tasklet_schedule(&sc->restq);
2722 tasklet_schedule(&sc->rxtq);
2724 if (status & AR5K_INT_SWBA) {
2725 tasklet_hi_schedule(&sc->beacontq);
2727 if (status & AR5K_INT_RXEOL) {
2729 * NB: the hardware should re-read the link when
2730 * RXE bit is written, but it doesn't work at
2731 * least on older hardware revs.
2735 if (status & AR5K_INT_TXURN) {
2736 /* bump tx trigger level */
2737 ath5k_hw_update_tx_triglevel(ah, true);
2739 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2740 tasklet_schedule(&sc->rxtq);
2741 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2742 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2743 tasklet_schedule(&sc->txtq);
2744 if (status & AR5K_INT_BMISS) {
2747 if (status & AR5K_INT_MIB) {
2748 sc->stats.mib_intr++;
2749 ath5k_hw_update_mib_counters(ah);
2750 ath5k_ani_mib_intr(ah);
2752 if (status & AR5K_INT_GPIO)
2753 tasklet_schedule(&sc->rf_kill.toggleq);
2756 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2758 if (unlikely(!counter))
2759 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2761 ath5k_intr_calibration_poll(ah);
2767 ath5k_tasklet_reset(unsigned long data)
2769 struct ath5k_softc *sc = (void *)data;
2771 ath5k_reset_wake(sc);
2775 * Periodically recalibrate the PHY to account
2776 * for temperature/environment changes.
2779 ath5k_tasklet_calibrate(unsigned long data)
2781 struct ath5k_softc *sc = (void *)data;
2782 struct ath5k_hw *ah = sc->ah;
2784 /* Only full calibration for now */
2785 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2787 /* Stop queues so that calibration
2788 * doesn't interfere with tx */
2789 ieee80211_stop_queues(sc->hw);
2791 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2792 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2793 sc->curchan->hw_value);
2795 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2797 * Rfgain is out of bounds, reset the chip
2798 * to load new gain values.
2800 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2801 ath5k_reset(sc, sc->curchan);
2803 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2804 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2805 ieee80211_frequency_to_channel(
2806 sc->curchan->center_freq));
2809 ieee80211_wake_queues(sc->hw);
2811 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2816 ath5k_tasklet_ani(unsigned long data)
2818 struct ath5k_softc *sc = (void *)data;
2819 struct ath5k_hw *ah = sc->ah;
2821 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2822 ath5k_ani_calibration(ah);
2823 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2827 /********************\
2828 * Mac80211 functions *
2829 \********************/
2832 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2834 struct ath5k_softc *sc = hw->priv;
2836 return ath5k_tx_queue(hw, skb, sc->txq);
2839 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2840 struct ath5k_txq *txq)
2842 struct ath5k_softc *sc = hw->priv;
2843 struct ath5k_buf *bf;
2844 unsigned long flags;
2847 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2849 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2850 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2853 * the hardware expects the header padded to 4 byte boundaries
2854 * if this is not the case we add the padding after the header
2856 padsize = ath5k_add_padding(skb);
2858 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
2859 " headroom to pad");
2863 spin_lock_irqsave(&sc->txbuflock, flags);
2864 if (list_empty(&sc->txbuf)) {
2865 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2866 spin_unlock_irqrestore(&sc->txbuflock, flags);
2867 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2870 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2871 list_del(&bf->list);
2873 if (list_empty(&sc->txbuf))
2874 ieee80211_stop_queues(hw);
2875 spin_unlock_irqrestore(&sc->txbuflock, flags);
2879 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
2881 spin_lock_irqsave(&sc->txbuflock, flags);
2882 list_add_tail(&bf->list, &sc->txbuf);
2884 spin_unlock_irqrestore(&sc->txbuflock, flags);
2887 return NETDEV_TX_OK;
2890 dev_kfree_skb_any(skb);
2891 return NETDEV_TX_OK;
2895 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2896 * and change to the given channel.
2899 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2901 struct ath5k_hw *ah = sc->ah;
2904 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2907 ath5k_hw_set_imr(ah, 0);
2908 ath5k_txq_cleanup(sc);
2912 sc->curband = &sc->sbands[chan->band];
2914 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2916 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2920 ret = ath5k_rx_start(sc);
2922 ATH5K_ERR(sc, "can't start recv logic\n");
2926 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2929 * Change channels and update the h/w rate map if we're switching;
2930 * e.g. 11a to 11b/g.
2932 * We may be doing a reset in response to an ioctl that changes the
2933 * channel so update any state that might change as a result.
2937 /* ath5k_chan_change(sc, c); */
2939 ath5k_beacon_config(sc);
2940 /* intrs are enabled by ath5k_beacon_config */
2948 ath5k_reset_wake(struct ath5k_softc *sc)
2952 ret = ath5k_reset(sc, sc->curchan);
2954 ieee80211_wake_queues(sc->hw);
2959 static int ath5k_start(struct ieee80211_hw *hw)
2961 return ath5k_init(hw->priv);
2964 static void ath5k_stop(struct ieee80211_hw *hw)
2966 ath5k_stop_hw(hw->priv);
2969 static int ath5k_add_interface(struct ieee80211_hw *hw,
2970 struct ieee80211_vif *vif)
2972 struct ath5k_softc *sc = hw->priv;
2975 mutex_lock(&sc->lock);
2983 switch (vif->type) {
2984 case NL80211_IFTYPE_AP:
2985 case NL80211_IFTYPE_STATION:
2986 case NL80211_IFTYPE_ADHOC:
2987 case NL80211_IFTYPE_MESH_POINT:
2988 case NL80211_IFTYPE_MONITOR:
2989 sc->opmode = vif->type;
2996 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
2998 ath5k_hw_set_lladdr(sc->ah, vif->addr);
2999 ath5k_mode_setup(sc);
3003 mutex_unlock(&sc->lock);
3008 ath5k_remove_interface(struct ieee80211_hw *hw,
3009 struct ieee80211_vif *vif)
3011 struct ath5k_softc *sc = hw->priv;
3012 u8 mac[ETH_ALEN] = {};
3014 mutex_lock(&sc->lock);
3018 ath5k_hw_set_lladdr(sc->ah, mac);
3021 mutex_unlock(&sc->lock);
3025 * TODO: Phy disable/diversity etc
3028 ath5k_config(struct ieee80211_hw *hw, u32 changed)
3030 struct ath5k_softc *sc = hw->priv;
3031 struct ath5k_hw *ah = sc->ah;
3032 struct ieee80211_conf *conf = &hw->conf;
3035 mutex_lock(&sc->lock);
3037 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3038 ret = ath5k_chan_set(sc, conf->channel);
3043 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
3044 (sc->power_level != conf->power_level)) {
3045 sc->power_level = conf->power_level;
3048 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
3052 * 1) Move this on config_interface and handle each case
3053 * separately eg. when we have only one STA vif, use
3054 * AR5K_ANTMODE_SINGLE_AP
3056 * 2) Allow the user to change antenna mode eg. when only
3057 * one antenna is present
3059 * 3) Allow the user to set default/tx antenna when possible
3061 * 4) Default mode should handle 90% of the cases, together
3062 * with fixed a/b and single AP modes we should be able to
3063 * handle 99%. Sectored modes are extreme cases and i still
3064 * haven't found a usage for them. If we decide to support them,
3065 * then we must allow the user to set how many tx antennas we
3068 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
3071 mutex_unlock(&sc->lock);
3075 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
3076 int mc_count, struct dev_addr_list *mclist)
3085 for (i = 0; i < mc_count; i++) {
3088 /* calculate XOR of eight 6-bit values */
3089 val = get_unaligned_le32(mclist->dmi_addr + 0);
3090 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3091 val = get_unaligned_le32(mclist->dmi_addr + 3);
3092 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3094 mfilt[pos / 32] |= (1 << (pos % 32));
3095 /* XXX: we might be able to just do this instead,
3096 * but not sure, needs testing, if we do use this we'd
3097 * neet to inform below to not reset the mcast */
3098 /* ath5k_hw_set_mcast_filterindex(ah,
3099 * mclist->dmi_addr[5]); */
3100 mclist = mclist->next;
3103 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3106 #define SUPPORTED_FIF_FLAGS \
3107 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3108 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3109 FIF_BCN_PRBRESP_PROMISC
3111 * o always accept unicast, broadcast, and multicast traffic
3112 * o multicast traffic for all BSSIDs will be enabled if mac80211
3114 * o maintain current state of phy ofdm or phy cck error reception.
3115 * If the hardware detects any of these type of errors then
3116 * ath5k_hw_get_rx_filter() will pass to us the respective
3117 * hardware filters to be able to receive these type of frames.
3118 * o probe request frames are accepted only when operating in
3119 * hostap, adhoc, or monitor modes
3120 * o enable promiscuous mode according to the interface state
3122 * - when operating in adhoc mode so the 802.11 layer creates
3123 * node table entries for peers,
3124 * - when operating in station mode for collecting rssi data when
3125 * the station is otherwise quiet, or
3128 static void ath5k_configure_filter(struct ieee80211_hw *hw,
3129 unsigned int changed_flags,
3130 unsigned int *new_flags,
3133 struct ath5k_softc *sc = hw->priv;
3134 struct ath5k_hw *ah = sc->ah;
3135 u32 mfilt[2], rfilt;
3137 mutex_lock(&sc->lock);
3139 mfilt[0] = multicast;
3140 mfilt[1] = multicast >> 32;
3142 /* Only deal with supported flags */
3143 changed_flags &= SUPPORTED_FIF_FLAGS;
3144 *new_flags &= SUPPORTED_FIF_FLAGS;
3146 /* If HW detects any phy or radar errors, leave those filters on.
3147 * Also, always enable Unicast, Broadcasts and Multicast
3148 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3149 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3150 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3151 AR5K_RX_FILTER_MCAST);
3153 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3154 if (*new_flags & FIF_PROMISC_IN_BSS) {
3155 rfilt |= AR5K_RX_FILTER_PROM;
3156 __set_bit(ATH_STAT_PROMISC, sc->status);
3158 __clear_bit(ATH_STAT_PROMISC, sc->status);
3162 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3163 if (*new_flags & FIF_ALLMULTI) {
3168 /* This is the best we can do */
3169 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3170 rfilt |= AR5K_RX_FILTER_PHYERR;
3172 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3173 * and probes for any BSSID, this needs testing */
3174 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3175 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3177 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3178 * set we should only pass on control frames for this
3179 * station. This needs testing. I believe right now this
3180 * enables *all* control frames, which is OK.. but
3181 * but we should see if we can improve on granularity */
3182 if (*new_flags & FIF_CONTROL)
3183 rfilt |= AR5K_RX_FILTER_CONTROL;
3185 /* Additional settings per mode -- this is per ath5k */
3187 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3189 switch (sc->opmode) {
3190 case NL80211_IFTYPE_MESH_POINT:
3191 case NL80211_IFTYPE_MONITOR:
3192 rfilt |= AR5K_RX_FILTER_CONTROL |
3193 AR5K_RX_FILTER_BEACON |
3194 AR5K_RX_FILTER_PROBEREQ |
3195 AR5K_RX_FILTER_PROM;
3197 case NL80211_IFTYPE_AP:
3198 case NL80211_IFTYPE_ADHOC:
3199 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3200 AR5K_RX_FILTER_BEACON;
3202 case NL80211_IFTYPE_STATION:
3204 rfilt |= AR5K_RX_FILTER_BEACON;
3210 ath5k_hw_set_rx_filter(ah, rfilt);
3212 /* Set multicast bits */
3213 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3214 /* Set the cached hw filter flags, this will alter actually
3216 sc->filter_flags = rfilt;
3218 mutex_unlock(&sc->lock);
3222 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3223 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3224 struct ieee80211_key_conf *key)
3226 struct ath5k_softc *sc = hw->priv;
3227 struct ath5k_hw *ah = sc->ah;
3228 struct ath_common *common = ath5k_hw_common(ah);
3231 if (modparam_nohwcrypt)
3234 if (sc->opmode == NL80211_IFTYPE_AP)
3242 if (sc->ah->ah_aes_support)
3251 mutex_lock(&sc->lock);
3255 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3256 sta ? sta->addr : NULL);
3258 ATH5K_ERR(sc, "can't set the key\n");
3261 __set_bit(key->keyidx, common->keymap);
3262 key->hw_key_idx = key->keyidx;
3263 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3264 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3267 ath5k_hw_reset_key(sc->ah, key->keyidx);
3268 __clear_bit(key->keyidx, common->keymap);
3277 mutex_unlock(&sc->lock);
3282 ath5k_get_stats(struct ieee80211_hw *hw,
3283 struct ieee80211_low_level_stats *stats)
3285 struct ath5k_softc *sc = hw->priv;
3288 ath5k_hw_update_mib_counters(sc->ah);
3290 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3291 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3292 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3293 stats->dot11FCSErrorCount = sc->stats.fcs_error;
3298 static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3299 struct survey_info *survey)
3301 struct ath5k_softc *sc = hw->priv;
3302 struct ieee80211_conf *conf = &hw->conf;
3307 survey->channel = conf->channel;
3308 survey->filled = SURVEY_INFO_NOISE_DBM;
3309 survey->noise = sc->ah->ah_noise_floor;
3315 ath5k_get_tsf(struct ieee80211_hw *hw)
3317 struct ath5k_softc *sc = hw->priv;
3319 return ath5k_hw_get_tsf64(sc->ah);
3323 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3325 struct ath5k_softc *sc = hw->priv;
3327 ath5k_hw_set_tsf64(sc->ah, tsf);
3331 ath5k_reset_tsf(struct ieee80211_hw *hw)
3333 struct ath5k_softc *sc = hw->priv;
3336 * in IBSS mode we need to update the beacon timers too.
3337 * this will also reset the TSF if we call it with 0
3339 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3340 ath5k_beacon_update_timers(sc, 0);
3342 ath5k_hw_reset_tsf(sc->ah);
3346 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3347 * this is called only once at config_bss time, for AP we do it every
3348 * SWBA interrupt so that the TIM will reflect buffered frames.
3350 * Called with the beacon lock.
3353 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3356 struct ath5k_softc *sc = hw->priv;
3357 struct sk_buff *skb;
3359 if (WARN_ON(!vif)) {
3364 skb = ieee80211_beacon_get(hw, vif);
3371 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3373 ath5k_txbuf_free(sc, sc->bbuf);
3374 sc->bbuf->skb = skb;
3375 ret = ath5k_beacon_setup(sc, sc->bbuf);
3377 sc->bbuf->skb = NULL;
3383 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3385 struct ath5k_softc *sc = hw->priv;
3386 struct ath5k_hw *ah = sc->ah;
3388 rfilt = ath5k_hw_get_rx_filter(ah);
3390 rfilt |= AR5K_RX_FILTER_BEACON;
3392 rfilt &= ~AR5K_RX_FILTER_BEACON;
3393 ath5k_hw_set_rx_filter(ah, rfilt);
3394 sc->filter_flags = rfilt;
3397 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3398 struct ieee80211_vif *vif,
3399 struct ieee80211_bss_conf *bss_conf,
3402 struct ath5k_softc *sc = hw->priv;
3403 struct ath5k_hw *ah = sc->ah;
3404 struct ath_common *common = ath5k_hw_common(ah);
3405 unsigned long flags;
3407 mutex_lock(&sc->lock);
3408 if (WARN_ON(sc->vif != vif))
3411 if (changes & BSS_CHANGED_BSSID) {
3412 /* Cache for later use during resets */
3413 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3415 ath5k_hw_set_associd(ah);
3419 if (changes & BSS_CHANGED_BEACON_INT)
3420 sc->bintval = bss_conf->beacon_int;
3422 if (changes & BSS_CHANGED_ASSOC) {
3423 sc->assoc = bss_conf->assoc;
3424 if (sc->opmode == NL80211_IFTYPE_STATION)
3425 set_beacon_filter(hw, sc->assoc);
3426 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3427 AR5K_LED_ASSOC : AR5K_LED_INIT);
3428 if (bss_conf->assoc) {
3429 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3430 "Bss Info ASSOC %d, bssid: %pM\n",
3431 bss_conf->aid, common->curbssid);
3432 common->curaid = bss_conf->aid;
3433 ath5k_hw_set_associd(ah);
3434 /* Once ANI is available you would start it here */
3438 if (changes & BSS_CHANGED_BEACON) {
3439 spin_lock_irqsave(&sc->block, flags);
3440 ath5k_beacon_update(hw, vif);
3441 spin_unlock_irqrestore(&sc->block, flags);
3444 if (changes & BSS_CHANGED_BEACON_ENABLED)
3445 sc->enable_beacon = bss_conf->enable_beacon;
3447 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3448 BSS_CHANGED_BEACON_INT))
3449 ath5k_beacon_config(sc);
3452 mutex_unlock(&sc->lock);
3455 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3457 struct ath5k_softc *sc = hw->priv;
3459 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3462 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3464 struct ath5k_softc *sc = hw->priv;
3465 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3466 AR5K_LED_ASSOC : AR5K_LED_INIT);
3470 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3472 * @hw: struct ieee80211_hw pointer
3473 * @coverage_class: IEEE 802.11 coverage class number
3475 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3476 * coverage class. The values are persistent, they are restored after device
3479 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3481 struct ath5k_softc *sc = hw->priv;
3483 mutex_lock(&sc->lock);
3484 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3485 mutex_unlock(&sc->lock);
git.openpandora.org / pandora-kernel.git / blob