6f97b7bbcbf13a29b9f2c567eb317a12ec51609c
[pandora-kernel.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2010 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
39 #include <linux/ip.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
45
46 #include <net/checksum.h>
47 #include <net/ip.h>
48
49 #include <asm/system.h>
50 #include <asm/io.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
53
54 #ifdef CONFIG_SPARC
55 #include <asm/idprom.h>
56 #include <asm/prom.h>
57 #endif
58
59 #define BAR_0   0
60 #define BAR_2   2
61
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
64 #else
65 #define TG3_VLAN_TAG_USED 0
66 #endif
67
68 #include "tg3.h"
69
70 #define DRV_MODULE_NAME         "tg3"
71 #define TG3_MAJ_NUM                     3
72 #define TG3_MIN_NUM                     115
73 #define DRV_MODULE_VERSION      \
74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE      "October 14, 2010"
76
77 #define TG3_DEF_MAC_MODE        0
78 #define TG3_DEF_RX_MODE         0
79 #define TG3_DEF_TX_MODE         0
80 #define TG3_DEF_MSG_ENABLE        \
81         (NETIF_MSG_DRV          | \
82          NETIF_MSG_PROBE        | \
83          NETIF_MSG_LINK         | \
84          NETIF_MSG_TIMER        | \
85          NETIF_MSG_IFDOWN       | \
86          NETIF_MSG_IFUP         | \
87          NETIF_MSG_RX_ERR       | \
88          NETIF_MSG_TX_ERR)
89
90 /* length of time before we decide the hardware is borked,
91  * and dev->tx_timeout() should be called to fix the problem
92  */
93 #define TG3_TX_TIMEOUT                  (5 * HZ)
94
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU                     60
97 #define TG3_MAX_MTU(tp) \
98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
99
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101  * You can't change the ring sizes, but you can change where you place
102  * them in the NIC onboard memory.
103  */
104 #define TG3_RX_STD_RING_SIZE(tp) \
105         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
106           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
107          RX_STD_MAX_SIZE_5717 : 512)
108 #define TG3_DEF_RX_RING_PENDING         200
109 #define TG3_RX_JMB_RING_SIZE(tp) \
110         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
111           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
112          1024 : 256)
113 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
114 #define TG3_RSS_INDIR_TBL_SIZE          128
115
116 /* Do not place this n-ring entries value into the tp struct itself,
117  * we really want to expose these constants to GCC so that modulo et
118  * al.  operations are done with shifts and masks instead of with
119  * hw multiply/modulo instructions.  Another solution would be to
120  * replace things like '% foo' with '& (foo - 1)'.
121  */
122
123 #define TG3_TX_RING_SIZE                512
124 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
125
126 #define TG3_RX_STD_RING_BYTES(tp) \
127         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
128 #define TG3_RX_JMB_RING_BYTES(tp) \
129         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
130 #define TG3_RX_RCB_RING_BYTES(tp) \
131         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
132 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
133                                  TG3_TX_RING_SIZE)
134 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
135
136 #define TG3_RX_DMA_ALIGN                16
137 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
138
139 #define TG3_DMA_BYTE_ENAB               64
140
141 #define TG3_RX_STD_DMA_SZ               1536
142 #define TG3_RX_JMB_DMA_SZ               9046
143
144 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
145
146 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
147 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
148
149 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
150         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
151
152 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
153         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
154
155 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
156  * that are at least dword aligned when used in PCIX mode.  The driver
157  * works around this bug by double copying the packet.  This workaround
158  * is built into the normal double copy length check for efficiency.
159  *
160  * However, the double copy is only necessary on those architectures
161  * where unaligned memory accesses are inefficient.  For those architectures
162  * where unaligned memory accesses incur little penalty, we can reintegrate
163  * the 5701 in the normal rx path.  Doing so saves a device structure
164  * dereference by hardcoding the double copy threshold in place.
165  */
166 #define TG3_RX_COPY_THRESHOLD           256
167 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
168         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
169 #else
170         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
171 #endif
172
173 /* minimum number of free TX descriptors required to wake up TX process */
174 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
175
176 #define TG3_RAW_IP_ALIGN 2
177
178 /* number of ETHTOOL_GSTATS u64's */
179 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
180
181 #define TG3_NUM_TEST            6
182
183 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
184
185 #define FIRMWARE_TG3            "tigon/tg3.bin"
186 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
187 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
188
189 static char version[] __devinitdata =
190         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
191
192 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
193 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
194 MODULE_LICENSE("GPL");
195 MODULE_VERSION(DRV_MODULE_VERSION);
196 MODULE_FIRMWARE(FIRMWARE_TG3);
197 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
198 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
199
200 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
201 module_param(tg3_debug, int, 0);
202 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
203
204 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
277         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
278         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
281         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
282         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
283         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
284         {}
285 };
286
287 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
288
289 static const struct {
290         const char string[ETH_GSTRING_LEN];
291 } ethtool_stats_keys[TG3_NUM_STATS] = {
292         { "rx_octets" },
293         { "rx_fragments" },
294         { "rx_ucast_packets" },
295         { "rx_mcast_packets" },
296         { "rx_bcast_packets" },
297         { "rx_fcs_errors" },
298         { "rx_align_errors" },
299         { "rx_xon_pause_rcvd" },
300         { "rx_xoff_pause_rcvd" },
301         { "rx_mac_ctrl_rcvd" },
302         { "rx_xoff_entered" },
303         { "rx_frame_too_long_errors" },
304         { "rx_jabbers" },
305         { "rx_undersize_packets" },
306         { "rx_in_length_errors" },
307         { "rx_out_length_errors" },
308         { "rx_64_or_less_octet_packets" },
309         { "rx_65_to_127_octet_packets" },
310         { "rx_128_to_255_octet_packets" },
311         { "rx_256_to_511_octet_packets" },
312         { "rx_512_to_1023_octet_packets" },
313         { "rx_1024_to_1522_octet_packets" },
314         { "rx_1523_to_2047_octet_packets" },
315         { "rx_2048_to_4095_octet_packets" },
316         { "rx_4096_to_8191_octet_packets" },
317         { "rx_8192_to_9022_octet_packets" },
318
319         { "tx_octets" },
320         { "tx_collisions" },
321
322         { "tx_xon_sent" },
323         { "tx_xoff_sent" },
324         { "tx_flow_control" },
325         { "tx_mac_errors" },
326         { "tx_single_collisions" },
327         { "tx_mult_collisions" },
328         { "tx_deferred" },
329         { "tx_excessive_collisions" },
330         { "tx_late_collisions" },
331         { "tx_collide_2times" },
332         { "tx_collide_3times" },
333         { "tx_collide_4times" },
334         { "tx_collide_5times" },
335         { "tx_collide_6times" },
336         { "tx_collide_7times" },
337         { "tx_collide_8times" },
338         { "tx_collide_9times" },
339         { "tx_collide_10times" },
340         { "tx_collide_11times" },
341         { "tx_collide_12times" },
342         { "tx_collide_13times" },
343         { "tx_collide_14times" },
344         { "tx_collide_15times" },
345         { "tx_ucast_packets" },
346         { "tx_mcast_packets" },
347         { "tx_bcast_packets" },
348         { "tx_carrier_sense_errors" },
349         { "tx_discards" },
350         { "tx_errors" },
351
352         { "dma_writeq_full" },
353         { "dma_write_prioq_full" },
354         { "rxbds_empty" },
355         { "rx_discards" },
356         { "rx_errors" },
357         { "rx_threshold_hit" },
358
359         { "dma_readq_full" },
360         { "dma_read_prioq_full" },
361         { "tx_comp_queue_full" },
362
363         { "ring_set_send_prod_index" },
364         { "ring_status_update" },
365         { "nic_irqs" },
366         { "nic_avoided_irqs" },
367         { "nic_tx_threshold_hit" }
368 };
369
370 static const struct {
371         const char string[ETH_GSTRING_LEN];
372 } ethtool_test_keys[TG3_NUM_TEST] = {
373         { "nvram test     (online) " },
374         { "link test      (online) " },
375         { "register test  (offline)" },
376         { "memory test    (offline)" },
377         { "loopback test  (offline)" },
378         { "interrupt test (offline)" },
379 };
380
381 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
382 {
383         writel(val, tp->regs + off);
384 }
385
386 static u32 tg3_read32(struct tg3 *tp, u32 off)
387 {
388         return readl(tp->regs + off);
389 }
390
391 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
392 {
393         writel(val, tp->aperegs + off);
394 }
395
396 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
397 {
398         return readl(tp->aperegs + off);
399 }
400
401 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
402 {
403         unsigned long flags;
404
405         spin_lock_irqsave(&tp->indirect_lock, flags);
406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
409 }
410
411 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
412 {
413         writel(val, tp->regs + off);
414         readl(tp->regs + off);
415 }
416
417 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
418 {
419         unsigned long flags;
420         u32 val;
421
422         spin_lock_irqsave(&tp->indirect_lock, flags);
423         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
424         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
425         spin_unlock_irqrestore(&tp->indirect_lock, flags);
426         return val;
427 }
428
429 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
430 {
431         unsigned long flags;
432
433         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
434                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
435                                        TG3_64BIT_REG_LOW, val);
436                 return;
437         }
438         if (off == TG3_RX_STD_PROD_IDX_REG) {
439                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
440                                        TG3_64BIT_REG_LOW, val);
441                 return;
442         }
443
444         spin_lock_irqsave(&tp->indirect_lock, flags);
445         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
446         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
447         spin_unlock_irqrestore(&tp->indirect_lock, flags);
448
449         /* In indirect mode when disabling interrupts, we also need
450          * to clear the interrupt bit in the GRC local ctrl register.
451          */
452         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
453             (val == 0x1)) {
454                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
455                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
456         }
457 }
458
459 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
460 {
461         unsigned long flags;
462         u32 val;
463
464         spin_lock_irqsave(&tp->indirect_lock, flags);
465         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
466         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
467         spin_unlock_irqrestore(&tp->indirect_lock, flags);
468         return val;
469 }
470
471 /* usec_wait specifies the wait time in usec when writing to certain registers
472  * where it is unsafe to read back the register without some delay.
473  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
474  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
475  */
476 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
477 {
478         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
479             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
480                 /* Non-posted methods */
481                 tp->write32(tp, off, val);
482         else {
483                 /* Posted method */
484                 tg3_write32(tp, off, val);
485                 if (usec_wait)
486                         udelay(usec_wait);
487                 tp->read32(tp, off);
488         }
489         /* Wait again after the read for the posted method to guarantee that
490          * the wait time is met.
491          */
492         if (usec_wait)
493                 udelay(usec_wait);
494 }
495
496 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
497 {
498         tp->write32_mbox(tp, off, val);
499         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
500             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
501                 tp->read32_mbox(tp, off);
502 }
503
504 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
505 {
506         void __iomem *mbox = tp->regs + off;
507         writel(val, mbox);
508         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
509                 writel(val, mbox);
510         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
511                 readl(mbox);
512 }
513
514 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
515 {
516         return readl(tp->regs + off + GRCMBOX_BASE);
517 }
518
519 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
520 {
521         writel(val, tp->regs + off + GRCMBOX_BASE);
522 }
523
524 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
525 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
526 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
527 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
528 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
529
530 #define tw32(reg, val)                  tp->write32(tp, reg, val)
531 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
532 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
533 #define tr32(reg)                       tp->read32(tp, reg)
534
535 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
536 {
537         unsigned long flags;
538
539         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
540             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
541                 return;
542
543         spin_lock_irqsave(&tp->indirect_lock, flags);
544         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
545                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
547
548                 /* Always leave this as zero. */
549                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
550         } else {
551                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
552                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
553
554                 /* Always leave this as zero. */
555                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
556         }
557         spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 }
559
560 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
561 {
562         unsigned long flags;
563
564         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
565             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
566                 *val = 0;
567                 return;
568         }
569
570         spin_lock_irqsave(&tp->indirect_lock, flags);
571         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
572                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
573                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
574
575                 /* Always leave this as zero. */
576                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
577         } else {
578                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
579                 *val = tr32(TG3PCI_MEM_WIN_DATA);
580
581                 /* Always leave this as zero. */
582                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
583         }
584         spin_unlock_irqrestore(&tp->indirect_lock, flags);
585 }
586
587 static void tg3_ape_lock_init(struct tg3 *tp)
588 {
589         int i;
590         u32 regbase;
591
592         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
593                 regbase = TG3_APE_LOCK_GRANT;
594         else
595                 regbase = TG3_APE_PER_LOCK_GRANT;
596
597         /* Make sure the driver hasn't any stale locks. */
598         for (i = 0; i < 8; i++)
599                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
600 }
601
602 static int tg3_ape_lock(struct tg3 *tp, int locknum)
603 {
604         int i, off;
605         int ret = 0;
606         u32 status, req, gnt;
607
608         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
609                 return 0;
610
611         switch (locknum) {
612         case TG3_APE_LOCK_GRC:
613         case TG3_APE_LOCK_MEM:
614                 break;
615         default:
616                 return -EINVAL;
617         }
618
619         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
620                 req = TG3_APE_LOCK_REQ;
621                 gnt = TG3_APE_LOCK_GRANT;
622         } else {
623                 req = TG3_APE_PER_LOCK_REQ;
624                 gnt = TG3_APE_PER_LOCK_GRANT;
625         }
626
627         off = 4 * locknum;
628
629         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
630
631         /* Wait for up to 1 millisecond to acquire lock. */
632         for (i = 0; i < 100; i++) {
633                 status = tg3_ape_read32(tp, gnt + off);
634                 if (status == APE_LOCK_GRANT_DRIVER)
635                         break;
636                 udelay(10);
637         }
638
639         if (status != APE_LOCK_GRANT_DRIVER) {
640                 /* Revoke the lock request. */
641                 tg3_ape_write32(tp, gnt + off,
642                                 APE_LOCK_GRANT_DRIVER);
643
644                 ret = -EBUSY;
645         }
646
647         return ret;
648 }
649
650 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
651 {
652         u32 gnt;
653
654         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
655                 return;
656
657         switch (locknum) {
658         case TG3_APE_LOCK_GRC:
659         case TG3_APE_LOCK_MEM:
660                 break;
661         default:
662                 return;
663         }
664
665         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
666                 gnt = TG3_APE_LOCK_GRANT;
667         else
668                 gnt = TG3_APE_PER_LOCK_GRANT;
669
670         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
671 }
672
673 static void tg3_disable_ints(struct tg3 *tp)
674 {
675         int i;
676
677         tw32(TG3PCI_MISC_HOST_CTRL,
678              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
679         for (i = 0; i < tp->irq_max; i++)
680                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
681 }
682
683 static void tg3_enable_ints(struct tg3 *tp)
684 {
685         int i;
686
687         tp->irq_sync = 0;
688         wmb();
689
690         tw32(TG3PCI_MISC_HOST_CTRL,
691              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
692
693         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
694         for (i = 0; i < tp->irq_cnt; i++) {
695                 struct tg3_napi *tnapi = &tp->napi[i];
696
697                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
698                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
699                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
700
701                 tp->coal_now |= tnapi->coal_now;
702         }
703
704         /* Force an initial interrupt */
705         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
706             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
707                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
708         else
709                 tw32(HOSTCC_MODE, tp->coal_now);
710
711         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
712 }
713
714 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
715 {
716         struct tg3 *tp = tnapi->tp;
717         struct tg3_hw_status *sblk = tnapi->hw_status;
718         unsigned int work_exists = 0;
719
720         /* check for phy events */
721         if (!(tp->tg3_flags &
722               (TG3_FLAG_USE_LINKCHG_REG |
723                TG3_FLAG_POLL_SERDES))) {
724                 if (sblk->status & SD_STATUS_LINK_CHG)
725                         work_exists = 1;
726         }
727         /* check for RX/TX work to do */
728         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
729             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
730                 work_exists = 1;
731
732         return work_exists;
733 }
734
735 /* tg3_int_reenable
736  *  similar to tg3_enable_ints, but it accurately determines whether there
737  *  is new work pending and can return without flushing the PIO write
738  *  which reenables interrupts
739  */
740 static void tg3_int_reenable(struct tg3_napi *tnapi)
741 {
742         struct tg3 *tp = tnapi->tp;
743
744         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
745         mmiowb();
746
747         /* When doing tagged status, this work check is unnecessary.
748          * The last_tag we write above tells the chip which piece of
749          * work we've completed.
750          */
751         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
752             tg3_has_work(tnapi))
753                 tw32(HOSTCC_MODE, tp->coalesce_mode |
754                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
755 }
756
757 static void tg3_switch_clocks(struct tg3 *tp)
758 {
759         u32 clock_ctrl;
760         u32 orig_clock_ctrl;
761
762         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
763             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
764                 return;
765
766         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
767
768         orig_clock_ctrl = clock_ctrl;
769         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
770                        CLOCK_CTRL_CLKRUN_OENABLE |
771                        0x1f);
772         tp->pci_clock_ctrl = clock_ctrl;
773
774         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
775                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
776                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
777                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
778                 }
779         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
780                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
781                             clock_ctrl |
782                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
783                             40);
784                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
785                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
786                             40);
787         }
788         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
789 }
790
791 #define PHY_BUSY_LOOPS  5000
792
793 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
794 {
795         u32 frame_val;
796         unsigned int loops;
797         int ret;
798
799         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800                 tw32_f(MAC_MI_MODE,
801                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
802                 udelay(80);
803         }
804
805         *val = 0x0;
806
807         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
808                       MI_COM_PHY_ADDR_MASK);
809         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
810                       MI_COM_REG_ADDR_MASK);
811         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
812
813         tw32_f(MAC_MI_COM, frame_val);
814
815         loops = PHY_BUSY_LOOPS;
816         while (loops != 0) {
817                 udelay(10);
818                 frame_val = tr32(MAC_MI_COM);
819
820                 if ((frame_val & MI_COM_BUSY) == 0) {
821                         udelay(5);
822                         frame_val = tr32(MAC_MI_COM);
823                         break;
824                 }
825                 loops -= 1;
826         }
827
828         ret = -EBUSY;
829         if (loops != 0) {
830                 *val = frame_val & MI_COM_DATA_MASK;
831                 ret = 0;
832         }
833
834         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
835                 tw32_f(MAC_MI_MODE, tp->mi_mode);
836                 udelay(80);
837         }
838
839         return ret;
840 }
841
842 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
843 {
844         u32 frame_val;
845         unsigned int loops;
846         int ret;
847
848         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
849             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
850                 return 0;
851
852         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
853                 tw32_f(MAC_MI_MODE,
854                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
855                 udelay(80);
856         }
857
858         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
859                       MI_COM_PHY_ADDR_MASK);
860         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
861                       MI_COM_REG_ADDR_MASK);
862         frame_val |= (val & MI_COM_DATA_MASK);
863         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
864
865         tw32_f(MAC_MI_COM, frame_val);
866
867         loops = PHY_BUSY_LOOPS;
868         while (loops != 0) {
869                 udelay(10);
870                 frame_val = tr32(MAC_MI_COM);
871                 if ((frame_val & MI_COM_BUSY) == 0) {
872                         udelay(5);
873                         frame_val = tr32(MAC_MI_COM);
874                         break;
875                 }
876                 loops -= 1;
877         }
878
879         ret = -EBUSY;
880         if (loops != 0)
881                 ret = 0;
882
883         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
884                 tw32_f(MAC_MI_MODE, tp->mi_mode);
885                 udelay(80);
886         }
887
888         return ret;
889 }
890
891 static int tg3_bmcr_reset(struct tg3 *tp)
892 {
893         u32 phy_control;
894         int limit, err;
895
896         /* OK, reset it, and poll the BMCR_RESET bit until it
897          * clears or we time out.
898          */
899         phy_control = BMCR_RESET;
900         err = tg3_writephy(tp, MII_BMCR, phy_control);
901         if (err != 0)
902                 return -EBUSY;
903
904         limit = 5000;
905         while (limit--) {
906                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
907                 if (err != 0)
908                         return -EBUSY;
909
910                 if ((phy_control & BMCR_RESET) == 0) {
911                         udelay(40);
912                         break;
913                 }
914                 udelay(10);
915         }
916         if (limit < 0)
917                 return -EBUSY;
918
919         return 0;
920 }
921
922 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
923 {
924         struct tg3 *tp = bp->priv;
925         u32 val;
926
927         spin_lock_bh(&tp->lock);
928
929         if (tg3_readphy(tp, reg, &val))
930                 val = -EIO;
931
932         spin_unlock_bh(&tp->lock);
933
934         return val;
935 }
936
937 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
938 {
939         struct tg3 *tp = bp->priv;
940         u32 ret = 0;
941
942         spin_lock_bh(&tp->lock);
943
944         if (tg3_writephy(tp, reg, val))
945                 ret = -EIO;
946
947         spin_unlock_bh(&tp->lock);
948
949         return ret;
950 }
951
952 static int tg3_mdio_reset(struct mii_bus *bp)
953 {
954         return 0;
955 }
956
957 static void tg3_mdio_config_5785(struct tg3 *tp)
958 {
959         u32 val;
960         struct phy_device *phydev;
961
962         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
963         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
964         case PHY_ID_BCM50610:
965         case PHY_ID_BCM50610M:
966                 val = MAC_PHYCFG2_50610_LED_MODES;
967                 break;
968         case PHY_ID_BCMAC131:
969                 val = MAC_PHYCFG2_AC131_LED_MODES;
970                 break;
971         case PHY_ID_RTL8211C:
972                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
973                 break;
974         case PHY_ID_RTL8201E:
975                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
976                 break;
977         default:
978                 return;
979         }
980
981         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
982                 tw32(MAC_PHYCFG2, val);
983
984                 val = tr32(MAC_PHYCFG1);
985                 val &= ~(MAC_PHYCFG1_RGMII_INT |
986                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
987                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
988                 tw32(MAC_PHYCFG1, val);
989
990                 return;
991         }
992
993         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
994                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
995                        MAC_PHYCFG2_FMODE_MASK_MASK |
996                        MAC_PHYCFG2_GMODE_MASK_MASK |
997                        MAC_PHYCFG2_ACT_MASK_MASK   |
998                        MAC_PHYCFG2_QUAL_MASK_MASK |
999                        MAC_PHYCFG2_INBAND_ENABLE;
1000
1001         tw32(MAC_PHYCFG2, val);
1002
1003         val = tr32(MAC_PHYCFG1);
1004         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1005                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1006         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1007                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1008                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1009                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1010                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1011         }
1012         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1013                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1014         tw32(MAC_PHYCFG1, val);
1015
1016         val = tr32(MAC_EXT_RGMII_MODE);
1017         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1018                  MAC_RGMII_MODE_RX_QUALITY |
1019                  MAC_RGMII_MODE_RX_ACTIVITY |
1020                  MAC_RGMII_MODE_RX_ENG_DET |
1021                  MAC_RGMII_MODE_TX_ENABLE |
1022                  MAC_RGMII_MODE_TX_LOWPWR |
1023                  MAC_RGMII_MODE_TX_RESET);
1024         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1025                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1026                         val |= MAC_RGMII_MODE_RX_INT_B |
1027                                MAC_RGMII_MODE_RX_QUALITY |
1028                                MAC_RGMII_MODE_RX_ACTIVITY |
1029                                MAC_RGMII_MODE_RX_ENG_DET;
1030                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1031                         val |= MAC_RGMII_MODE_TX_ENABLE |
1032                                MAC_RGMII_MODE_TX_LOWPWR |
1033                                MAC_RGMII_MODE_TX_RESET;
1034         }
1035         tw32(MAC_EXT_RGMII_MODE, val);
1036 }
1037
1038 static void tg3_mdio_start(struct tg3 *tp)
1039 {
1040         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1041         tw32_f(MAC_MI_MODE, tp->mi_mode);
1042         udelay(80);
1043
1044         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1046                 tg3_mdio_config_5785(tp);
1047 }
1048
1049 static int tg3_mdio_init(struct tg3 *tp)
1050 {
1051         int i;
1052         u32 reg;
1053         struct phy_device *phydev;
1054
1055         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1057                 u32 is_serdes;
1058
1059                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1060
1061                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1062                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1063                 else
1064                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1065                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1066                 if (is_serdes)
1067                         tp->phy_addr += 7;
1068         } else
1069                 tp->phy_addr = TG3_PHY_MII_ADDR;
1070
1071         tg3_mdio_start(tp);
1072
1073         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1074             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1075                 return 0;
1076
1077         tp->mdio_bus = mdiobus_alloc();
1078         if (tp->mdio_bus == NULL)
1079                 return -ENOMEM;
1080
1081         tp->mdio_bus->name     = "tg3 mdio bus";
1082         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1083                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1084         tp->mdio_bus->priv     = tp;
1085         tp->mdio_bus->parent   = &tp->pdev->dev;
1086         tp->mdio_bus->read     = &tg3_mdio_read;
1087         tp->mdio_bus->write    = &tg3_mdio_write;
1088         tp->mdio_bus->reset    = &tg3_mdio_reset;
1089         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1090         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1091
1092         for (i = 0; i < PHY_MAX_ADDR; i++)
1093                 tp->mdio_bus->irq[i] = PHY_POLL;
1094
1095         /* The bus registration will look for all the PHYs on the mdio bus.
1096          * Unfortunately, it does not ensure the PHY is powered up before
1097          * accessing the PHY ID registers.  A chip reset is the
1098          * quickest way to bring the device back to an operational state..
1099          */
1100         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1101                 tg3_bmcr_reset(tp);
1102
1103         i = mdiobus_register(tp->mdio_bus);
1104         if (i) {
1105                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1106                 mdiobus_free(tp->mdio_bus);
1107                 return i;
1108         }
1109
1110         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1111
1112         if (!phydev || !phydev->drv) {
1113                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1114                 mdiobus_unregister(tp->mdio_bus);
1115                 mdiobus_free(tp->mdio_bus);
1116                 return -ENODEV;
1117         }
1118
1119         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1120         case PHY_ID_BCM57780:
1121                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1122                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1123                 break;
1124         case PHY_ID_BCM50610:
1125         case PHY_ID_BCM50610M:
1126                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1127                                      PHY_BRCM_RX_REFCLK_UNUSED |
1128                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1129                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1130                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1131                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1132                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1133                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1134                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1135                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1136                 /* fallthru */
1137         case PHY_ID_RTL8211C:
1138                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1139                 break;
1140         case PHY_ID_RTL8201E:
1141         case PHY_ID_BCMAC131:
1142                 phydev->interface = PHY_INTERFACE_MODE_MII;
1143                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1144                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1145                 break;
1146         }
1147
1148         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1149
1150         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1151                 tg3_mdio_config_5785(tp);
1152
1153         return 0;
1154 }
1155
1156 static void tg3_mdio_fini(struct tg3 *tp)
1157 {
1158         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1159                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1160                 mdiobus_unregister(tp->mdio_bus);
1161                 mdiobus_free(tp->mdio_bus);
1162         }
1163 }
1164
1165 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1166 {
1167         int err;
1168
1169         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1170         if (err)
1171                 goto done;
1172
1173         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1174         if (err)
1175                 goto done;
1176
1177         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1178                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1179         if (err)
1180                 goto done;
1181
1182         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1183
1184 done:
1185         return err;
1186 }
1187
1188 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1189 {
1190         int err;
1191
1192         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1193         if (err)
1194                 goto done;
1195
1196         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1197         if (err)
1198                 goto done;
1199
1200         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1201                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1202         if (err)
1203                 goto done;
1204
1205         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1206
1207 done:
1208         return err;
1209 }
1210
1211 /* tp->lock is held. */
1212 static inline void tg3_generate_fw_event(struct tg3 *tp)
1213 {
1214         u32 val;
1215
1216         val = tr32(GRC_RX_CPU_EVENT);
1217         val |= GRC_RX_CPU_DRIVER_EVENT;
1218         tw32_f(GRC_RX_CPU_EVENT, val);
1219
1220         tp->last_event_jiffies = jiffies;
1221 }
1222
1223 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1224
1225 /* tp->lock is held. */
1226 static void tg3_wait_for_event_ack(struct tg3 *tp)
1227 {
1228         int i;
1229         unsigned int delay_cnt;
1230         long time_remain;
1231
1232         /* If enough time has passed, no wait is necessary. */
1233         time_remain = (long)(tp->last_event_jiffies + 1 +
1234                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1235                       (long)jiffies;
1236         if (time_remain < 0)
1237                 return;
1238
1239         /* Check if we can shorten the wait time. */
1240         delay_cnt = jiffies_to_usecs(time_remain);
1241         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1242                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1243         delay_cnt = (delay_cnt >> 3) + 1;
1244
1245         for (i = 0; i < delay_cnt; i++) {
1246                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1247                         break;
1248                 udelay(8);
1249         }
1250 }
1251
1252 /* tp->lock is held. */
1253 static void tg3_ump_link_report(struct tg3 *tp)
1254 {
1255         u32 reg;
1256         u32 val;
1257
1258         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1259             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1260                 return;
1261
1262         tg3_wait_for_event_ack(tp);
1263
1264         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1265
1266         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1267
1268         val = 0;
1269         if (!tg3_readphy(tp, MII_BMCR, &reg))
1270                 val = reg << 16;
1271         if (!tg3_readphy(tp, MII_BMSR, &reg))
1272                 val |= (reg & 0xffff);
1273         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1274
1275         val = 0;
1276         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1277                 val = reg << 16;
1278         if (!tg3_readphy(tp, MII_LPA, &reg))
1279                 val |= (reg & 0xffff);
1280         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1281
1282         val = 0;
1283         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1284                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1285                         val = reg << 16;
1286                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1287                         val |= (reg & 0xffff);
1288         }
1289         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1290
1291         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1292                 val = reg << 16;
1293         else
1294                 val = 0;
1295         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1296
1297         tg3_generate_fw_event(tp);
1298 }
1299
1300 static void tg3_link_report(struct tg3 *tp)
1301 {
1302         if (!netif_carrier_ok(tp->dev)) {
1303                 netif_info(tp, link, tp->dev, "Link is down\n");
1304                 tg3_ump_link_report(tp);
1305         } else if (netif_msg_link(tp)) {
1306                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1307                             (tp->link_config.active_speed == SPEED_1000 ?
1308                              1000 :
1309                              (tp->link_config.active_speed == SPEED_100 ?
1310                               100 : 10)),
1311                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1312                              "full" : "half"));
1313
1314                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1315                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1316                             "on" : "off",
1317                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1318                             "on" : "off");
1319                 tg3_ump_link_report(tp);
1320         }
1321 }
1322
1323 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1324 {
1325         u16 miireg;
1326
1327         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1328                 miireg = ADVERTISE_PAUSE_CAP;
1329         else if (flow_ctrl & FLOW_CTRL_TX)
1330                 miireg = ADVERTISE_PAUSE_ASYM;
1331         else if (flow_ctrl & FLOW_CTRL_RX)
1332                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1333         else
1334                 miireg = 0;
1335
1336         return miireg;
1337 }
1338
1339 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1340 {
1341         u16 miireg;
1342
1343         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1344                 miireg = ADVERTISE_1000XPAUSE;
1345         else if (flow_ctrl & FLOW_CTRL_TX)
1346                 miireg = ADVERTISE_1000XPSE_ASYM;
1347         else if (flow_ctrl & FLOW_CTRL_RX)
1348                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1349         else
1350                 miireg = 0;
1351
1352         return miireg;
1353 }
1354
1355 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1356 {
1357         u8 cap = 0;
1358
1359         if (lcladv & ADVERTISE_1000XPAUSE) {
1360                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1361                         if (rmtadv & LPA_1000XPAUSE)
1362                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1363                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1364                                 cap = FLOW_CTRL_RX;
1365                 } else {
1366                         if (rmtadv & LPA_1000XPAUSE)
1367                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1368                 }
1369         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1370                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1371                         cap = FLOW_CTRL_TX;
1372         }
1373
1374         return cap;
1375 }
1376
1377 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1378 {
1379         u8 autoneg;
1380         u8 flowctrl = 0;
1381         u32 old_rx_mode = tp->rx_mode;
1382         u32 old_tx_mode = tp->tx_mode;
1383
1384         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1385                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1386         else
1387                 autoneg = tp->link_config.autoneg;
1388
1389         if (autoneg == AUTONEG_ENABLE &&
1390             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1391                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1392                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1393                 else
1394                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1395         } else
1396                 flowctrl = tp->link_config.flowctrl;
1397
1398         tp->link_config.active_flowctrl = flowctrl;
1399
1400         if (flowctrl & FLOW_CTRL_RX)
1401                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1402         else
1403                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1404
1405         if (old_rx_mode != tp->rx_mode)
1406                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1407
1408         if (flowctrl & FLOW_CTRL_TX)
1409                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1410         else
1411                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1412
1413         if (old_tx_mode != tp->tx_mode)
1414                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1415 }
1416
1417 static void tg3_adjust_link(struct net_device *dev)
1418 {
1419         u8 oldflowctrl, linkmesg = 0;
1420         u32 mac_mode, lcl_adv, rmt_adv;
1421         struct tg3 *tp = netdev_priv(dev);
1422         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1423
1424         spin_lock_bh(&tp->lock);
1425
1426         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1427                                     MAC_MODE_HALF_DUPLEX);
1428
1429         oldflowctrl = tp->link_config.active_flowctrl;
1430
1431         if (phydev->link) {
1432                 lcl_adv = 0;
1433                 rmt_adv = 0;
1434
1435                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1436                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1437                 else if (phydev->speed == SPEED_1000 ||
1438                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1439                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1440                 else
1441                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1442
1443                 if (phydev->duplex == DUPLEX_HALF)
1444                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1445                 else {
1446                         lcl_adv = tg3_advert_flowctrl_1000T(
1447                                   tp->link_config.flowctrl);
1448
1449                         if (phydev->pause)
1450                                 rmt_adv = LPA_PAUSE_CAP;
1451                         if (phydev->asym_pause)
1452                                 rmt_adv |= LPA_PAUSE_ASYM;
1453                 }
1454
1455                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1456         } else
1457                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1458
1459         if (mac_mode != tp->mac_mode) {
1460                 tp->mac_mode = mac_mode;
1461                 tw32_f(MAC_MODE, tp->mac_mode);
1462                 udelay(40);
1463         }
1464
1465         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1466                 if (phydev->speed == SPEED_10)
1467                         tw32(MAC_MI_STAT,
1468                              MAC_MI_STAT_10MBPS_MODE |
1469                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1470                 else
1471                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1472         }
1473
1474         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1475                 tw32(MAC_TX_LENGTHS,
1476                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1477                       (6 << TX_LENGTHS_IPG_SHIFT) |
1478                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1479         else
1480                 tw32(MAC_TX_LENGTHS,
1481                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1482                       (6 << TX_LENGTHS_IPG_SHIFT) |
1483                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1484
1485         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1486             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1487             phydev->speed != tp->link_config.active_speed ||
1488             phydev->duplex != tp->link_config.active_duplex ||
1489             oldflowctrl != tp->link_config.active_flowctrl)
1490                 linkmesg = 1;
1491
1492         tp->link_config.active_speed = phydev->speed;
1493         tp->link_config.active_duplex = phydev->duplex;
1494
1495         spin_unlock_bh(&tp->lock);
1496
1497         if (linkmesg)
1498                 tg3_link_report(tp);
1499 }
1500
1501 static int tg3_phy_init(struct tg3 *tp)
1502 {
1503         struct phy_device *phydev;
1504
1505         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1506                 return 0;
1507
1508         /* Bring the PHY back to a known state. */
1509         tg3_bmcr_reset(tp);
1510
1511         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1512
1513         /* Attach the MAC to the PHY. */
1514         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1515                              phydev->dev_flags, phydev->interface);
1516         if (IS_ERR(phydev)) {
1517                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1518                 return PTR_ERR(phydev);
1519         }
1520
1521         /* Mask with MAC supported features. */
1522         switch (phydev->interface) {
1523         case PHY_INTERFACE_MODE_GMII:
1524         case PHY_INTERFACE_MODE_RGMII:
1525                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1526                         phydev->supported &= (PHY_GBIT_FEATURES |
1527                                               SUPPORTED_Pause |
1528                                               SUPPORTED_Asym_Pause);
1529                         break;
1530                 }
1531                 /* fallthru */
1532         case PHY_INTERFACE_MODE_MII:
1533                 phydev->supported &= (PHY_BASIC_FEATURES |
1534                                       SUPPORTED_Pause |
1535                                       SUPPORTED_Asym_Pause);
1536                 break;
1537         default:
1538                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1539                 return -EINVAL;
1540         }
1541
1542         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1543
1544         phydev->advertising = phydev->supported;
1545
1546         return 0;
1547 }
1548
1549 static void tg3_phy_start(struct tg3 *tp)
1550 {
1551         struct phy_device *phydev;
1552
1553         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1554                 return;
1555
1556         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1557
1558         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1559                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1560                 phydev->speed = tp->link_config.orig_speed;
1561                 phydev->duplex = tp->link_config.orig_duplex;
1562                 phydev->autoneg = tp->link_config.orig_autoneg;
1563                 phydev->advertising = tp->link_config.orig_advertising;
1564         }
1565
1566         phy_start(phydev);
1567
1568         phy_start_aneg(phydev);
1569 }
1570
1571 static void tg3_phy_stop(struct tg3 *tp)
1572 {
1573         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1574                 return;
1575
1576         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1577 }
1578
1579 static void tg3_phy_fini(struct tg3 *tp)
1580 {
1581         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1582                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1583                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1584         }
1585 }
1586
1587 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1588 {
1589         int err;
1590
1591         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1592         if (!err)
1593                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1594
1595         return err;
1596 }
1597
1598 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1599 {
1600         int err;
1601
1602         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1603         if (!err)
1604                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1605
1606         return err;
1607 }
1608
1609 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1610 {
1611         u32 phytest;
1612
1613         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1614                 u32 phy;
1615
1616                 tg3_writephy(tp, MII_TG3_FET_TEST,
1617                              phytest | MII_TG3_FET_SHADOW_EN);
1618                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1619                         if (enable)
1620                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1621                         else
1622                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1623                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1624                 }
1625                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1626         }
1627 }
1628
1629 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1630 {
1631         u32 reg;
1632
1633         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1634             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1635               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1636              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1637                 return;
1638
1639         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1640                 tg3_phy_fet_toggle_apd(tp, enable);
1641                 return;
1642         }
1643
1644         reg = MII_TG3_MISC_SHDW_WREN |
1645               MII_TG3_MISC_SHDW_SCR5_SEL |
1646               MII_TG3_MISC_SHDW_SCR5_LPED |
1647               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1648               MII_TG3_MISC_SHDW_SCR5_SDTL |
1649               MII_TG3_MISC_SHDW_SCR5_C125OE;
1650         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1651                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1652
1653         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1654
1655
1656         reg = MII_TG3_MISC_SHDW_WREN |
1657               MII_TG3_MISC_SHDW_APD_SEL |
1658               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1659         if (enable)
1660                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1661
1662         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1663 }
1664
1665 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1666 {
1667         u32 phy;
1668
1669         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1670             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1671                 return;
1672
1673         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1674                 u32 ephy;
1675
1676                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1677                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1678
1679                         tg3_writephy(tp, MII_TG3_FET_TEST,
1680                                      ephy | MII_TG3_FET_SHADOW_EN);
1681                         if (!tg3_readphy(tp, reg, &phy)) {
1682                                 if (enable)
1683                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1684                                 else
1685                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1686                                 tg3_writephy(tp, reg, phy);
1687                         }
1688                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1689                 }
1690         } else {
1691                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1692                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1693                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1694                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1695                         if (enable)
1696                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1697                         else
1698                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1699                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1700                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1701                 }
1702         }
1703 }
1704
1705 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1706 {
1707         u32 val;
1708
1709         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1710                 return;
1711
1712         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1713             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1714                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1715                              (val | (1 << 15) | (1 << 4)));
1716 }
1717
1718 static void tg3_phy_apply_otp(struct tg3 *tp)
1719 {
1720         u32 otp, phy;
1721
1722         if (!tp->phy_otp)
1723                 return;
1724
1725         otp = tp->phy_otp;
1726
1727         /* Enable SM_DSP clock and tx 6dB coding. */
1728         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1729               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1730               MII_TG3_AUXCTL_ACTL_TX_6DB;
1731         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1732
1733         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1734         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1735         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1736
1737         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1738               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1739         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1740
1741         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1742         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1743         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1744
1745         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1746         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1747
1748         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1749         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1750
1751         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1752               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1753         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1754
1755         /* Turn off SM_DSP clock. */
1756         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1757               MII_TG3_AUXCTL_ACTL_TX_6DB;
1758         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1759 }
1760
1761 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1762 {
1763         u32 val;
1764
1765         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1766                 return;
1767
1768         tp->setlpicnt = 0;
1769
1770         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1771             current_link_up == 1 &&
1772             (tp->link_config.active_speed == SPEED_1000 ||
1773              (tp->link_config.active_speed == SPEED_100 &&
1774               tp->link_config.active_duplex == DUPLEX_FULL))) {
1775                 u32 eeectl;
1776
1777                 if (tp->link_config.active_speed == SPEED_1000)
1778                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1779                 else
1780                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1781
1782                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1783
1784                 tg3_phy_cl45_read(tp, 0x7, TG3_CL45_D7_EEERES_STAT, &val);
1785
1786                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1787                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1788                         tp->setlpicnt = 2;
1789         }
1790
1791         if (!tp->setlpicnt) {
1792                 val = tr32(TG3_CPMU_EEE_MODE);
1793                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1794         }
1795 }
1796
1797 static int tg3_wait_macro_done(struct tg3 *tp)
1798 {
1799         int limit = 100;
1800
1801         while (limit--) {
1802                 u32 tmp32;
1803
1804                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1805                         if ((tmp32 & 0x1000) == 0)
1806                                 break;
1807                 }
1808         }
1809         if (limit < 0)
1810                 return -EBUSY;
1811
1812         return 0;
1813 }
1814
1815 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1816 {
1817         static const u32 test_pat[4][6] = {
1818         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1819         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1820         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1821         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1822         };
1823         int chan;
1824
1825         for (chan = 0; chan < 4; chan++) {
1826                 int i;
1827
1828                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1829                              (chan * 0x2000) | 0x0200);
1830                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1831
1832                 for (i = 0; i < 6; i++)
1833                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1834                                      test_pat[chan][i]);
1835
1836                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1837                 if (tg3_wait_macro_done(tp)) {
1838                         *resetp = 1;
1839                         return -EBUSY;
1840                 }
1841
1842                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1843                              (chan * 0x2000) | 0x0200);
1844                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1845                 if (tg3_wait_macro_done(tp)) {
1846                         *resetp = 1;
1847                         return -EBUSY;
1848                 }
1849
1850                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1851                 if (tg3_wait_macro_done(tp)) {
1852                         *resetp = 1;
1853                         return -EBUSY;
1854                 }
1855
1856                 for (i = 0; i < 6; i += 2) {
1857                         u32 low, high;
1858
1859                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1860                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1861                             tg3_wait_macro_done(tp)) {
1862                                 *resetp = 1;
1863                                 return -EBUSY;
1864                         }
1865                         low &= 0x7fff;
1866                         high &= 0x000f;
1867                         if (low != test_pat[chan][i] ||
1868                             high != test_pat[chan][i+1]) {
1869                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1870                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1871                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1872
1873                                 return -EBUSY;
1874                         }
1875                 }
1876         }
1877
1878         return 0;
1879 }
1880
1881 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1882 {
1883         int chan;
1884
1885         for (chan = 0; chan < 4; chan++) {
1886                 int i;
1887
1888                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1889                              (chan * 0x2000) | 0x0200);
1890                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1891                 for (i = 0; i < 6; i++)
1892                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1893                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1894                 if (tg3_wait_macro_done(tp))
1895                         return -EBUSY;
1896         }
1897
1898         return 0;
1899 }
1900
1901 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1902 {
1903         u32 reg32, phy9_orig;
1904         int retries, do_phy_reset, err;
1905
1906         retries = 10;
1907         do_phy_reset = 1;
1908         do {
1909                 if (do_phy_reset) {
1910                         err = tg3_bmcr_reset(tp);
1911                         if (err)
1912                                 return err;
1913                         do_phy_reset = 0;
1914                 }
1915
1916                 /* Disable transmitter and interrupt.  */
1917                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1918                         continue;
1919
1920                 reg32 |= 0x3000;
1921                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1922
1923                 /* Set full-duplex, 1000 mbps.  */
1924                 tg3_writephy(tp, MII_BMCR,
1925                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1926
1927                 /* Set to master mode.  */
1928                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1929                         continue;
1930
1931                 tg3_writephy(tp, MII_TG3_CTRL,
1932                              (MII_TG3_CTRL_AS_MASTER |
1933                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1934
1935                 /* Enable SM_DSP_CLOCK and 6dB.  */
1936                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1937
1938                 /* Block the PHY control access.  */
1939                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1940
1941                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1942                 if (!err)
1943                         break;
1944         } while (--retries);
1945
1946         err = tg3_phy_reset_chanpat(tp);
1947         if (err)
1948                 return err;
1949
1950         tg3_phydsp_write(tp, 0x8005, 0x0000);
1951
1952         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1953         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1954
1955         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1956             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1957                 /* Set Extended packet length bit for jumbo frames */
1958                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1959         } else {
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1961         }
1962
1963         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1964
1965         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1966                 reg32 &= ~0x3000;
1967                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1968         } else if (!err)
1969                 err = -EBUSY;
1970
1971         return err;
1972 }
1973
1974 /* This will reset the tigon3 PHY if there is no valid
1975  * link unless the FORCE argument is non-zero.
1976  */
1977 static int tg3_phy_reset(struct tg3 *tp)
1978 {
1979         u32 val, cpmuctrl;
1980         int err;
1981
1982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1983                 val = tr32(GRC_MISC_CFG);
1984                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1985                 udelay(40);
1986         }
1987         err  = tg3_readphy(tp, MII_BMSR, &val);
1988         err |= tg3_readphy(tp, MII_BMSR, &val);
1989         if (err != 0)
1990                 return -EBUSY;
1991
1992         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1993                 netif_carrier_off(tp->dev);
1994                 tg3_link_report(tp);
1995         }
1996
1997         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2000                 err = tg3_phy_reset_5703_4_5(tp);
2001                 if (err)
2002                         return err;
2003                 goto out;
2004         }
2005
2006         cpmuctrl = 0;
2007         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2008             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2009                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2010                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2011                         tw32(TG3_CPMU_CTRL,
2012                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2013         }
2014
2015         err = tg3_bmcr_reset(tp);
2016         if (err)
2017                 return err;
2018
2019         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2020                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2021                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2022
2023                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2024         }
2025
2026         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2027             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2028                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2029                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2030                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2031                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2032                         udelay(40);
2033                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2034                 }
2035         }
2036
2037         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2038              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2039             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2040                 return 0;
2041
2042         tg3_phy_apply_otp(tp);
2043
2044         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2045                 tg3_phy_toggle_apd(tp, true);
2046         else
2047                 tg3_phy_toggle_apd(tp, false);
2048
2049 out:
2050         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2051                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2052                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2053                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2054                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2055         }
2056         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2057                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2058                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2059         }
2060         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2061                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2062                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2063                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2064                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2065                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2066         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2067                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2068                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2069                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2070                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2071                         tg3_writephy(tp, MII_TG3_TEST1,
2072                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2073                 } else
2074                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2075                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2076         }
2077         /* Set Extended packet length bit (bit 14) on all chips that */
2078         /* support jumbo frames */
2079         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2080                 /* Cannot do read-modify-write on 5401 */
2081                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2082         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2083                 /* Set bit 14 with read-modify-write to preserve other bits */
2084                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2085                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2086                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2087         }
2088
2089         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2090          * jumbo frames transmission.
2091          */
2092         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2093                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2094                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2095                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2096         }
2097
2098         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2099                 /* adjust output voltage */
2100                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2101         }
2102
2103         tg3_phy_toggle_automdix(tp, 1);
2104         tg3_phy_set_wirespeed(tp);
2105         return 0;
2106 }
2107
2108 static void tg3_frob_aux_power(struct tg3 *tp)
2109 {
2110         struct tg3 *tp_peer = tp;
2111
2112         /* The GPIOs do something completely different on 57765. */
2113         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2114             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2115             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2116                 return;
2117
2118         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2119             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2120             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2121                 struct net_device *dev_peer;
2122
2123                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2124                 /* remove_one() may have been run on the peer. */
2125                 if (!dev_peer)
2126                         tp_peer = tp;
2127                 else
2128                         tp_peer = netdev_priv(dev_peer);
2129         }
2130
2131         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2132             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2133             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2134             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2135                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2136                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2137                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2138                                     (GRC_LCLCTRL_GPIO_OE0 |
2139                                      GRC_LCLCTRL_GPIO_OE1 |
2140                                      GRC_LCLCTRL_GPIO_OE2 |
2141                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2142                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2143                                     100);
2144                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2145                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2146                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2147                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2148                                              GRC_LCLCTRL_GPIO_OE1 |
2149                                              GRC_LCLCTRL_GPIO_OE2 |
2150                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2151                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2152                                              tp->grc_local_ctrl;
2153                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2154
2155                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2156                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2157
2158                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2159                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2160                 } else {
2161                         u32 no_gpio2;
2162                         u32 grc_local_ctrl = 0;
2163
2164                         if (tp_peer != tp &&
2165                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2166                                 return;
2167
2168                         /* Workaround to prevent overdrawing Amps. */
2169                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2170                             ASIC_REV_5714) {
2171                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2172                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2173                                             grc_local_ctrl, 100);
2174                         }
2175
2176                         /* On 5753 and variants, GPIO2 cannot be used. */
2177                         no_gpio2 = tp->nic_sram_data_cfg &
2178                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2179
2180                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2181                                          GRC_LCLCTRL_GPIO_OE1 |
2182                                          GRC_LCLCTRL_GPIO_OE2 |
2183                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2184                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2185                         if (no_gpio2) {
2186                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2187                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2188                         }
2189                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2190                                                     grc_local_ctrl, 100);
2191
2192                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2193
2194                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2195                                                     grc_local_ctrl, 100);
2196
2197                         if (!no_gpio2) {
2198                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2199                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2200                                             grc_local_ctrl, 100);
2201                         }
2202                 }
2203         } else {
2204                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2205                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2206                         if (tp_peer != tp &&
2207                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2208                                 return;
2209
2210                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2211                                     (GRC_LCLCTRL_GPIO_OE1 |
2212                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2213
2214                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2215                                     GRC_LCLCTRL_GPIO_OE1, 100);
2216
2217                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2218                                     (GRC_LCLCTRL_GPIO_OE1 |
2219                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2220                 }
2221         }
2222 }
2223
2224 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2225 {
2226         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2227                 return 1;
2228         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2229                 if (speed != SPEED_10)
2230                         return 1;
2231         } else if (speed == SPEED_10)
2232                 return 1;
2233
2234         return 0;
2235 }
2236
2237 static int tg3_setup_phy(struct tg3 *, int);
2238
2239 #define RESET_KIND_SHUTDOWN     0
2240 #define RESET_KIND_INIT         1
2241 #define RESET_KIND_SUSPEND      2
2242
2243 static void tg3_write_sig_post_reset(struct tg3 *, int);
2244 static int tg3_halt_cpu(struct tg3 *, u32);
2245
2246 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2247 {
2248         u32 val;
2249
2250         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2251                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2252                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2253                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2254
2255                         sg_dig_ctrl |=
2256                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2257                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2258                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2259                 }
2260                 return;
2261         }
2262
2263         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2264                 tg3_bmcr_reset(tp);
2265                 val = tr32(GRC_MISC_CFG);
2266                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2267                 udelay(40);
2268                 return;
2269         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2270                 u32 phytest;
2271                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2272                         u32 phy;
2273
2274                         tg3_writephy(tp, MII_ADVERTISE, 0);
2275                         tg3_writephy(tp, MII_BMCR,
2276                                      BMCR_ANENABLE | BMCR_ANRESTART);
2277
2278                         tg3_writephy(tp, MII_TG3_FET_TEST,
2279                                      phytest | MII_TG3_FET_SHADOW_EN);
2280                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2281                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2282                                 tg3_writephy(tp,
2283                                              MII_TG3_FET_SHDW_AUXMODE4,
2284                                              phy);
2285                         }
2286                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2287                 }
2288                 return;
2289         } else if (do_low_power) {
2290                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2291                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2292
2293                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2294                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2295                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2296                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2297                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2298         }
2299
2300         /* The PHY should not be powered down on some chips because
2301          * of bugs.
2302          */
2303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2304             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2305             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2306              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2307                 return;
2308
2309         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2310             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2311                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2312                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2313                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2314                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2315         }
2316
2317         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2318 }
2319
2320 /* tp->lock is held. */
2321 static int tg3_nvram_lock(struct tg3 *tp)
2322 {
2323         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2324                 int i;
2325
2326                 if (tp->nvram_lock_cnt == 0) {
2327                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2328                         for (i = 0; i < 8000; i++) {
2329                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2330                                         break;
2331                                 udelay(20);
2332                         }
2333                         if (i == 8000) {
2334                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2335                                 return -ENODEV;
2336                         }
2337                 }
2338                 tp->nvram_lock_cnt++;
2339         }
2340         return 0;
2341 }
2342
2343 /* tp->lock is held. */
2344 static void tg3_nvram_unlock(struct tg3 *tp)
2345 {
2346         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2347                 if (tp->nvram_lock_cnt > 0)
2348                         tp->nvram_lock_cnt--;
2349                 if (tp->nvram_lock_cnt == 0)
2350                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2351         }
2352 }
2353
2354 /* tp->lock is held. */
2355 static void tg3_enable_nvram_access(struct tg3 *tp)
2356 {
2357         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2358             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2359                 u32 nvaccess = tr32(NVRAM_ACCESS);
2360
2361                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2362         }
2363 }
2364
2365 /* tp->lock is held. */
2366 static void tg3_disable_nvram_access(struct tg3 *tp)
2367 {
2368         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2369             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2370                 u32 nvaccess = tr32(NVRAM_ACCESS);
2371
2372                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2373         }
2374 }
2375
2376 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2377                                         u32 offset, u32 *val)
2378 {
2379         u32 tmp;
2380         int i;
2381
2382         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2383                 return -EINVAL;
2384
2385         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2386                                         EEPROM_ADDR_DEVID_MASK |
2387                                         EEPROM_ADDR_READ);
2388         tw32(GRC_EEPROM_ADDR,
2389              tmp |
2390              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2391              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2392               EEPROM_ADDR_ADDR_MASK) |
2393              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2394
2395         for (i = 0; i < 1000; i++) {
2396                 tmp = tr32(GRC_EEPROM_ADDR);
2397
2398                 if (tmp & EEPROM_ADDR_COMPLETE)
2399                         break;
2400                 msleep(1);
2401         }
2402         if (!(tmp & EEPROM_ADDR_COMPLETE))
2403                 return -EBUSY;
2404
2405         tmp = tr32(GRC_EEPROM_DATA);
2406
2407         /*
2408          * The data will always be opposite the native endian
2409          * format.  Perform a blind byteswap to compensate.
2410          */
2411         *val = swab32(tmp);
2412
2413         return 0;
2414 }
2415
2416 #define NVRAM_CMD_TIMEOUT 10000
2417
2418 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2419 {
2420         int i;
2421
2422         tw32(NVRAM_CMD, nvram_cmd);
2423         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2424                 udelay(10);
2425                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2426                         udelay(10);
2427                         break;
2428                 }
2429         }
2430
2431         if (i == NVRAM_CMD_TIMEOUT)
2432                 return -EBUSY;
2433
2434         return 0;
2435 }
2436
2437 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2438 {
2439         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2440             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2441             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2442            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2443             (tp->nvram_jedecnum == JEDEC_ATMEL))
2444
2445                 addr = ((addr / tp->nvram_pagesize) <<
2446                         ATMEL_AT45DB0X1B_PAGE_POS) +
2447                        (addr % tp->nvram_pagesize);
2448
2449         return addr;
2450 }
2451
2452 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2453 {
2454         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2455             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2456             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2457            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2458             (tp->nvram_jedecnum == JEDEC_ATMEL))
2459
2460                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2461                         tp->nvram_pagesize) +
2462                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2463
2464         return addr;
2465 }
2466
2467 /* NOTE: Data read in from NVRAM is byteswapped according to
2468  * the byteswapping settings for all other register accesses.
2469  * tg3 devices are BE devices, so on a BE machine, the data
2470  * returned will be exactly as it is seen in NVRAM.  On a LE
2471  * machine, the 32-bit value will be byteswapped.
2472  */
2473 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2474 {
2475         int ret;
2476
2477         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2478                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2479
2480         offset = tg3_nvram_phys_addr(tp, offset);
2481
2482         if (offset > NVRAM_ADDR_MSK)
2483                 return -EINVAL;
2484
2485         ret = tg3_nvram_lock(tp);
2486         if (ret)
2487                 return ret;
2488
2489         tg3_enable_nvram_access(tp);
2490
2491         tw32(NVRAM_ADDR, offset);
2492         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2493                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2494
2495         if (ret == 0)
2496                 *val = tr32(NVRAM_RDDATA);
2497
2498         tg3_disable_nvram_access(tp);
2499
2500         tg3_nvram_unlock(tp);
2501
2502         return ret;
2503 }
2504
2505 /* Ensures NVRAM data is in bytestream format. */
2506 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2507 {
2508         u32 v;
2509         int res = tg3_nvram_read(tp, offset, &v);
2510         if (!res)
2511                 *val = cpu_to_be32(v);
2512         return res;
2513 }
2514
2515 /* tp->lock is held. */
2516 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2517 {
2518         u32 addr_high, addr_low;
2519         int i;
2520
2521         addr_high = ((tp->dev->dev_addr[0] << 8) |
2522                      tp->dev->dev_addr[1]);
2523         addr_low = ((tp->dev->dev_addr[2] << 24) |
2524                     (tp->dev->dev_addr[3] << 16) |
2525                     (tp->dev->dev_addr[4] <<  8) |
2526                     (tp->dev->dev_addr[5] <<  0));
2527         for (i = 0; i < 4; i++) {
2528                 if (i == 1 && skip_mac_1)
2529                         continue;
2530                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2531                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2532         }
2533
2534         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2535             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2536                 for (i = 0; i < 12; i++) {
2537                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2538                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2539                 }
2540         }
2541
2542         addr_high = (tp->dev->dev_addr[0] +
2543                      tp->dev->dev_addr[1] +
2544                      tp->dev->dev_addr[2] +
2545                      tp->dev->dev_addr[3] +
2546                      tp->dev->dev_addr[4] +
2547                      tp->dev->dev_addr[5]) &
2548                 TX_BACKOFF_SEED_MASK;
2549         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2550 }
2551
2552 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2553 {
2554         u32 misc_host_ctrl;
2555         bool device_should_wake, do_low_power;
2556
2557         /* Make sure register accesses (indirect or otherwise)
2558          * will function correctly.
2559          */
2560         pci_write_config_dword(tp->pdev,
2561                                TG3PCI_MISC_HOST_CTRL,
2562                                tp->misc_host_ctrl);
2563
2564         switch (state) {
2565         case PCI_D0:
2566                 pci_enable_wake(tp->pdev, state, false);
2567                 pci_set_power_state(tp->pdev, PCI_D0);
2568
2569                 /* Switch out of Vaux if it is a NIC */
2570                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2571                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2572
2573                 return 0;
2574
2575         case PCI_D1:
2576         case PCI_D2:
2577         case PCI_D3hot:
2578                 break;
2579
2580         default:
2581                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2582                            state);
2583                 return -EINVAL;
2584         }
2585
2586         /* Restore the CLKREQ setting. */
2587         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2588                 u16 lnkctl;
2589
2590                 pci_read_config_word(tp->pdev,
2591                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2592                                      &lnkctl);
2593                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2594                 pci_write_config_word(tp->pdev,
2595                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2596                                       lnkctl);
2597         }
2598
2599         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2600         tw32(TG3PCI_MISC_HOST_CTRL,
2601              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2602
2603         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2604                              device_may_wakeup(&tp->pdev->dev) &&
2605                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2606
2607         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2608                 do_low_power = false;
2609                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2610                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2611                         struct phy_device *phydev;
2612                         u32 phyid, advertising;
2613
2614                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2615
2616                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2617
2618                         tp->link_config.orig_speed = phydev->speed;
2619                         tp->link_config.orig_duplex = phydev->duplex;
2620                         tp->link_config.orig_autoneg = phydev->autoneg;
2621                         tp->link_config.orig_advertising = phydev->advertising;
2622
2623                         advertising = ADVERTISED_TP |
2624                                       ADVERTISED_Pause |
2625                                       ADVERTISED_Autoneg |
2626                                       ADVERTISED_10baseT_Half;
2627
2628                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2629                             device_should_wake) {
2630                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2631                                         advertising |=
2632                                                 ADVERTISED_100baseT_Half |
2633                                                 ADVERTISED_100baseT_Full |
2634                                                 ADVERTISED_10baseT_Full;
2635                                 else
2636                                         advertising |= ADVERTISED_10baseT_Full;
2637                         }
2638
2639                         phydev->advertising = advertising;
2640
2641                         phy_start_aneg(phydev);
2642
2643                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2644                         if (phyid != PHY_ID_BCMAC131) {
2645                                 phyid &= PHY_BCM_OUI_MASK;
2646                                 if (phyid == PHY_BCM_OUI_1 ||
2647                                     phyid == PHY_BCM_OUI_2 ||
2648                                     phyid == PHY_BCM_OUI_3)
2649                                         do_low_power = true;
2650                         }
2651                 }
2652         } else {
2653                 do_low_power = true;
2654
2655                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2656                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2657                         tp->link_config.orig_speed = tp->link_config.speed;
2658                         tp->link_config.orig_duplex = tp->link_config.duplex;
2659                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2660                 }
2661
2662                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2663                         tp->link_config.speed = SPEED_10;
2664                         tp->link_config.duplex = DUPLEX_HALF;
2665                         tp->link_config.autoneg = AUTONEG_ENABLE;
2666                         tg3_setup_phy(tp, 0);
2667                 }
2668         }
2669
2670         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2671                 u32 val;
2672
2673                 val = tr32(GRC_VCPU_EXT_CTRL);
2674                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2675         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2676                 int i;
2677                 u32 val;
2678
2679                 for (i = 0; i < 200; i++) {
2680                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2681                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2682                                 break;
2683                         msleep(1);
2684                 }
2685         }
2686         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2687                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2688                                                      WOL_DRV_STATE_SHUTDOWN |
2689                                                      WOL_DRV_WOL |
2690                                                      WOL_SET_MAGIC_PKT);
2691
2692         if (device_should_wake) {
2693                 u32 mac_mode;
2694
2695                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2696                         if (do_low_power) {
2697                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2698                                 udelay(40);
2699                         }
2700
2701                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2702                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2703                         else
2704                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2705
2706                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2707                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2708                             ASIC_REV_5700) {
2709                                 u32 speed = (tp->tg3_flags &
2710                                              TG3_FLAG_WOL_SPEED_100MB) ?
2711                                              SPEED_100 : SPEED_10;
2712                                 if (tg3_5700_link_polarity(tp, speed))
2713                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2714                                 else
2715                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2716                         }
2717                 } else {
2718                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2719                 }
2720
2721                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2722                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2723
2724                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2725                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2726                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2727                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2728                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2729                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2730
2731                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2732                         mac_mode |= tp->mac_mode &
2733                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2734                         if (mac_mode & MAC_MODE_APE_TX_EN)
2735                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2736                 }
2737
2738                 tw32_f(MAC_MODE, mac_mode);
2739                 udelay(100);
2740
2741                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2742                 udelay(10);
2743         }
2744
2745         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2746             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2747              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2748                 u32 base_val;
2749
2750                 base_val = tp->pci_clock_ctrl;
2751                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2752                              CLOCK_CTRL_TXCLK_DISABLE);
2753
2754                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2755                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2756         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2757                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2758                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2759                 /* do nothing */
2760         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2761                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2762                 u32 newbits1, newbits2;
2763
2764                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2765                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2766                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2767                                     CLOCK_CTRL_TXCLK_DISABLE |
2768                                     CLOCK_CTRL_ALTCLK);
2769                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2770                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2771                         newbits1 = CLOCK_CTRL_625_CORE;
2772                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2773                 } else {
2774                         newbits1 = CLOCK_CTRL_ALTCLK;
2775                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2776                 }
2777
2778                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2779                             40);
2780
2781                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2782                             40);
2783
2784                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2785                         u32 newbits3;
2786
2787                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2788                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2789                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2790                                             CLOCK_CTRL_TXCLK_DISABLE |
2791                                             CLOCK_CTRL_44MHZ_CORE);
2792                         } else {
2793                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2794                         }
2795
2796                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2797                                     tp->pci_clock_ctrl | newbits3, 40);
2798                 }
2799         }
2800
2801         if (!(device_should_wake) &&
2802             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2803                 tg3_power_down_phy(tp, do_low_power);
2804
2805         tg3_frob_aux_power(tp);
2806
2807         /* Workaround for unstable PLL clock */
2808         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2809             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2810                 u32 val = tr32(0x7d00);
2811
2812                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2813                 tw32(0x7d00, val);
2814                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2815                         int err;
2816
2817                         err = tg3_nvram_lock(tp);
2818                         tg3_halt_cpu(tp, RX_CPU_BASE);
2819                         if (!err)
2820                                 tg3_nvram_unlock(tp);
2821                 }
2822         }
2823
2824         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2825
2826         if (device_should_wake)
2827                 pci_enable_wake(tp->pdev, state, true);
2828
2829         /* Finally, set the new power state. */
2830         pci_set_power_state(tp->pdev, state);
2831
2832         return 0;
2833 }
2834
2835 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2836 {
2837         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2838         case MII_TG3_AUX_STAT_10HALF:
2839                 *speed = SPEED_10;
2840                 *duplex = DUPLEX_HALF;
2841                 break;
2842
2843         case MII_TG3_AUX_STAT_10FULL:
2844                 *speed = SPEED_10;
2845                 *duplex = DUPLEX_FULL;
2846                 break;
2847
2848         case MII_TG3_AUX_STAT_100HALF:
2849                 *speed = SPEED_100;
2850                 *duplex = DUPLEX_HALF;
2851                 break;
2852
2853         case MII_TG3_AUX_STAT_100FULL:
2854                 *speed = SPEED_100;
2855                 *duplex = DUPLEX_FULL;
2856                 break;
2857
2858         case MII_TG3_AUX_STAT_1000HALF:
2859                 *speed = SPEED_1000;
2860                 *duplex = DUPLEX_HALF;
2861                 break;
2862
2863         case MII_TG3_AUX_STAT_1000FULL:
2864                 *speed = SPEED_1000;
2865                 *duplex = DUPLEX_FULL;
2866                 break;
2867
2868         default:
2869                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2870                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2871                                  SPEED_10;
2872                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2873                                   DUPLEX_HALF;
2874                         break;
2875                 }
2876                 *speed = SPEED_INVALID;
2877                 *duplex = DUPLEX_INVALID;
2878                 break;
2879         }
2880 }
2881
2882 static void tg3_phy_copper_begin(struct tg3 *tp)
2883 {
2884         u32 new_adv;
2885         int i;
2886
2887         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2888                 /* Entering low power mode.  Disable gigabit and
2889                  * 100baseT advertisements.
2890                  */
2891                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2892
2893                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2894                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2895                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2896                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2897
2898                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2899         } else if (tp->link_config.speed == SPEED_INVALID) {
2900                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2901                         tp->link_config.advertising &=
2902                                 ~(ADVERTISED_1000baseT_Half |
2903                                   ADVERTISED_1000baseT_Full);
2904
2905                 new_adv = ADVERTISE_CSMA;
2906                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2907                         new_adv |= ADVERTISE_10HALF;
2908                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2909                         new_adv |= ADVERTISE_10FULL;
2910                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2911                         new_adv |= ADVERTISE_100HALF;
2912                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2913                         new_adv |= ADVERTISE_100FULL;
2914
2915                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2916
2917                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2918
2919                 if (tp->link_config.advertising &
2920                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2921                         new_adv = 0;
2922                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2923                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2924                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2925                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2926                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2927                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2928                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2929                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2930                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2931                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2932                 } else {
2933                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2934                 }
2935         } else {
2936                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2937                 new_adv |= ADVERTISE_CSMA;
2938
2939                 /* Asking for a specific link mode. */
2940                 if (tp->link_config.speed == SPEED_1000) {
2941                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2942
2943                         if (tp->link_config.duplex == DUPLEX_FULL)
2944                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2945                         else
2946                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2947                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2948                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2949                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2950                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2951                 } else {
2952                         if (tp->link_config.speed == SPEED_100) {
2953                                 if (tp->link_config.duplex == DUPLEX_FULL)
2954                                         new_adv |= ADVERTISE_100FULL;
2955                                 else
2956                                         new_adv |= ADVERTISE_100HALF;
2957                         } else {
2958                                 if (tp->link_config.duplex == DUPLEX_FULL)
2959                                         new_adv |= ADVERTISE_10FULL;
2960                                 else
2961                                         new_adv |= ADVERTISE_10HALF;
2962                         }
2963                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2964
2965                         new_adv = 0;
2966                 }
2967
2968                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2969         }
2970
2971         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2972                 u32 val = 0;
2973
2974                 tw32(TG3_CPMU_EEE_MODE,
2975                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2976
2977                 /* Enable SM_DSP clock and tx 6dB coding. */
2978                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2979                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2980                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2981                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2982
2983                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2984                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2985                     !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2986                         tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
2987                                          val | MII_TG3_DSP_CH34TP2_HIBW01);
2988
2989                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2990                         /* Advertise 100-BaseTX EEE ability */
2991                         if (tp->link_config.advertising &
2992                             (ADVERTISED_100baseT_Half |
2993                              ADVERTISED_100baseT_Full))
2994                                 val |= TG3_CL45_D7_EEEADV_CAP_100TX;
2995                         /* Advertise 1000-BaseT EEE ability */
2996                         if (tp->link_config.advertising &
2997                             (ADVERTISED_1000baseT_Half |
2998                              ADVERTISED_1000baseT_Full))
2999                                 val |= TG3_CL45_D7_EEEADV_CAP_1000T;
3000                 }
3001                 tg3_phy_cl45_write(tp, 0x7, TG3_CL45_D7_EEEADV_CAP, val);
3002
3003                 /* Turn off SM_DSP clock. */
3004                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3005                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3006                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3007         }
3008
3009         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3010             tp->link_config.speed != SPEED_INVALID) {
3011                 u32 bmcr, orig_bmcr;
3012
3013                 tp->link_config.active_speed = tp->link_config.speed;
3014                 tp->link_config.active_duplex = tp->link_config.duplex;
3015
3016                 bmcr = 0;
3017                 switch (tp->link_config.speed) {
3018                 default:
3019                 case SPEED_10:
3020                         break;
3021
3022                 case SPEED_100:
3023                         bmcr |= BMCR_SPEED100;
3024                         break;
3025
3026                 case SPEED_1000:
3027                         bmcr |= TG3_BMCR_SPEED1000;
3028                         break;
3029                 }
3030
3031                 if (tp->link_config.duplex == DUPLEX_FULL)
3032                         bmcr |= BMCR_FULLDPLX;
3033
3034                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3035                     (bmcr != orig_bmcr)) {
3036                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3037                         for (i = 0; i < 1500; i++) {
3038                                 u32 tmp;
3039
3040                                 udelay(10);
3041                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3042                                     tg3_readphy(tp, MII_BMSR, &tmp))
3043                                         continue;
3044                                 if (!(tmp & BMSR_LSTATUS)) {
3045                                         udelay(40);
3046                                         break;
3047                                 }
3048                         }
3049                         tg3_writephy(tp, MII_BMCR, bmcr);
3050                         udelay(40);
3051                 }
3052         } else {
3053                 tg3_writephy(tp, MII_BMCR,
3054                              BMCR_ANENABLE | BMCR_ANRESTART);
3055         }
3056 }
3057
3058 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3059 {
3060         int err;
3061
3062         /* Turn off tap power management. */
3063         /* Set Extended packet length bit */
3064         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3065
3066         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3067         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3068         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3069         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3070         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3071
3072         udelay(40);
3073
3074         return err;
3075 }
3076
3077 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3078 {
3079         u32 adv_reg, all_mask = 0;
3080
3081         if (mask & ADVERTISED_10baseT_Half)
3082                 all_mask |= ADVERTISE_10HALF;
3083         if (mask & ADVERTISED_10baseT_Full)
3084                 all_mask |= ADVERTISE_10FULL;
3085         if (mask & ADVERTISED_100baseT_Half)
3086                 all_mask |= ADVERTISE_100HALF;
3087         if (mask & ADVERTISED_100baseT_Full)
3088                 all_mask |= ADVERTISE_100FULL;
3089
3090         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3091                 return 0;
3092
3093         if ((adv_reg & all_mask) != all_mask)
3094                 return 0;
3095         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3096                 u32 tg3_ctrl;
3097
3098                 all_mask = 0;
3099                 if (mask & ADVERTISED_1000baseT_Half)
3100                         all_mask |= ADVERTISE_1000HALF;
3101                 if (mask & ADVERTISED_1000baseT_Full)
3102                         all_mask |= ADVERTISE_1000FULL;
3103
3104                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3105                         return 0;
3106
3107                 if ((tg3_ctrl & all_mask) != all_mask)
3108                         return 0;
3109         }
3110         return 1;
3111 }
3112
3113 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3114 {
3115         u32 curadv, reqadv;
3116
3117         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3118                 return 1;
3119
3120         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3121         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3122
3123         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3124                 if (curadv != reqadv)
3125                         return 0;
3126
3127                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3128                         tg3_readphy(tp, MII_LPA, rmtadv);
3129         } else {
3130                 /* Reprogram the advertisement register, even if it
3131                  * does not affect the current link.  If the link
3132                  * gets renegotiated in the future, we can save an
3133                  * additional renegotiation cycle by advertising
3134                  * it correctly in the first place.
3135                  */
3136                 if (curadv != reqadv) {
3137                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3138                                      ADVERTISE_PAUSE_ASYM);
3139                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3140                 }
3141         }
3142
3143         return 1;
3144 }
3145
3146 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3147 {
3148         int current_link_up;
3149         u32 bmsr, val;
3150         u32 lcl_adv, rmt_adv;
3151         u16 current_speed;
3152         u8 current_duplex;
3153         int i, err;
3154
3155         tw32(MAC_EVENT, 0);
3156
3157         tw32_f(MAC_STATUS,
3158              (MAC_STATUS_SYNC_CHANGED |
3159               MAC_STATUS_CFG_CHANGED |
3160               MAC_STATUS_MI_COMPLETION |
3161               MAC_STATUS_LNKSTATE_CHANGED));
3162         udelay(40);
3163
3164         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3165                 tw32_f(MAC_MI_MODE,
3166                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));