drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47
  48 char ixgbe_driver_name[] = "ixgbe";
  49 static const char ixgbe_driver_string[] =
  50                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  51
  52 #define DRV_VERSION "2.0.37-k2"
  53 const char ixgbe_driver_version[] = DRV_VERSION;
  54 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  55
  56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  57         [board_82598] = &ixgbe_82598_info,
  58         [board_82599] = &ixgbe_82599_info,
  59 };
  60
  61 /* ixgbe_pci_tbl - PCI Device ID Table
  62  *
  63  * Wildcard entries (PCI_ANY_ID) should come last
  64  * Last entry must be all 0s
  65  *
  66  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  67  *   Class, Class Mask, private data (not used) }
  68  */
  69 static struct pci_device_id ixgbe_pci_tbl[] = {
  70         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  71          board_82598 },
  72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  73          board_82598 },
  74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  75          board_82598 },
  76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  77          board_82598 },
  78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  79          board_82598 },
  80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  81          board_82598 },
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  93          board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  95          board_82599 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  97          board_82599 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  99          board_82599 },
 100
 101         /* required last entry */
 102         {0, }
 103 };
 104 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 105
 106 #ifdef CONFIG_IXGBE_DCA
 107 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 108                             void *p);
 109 static struct notifier_block dca_notifier = {
 110         .notifier_call = ixgbe_notify_dca,
 111         .next          = NULL,
 112         .priority      = 0
 113 };
 114 #endif
 115
 116 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 117 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 118 MODULE_LICENSE("GPL");
 119 MODULE_VERSION(DRV_VERSION);
 120
 121 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 122
 123 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 124 {
 125         u32 ctrl_ext;
 126
 127         /* Let firmware take over control of h/w */
 128         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 129         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 130                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 131 }
 132
 133 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 134 {
 135         u32 ctrl_ext;
 136
 137         /* Let firmware know the driver has taken over */
 138         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 139         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 140                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 141 }
 142
 143 /*
 144  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 145  * @adapter: pointer to adapter struct
 146  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 147  * @queue: queue to map the corresponding interrupt to
 148  * @msix_vector: the vector to map to the corresponding queue
 149  *
 150  */
 151 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 152                            u8 queue, u8 msix_vector)
 153 {
 154         u32 ivar, index;
 155         struct ixgbe_hw *hw = &adapter->hw;
 156         switch (hw->mac.type) {
 157         case ixgbe_mac_82598EB:
 158                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 159                 if (direction == -1)
 160                         direction = 0;
 161                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 162                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 163                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 164                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 165                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 166                 break;
 167         case ixgbe_mac_82599EB:
 168                 if (direction == -1) {
 169                         /* other causes */
 170                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 171                         index = ((queue & 1) * 8);
 172                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 173                         ivar &= ~(0xFF << index);
 174                         ivar |= (msix_vector << index);
 175                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 176                         break;
 177                 } else {
 178                         /* tx or rx causes */
 179                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 180                         index = ((16 * (queue & 1)) + (8 * direction));
 181                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 182                         ivar &= ~(0xFF << index);
 183                         ivar |= (msix_vector << index);
 184                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 185                         break;
 186                 }
 187         default:
 188                 break;
 189         }
 190 }
 191
 192 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 193                                           u64 qmask)
 194 {
 195         u32 mask;
 196
 197         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 198                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 199                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 200         } else {
 201                 mask = (qmask & 0xFFFFFFFF);
 202                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 203                 mask = (qmask >> 32);
 204                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 205         }
 206 }
 207
 208 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 209                                              struct ixgbe_tx_buffer
 210                                              *tx_buffer_info)
 211 {
 212         tx_buffer_info->dma = 0;
 213         if (tx_buffer_info->skb) {
 214                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 215                               DMA_TO_DEVICE);
 216                 dev_kfree_skb_any(tx_buffer_info->skb);
 217                 tx_buffer_info->skb = NULL;
 218         }
 219         tx_buffer_info->time_stamp = 0;
 220         /* tx_buffer_info must be completely set up in the transmit path */
 221 }
 222
 223 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 224                                        struct ixgbe_ring *tx_ring,
 225                                        unsigned int eop)
 226 {
 227         struct ixgbe_hw *hw = &adapter->hw;
 228
 229         /* Detect a transmit hang in hardware, this serializes the
 230          * check with the clearing of time_stamp and movement of eop */
 231         adapter->detect_tx_hung = false;
 232         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 233             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 234             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 235                 /* detected Tx unit hang */
 236                 union ixgbe_adv_tx_desc *tx_desc;
 237                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 238                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 239                         "  Tx Queue             <%d>\n"
 240                         "  TDH, TDT             <%x>, <%x>\n"
 241                         "  next_to_use          <%x>\n"
 242                         "  next_to_clean        <%x>\n"
 243                         "tx_buffer_info[next_to_clean]\n"
 244                         "  time_stamp           <%lx>\n"
 245                         "  jiffies              <%lx>\n",
 246                         tx_ring->queue_index,
 247                         IXGBE_READ_REG(hw, tx_ring->head),
 248                         IXGBE_READ_REG(hw, tx_ring->tail),
 249                         tx_ring->next_to_use, eop,
 250                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 251                 return true;
 252         }
 253
 254         return false;
 255 }
 256
 257 #define IXGBE_MAX_TXD_PWR       14
 258 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 259
 260 /* Tx Descriptors needed, worst case */
 261 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 262                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 263 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 264         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 265
 266 static void ixgbe_tx_timeout(struct net_device *netdev);
 267
 268 /**
 269  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 270  * @q_vector: structure containing interrupt and ring information
 271  * @tx_ring: tx ring to clean
 272  **/
 273 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 274                                struct ixgbe_ring *tx_ring)
 275 {
 276         struct ixgbe_adapter *adapter = q_vector->adapter;
 277         struct net_device *netdev = adapter->netdev;
 278         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 279         struct ixgbe_tx_buffer *tx_buffer_info;
 280         unsigned int i, eop, count = 0;
 281         unsigned int total_bytes = 0, total_packets = 0;
 282
 283         i = tx_ring->next_to_clean;
 284         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 285         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 286
 287         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 288                (count < tx_ring->work_limit)) {
 289                 bool cleaned = false;
 290                 for ( ; !cleaned; count++) {
 291                         struct sk_buff *skb;
 292                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 293                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 294                         cleaned = (i == eop);
 295                         skb = tx_buffer_info->skb;
 296
 297                         if (cleaned && skb) {
 298                                 unsigned int segs, bytecount;
 299                                 unsigned int hlen = skb_headlen(skb);
 300
 301                                 /* gso_segs is currently only valid for tcp */
 302                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 303 #ifdef IXGBE_FCOE
 304                                 /* adjust for FCoE Sequence Offload */
 305                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 306                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 307                                     skb_is_gso(skb)) {
 308                                         hlen = skb_transport_offset(skb) +
 309                                                 sizeof(struct fc_frame_header) +
 310                                                 sizeof(struct fcoe_crc_eof);
 311                                         segs = DIV_ROUND_UP(skb->len - hlen,
 312                                                 skb_shinfo(skb)->gso_size);
 313                                 }
 314 #endif /* IXGBE_FCOE */
 315                                 /* multiply data chunks by size of headers */
 316                                 bytecount = ((segs - 1) * hlen) + skb->len;
 317                                 total_packets += segs;
 318                                 total_bytes += bytecount;
 319                         }
 320
 321                         ixgbe_unmap_and_free_tx_resource(adapter,
 322                                                          tx_buffer_info);
 323
 324                         tx_desc->wb.status = 0;
 325
 326                         i++;
 327                         if (i == tx_ring->count)
 328                                 i = 0;
 329                 }
 330
 331                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 332                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 333         }
 334
 335         tx_ring->next_to_clean = i;
 336
 337 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 338         if (unlikely(count && netif_carrier_ok(netdev) &&
 339                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 340                 /* Make sure that anybody stopping the queue after this
 341                  * sees the new next_to_clean.
 342                  */
 343                 smp_mb();
 344                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 345                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 346                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 347                         ++adapter->restart_queue;
 348                 }
 349         }
 350
 351         if (adapter->detect_tx_hung) {
 352                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 353                         /* schedule immediate reset if we believe we hung */
 354                         DPRINTK(PROBE, INFO,
 355                                 "tx hang %d detected, resetting adapter\n",
 356                                 adapter->tx_timeout_count + 1);
 357                         ixgbe_tx_timeout(adapter->netdev);
 358                 }
 359         }
 360
 361         /* re-arm the interrupt */
 362         if (count >= tx_ring->work_limit)
 363                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 364
 365         tx_ring->total_bytes += total_bytes;
 366         tx_ring->total_packets += total_packets;
 367         tx_ring->stats.packets += total_packets;
 368         tx_ring->stats.bytes += total_bytes;
 369         adapter->net_stats.tx_bytes += total_bytes;
 370         adapter->net_stats.tx_packets += total_packets;
 371         return (count < tx_ring->work_limit);
 372 }
 373
 374 #ifdef CONFIG_IXGBE_DCA
 375 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 376                                 struct ixgbe_ring *rx_ring)
 377 {
 378         u32 rxctrl;
 379         int cpu = get_cpu();
 380         int q = rx_ring - adapter->rx_ring;
 381
 382         if (rx_ring->cpu != cpu) {
 383                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 384                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 385                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 386                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 387                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 388                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 389                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 390                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 391                 }
 392                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 393                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 394                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 395                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 396                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 397                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 398                 rx_ring->cpu = cpu;
 399         }
 400         put_cpu();
 401 }
 402
 403 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 404                                 struct ixgbe_ring *tx_ring)
 405 {
 406         u32 txctrl;
 407         int cpu = get_cpu();
 408         int q = tx_ring - adapter->tx_ring;
 409
 410         if (tx_ring->cpu != cpu) {
 411                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 412                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 413                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 414                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 415                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 416                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 417                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 418                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 419                 }
 420                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 421                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 422                 tx_ring->cpu = cpu;
 423         }
 424         put_cpu();
 425 }
 426
 427 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 428 {
 429         int i;
 430
 431         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 432                 return;
 433
 434         /* always use CB2 mode, difference is masked in the CB driver */
 435         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 436
 437         for (i = 0; i < adapter->num_tx_queues; i++) {
 438                 adapter->tx_ring[i].cpu = -1;
 439                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 440         }
 441         for (i = 0; i < adapter->num_rx_queues; i++) {
 442                 adapter->rx_ring[i].cpu = -1;
 443                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 444         }
 445 }
 446
 447 static int __ixgbe_notify_dca(struct device *dev, void *data)
 448 {
 449         struct net_device *netdev = dev_get_drvdata(dev);
 450         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 451         unsigned long event = *(unsigned long *)data;
 452
 453         switch (event) {
 454         case DCA_PROVIDER_ADD:
 455                 /* if we're already enabled, don't do it again */
 456                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 457                         break;
 458                 if (dca_add_requester(dev) == 0) {
 459                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 460                         ixgbe_setup_dca(adapter);
 461                         break;
 462                 }
 463                 /* Fall Through since DCA is disabled. */
 464         case DCA_PROVIDER_REMOVE:
 465                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 466                         dca_remove_requester(dev);
 467                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 468                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 469                 }
 470                 break;
 471         }
 472
 473         return 0;
 474 }
 475
 476 #endif /* CONFIG_IXGBE_DCA */
 477 /**
 478  * ixgbe_receive_skb - Send a completed packet up the stack
 479  * @adapter: board private structure
 480  * @skb: packet to send up
 481  * @status: hardware indication of status of receive
 482  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 483  * @rx_desc: rx descriptor
 484  **/
 485 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 486                               struct sk_buff *skb, u8 status,
 487                               struct ixgbe_ring *ring,
 488                               union ixgbe_adv_rx_desc *rx_desc)
 489 {
 490         struct ixgbe_adapter *adapter = q_vector->adapter;
 491         struct napi_struct *napi = &q_vector->napi;
 492         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 493         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 494
 495         skb_record_rx_queue(skb, ring->queue_index);
 496         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 497                 if (adapter->vlgrp && is_vlan && (tag != 0))
 498                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 499                 else
 500                         napi_gro_receive(napi, skb);
 501         } else {
 502                 if (adapter->vlgrp && is_vlan && (tag != 0))
 503                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 504                 else
 505                         netif_rx(skb);
 506         }
 507 }
 508
 509 /**
 510  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 511  * @adapter: address of board private structure
 512  * @status_err: hardware indication of status of receive
 513  * @skb: skb currently being received and modified
 514  **/
 515 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 516                                      u32 status_err, struct sk_buff *skb)
 517 {
 518         skb->ip_summed = CHECKSUM_NONE;
 519
 520         /* Rx csum disabled */
 521         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 522                 return;
 523
 524         /* if IP and error */
 525         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 526             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 527                 adapter->hw_csum_rx_error++;
 528                 return;
 529         }
 530
 531         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 532                 return;
 533
 534         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 535                 adapter->hw_csum_rx_error++;
 536                 return;
 537         }
 538
 539         /* It must be a TCP or UDP packet with a valid checksum */
 540         skb->ip_summed = CHECKSUM_UNNECESSARY;
 541         adapter->hw_csum_rx_good++;
 542 }
 543
 544 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 545                                          struct ixgbe_ring *rx_ring, u32 val)
 546 {
 547         /*
 548          * Force memory writes to complete before letting h/w
 549          * know there are new descriptors to fetch.  (Only
 550          * applicable for weak-ordered memory model archs,
 551          * such as IA-64).
 552          */
 553         wmb();
 554         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 555 }
 556
 557 /**
 558  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 559  * @adapter: address of board private structure
 560  **/
 561 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 562                                    struct ixgbe_ring *rx_ring,
 563                                    int cleaned_count)
 564 {
 565         struct pci_dev *pdev = adapter->pdev;
 566         union ixgbe_adv_rx_desc *rx_desc;
 567         struct ixgbe_rx_buffer *bi;
 568         unsigned int i;
 569
 570         i = rx_ring->next_to_use;
 571         bi = &rx_ring->rx_buffer_info[i];
 572
 573         while (cleaned_count--) {
 574                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 575
 576                 if (!bi->page_dma &&
 577                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
 578                         if (!bi->page) {
 579                                 bi->page = alloc_page(GFP_ATOMIC);
 580                                 if (!bi->page) {
 581                                         adapter->alloc_rx_page_failed++;
 582                                         goto no_buffers;
 583                                 }
 584                                 bi->page_offset = 0;
 585                         } else {
 586                                 /* use a half page if we're re-using */
 587                                 bi->page_offset ^= (PAGE_SIZE / 2);
 588                         }
 589
 590                         bi->page_dma = pci_map_page(pdev, bi->page,
 591                                                     bi->page_offset,
 592                                                     (PAGE_SIZE / 2),
 593                                                     PCI_DMA_FROMDEVICE);
 594                 }
 595
 596                 if (!bi->skb) {
 597                         struct sk_buff *skb;
 598                         skb = netdev_alloc_skb(adapter->netdev,
 599                                                (rx_ring->rx_buf_len +
 600                                                 NET_IP_ALIGN));
 601
 602                         if (!skb) {
 603                                 adapter->alloc_rx_buff_failed++;
 604                                 goto no_buffers;
 605                         }
 606
 607                         /*
 608                          * Make buffer alignment 2 beyond a 16 byte boundary
 609                          * this will result in a 16 byte aligned IP header after
 610                          * the 14 byte MAC header is removed
 611                          */
 612                         skb_reserve(skb, NET_IP_ALIGN);
 613
 614                         bi->skb = skb;
 615                         bi->dma = pci_map_single(pdev, skb->data,
 616                                                  rx_ring->rx_buf_len,
 617                                                  PCI_DMA_FROMDEVICE);
 618                 }
 619                 /* Refresh the desc even if buffer_addrs didn't change because
 620                  * each write-back erases this info. */
 621                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 622                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 623                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 624                 } else {
 625                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 626                 }
 627
 628                 i++;
 629                 if (i == rx_ring->count)
 630                         i = 0;
 631                 bi = &rx_ring->rx_buffer_info[i];
 632         }
 633
 634 no_buffers:
 635         if (rx_ring->next_to_use != i) {
 636                 rx_ring->next_to_use = i;
 637                 if (i-- == 0)
 638                         i = (rx_ring->count - 1);
 639
 640                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 641         }
 642 }
 643
 644 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 645 {
 646         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 647 }
 648
 649 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 650 {
 651         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 652 }
 653
 654 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 655 {
 656         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 657                 IXGBE_RXDADV_RSCCNT_MASK) >>
 658                 IXGBE_RXDADV_RSCCNT_SHIFT;
 659 }
 660
 661 /**
 662  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 663  * @skb: pointer to the last skb in the rsc queue
 664  *
 665  * This function changes a queue full of hw rsc buffers into a completed
 666  * packet.  It uses the ->prev pointers to find the first packet and then
 667  * turns it into the frag list owner.
 668  **/
 669 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 670 {
 671         unsigned int frag_list_size = 0;
 672
 673         while (skb->prev) {
 674                 struct sk_buff *prev = skb->prev;
 675                 frag_list_size += skb->len;
 676                 skb->prev = NULL;
 677                 skb = prev;
 678         }
 679
 680         skb_shinfo(skb)->frag_list = skb->next;
 681         skb->next = NULL;
 682         skb->len += frag_list_size;
 683         skb->data_len += frag_list_size;
 684         skb->truesize += frag_list_size;
 685         return skb;
 686 }
 687
 688 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 689                                struct ixgbe_ring *rx_ring,
 690                                int *work_done, int work_to_do)
 691 {
 692         struct ixgbe_adapter *adapter = q_vector->adapter;
 693         struct pci_dev *pdev = adapter->pdev;
 694         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 695         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 696         struct sk_buff *skb;
 697         unsigned int i, rsc_count = 0;
 698         u32 len, staterr;
 699         u16 hdr_info;
 700         bool cleaned = false;
 701         int cleaned_count = 0;
 702         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 703 #ifdef IXGBE_FCOE
 704         int ddp_bytes = 0;
 705 #endif /* IXGBE_FCOE */
 706
 707         i = rx_ring->next_to_clean;
 708         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 709         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 710         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 711
 712         while (staterr & IXGBE_RXD_STAT_DD) {
 713                 u32 upper_len = 0;
 714                 if (*work_done >= work_to_do)
 715                         break;
 716                 (*work_done)++;
 717
 718                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 719                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 720                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 721                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 722                         if (hdr_info & IXGBE_RXDADV_SPH)
 723                                 adapter->rx_hdr_split++;
 724                         if (len > IXGBE_RX_HDR_SIZE)
 725                                 len = IXGBE_RX_HDR_SIZE;
 726                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 727                 } else {
 728                         len = le16_to_cpu(rx_desc->wb.upper.length);
 729                 }
 730
 731                 cleaned = true;
 732                 skb = rx_buffer_info->skb;
 733                 prefetch(skb->data - NET_IP_ALIGN);
 734                 rx_buffer_info->skb = NULL;
 735
 736                 if (rx_buffer_info->dma) {
 737                         pci_unmap_single(pdev, rx_buffer_info->dma,
 738                                          rx_ring->rx_buf_len,
 739                                          PCI_DMA_FROMDEVICE);
 740                         rx_buffer_info->dma = 0;
 741                         skb_put(skb, len);
 742                 }
 743
 744                 if (upper_len) {
 745                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 746                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 747                         rx_buffer_info->page_dma = 0;
 748                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 749                                            rx_buffer_info->page,
 750                                            rx_buffer_info->page_offset,
 751                                            upper_len);
 752
 753                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 754                             (page_count(rx_buffer_info->page) != 1))
 755                                 rx_buffer_info->page = NULL;
 756                         else
 757                                 get_page(rx_buffer_info->page);
 758
 759                         skb->len += upper_len;
 760                         skb->data_len += upper_len;
 761                         skb->truesize += upper_len;
 762                 }
 763
 764                 i++;
 765                 if (i == rx_ring->count)
 766                         i = 0;
 767
 768                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 769                 prefetch(next_rxd);
 770                 cleaned_count++;
 771
 772                 if (adapter->flags & IXGBE_FLAG2_RSC_CAPABLE)
 773                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 774
 775                 if (rsc_count) {
 776                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 777                                      IXGBE_RXDADV_NEXTP_SHIFT;
 778                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 779                         rx_ring->rsc_count += (rsc_count - 1);
 780                 } else {
 781                         next_buffer = &rx_ring->rx_buffer_info[i];
 782                 }
 783
 784                 if (staterr & IXGBE_RXD_STAT_EOP) {
 785                         if (skb->prev)
 786                                 skb = ixgbe_transform_rsc_queue(skb);
 787                         rx_ring->stats.packets++;
 788                         rx_ring->stats.bytes += skb->len;
 789                 } else {
 790                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 791                                 rx_buffer_info->skb = next_buffer->skb;
 792                                 rx_buffer_info->dma = next_buffer->dma;
 793                                 next_buffer->skb = skb;
 794                                 next_buffer->dma = 0;
 795                         } else {
 796                                 skb->next = next_buffer->skb;
 797                                 skb->next->prev = skb;
 798                         }
 799                         adapter->non_eop_descs++;
 800                         goto next_desc;
 801                 }
 802
 803                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 804                         dev_kfree_skb_irq(skb);
 805                         goto next_desc;
 806                 }
 807
 808                 ixgbe_rx_checksum(adapter, staterr, skb);
 809
 810                 /* probably a little skewed due to removing CRC */
 811                 total_rx_bytes += skb->len;
 812                 total_rx_packets++;
 813
 814                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 815 #ifdef IXGBE_FCOE
 816                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 817                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 818                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 819                         if (!ddp_bytes)
 820                                 goto next_desc;
 821                 }
 822 #endif /* IXGBE_FCOE */
 823                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 824
 825 next_desc:
 826                 rx_desc->wb.upper.status_error = 0;
 827
 828                 /* return some buffers to hardware, one at a time is too slow */
 829                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 830                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 831                         cleaned_count = 0;
 832                 }
 833
 834                 /* use prefetched values */
 835                 rx_desc = next_rxd;
 836                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 837
 838                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 839         }
 840
 841         rx_ring->next_to_clean = i;
 842         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 843
 844         if (cleaned_count)
 845                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 846
 847 #ifdef IXGBE_FCOE
 848         /* include DDPed FCoE data */
 849         if (ddp_bytes > 0) {
 850                 unsigned int mss;
 851
 852                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 853                         sizeof(struct fc_frame_header) -
 854                         sizeof(struct fcoe_crc_eof);
 855                 if (mss > 512)
 856                         mss &= ~511;
 857                 total_rx_bytes += ddp_bytes;
 858                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 859         }
 860 #endif /* IXGBE_FCOE */
 861
 862         rx_ring->total_packets += total_rx_packets;
 863         rx_ring->total_bytes += total_rx_bytes;
 864         adapter->net_stats.rx_bytes += total_rx_bytes;
 865         adapter->net_stats.rx_packets += total_rx_packets;
 866
 867         return cleaned;
 868 }
 869
 870 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 871 /**
 872  * ixgbe_configure_msix - Configure MSI-X hardware
 873  * @adapter: board private structure
 874  *
 875  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 876  * interrupts.
 877  **/
 878 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 879 {
 880         struct ixgbe_q_vector *q_vector;
 881         int i, j, q_vectors, v_idx, r_idx;
 882         u32 mask;
 883
 884         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 885
 886         /*
 887          * Populate the IVAR table and set the ITR values to the
 888          * corresponding register.
 889          */
 890         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 891                 q_vector = adapter->q_vector[v_idx];
 892                 /* XXX for_each_bit(...) */
 893                 r_idx = find_first_bit(q_vector->rxr_idx,
 894                                        adapter->num_rx_queues);
 895
 896                 for (i = 0; i < q_vector->rxr_count; i++) {
 897                         j = adapter->rx_ring[r_idx].reg_idx;
 898                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 899                         r_idx = find_next_bit(q_vector->rxr_idx,
 900                                               adapter->num_rx_queues,
 901                                               r_idx + 1);
 902                 }
 903                 r_idx = find_first_bit(q_vector->txr_idx,
 904                                        adapter->num_tx_queues);
 905
 906                 for (i = 0; i < q_vector->txr_count; i++) {
 907                         j = adapter->tx_ring[r_idx].reg_idx;
 908                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 909                         r_idx = find_next_bit(q_vector->txr_idx,
 910                                               adapter->num_tx_queues,
 911                                               r_idx + 1);
 912                 }
 913
 914                 /* if this is a tx only vector halve the interrupt rate */
 915                 if (q_vector->txr_count && !q_vector->rxr_count)
 916                         q_vector->eitr = (adapter->eitr_param >> 1);
 917                 else if (q_vector->rxr_count)
 918                         /* rx only */
 919                         q_vector->eitr = adapter->eitr_param;
 920
 921                 ixgbe_write_eitr(q_vector);
 922         }
 923
 924         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 925                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 926                                v_idx);
 927         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 928                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 929         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 930
 931         /* set up to autoclear timer, and the vectors */
 932         mask = IXGBE_EIMS_ENABLE_MASK;
 933         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 934         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 935 }
 936
 937 enum latency_range {
 938         lowest_latency = 0,
 939         low_latency = 1,
 940         bulk_latency = 2,
 941         latency_invalid = 255
 942 };
 943
 944 /**
 945  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 946  * @adapter: pointer to adapter
 947  * @eitr: eitr setting (ints per sec) to give last timeslice
 948  * @itr_setting: current throttle rate in ints/second
 949  * @packets: the number of packets during this measurement interval
 950  * @bytes: the number of bytes during this measurement interval
 951  *
 952  *      Stores a new ITR value based on packets and byte
 953  *      counts during the last interrupt.  The advantage of per interrupt
 954  *      computation is faster updates and more accurate ITR for the current
 955  *      traffic pattern.  Constants in this function were computed
 956  *      based on theoretical maximum wire speed and thresholds were set based
 957  *      on testing data as well as attempting to minimize response time
 958  *      while increasing bulk throughput.
 959  *      this functionality is controlled by the InterruptThrottleRate module
 960  *      parameter (see ixgbe_param.c)
 961  **/
 962 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 963                            u32 eitr, u8 itr_setting,
 964                            int packets, int bytes)
 965 {
 966         unsigned int retval = itr_setting;
 967         u32 timepassed_us;
 968         u64 bytes_perint;
 969
 970         if (packets == 0)
 971                 goto update_itr_done;
 972
 973
 974         /* simple throttlerate management
 975          *    0-20MB/s lowest (100000 ints/s)
 976          *   20-100MB/s low   (20000 ints/s)
 977          *  100-1249MB/s bulk (8000 ints/s)
 978          */
 979         /* what was last interrupt timeslice? */
 980         timepassed_us = 1000000/eitr;
 981         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 982
 983         switch (itr_setting) {
 984         case lowest_latency:
 985                 if (bytes_perint > adapter->eitr_low)
 986                         retval = low_latency;
 987                 break;
 988         case low_latency:
 989                 if (bytes_perint > adapter->eitr_high)
 990                         retval = bulk_latency;
 991                 else if (bytes_perint <= adapter->eitr_low)
 992                         retval = lowest_latency;
 993                 break;
 994         case bulk_latency:
 995                 if (bytes_perint <= adapter->eitr_high)
 996                         retval = low_latency;
 997                 break;
 998         }
 999
1000 update_itr_done:
1001         return retval;
1002 }
1003
1004 /**
1005  * ixgbe_write_eitr - write EITR register in hardware specific way
1006  * @q_vector: structure containing interrupt and ring information
1007  *
1008  * This function is made to be called by ethtool and by the driver
1009  * when it needs to update EITR registers at runtime.  Hardware
1010  * specific quirks/differences are taken care of here.
1011  */
1012 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1013 {
1014         struct ixgbe_adapter *adapter = q_vector->adapter;
1015         struct ixgbe_hw *hw = &adapter->hw;
1016         int v_idx = q_vector->v_idx;
1017         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1018
1019         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1020                 /* must write high and low 16 bits to reset counter */
1021                 itr_reg |= (itr_reg << 16);
1022         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1023                 /*
1024                  * set the WDIS bit to not clear the timer bits and cause an
1025                  * immediate assertion of the interrupt
1026                  */
1027                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1028         }
1029         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1030 }
1031
1032 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1033 {
1034         struct ixgbe_adapter *adapter = q_vector->adapter;
1035         u32 new_itr;
1036         u8 current_itr, ret_itr;
1037         int i, r_idx;
1038         struct ixgbe_ring *rx_ring, *tx_ring;
1039
1040         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1041         for (i = 0; i < q_vector->txr_count; i++) {
1042                 tx_ring = &(adapter->tx_ring[r_idx]);
1043                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1044                                            q_vector->tx_itr,
1045                                            tx_ring->total_packets,
1046                                            tx_ring->total_bytes);
1047                 /* if the result for this queue would decrease interrupt
1048                  * rate for this vector then use that result */
1049                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1050                                     q_vector->tx_itr - 1 : ret_itr);
1051                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1052                                       r_idx + 1);
1053         }
1054
1055         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1056         for (i = 0; i < q_vector->rxr_count; i++) {
1057                 rx_ring = &(adapter->rx_ring[r_idx]);
1058                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1059                                            q_vector->rx_itr,
1060                                            rx_ring->total_packets,
1061                                            rx_ring->total_bytes);
1062                 /* if the result for this queue would decrease interrupt
1063                  * rate for this vector then use that result */
1064                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1065                                     q_vector->rx_itr - 1 : ret_itr);
1066                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1067                                       r_idx + 1);
1068         }
1069
1070         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1071
1072         switch (current_itr) {
1073         /* counts and packets in update_itr are dependent on these numbers */
1074         case lowest_latency:
1075                 new_itr = 100000;
1076                 break;
1077         case low_latency:
1078                 new_itr = 20000; /* aka hwitr = ~200 */
1079                 break;
1080         case bulk_latency:
1081         default:
1082                 new_itr = 8000;
1083                 break;
1084         }
1085
1086         if (new_itr != q_vector->eitr) {
1087                 /* do an exponential smoothing */
1088                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1089
1090                 /* save the algorithm value here, not the smoothed one */
1091                 q_vector->eitr = new_itr;
1092
1093                 ixgbe_write_eitr(q_vector);
1094         }
1095
1096         return;
1097 }
1098
1099 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1100 {
1101         struct ixgbe_hw *hw = &adapter->hw;
1102
1103         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1104             (eicr & IXGBE_EICR_GPI_SDP1)) {
1105                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1106                 /* write to clear the interrupt */
1107                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1108         }
1109 }
1110
1111 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1112 {
1113         struct ixgbe_hw *hw = &adapter->hw;
1114
1115         if (eicr & IXGBE_EICR_GPI_SDP1) {
1116                 /* Clear the interrupt */
1117                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1118                 schedule_work(&adapter->multispeed_fiber_task);
1119         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1120                 /* Clear the interrupt */
1121                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1122                 schedule_work(&adapter->sfp_config_module_task);
1123         } else {
1124                 /* Interrupt isn't for us... */
1125                 return;
1126         }
1127 }
1128
1129 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1130 {
1131         struct ixgbe_hw *hw = &adapter->hw;
1132
1133         adapter->lsc_int++;
1134         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1135         adapter->link_check_timeout = jiffies;
1136         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1137                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1138                 schedule_work(&adapter->watchdog_task);
1139         }
1140 }
1141
1142 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1143 {
1144         struct net_device *netdev = data;
1145         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1146         struct ixgbe_hw *hw = &adapter->hw;
1147         u32 eicr;
1148
1149         /*
1150          * Workaround for Silicon errata.  Use clear-by-write instead
1151          * of clear-by-read.  Reading with EICS will return the
1152          * interrupt causes without clearing, which later be done
1153          * with the write to EICR.
1154          */
1155         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1156         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1157
1158         if (eicr & IXGBE_EICR_LSC)
1159                 ixgbe_check_lsc(adapter);
1160
1161         if (hw->mac.type == ixgbe_mac_82598EB)
1162                 ixgbe_check_fan_failure(adapter, eicr);
1163
1164         if (hw->mac.type == ixgbe_mac_82599EB) {
1165                 ixgbe_check_sfp_event(adapter, eicr);
1166
1167                 /* Handle Flow Director Full threshold interrupt */
1168                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1169                         int i;
1170                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1171                         /* Disable transmits before FDIR Re-initialization */
1172                         netif_tx_stop_all_queues(netdev);
1173                         for (i = 0; i < adapter->num_tx_queues; i++) {
1174                                 struct ixgbe_ring *tx_ring =
1175                                                            &adapter->tx_ring[i];
1176                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1177                                                        &tx_ring->reinit_state))
1178                                         schedule_work(&adapter->fdir_reinit_task);
1179                         }
1180                 }
1181         }
1182         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1183                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1184
1185         return IRQ_HANDLED;
1186 }
1187
1188 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1189                                            u64 qmask)
1190 {
1191         u32 mask;
1192
1193         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1194                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1195                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1196         } else {
1197                 mask = (qmask & 0xFFFFFFFF);
1198                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1199                 mask = (qmask >> 32);
1200                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1201         }
1202         /* skip the flush */
1203 }
1204
1205 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1206                                             u64 qmask)
1207 {
1208         u32 mask;
1209
1210         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1211                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1212                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1213         } else {
1214                 mask = (qmask & 0xFFFFFFFF);
1215                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1216                 mask = (qmask >> 32);
1217                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1218         }
1219         /* skip the flush */
1220 }
1221
1222 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1223 {
1224         struct ixgbe_q_vector *q_vector = data;
1225         struct ixgbe_adapter  *adapter = q_vector->adapter;
1226         struct ixgbe_ring     *tx_ring;
1227         int i, r_idx;
1228
1229         if (!q_vector->txr_count)
1230                 return IRQ_HANDLED;
1231
1232         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1233         for (i = 0; i < q_vector->txr_count; i++) {
1234                 tx_ring = &(adapter->tx_ring[r_idx]);
1235                 tx_ring->total_bytes = 0;
1236                 tx_ring->total_packets = 0;
1237                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1238                                       r_idx + 1);
1239         }
1240
1241         /* disable interrupts on this vector only */
1242         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1243         napi_schedule(&q_vector->napi);
1244
1245         return IRQ_HANDLED;
1246 }
1247
1248 /**
1249  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1250  * @irq: unused
1251  * @data: pointer to our q_vector struct for this interrupt vector
1252  **/
1253 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1254 {
1255         struct ixgbe_q_vector *q_vector = data;
1256         struct ixgbe_adapter  *adapter = q_vector->adapter;
1257         struct ixgbe_ring  *rx_ring;
1258         int r_idx;
1259         int i;
1260
1261         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1262         for (i = 0;  i < q_vector->rxr_count; i++) {
1263                 rx_ring = &(adapter->rx_ring[r_idx]);
1264                 rx_ring->total_bytes = 0;
1265                 rx_ring->total_packets = 0;
1266                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1267                                       r_idx + 1);
1268         }
1269
1270         if (!q_vector->rxr_count)
1271                 return IRQ_HANDLED;
1272
1273         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1274         rx_ring = &(adapter->rx_ring[r_idx]);
1275         /* disable interrupts on this vector only */
1276         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1277         napi_schedule(&q_vector->napi);
1278
1279         return IRQ_HANDLED;
1280 }
1281
1282 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1283 {
1284         struct ixgbe_q_vector *q_vector = data;
1285         struct ixgbe_adapter  *adapter = q_vector->adapter;
1286         struct ixgbe_ring  *ring;
1287         int r_idx;
1288         int i;
1289
1290         if (!q_vector->txr_count && !q_vector->rxr_count)
1291                 return IRQ_HANDLED;
1292
1293         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1294         for (i = 0; i < q_vector->txr_count; i++) {
1295                 ring = &(adapter->tx_ring[r_idx]);
1296                 ring->total_bytes = 0;
1297                 ring->total_packets = 0;
1298                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1299                                       r_idx + 1);
1300         }
1301
1302         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1303         for (i = 0; i < q_vector->rxr_count; i++) {
1304                 ring = &(adapter->rx_ring[r_idx]);
1305                 ring->total_bytes = 0;
1306                 ring->total_packets = 0;
1307                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1308                                       r_idx + 1);
1309         }
1310
1311         /* disable interrupts on this vector only */
1312         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1313         napi_schedule(&q_vector->napi);
1314
1315         return IRQ_HANDLED;
1316 }
1317
1318 /**
1319  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1320  * @napi: napi struct with our devices info in it
1321  * @budget: amount of work driver is allowed to do this pass, in packets
1322  *
1323  * This function is optimized for cleaning one queue only on a single
1324  * q_vector!!!
1325  **/
1326 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1327 {
1328         struct ixgbe_q_vector *q_vector =
1329                                container_of(napi, struct ixgbe_q_vector, napi);
1330         struct ixgbe_adapter *adapter = q_vector->adapter;
1331         struct ixgbe_ring *rx_ring = NULL;
1332         int work_done = 0;
1333         long r_idx;
1334
1335         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1336         rx_ring = &(adapter->rx_ring[r_idx]);
1337 #ifdef CONFIG_IXGBE_DCA
1338         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1339                 ixgbe_update_rx_dca(adapter, rx_ring);
1340 #endif
1341
1342         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1343
1344         /* If all Rx work done, exit the polling mode */
1345         if (work_done < budget) {
1346                 napi_complete(napi);
1347                 if (adapter->itr_setting & 1)
1348                         ixgbe_set_itr_msix(q_vector);
1349                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1350                         ixgbe_irq_enable_queues(adapter,
1351                                                 ((u64)1 << q_vector->v_idx));
1352         }
1353
1354         return work_done;
1355 }
1356
1357 /**
1358  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1359  * @napi: napi struct with our devices info in it
1360  * @budget: amount of work driver is allowed to do this pass, in packets
1361  *
1362  * This function will clean more than one rx queue associated with a
1363  * q_vector.
1364  **/
1365 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1366 {
1367         struct ixgbe_q_vector *q_vector =
1368                                container_of(napi, struct ixgbe_q_vector, napi);
1369         struct ixgbe_adapter *adapter = q_vector->adapter;
1370         struct ixgbe_ring *ring = NULL;
1371         int work_done = 0, i;
1372         long r_idx;
1373         bool tx_clean_complete = true;
1374
1375         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1376         for (i = 0; i < q_vector->txr_count; i++) {
1377                 ring = &(adapter->tx_ring[r_idx]);
1378 #ifdef CONFIG_IXGBE_DCA
1379                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1380                         ixgbe_update_tx_dca(adapter, ring);
1381 #endif
1382                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1383                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1384                                       r_idx + 1);
1385         }
1386
1387         /* attempt to distribute budget to each queue fairly, but don't allow
1388          * the budget to go below 1 because we'll exit polling */
1389         budget /= (q_vector->rxr_count ?: 1);
1390         budget = max(budget, 1);
1391         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1392         for (i = 0; i < q_vector->rxr_count; i++) {
1393                 ring = &(adapter->rx_ring[r_idx]);
1394 #ifdef CONFIG_IXGBE_DCA
1395                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1396                         ixgbe_update_rx_dca(adapter, ring);
1397 #endif
1398                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1399                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1400                                       r_idx + 1);
1401         }
1402
1403         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1404         ring = &(adapter->rx_ring[r_idx]);
1405         /* If all Rx work done, exit the polling mode */
1406         if (work_done < budget) {
1407                 napi_complete(napi);
1408                 if (adapter->itr_setting & 1)
1409                         ixgbe_set_itr_msix(q_vector);
1410                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1411                         ixgbe_irq_enable_queues(adapter,
1412                                                 ((u64)1 << q_vector->v_idx));
1413                 return 0;
1414         }
1415
1416         return work_done;
1417 }
1418
1419 /**
1420  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1421  * @napi: napi struct with our devices info in it
1422  * @budget: amount of work driver is allowed to do this pass, in packets
1423  *
1424  * This function is optimized for cleaning one queue only on a single
1425  * q_vector!!!
1426  **/
1427 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1428 {
1429         struct ixgbe_q_vector *q_vector =
1430                                container_of(napi, struct ixgbe_q_vector, napi);
1431         struct ixgbe_adapter *adapter = q_vector->adapter;
1432         struct ixgbe_ring *tx_ring = NULL;
1433         int work_done = 0;
1434         long r_idx;
1435
1436         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1437         tx_ring = &(adapter->tx_ring[r_idx]);
1438 #ifdef CONFIG_IXGBE_DCA
1439         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1440                 ixgbe_update_tx_dca(adapter, tx_ring);
1441 #endif
1442
1443         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1444                 work_done = budget;
1445
1446         /* If all Rx work done, exit the polling mode */
1447         if (work_done < budget) {
1448                 napi_complete(napi);
1449                 if (adapter->itr_setting & 1)
1450                         ixgbe_set_itr_msix(q_vector);
1451                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1452                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1453         }
1454
1455         return work_done;
1456 }
1457
1458 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1459                                      int r_idx)
1460 {
1461         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1462
1463         set_bit(r_idx, q_vector->rxr_idx);
1464         q_vector->rxr_count++;
1465 }
1466
1467 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1468                                      int t_idx)
1469 {
1470         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1471
1472         set_bit(t_idx, q_vector->txr_idx);
1473         q_vector->txr_count++;
1474 }
1475
1476 /**
1477  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1478  * @adapter: board private structure to initialize
1479  * @vectors: allotted vector count for descriptor rings
1480  *
1481  * This function maps descriptor rings to the queue-specific vectors
1482  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1483  * one vector per ring/queue, but on a constrained vector budget, we
1484  * group the rings as "efficiently" as possible.  You would add new
1485  * mapping configurations in here.
1486  **/
1487 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1488                                       int vectors)
1489 {
1490         int v_start = 0;
1491         int rxr_idx = 0, txr_idx = 0;
1492         int rxr_remaining = adapter->num_rx_queues;
1493         int txr_remaining = adapter->num_tx_queues;
1494         int i, j;
1495         int rqpv, tqpv;
1496         int err = 0;
1497
1498         /* No mapping required if MSI-X is disabled. */
1499         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1500                 goto out;
1501
1502         /*
1503          * The ideal configuration...
1504          * We have enough vectors to map one per queue.
1505          */
1506         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1507                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1508                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1509
1510                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1511                         map_vector_to_txq(adapter, v_start, txr_idx);
1512
1513                 goto out;
1514         }
1515
1516         /*
1517          * If we don't have enough vectors for a 1-to-1
1518          * mapping, we'll have to group them so there are
1519          * multiple queues per vector.
1520          */
1521         /* Re-adjusting *qpv takes care of the remainder. */
1522         for (i = v_start; i < vectors; i++) {
1523                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1524                 for (j = 0; j < rqpv; j++) {
1525                         map_vector_to_rxq(adapter, i, rxr_idx);
1526                         rxr_idx++;
1527                         rxr_remaining--;
1528                 }
1529         }
1530         for (i = v_start; i < vectors; i++) {
1531                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1532                 for (j = 0; j < tqpv; j++) {
1533                         map_vector_to_txq(adapter, i, txr_idx);
1534                         txr_idx++;
1535                         txr_remaining--;
1536                 }
1537         }
1538
1539 out:
1540         return err;
1541 }
1542
1543 /**
1544  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1545  * @adapter: board private structure
1546  *
1547  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1548  * interrupts from the kernel.
1549  **/
1550 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1551 {
1552         struct net_device *netdev = adapter->netdev;
1553         irqreturn_t (*handler)(int, void *);
1554         int i, vector, q_vectors, err;
1555         int ri=0, ti=0;
1556
1557         /* Decrement for Other and TCP Timer vectors */
1558         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1559
1560         /* Map the Tx/Rx rings to the vectors we were allotted. */
1561         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1562         if (err)
1563                 goto out;
1564
1565 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1566                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1567                          &ixgbe_msix_clean_many)
1568         for (vector = 0; vector < q_vectors; vector++) {
1569                 handler = SET_HANDLER(adapter->q_vector[vector]);
1570
1571                 if(handler == &ixgbe_msix_clean_rx) {
1572                         sprintf(adapter->name[vector], "%s-%s-%d",
1573                                 netdev->name, "rx", ri++);
1574                 }
1575                 else if(handler == &ixgbe_msix_clean_tx) {
1576                         sprintf(adapter->name[vector], "%s-%s-%d",
1577                                 netdev->name, "tx", ti++);
1578                 }
1579                 else
1580                         sprintf(adapter->name[vector], "%s-%s-%d",
1581                                 netdev->name, "TxRx", vector);
1582
1583                 err = request_irq(adapter->msix_entries[vector].vector,
1584                                   handler, 0, adapter->name[vector],
1585                                   adapter->q_vector[vector]);
1586                 if (err) {
1587                         DPRINTK(PROBE, ERR,
1588                                 "request_irq failed for MSIX interrupt "
1589                                 "Error: %d\n", err);
1590                         goto free_queue_irqs;
1591                 }
1592         }
1593
1594         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1595         err = request_irq(adapter->msix_entries[vector].vector,
1596                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1597         if (err) {
1598                 DPRINTK(PROBE, ERR,
1599                         "request_irq for msix_lsc failed: %d\n", err);
1600                 goto free_queue_irqs;
1601         }
1602
1603         return 0;
1604
1605 free_queue_irqs:
1606         for (i = vector - 1; i >= 0; i--)
1607                 free_irq(adapter->msix_entries[--vector].vector,
1608                          adapter->q_vector[i]);
1609         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1610         pci_disable_msix(adapter->pdev);
1611         kfree(adapter->msix_entries);
1612         adapter->msix_entries = NULL;
1613 out:
1614         return err;
1615 }
1616
1617 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1618 {
1619         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1620         u8 current_itr;
1621         u32 new_itr = q_vector->eitr;
1622         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1623         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1624
1625         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1626                                             q_vector->tx_itr,
1627                                             tx_ring->total_packets,
1628                                             tx_ring->total_bytes);
1629         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1630                                             q_vector->rx_itr,
1631                                             rx_ring->total_packets,
1632                                             rx_ring->total_bytes);
1633
1634         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1635
1636         switch (current_itr) {
1637         /* counts and packets in update_itr are dependent on these numbers */
1638         case lowest_latency:
1639                 new_itr = 100000;
1640                 break;
1641         case low_latency:
1642                 new_itr = 20000; /* aka hwitr = ~200 */
1643                 break;
1644         case bulk_latency:
1645                 new_itr = 8000;
1646                 break;
1647         default:
1648                 break;
1649         }
1650
1651         if (new_itr != q_vector->eitr) {
1652                 /* do an exponential smoothing */
1653                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1654
1655                 /* save the algorithm value here, not the smoothed one */
1656                 q_vector->eitr = new_itr;
1657
1658                 ixgbe_write_eitr(q_vector);
1659         }
1660
1661         return;
1662 }
1663
1664 /**
1665  * ixgbe_irq_enable - Enable default interrupt generation settings
1666  * @adapter: board private structure
1667  **/
1668 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1669 {
1670         u32 mask;
1671
1672         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1673         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1674                 mask |= IXGBE_EIMS_GPI_SDP1;
1675         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1676                 mask |= IXGBE_EIMS_ECC;
1677                 mask |= IXGBE_EIMS_GPI_SDP1;
1678                 mask |= IXGBE_EIMS_GPI_SDP2;
1679         }
1680         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1681             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1682                 mask |= IXGBE_EIMS_FLOW_DIR;
1683
1684         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1685         ixgbe_irq_enable_queues(adapter, ~0);
1686         IXGBE_WRITE_FLUSH(&adapter->hw);
1687 }
1688
1689 /**
1690  * ixgbe_intr - legacy mode Interrupt Handler
1691  * @irq: interrupt number
1692  * @data: pointer to a network interface device structure
1693  **/
1694 static irqreturn_t ixgbe_intr(int irq, void *data)
1695 {
1696         struct net_device *netdev = data;
1697         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1698         struct ixgbe_hw *hw = &adapter->hw;
1699         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1700         u32 eicr;
1701
1702         /*
1703          * Workaround for silicon errata.  Mask the interrupts
1704          * before the read of EICR.
1705          */
1706         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1707
1708         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1709          * therefore no explict interrupt disable is necessary */
1710         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1711         if (!eicr) {
1712                 /* shared interrupt alert!
1713                  * make sure interrupts are enabled because the read will
1714                  * have disabled interrupts due to EIAM */
1715                 ixgbe_irq_enable(adapter);
1716                 return IRQ_NONE;        /* Not our interrupt */
1717         }
1718
1719         if (eicr & IXGBE_EICR_LSC)
1720                 ixgbe_check_lsc(adapter);
1721
1722         if (hw->mac.type == ixgbe_mac_82599EB)
1723                 ixgbe_check_sfp_event(adapter, eicr);
1724
1725         ixgbe_check_fan_failure(adapter, eicr);
1726
1727         if (napi_schedule_prep(&(q_vector->napi))) {
1728                 adapter->tx_ring[0].total_packets = 0;
1729                 adapter->tx_ring[0].total_bytes = 0;
1730                 adapter->rx_ring[0].total_packets = 0;
1731                 adapter->rx_ring[0].total_bytes = 0;
1732                 /* would disable interrupts here but EIAM disabled it */
1733                 __napi_schedule(&(q_vector->napi));
1734         }
1735
1736         return IRQ_HANDLED;
1737 }
1738
1739 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1740 {
1741         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1742
1743         for (i = 0; i < q_vectors; i++) {
1744                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1745                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1746                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1747                 q_vector->rxr_count = 0;
1748                 q_vector->txr_count = 0;
1749         }
1750 }
1751
1752 /**
1753  * ixgbe_request_irq - initialize interrupts
1754  * @adapter: board private structure
1755  *
1756  * Attempts to configure interrupts using the best available
1757  * capabilities of the hardware and kernel.
1758  **/
1759 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1760 {
1761         struct net_device *netdev = adapter->netdev;
1762         int err;
1763
1764         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1765                 err = ixgbe_request_msix_irqs(adapter);
1766         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1767                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1768                                   netdev->name, netdev);
1769         } else {
1770                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1771                                   netdev->name, netdev);
1772         }
1773
1774         if (err)
1775                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1776
1777         return err;
1778 }
1779
1780 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1781 {
1782         struct net_device *netdev = adapter->netdev;
1783
1784         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1785                 int i, q_vectors;
1786
1787                 q_vectors = adapter->num_msix_vectors;
1788
1789                 i = q_vectors - 1;
1790                 free_irq(adapter->msix_entries[i].vector, netdev);
1791
1792                 i--;
1793                 for (; i >= 0; i--) {
1794                         free_irq(adapter->msix_entries[i].vector,
1795                                  adapter->q_vector[i]);
1796                 }
1797
1798                 ixgbe_reset_q_vectors(adapter);
1799         } else {
1800                 free_irq(adapter->pdev->irq, netdev);
1801         }
1802 }
1803
1804 /**
1805  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1806  * @adapter: board private structure
1807  **/
1808 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1809 {
1810         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1811                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1812         } else {
1813                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1814                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1815                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1816         }
1817         IXGBE_WRITE_FLUSH(&adapter->hw);
1818         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1819                 int i;
1820                 for (i = 0; i < adapter->num_msix_vectors; i++)
1821                         synchronize_irq(adapter->msix_entries[i].vector);
1822         } else {
1823                 synchronize_irq(adapter->pdev->irq);
1824         }
1825 }
1826
1827 /**
1828  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1829  *
1830  **/
1831 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1832 {
1833         struct ixgbe_hw *hw = &adapter->hw;
1834
1835         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1836                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1837
1838         ixgbe_set_ivar(adapter, 0, 0, 0);
1839         ixgbe_set_ivar(adapter, 1, 0, 0);
1840
1841         map_vector_to_rxq(adapter, 0, 0);
1842         map_vector_to_txq(adapter, 0, 0);
1843
1844         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1845 }
1846
1847 /**
1848  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1849  * @adapter: board private structure
1850  *
1851  * Configure the Tx unit of the MAC after a reset.
1852  **/
1853 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1854 {
1855         u64 tdba;
1856         struct ixgbe_hw *hw = &adapter->hw;
1857         u32 i, j, tdlen, txctrl;
1858
1859         /* Setup the HW Tx Head and Tail descriptor pointers */
1860         for (i = 0; i < adapter->num_tx_queues; i++) {
1861                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1862                 j = ring->reg_idx;
1863                 tdba = ring->dma;
1864                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1865                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1866                                 (tdba & DMA_BIT_MASK(32)));
1867                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1868                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1869                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1870                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1871                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1872                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1873                 /* Disable Tx Head Writeback RO bit, since this hoses
1874                  * bookkeeping if things aren't delivered in order.
1875                  */
1876                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1877                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1878                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1879         }
1880         if (hw->mac.type == ixgbe_mac_82599EB) {
1881                 /* We enable 8 traffic classes, DCB only */
1882                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1883                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1884                                         IXGBE_MTQC_8TC_8TQ));
1885         }
1886 }
1887
1888 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1889
1890 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1891 {
1892         struct ixgbe_ring *rx_ring;
1893         u32 srrctl;
1894         int queue0 = 0;
1895         unsigned long mask;
1896         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1897
1898         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1899                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1900                         int dcb_i = feature[RING_F_DCB].indices;
1901                         if (dcb_i == 8)
1902                                 queue0 = index >> 4;
1903                         else if (dcb_i == 4)
1904                                 queue0 = index >> 5;
1905                         else
1906                                 dev_err(&adapter->pdev->dev, "Invalid DCB "
1907                                         "configuration\n");
1908 #ifdef IXGBE_FCOE
1909                         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1910                                 struct ixgbe_ring_feature *f;
1911
1912                                 rx_ring = &adapter->rx_ring[queue0];
1913                                 f = &adapter->ring_feature[RING_F_FCOE];
1914                                 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1915                                         queue0 = f->mask + index -
1916                                                  rx_ring->reg_idx - 1;
1917                         }
1918 #endif /* IXGBE_FCOE */
1919                 } else {
1920                         queue0 = index;
1921                 }
1922         } else {
1923                 mask = (unsigned long) feature[RING_F_RSS].mask;
1924                 queue0 = index & mask;
1925                 index = index & mask;
1926         }
1927
1928         rx_ring = &adapter->rx_ring[queue0];
1929
1930         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1931
1932         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1933         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1934
1935         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1936                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1937
1938         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1939 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1940                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1941 #else
1942                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1943 #endif
1944                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1945         } else {
1946                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1947                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1948                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1949         }
1950
1951         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1952 }
1953
1954 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1955 {
1956         u32 mrqc = 0;
1957         int mask;
1958
1959         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1960                 return mrqc;
1961
1962         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1963 #ifdef CONFIG_IXGBE_DCB
1964                                  | IXGBE_FLAG_DCB_ENABLED
1965 #endif
1966                                 );
1967
1968         switch (mask) {
1969         case (IXGBE_FLAG_RSS_ENABLED):
1970                 mrqc = IXGBE_MRQC_RSSEN;
1971                 break;
1972 #ifdef CONFIG_IXGBE_DCB
1973         case (IXGBE_FLAG_DCB_ENABLED):
1974                 mrqc = IXGBE_MRQC_RT8TCEN;
1975                 break;
1976 #endif /* CONFIG_IXGBE_DCB */
1977         default:
1978                 break;
1979         }
1980
1981         return mrqc;
1982 }
1983
1984 /**
1985  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1986  * @adapter: board private structure
1987  *
1988  * Configure the Rx unit of the MAC after a reset.
1989  **/
1990 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1991 {
1992         u64 rdba;
1993         struct ixgbe_hw *hw = &adapter->hw;
1994         struct net_device *netdev = adapter->netdev;
1995         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1996         int i, j;
1997         u32 rdlen, rxctrl, rxcsum;
1998         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1999                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2000                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2001         u32 fctrl, hlreg0;
2002         u32 reta = 0, mrqc = 0;
2003         u32 rdrxctl;
2004         u32 rscctrl;
2005         int rx_buf_len;
2006
2007         /* Decide whether to use packet split mode or not */
2008         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2009
2010 #ifdef IXGBE_FCOE
2011         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2012                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2013 #endif /* IXGBE_FCOE */
2014
2015         /* Set the RX buffer length according to the mode */
2016         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2017                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2018                 if (hw->mac.type == ixgbe_mac_82599EB) {
2019                         /* PSRTYPE must be initialized in 82599 */
2020                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2021                                       IXGBE_PSRTYPE_UDPHDR |
2022                                       IXGBE_PSRTYPE_IPV4HDR |
2023                                       IXGBE_PSRTYPE_IPV6HDR |
2024                                       IXGBE_PSRTYPE_L2HDR;
2025                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2026                 }
2027         } else {
2028                 if (!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED) &&
2029                     (netdev->mtu <= ETH_DATA_LEN))
2030                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2031                 else
2032                         rx_buf_len = ALIGN(max_frame, 1024);
2033         }
2034
2035         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2036         fctrl |= IXGBE_FCTRL_BAM;
2037         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2038         fctrl |= IXGBE_FCTRL_PMCF;
2039         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2040
2041         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2042         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2043                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2044         else
2045                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2046 #ifdef IXGBE_FCOE
2047         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2048                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2049 #endif
2050         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2051
2052         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2053         /* disable receives while setting up the descriptors */
2054         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2055         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2056
2057         /*
2058          * Setup the HW Rx Head and Tail Descriptor Pointers and
2059          * the Base and Length of the Rx Descriptor Ring
2060          */
2061         for (i = 0; i < adapter->num_rx_queues; i++) {
2062                 rdba = adapter->rx_ring[i].dma;
2063                 j = adapter->rx_ring[i].reg_idx;
2064                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2065                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2066                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2067                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2068                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2069                 adapter->rx_ring[i].head = IXGBE_RDH(j);
2070                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
2071                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
2072
2073 #ifdef IXGBE_FCOE
2074                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2075                         struct ixgbe_ring_feature *f;
2076                         f = &adapter->ring_feature[RING_F_FCOE];
2077                         if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
2078                             (i >= f->mask) && (i < f->mask + f->indices))
2079                                 adapter->rx_ring[i].rx_buf_len =
2080                                         IXGBE_FCOE_JUMBO_FRAME_SIZE;
2081                 }
2082
2083 #endif /* IXGBE_FCOE */
2084                 ixgbe_configure_srrctl(adapter, j);
2085         }
2086
2087         if (hw->mac.type == ixgbe_mac_82598EB) {
2088                 /*
2089                  * For VMDq support of different descriptor types or
2090                  * buffer sizes through the use of multiple SRRCTL
2091                  * registers, RDRXCTL.MVMEN must be set to 1
2092                  *
2093                  * also, the manual doesn't mention it clearly but DCA hints
2094                  * will only use queue 0's tags unless this bit is set.  Side
2095                  * effects of setting this bit are only that SRRCTL must be
2096                  * fully programmed [0..15]
2097                  */
2098                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2099                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2100                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2101         }
2102
2103         /* Program MRQC for the distribution of queues */
2104         mrqc = ixgbe_setup_mrqc(adapter);
2105
2106         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2107                 /* Fill out redirection table */
2108                 for (i = 0, j = 0; i < 128; i++, j++) {
2109                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2110                                 j = 0;
2111                         /* reta = 4-byte sliding window of
2112                          * 0x00..(indices-1)(indices-1)00..etc. */
2113                         reta = (reta << 8) | (j * 0x11);
2114                         if ((i & 3) == 3)
2115                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2116                 }
2117
2118                 /* Fill out hash function seeds */
2119                 for (i = 0; i < 10; i++)
2120                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2121
2122                 if (hw->mac.type == ixgbe_mac_82598EB)
2123                         mrqc |= IXGBE_MRQC_RSSEN;
2124                     /* Perform hash on these packet types */
2125                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2126                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2127                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2128                       | IXGBE_MRQC_RSS_FIELD_IPV6
2129                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2130                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2131         }
2132         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2133
2134         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2135
2136         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2137             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2138                 /* Disable indicating checksum in descriptor, enables
2139                  * RSS hash */
2140                 rxcsum |= IXGBE_RXCSUM_PCSD;
2141         }
2142         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2143                 /* Enable IPv4 payload checksum for UDP fragments
2144                  * if PCSD is not set */
2145                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2146         }
2147
2148         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2149
2150         if (hw->mac.type == ixgbe_mac_82599EB) {
2151                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2152                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2153                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2154                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2155         }
2156
2157         if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) {
2158                 /* Enable 82599 HW-RSC */
2159                 for (i = 0; i < adapter->num_rx_queues; i++) {
2160                         j = adapter->rx_ring[i].reg_idx;
2161                         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2162                         rscctrl |= IXGBE_RSCCTL_RSCEN;
2163                         /*
2164                          * we must limit the number of descriptors so that the
2165                          * total size of max desc * buf_len is not greater
2166                          * than 65535
2167                          */
2168                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2169 #if (MAX_SKB_FRAGS > 16)
2170                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2171 #elif (MAX_SKB_FRAGS > 8)
2172                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2173 #elif (MAX_SKB_FRAGS > 4)
2174                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2175 #else
2176                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2177 #endif
2178                         } else {
2179                                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2180                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2181                                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2182                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2183                                 else
2184                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2185                         }
2186                         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2187                 }
2188                 /* Disable RSC for ACK packets */
2189                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2190                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2191         }
2192 }
2193
2194 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2195 {
2196         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2197         struct ixgbe_hw *hw = &adapter->hw;
2198
2199         /* add VID to filter table */
2200         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2201 }
2202
2203 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2204 {
2205         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2206         struct ixgbe_hw *hw = &adapter->hw;
2207
2208         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2209                 ixgbe_irq_disable(adapter);
2210
2211         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2212
2213         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2214                 ixgbe_irq_enable(adapter);
2215
2216         /* remove VID from filter table */
2217         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2218 }
2219
2220 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2221                                    struct vlan_group *grp)
2222 {
2223         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2224         u32 ctrl;
2225         int i, j;
2226
2227         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2228                 ixgbe_irq_disable(adapter);
2229         adapter->vlgrp = grp;
2230
2231         /*
2232          * For a DCB driver, always enable VLAN tag stripping so we can
2233          * still receive traffic from a DCB-enabled host even if we're
2234          * not in DCB mode.
2235          */
2236         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2237         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2238                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2239                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2240                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2241         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2242                 ctrl |= IXGBE_VLNCTRL_VFE;
2243                 /* enable VLAN tag insert/strip */
2244                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2245                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2246                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2247                 for (i = 0; i < adapter->num_rx_queues; i++) {
2248                         j = adapter->rx_ring[i].reg_idx;
2249                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2250                         ctrl |= IXGBE_RXDCTL_VME;
2251                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2252                 }
2253         }
2254         ixgbe_vlan_rx_add_vid(netdev, 0);
2255
2256         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2257                 ixgbe_irq_enable(adapter);
2258 }
2259
2260 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2261 {
2262         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2263
2264         if (adapter->vlgrp) {
2265                 u16 vid;
2266                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2267                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2268                                 continue;
2269                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2270                 }
2271         }
2272 }
2273
2274 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2275 {
2276         struct dev_mc_list *mc_ptr;
2277         u8 *addr = *mc_addr_ptr;
2278         *vmdq = 0;
2279
2280         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2281         if (mc_ptr->next)
2282                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2283         else
2284                 *mc_addr_ptr = NULL;
2285
2286         return addr;
2287 }
2288
2289 /**
2290  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2291  * @netdev: network interface device structure
2292  *
2293  * The set_rx_method entry point is called whenever the unicast/multicast
2294  * address list or the network interface flags are updated.  This routine is
2295  * responsible for configuring the hardware for proper unicast, multicast and
2296  * promiscuous mode.
2297  **/
2298 static void ixgbe_set_rx_mode(struct net_device *netdev)
2299 {
2300         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2301         struct ixgbe_hw *hw = &adapter->hw;
2302         u32 fctrl, vlnctrl;
2303         u8 *addr_list = NULL;
2304         int addr_count = 0;
2305
2306         /* Check for Promiscuous and All Multicast modes */
2307
2308         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2309         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2310
2311         if (netdev->flags & IFF_PROMISC) {
2312                 hw->addr_ctrl.user_set_promisc = 1;
2313                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2314                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2315         } else {
2316                 if (netdev->flags & IFF_ALLMULTI) {
2317                         fctrl |= IXGBE_FCTRL_MPE;
2318                         fctrl &= ~IXGBE_FCTRL_UPE;
2319                 } else {
2320                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2321                 }
2322                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2323                 hw->addr_ctrl.user_set_promisc = 0;
2324         }
2325
2326         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2327         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2328
2329         /* reprogram secondary unicast list */
2330         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2331
2332         /* reprogram multicast list */
2333         addr_count = netdev->mc_count;
2334         if (addr_count)
2335                 addr_list = netdev->mc_list->dmi_addr;
2336         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2337                                         ixgbe_addr_list_itr);
2338 }
2339
2340 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2341 {
2342         int q_idx;
2343         struct ixgbe_q_vector *q_vector;
2344         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2345
2346         /* legacy and MSI only use one vector */
2347         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2348                 q_vectors = 1;
2349
2350         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2351                 struct napi_struct *napi;
2352                 q_vector = adapter->q_vector[q_idx];
2353                 napi = &q_vector->napi;
2354                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2355                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2356                                 if (q_vector->txr_count == 1)
2357                                         napi->poll = &ixgbe_clean_txonly;
2358                                 else if (q_vector->rxr_count == 1)
2359                                         napi->poll = &ixgbe_clean_rxonly;
2360                         }
2361                 }
2362
2363                 napi_enable(napi);
2364         }
2365 }
2366
2367 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2368 {
2369         int q_idx;
2370         struct ixgbe_q_vector *q_vector;
2371         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2372
2373         /* legacy and MSI only use one vector */
2374         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2375                 q_vectors = 1;
2376
2377         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2378                 q_vector = adapter->q_vector[q_idx];
2379                 napi_disable(&q_vector->napi);
2380         }
2381 }
2382
2383 #ifdef CONFIG_IXGBE_DCB
2384 /*
2385  * ixgbe_configure_dcb - Configure DCB hardware
2386  * @adapter: ixgbe adapter struct
2387  *
2388  * This is called by the driver on open to configure the DCB hardware.
2389  * This is also called by the gennetlink interface when reconfiguring
2390  * the DCB state.
2391  */
2392 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2393 {
2394         struct ixgbe_hw *hw = &adapter->hw;
2395         u32 txdctl, vlnctrl;
2396         int i, j;
2397
2398         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2399         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2400         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2401
2402         /* reconfigure the hardware */
2403         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2404
2405         for (i = 0; i < adapter->num_tx_queues; i++) {
2406                 j = adapter->tx_ring[i].reg_idx;
2407                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2408                 /* PThresh workaround for Tx hang with DFP enabled. */
2409                 txdctl |= 32;
2410                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2411         }
2412         /* Enable VLAN tag insert/strip */
2413         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2414         if (hw->mac.type == ixgbe_mac_82598EB) {
2415                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2416                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2417                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2418         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2419                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2420                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2421                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2422                 for (i = 0; i < adapter->num_rx_queues; i++) {
2423                         j = adapter->rx_ring[i].reg_idx;
2424                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2425                         vlnctrl |= IXGBE_RXDCTL_VME;
2426                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2427                 }
2428         }
2429         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2430 }
2431
2432 #endif
2433 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2434 {
2435         struct net_device *netdev = adapter->netdev;
2436         struct ixgbe_hw *hw = &adapter->hw;
2437         int i;
2438
2439         ixgbe_set_rx_mode(netdev);
2440
2441         ixgbe_restore_vlan(adapter);
2442 #ifdef CONFIG_IXGBE_DCB
2443         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2444                 netif_set_gso_max_size(netdev, 32768);
2445                 ixgbe_configure_dcb(adapter);
2446         } else {
2447                 netif_set_gso_max_size(netdev, 65536);
2448         }
2449 #else
2450         netif_set_gso_max_size(netdev, 65536);
2451 #endif
2452
2453 #ifdef IXGBE_FCOE
2454         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2455                 ixgbe_configure_fcoe(adapter);
2456
2457 #endif /* IXGBE_FCOE */
2458         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2459                 for (i = 0; i < adapter->num_tx_queues; i++)
2460                         adapter->tx_ring[i].atr_sample_rate =
2461                                                        adapter->atr_sample_rate;
2462                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2463         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2464                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2465         }
2466
2467         ixgbe_configure_tx(adapter);
2468         ixgbe_configure_rx(adapter);
2469         for (i = 0; i < adapter->num_rx_queues; i++)
2470                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2471                                        (adapter->rx_ring[i].count - 1));
2472 }
2473
2474 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2475 {
2476         switch (hw->phy.type) {
2477         case ixgbe_phy_sfp_avago:
2478         case ixgbe_phy_sfp_ftl:
2479         case ixgbe_phy_sfp_intel:
2480         case ixgbe_phy_sfp_unknown:
2481         case ixgbe_phy_tw_tyco:
2482         case ixgbe_phy_tw_unknown:
2483                 return true;
2484         default:
2485                 return false;
2486         }
2487 }
2488
2489 /**
2490  * ixgbe_sfp_link_config - set up SFP+ link
2491  * @adapter: pointer to private adapter struct
2492  **/
2493 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2494 {
2495         struct ixgbe_hw *hw = &adapter->hw;
2496
2497                 if (hw->phy.multispeed_fiber) {
2498                         /*
2499                          * In multispeed fiber setups, the device may not have
2500                          * had a physical connection when the driver loaded.
2501                          * If that's the case, the initial link configuration
2502                          * couldn't get the MAC into 10G or 1G mode, so we'll
2503                          * never have a link status change interrupt fire.
2504                          * We need to try and force an autonegotiation
2505                          * session, then bring up link.
2506                          */
2507                         hw->mac.ops.setup_sfp(hw);
2508                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2509                                 schedule_work(&adapter->multispeed_fiber_task);
2510                 } else {
2511                         /*
2512                          * Direct Attach Cu and non-multispeed fiber modules
2513                          * still need to be configured properly prior to
2514                          * attempting link.
2515                          */
2516                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2517                                 schedule_work(&adapter->sfp_config_module_task);
2518                 }
2519 }
2520
2521 /**
2522  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2523  * @hw: pointer to private hardware struct
2524  *
2525  * Returns 0 on success, negative on failure
2526  **/
2527 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2528 {
2529         u32 autoneg;
2530         bool link_up = false;
2531         u32 ret = IXGBE_ERR_LINK_SETUP;
2532
2533         if (hw->mac.ops.check_link)
2534                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2535
2536         if (ret)
2537                 goto link_cfg_out;
2538
2539         if (hw->mac.ops.get_link_capabilities)
2540                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2541                                                         &hw->mac.autoneg);
2542         if (ret)
2543                 goto link_cfg_out;
2544
2545         if (hw->mac.ops.setup_link_speed)
2546                 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2547 link_cfg_out:
2548         return ret;
2549 }
2550
2551 #define IXGBE_MAX_RX_DESC_POLL 10
2552 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2553                                               int rxr)
2554 {
2555         int j = adapter->rx_ring[rxr].reg_idx;
2556         int k;
2557
2558         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2559                 if (IXGBE_READ_REG(&adapter->hw,
2560                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2561                         break;
2562                 else
2563                         msleep(1);
2564         }
2565         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2566                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2567                         "not set within the polling period\n", rxr);
2568         }
2569         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2570                               (adapter->rx_ring[rxr].count - 1));
2571 }
2572
2573 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2574 {
2575         struct net_device *netdev = adapter->netdev;
2576         struct ixgbe_hw *hw = &adapter->hw;
2577         int i, j = 0;
2578         int num_rx_rings = adapter->num_rx_queues;
2579         int err;
2580         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2581         u32 txdctl, rxdctl, mhadd;
2582         u32 dmatxctl;
2583         u32 gpie;
2584
2585         ixgbe_get_hw_control(adapter);
2586
2587         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2588             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2589                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2590                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2591                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2592                 } else {
2593                         /* MSI only */
2594                         gpie = 0;
2595                 }
2596                 /* XXX: to interrupt immediately for EICS writes, enable this */
2597                 /* gpie |= IXGBE_GPIE_EIMEN; */
2598                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2599         }
2600
2601         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2602                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2603                  * specifically only auto mask tx and rx interrupts */
2604                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2605         }
2606
2607         /* Enable fan failure interrupt if media type is copper */
2608         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2609                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2610                 gpie |= IXGBE_SDP1_GPIEN;
2611                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2612         }
2613
2614         if (hw->mac.type == ixgbe_mac_82599EB) {
2615                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2616                 gpie |= IXGBE_SDP1_GPIEN;
2617                 gpie |= IXGBE_SDP2_GPIEN;
2618                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2619         }
2620
2621 #ifdef IXGBE_FCOE
2622         /* adjust max frame to be able to do baby jumbo for FCoE */
2623         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2624             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2625                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2626
2627 #endif /* IXGBE_FCOE */
2628         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2629         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2630                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2631                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2632
2633                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2634         }
2635
2636         for (i = 0; i < adapter->num_tx_queues; i++) {
2637                 j = adapter->tx_ring[i].reg_idx;
2638                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2639                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2640                 txdctl |= (8 << 16);
2641                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2642         }
2643
2644         if (hw->mac.type == ixgbe_mac_82599EB) {
2645                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2646                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2647                 dmatxctl |= IXGBE_DMATXCTL_TE;
2648                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2649         }
2650         for (i = 0; i < adapter->num_tx_queues; i++) {
2651                 j = adapter->tx_ring[i].reg_idx;
2652                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2653                 txdctl |= IXGBE_TXDCTL_ENABLE;
2654                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2655         }
2656
2657         for (i = 0; i < num_rx_rings; i++) {
2658                 j = adapter->rx_ring[i].reg_idx;
2659                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2660                 /* enable PTHRESH=32 descriptors (half the internal cache)
2661                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2662                  * this also removes a pesky rx_no_buffer_count increment */
2663                 rxdctl |= 0x0020;
2664                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2665                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2666                 if (hw->mac.type == ixgbe_mac_82599EB)
2667                         ixgbe_rx_desc_queue_enable(adapter, i);
2668         }
2669         /* enable all receives */
2670         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2671         if (hw->mac.type == ixgbe_mac_82598EB)
2672                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2673         else
2674                 rxdctl |= IXGBE_RXCTRL_RXEN;
2675         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2676
2677         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2678                 ixgbe_configure_msix(adapter);
2679         else
2680                 ixgbe_configure_msi_and_legacy(adapter);
2681
2682         clear_bit(__IXGBE_DOWN, &adapter->state);
2683         ixgbe_napi_enable_all(adapter);
2684
2685         /* clear any pending interrupts, may auto mask */
2686         IXGBE_READ_REG(hw, IXGBE_EICR);
2687
2688         ixgbe_irq_enable(adapter);
2689
2690         /*
2691          * If this adapter has a fan, check to see if we had a failure
2692          * before we enabled the interrupt.
2693          */
2694         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2695                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2696                 if (esdp & IXGBE_ESDP_SDP1)
2697                         DPRINTK(DRV, CRIT,
2698                                 "Fan has stopped, replace the adapter\n");
2699         }
2700
2701         /*
2702          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2703          * arrived before interrupts were enabled but after probe.  Such
2704          * devices wouldn't have their type identified yet. We need to
2705          * kick off the SFP+ module setup first, then try to bring up link.
2706          * If we're not hot-pluggable SFP+, we just need to configure link
2707          * and bring it up.
2708          */
2709         if (hw->phy.type == ixgbe_phy_unknown) {
2710                 err = hw->phy.ops.identify(hw);
2711                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2712                         /*
2713                          * Take the device down and schedule the sfp tasklet
2714                          * which will unregister_netdev and log it.
2715                          */
2716                         ixgbe_down(adapter);
2717                         schedule_work(&adapter->sfp_config_module_task);
2718                         return err;
2719                 }
2720         }
2721
2722         if (ixgbe_is_sfp(hw)) {
2723                 ixgbe_sfp_link_config(adapter);
2724         } else {
2725                 err = ixgbe_non_sfp_link_config(hw);
2726                 if (err)
2727                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2728         }
2729
2730         for (i = 0; i < adapter->num_tx_queues; i++)
2731                 set_bit(__IXGBE_FDIR_INIT_DONE,
2732                         &(adapter->tx_ring[i].reinit_state));
2733
2734         /* enable transmits */
2735         netif_tx_start_all_queues(netdev);
2736
2737         /* bring the link up in the watchdog, this could race with our first
2738          * link up interrupt but shouldn't be a problem */
2739         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2740         adapter->link_check_timeout = jiffies;
2741         mod_timer(&adapter->watchdog_timer, jiffies);
2742         return 0;
2743 }
2744
2745 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2746 {
2747         WARN_ON(in_interrupt());
2748         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2749                 msleep(1);
2750         ixgbe_down(adapter);
2751         ixgbe_up(adapter);
2752         clear_bit(__IXGBE_RESETTING, &adapter->state);
2753 }
2754
2755 int ixgbe_up(struct ixgbe_adapter *adapter)
2756 {
2757         /* hardware has been reset, we need to reload some things */
2758         ixgbe_configure(adapter);
2759
2760         return ixgbe_up_complete(adapter);
2761 }
2762
2763 void ixgbe_reset(struct ixgbe_adapter *adapter)
2764 {
2765         struct ixgbe_hw *hw = &adapter->hw;
2766         int err;
2767
2768         err = hw->mac.ops.init_hw(hw);
2769         switch (err) {
2770         case 0:
2771         case IXGBE_ERR_SFP_NOT_PRESENT:
2772                 break;
2773         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2774                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2775                 break;
2776         case IXGBE_ERR_EEPROM_VERSION:
2777                 /* We are running on a pre-production device, log a warning */
2778                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2779                          "adapter/LOM.  Please be aware there may be issues "
2780                          "associated with your hardware.  If you are "
2781                          "experiencing problems please contact your Intel or "
2782                          "hardware representative who provided you with this "
2783                          "hardware.\n");
2784                 break;
2785         default:
2786                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2787         }
2788
2789         /* reprogram the RAR[0] in case user changed it. */
2790         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2791 }
2792
2793 /**
2794  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2795  * @adapter: board private structure
2796  * @rx_ring: ring to free buffers from
2797  **/
2798 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2799                                 struct ixgbe_ring *rx_ring)
2800 {
2801         struct pci_dev *pdev = adapter->pdev;
2802         unsigned long size;
2803         unsigned int i;
2804
2805         /* Free all the Rx ring sk_buffs */
2806
2807         for (i = 0; i < rx_ring->count; i++) {
2808                 struct ixgbe_rx_buffer *rx_buffer_info;
2809
2810                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2811                 if (rx_buffer_info->dma) {
2812                         pci_unmap_single(pdev, rx_buffer_info->dma,
2813                                          rx_ring->rx_buf_len,
2814                                          PCI_DMA_FROMDEVICE);
2815                         rx_buffer_info->dma = 0;
2816                 }
2817                 if (rx_buffer_info->skb) {
2818                         struct sk_buff *skb = rx_buffer_info->skb;
2819                         rx_buffer_info->skb = NULL;
2820                         do {
2821                                 struct sk_buff *this = skb;
2822                                 skb = skb->prev;
2823                                 dev_kfree_skb(this);
2824                         } while (skb);
2825                 }
2826                 if (!rx_buffer_info->page)
2827                         continue;
2828                 if (rx_buffer_info->page_dma) {
2829                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2830                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2831                         rx_buffer_info->page_dma = 0;
2832                 }
2833                 put_page(rx_buffer_info->page);
2834                 rx_buffer_info->page = NULL;
2835                 rx_buffer_info->page_offset = 0;
2836         }
2837
2838         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2839         memset(rx_ring->rx_buffer_info, 0, size);
2840
2841         /* Zero out the descriptor ring */
2842         memset(rx_ring->desc, 0, rx_ring->size);
2843
2844         rx_ring->next_to_clean = 0;
2845         rx_ring->next_to_use = 0;
2846
2847         if (rx_ring->head)
2848                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2849         if (rx_ring->tail)
2850                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2851 }
2852
2853 /**
2854  * ixgbe_clean_tx_ring - Free Tx Buffers
2855  * @adapter: board private structure
2856  * @tx_ring: ring to be cleaned
2857  **/
2858 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2859                                 struct ixgbe_ring *tx_ring)
2860 {
2861         struct ixgbe_tx_buffer *tx_buffer_info;
2862         unsigned long size;
2863         unsigned int i;
2864
2865         /* Free all the Tx ring sk_buffs */
2866
2867         for (i = 0; i < tx_ring->count; i++) {
2868                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2869                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2870         }
2871
2872         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2873         memset(tx_ring->tx_buffer_info, 0, size);
2874
2875         /* Zero out the descriptor ring */
2876         memset(tx_ring->desc, 0, tx_ring->size);
2877
2878         tx_ring->next_to_use = 0;
2879         tx_ring->next_to_clean = 0;
2880
2881         if (tx_ring->head)
2882                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2883         if (tx_ring->tail)
2884                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2885 }
2886
2887 /**
2888  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2889  * @adapter: board private structure
2890  **/
2891 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2892 {
2893         int i;
2894
2895         for (i = 0; i < adapter->num_rx_queues; i++)
2896                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2897 }
2898
2899 /**
2900  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2901  * @adapter: board private structure
2902  **/
2903 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2904 {
2905         int i;
2906
2907         for (i = 0; i < adapter->num_tx_queues; i++)
2908                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2909 }
2910
2911 void ixgbe_down(struct ixgbe_adapter *adapter)
2912 {
2913         struct net_device *netdev = adapter->netdev;
2914         struct ixgbe_hw *hw = &adapter->hw;
2915         u32 rxctrl;
2916         u32 txdctl;
2917         int i, j;
2918
2919         /* signal that we are down to the interrupt handler */
2920         set_bit(__IXGBE_DOWN, &adapter->state);
2921
2922         /* disable receives */
2923         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2924         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2925
2926         netif_tx_disable(netdev);
2927
2928         IXGBE_WRITE_FLUSH(hw);
2929         msleep(10);
2930
2931         netif_tx_stop_all_queues(netdev);
2932
2933         ixgbe_irq_disable(adapter);
2934
2935         ixgbe_napi_disable_all(adapter);
2936
2937         del_timer_sync(&adapter->watchdog_timer);
2938         cancel_work_sync(&adapter->watchdog_task);
2939
2940         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2941             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2942                 cancel_work_sync(&adapter->fdir_reinit_task);
2943
2944         /* disable transmits in the hardware now that interrupts are off */
2945         for (i = 0; i < adapter->num_tx_queues; i++) {
2946                 j = adapter->tx_ring[i].reg_idx;
2947                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2948                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2949                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2950         }
2951         /* Disable the Tx DMA engine on 82599 */
2952         if (hw->mac.type == ixgbe_mac_82599EB)
2953                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2954                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2955                                  ~IXGBE_DMATXCTL_TE));
2956
2957         netif_carrier_off(netdev);
2958
2959         if (!pci_channel_offline(adapter->pdev))
2960                 ixgbe_reset(adapter);
2961         ixgbe_clean_all_tx_rings(adapter);
2962         ixgbe_clean_all_rx_rings(adapter);
2963
2964 #ifdef CONFIG_IXGBE_DCA
2965         /* since we reset the hardware DCA settings were cleared */
2966         ixgbe_setup_dca(adapter);
2967 #endif
2968 }
2969
2970 /**
2971  * ixgbe_poll - NAPI Rx polling callback
2972  * @napi: structure for representing this polling device
2973  * @budget: how many packets driver is allowed to clean
2974  *
2975  * This function is used for legacy and MSI, NAPI mode
2976  **/
2977 static int ixgbe_poll(struct napi_struct *napi, int budget)
2978 {
2979         struct ixgbe_q_vector *q_vector =
2980                                 container_of(napi, struct ixgbe_q_vector, napi);
2981         struct ixgbe_adapter *adapter = q_vector->adapter;
2982         int tx_clean_complete, work_done = 0;
2983
2984 #ifdef CONFIG_IXGBE_DCA
2985         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2986                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2987                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2988         }
2989 #endif
2990
2991         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
2992         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2993
2994         if (!tx_clean_complete)
2995                 work_done = budget;
2996
2997         /* If budget not fully consumed, exit the polling mode */
2998         if (work_done < budget) {
2999                 napi_complete(napi);
3000                 if (adapter->itr_setting & 1)
3001                         ixgbe_set_itr(adapter);
3002                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3003                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3004         }
3005         return work_done;
3006 }
3007
3008 /**
3009  * ixgbe_tx_timeout - Respond to a Tx Hang
3010  * @netdev: network interface device structure
3011  **/
3012 static void ixgbe_tx_timeout(struct net_device *netdev)
3013 {
3014         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3015
3016         /* Do the reset outside of interrupt context */
3017         schedule_work(&adapter->reset_task);
3018 }
3019
3020 static void ixgbe_reset_task(struct work_struct *work)
3021 {
3022         struct ixgbe_adapter *adapter;
3023         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3024
3025         /* If we're already down or resetting, just bail */
3026         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3027             test_bit(__IXGBE_RESETTING, &adapter->state))
3028                 return;
3029
3030         adapter->tx_timeout_count++;
3031
3032         ixgbe_reinit_locked(adapter);
3033 }
3034
3035 #ifdef CONFIG_IXGBE_DCB
3036 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3037 {
3038         bool ret = false;
3039         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3040
3041         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3042                 return ret;
3043
3044         f->mask = 0x7 << 3;
3045         adapter->num_rx_queues = f->indices;
3046         adapter->num_tx_queues = f->indices;
3047         ret = true;
3048
3049         return ret;
3050 }
3051 #endif
3052
3053 /**
3054  * ixgbe_set_rss_queues: Allocate queues for RSS
3055  * @adapter: board private structure to initialize
3056  *
3057  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3058  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3059  *
3060  **/
3061 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3062 {
3063         bool ret = false;
3064         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3065
3066         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3067                 f->mask = 0xF;
3068                 adapter->num_rx_queues = f->indices;
3069                 adapter->num_tx_queues = f->indices;
3070                 ret = true;
3071         } else {
3072                 ret = false;
3073         }
3074
3075         return ret;
3076 }
3077
3078 /**
3079  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3080  * @adapter: board private structure to initialize
3081  *
3082  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3083  * to the original CPU that initiated the Tx session.  This runs in addition
3084  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3085  * Rx load across CPUs using RSS.
3086  *
3087  **/
3088 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3089 {
3090         bool ret = false;
3091         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3092
3093         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3094         f_fdir->mask = 0;
3095
3096         /* Flow Director must have RSS enabled */
3097         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3098             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3099              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3100                 adapter->num_tx_queues = f_fdir->indices;
3101                 adapter->num_rx_queues = f_fdir->indices;
3102                 ret = true;
3103         } else {
3104                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3105                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3106         }
3107         return ret;
3108 }
3109
3110 #ifdef IXGBE_FCOE
3111 /**
3112  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3113  * @adapter: board private structure to initialize
3114  *
3115  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3116  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3117  * rx queues out of the max number of rx queues, instead, it is used as the
3118  * index of the first rx queue used by FCoE.
3119  *
3120  **/
3121 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3122 {
3123         bool ret = false;
3124         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3125
3126         f->indices = min((int)num_online_cpus(), f->indices);
3127         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3128 #ifdef CONFIG_IXGBE_DCB
3129                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3130                         DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
3131                         ixgbe_set_dcb_queues(adapter);
3132                 }
3133 #endif
3134                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3135                         DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
3136                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3137                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3138                                 ixgbe_set_fdir_queues(adapter);
3139                         else
3140                                 ixgbe_set_rss_queues(adapter);
3141                 }
3142                 /* adding FCoE rx rings to the end */
3143                 f->mask = adapter->num_rx_queues;
3144                 adapter->num_rx_queues += f->indices;
3145                 if (adapter->num_tx_queues == 0)
3146                         adapter->num_tx_queues = f->indices;
3147
3148                 ret = true;
3149         }
3150
3151         return ret;
3152 }
3153
3154 #endif /* IXGBE_FCOE */
3155 /*
3156  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3157  * @adapter: board private structure to initialize
3158  *
3159  * This is the top level queue allocation routine.  The order here is very
3160  * important, starting with the "most" number of features turned on at once,
3161  * and ending with the smallest set of features.  This way large combinations
3162  * can be allocated if they're turned on, and smaller combinations are the
3163  * fallthrough conditions.
3164  *
3165  **/
3166 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3167 {
3168 #ifdef IXGBE_FCOE
3169         if (ixgbe_set_fcoe_queues(adapter))
3170                 goto done;
3171
3172 #endif /* IXGBE_FCOE */
3173 #ifdef CONFIG_IXGBE_DCB
3174         if (ixgbe_set_dcb_queues(adapter))
3175                 goto done;
3176
3177 #endif
3178         if (ixgbe_set_fdir_queues(adapter))
3179                 goto done;
3180
3181         if (ixgbe_set_rss_queues(adapter))
3182                 goto done;
3183
3184         /* fallback to base case */
3185         adapter->num_rx_queues = 1;
3186         adapter->num_tx_queues = 1;
3187
3188 done:
3189         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3190         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3191 }
3192
3193 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3194                                        int vectors)
3195 {
3196         int err, vector_threshold;
3197
3198         /* We'll want at least 3 (vector_threshold):
3199          * 1) TxQ[0] Cleanup
3200          * 2) RxQ[0] Cleanup
3201          * 3) Other (Link Status Change, etc.)
3202          * 4) TCP Timer (optional)
3203          */
3204         vector_threshold = MIN_MSIX_COUNT;
3205
3206         /* The more we get, the more we will assign to Tx/Rx Cleanup
3207          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3208          * Right now, we simply care about how many we'll get; we'll
3209          * set them up later while requesting irq's.
3210          */
3211         while (vectors >= vector_threshold) {
3212                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3213                                       vectors);
3214                 if (!err) /* Success in acquiring all requested vectors. */
3215                         break;
3216                 else if (err < 0)
3217                         vectors = 0; /* Nasty failure, quit now */
3218                 else /* err == number of vectors we should try again with */
3219                         vectors = err;
3220         }
3221
3222         if (vectors < vector_threshold) {
3223                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3224                  * This just means we'll go with either a single MSI
3225                  * vector or fall back to legacy interrupts.
3226                  */
3227                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3228                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3229                 kfree(adapter->msix_entries);
3230                 adapter->msix_entries = NULL;
3231         } else {
3232                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3233                 /*
3234                  * Adjust for only the vectors we'll use, which is minimum
3235                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3236                  * vectors we were allocated.
3237                  */
3238                 adapter->num_msix_vectors = min(vectors,
3239                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3240         }
3241 }
3242
3243 /**
3244  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3245  * @adapter: board private structure to initialize
3246  *
3247  * Cache the descriptor ring offsets for RSS to the assigned rings.
3248  *
3249  **/
3250 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3251 {
3252         int i;
3253         bool ret = false;
3254
3255         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3256                 for (i = 0; i < adapter->num_rx_queues; i++)
3257                         adapter->rx_ring[i].reg_idx = i;
3258                 for (i = 0; i < adapter->num_tx_queues; i++)
3259                         adapter->tx_ring[i].reg_idx = i;
3260                 ret = true;
3261         } else {
3262                 ret = false;
3263         }
3264
3265         return ret;
3266 }
3267
3268 #ifdef CONFIG_IXGBE_DCB
3269 /**
3270  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3271  * @adapter: board private structure to initialize
3272  *
3273  * Cache the descriptor ring offsets for DCB to the assigned rings.
3274  *
3275  **/
3276 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3277 {
3278         int i;
3279         bool ret = false;
3280         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3281
3282         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3283                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3284                         /* the number of queues is assumed to be symmetric */
3285                         for (i = 0; i < dcb_i; i++) {
3286                                 adapter->rx_ring[i].reg_idx = i << 3;
3287                                 adapter->tx_ring[i].reg_idx = i << 2;
3288                         }
3289                         ret = true;
3290                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3291                         if (dcb_i == 8) {
3292                                 /*
3293                                  * Tx TC0 starts at: descriptor queue 0
3294                                  * Tx TC1 starts at: descriptor queue 32
3295                                  * Tx TC2 starts at: descriptor queue 64
3296                                  * Tx TC3 starts at: descriptor queue 80
3297                                  * Tx TC4 starts at: descriptor queue 96
3298                                  * Tx TC5 starts at: descriptor queue 104
3299                                  * Tx TC6 starts at: descriptor queue 112
3300                                  * Tx TC7 starts at: descriptor queue 120
3301                                  *
3302                                  * Rx TC0-TC7 are offset by 16 queues each
3303                                  */
3304                                 for (i = 0; i < 3; i++) {
3305                                         adapter->tx_ring[i].reg_idx = i << 5;
3306                                         adapter->rx_ring[i].reg_idx = i << 4;
3307                                 }
3308                                 for ( ; i < 5; i++) {
3309                                         adapter->tx_ring[i].reg_idx =
3310                                                                  ((i + 2) << 4);
3311                                         adapter->rx_ring[i].reg_idx = i << 4;
3312                                 }
3313                                 for ( ; i < dcb_i; i++) {
3314                                         adapter->tx_ring[i].reg_idx =
3315                                                                  ((i + 8) << 3);
3316                                         adapter->rx_ring[i].reg_idx = i << 4;
3317                                 }
3318
3319                                 ret = true;
3320                         } else if (dcb_i == 4) {
3321                                 /*
3322                                  * Tx TC0 starts at: descriptor queue 0
3323                                  * Tx TC1 starts at: descriptor queue 64
3324                                  * Tx TC2 starts at: descriptor queue 96
3325                                  * Tx TC3 starts at: descriptor queue 112
3326                                  *
3327                                  * Rx TC0-TC3 are offset by 32 queues each
3328                                  */
3329                                 adapter->tx_ring[0].reg_idx = 0;
3330                                 adapter->tx_ring[1].reg_idx = 64;
3331                                 adapter->tx_ring[2].reg_idx = 96;
3332                                 adapter->tx_ring[3].reg_idx = 112;
3333                                 for (i = 0 ; i < dcb_i; i++)
3334                                         adapter->rx_ring[i].reg_idx = i << 5;
3335
3336                                 ret = true;
3337                         } else {
3338                                 ret = false;
3339                         }
3340                 } else {
3341                         ret = false;
3342                 }
3343         } else {
3344                 ret = false;
3345         }
3346
3347         return ret;
3348 }
3349 #endif
3350
3351 /**
3352  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3353  * @adapter: board private structure to initialize
3354  *
3355  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3356  *
3357  **/
3358 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3359 {
3360         int i;
3361         bool ret = false;
3362
3363         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3364             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3365              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3366                 for (i = 0; i < adapter->num_rx_queues; i++)
3367                         adapter->rx_ring[i].reg_idx = i;
3368                 for (i = 0; i < adapter->num_tx_queues; i++)
3369                         adapter->tx_ring[i].reg_idx = i;
3370                 ret = true;
3371         }
3372
3373         return ret;
3374 }
3375
3376 #ifdef IXGBE_FCOE
3377 /**
3378  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3379  * @adapter: board private structure to initialize
3380  *
3381  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3382  *
3383  */
3384 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3385 {
3386         int i, fcoe_i = 0;
3387         bool ret = false;
3388         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3389
3390         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3391 #ifdef CONFIG_IXGBE_DCB
3392                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3393                         ixgbe_cache_ring_dcb(adapter);
3394                         fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3395                 }
3396 #endif /* CONFIG_IXGBE_DCB */
3397                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3398                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3399                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3400                                 ixgbe_cache_ring_fdir(adapter);
3401                         else
3402                                 ixgbe_cache_ring_rss(adapter);
3403
3404                         fcoe_i = f->mask;
3405                 }
3406                 for (i = 0; i < f->indices; i++, fcoe_i++)
3407                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3408                 ret = true;
3409         }
3410         return ret;
3411 }
3412
3413 #endif /* IXGBE_FCOE */
3414 /**
3415  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3416  * @adapter: board private structure to initialize
3417  *
3418  * Once we know the feature-set enabled for the device, we'll cache
3419  * the register offset the descriptor ring is assigned to.
3420  *
3421  * Note, the order the various feature calls is important.  It must start with
3422  * the "most" features enabled at the same time, then trickle down to the
3423  * least amount of features turned on at once.
3424  **/
3425 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3426 {
3427         /* start with default case */
3428         adapter->rx_ring[0].reg_idx = 0;
3429         adapter->tx_ring[0].reg_idx = 0;
3430
3431 #ifdef IXGBE_FCOE
3432         if (ixgbe_cache_ring_fcoe(adapter))
3433                 return;
3434
3435 #endif /* IXGBE_FCOE */
3436 #ifdef CONFIG_IXGBE_DCB
3437         if (ixgbe_cache_ring_dcb(adapter))
3438                 return;
3439
3440 #endif
3441         if (ixgbe_cache_ring_fdir(adapter))
3442                 return;
3443
3444         if (ixgbe_cache_ring_rss(adapter))
3445                 return;
3446 }
3447
3448 /**
3449  * ixgbe_alloc_queues - Allocate memory for all rings
3450  * @adapter: board private structure to initialize
3451  *
3452  * We allocate one ring per queue at run-time since we don't know the
3453  * number of queues at compile-time.  The polling_netdev array is
3454  * intended for Multiqueue, but should work fine with a single queue.
3455  **/
3456 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3457 {
3458         int i;
3459
3460         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3461                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3462         if (!adapter->tx_ring)
3463                 goto err_tx_ring_allocation;
3464
3465         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3466                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3467         if (!adapter->rx_ring)
3468                 goto err_rx_ring_allocation;
3469
3470         for (i = 0; i < adapter->num_tx_queues; i++) {
3471                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3472                 adapter->tx_ring[i].queue_index = i;
3473         }
3474
3475         for (i = 0; i < adapter->num_rx_queues; i++) {
3476                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3477                 adapter->rx_ring[i].queue_index = i;
3478         }
3479
3480         ixgbe_cache_ring_register(adapter);
3481
3482         return 0;
3483
3484 err_rx_ring_allocation:
3485         kfree(adapter->tx_ring);
3486 err_tx_ring_allocation:
3487         return -ENOMEM;
3488 }
3489
3490 /**
3491  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3492  * @adapter: board private structure to initialize
3493  *
3494  * Attempt to configure the interrupts using the best available
3495  * capabilities of the hardware and the kernel.
3496  **/
3497 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3498 {
3499         struct ixgbe_hw *hw = &adapter->hw;
3500         int err = 0;
3501         int vector, v_budget;
3502
3503         /*
3504          * It's easy to be greedy for MSI-X vectors, but it really
3505          * doesn't do us much good if we have a lot more vectors
3506          * than CPU's.  So let's be conservative and only ask for
3507          * (roughly) twice the number of vectors as there are CPU's.
3508          */
3509         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3510                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3511
3512         /*
3513          * At the same time, hardware can only support a maximum of
3514          * hw.mac->max_msix_vectors vectors.  With features
3515          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3516          * descriptor queues supported by our device.  Thus, we cap it off in
3517          * those rare cases where the cpu count also exceeds our vector limit.
3518          */
3519         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3520
3521         /* A failure in MSI-X entry allocation isn't fatal, but it does
3522          * mean we disable MSI-X capabilities of the adapter. */
3523         adapter->msix_entries = kcalloc(v_budget,
3524                                         sizeof(struct msix_entry), GFP_KERNEL);
3525         if (adapter->msix_entries) {
3526                 for (vector = 0; vector < v_budget; vector++)
3527                         adapter->msix_entries[vector].entry = vector;
3528
3529                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3530
3531                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3532                         goto out;
3533         }
3534
3535         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3536         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3537         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3538         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3539         adapter->atr_sample_rate = 0;
3540         ixgbe_set_num_queues(adapter);
3541
3542         err = pci_enable_msi(adapter->pdev);
3543         if (!err) {
3544                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3545         } else {
3546                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3547                         "falling back to legacy.  Error: %d\n", err);
3548                 /* reset err */
3549                 err = 0;
3550         }
3551
3552 out:
3553         return err;
3554 }
3555
3556 /**
3557  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3558  * @adapter: board private structure to initialize
3559  *
3560  * We allocate one q_vector per queue interrupt.  If allocation fails we
3561  * return -ENOMEM.
3562  **/
3563 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3564 {
3565         int q_idx, num_q_vectors;
3566         struct ixgbe_q_vector *q_vector;
3567         int napi_vectors;
3568         int (*poll)(struct napi_struct *, int);
3569
3570         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3571                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3572                 napi_vectors = adapter->num_rx_queues;
3573                 poll = &ixgbe_clean_rxtx_many;
3574         } else {
3575                 num_q_vectors = 1;
3576                 napi_vectors = 1;
3577                 poll = &ixgbe_poll;
3578         }
3579
3580         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3581                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3582                 if (!q_vector)
3583                         goto err_out;
3584                 q_vector->adapter = adapter;
3585                 q_vector->eitr = adapter->eitr_param;
3586                 q_vector->v_idx = q_idx;
3587                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3588                 adapter->q_vector[q_idx] = q_vector;
3589         }
3590
3591         return 0;
3592
3593 err_out:
3594         while (q_idx) {
3595                 q_idx--;
3596                 q_vector = adapter->q_vector[q_idx];
3597                 netif_napi_del(&q_vector->napi);
3598                 kfree(q_vector);
3599                 adapter->q_vector[q_idx] = NULL;
3600         }
3601         return -ENOMEM;
3602 }
3603
3604 /**
3605  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3606  * @adapter: board private structure to initialize
3607  *
3608  * This function frees the memory allocated to the q_vectors.  In addition if
3609  * NAPI is enabled it will delete any references to the NAPI struct prior
3610  * to freeing the q_vector.
3611  **/
3612 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3613 {
3614         int q_idx, num_q_vectors;
3615
3616         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3617                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3618         else
3619                 num_q_vectors = 1;
3620
3621         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3622                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3623                 adapter->q_vector[q_idx] = NULL;
3624                 netif_napi_del(&q_vector->napi);
3625                 kfree(q_vector);
3626         }
3627 }
3628
3629 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3630 {
3631         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3632                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3633                 pci_disable_msix(adapter->pdev);
3634                 kfree(adapter->msix_entries);
3635                 adapter->msix_entries = NULL;
3636         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3637                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3638                 pci_disable_msi(adapter->pdev);
3639         }
3640         return;
3641 }
3642
3643 /**
3644  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3645  * @adapter: board private structure to initialize
3646  *
3647  * We determine which interrupt scheme to use based on...
3648  * - Kernel support (MSI, MSI-X)
3649  *   - which can be user-defined (via MODULE_PARAM)
3650  * - Hardware queue count (num_*_queues)
3651  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3652  **/
3653 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3654 {
3655         int err;
3656
3657         /* Number of supported queues */
3658         ixgbe_set_num_queues(adapter);
3659
3660         err = ixgbe_set_interrupt_capability(adapter);
3661         if (err) {
3662                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3663                 goto err_set_interrupt;
3664         }
3665
3666         err = ixgbe_alloc_q_vectors(adapter);
3667         if (err) {
3668                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3669                         "vectors\n");
3670                 goto err_alloc_q_vectors;
3671         }
3672
3673         err = ixgbe_alloc_queues(adapter);
3674         if (err) {
3675                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3676                 goto err_alloc_queues;
3677         }
3678
3679         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3680                 "Tx Queue count = %u\n",
3681                 (adapter->num_rx_queues > 1) ? "Enabled" :
3682                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3683
3684         set_bit(__IXGBE_DOWN, &adapter->state);
3685
3686         return 0;
3687
3688 err_alloc_queues:
3689         ixgbe_free_q_vectors(adapter);
3690 err_alloc_q_vectors:
3691         ixgbe_reset_interrupt_capability(adapter);
3692 err_set_interrupt:
3693         return err;
3694 }
3695
3696 /**
3697  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3698  * @adapter: board private structure to clear interrupt scheme on
3699  *
3700  * We go through and clear interrupt specific resources and reset the structure
3701  * to pre-load conditions
3702  **/
3703 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3704 {
3705         kfree(adapter->tx_ring);
3706         kfree(adapter->rx_ring);
3707         adapter->tx_ring = NULL;
3708         adapter->rx_ring = NULL;
3709
3710         ixgbe_free_q_vectors(adapter);
3711         ixgbe_reset_interrupt_capability(adapter);
3712 }
3713
3714 /**
3715  * ixgbe_sfp_timer - worker thread to find a missing module
3716  * @data: pointer to our adapter struct
3717  **/
3718 static void ixgbe_sfp_timer(unsigned long data)
3719 {
3720         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3721
3722         /*
3723          * Do the sfp_timer outside of interrupt context due to the
3724          * delays that sfp+ detection requires
3725          */
3726         schedule_work(&adapter->sfp_task);
3727 }
3728
3729 /**
3730  * ixgbe_sfp_task - worker thread to find a missing module
3731  * @work: pointer to work_struct containing our data
3732  **/
3733 static void ixgbe_sfp_task(struct work_struct *work)
3734 {
3735         struct ixgbe_adapter *adapter = container_of(work,
3736                                                      struct ixgbe_adapter,
3737                                                      sfp_task);
3738         struct ixgbe_hw *hw = &adapter->hw;
3739
3740         if ((hw->phy.type == ixgbe_phy_nl) &&
3741             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3742                 s32 ret = hw->phy.ops.identify_sfp(hw);
3743                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3744                         goto reschedule;
3745                 ret = hw->phy.ops.reset(hw);
3746                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3747                         dev_err(&adapter->pdev->dev, "failed to initialize "
3748                                 "because an unsupported SFP+ module type "
3749                                 "was detected.\n"
3750                                 "Reload the driver after installing a "
3751                                 "supported module.\n");
3752                         unregister_netdev(adapter->netdev);
3753                 } else {
3754                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3755                                 hw->phy.sfp_type);
3756                 }
3757                 /* don't need this routine any more */
3758                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3759         }
3760         return;
3761 reschedule:
3762         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3763                 mod_timer(&adapter->sfp_timer,
3764                           round_jiffies(jiffies + (2 * HZ)));
3765 }
3766
3767 /**
3768  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3769  * @adapter: board private structure to initialize
3770  *
3771  * ixgbe_sw_init initializes the Adapter private data structure.
3772  * Fields are initialized based on PCI device information and
3773  * OS network device settings (MTU size).
3774  **/
3775 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3776 {
3777         struct ixgbe_hw *hw = &adapter->hw;
3778         struct pci_dev *pdev = adapter->pdev;
3779         unsigned int rss;
3780 #ifdef CONFIG_IXGBE_DCB
3781         int j;
3782         struct tc_configuration *tc;
3783 #endif
3784
3785         /* PCI config space info */
3786
3787         hw->vendor_id = pdev->vendor;
3788         hw->device_id = pdev->device;
3789         hw->revision_id = pdev->revision;
3790         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3791         hw->subsystem_device_id = pdev->subsystem_device;
3792
3793         /* Set capability flags */
3794         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3795         adapter->ring_feature[RING_F_RSS].indices = rss;
3796         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3797         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3798         if (hw->mac.type == ixgbe_mac_82598EB) {
3799                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3800                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3801                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3802         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3803                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3804                 adapter->flags |= IXGBE_FLAG2_RSC_CAPABLE;
3805                 adapter->flags |= IXGBE_FLAG2_RSC_ENABLED;
3806                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3807                 adapter->ring_feature[RING_F_FDIR].indices =
3808                                                          IXGBE_MAX_FDIR_INDICES;
3809                 adapter->atr_sample_rate = 20;
3810                 adapter->fdir_pballoc = 0;
3811 #ifdef IXGBE_FCOE
3812                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3813                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3814                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3815 #endif /* IXGBE_FCOE */
3816         }
3817
3818 #ifdef CONFIG_IXGBE_DCB
3819         /* Configure DCB traffic classes */
3820         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3821                 tc = &adapter->dcb_cfg.tc_config[j];
3822                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3823                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3824                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3825                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3826                 tc->dcb_pfc = pfc_disabled;
3827         }
3828         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3829         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3830         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3831         adapter->dcb_cfg.pfc_mode_enable = false;
3832         adapter->dcb_cfg.round_robin_enable = false;
3833         adapter->dcb_set_bitmap = 0x00;
3834         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3835                            adapter->ring_feature[RING_F_DCB].indices);
3836
3837 #endif
3838
3839         /* default flow control settings */
3840         hw->fc.requested_mode = ixgbe_fc_full;
3841         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3842 #ifdef CONFIG_DCB
3843         adapter->last_lfc_mode = hw->fc.current_mode;
3844 #endif
3845         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3846         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3847         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3848         hw->fc.send_xon = true;
3849         hw->fc.disable_fc_autoneg = false;
3850
3851         /* enable itr by default in dynamic mode */
3852         adapter->itr_setting = 1;
3853         adapter->eitr_param = 20000;
3854
3855         /* set defaults for eitr in MegaBytes */
3856         adapter->eitr_low = 10;
3857         adapter->eitr_high = 20;
3858
3859         /* set default ring sizes */
3860         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3861         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3862
3863         /* initialize eeprom parameters */
3864         if (ixgbe_init_eeprom_params_generic(hw)) {
3865                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3866                 return -EIO;
3867         }
3868
3869         /* enable rx csum by default */
3870         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3871
3872         set_bit(__IXGBE_DOWN, &adapter->state);
3873
3874         return 0;
3875 }
3876
3877 /**
3878  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3879  * @adapter: board private structure
3880  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3881  *
3882  * Return 0 on success, negative on failure
3883  **/
3884 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3885                              struct ixgbe_ring *tx_ring)
3886 {
3887         struct pci_dev *pdev = adapter->pdev;
3888         int size;
3889
3890         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3891         tx_ring->tx_buffer_info = vmalloc(size);
3892         if (!tx_ring->tx_buffer_info)
3893                 goto err;
3894         memset(tx_ring->tx_buffer_info, 0, size);
3895
3896         /* round up to nearest 4K */
3897         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3898         tx_ring->size = ALIGN(tx_ring->size, 4096);
3899
3900         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3901                                              &tx_ring->dma);
3902         if (!tx_ring->desc)
3903                 goto err;
3904
3905         tx_ring->next_to_use = 0;
3906         tx_ring->next_to_clean = 0;
3907         tx_ring->work_limit = tx_ring->count;
3908         return 0;
3909
3910 err:
3911         vfree(tx_ring->tx_buffer_info);
3912         tx_ring->tx_buffer_info = NULL;
3913         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3914                             "descriptor ring\n");
3915         return -ENOMEM;
3916 }
3917
3918 /**
3919  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3920  * @adapter: board private structure
3921  *
3922  * If this function returns with an error, then it's possible one or
3923  * more of the rings is populated (while the rest are not).  It is the
3924  * callers duty to clean those orphaned rings.
3925  *
3926  * Return 0 on success, negative on failure
3927  **/
3928 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3929 {
3930         int i, err = 0;
3931
3932         for (i = 0; i < adapter->num_tx_queues; i++) {
3933                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3934                 if (!err)
3935                         continue;
3936                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3937                 break;
3938         }
3939
3940         return err;
3941 }
3942
3943 /**
3944  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3945  * @adapter: board private structure
3946  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
3947  *
3948  * Returns 0 on success, negative on failure
3949  **/
3950 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3951                              struct ixgbe_ring *rx_ring)
3952 {
3953         struct pci_dev *pdev = adapter->pdev;
3954         int size;
3955
3956         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3957         rx_ring->rx_buffer_info = vmalloc(size);
3958         if (!rx_ring->rx_buffer_info) {
3959                 DPRINTK(PROBE, ERR,
3960                         "vmalloc allocation failed for the rx desc ring\n");
3961                 goto alloc_failed;
3962         }
3963         memset(rx_ring->rx_buffer_info, 0, size);
3964
3965         /* Round up to nearest 4K */
3966         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3967         rx_ring->size = ALIGN(rx_ring->size, 4096);
3968
3969         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3970
3971         if (!rx_ring->desc) {
3972                 DPRINTK(PROBE, ERR,
3973                         "Memory allocation failed for the rx desc ring\n");
3974                 vfree(rx_ring->rx_buffer_info);
3975                 goto alloc_failed;
3976         }
3977
3978         rx_ring->next_to_clean = 0;
3979         rx_ring->next_to_use = 0;
3980
3981         return 0;
3982
3983 alloc_failed:
3984         return -ENOMEM;
3985 }
3986
3987 /**
3988  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3989  * @adapter: board private structure
3990  *
3991  * If this function returns with an error, then it's possible one or
3992  * more of the rings is populated (while the rest are not).  It is the
3993  * callers duty to clean those orphaned rings.
3994  *
3995  * Return 0 on success, negative on failure
3996  **/
3997
3998 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3999 {
4000         int i, err = 0;
4001
4002         for (i = 0; i < adapter->num_rx_queues; i++) {
4003                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4004                 if (!err)
4005                         continue;
4006                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4007                 break;
4008         }
4009
4010         return err;
4011 }
4012
4013 /**
4014  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4015  * @adapter: board private structure
4016  * @tx_ring: Tx descriptor ring for a specific queue
4017  *
4018  * Free all transmit software resources
4019  **/
4020 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4021                              struct ixgbe_ring *tx_ring)
4022 {
4023         struct pci_dev *pdev = adapter->pdev;
4024
4025         ixgbe_clean_tx_ring(adapter, tx_ring);
4026
4027         vfree(tx_ring->tx_buffer_info);
4028         tx_ring->tx_buffer_info = NULL;
4029
4030         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4031
4032         tx_ring->desc = NULL;
4033 }
4034
4035 /**
4036  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4037  * @adapter: board private structure
4038  *
4039  * Free all transmit software resources
4040  **/
4041 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4042 {
4043         int i;
4044
4045         for (i = 0; i < adapter->num_tx_queues; i++)
4046                 if (adapter->tx_ring[i].desc)
4047                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4048 }
4049
4050 /**
4051  * ixgbe_free_rx_resources - Free Rx Resources
4052  * @adapter: board private structure
4053  * @rx_ring: ring to clean the resources from
4054  *
4055  * Free all receive software resources
4056  **/
4057 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4058                              struct ixgbe_ring *rx_ring)
4059 {
4060         struct pci_dev *pdev = adapter->pdev;
4061
4062         ixgbe_clean_rx_ring(adapter, rx_ring);
4063
4064         vfree(rx_ring->rx_buffer_info);
4065         rx_ring->rx_buffer_info = NULL;
4066
4067         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4068
4069         rx_ring->desc = NULL;
4070 }
4071
4072 /**
4073  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4074  * @adapter: board private structure
4075  *
4076  * Free all receive software resources
4077  **/
4078 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4079 {
4080         int i;
4081
4082         for (i = 0; i < adapter->num_rx_queues; i++)
4083                 if (adapter->rx_ring[i].desc)
4084                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4085 }
4086
4087 /**
4088  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4089  * @netdev: network interface device structure
4090  * @new_mtu: new value for maximum frame size
4091  *
4092  * Returns 0 on success, negative on failure
4093  **/
4094 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4095 {
4096         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4097         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4098
4099         /* MTU < 68 is an error and causes problems on some kernels */
4100         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4101                 return -EINVAL;
4102
4103         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4104                 netdev->mtu, new_mtu);
4105         /* must set new MTU before calling down or up */
4106         netdev->mtu = new_mtu;
4107
4108         if (netif_running(netdev))
4109                 ixgbe_reinit_locked(adapter);
4110
4111         return 0;
4112 }
4113
4114 /**
4115  * ixgbe_open - Called when a network interface is made active
4116  * @netdev: network interface device structure
4117  *
4118  * Returns 0 on success, negative value on failure
4119  *
4120  * The open entry point is called when a network interface is made
4121  * active by the system (IFF_UP).  At this point all resources needed
4122  * for transmit and receive operations are allocated, the interrupt
4123  * handler is registered with the OS, the watchdog timer is started,
4124  * and the stack is notified that the interface is ready.
4125  **/
4126 static int ixgbe_open(struct net_device *netdev)
4127 {
4128         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4129         int err;
4130
4131         /* disallow open during test */
4132         if (test_bit(__IXGBE_TESTING, &adapter->state))
4133                 return -EBUSY;
4134
4135         netif_carrier_off(netdev);
4136
4137         /* allocate transmit descriptors */
4138         err = ixgbe_setup_all_tx_resources(adapter);
4139         if (err)
4140                 goto err_setup_tx;
4141
4142         /* allocate receive descriptors */
4143         err = ixgbe_setup_all_rx_resources(adapter);
4144         if (err)
4145                 goto err_setup_rx;
4146
4147         ixgbe_configure(adapter);
4148
4149         err = ixgbe_request_irq(adapter);
4150         if (err)
4151                 goto err_req_irq;
4152
4153         err = ixgbe_up_complete(adapter);
4154         if (err)
4155                 goto err_up;
4156
4157         netif_tx_start_all_queues(netdev);
4158
4159         return 0;
4160
4161 err_up:
4162         ixgbe_release_hw_control(adapter);
4163         ixgbe_free_irq(adapter);
4164 err_req_irq:
4165 err_setup_rx:
4166         ixgbe_free_all_rx_resources(adapter);
4167 err_setup_tx:
4168         ixgbe_free_all_tx_resources(adapter);
4169         ixgbe_reset(adapter);
4170
4171         return err;
4172 }
4173
4174 /**
4175  * ixgbe_close - Disables a network interface
4176  * @netdev: network interface device structure
4177  *
4178  * Returns 0, this is not allowed to fail
4179  *
4180  * The close entry point is called when an interface is de-activated
4181  * by the OS.  The hardware is still under the drivers control, but
4182  * needs to be disabled.  A global MAC reset is issued to stop the
4183  * hardware, and all transmit and receive resources are freed.
4184  **/
4185 static int ixgbe_close(struct net_device *netdev)
4186 {
4187         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4188
4189         ixgbe_down(adapter);
4190         ixgbe_free_irq(adapter);
4191
4192         ixgbe_free_all_tx_resources(adapter);
4193         ixgbe_free_all_rx_resources(adapter);
4194
4195         ixgbe_release_hw_control(adapter);
4196
4197         return 0;
4198 }
4199
4200 #ifdef CONFIG_PM
4201 static int ixgbe_resume(struct pci_dev *pdev)
4202 {
4203         struct net_device *netdev = pci_get_drvdata(pdev);
4204         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4205         u32 err;
4206
4207         pci_set_power_state(pdev, PCI_D0);
4208         pci_restore_state(pdev);
4209
4210         err = pci_enable_device_mem(pdev);
4211         if (err) {
4212                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4213                                 "suspend\n");
4214                 return err;
4215         }
4216         pci_set_master(pdev);
4217
4218         pci_wake_from_d3(pdev, false);
4219
4220         err = ixgbe_init_interrupt_scheme(adapter);
4221         if (err) {
4222                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4223                                 "device\n");
4224                 return err;
4225         }
4226
4227         ixgbe_reset(adapter);
4228
4229         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4230
4231         if (netif_running(netdev)) {
4232                 err = ixgbe_open(adapter->netdev);
4233                 if (err)
4234                         return err;
4235         }
4236
4237         netif_device_attach(netdev);
4238
4239         return 0;
4240 }
4241 #endif /* CONFIG_PM */
4242
4243 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4244 {
4245         struct net_device *netdev = pci_get_drvdata(pdev);
4246         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4247         struct ixgbe_hw *hw = &adapter->hw;
4248         u32 ctrl, fctrl;
4249         u32 wufc = adapter->wol;
4250 #ifdef CONFIG_PM
4251         int retval = 0;
4252 #endif
4253
4254         netif_device_detach(netdev);
4255
4256         if (netif_running(netdev)) {
4257                 ixgbe_down(adapter);
4258                 ixgbe_free_irq(adapter);
4259                 ixgbe_free_all_tx_resources(adapter);
4260                 ixgbe_free_all_rx_resources(adapter);
4261         }
4262         ixgbe_clear_interrupt_scheme(adapter);
4263
4264 #ifdef CONFIG_PM
4265         retval = pci_save_state(pdev);
4266         if (retval)
4267                 return retval;
4268
4269 #endif
4270         if (wufc) {
4271                 ixgbe_set_rx_mode(netdev);
4272
4273                 /* turn on all-multi mode if wake on multicast is enabled */
4274                 if (wufc & IXGBE_WUFC_MC) {
4275                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4276                         fctrl |= IXGBE_FCTRL_MPE;
4277                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4278                 }
4279
4280                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4281                 ctrl |= IXGBE_CTRL_GIO_DIS;
4282                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4283
4284                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4285         } else {
4286                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4287                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4288         }
4289
4290         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4291                 pci_wake_from_d3(pdev, true);
4292         else
4293                 pci_wake_from_d3(pdev, false);
4294
4295         *enable_wake = !!wufc;
4296
4297         ixgbe_release_hw_control(adapter);
4298
4299         pci_disable_device(pdev);
4300
4301         return 0;
4302 }
4303
4304 #ifdef CONFIG_PM
4305 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4306 {
4307         int retval;
4308         bool wake;
4309
4310         retval = __ixgbe_shutdown(pdev, &wake);
4311         if (retval)
4312                 return retval;
4313
4314         if (wake) {
4315                 pci_prepare_to_sleep(pdev);
4316         } else {
4317                 pci_wake_from_d3(pdev, false);
4318                 pci_set_power_state(pdev, PCI_D3hot);
4319         }
4320
4321         return 0;
4322 }
4323 #endif /* CONFIG_PM */
4324
4325 static void ixgbe_shutdown(struct pci_dev *pdev)
4326 {
4327         bool wake;
4328
4329         __ixgbe_shutdown(pdev, &wake);
4330
4331         if (system_state == SYSTEM_POWER_OFF) {
4332                 pci_wake_from_d3(pdev, wake);
4333                 pci_set_power_state(pdev, PCI_D3hot);
4334         }
4335 }
4336
4337 /**
4338  * ixgbe_update_stats - Update the board statistics counters.
4339  * @adapter: board private structure
4340  **/
4341 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4342 {
4343         struct ixgbe_hw *hw = &adapter->hw;
4344         u64 total_mpc = 0;
4345         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4346
4347         if (hw->mac.type == ixgbe_mac_82599EB) {
4348                 u64 rsc_count = 0;
4349                 for (i = 0; i < 16; i++)
4350                         adapter->hw_rx_no_dma_resources +=
4351                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4352                 for (i = 0; i < adapter->num_rx_queues; i++)
4353                         rsc_count += adapter->rx_ring[i].rsc_count;
4354                 adapter->rsc_count = rsc_count;
4355         }
4356
4357         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4358         for (i = 0; i < 8; i++) {
4359                 /* for packet buffers not used, the register should read 0 */
4360                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4361                 missed_rx += mpc;
4362                 adapter->stats.mpc[i] += mpc;
4363                 total_mpc += adapter->stats.mpc[i];
4364                 if (hw->mac.type == ixgbe_mac_82598EB)
4365                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4366                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4367                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4368                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4369                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4370                 if (hw->mac.type == ixgbe_mac_82599EB) {
4371                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4372                                                             IXGBE_PXONRXCNT(i));
4373                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4374                                                            IXGBE_PXOFFRXCNT(i));
4375                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4376                 } else {
4377                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4378                                                               IXGBE_PXONRXC(i));
4379                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4380                                                              IXGBE_PXOFFRXC(i));
4381                 }
4382                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4383                                                             IXGBE_PXONTXC(i));
4384                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4385                                                              IXGBE_PXOFFTXC(i));
4386         }
4387         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4388         /* work around hardware counting issue */
4389         adapter->stats.gprc -= missed_rx;
4390
4391         /* 82598 hardware only has a 32 bit counter in the high register */
4392         if (hw->mac.type == ixgbe_mac_82599EB) {
4393                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4394                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4395                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4396                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4397                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4398                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4399                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4400                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4401                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4402                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4403 #ifdef IXGBE_FCOE
4404                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4405                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4406                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4407                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4408                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4409                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4410 #endif /* IXGBE_FCOE */
4411         } else {
4412                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4413                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4414                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4415                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4416                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4417         }
4418         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4419         adapter->stats.bprc += bprc;
4420         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4421         if (hw->mac.type == ixgbe_mac_82598EB)
4422                 adapter->stats.mprc -= bprc;
4423         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4424         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4425         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4426         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4427         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4428         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4429         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4430         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4431         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4432         adapter->stats.lxontxc += lxon;
4433         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4434         adapter->stats.lxofftxc += lxoff;
4435         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4436         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4437         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4438         /*
4439          * 82598 errata - tx of flow control packets is included in tx counters
4440          */
4441         xon_off_tot = lxon + lxoff;
4442         adapter->stats.gptc -= xon_off_tot;
4443         adapter->stats.mptc -= xon_off_tot;
4444         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4445         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4446         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4447         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4448         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4449         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4450         adapter->stats.ptc64 -= xon_off_tot;
4451         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4452         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4453         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4454         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4455         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4456         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4457
4458         /* Fill out the OS statistics structure */
4459         adapter->net_stats.multicast = adapter->stats.mprc;
4460
4461         /* Rx Errors */
4462         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4463                                        adapter->stats.rlec;
4464         adapter->net_stats.rx_dropped = 0;
4465         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4466         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4467         adapter->net_stats.rx_missed_errors = total_mpc;
4468 }
4469
4470 /**
4471  * ixgbe_watchdog - Timer Call-back
4472  * @data: pointer to adapter cast into an unsigned long
4473  **/
4474 static void ixgbe_watchdog(unsigned long data)
4475 {
4476         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4477         struct ixgbe_hw *hw = &adapter->hw;
4478         u64 eics = 0;
4479         int i;
4480
4481         /*
4482          *  Do the watchdog outside of interrupt context due to the lovely
4483          * delays that some of the newer hardware requires
4484          */
4485
4486         if (test_bit(__IXGBE_DOWN, &adapter->state))
4487                 goto watchdog_short_circuit;
4488
4489         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4490                 /*
4491                  * for legacy and MSI interrupts don't set any bits
4492                  * that are enabled for EIAM, because this operation
4493                  * would set *both* EIMS and EICS for any bit in EIAM
4494                  */
4495                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4496                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4497                 goto watchdog_reschedule;
4498         }
4499
4500         /* get one bit for every active tx/rx interrupt vector */
4501         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4502                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4503                 if (qv->rxr_count || qv->txr_count)
4504                         eics |= ((u64)1 << i);
4505         }
4506
4507         /* Cause software interrupt to ensure rx rings are cleaned */
4508         ixgbe_irq_rearm_queues(adapter, eics);
4509
4510 watchdog_reschedule:
4511         /* Reset the timer */
4512         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4513
4514 watchdog_short_circuit:
4515         schedule_work(&adapter->watchdog_task);
4516 }
4517
4518 /**
4519  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4520  * @work: pointer to work_struct containing our data
4521  **/
4522 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4523 {
4524         struct ixgbe_adapter *adapter = container_of(work,
4525                                                      struct ixgbe_adapter,
4526                                                      multispeed_fiber_task);
4527         struct ixgbe_hw *hw = &adapter->hw;
4528         u32 autoneg;
4529
4530         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4531         autoneg = hw->phy.autoneg_advertised;
4532         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4533                 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4534                                                   &hw->mac.autoneg);
4535         if (hw->mac.ops.setup_link_speed)
4536                 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4537         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4538         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4539 }
4540
4541 /**
4542  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4543  * @work: pointer to work_struct containing our data
4544  **/
4545 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4546 {
4547         struct ixgbe_adapter *adapter = container_of(work,
4548                                                      struct ixgbe_adapter,
4549                                                      sfp_config_module_task);
4550         struct ixgbe_hw *hw = &adapter->hw;
4551         u32 err;
4552
4553         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4554
4555         /* Time for electrical oscillations to settle down */
4556         msleep(100);
4557         err = hw->phy.ops.identify_sfp(hw);
4558
4559         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4560                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4561                         "an unsupported SFP+ module type was detected.\n"
4562                         "Reload the driver after installing a supported "
4563                         "module.\n");
4564                 unregister_netdev(adapter->netdev);
4565                 return;
4566         }
4567         hw->mac.ops.setup_sfp(hw);
4568
4569         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4570                 /* This will also work for DA Twinax connections */
4571                 schedule_work(&adapter->multispeed_fiber_task);
4572         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4573 }
4574
4575 /**
4576  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4577  * @work: pointer to work_struct containing our data
4578  **/
4579 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4580 {
4581         struct ixgbe_adapter *adapter = container_of(work,
4582                                                      struct ixgbe_adapter,
4583                                                      fdir_reinit_task);
4584         struct ixgbe_hw *hw = &adapter->hw;
4585         int i;
4586
4587         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4588                 for (i = 0; i < adapter->num_tx_queues; i++)
4589                         set_bit(__IXGBE_FDIR_INIT_DONE,
4590                                 &(adapter->tx_ring[i].reinit_state));
4591         } else {
4592                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4593                         "ignored adding FDIR ATR filters \n");
4594         }
4595         /* Done FDIR Re-initialization, enable transmits */
4596         netif_tx_start_all_queues(adapter->netdev);
4597 }
4598
4599 /**
4600  * ixgbe_watchdog_task - worker thread to bring link up
4601  * @work: pointer to work_struct containing our data
4602  **/
4603 static void ixgbe_watchdog_task(struct work_struct *work)
4604 {
4605         struct ixgbe_adapter *adapter = container_of(work,
4606                                                      struct ixgbe_adapter,
4607                                                      watchdog_task);
4608         struct net_device *netdev = adapter->netdev;
4609         struct ixgbe_hw *hw = &adapter->hw;
4610         u32 link_speed = adapter->link_speed;
4611         bool link_up = adapter->link_up;
4612         int i;
4613         struct ixgbe_ring *tx_ring;
4614         int some_tx_pending = 0;
4615
4616         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4617
4618         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4619                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4620                 if (link_up) {
4621 #ifdef CONFIG_DCB
4622                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4623                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4624                                         hw->mac.ops.fc_enable(hw, i);
4625                         } else {
4626                                 hw->mac.ops.fc_enable(hw, 0);
4627                         }
4628 #else
4629                         hw->mac.ops.fc_enable(hw, 0);
4630 #endif
4631                 }
4632
4633                 if (link_up ||
4634                     time_after(jiffies, (adapter->link_check_timeout +
4635                                          IXGBE_TRY_LINK_TIMEOUT))) {
4636                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4637                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4638                 }
4639                 adapter->link_up = link_up;
4640                 adapter->link_speed = link_speed;
4641         }
4642
4643         if (link_up) {
4644                 if (!netif_carrier_ok(netdev)) {
4645                         bool flow_rx, flow_tx;
4646
4647                         if (hw->mac.type == ixgbe_mac_82599EB) {
4648                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4649                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4650                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4651                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4652                         } else {
4653                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4654                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4655                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4656                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4657                         }
4658
4659                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4660                                "Flow Control: %s\n",
4661                                netdev->name,
4662                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4663                                 "10 Gbps" :
4664                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4665                                  "1 Gbps" : "unknown speed")),
4666                                ((flow_rx && flow_tx) ? "RX/TX" :
4667                                 (flow_rx ? "RX" :
4668                                 (flow_tx ? "TX" : "None"))));
4669
4670                         netif_carrier_on(netdev);
4671                 } else {
4672                         /* Force detection of hung controller */
4673                         adapter->detect_tx_hung = true;
4674                 }
4675         } else {
4676                 adapter->link_up = false;
4677                 adapter->link_speed = 0;
4678                 if (netif_carrier_ok(netdev)) {
4679                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4680                                netdev->name);
4681                         netif_carrier_off(netdev);
4682                 }
4683         }
4684
4685         if (!netif_carrier_ok(netdev)) {
4686                 for (i = 0; i < adapter->num_tx_queues; i++) {
4687                         tx_ring = &adapter->tx_ring[i];
4688                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4689                                 some_tx_pending = 1;
4690                                 break;
4691                         }
4692                 }
4693
4694                 if (some_tx_pending) {
4695                         /* We've lost link, so the controller stops DMA,
4696                          * but we've got queued Tx work that's never going
4697                          * to get done, so reset controller to flush Tx.
4698                          * (Do the reset outside of interrupt context).
4699                          */
4700                          schedule_work(&adapter->reset_task);
4701                 }
4702         }
4703
4704         ixgbe_update_stats(adapter);
4705         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4706 }
4707
4708 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4709                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4710                      u32 tx_flags, u8 *hdr_len)
4711 {
4712         struct ixgbe_adv_tx_context_desc *context_desc;
4713         unsigned int i;
4714         int err;
4715         struct ixgbe_tx_buffer *tx_buffer_info;
4716         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4717         u32 mss_l4len_idx, l4len;
4718
4719         if (skb_is_gso(skb)) {
4720                 if (skb_header_cloned(skb)) {
4721                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4722                         if (err)
4723                                 return err;
4724                 }
4725                 l4len = tcp_hdrlen(skb);
4726                 *hdr_len += l4len;
4727
4728                 if (skb->protocol == htons(ETH_P_IP)) {
4729                         struct iphdr *iph = ip_hdr(skb);
4730                         iph->tot_len = 0;
4731                         iph->check = 0;
4732                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4733                                                                  iph->daddr, 0,
4734                                                                  IPPROTO_TCP,
4735                                                                  0);
4736                         adapter->hw_tso_ctxt++;
4737                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4738                         ipv6_hdr(skb)->payload_len = 0;
4739                         tcp_hdr(skb)->check =
4740                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4741                                              &ipv6_hdr(skb)->daddr,
4742                                              0, IPPROTO_TCP, 0);
4743                         adapter->hw_tso6_ctxt++;
4744                 }
4745
4746                 i = tx_ring->next_to_use;
4747
4748                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4749                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4750
4751                 /* VLAN MACLEN IPLEN */
4752                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4753                         vlan_macip_lens |=
4754                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4755                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4756                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4757                 *hdr_len += skb_network_offset(skb);
4758                 vlan_macip_lens |=
4759                     (skb_transport_header(skb) - skb_network_header(skb));
4760                 *hdr_len +=
4761                     (skb_transport_header(skb) - skb_network_header(skb));
4762                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4763                 context_desc->seqnum_seed = 0;
4764
4765                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4766                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4767                                    IXGBE_ADVTXD_DTYP_CTXT);
4768
4769                 if (skb->protocol == htons(ETH_P_IP))
4770                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4771                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4772                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4773
4774                 /* MSS L4LEN IDX */
4775                 mss_l4len_idx =
4776                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4777                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4778                 /* use index 1 for TSO */
4779                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4780                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4781
4782                 tx_buffer_info->time_stamp = jiffies;
4783                 tx_buffer_info->next_to_watch = i;
4784
4785                 i++;
4786                 if (i == tx_ring->count)
4787                         i = 0;
4788                 tx_ring->next_to_use = i;
4789
4790                 return true;
4791         }
4792         return false;
4793 }
4794
4795 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4796                           struct ixgbe_ring *tx_ring,
4797                           struct sk_buff *skb, u32 tx_flags)
4798 {
4799         struct ixgbe_adv_tx_context_desc *context_desc;
4800         unsigned int i;
4801         struct ixgbe_tx_buffer *tx_buffer_info;
4802         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4803
4804         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4805             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4806                 i = tx_ring->next_to_use;
4807                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4808                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4809
4810                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4811                         vlan_macip_lens |=
4812                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4813                 vlan_macip_lens |= (skb_network_offset(skb) <<
4814                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4815                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4816                         vlan_macip_lens |= (skb_transport_header(skb) -
4817                                             skb_network_header(skb));
4818
4819                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4820                 context_desc->seqnum_seed = 0;
4821
4822                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4823                                     IXGBE_ADVTXD_DTYP_CTXT);
4824
4825                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4826                         switch (skb->protocol) {
4827                         case cpu_to_be16(ETH_P_IP):
4828                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4829                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4830                                         type_tucmd_mlhl |=
4831                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4832                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4833                                         type_tucmd_mlhl |=
4834                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4835                                 break;
4836                         case cpu_to_be16(ETH_P_IPV6):
4837                                 /* XXX what about other V6 headers?? */
4838                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4839                                         type_tucmd_mlhl |=
4840                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4841                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4842                                         type_tucmd_mlhl |=
4843                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4844                                 break;
4845                         default:
4846                                 if (unlikely(net_ratelimit())) {
4847                                         DPRINTK(PROBE, WARNING,
4848                                          "partial checksum but proto=%x!\n",
4849                                          skb->protocol);
4850                                 }
4851                                 break;
4852                         }
4853                 }
4854
4855                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4856                 /* use index zero for tx checksum offload */
4857                 context_desc->mss_l4len_idx = 0;
4858
4859                 tx_buffer_info->time_stamp = jiffies;
4860                 tx_buffer_info->next_to_watch = i;
4861
4862                 adapter->hw_csum_tx_good++;
4863                 i++;
4864                 if (i == tx_ring->count)
4865                         i = 0;
4866                 tx_ring->next_to_use = i;
4867
4868                 return true;
4869         }
4870
4871         return false;
4872 }
4873
4874 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4875                         struct ixgbe_ring *tx_ring,
4876                         struct sk_buff *skb, u32 tx_flags,
4877                         unsigned int first)
4878 {
4879         struct ixgbe_tx_buffer *tx_buffer_info;
4880         unsigned int len;
4881         unsigned int total = skb->len;
4882         unsigned int offset = 0, size, count = 0, i;
4883         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4884         unsigned int f;
4885         dma_addr_t *map;
4886
4887         i = tx_ring->next_to_use;
4888
4889         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4890                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4891                 return 0;
4892         }
4893
4894         map = skb_shinfo(skb)->dma_maps;
4895
4896         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4897                 /* excluding fcoe_crc_eof for FCoE */
4898                 total -= sizeof(struct fcoe_crc_eof);
4899
4900         len = min(skb_headlen(skb), total);
4901         while (len) {
4902                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4903                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4904
4905                 tx_buffer_info->length = size;
4906                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
4907                 tx_buffer_info->time_stamp = jiffies;
4908                 tx_buffer_info->next_to_watch = i;
4909
4910                 len -= size;
4911                 total -= size;
4912                 offset += size;
4913                 count++;
4914
4915                 if (len) {
4916                         i++;
4917                         if (i == tx_ring->count)
4918                                 i = 0;
4919                 }
4920         }
4921
4922         for (f = 0; f < nr_frags; f++) {
4923                 struct skb_frag_struct *frag;
4924
4925                 frag = &skb_shinfo(skb)->frags[f];
4926                 len = min((unsigned int)frag->size, total);
4927                 offset = 0;
4928
4929                 while (len) {
4930                         i++;
4931                         if (i == tx_ring->count)
4932                                 i = 0;
4933
4934                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4935                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4936
4937                         tx_buffer_info->length = size;
4938                         tx_buffer_info->dma = map[f] + offset;
4939                         tx_buffer_info->time_stamp = jiffies;
4940                         tx_buffer_info->next_to_watch = i;
4941
4942                         len -= size;
4943                         total -= size;
4944                         offset += size;
4945                         count++;
4946                 }
4947                 if (total == 0)
4948                         break;
4949         }
4950
4951         tx_ring->tx_buffer_info[i].skb = skb;
4952         tx_ring->tx_buffer_info[first].next_to_watch = i;
4953
4954         return count;
4955 }
4956
4957 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4958                            struct ixgbe_ring *tx_ring,
4959                            int tx_flags, int count, u32 paylen, u8 hdr_len)
4960 {
4961         union ixgbe_adv_tx_desc *tx_desc = NULL;
4962         struct ixgbe_tx_buffer *tx_buffer_info;
4963         u32 olinfo_status = 0, cmd_type_len = 0;
4964         unsigned int i;
4965         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4966
4967         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4968
4969         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4970
4971         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4972                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4973
4974         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4975                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4976
4977                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4978                                  IXGBE_ADVTXD_POPTS_SHIFT;
4979
4980                 /* use index 1 context for tso */
4981                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4982                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4983                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4984                                          IXGBE_ADVTXD_POPTS_SHIFT;
4985
4986         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4987                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4988                                  IXGBE_ADVTXD_POPTS_SHIFT;
4989
4990         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4991                 olinfo_status |= IXGBE_ADVTXD_CC;
4992                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4993                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4994                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4995         }
4996
4997         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4998
4999         i = tx_ring->next_to_use;
5000         while (count--) {
5001                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5002                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5003                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5004                 tx_desc->read.cmd_type_len =
5005                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5006                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5007                 i++;
5008                 if (i == tx_ring->count)
5009                         i = 0;
5010         }
5011
5012         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5013
5014         /*
5015          * Force memory writes to complete before letting h/w
5016          * know there are new descriptors to fetch.  (Only
5017          * applicable for weak-ordered memory model archs,
5018          * such as IA-64).
5019          */
5020         wmb();
5021
5022         tx_ring->next_to_use = i;
5023         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5024 }
5025
5026 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5027                       int queue, u32 tx_flags)
5028 {
5029         /* Right now, we support IPv4 only */
5030         struct ixgbe_atr_input atr_input;
5031         struct tcphdr *th;
5032         struct udphdr *uh;
5033         struct iphdr *iph = ip_hdr(skb);
5034         struct ethhdr *eth = (struct ethhdr *)skb->data;
5035         u16 vlan_id, src_port, dst_port, flex_bytes;
5036         u32 src_ipv4_addr, dst_ipv4_addr;
5037         u8 l4type = 0;
5038
5039         /* check if we're UDP or TCP */
5040         if (iph->protocol == IPPROTO_TCP) {
5041                 th = tcp_hdr(skb);
5042                 src_port = th->source;
5043                 dst_port = th->dest;
5044                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5045                 /* l4type IPv4 type is 0, no need to assign */
5046         } else if(iph->protocol == IPPROTO_UDP) {
5047                 uh = udp_hdr(skb);
5048                 src_port = uh->source;
5049                 dst_port = uh->dest;
5050                 l4type |= IXGBE_ATR_L4TYPE_UDP;
5051                 /* l4type IPv4 type is 0, no need to assign */
5052         } else {
5053                 /* Unsupported L4 header, just bail here */
5054                 return;
5055         }
5056
5057         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5058
5059         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5060                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5061         src_ipv4_addr = iph->saddr;
5062         dst_ipv4_addr = iph->daddr;
5063         flex_bytes = eth->h_proto;
5064
5065         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5066         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5067         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5068         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5069         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5070         /* src and dst are inverted, think how the receiver sees them */
5071         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5072         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5073
5074         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5075         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5076 }
5077
5078 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5079                                  struct ixgbe_ring *tx_ring, int size)
5080 {
5081         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5082
5083         netif_stop_subqueue(netdev, tx_ring->queue_index);
5084         /* Herbert's original patch had:
5085          *  smp_mb__after_netif_stop_queue();
5086          * but since that doesn't exist yet, just open code it. */
5087         smp_mb();
5088
5089         /* We need to check again in a case another CPU has just
5090          * made room available. */
5091         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5092                 return -EBUSY;
5093
5094         /* A reprieve! - use start_queue because it doesn't call schedule */
5095         netif_start_subqueue(netdev, tx_ring->queue_index);
5096         ++adapter->restart_queue;
5097         return 0;
5098 }
5099
5100 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5101                               struct ixgbe_ring *tx_ring, int size)
5102 {
5103         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5104                 return 0;
5105         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5106 }
5107
5108 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5109 {
5110         struct ixgbe_adapter *adapter = netdev_priv(dev);
5111
5112         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5113                 return smp_processor_id();
5114
5115         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5116                 return 0;  /* All traffic should default to class 0 */
5117
5118         return skb_tx_hash(dev, skb);
5119 }
5120
5121 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
5122 {
5123         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5124         struct ixgbe_ring *tx_ring;
5125         unsigned int first;
5126         unsigned int tx_flags = 0;
5127         u8 hdr_len = 0;
5128         int r_idx = 0, tso;
5129         int count = 0;
5130         unsigned int f;
5131
5132         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5133                 tx_flags |= vlan_tx_tag_get(skb);
5134                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5135                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5136                         tx_flags |= (skb->queue_mapping << 13);
5137                 }
5138                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5139                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5140         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5141                 if (skb->priority != TC_PRIO_CONTROL) {
5142                         tx_flags |= (skb->queue_mapping << 13);
5143                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5144                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5145                 } else {
5146                         skb->queue_mapping =
5147                                 adapter->ring_feature[RING_F_DCB].indices-1;
5148                 }
5149         }
5150
5151         r_idx = skb->queue_mapping;
5152         tx_ring = &adapter->tx_ring[r_idx];
5153
5154         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5155             (skb->protocol == htons(ETH_P_FCOE)))
5156                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5157
5158         /* four things can cause us to need a context descriptor */
5159         if (skb_is_gso(skb) ||
5160             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5161             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5162             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5163                 count++;
5164
5165         count += TXD_USE_COUNT(skb_headlen(skb));
5166         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5167                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5168
5169         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5170                 adapter->tx_busy++;
5171                 return NETDEV_TX_BUSY;
5172         }
5173
5174         first = tx_ring->next_to_use;
5175         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5176 #ifdef IXGBE_FCOE
5177                 /* setup tx offload for FCoE */
5178                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5179                 if (tso < 0) {
5180                         dev_kfree_skb_any(skb);
5181                         return NETDEV_TX_OK;
5182                 }
5183                 if (tso)
5184                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5185 #endif /* IXGBE_FCOE */
5186         } else {
5187                 if (skb->protocol == htons(ETH_P_IP))
5188                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5189                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5190                 if (tso < 0) {
5191                         dev_kfree_skb_any(skb);
5192                         return NETDEV_TX_OK;
5193                 }
5194
5195                 if (tso)
5196                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5197                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5198                          (skb->ip_summed == CHECKSUM_PARTIAL))
5199                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5200         }
5201
5202         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5203         if (count) {
5204                 /* add the ATR filter if ATR is on */
5205                 if (tx_ring->atr_sample_rate) {
5206                         ++tx_ring->atr_count;
5207                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5208                              test_bit(__IXGBE_FDIR_INIT_DONE,
5209                                       &tx_ring->reinit_state)) {
5210                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5211                                           tx_flags);
5212                                 tx_ring->atr_count = 0;
5213                         }
5214                 }
5215                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5216                                hdr_len);
5217                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5218
5219         } else {
5220                 dev_kfree_skb_any(skb);
5221                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5222                 tx_ring->next_to_use = first;
5223         }
5224
5225         return NETDEV_TX_OK;
5226 }
5227
5228 /**
5229  * ixgbe_get_stats - Get System Network Statistics
5230  * @netdev: network interface device structure
5231  *
5232  * Returns the address of the device statistics structure.
5233  * The statistics are actually updated from the timer callback.
5234  **/
5235 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5236 {
5237         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5238
5239         /* only return the current stats */
5240         return &adapter->net_stats;
5241 }
5242
5243 /**
5244  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5245  * @netdev: network interface device structure
5246  * @p: pointer to an address structure
5247  *
5248  * Returns 0 on success, negative on failure
5249  **/
5250 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5251 {
5252         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5253         struct ixgbe_hw *hw = &adapter->hw;
5254         struct sockaddr *addr = p;
5255
5256         if (!is_valid_ether_addr(addr->sa_data))
5257                 return -EADDRNOTAVAIL;
5258
5259         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5260         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5261
5262         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5263
5264         return 0;
5265 }
5266
5267 static int
5268 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5269 {
5270         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5271         struct ixgbe_hw *hw = &adapter->hw;
5272         u16 value;
5273         int rc;
5274
5275         if (prtad != hw->phy.mdio.prtad)
5276                 return -EINVAL;
5277         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5278         if (!rc)
5279                 rc = value;
5280         return rc;
5281 }
5282
5283 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5284                             u16 addr, u16 value)
5285 {
5286         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5287         struct ixgbe_hw *hw = &adapter->hw;
5288
5289         if (prtad != hw->phy.mdio.prtad)
5290                 return -EINVAL;
5291         return hw->phy.ops.write_reg(hw, addr, devad, value);
5292 }
5293
5294 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5295 {
5296         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5297
5298         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5299 }
5300
5301 /**
5302  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5303  * netdev->dev_addrs
5304  * @netdev: network interface device structure
5305  *
5306  * Returns non-zero on failure
5307  **/
5308 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5309 {
5310         int err = 0;
5311         struct ixgbe_adapter *adapter = netdev_priv(dev);
5312         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5313
5314         if (is_valid_ether_addr(mac->san_addr)) {
5315                 rtnl_lock();
5316                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5317                 rtnl_unlock();
5318         }
5319         return err;
5320 }
5321
5322 /**
5323  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5324  * netdev->dev_addrs
5325  * @netdev: network interface device structure
5326  *
5327  * Returns non-zero on failure
5328  **/
5329 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5330 {
5331         int err = 0;
5332         struct ixgbe_adapter *adapter = netdev_priv(dev);
5333         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5334
5335         if (is_valid_ether_addr(mac->san_addr)) {
5336                 rtnl_lock();
5337                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5338                 rtnl_unlock();
5339         }
5340         return err;
5341 }
5342
5343 #ifdef CONFIG_NET_POLL_CONTROLLER
5344 /*
5345  * Polling 'interrupt' - used by things like netconsole to send skbs
5346  * without having to re-enable interrupts. It's not called while
5347  * the interrupt routine is executing.
5348  */
5349 static void ixgbe_netpoll(struct net_device *netdev)
5350 {
5351         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5352
5353         disable_irq(adapter->pdev->irq);
5354         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5355         ixgbe_intr(adapter->pdev->irq, netdev);
5356         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5357         enable_irq(adapter->pdev->irq);
5358 }
5359 #endif
5360
5361 static const struct net_device_ops ixgbe_netdev_ops = {
5362         .ndo_open               = ixgbe_open,
5363         .ndo_stop               = ixgbe_close,
5364         .ndo_start_xmit         = ixgbe_xmit_frame,
5365         .ndo_select_queue       = ixgbe_select_queue,
5366         .ndo_get_stats          = ixgbe_get_stats,
5367         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5368         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5369         .ndo_validate_addr      = eth_validate_addr,
5370         .ndo_set_mac_address    = ixgbe_set_mac,
5371         .ndo_change_mtu         = ixgbe_change_mtu,
5372         .ndo_tx_timeout         = ixgbe_tx_timeout,
5373         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5374         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5375         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5376         .ndo_do_ioctl           = ixgbe_ioctl,
5377 #ifdef CONFIG_NET_POLL_CONTROLLER
5378         .ndo_poll_controller    = ixgbe_netpoll,
5379 #endif
5380 #ifdef IXGBE_FCOE
5381         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5382         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5383 #endif /* IXGBE_FCOE */
5384 };
5385
5386 /**
5387  * ixgbe_probe - Device Initialization Routine
5388  * @pdev: PCI device information struct
5389  * @ent: entry in ixgbe_pci_tbl
5390  *
5391  * Returns 0 on success, negative on failure
5392  *
5393  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5394  * The OS initialization, configuring of the adapter private structure,
5395  * and a hardware reset occur.
5396  **/
5397 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5398                                  const struct pci_device_id *ent)
5399 {
5400         struct net_device *netdev;
5401         struct ixgbe_adapter *adapter = NULL;
5402         struct ixgbe_hw *hw;
5403         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5404         static int cards_found;
5405         int i, err, pci_using_dac;
5406 #ifdef IXGBE_FCOE
5407         u16 device_caps;
5408 #endif
5409         u32 part_num, eec;
5410
5411         err = pci_enable_device_mem(pdev);
5412         if (err)
5413                 return err;
5414
5415         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5416             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5417                 pci_using_dac = 1;
5418         } else {
5419                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5420                 if (err) {
5421                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5422                         if (err) {
5423                                 dev_err(&pdev->dev, "No usable DMA "
5424                                         "configuration, aborting\n");
5425                                 goto err_dma;
5426                         }
5427                 }
5428                 pci_using_dac = 0;
5429         }
5430
5431         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5432                                            IORESOURCE_MEM), ixgbe_driver_name);
5433         if (err) {
5434                 dev_err(&pdev->dev,
5435                         "pci_request_selected_regions failed 0x%x\n", err);
5436                 goto err_pci_reg;
5437         }
5438
5439         err = pci_enable_pcie_error_reporting(pdev);
5440         if (err) {
5441                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5442                                     "0x%x\n", err);
5443                 /* non-fatal, continue */
5444         }
5445
5446         pci_set_master(pdev);
5447         pci_save_state(pdev);
5448
5449         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5450         if (!netdev) {
5451                 err = -ENOMEM;
5452                 goto err_alloc_etherdev;
5453         }
5454
5455         SET_NETDEV_DEV(netdev, &pdev->dev);
5456
5457         pci_set_drvdata(pdev, netdev);
5458         adapter = netdev_priv(netdev);
5459
5460         adapter->netdev = netdev;
5461         adapter->pdev = pdev;
5462         hw = &adapter->hw;
5463         hw->back = adapter;
5464         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5465
5466         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5467                               pci_resource_len(pdev, 0));
5468         if (!hw->hw_addr) {
5469                 err = -EIO;
5470                 goto err_ioremap;
5471         }
5472
5473         for (i = 1; i <= 5; i++) {
5474                 if (pci_resource_len(pdev, i) == 0)
5475                         continue;
5476         }
5477
5478         netdev->netdev_ops = &ixgbe_netdev_ops;
5479         ixgbe_set_ethtool_ops(netdev);
5480         netdev->watchdog_timeo = 5 * HZ;
5481         strcpy(netdev->name, pci_name(pdev));
5482
5483         adapter->bd_number = cards_found;
5484
5485         /* Setup hw api */
5486         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5487         hw->mac.type  = ii->mac;
5488
5489         /* EEPROM */
5490         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5491         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5492         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5493         if (!(eec & (1 << 8)))
5494                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5495
5496         /* PHY */
5497         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5498         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5499         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5500         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5501         hw->phy.mdio.mmds = 0;
5502         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5503         hw->phy.mdio.dev = netdev;
5504         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5505         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5506
5507         /* set up this timer and work struct before calling get_invariants
5508          * which might start the timer
5509          */
5510         init_timer(&adapter->sfp_timer);
5511         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5512         adapter->sfp_timer.data = (unsigned long) adapter;
5513
5514         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5515
5516         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5517         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5518
5519         /* a new SFP+ module arrival, called from GPI SDP2 context */
5520         INIT_WORK(&adapter->sfp_config_module_task,
5521                   ixgbe_sfp_config_module_task);
5522
5523         ii->get_invariants(hw);
5524
5525         /* setup the private structure */
5526         err = ixgbe_sw_init(adapter);
5527         if (err)
5528                 goto err_sw_init;
5529
5530         /*
5531          * If there is a fan on this device and it has failed log the
5532          * failure.
5533          */
5534         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5535                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5536                 if (esdp & IXGBE_ESDP_SDP1)
5537                         DPRINTK(PROBE, CRIT,
5538                                 "Fan has stopped, replace the adapter\n");
5539         }
5540
5541         /* reset_hw fills in the perm_addr as well */
5542         err = hw->mac.ops.reset_hw(hw);
5543         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5544             hw->mac.type == ixgbe_mac_82598EB) {
5545                 /*
5546                  * Start a kernel thread to watch for a module to arrive.
5547                  * Only do this for 82598, since 82599 will generate
5548                  * interrupts on module arrival.
5549                  */
5550                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5551                 mod_timer(&adapter->sfp_timer,
5552                           round_jiffies(jiffies + (2 * HZ)));
5553                 err = 0;
5554         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5555                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5556                         "an unsupported SFP+ module type was detected.\n"
5557                         "Reload the driver after installing a supported "
5558                         "module.\n");
5559                 goto err_sw_init;
5560         } else if (err) {
5561                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5562                 goto err_sw_init;
5563         }
5564
5565         netdev->features = NETIF_F_SG |
5566                            NETIF_F_IP_CSUM |
5567                            NETIF_F_HW_VLAN_TX |
5568                            NETIF_F_HW_VLAN_RX |
5569                            NETIF_F_HW_VLAN_FILTER;
5570
5571         netdev->features |= NETIF_F_IPV6_CSUM;
5572         netdev->features |= NETIF_F_TSO;
5573         netdev->features |= NETIF_F_TSO6;
5574         netdev->features |= NETIF_F_GRO;
5575
5576         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5577                 netdev->features |= NETIF_F_SCTP_CSUM;
5578
5579         netdev->vlan_features |= NETIF_F_TSO;
5580         netdev->vlan_features |= NETIF_F_TSO6;
5581         netdev->vlan_features |= NETIF_F_IP_CSUM;
5582         netdev->vlan_features |= NETIF_F_SG;
5583
5584         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5585                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5586
5587 #ifdef CONFIG_IXGBE_DCB
5588         netdev->dcbnl_ops = &dcbnl_ops;
5589 #endif
5590
5591 #ifdef IXGBE_FCOE
5592         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5593                 if (hw->mac.ops.get_device_caps) {
5594                         hw->mac.ops.get_device_caps(hw, &device_caps);
5595                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5596                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5597                 }
5598         }
5599 #endif /* IXGBE_FCOE */
5600         if (pci_using_dac)
5601                 netdev->features |= NETIF_F_HIGHDMA;
5602
5603         if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED)
5604                 netdev->features |= NETIF_F_LRO;
5605
5606         /* make sure the EEPROM is good */
5607         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5608                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5609                 err = -EIO;
5610                 goto err_eeprom;
5611         }
5612
5613         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5614         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5615
5616         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5617                 dev_err(&pdev->dev, "invalid MAC address\n");
5618                 err = -EIO;
5619                 goto err_eeprom;
5620         }
5621
5622         init_timer(&adapter->watchdog_timer);
5623         adapter->watchdog_timer.function = &ixgbe_watchdog;
5624         adapter->watchdog_timer.data = (unsigned long)adapter;
5625
5626         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5627         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5628
5629         err = ixgbe_init_interrupt_scheme(adapter);
5630         if (err)
5631                 goto err_sw_init;
5632
5633         switch (pdev->device) {
5634         case IXGBE_DEV_ID_82599_KX4:
5635                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5636                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5637                 /* Enable ACPI wakeup in GRC */
5638                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5639                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5640                 break;
5641         default:
5642                 adapter->wol = 0;
5643                 break;
5644         }
5645         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5646
5647         /* pick up the PCI bus settings for reporting later */
5648         hw->mac.ops.get_bus_info(hw);
5649
5650         /* print bus type/speed/width info */
5651         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5652                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5653                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5654                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5655                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5656                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5657                  "Unknown"),
5658                 netdev->dev_addr);
5659         ixgbe_read_pba_num_generic(hw, &part_num);
5660         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5661                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5662                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5663                          (part_num >> 8), (part_num & 0xff));
5664         else
5665                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5666                          hw->mac.type, hw->phy.type,
5667                          (part_num >> 8), (part_num & 0xff));
5668
5669         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5670                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5671                          "this card is not sufficient for optimal "
5672                          "performance.\n");
5673                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5674                          "PCI-Express slot is required.\n");
5675         }
5676
5677         /* save off EEPROM version number */
5678         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5679
5680         /* reset the hardware with the new settings */
5681         err = hw->mac.ops.start_hw(hw);
5682
5683         if (err == IXGBE_ERR_EEPROM_VERSION) {
5684                 /* We are running on a pre-production device, log a warning */
5685                 dev_warn(&pdev->dev, "This device is a pre-production "
5686                          "adapter/LOM.  Please be aware there may be issues "
5687                          "associated with your hardware.  If you are "
5688                          "experiencing problems please contact your Intel or "
5689                          "hardware representative who provided you with this "
5690                          "hardware.\n");
5691         }
5692         strcpy(netdev->name, "eth%d");
5693         err = register_netdev(netdev);
5694         if (err)
5695                 goto err_register;
5696
5697         /* carrier off reporting is important to ethtool even BEFORE open */
5698         netif_carrier_off(netdev);
5699
5700         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5701             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5702                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5703
5704 #ifdef CONFIG_IXGBE_DCA
5705         if (dca_add_requester(&pdev->dev) == 0) {
5706                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5707                 ixgbe_setup_dca(adapter);
5708         }
5709 #endif
5710         /* add san mac addr to netdev */
5711         ixgbe_add_sanmac_netdev(netdev);
5712
5713         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5714         cards_found++;
5715         return 0;
5716
5717 err_register:
5718         ixgbe_release_hw_control(adapter);
5719         ixgbe_clear_interrupt_scheme(adapter);
5720 err_sw_init:
5721 err_eeprom:
5722         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5723         del_timer_sync(&adapter->sfp_timer);
5724         cancel_work_sync(&adapter->sfp_task);
5725         cancel_work_sync(&adapter->multispeed_fiber_task);
5726         cancel_work_sync(&adapter->sfp_config_module_task);
5727         iounmap(hw->hw_addr);
5728 err_ioremap:
5729         free_netdev(netdev);
5730 err_alloc_etherdev:
5731         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5732                                      IORESOURCE_MEM));
5733 err_pci_reg:
5734 err_dma:
5735         pci_disable_device(pdev);
5736         return err;
5737 }
5738
5739 /**
5740  * ixgbe_remove - Device Removal Routine
5741  * @pdev: PCI device information struct
5742  *
5743  * ixgbe_remove is called by the PCI subsystem to alert the driver
5744  * that it should release a PCI device.  The could be caused by a
5745  * Hot-Plug event, or because the driver is going to be removed from
5746  * memory.
5747  **/
5748 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5749 {
5750         struct net_device *netdev = pci_get_drvdata(pdev);
5751         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5752         int err;
5753
5754         set_bit(__IXGBE_DOWN, &adapter->state);
5755         /* clear the module not found bit to make sure the worker won't
5756          * reschedule
5757          */
5758         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5759         del_timer_sync(&adapter->watchdog_timer);
5760
5761         del_timer_sync(&adapter->sfp_timer);
5762         cancel_work_sync(&adapter->watchdog_task);
5763         cancel_work_sync(&adapter->sfp_task);
5764         cancel_work_sync(&adapter->multispeed_fiber_task);
5765         cancel_work_sync(&adapter->sfp_config_module_task);
5766         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5767             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5768                 cancel_work_sync(&adapter->fdir_reinit_task);
5769         flush_scheduled_work();
5770
5771 #ifdef CONFIG_IXGBE_DCA
5772         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5773                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5774                 dca_remove_requester(&pdev->dev);
5775                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5776         }
5777
5778 #endif
5779 #ifdef IXGBE_FCOE
5780         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5781                 ixgbe_cleanup_fcoe(adapter);
5782
5783 #endif /* IXGBE_FCOE */
5784
5785         /* remove the added san mac */
5786         ixgbe_del_sanmac_netdev(netdev);
5787
5788         if (netdev->reg_state == NETREG_REGISTERED)
5789                 unregister_netdev(netdev);
5790
5791         ixgbe_clear_interrupt_scheme(adapter);
5792
5793         ixgbe_release_hw_control(adapter);
5794
5795         iounmap(adapter->hw.hw_addr);
5796         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5797                                      IORESOURCE_MEM));
5798
5799         DPRINTK(PROBE, INFO, "complete\n");
5800
5801         free_netdev(netdev);
5802
5803         err = pci_disable_pcie_error_reporting(pdev);
5804         if (err)
5805                 dev_err(&pdev->dev,
5806                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5807
5808         pci_disable_device(pdev);
5809 }
5810
5811 /**
5812  * ixgbe_io_error_detected - called when PCI error is detected
5813  * @pdev: Pointer to PCI device
5814  * @state: The current pci connection state
5815  *
5816  * This function is called after a PCI bus error affecting
5817  * this device has been detected.
5818  */
5819 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5820                                                 pci_channel_state_t state)
5821 {
5822         struct net_device *netdev = pci_get_drvdata(pdev);
5823         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5824
5825         netif_device_detach(netdev);
5826
5827         if (state == pci_channel_io_perm_failure)
5828                 return PCI_ERS_RESULT_DISCONNECT;
5829
5830         if (netif_running(netdev))
5831                 ixgbe_down(adapter);
5832         pci_disable_device(pdev);
5833
5834         /* Request a slot reset. */
5835         return PCI_ERS_RESULT_NEED_RESET;
5836 }
5837
5838 /**
5839  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5840  * @pdev: Pointer to PCI device
5841  *
5842  * Restart the card from scratch, as if from a cold-boot.
5843  */
5844 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5845 {
5846         struct net_device *netdev = pci_get_drvdata(pdev);
5847         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5848         pci_ers_result_t result;
5849         int err;
5850
5851         if (pci_enable_device_mem(pdev)) {
5852                 DPRINTK(PROBE, ERR,
5853                         "Cannot re-enable PCI device after reset.\n");
5854                 result = PCI_ERS_RESULT_DISCONNECT;
5855         } else {
5856                 pci_set_master(pdev);
5857                 pci_restore_state(pdev);
5858
5859                 pci_wake_from_d3(pdev, false);
5860
5861                 ixgbe_reset(adapter);
5862                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5863                 result = PCI_ERS_RESULT_RECOVERED;
5864         }
5865
5866         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5867         if (err) {
5868                 dev_err(&pdev->dev,
5869                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5870                 /* non-fatal, continue */
5871         }
5872
5873         return result;
5874 }
5875
5876 /**
5877  * ixgbe_io_resume - called when traffic can start flowing again.
5878  * @pdev: Pointer to PCI device
5879  *
5880  * This callback is called when the error recovery driver tells us that
5881  * its OK to resume normal operation.
5882  */
5883 static void ixgbe_io_resume(struct pci_dev *pdev)
5884 {
5885         struct net_device *netdev = pci_get_drvdata(pdev);
5886         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5887
5888         if (netif_running(netdev)) {
5889                 if (ixgbe_up(adapter)) {
5890                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5891                         return;
5892                 }
5893         }
5894
5895         netif_device_attach(netdev);
5896 }
5897
5898 static struct pci_error_handlers ixgbe_err_handler = {
5899         .error_detected = ixgbe_io_error_detected,
5900         .slot_reset = ixgbe_io_slot_reset,
5901         .resume = ixgbe_io_resume,
5902 };
5903
5904 static struct pci_driver ixgbe_driver = {
5905         .name     = ixgbe_driver_name,
5906         .id_table = ixgbe_pci_tbl,
5907         .probe    = ixgbe_probe,
5908         .remove   = __devexit_p(ixgbe_remove),
5909 #ifdef CONFIG_PM
5910         .suspend  = ixgbe_suspend,
5911         .resume   = ixgbe_resume,
5912 #endif
5913         .shutdown = ixgbe_shutdown,
5914         .err_handler = &ixgbe_err_handler
5915 };
5916
5917 /**
5918  * ixgbe_init_module - Driver Registration Routine
5919  *
5920  * ixgbe_init_module is the first routine called when the driver is
5921  * loaded. All it does is register with the PCI subsystem.
5922  **/
5923 static int __init ixgbe_init_module(void)
5924 {
5925         int ret;
5926         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5927                ixgbe_driver_string, ixgbe_driver_version);
5928
5929         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5930
5931 #ifdef CONFIG_IXGBE_DCA
5932         dca_register_notify(&dca_notifier);
5933 #endif
5934
5935         ret = pci_register_driver(&ixgbe_driver);
5936         return ret;
5937 }
5938
5939 module_init(ixgbe_init_module);
5940
5941 /**
5942  * ixgbe_exit_module - Driver Exit Cleanup Routine
5943  *
5944  * ixgbe_exit_module is called just before the driver is removed
5945  * from memory.
5946  **/
5947 static void __exit ixgbe_exit_module(void)
5948 {
5949 #ifdef CONFIG_IXGBE_DCA
5950         dca_unregister_notify(&dca_notifier);
5951 #endif
5952         pci_unregister_driver(&ixgbe_driver);
5953 }
5954
5955 #ifdef CONFIG_IXGBE_DCA
5956 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5957                             void *p)
5958 {
5959         int ret_val;
5960
5961         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5962                                          __ixgbe_notify_dca);
5963
5964         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5965 }
5966
5967 #endif /* CONFIG_IXGBE_DCA */
5968 #ifdef DEBUG
5969 /**
5970  * ixgbe_get_hw_dev_name - return device name string
5971  * used by hardware layer to print debugging information
5972  **/
5973 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5974 {
5975         struct ixgbe_adapter *adapter = hw->back;
5976         return adapter->netdev->name;
5977 }
5978
5979 #endif
5980 module_exit(ixgbe_exit_module);
5981
5982 /* ixgbe_main.c */