drivers/net/ethernet/sfc/falcon.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2013 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/i2c.h>
  17 #include <linux/mii.h>
  18 #include <linux/slab.h>
  19 #include "net_driver.h"
  20 #include "bitfield.h"
  21 #include "efx.h"
  22 #include "nic.h"
  23 #include "farch_regs.h"
  24 #include "io.h"
  25 #include "phy.h"
  26 #include "workarounds.h"
  27 #include "selftest.h"
  28 #include "mdio_10g.h"
  29
  30 /* Hardware control for SFC4000 (aka Falcon). */
  31
  32 /**************************************************************************
  33  *
  34  * NIC stats
  35  *
  36  **************************************************************************
  37  */
  38
  39 #define FALCON_MAC_STATS_SIZE 0x100
  40
  41 #define XgRxOctets_offset 0x0
  42 #define XgRxOctets_WIDTH 48
  43 #define XgRxOctetsOK_offset 0x8
  44 #define XgRxOctetsOK_WIDTH 48
  45 #define XgRxPkts_offset 0x10
  46 #define XgRxPkts_WIDTH 32
  47 #define XgRxPktsOK_offset 0x14
  48 #define XgRxPktsOK_WIDTH 32
  49 #define XgRxBroadcastPkts_offset 0x18
  50 #define XgRxBroadcastPkts_WIDTH 32
  51 #define XgRxMulticastPkts_offset 0x1C
  52 #define XgRxMulticastPkts_WIDTH 32
  53 #define XgRxUnicastPkts_offset 0x20
  54 #define XgRxUnicastPkts_WIDTH 32
  55 #define XgRxUndersizePkts_offset 0x24
  56 #define XgRxUndersizePkts_WIDTH 32
  57 #define XgRxOversizePkts_offset 0x28
  58 #define XgRxOversizePkts_WIDTH 32
  59 #define XgRxJabberPkts_offset 0x2C
  60 #define XgRxJabberPkts_WIDTH 32
  61 #define XgRxUndersizeFCSerrorPkts_offset 0x30
  62 #define XgRxUndersizeFCSerrorPkts_WIDTH 32
  63 #define XgRxDropEvents_offset 0x34
  64 #define XgRxDropEvents_WIDTH 32
  65 #define XgRxFCSerrorPkts_offset 0x38
  66 #define XgRxFCSerrorPkts_WIDTH 32
  67 #define XgRxAlignError_offset 0x3C
  68 #define XgRxAlignError_WIDTH 32
  69 #define XgRxSymbolError_offset 0x40
  70 #define XgRxSymbolError_WIDTH 32
  71 #define XgRxInternalMACError_offset 0x44
  72 #define XgRxInternalMACError_WIDTH 32
  73 #define XgRxControlPkts_offset 0x48
  74 #define XgRxControlPkts_WIDTH 32
  75 #define XgRxPausePkts_offset 0x4C
  76 #define XgRxPausePkts_WIDTH 32
  77 #define XgRxPkts64Octets_offset 0x50
  78 #define XgRxPkts64Octets_WIDTH 32
  79 #define XgRxPkts65to127Octets_offset 0x54
  80 #define XgRxPkts65to127Octets_WIDTH 32
  81 #define XgRxPkts128to255Octets_offset 0x58
  82 #define XgRxPkts128to255Octets_WIDTH 32
  83 #define XgRxPkts256to511Octets_offset 0x5C
  84 #define XgRxPkts256to511Octets_WIDTH 32
  85 #define XgRxPkts512to1023Octets_offset 0x60
  86 #define XgRxPkts512to1023Octets_WIDTH 32
  87 #define XgRxPkts1024to15xxOctets_offset 0x64
  88 #define XgRxPkts1024to15xxOctets_WIDTH 32
  89 #define XgRxPkts15xxtoMaxOctets_offset 0x68
  90 #define XgRxPkts15xxtoMaxOctets_WIDTH 32
  91 #define XgRxLengthError_offset 0x6C
  92 #define XgRxLengthError_WIDTH 32
  93 #define XgTxPkts_offset 0x80
  94 #define XgTxPkts_WIDTH 32
  95 #define XgTxOctets_offset 0x88
  96 #define XgTxOctets_WIDTH 48
  97 #define XgTxMulticastPkts_offset 0x90
  98 #define XgTxMulticastPkts_WIDTH 32
  99 #define XgTxBroadcastPkts_offset 0x94
 100 #define XgTxBroadcastPkts_WIDTH 32
 101 #define XgTxUnicastPkts_offset 0x98
 102 #define XgTxUnicastPkts_WIDTH 32
 103 #define XgTxControlPkts_offset 0x9C
 104 #define XgTxControlPkts_WIDTH 32
 105 #define XgTxPausePkts_offset 0xA0
 106 #define XgTxPausePkts_WIDTH 32
 107 #define XgTxPkts64Octets_offset 0xA4
 108 #define XgTxPkts64Octets_WIDTH 32
 109 #define XgTxPkts65to127Octets_offset 0xA8
 110 #define XgTxPkts65to127Octets_WIDTH 32
 111 #define XgTxPkts128to255Octets_offset 0xAC
 112 #define XgTxPkts128to255Octets_WIDTH 32
 113 #define XgTxPkts256to511Octets_offset 0xB0
 114 #define XgTxPkts256to511Octets_WIDTH 32
 115 #define XgTxPkts512to1023Octets_offset 0xB4
 116 #define XgTxPkts512to1023Octets_WIDTH 32
 117 #define XgTxPkts1024to15xxOctets_offset 0xB8
 118 #define XgTxPkts1024to15xxOctets_WIDTH 32
 119 #define XgTxPkts1519toMaxOctets_offset 0xBC
 120 #define XgTxPkts1519toMaxOctets_WIDTH 32
 121 #define XgTxUndersizePkts_offset 0xC0
 122 #define XgTxUndersizePkts_WIDTH 32
 123 #define XgTxOversizePkts_offset 0xC4
 124 #define XgTxOversizePkts_WIDTH 32
 125 #define XgTxNonTcpUdpPkt_offset 0xC8
 126 #define XgTxNonTcpUdpPkt_WIDTH 16
 127 #define XgTxMacSrcErrPkt_offset 0xCC
 128 #define XgTxMacSrcErrPkt_WIDTH 16
 129 #define XgTxIpSrcErrPkt_offset 0xD0
 130 #define XgTxIpSrcErrPkt_WIDTH 16
 131 #define XgDmaDone_offset 0xD4
 132 #define XgDmaDone_WIDTH 32
 133
 134 #define FALCON_XMAC_STATS_DMA_FLAG(efx)                         \
 135         (*(u32 *)((efx)->stats_buffer.addr + XgDmaDone_offset))
 136
 137 #define FALCON_DMA_STAT(ext_name, hw_name)                              \
 138         [FALCON_STAT_ ## ext_name] =                                    \
 139         { #ext_name,                                                    \
 140           /* 48-bit stats are zero-padded to 64 on DMA */               \
 141           hw_name ## _ ## WIDTH == 48 ? 64 : hw_name ## _ ## WIDTH,     \
 142           hw_name ## _ ## offset }
 143 #define FALCON_OTHER_STAT(ext_name)                                     \
 144         [FALCON_STAT_ ## ext_name] = { #ext_name, 0, 0 }
 145
 146 static const struct efx_hw_stat_desc falcon_stat_desc[FALCON_STAT_COUNT] = {
 147         FALCON_DMA_STAT(tx_bytes, XgTxOctets),
 148         FALCON_DMA_STAT(tx_packets, XgTxPkts),
 149         FALCON_DMA_STAT(tx_pause, XgTxPausePkts),
 150         FALCON_DMA_STAT(tx_control, XgTxControlPkts),
 151         FALCON_DMA_STAT(tx_unicast, XgTxUnicastPkts),
 152         FALCON_DMA_STAT(tx_multicast, XgTxMulticastPkts),
 153         FALCON_DMA_STAT(tx_broadcast, XgTxBroadcastPkts),
 154         FALCON_DMA_STAT(tx_lt64, XgTxUndersizePkts),
 155         FALCON_DMA_STAT(tx_64, XgTxPkts64Octets),
 156         FALCON_DMA_STAT(tx_65_to_127, XgTxPkts65to127Octets),
 157         FALCON_DMA_STAT(tx_128_to_255, XgTxPkts128to255Octets),
 158         FALCON_DMA_STAT(tx_256_to_511, XgTxPkts256to511Octets),
 159         FALCON_DMA_STAT(tx_512_to_1023, XgTxPkts512to1023Octets),
 160         FALCON_DMA_STAT(tx_1024_to_15xx, XgTxPkts1024to15xxOctets),
 161         FALCON_DMA_STAT(tx_15xx_to_jumbo, XgTxPkts1519toMaxOctets),
 162         FALCON_DMA_STAT(tx_gtjumbo, XgTxOversizePkts),
 163         FALCON_DMA_STAT(tx_non_tcpudp, XgTxNonTcpUdpPkt),
 164         FALCON_DMA_STAT(tx_mac_src_error, XgTxMacSrcErrPkt),
 165         FALCON_DMA_STAT(tx_ip_src_error, XgTxIpSrcErrPkt),
 166         FALCON_DMA_STAT(rx_bytes, XgRxOctets),
 167         FALCON_DMA_STAT(rx_good_bytes, XgRxOctetsOK),
 168         FALCON_OTHER_STAT(rx_bad_bytes),
 169         FALCON_DMA_STAT(rx_packets, XgRxPkts),
 170         FALCON_DMA_STAT(rx_good, XgRxPktsOK),
 171         FALCON_DMA_STAT(rx_bad, XgRxFCSerrorPkts),
 172         FALCON_DMA_STAT(rx_pause, XgRxPausePkts),
 173         FALCON_DMA_STAT(rx_control, XgRxControlPkts),
 174         FALCON_DMA_STAT(rx_unicast, XgRxUnicastPkts),
 175         FALCON_DMA_STAT(rx_multicast, XgRxMulticastPkts),
 176         FALCON_DMA_STAT(rx_broadcast, XgRxBroadcastPkts),
 177         FALCON_DMA_STAT(rx_lt64, XgRxUndersizePkts),
 178         FALCON_DMA_STAT(rx_64, XgRxPkts64Octets),
 179         FALCON_DMA_STAT(rx_65_to_127, XgRxPkts65to127Octets),
 180         FALCON_DMA_STAT(rx_128_to_255, XgRxPkts128to255Octets),
 181         FALCON_DMA_STAT(rx_256_to_511, XgRxPkts256to511Octets),
 182         FALCON_DMA_STAT(rx_512_to_1023, XgRxPkts512to1023Octets),
 183         FALCON_DMA_STAT(rx_1024_to_15xx, XgRxPkts1024to15xxOctets),
 184         FALCON_DMA_STAT(rx_15xx_to_jumbo, XgRxPkts15xxtoMaxOctets),
 185         FALCON_DMA_STAT(rx_gtjumbo, XgRxOversizePkts),
 186         FALCON_DMA_STAT(rx_bad_lt64, XgRxUndersizeFCSerrorPkts),
 187         FALCON_DMA_STAT(rx_bad_gtjumbo, XgRxJabberPkts),
 188         FALCON_DMA_STAT(rx_overflow, XgRxDropEvents),
 189         FALCON_DMA_STAT(rx_symbol_error, XgRxSymbolError),
 190         FALCON_DMA_STAT(rx_align_error, XgRxAlignError),
 191         FALCON_DMA_STAT(rx_length_error, XgRxLengthError),
 192         FALCON_DMA_STAT(rx_internal_error, XgRxInternalMACError),
 193         FALCON_OTHER_STAT(rx_nodesc_drop_cnt),
 194 };
 195 static const unsigned long falcon_stat_mask[] = {
 196         [0 ... BITS_TO_LONGS(FALCON_STAT_COUNT) - 1] = ~0UL,
 197 };
 198
 199 /**************************************************************************
 200  *
 201  * Basic SPI command set and bit definitions
 202  *
 203  *************************************************************************/
 204
 205 #define SPI_WRSR 0x01           /* Write status register */
 206 #define SPI_WRITE 0x02          /* Write data to memory array */
 207 #define SPI_READ 0x03           /* Read data from memory array */
 208 #define SPI_WRDI 0x04           /* Reset write enable latch */
 209 #define SPI_RDSR 0x05           /* Read status register */
 210 #define SPI_WREN 0x06           /* Set write enable latch */
 211 #define SPI_SST_EWSR 0x50       /* SST: Enable write to status register */
 212
 213 #define SPI_STATUS_WPEN 0x80    /* Write-protect pin enabled */
 214 #define SPI_STATUS_BP2 0x10     /* Block protection bit 2 */
 215 #define SPI_STATUS_BP1 0x08     /* Block protection bit 1 */
 216 #define SPI_STATUS_BP0 0x04     /* Block protection bit 0 */
 217 #define SPI_STATUS_WEN 0x02     /* State of the write enable latch */
 218 #define SPI_STATUS_NRDY 0x01    /* Device busy flag */
 219
 220 /**************************************************************************
 221  *
 222  * Non-volatile memory layout
 223  *
 224  **************************************************************************
 225  */
 226
 227 /* SFC4000 flash is partitioned into:
 228  *     0-0x400       chip and board config (see struct falcon_nvconfig)
 229  *     0x400-0x8000  unused (or may contain VPD if EEPROM not present)
 230  *     0x8000-end    boot code (mapped to PCI expansion ROM)
 231  * SFC4000 small EEPROM (size < 0x400) is used for VPD only.
 232  * SFC4000 large EEPROM (size >= 0x400) is partitioned into:
 233  *     0-0x400       chip and board config
 234  *     configurable  VPD
 235  *     0x800-0x1800  boot config
 236  * Aside from the chip and board config, all of these are optional and may
 237  * be absent or truncated depending on the devices used.
 238  */
 239 #define FALCON_NVCONFIG_END 0x400U
 240 #define FALCON_FLASH_BOOTCODE_START 0x8000U
 241 #define FALCON_EEPROM_BOOTCONFIG_START 0x800U
 242 #define FALCON_EEPROM_BOOTCONFIG_END 0x1800U
 243
 244 /* Board configuration v2 (v1 is obsolete; later versions are compatible) */
 245 struct falcon_nvconfig_board_v2 {
 246         __le16 nports;
 247         u8 port0_phy_addr;
 248         u8 port0_phy_type;
 249         u8 port1_phy_addr;
 250         u8 port1_phy_type;
 251         __le16 asic_sub_revision;
 252         __le16 board_revision;
 253 } __packed;
 254
 255 /* Board configuration v3 extra information */
 256 struct falcon_nvconfig_board_v3 {
 257         __le32 spi_device_type[2];
 258 } __packed;
 259
 260 /* Bit numbers for spi_device_type */
 261 #define SPI_DEV_TYPE_SIZE_LBN 0
 262 #define SPI_DEV_TYPE_SIZE_WIDTH 5
 263 #define SPI_DEV_TYPE_ADDR_LEN_LBN 6
 264 #define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
 265 #define SPI_DEV_TYPE_ERASE_CMD_LBN 8
 266 #define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
 267 #define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
 268 #define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
 269 #define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
 270 #define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
 271 #define SPI_DEV_TYPE_FIELD(type, field)                                 \
 272         (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
 273
 274 #define FALCON_NVCONFIG_OFFSET 0x300
 275
 276 #define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
 277 struct falcon_nvconfig {
 278         efx_oword_t ee_vpd_cfg_reg;                     /* 0x300 */
 279         u8 mac_address[2][8];                   /* 0x310 */
 280         efx_oword_t pcie_sd_ctl0123_reg;                /* 0x320 */
 281         efx_oword_t pcie_sd_ctl45_reg;                  /* 0x330 */
 282         efx_oword_t pcie_pcs_ctl_stat_reg;              /* 0x340 */
 283         efx_oword_t hw_init_reg;                        /* 0x350 */
 284         efx_oword_t nic_stat_reg;                       /* 0x360 */
 285         efx_oword_t glb_ctl_reg;                        /* 0x370 */
 286         efx_oword_t srm_cfg_reg;                        /* 0x380 */
 287         efx_oword_t spare_reg;                          /* 0x390 */
 288         __le16 board_magic_num;                 /* 0x3A0 */
 289         __le16 board_struct_ver;
 290         __le16 board_checksum;
 291         struct falcon_nvconfig_board_v2 board_v2;
 292         efx_oword_t ee_base_page_reg;                   /* 0x3B0 */
 293         struct falcon_nvconfig_board_v3 board_v3;       /* 0x3C0 */
 294 } __packed;
 295
 296 /*************************************************************************/
 297
 298 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method);
 299 static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx);
 300
 301 static const unsigned int
 302 /* "Large" EEPROM device: Atmel AT25640 or similar
 303  * 8 KB, 16-bit address, 32 B write block */
 304 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
 305                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
 306                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
 307 /* Default flash device: Atmel AT25F1024
 308  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
 309 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
 310                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
 311                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
 312                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
 313                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
 314
 315 /**************************************************************************
 316  *
 317  * I2C bus - this is a bit-bashing interface using GPIO pins
 318  * Note that it uses the output enables to tristate the outputs
 319  * SDA is the data pin and SCL is the clock
 320  *
 321  **************************************************************************
 322  */
 323 static void falcon_setsda(void *data, int state)
 324 {
 325         struct efx_nic *efx = (struct efx_nic *)data;
 326         efx_oword_t reg;
 327
 328         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 329         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
 330         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
 331 }
 332
 333 static void falcon_setscl(void *data, int state)
 334 {
 335         struct efx_nic *efx = (struct efx_nic *)data;
 336         efx_oword_t reg;
 337
 338         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 339         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
 340         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
 341 }
 342
 343 static int falcon_getsda(void *data)
 344 {
 345         struct efx_nic *efx = (struct efx_nic *)data;
 346         efx_oword_t reg;
 347
 348         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 349         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
 350 }
 351
 352 static int falcon_getscl(void *data)
 353 {
 354         struct efx_nic *efx = (struct efx_nic *)data;
 355         efx_oword_t reg;
 356
 357         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
 358         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
 359 }
 360
 361 static const struct i2c_algo_bit_data falcon_i2c_bit_operations = {
 362         .setsda         = falcon_setsda,
 363         .setscl         = falcon_setscl,
 364         .getsda         = falcon_getsda,
 365         .getscl         = falcon_getscl,
 366         .udelay         = 5,
 367         /* Wait up to 50 ms for slave to let us pull SCL high */
 368         .timeout        = DIV_ROUND_UP(HZ, 20),
 369 };
 370
 371 static void falcon_push_irq_moderation(struct efx_channel *channel)
 372 {
 373         efx_dword_t timer_cmd;
 374         struct efx_nic *efx = channel->efx;
 375
 376         /* Set timer register */
 377         if (channel->irq_moderation) {
 378                 EFX_POPULATE_DWORD_2(timer_cmd,
 379                                      FRF_AB_TC_TIMER_MODE,
 380                                      FFE_BB_TIMER_MODE_INT_HLDOFF,
 381                                      FRF_AB_TC_TIMER_VAL,
 382                                      channel->irq_moderation - 1);
 383         } else {
 384                 EFX_POPULATE_DWORD_2(timer_cmd,
 385                                      FRF_AB_TC_TIMER_MODE,
 386                                      FFE_BB_TIMER_MODE_DIS,
 387                                      FRF_AB_TC_TIMER_VAL, 0);
 388         }
 389         BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
 390         efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
 391                                channel->channel);
 392 }
 393
 394 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
 395
 396 static void falcon_prepare_flush(struct efx_nic *efx)
 397 {
 398         falcon_deconfigure_mac_wrapper(efx);
 399
 400         /* Wait for the tx and rx fifo's to get to the next packet boundary
 401          * (~1ms without back-pressure), then to drain the remainder of the
 402          * fifo's at data path speeds (negligible), with a healthy margin. */
 403         msleep(10);
 404 }
 405
 406 /* Acknowledge a legacy interrupt from Falcon
 407  *
 408  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
 409  *
 410  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
 411  * BIU. Interrupt acknowledge is read sensitive so must write instead
 412  * (then read to ensure the BIU collector is flushed)
 413  *
 414  * NB most hardware supports MSI interrupts
 415  */
 416 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
 417 {
 418         efx_dword_t reg;
 419
 420         EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
 421         efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
 422         efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
 423 }
 424
 425
 426 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
 427 {
 428         struct efx_nic *efx = dev_id;
 429         efx_oword_t *int_ker = efx->irq_status.addr;
 430         int syserr;
 431         int queues;
 432
 433         /* Check to see if this is our interrupt.  If it isn't, we
 434          * exit without having touched the hardware.
 435          */
 436         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
 437                 netif_vdbg(efx, intr, efx->net_dev,
 438                            "IRQ %d on CPU %d not for me\n", irq,
 439                            raw_smp_processor_id());
 440                 return IRQ_NONE;
 441         }
 442         efx->last_irq_cpu = raw_smp_processor_id();
 443         netif_vdbg(efx, intr, efx->net_dev,
 444                    "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
 445                    irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
 446
 447         if (!likely(ACCESS_ONCE(efx->irq_soft_enabled)))
 448                 return IRQ_HANDLED;
 449
 450         /* Check to see if we have a serious error condition */
 451         syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
 452         if (unlikely(syserr))
 453                 return efx_farch_fatal_interrupt(efx);
 454
 455         /* Determine interrupting queues, clear interrupt status
 456          * register and acknowledge the device interrupt.
 457          */
 458         BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
 459         queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
 460         EFX_ZERO_OWORD(*int_ker);
 461         wmb(); /* Ensure the vector is cleared before interrupt ack */
 462         falcon_irq_ack_a1(efx);
 463
 464         if (queues & 1)
 465                 efx_schedule_channel_irq(efx_get_channel(efx, 0));
 466         if (queues & 2)
 467                 efx_schedule_channel_irq(efx_get_channel(efx, 1));
 468         return IRQ_HANDLED;
 469 }
 470 /**************************************************************************
 471  *
 472  * RSS
 473  *
 474  **************************************************************************
 475  */
 476
 477 static void falcon_b0_rx_push_rss_config(struct efx_nic *efx)
 478 {
 479         efx_oword_t temp;
 480
 481         /* Set hash key for IPv4 */
 482         memcpy(&temp, efx->rx_hash_key, sizeof(temp));
 483         efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
 484
 485         efx_farch_rx_push_indir_table(efx);
 486 }
 487
 488 /**************************************************************************
 489  *
 490  * EEPROM/flash
 491  *
 492  **************************************************************************
 493  */
 494
 495 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
 496
 497 static int falcon_spi_poll(struct efx_nic *efx)
 498 {
 499         efx_oword_t reg;
 500         efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
 501         return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
 502 }
 503
 504 /* Wait for SPI command completion */
 505 static int falcon_spi_wait(struct efx_nic *efx)
 506 {
 507         /* Most commands will finish quickly, so we start polling at
 508          * very short intervals.  Sometimes the command may have to
 509          * wait for VPD or expansion ROM access outside of our
 510          * control, so we allow up to 100 ms. */
 511         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
 512         int i;
 513
 514         for (i = 0; i < 10; i++) {
 515                 if (!falcon_spi_poll(efx))
 516                         return 0;
 517                 udelay(10);
 518         }
 519
 520         for (;;) {
 521                 if (!falcon_spi_poll(efx))
 522                         return 0;
 523                 if (time_after_eq(jiffies, timeout)) {
 524                         netif_err(efx, hw, efx->net_dev,
 525                                   "timed out waiting for SPI\n");
 526                         return -ETIMEDOUT;
 527                 }
 528                 schedule_timeout_uninterruptible(1);
 529         }
 530 }
 531
 532 static int
 533 falcon_spi_cmd(struct efx_nic *efx, const struct falcon_spi_device *spi,
 534                unsigned int command, int address,
 535                const void *in, void *out, size_t len)
 536 {
 537         bool addressed = (address >= 0);
 538         bool reading = (out != NULL);
 539         efx_oword_t reg;
 540         int rc;
 541
 542         /* Input validation */
 543         if (len > FALCON_SPI_MAX_LEN)
 544                 return -EINVAL;
 545
 546         /* Check that previous command is not still running */
 547         rc = falcon_spi_poll(efx);
 548         if (rc)
 549                 return rc;
 550
 551         /* Program address register, if we have an address */
 552         if (addressed) {
 553                 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
 554                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
 555         }
 556
 557         /* Program data register, if we have data */
 558         if (in != NULL) {
 559                 memcpy(&reg, in, len);
 560                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
 561         }
 562
 563         /* Issue read/write command */
 564         EFX_POPULATE_OWORD_7(reg,
 565                              FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
 566                              FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
 567                              FRF_AB_EE_SPI_HCMD_DABCNT, len,
 568                              FRF_AB_EE_SPI_HCMD_READ, reading,
 569                              FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
 570                              FRF_AB_EE_SPI_HCMD_ADBCNT,
 571                              (addressed ? spi->addr_len : 0),
 572                              FRF_AB_EE_SPI_HCMD_ENC, command);
 573         efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
 574
 575         /* Wait for read/write to complete */
 576         rc = falcon_spi_wait(efx);
 577         if (rc)
 578                 return rc;
 579
 580         /* Read data */
 581         if (out != NULL) {
 582                 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
 583                 memcpy(out, &reg, len);
 584         }
 585
 586         return 0;
 587 }
 588
 589 static inline u8
 590 falcon_spi_munge_command(const struct falcon_spi_device *spi,
 591                          const u8 command, const unsigned int address)
 592 {
 593         return command | (((address >> 8) & spi->munge_address) << 3);
 594 }
 595
 596 static int
 597 falcon_spi_read(struct efx_nic *efx, const struct falcon_spi_device *spi,
 598                 loff_t start, size_t len, size_t *retlen, u8 *buffer)
 599 {
 600         size_t block_len, pos = 0;
 601         unsigned int command;
 602         int rc = 0;
 603
 604         while (pos < len) {
 605                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
 606
 607                 command = falcon_spi_munge_command(spi, SPI_READ, start + pos);
 608                 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
 609                                     buffer + pos, block_len);
 610                 if (rc)
 611                         break;
 612                 pos += block_len;
 613
 614                 /* Avoid locking up the system */
 615                 cond_resched();
 616                 if (signal_pending(current)) {
 617                         rc = -EINTR;
 618                         break;
 619                 }
 620         }
 621
 622         if (retlen)
 623                 *retlen = pos;
 624         return rc;
 625 }
 626
 627 #ifdef CONFIG_SFC_MTD
 628
 629 struct falcon_mtd_partition {
 630         struct efx_mtd_partition common;
 631         const struct falcon_spi_device *spi;
 632         size_t offset;
 633 };
 634
 635 #define to_falcon_mtd_partition(mtd)                            \
 636         container_of(mtd, struct falcon_mtd_partition, common.mtd)
 637
 638 static size_t
 639 falcon_spi_write_limit(const struct falcon_spi_device *spi, size_t start)
 640 {
 641         return min(FALCON_SPI_MAX_LEN,
 642                    (spi->block_size - (start & (spi->block_size - 1))));
 643 }
 644
 645 /* Wait up to 10 ms for buffered write completion */
 646 static int
 647 falcon_spi_wait_write(struct efx_nic *efx, const struct falcon_spi_device *spi)
 648 {
 649         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
 650         u8 status;
 651         int rc;
 652
 653         for (;;) {
 654                 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
 655                                     &status, sizeof(status));
 656                 if (rc)
 657                         return rc;
 658                 if (!(status & SPI_STATUS_NRDY))
 659                         return 0;
 660                 if (time_after_eq(jiffies, timeout)) {
 661                         netif_err(efx, hw, efx->net_dev,
 662                                   "SPI write timeout on device %d"
 663                                   " last status=0x%02x\n",
 664                                   spi->device_id, status);
 665                         return -ETIMEDOUT;
 666                 }
 667                 schedule_timeout_uninterruptible(1);
 668         }
 669 }
 670
 671 static int
 672 falcon_spi_write(struct efx_nic *efx, const struct falcon_spi_device *spi,
 673                  loff_t start, size_t len, size_t *retlen, const u8 *buffer)
 674 {
 675         u8 verify_buffer[FALCON_SPI_MAX_LEN];
 676         size_t block_len, pos = 0;
 677         unsigned int command;
 678         int rc = 0;
 679
 680         while (pos < len) {
 681                 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
 682                 if (rc)
 683                         break;
 684
 685                 block_len = min(len - pos,
 686                                 falcon_spi_write_limit(spi, start + pos));
 687                 command = falcon_spi_munge_command(spi, SPI_WRITE, start + pos);
 688                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
 689                                     buffer + pos, NULL, block_len);
 690                 if (rc)
 691                         break;
 692
 693                 rc = falcon_spi_wait_write(efx, spi);
 694                 if (rc)
 695                         break;
 696
 697                 command = falcon_spi_munge_command(spi, SPI_READ, start + pos);
 698                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
 699                                     NULL, verify_buffer, block_len);
 700                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
 701                         rc = -EIO;
 702                         break;
 703                 }
 704
 705                 pos += block_len;
 706
 707                 /* Avoid locking up the system */
 708                 cond_resched();
 709                 if (signal_pending(current)) {
 710                         rc = -EINTR;
 711                         break;
 712                 }
 713         }
 714
 715         if (retlen)
 716                 *retlen = pos;
 717         return rc;
 718 }
 719
 720 static int
 721 falcon_spi_slow_wait(struct falcon_mtd_partition *part, bool uninterruptible)
 722 {
 723         const struct falcon_spi_device *spi = part->spi;
 724         struct efx_nic *efx = part->common.mtd.priv;
 725         u8 status;
 726         int rc, i;
 727
 728         /* Wait up to 4s for flash/EEPROM to finish a slow operation. */
 729         for (i = 0; i < 40; i++) {
 730                 __set_current_state(uninterruptible ?
 731                                     TASK_UNINTERRUPTIBLE : TASK_INTERRUPTIBLE);
 732                 schedule_timeout(HZ / 10);
 733                 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
 734                                     &status, sizeof(status));
 735                 if (rc)
 736                         return rc;
 737                 if (!(status & SPI_STATUS_NRDY))
 738                         return 0;
 739                 if (signal_pending(current))
 740                         return -EINTR;
 741         }
 742         pr_err("%s: timed out waiting for %s\n",
 743                part->common.name, part->common.dev_type_name);
 744         return -ETIMEDOUT;
 745 }
 746
 747 static int
 748 falcon_spi_unlock(struct efx_nic *efx, const struct falcon_spi_device *spi)
 749 {
 750         const u8 unlock_mask = (SPI_STATUS_BP2 | SPI_STATUS_BP1 |
 751                                 SPI_STATUS_BP0);
 752         u8 status;
 753         int rc;
 754
 755         rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
 756                             &status, sizeof(status));
 757         if (rc)
 758                 return rc;
 759
 760         if (!(status & unlock_mask))
 761                 return 0; /* already unlocked */
 762
 763         rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
 764         if (rc)
 765                 return rc;
 766         rc = falcon_spi_cmd(efx, spi, SPI_SST_EWSR, -1, NULL, NULL, 0);
 767         if (rc)
 768                 return rc;
 769
 770         status &= ~unlock_mask;
 771         rc = falcon_spi_cmd(efx, spi, SPI_WRSR, -1, &status,
 772                             NULL, sizeof(status));
 773         if (rc)
 774                 return rc;
 775         rc = falcon_spi_wait_write(efx, spi);
 776         if (rc)
 777                 return rc;
 778
 779         return 0;
 780 }
 781
 782 #define FALCON_SPI_VERIFY_BUF_LEN 16
 783
 784 static int
 785 falcon_spi_erase(struct falcon_mtd_partition *part, loff_t start, size_t len)
 786 {
 787         const struct falcon_spi_device *spi = part->spi;
 788         struct efx_nic *efx = part->common.mtd.priv;
 789         unsigned pos, block_len;
 790         u8 empty[FALCON_SPI_VERIFY_BUF_LEN];
 791         u8 buffer[FALCON_SPI_VERIFY_BUF_LEN];
 792         int rc;
 793
 794         if (len != spi->erase_size)
 795                 return -EINVAL;
 796
 797         if (spi->erase_command == 0)
 798                 return -EOPNOTSUPP;
 799
 800         rc = falcon_spi_unlock(efx, spi);
 801         if (rc)
 802                 return rc;
 803         rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
 804         if (rc)
 805                 return rc;
 806         rc = falcon_spi_cmd(efx, spi, spi->erase_command, start, NULL,
 807                             NULL, 0);
 808         if (rc)
 809                 return rc;
 810         rc = falcon_spi_slow_wait(part, false);
 811
 812         /* Verify the entire region has been wiped */
 813         memset(empty, 0xff, sizeof(empty));
 814         for (pos = 0; pos < len; pos += block_len) {
 815                 block_len = min(len - pos, sizeof(buffer));
 816                 rc = falcon_spi_read(efx, spi, start + pos, block_len,
 817                                      NULL, buffer);
 818                 if (rc)
 819                         return rc;
 820                 if (memcmp(empty, buffer, block_len))
 821                         return -EIO;
 822
 823                 /* Avoid locking up the system */
 824                 cond_resched();
 825                 if (signal_pending(current))
 826                         return -EINTR;
 827         }
 828
 829         return rc;
 830 }
 831
 832 static void falcon_mtd_rename(struct efx_mtd_partition *part)
 833 {
 834         struct efx_nic *efx = part->mtd.priv;
 835
 836         snprintf(part->name, sizeof(part->name), "%s %s",
 837                  efx->name, part->type_name);
 838 }
 839
 840 static int falcon_mtd_read(struct mtd_info *mtd, loff_t start,
 841                            size_t len, size_t *retlen, u8 *buffer)
 842 {
 843         struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
 844         struct efx_nic *efx = mtd->priv;
 845         struct falcon_nic_data *nic_data = efx->nic_data;
 846         int rc;
 847
 848         rc = mutex_lock_interruptible(&nic_data->spi_lock);
 849         if (rc)
 850                 return rc;
 851         rc = falcon_spi_read(efx, part->spi, part->offset + start,
 852                              len, retlen, buffer);
 853         mutex_unlock(&nic_data->spi_lock);
 854         return rc;
 855 }
 856
 857 static int falcon_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
 858 {
 859         struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
 860         struct efx_nic *efx = mtd->priv;
 861         struct falcon_nic_data *nic_data = efx->nic_data;
 862         int rc;
 863
 864         rc = mutex_lock_interruptible(&nic_data->spi_lock);
 865         if (rc)
 866                 return rc;
 867         rc = falcon_spi_erase(part, part->offset + start, len);
 868         mutex_unlock(&nic_data->spi_lock);
 869         return rc;
 870 }
 871
 872 static int falcon_mtd_write(struct mtd_info *mtd, loff_t start,
 873                             size_t len, size_t *retlen, const u8 *buffer)
 874 {
 875         struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
 876         struct efx_nic *efx = mtd->priv;
 877         struct falcon_nic_data *nic_data = efx->nic_data;
 878         int rc;
 879
 880         rc = mutex_lock_interruptible(&nic_data->spi_lock);
 881         if (rc)
 882                 return rc;
 883         rc = falcon_spi_write(efx, part->spi, part->offset + start,
 884                               len, retlen, buffer);
 885         mutex_unlock(&nic_data->spi_lock);
 886         return rc;
 887 }
 888
 889 static int falcon_mtd_sync(struct mtd_info *mtd)
 890 {
 891         struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
 892         struct efx_nic *efx = mtd->priv;
 893         struct falcon_nic_data *nic_data = efx->nic_data;
 894         int rc;
 895
 896         mutex_lock(&nic_data->spi_lock);
 897         rc = falcon_spi_slow_wait(part, true);
 898         mutex_unlock(&nic_data->spi_lock);
 899         return rc;
 900 }
 901
 902 static int falcon_mtd_probe(struct efx_nic *efx)
 903 {
 904         struct falcon_nic_data *nic_data = efx->nic_data;
 905         struct falcon_mtd_partition *parts;
 906         struct falcon_spi_device *spi;
 907         size_t n_parts;
 908         int rc = -ENODEV;
 909
 910         ASSERT_RTNL();
 911
 912         /* Allocate space for maximum number of partitions */
 913         parts = kcalloc(2, sizeof(*parts), GFP_KERNEL);
 914         if (!parts)
 915                 return -ENOMEM;
 916         n_parts = 0;
 917
 918         spi = &nic_data->spi_flash;
 919         if (falcon_spi_present(spi) && spi->size > FALCON_FLASH_BOOTCODE_START) {
 920                 parts[n_parts].spi = spi;
 921                 parts[n_parts].offset = FALCON_FLASH_BOOTCODE_START;
 922                 parts[n_parts].common.dev_type_name = "flash";
 923                 parts[n_parts].common.type_name = "sfc_flash_bootrom";
 924                 parts[n_parts].common.mtd.type = MTD_NORFLASH;
 925                 parts[n_parts].common.mtd.flags = MTD_CAP_NORFLASH;
 926                 parts[n_parts].common.mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START;
 927                 parts[n_parts].common.mtd.erasesize = spi->erase_size;
 928                 n_parts++;
 929         }
 930
 931         spi = &nic_data->spi_eeprom;
 932         if (falcon_spi_present(spi) && spi->size > FALCON_EEPROM_BOOTCONFIG_START) {
 933                 parts[n_parts].spi = spi;
 934                 parts[n_parts].offset = FALCON_EEPROM_BOOTCONFIG_START;
 935                 parts[n_parts].common.dev_type_name = "EEPROM";
 936                 parts[n_parts].common.type_name = "sfc_bootconfig";
 937                 parts[n_parts].common.mtd.type = MTD_RAM;
 938                 parts[n_parts].common.mtd.flags = MTD_CAP_RAM;
 939                 parts[n_parts].common.mtd.size =
 940                         min(spi->size, FALCON_EEPROM_BOOTCONFIG_END) -
 941                         FALCON_EEPROM_BOOTCONFIG_START;
 942                 parts[n_parts].common.mtd.erasesize = spi->erase_size;
 943                 n_parts++;
 944         }
 945
 946         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
 947         if (rc)
 948                 kfree(parts);
 949         return rc;
 950 }
 951
 952 #endif /* CONFIG_SFC_MTD */
 953
 954 /**************************************************************************
 955  *
 956  * XMAC operations
 957  *
 958  **************************************************************************
 959  */
 960
 961 /* Configure the XAUI driver that is an output from Falcon */
 962 static void falcon_setup_xaui(struct efx_nic *efx)
 963 {
 964         efx_oword_t sdctl, txdrv;
 965
 966         /* Move the XAUI into low power, unless there is no PHY, in
 967          * which case the XAUI will have to drive a cable. */
 968         if (efx->phy_type == PHY_TYPE_NONE)
 969                 return;
 970
 971         efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
 972         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
 973         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
 974         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
 975         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
 976         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
 977         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
 978         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
 979         EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
 980         efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
 981
 982         EFX_POPULATE_OWORD_8(txdrv,
 983                              FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
 984                              FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
 985                              FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
 986                              FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
 987                              FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
 988                              FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
 989                              FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
 990                              FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
 991         efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
 992 }
 993
 994 int falcon_reset_xaui(struct efx_nic *efx)
 995 {
 996         struct falcon_nic_data *nic_data = efx->nic_data;
 997         efx_oword_t reg;
 998         int count;
 999
1000         /* Don't fetch MAC statistics over an XMAC reset */
1001         WARN_ON(nic_data->stats_disable_count == 0);
1002
1003         /* Start reset sequence */
1004         EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
1005         efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);
1006
1007         /* Wait up to 10 ms for completion, then reinitialise */
1008         for (count = 0; count < 1000; count++) {
1009                 efx_reado(efx, &reg, FR_AB_XX_PWR_RST);
1010                 if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
1011                     EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
1012                         falcon_setup_xaui(efx);
1013                         return 0;
1014                 }
1015                 udelay(10);
1016         }
1017         netif_err(efx, hw, efx->net_dev,
1018                   "timed out waiting for XAUI/XGXS reset\n");
1019         return -ETIMEDOUT;
1020 }
1021
1022 static void falcon_ack_status_intr(struct efx_nic *efx)
1023 {
1024         struct falcon_nic_data *nic_data = efx->nic_data;
1025         efx_oword_t reg;
1026
1027         if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
1028                 return;
1029
1030         /* We expect xgmii faults if the wireside link is down */
1031         if (!efx->link_state.up)
1032                 return;
1033
1034         /* We can only use this interrupt to signal the negative edge of
1035          * xaui_align [we have to poll the positive edge]. */
1036         if (nic_data->xmac_poll_required)
1037                 return;
1038
1039         efx_reado(efx, &reg, FR_AB_XM_MGT_INT_MSK);
1040 }
1041
1042 static bool falcon_xgxs_link_ok(struct efx_nic *efx)
1043 {
1044         efx_oword_t reg;
1045         bool align_done, link_ok = false;
1046         int sync_status;
1047
1048         /* Read link status */
1049         efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
1050
1051         align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
1052         sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
1053         if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
1054                 link_ok = true;
1055
1056         /* Clear link status ready for next read */
1057         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
1058         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
1059         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
1060         efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
1061
1062         return link_ok;
1063 }
1064
1065 static bool falcon_xmac_link_ok(struct efx_nic *efx)
1066 {
1067         /*
1068          * Check MAC's XGXS link status except when using XGMII loopback
1069          * which bypasses the XGXS block.
1070          * If possible, check PHY's XGXS link status except when using
1071          * MAC loopback.
1072          */
1073         return (efx->loopback_mode == LOOPBACK_XGMII ||
1074                 falcon_xgxs_link_ok(efx)) &&
1075                 (!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) ||
1076                  LOOPBACK_INTERNAL(efx) ||
1077                  efx_mdio_phyxgxs_lane_sync(efx));
1078 }
1079
1080 static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
1081 {
1082         unsigned int max_frame_len;
1083         efx_oword_t reg;
1084         bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
1085         bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
1086
1087         /* Configure MAC  - cut-thru mode is hard wired on */
1088         EFX_POPULATE_OWORD_3(reg,
1089                              FRF_AB_XM_RX_JUMBO_MODE, 1,
1090                              FRF_AB_XM_TX_STAT_EN, 1,
1091                              FRF_AB_XM_RX_STAT_EN, 1);
1092         efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1093
1094         /* Configure TX */
1095         EFX_POPULATE_OWORD_6(reg,
1096                              FRF_AB_XM_TXEN, 1,
1097                              FRF_AB_XM_TX_PRMBL, 1,
1098                              FRF_AB_XM_AUTO_PAD, 1,
1099                              FRF_AB_XM_TXCRC, 1,
1100                              FRF_AB_XM_FCNTL, tx_fc,
1101                              FRF_AB_XM_IPG, 0x3);
1102         efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);
1103
1104         /* Configure RX */
1105         EFX_POPULATE_OWORD_5(reg,
1106                              FRF_AB_XM_RXEN, 1,
1107                              FRF_AB_XM_AUTO_DEPAD, 0,
1108                              FRF_AB_XM_ACPT_ALL_MCAST, 1,
1109                              FRF_AB_XM_ACPT_ALL_UCAST, !efx->unicast_filter,
1110                              FRF_AB_XM_PASS_CRC_ERR, 1);
1111         efx_writeo(efx, &reg, FR_AB_XM_RX_CFG);
1112
1113         /* Set frame length */
1114         max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
1115         EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
1116         efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);
1117         EFX_POPULATE_OWORD_2(reg,
1118                              FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
1119                              FRF_AB_XM_TX_JUMBO_MODE, 1);
1120         efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);
1121
1122         EFX_POPULATE_OWORD_2(reg,
1123                              FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
1124                              FRF_AB_XM_DIS_FCNTL, !rx_fc);
1125         efx_writeo(efx, &reg, FR_AB_XM_FC);
1126
1127         /* Set MAC address */
1128         memcpy(&reg, &efx->net_dev->dev_addr[0], 4);
1129         efx_writeo(efx, &reg, FR_AB_XM_ADR_LO);
1130         memcpy(&reg, &efx->net_dev->dev_addr[4], 2);
1131         efx_writeo(efx, &reg, FR_AB_XM_ADR_HI);
1132 }
1133
1134 static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
1135 {
1136         efx_oword_t reg;
1137         bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
1138         bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
1139         bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
1140         bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
1141
1142         /* XGXS block is flaky and will need to be reset if moving
1143          * into our out of XGMII, XGXS or XAUI loopbacks. */
1144         efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
1145         old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
1146         old_xgmii_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
1147
1148         efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
1149         old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
1150
1151         /* The PHY driver may have turned XAUI off */
1152         if ((xgxs_loopback != old_xgxs_loopback) ||
1153             (xaui_loopback != old_xaui_loopback) ||
1154             (xgmii_loopback != old_xgmii_loopback))
1155                 falcon_reset_xaui(efx);
1156
1157         efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
1158         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
1159                             (xgxs_loopback || xaui_loopback) ?
1160                             FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
1161         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
1162         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
1163         efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
1164
1165         efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
1166         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
1167         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
1168         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
1169         EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
1170         efx_writeo(efx, &reg, FR_AB_XX_SD_CTL);
1171 }
1172
1173
1174 /* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
1175 static bool falcon_xmac_link_ok_retry(struct efx_nic *efx, int tries)
1176 {
1177         bool mac_up = falcon_xmac_link_ok(efx);
1178
1179         if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
1180             efx_phy_mode_disabled(efx->phy_mode))
1181                 /* XAUI link is expected to be down */
1182                 return mac_up;
1183
1184         falcon_stop_nic_stats(efx);
1185
1186         while (!mac_up && tries) {
1187                 netif_dbg(efx, hw, efx->net_dev, "bashing xaui\n");
1188                 falcon_reset_xaui(efx);
1189                 udelay(200);
1190
1191                 mac_up = falcon_xmac_link_ok(efx);
1192                 --tries;
1193         }
1194
1195         falcon_start_nic_stats(efx);
1196
1197         return mac_up;
1198 }
1199
1200 static bool falcon_xmac_check_fault(struct efx_nic *efx)
1201 {
1202         return !falcon_xmac_link_ok_retry(efx, 5);
1203 }
1204
1205 static int falcon_reconfigure_xmac(struct efx_nic *efx)
1206 {
1207         struct falcon_nic_data *nic_data = efx->nic_data;
1208
1209         efx_farch_filter_sync_rx_mode(efx);
1210
1211         falcon_reconfigure_xgxs_core(efx);
1212         falcon_reconfigure_xmac_core(efx);
1213
1214         falcon_reconfigure_mac_wrapper(efx);
1215
1216         nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
1217         falcon_ack_status_intr(efx);
1218
1219         return 0;
1220 }
1221
1222 static void falcon_poll_xmac(struct efx_nic *efx)
1223 {
1224         struct falcon_nic_data *nic_data = efx->nic_data;
1225
1226         /* We expect xgmii faults if the wireside link is down */
1227         if (!efx->link_state.up || !nic_data->xmac_poll_required)
1228                 return;
1229
1230         nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
1231         falcon_ack_status_intr(efx);
1232 }
1233
1234 /**************************************************************************
1235  *
1236  * MAC wrapper
1237  *
1238  **************************************************************************
1239  */
1240
1241 static void falcon_push_multicast_hash(struct efx_nic *efx)
1242 {
1243         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
1244
1245         WARN_ON(!mutex_is_locked(&efx->mac_lock));
1246
1247         efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
1248         efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
1249 }
1250
1251 static void falcon_reset_macs(struct efx_nic *efx)
1252 {
1253         struct falcon_nic_data *nic_data = efx->nic_data;
1254         efx_oword_t reg, mac_ctrl;
1255         int count;
1256
1257         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
1258                 /* It's not safe to use GLB_CTL_REG to reset the
1259                  * macs, so instead use the internal MAC resets
1260                  */
1261                 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1262                 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1263
1264                 for (count = 0; count < 10000; count++) {
1265                         efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
1266                         if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1267                             0)
1268                                 return;
1269                         udelay(10);
1270                 }
1271
1272                 netif_err(efx, hw, efx->net_dev,
1273                           "timed out waiting for XMAC core reset\n");
1274         }
1275
1276         /* Mac stats will fail whist the TX fifo is draining */
1277         WARN_ON(nic_data->stats_disable_count == 0);
1278
1279         efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1280         EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
1281         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1282
1283         efx_reado(efx, &reg, FR_AB_GLB_CTL);
1284         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1285         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1286         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1287         efx_writeo(efx, &reg, FR_AB_GLB_CTL);
1288
1289         count = 0;
1290         while (1) {
1291                 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1292                 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1293                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1294                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1295                         netif_dbg(efx, hw, efx->net_dev,
1296                                   "Completed MAC reset after %d loops\n",
1297                                   count);
1298                         break;
1299                 }
1300                 if (count > 20) {
1301                         netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
1302                         break;
1303                 }
1304                 count++;
1305                 udelay(10);
1306         }
1307
1308         /* Ensure the correct MAC is selected before statistics
1309          * are re-enabled by the caller */
1310         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
1311
1312         falcon_setup_xaui(efx);
1313 }
1314
1315 static void falcon_drain_tx_fifo(struct efx_nic *efx)
1316 {
1317         efx_oword_t reg;
1318
1319         if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
1320             (efx->loopback_mode != LOOPBACK_NONE))
1321                 return;
1322
1323         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1324         /* There is no point in draining more than once */
1325         if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1326                 return;
1327
1328         falcon_reset_macs(efx);
1329 }
1330
1331 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1332 {
1333         efx_oword_t reg;
1334
1335         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1336                 return;
1337
1338         /* Isolate the MAC -> RX */
1339         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1340         EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1341         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1342
1343         /* Isolate TX -> MAC */
1344         falcon_drain_tx_fifo(efx);
1345 }
1346
1347 static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1348 {
1349         struct efx_link_state *link_state = &efx->link_state;
1350         efx_oword_t reg;
1351         int link_speed, isolate;
1352
1353         isolate = !!ACCESS_ONCE(efx->reset_pending);
1354
1355         switch (link_state->speed) {
1356         case 10000: link_speed = 3; break;
1357         case 1000:  link_speed = 2; break;
1358         case 100:   link_speed = 1; break;
1359         default:    link_speed = 0; break;
1360         }
1361         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1362          * as advertised.  Disable to ensure packets are not
1363          * indefinitely held and TX queue can be flushed at any point
1364          * while the link is down. */
1365         EFX_POPULATE_OWORD_5(reg,
1366                              FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1367                              FRF_AB_MAC_BCAD_ACPT, 1,
1368                              FRF_AB_MAC_UC_PROM, !efx->unicast_filter,
1369                              FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1370                              FRF_AB_MAC_SPEED, link_speed);
1371         /* On B0, MAC backpressure can be disabled and packets get
1372          * discarded. */
1373         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1374                 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
1375                                     !link_state->up || isolate);
1376         }
1377
1378         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1379
1380         /* Restore the multicast hash registers. */
1381         falcon_push_multicast_hash(efx);
1382
1383         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1384         /* Enable XOFF signal from RX FIFO (we enabled it during NIC
1385          * initialisation but it may read back as 0) */
1386         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1387         /* Unisolate the MAC -> RX */
1388         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1389                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);
1390         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1391 }
1392
1393 static void falcon_stats_request(struct efx_nic *efx)
1394 {
1395         struct falcon_nic_data *nic_data = efx->nic_data;
1396         efx_oword_t reg;
1397
1398         WARN_ON(nic_data->stats_pending);
1399         WARN_ON(nic_data->stats_disable_count);
1400
1401         FALCON_XMAC_STATS_DMA_FLAG(efx) = 0;
1402         nic_data->stats_pending = true;
1403         wmb(); /* ensure done flag is clear */
1404
1405         /* Initiate DMA transfer of stats */
1406         EFX_POPULATE_OWORD_2(reg,
1407                              FRF_AB_MAC_STAT_DMA_CMD, 1,
1408                              FRF_AB_MAC_STAT_DMA_ADR,
1409                              efx->stats_buffer.dma_addr);
1410         efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
1411
1412         mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
1413 }
1414
1415 static void falcon_stats_complete(struct efx_nic *efx)
1416 {
1417         struct falcon_nic_data *nic_data = efx->nic_data;
1418
1419         if (!nic_data->stats_pending)
1420                 return;
1421
1422         nic_data->stats_pending = false;
1423         if (FALCON_XMAC_STATS_DMA_FLAG(efx)) {
1424                 rmb(); /* read the done flag before the stats */
1425                 efx_nic_update_stats(falcon_stat_desc, FALCON_STAT_COUNT,
1426                                      falcon_stat_mask, nic_data->stats,
1427                                      efx->stats_buffer.addr, true);
1428         } else {
1429                 netif_err(efx, hw, efx->net_dev,
1430                           "timed out waiting for statistics\n");
1431         }
1432 }
1433
1434 static void falcon_stats_timer_func(unsigned long context)
1435 {
1436         struct efx_nic *efx = (struct efx_nic *)context;
1437         struct falcon_nic_data *nic_data = efx->nic_data;
1438
1439         spin_lock(&efx->stats_lock);
1440
1441         falcon_stats_complete(efx);
1442         if (nic_data->stats_disable_count == 0)
1443                 falcon_stats_request(efx);
1444
1445         spin_unlock(&efx->stats_lock);
1446 }
1447
1448 static bool falcon_loopback_link_poll(struct efx_nic *efx)
1449 {
1450         struct efx_link_state old_state = efx->link_state;
1451
1452         WARN_ON(!mutex_is_locked(&efx->mac_lock));
1453         WARN_ON(!LOOPBACK_INTERNAL(efx));
1454
1455         efx->link_state.fd = true;
1456         efx->link_state.fc = efx->wanted_fc;
1457         efx->link_state.up = true;
1458         efx->link_state.speed = 10000;
1459
1460         return !efx_link_state_equal(&efx->link_state, &old_state);
1461 }
1462
1463 static int falcon_reconfigure_port(struct efx_nic *efx)
1464 {
1465         int rc;
1466
1467         WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
1468
1469         /* Poll the PHY link state *before* reconfiguring it. This means we
1470          * will pick up the correct speed (in loopback) to select the correct
1471          * MAC.
1472          */
1473         if (LOOPBACK_INTERNAL(efx))
1474                 falcon_loopback_link_poll(efx);
1475         else
1476                 efx->phy_op->poll(efx);
1477
1478         falcon_stop_nic_stats(efx);
1479         falcon_deconfigure_mac_wrapper(efx);
1480
1481         falcon_reset_macs(efx);
1482
1483         efx->phy_op->reconfigure(efx);
1484         rc = falcon_reconfigure_xmac(efx);
1485         BUG_ON(rc);
1486
1487         falcon_start_nic_stats(efx);
1488
1489         /* Synchronise efx->link_state with the kernel */
1490         efx_link_status_changed(efx);
1491
1492         return 0;
1493 }
1494
1495 /* TX flow control may automatically turn itself off if the link
1496  * partner (intermittently) stops responding to pause frames. There
1497  * isn't any indication that this has happened, so the best we do is
1498  * leave it up to the user to spot this and fix it by cycling transmit
1499  * flow control on this end.
1500  */
1501
1502 static void falcon_a1_prepare_enable_fc_tx(struct efx_nic *efx)
1503 {
1504         /* Schedule a reset to recover */
1505         efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
1506 }
1507
1508 static void falcon_b0_prepare_enable_fc_tx(struct efx_nic *efx)
1509 {
1510         /* Recover by resetting the EM block */
1511         falcon_stop_nic_stats(efx);
1512         falcon_drain_tx_fifo(efx);
1513         falcon_reconfigure_xmac(efx);
1514         falcon_start_nic_stats(efx);
1515 }
1516
1517 /**************************************************************************
1518  *
1519  * PHY access via GMII
1520  *
1521  **************************************************************************
1522  */
1523
1524 /* Wait for GMII access to complete */
1525 static int falcon_gmii_wait(struct efx_nic *efx)
1526 {
1527         efx_oword_t md_stat;
1528         int count;
1529
1530         /* wait up to 50ms - taken max from datasheet */
1531         for (count = 0; count < 5000; count++) {
1532                 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
1533                 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
1534                         if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
1535                             EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
1536                                 netif_err(efx, hw, efx->net_dev,
1537                                           "error from GMII access "
1538                                           EFX_OWORD_FMT"\n",
1539                                           EFX_OWORD_VAL(md_stat));
1540                                 return -EIO;
1541                         }
1542                         return 0;
1543                 }
1544                 udelay(10);
1545         }
1546         netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
1547         return -ETIMEDOUT;
1548 }
1549
1550 /* Write an MDIO register of a PHY connected to Falcon. */
1551 static int falcon_mdio_write(struct net_device *net_dev,
1552                              int prtad, int devad, u16 addr, u16 value)
1553 {
1554         struct efx_nic *efx = netdev_priv(net_dev);
1555         struct falcon_nic_data *nic_data = efx->nic_data;
1556         efx_oword_t reg;
1557         int rc;
1558
1559         netif_vdbg(efx, hw, efx->net_dev,
1560                    "writing MDIO %d register %d.%d with 0x%04x\n",
1561                     prtad, devad, addr, value);
1562
1563         mutex_lock(&nic_data->mdio_lock);
1564
1565         /* Check MDIO not currently being accessed */
1566         rc = falcon_gmii_wait(efx);
1567         if (rc)
1568                 goto out;
1569
1570         /* Write the address/ID register */
1571         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
1572         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
1573
1574         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
1575                              FRF_AB_MD_DEV_ADR, devad);
1576         efx_writeo(efx, &reg, FR_AB_MD_ID);
1577
1578         /* Write data */
1579         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
1580         efx_writeo(efx, &reg, FR_AB_MD_TXD);
1581
1582         EFX_POPULATE_OWORD_2(reg,
1583                              FRF_AB_MD_WRC, 1,
1584                              FRF_AB_MD_GC, 0);
1585         efx_writeo(efx, &reg, FR_AB_MD_CS);
1586
1587         /* Wait for data to be written */
1588         rc = falcon_gmii_wait(efx);
1589         if (rc) {
1590                 /* Abort the write operation */
1591                 EFX_POPULATE_OWORD_2(reg,
1592                                      FRF_AB_MD_WRC, 0,
1593                                      FRF_AB_MD_GC, 1);
1594                 efx_writeo(efx, &reg, FR_AB_MD_CS);
1595                 udelay(10);
1596         }
1597
1598 out:
1599         mutex_unlock(&nic_data->mdio_lock);
1600         return rc;
1601 }
1602
1603 /* Read an MDIO register of a PHY connected to Falcon. */
1604 static int falcon_mdio_read(struct net_device *net_dev,
1605                             int prtad, int devad, u16 addr)
1606 {
1607         struct efx_nic *efx = netdev_priv(net_dev);
1608         struct falcon_nic_data *nic_data = efx->nic_data;
1609         efx_oword_t reg;
1610         int rc;
1611
1612         mutex_lock(&nic_data->mdio_lock);
1613
1614         /* Check MDIO not currently being accessed */
1615         rc = falcon_gmii_wait(efx);
1616         if (rc)
1617                 goto out;
1618
1619         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
1620         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
1621
1622         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
1623                              FRF_AB_MD_DEV_ADR, devad);
1624         efx_writeo(efx, &reg, FR_AB_MD_ID);
1625
1626         /* Request data to be read */
1627         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
1628         efx_writeo(efx, &reg, FR_AB_MD_CS);
1629
1630         /* Wait for data to become available */
1631         rc = falcon_gmii_wait(efx);
1632         if (rc == 0) {
1633                 efx_reado(efx, &reg, FR_AB_MD_RXD);
1634                 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
1635                 netif_vdbg(efx, hw, efx->net_dev,
1636                            "read from MDIO %d register %d.%d, got %04x\n",
1637                            prtad, devad, addr, rc);
1638         } else {
1639                 /* Abort the read operation */
1640                 EFX_POPULATE_OWORD_2(reg,
1641                                      FRF_AB_MD_RIC, 0,
1642                                      FRF_AB_MD_GC, 1);
1643                 efx_writeo(efx, &reg, FR_AB_MD_CS);
1644
1645                 netif_dbg(efx, hw, efx->net_dev,
1646                           "read from MDIO %d register %d.%d, got error %d\n",
1647                           prtad, devad, addr, rc);
1648         }
1649
1650 out:
1651         mutex_unlock(&nic_data->mdio_lock);
1652         return rc;
1653 }
1654
1655 /* This call is responsible for hooking in the MAC and PHY operations */
1656 static int falcon_probe_port(struct efx_nic *efx)
1657 {
1658         struct falcon_nic_data *nic_data = efx->nic_data;
1659         int rc;
1660
1661         switch (efx->phy_type) {
1662         case PHY_TYPE_SFX7101:
1663                 efx->phy_op = &falcon_sfx7101_phy_ops;
1664                 break;
1665         case PHY_TYPE_QT2022C2:
1666         case PHY_TYPE_QT2025C:
1667                 efx->phy_op = &falcon_qt202x_phy_ops;
1668                 break;
1669         case PHY_TYPE_TXC43128:
1670                 efx->phy_op = &falcon_txc_phy_ops;
1671                 break;
1672         default:
1673                 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
1674                           efx->phy_type);
1675                 return -ENODEV;
1676         }
1677
1678         /* Fill out MDIO structure and loopback modes */
1679         mutex_init(&nic_data->mdio_lock);
1680         efx->mdio.mdio_read = falcon_mdio_read;
1681         efx->mdio.mdio_write = falcon_mdio_write;
1682         rc = efx->phy_op->probe(efx);
1683         if (rc != 0)
1684                 return rc;
1685
1686         /* Initial assumption */
1687         efx->link_state.speed = 10000;
1688         efx->link_state.fd = true;
1689
1690         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
1691         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1692                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
1693         else
1694                 efx->wanted_fc = EFX_FC_RX;
1695         if (efx->mdio.mmds & MDIO_DEVS_AN)
1696                 efx->wanted_fc |= EFX_FC_AUTO;
1697
1698         /* Allocate buffer for stats */
1699         rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
1700                                   FALCON_MAC_STATS_SIZE, GFP_KERNEL);
1701         if (rc)
1702                 return rc;
1703         netif_dbg(efx, probe, efx->net_dev,
1704                   "stats buffer at %llx (virt %p phys %llx)\n",
1705                   (u64)efx->stats_buffer.dma_addr,
1706                   efx->stats_buffer.addr,
1707                   (u64)virt_to_phys(efx->stats_buffer.addr));
1708
1709         return 0;
1710 }
1711
1712 static void falcon_remove_port(struct efx_nic *efx)
1713 {
1714         efx->phy_op->remove(efx);
1715         efx_nic_free_buffer(efx, &efx->stats_buffer);
1716 }
1717
1718 /* Global events are basically PHY events */
1719 static bool
1720 falcon_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
1721 {
1722         struct efx_nic *efx = channel->efx;
1723         struct falcon_nic_data *nic_data = efx->nic_data;
1724
1725         if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
1726             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
1727             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR))
1728                 /* Ignored */
1729                 return true;
1730
1731         if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) &&
1732             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
1733                 nic_data->xmac_poll_required = true;
1734                 return true;
1735         }
1736
1737         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
1738             EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
1739             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
1740                 netif_err(efx, rx_err, efx->net_dev,
1741                           "channel %d seen global RX_RESET event. Resetting.\n",
1742                           channel->channel);
1743
1744                 atomic_inc(&efx->rx_reset);
1745                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
1746                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
1747                 return true;
1748         }
1749
1750         return false;
1751 }
1752
1753 /**************************************************************************
1754  *
1755  * Falcon test code
1756  *
1757  **************************************************************************/
1758
1759 static int
1760 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
1761 {
1762         struct falcon_nic_data *nic_data = efx->nic_data;
1763         struct falcon_nvconfig *nvconfig;
1764         struct falcon_spi_device *spi;
1765         void *region;
1766         int rc, magic_num, struct_ver;
1767         __le16 *word, *limit;
1768         u32 csum;
1769
1770         if (falcon_spi_present(&nic_data->spi_flash))
1771                 spi = &nic_data->spi_flash;
1772         else if (falcon_spi_present(&nic_data->spi_eeprom))
1773                 spi = &nic_data->spi_eeprom;
1774         else
1775                 return -EINVAL;
1776
1777         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
1778         if (!region)
1779                 return -ENOMEM;
1780         nvconfig = region + FALCON_NVCONFIG_OFFSET;
1781
1782         mutex_lock(&nic_data->spi_lock);
1783         rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
1784         mutex_unlock(&nic_data->spi_lock);
1785         if (rc) {
1786                 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
1787                           falcon_spi_present(&nic_data->spi_flash) ?
1788                           "flash" : "EEPROM");
1789                 rc = -EIO;
1790                 goto out;
1791         }
1792
1793         magic_num = le16_to_cpu(nvconfig->board_magic_num);
1794         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
1795
1796         rc = -EINVAL;
1797         if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
1798                 netif_err(efx, hw, efx->net_dev,
1799                           "NVRAM bad magic 0x%x\n", magic_num);
1800                 goto out;
1801         }
1802         if (struct_ver < 2) {
1803                 netif_err(efx, hw, efx->net_dev,
1804                           "NVRAM has ancient version 0x%x\n", struct_ver);
1805                 goto out;
1806         } else if (struct_ver < 4) {
1807                 word = &nvconfig->board_magic_num;
1808                 limit = (__le16 *) (nvconfig + 1);
1809         } else {
1810                 word = region;
1811                 limit = region + FALCON_NVCONFIG_END;
1812         }
1813         for (csum = 0; word < limit; ++word)
1814                 csum += le16_to_cpu(*word);
1815
1816         if (~csum & 0xffff) {
1817                 netif_err(efx, hw, efx->net_dev,
1818                           "NVRAM has incorrect checksum\n");
1819                 goto out;
1820         }
1821
1822         rc = 0;
1823         if (nvconfig_out)
1824                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
1825
1826  out:
1827         kfree(region);
1828         return rc;
1829 }
1830
1831 static int falcon_test_nvram(struct efx_nic *efx)
1832 {
1833         return falcon_read_nvram(efx, NULL);
1834 }
1835
1836 static const struct efx_farch_register_test falcon_b0_register_tests[] = {
1837         { FR_AZ_ADR_REGION,
1838           EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1839         { FR_AZ_RX_CFG,
1840           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1841         { FR_AZ_TX_CFG,
1842           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1843         { FR_AZ_TX_RESERVED,
1844           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1845         { FR_AB_MAC_CTRL,
1846           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1847         { FR_AZ_SRM_TX_DC_CFG,
1848           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1849         { FR_AZ_RX_DC_CFG,
1850           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1851         { FR_AZ_RX_DC_PF_WM,
1852           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1853         { FR_BZ_DP_CTRL,
1854           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1855         { FR_AB_GM_CFG2,
1856           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1857         { FR_AB_GMF_CFG0,
1858           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1859         { FR_AB_XM_GLB_CFG,
1860           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1861         { FR_AB_XM_TX_CFG,
1862           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1863         { FR_AB_XM_RX_CFG,
1864           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1865         { FR_AB_XM_RX_PARAM,
1866           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1867         { FR_AB_XM_FC,
1868           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1869         { FR_AB_XM_ADR_LO,
1870           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1871         { FR_AB_XX_SD_CTL,
1872           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1873 };
1874
1875 static int
1876 falcon_b0_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
1877 {
1878         enum reset_type reset_method = RESET_TYPE_INVISIBLE;
1879         int rc, rc2;
1880
1881         mutex_lock(&efx->mac_lock);
1882         if (efx->loopback_modes) {
1883                 /* We need the 312 clock from the PHY to test the XMAC
1884                  * registers, so move into XGMII loopback if available */
1885                 if (efx->loopback_modes & (1 << LOOPBACK_XGMII))
1886                         efx->loopback_mode = LOOPBACK_XGMII;
1887                 else
1888                         efx->loopback_mode = __ffs(efx->loopback_modes);
1889         }
1890         __efx_reconfigure_port(efx);
1891         mutex_unlock(&efx->mac_lock);
1892
1893         efx_reset_down(efx, reset_method);
1894
1895         tests->registers =
1896                 efx_farch_test_registers(efx, falcon_b0_register_tests,
1897                                          ARRAY_SIZE(falcon_b0_register_tests))
1898                 ? -1 : 1;
1899
1900         rc = falcon_reset_hw(efx, reset_method);
1901         rc2 = efx_reset_up(efx, reset_method, rc == 0);
1902         return rc ? rc : rc2;
1903 }
1904
1905 /**************************************************************************
1906  *
1907  * Device reset
1908  *
1909  **************************************************************************
1910  */
1911
1912 static enum reset_type falcon_map_reset_reason(enum reset_type reason)
1913 {
1914         switch (reason) {
1915         case RESET_TYPE_RX_RECOVERY:
1916         case RESET_TYPE_DMA_ERROR:
1917         case RESET_TYPE_TX_SKIP:
1918                 /* These can occasionally occur due to hardware bugs.
1919                  * We try to reset without disrupting the link.
1920                  */
1921                 return RESET_TYPE_INVISIBLE;
1922         default:
1923                 return RESET_TYPE_ALL;
1924         }
1925 }
1926
1927 static int falcon_map_reset_flags(u32 *flags)
1928 {
1929         enum {
1930                 FALCON_RESET_INVISIBLE = (ETH_RESET_DMA | ETH_RESET_FILTER |
1931                                           ETH_RESET_OFFLOAD | ETH_RESET_MAC),
1932                 FALCON_RESET_ALL = FALCON_RESET_INVISIBLE | ETH_RESET_PHY,
1933                 FALCON_RESET_WORLD = FALCON_RESET_ALL | ETH_RESET_IRQ,
1934         };
1935
1936         if ((*flags & FALCON_RESET_WORLD) == FALCON_RESET_WORLD) {
1937                 *flags &= ~FALCON_RESET_WORLD;
1938                 return RESET_TYPE_WORLD;
1939         }
1940
1941         if ((*flags & FALCON_RESET_ALL) == FALCON_RESET_ALL) {
1942                 *flags &= ~FALCON_RESET_ALL;
1943                 return RESET_TYPE_ALL;
1944         }
1945
1946         if ((*flags & FALCON_RESET_INVISIBLE) == FALCON_RESET_INVISIBLE) {
1947                 *flags &= ~FALCON_RESET_INVISIBLE;
1948                 return RESET_TYPE_INVISIBLE;
1949         }
1950
1951         return -EINVAL;
1952 }
1953
1954 /* Resets NIC to known state.  This routine must be called in process
1955  * context and is allowed to sleep. */
1956 static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1957 {
1958         struct falcon_nic_data *nic_data = efx->nic_data;
1959         efx_oword_t glb_ctl_reg_ker;
1960         int rc;
1961
1962         netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
1963                   RESET_TYPE(method));
1964
1965         /* Initiate device reset */
1966         if (method == RESET_TYPE_WORLD) {
1967                 rc = pci_save_state(efx->pci_dev);
1968                 if (rc) {
1969                         netif_err(efx, drv, efx->net_dev,
1970                                   "failed to backup PCI state of primary "
1971                                   "function prior to hardware reset\n");
1972                         goto fail1;
1973                 }
1974                 if (efx_nic_is_dual_func(efx)) {
1975                         rc = pci_save_state(nic_data->pci_dev2);
1976                         if (rc) {
1977                                 netif_err(efx, drv, efx->net_dev,
1978                                           "failed to backup PCI state of "
1979                                           "secondary function prior to "
1980                                           "hardware reset\n");
1981                                 goto fail2;
1982                         }
1983                 }
1984
1985                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1986                                      FRF_AB_EXT_PHY_RST_DUR,
1987                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
1988                                      FRF_AB_SWRST, 1);
1989         } else {
1990                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1991                                      /* exclude PHY from "invisible" reset */
1992                                      FRF_AB_EXT_PHY_RST_CTL,
1993                                      method == RESET_TYPE_INVISIBLE,
1994                                      /* exclude EEPROM/flash and PCIe */
1995                                      FRF_AB_PCIE_CORE_RST_CTL, 1,
1996                                      FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1997                                      FRF_AB_PCIE_SD_RST_CTL, 1,
1998                                      FRF_AB_EE_RST_CTL, 1,
1999                                      FRF_AB_EXT_PHY_RST_DUR,
2000                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
2001                                      FRF_AB_SWRST, 1);
2002         }
2003         efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2004
2005         netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
2006         schedule_timeout_uninterruptible(HZ / 20);
2007
2008         /* Restore PCI configuration if needed */
2009         if (method == RESET_TYPE_WORLD) {
2010                 if (efx_nic_is_dual_func(efx))
2011                         pci_restore_state(nic_data->pci_dev2);
2012                 pci_restore_state(efx->pci_dev);
2013                 netif_dbg(efx, drv, efx->net_dev,
2014                           "successfully restored PCI config\n");
2015         }
2016
2017         /* Assert that reset complete */
2018         efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2019         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2020                 rc = -ETIMEDOUT;
2021                 netif_err(efx, hw, efx->net_dev,
2022                           "timed out waiting for hardware reset\n");
2023                 goto fail3;
2024         }
2025         netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
2026
2027         return 0;
2028
2029         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2030 fail2:
2031         pci_restore_state(efx->pci_dev);
2032 fail1:
2033 fail3:
2034         return rc;
2035 }
2036
2037 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2038 {
2039         struct falcon_nic_data *nic_data = efx->nic_data;
2040         int rc;
2041
2042         mutex_lock(&nic_data->spi_lock);
2043         rc = __falcon_reset_hw(efx, method);
2044         mutex_unlock(&nic_data->spi_lock);
2045
2046         return rc;
2047 }
2048
2049 static void falcon_monitor(struct efx_nic *efx)
2050 {
2051         bool link_changed;
2052         int rc;
2053
2054         BUG_ON(!mutex_is_locked(&efx->mac_lock));
2055
2056         rc = falcon_board(efx)->type->monitor(efx);
2057         if (rc) {
2058                 netif_err(efx, hw, efx->net_dev,
2059                           "Board sensor %s; shutting down PHY\n",
2060                           (rc == -ERANGE) ? "reported fault" : "failed");
2061                 efx->phy_mode |= PHY_MODE_LOW_POWER;
2062                 rc = __efx_reconfigure_port(efx);
2063                 WARN_ON(rc);
2064         }
2065
2066         if (LOOPBACK_INTERNAL(efx))
2067                 link_changed = falcon_loopback_link_poll(efx);
2068         else
2069                 link_changed = efx->phy_op->poll(efx);
2070
2071         if (link_changed) {
2072                 falcon_stop_nic_stats(efx);
2073                 falcon_deconfigure_mac_wrapper(efx);
2074
2075                 falcon_reset_macs(efx);
2076                 rc = falcon_reconfigure_xmac(efx);
2077                 BUG_ON(rc);
2078
2079                 falcon_start_nic_stats(efx);
2080
2081                 efx_link_status_changed(efx);
2082         }
2083
2084         falcon_poll_xmac(efx);
2085 }
2086
2087 /* Zeroes out the SRAM contents.  This routine must be called in
2088  * process context and is allowed to sleep.
2089  */
2090 static int falcon_reset_sram(struct efx_nic *efx)
2091 {
2092         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2093         int count;
2094
2095         /* Set the SRAM wake/sleep GPIO appropriately. */
2096         efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2097         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2098         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2099         efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2100
2101         /* Initiate SRAM reset */
2102         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2103                              FRF_AZ_SRM_INIT_EN, 1,
2104                              FRF_AZ_SRM_NB_SZ, 0);
2105         efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2106
2107         /* Wait for SRAM reset to complete */
2108         count = 0;
2109         do {
2110                 netif_dbg(efx, hw, efx->net_dev,
2111                           "waiting for SRAM reset (attempt %d)...\n", count);
2112
2113                 /* SRAM reset is slow; expect around 16ms */
2114                 schedule_timeout_uninterruptible(HZ / 50);
2115
2116                 /* Check for reset complete */
2117                 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2118                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2119                         netif_dbg(efx, hw, efx->net_dev,
2120                                   "SRAM reset complete\n");
2121
2122                         return 0;
2123                 }
2124         } while (++count < 20); /* wait up to 0.4 sec */
2125
2126         netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
2127         return -ETIMEDOUT;
2128 }
2129
2130 static void falcon_spi_device_init(struct efx_nic *efx,
2131                                   struct falcon_spi_device *spi_device,
2132                                   unsigned int device_id, u32 device_type)
2133 {
2134         if (device_type != 0) {
2135                 spi_device->device_id = device_id;
2136                 spi_device->size =
2137                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2138                 spi_device->addr_len =
2139                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2140                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2141                                              spi_device->addr_len == 1);
2142                 spi_device->erase_command =
2143                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2144                 spi_device->erase_size =
2145                         1 << SPI_DEV_TYPE_FIELD(device_type,
2146                                                 SPI_DEV_TYPE_ERASE_SIZE);
2147                 spi_device->block_size =
2148                         1 << SPI_DEV_TYPE_FIELD(device_type,
2149                                                 SPI_DEV_TYPE_BLOCK_SIZE);
2150         } else {
2151                 spi_device->size = 0;
2152         }
2153 }
2154
2155 /* Extract non-volatile configuration */
2156 static int falcon_probe_nvconfig(struct efx_nic *efx)
2157 {
2158         struct falcon_nic_data *nic_data = efx->nic_data;
2159         struct falcon_nvconfig *nvconfig;
2160         int rc;
2161
2162         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2163         if (!nvconfig)
2164                 return -ENOMEM;
2165
2166         rc = falcon_read_nvram(efx, nvconfig);
2167         if (rc)
2168                 goto out;
2169
2170         efx->phy_type = nvconfig->board_v2.port0_phy_type;
2171         efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr;
2172
2173         if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2174                 falcon_spi_device_init(
2175                         efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2176                         le32_to_cpu(nvconfig->board_v3
2177                                     .spi_device_type[FFE_AB_SPI_DEVICE_FLASH]));
2178                 falcon_spi_device_init(
2179                         efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2180                         le32_to_cpu(nvconfig->board_v3
2181                                     .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM]));
2182         }
2183
2184         /* Read the MAC addresses */
2185         memcpy(efx->net_dev->perm_addr, nvconfig->mac_address[0], ETH_ALEN);
2186
2187         netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
2188                   efx->phy_type, efx->mdio.prtad);
2189
2190         rc = falcon_probe_board(efx,
2191                                 le16_to_cpu(nvconfig->board_v2.board_revision));
2192 out:
2193         kfree(nvconfig);
2194         return rc;
2195 }
2196
2197 static int falcon_dimension_resources(struct efx_nic *efx)
2198 {
2199         efx->rx_dc_base = 0x20000;
2200         efx->tx_dc_base = 0x26000;
2201         return 0;
2202 }
2203
2204 /* Probe all SPI devices on the NIC */
2205 static void falcon_probe_spi_devices(struct efx_nic *efx)
2206 {
2207         struct falcon_nic_data *nic_data = efx->nic_data;
2208         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2209         int boot_dev;
2210
2211         efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2212         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2213         efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2214
2215         if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2216                 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2217                             FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2218                 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
2219                           boot_dev == FFE_AB_SPI_DEVICE_FLASH ?
2220                           "flash" : "EEPROM");
2221         } else {
2222                 /* Disable VPD and set clock dividers to safe
2223                  * values for initial programming. */
2224                 boot_dev = -1;
2225                 netif_dbg(efx, probe, efx->net_dev,
2226                           "Booted from internal ASIC settings;"
2227                           " setting SPI config\n");
2228                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2229                                      /* 125 MHz / 7 ~= 20 MHz */
2230                                      FRF_AB_EE_SF_CLOCK_DIV, 7,
2231                                      /* 125 MHz / 63 ~= 2 MHz */
2232                                      FRF_AB_EE_EE_CLOCK_DIV, 63);
2233                 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2234         }
2235
2236         mutex_init(&nic_data->spi_lock);
2237
2238         if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2239                 falcon_spi_device_init(efx, &nic_data->spi_flash,
2240                                        FFE_AB_SPI_DEVICE_FLASH,
2241                                        default_flash_type);
2242         if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2243                 falcon_spi_device_init(efx, &nic_data->spi_eeprom,
2244                                        FFE_AB_SPI_DEVICE_EEPROM,
2245                                        large_eeprom_type);
2246 }
2247
2248 static unsigned int falcon_a1_mem_map_size(struct efx_nic *efx)
2249 {
2250         return 0x20000;
2251 }
2252
2253 static unsigned int falcon_b0_mem_map_size(struct efx_nic *efx)
2254 {
2255         /* Map everything up to and including the RSS indirection table.
2256          * The PCI core takes care of mapping the MSI-X tables.
2257          */
2258         return FR_BZ_RX_INDIRECTION_TBL +
2259                 FR_BZ_RX_INDIRECTION_TBL_STEP * FR_BZ_RX_INDIRECTION_TBL_ROWS;
2260 }
2261
2262 static int falcon_probe_nic(struct efx_nic *efx)
2263 {
2264         struct falcon_nic_data *nic_data;
2265         struct falcon_board *board;
2266         int rc;
2267
2268         efx->primary = efx; /* only one usable function per controller */
2269
2270         /* Allocate storage for hardware specific data */
2271         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2272         if (!nic_data)
2273                 return -ENOMEM;
2274         efx->nic_data = nic_data;
2275
2276         rc = -ENODEV;
2277
2278         if (efx_farch_fpga_ver(efx) != 0) {
2279                 netif_err(efx, probe, efx->net_dev,
2280                           "Falcon FPGA not supported\n");
2281                 goto fail1;
2282         }
2283
2284         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2285                 efx_oword_t nic_stat;
2286                 struct pci_dev *dev;
2287                 u8 pci_rev = efx->pci_dev->revision;
2288
2289                 if ((pci_rev == 0xff) || (pci_rev == 0)) {
2290                         netif_err(efx, probe, efx->net_dev,
2291                                   "Falcon rev A0 not supported\n");
2292                         goto fail1;
2293                 }
2294                 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2295                 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
2296                         netif_err(efx, probe, efx->net_dev,
2297                                   "Falcon rev A1 1G not supported\n");
2298                         goto fail1;
2299                 }
2300                 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2301                         netif_err(efx, probe, efx->net_dev,
2302                                   "Falcon rev A1 PCI-X not supported\n");
2303                         goto fail1;
2304                 }
2305
2306                 dev = pci_dev_get(efx->pci_dev);
2307                 while ((dev = pci_get_device(PCI_VENDOR_ID_SOLARFLARE,
2308                                              PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1,
2309                                              dev))) {
2310                         if (dev->bus == efx->pci_dev->bus &&
2311                             dev->devfn == efx->pci_dev->devfn + 1) {
2312                                 nic_data->pci_dev2 = dev;
2313                                 break;
2314                         }
2315                 }
2316                 if (!nic_data->pci_dev2) {
2317                         netif_err(efx, probe, efx->net_dev,
2318                                   "failed to find secondary function\n");
2319                         rc = -ENODEV;
2320                         goto fail2;
2321                 }
2322         }
2323
2324         /* Now we can reset the NIC */
2325         rc = __falcon_reset_hw(efx, RESET_TYPE_ALL);
2326         if (rc) {
2327                 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
2328                 goto fail3;
2329         }
2330
2331         /* Allocate memory for INT_KER */
2332         rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
2333                                   GFP_KERNEL);
2334         if (rc)
2335                 goto fail4;
2336         BUG_ON(efx->irq_status.dma_addr & 0x0f);
2337
2338         netif_dbg(efx, probe, efx->net_dev,
2339                   "INT_KER at %llx (virt %p phys %llx)\n",
2340                   (u64)efx->irq_status.dma_addr,
2341                   efx->irq_status.addr,
2342                   (u64)virt_to_phys(efx->irq_status.addr));
2343
2344         falcon_probe_spi_devices(efx);
2345
2346         /* Read in the non-volatile configuration */
2347         rc = falcon_probe_nvconfig(efx);
2348         if (rc) {
2349                 if (rc == -EINVAL)
2350                         netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n");
2351                 goto fail5;
2352         }
2353
2354         efx->max_channels = (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ? 4 :
2355                              EFX_MAX_CHANNELS);
2356         efx->timer_quantum_ns = 4968; /* 621 cycles */
2357
2358         /* Initialise I2C adapter */
2359         board = falcon_board(efx);
2360         board->i2c_adap.owner = THIS_MODULE;
2361         board->i2c_data = falcon_i2c_bit_operations;
2362         board->i2c_data.data = efx;
2363         board->i2c_adap.algo_data = &board->i2c_data;
2364         board->i2c_adap.dev.parent = &efx->pci_dev->dev;
2365         strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
2366                 sizeof(board->i2c_adap.name));
2367         rc = i2c_bit_add_bus(&board->i2c_adap);
2368         if (rc)
2369                 goto fail5;
2370
2371         rc = falcon_board(efx)->type->init(efx);
2372         if (rc) {
2373                 netif_err(efx, probe, efx->net_dev,
2374                           "failed to initialise board\n");
2375                 goto fail6;
2376         }
2377
2378         nic_data->stats_disable_count = 1;
2379         setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
2380                     (unsigned long)efx);
2381
2382         return 0;
2383
2384  fail6:
2385         i2c_del_adapter(&board->i2c_adap);
2386         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2387  fail5:
2388         efx_nic_free_buffer(efx, &efx->irq_status);
2389  fail4:
2390  fail3:
2391         if (nic_data->pci_dev2) {
2392                 pci_dev_put(nic_data->pci_dev2);
2393                 nic_data->pci_dev2 = NULL;
2394         }
2395  fail2:
2396  fail1:
2397         kfree(efx->nic_data);
2398         return rc;
2399 }
2400
2401 static void falcon_init_rx_cfg(struct efx_nic *efx)
2402 {
2403         /* RX control FIFO thresholds (32 entries) */
2404         const unsigned ctrl_xon_thr = 20;
2405         const unsigned ctrl_xoff_thr = 25;
2406         efx_oword_t reg;
2407
2408         efx_reado(efx, &reg, FR_AZ_RX_CFG);
2409         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
2410                 /* Data FIFO size is 5.5K.  The RX DMA engine only
2411                  * supports scattering for user-mode queues, but will
2412                  * split DMA writes at intervals of RX_USR_BUF_SIZE
2413                  * (32-byte units) even for kernel-mode queues.  We
2414                  * set it to be so large that that never happens.
2415                  */
2416                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2417                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2418                                     (3 * 4096) >> 5);
2419                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8);
2420                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8);
2421                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2422                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2423         } else {
2424                 /* Data FIFO size is 80K; register fields moved */
2425                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2426                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2427                                     EFX_RX_USR_BUF_SIZE >> 5);
2428                 /* Send XON and XOFF at ~3 * max MTU away from empty/full */
2429                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8);
2430                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8);
2431                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2432                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2433                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2434
2435                 /* Enable hash insertion. This is broken for the
2436                  * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
2437                  * IPv4 hashes. */
2438                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);
2439                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1);
2440                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1);
2441         }
2442         /* Always enable XOFF signal from RX FIFO.  We enable
2443          * or disable transmission of pause frames at the MAC. */
2444         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
2445         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2446 }
2447
2448 /* This call performs hardware-specific global initialisation, such as
2449  * defining the descriptor cache sizes and number of RSS channels.
2450  * It does not set up any buffers, descriptor rings or event queues.
2451  */
2452 static int falcon_init_nic(struct efx_nic *efx)
2453 {
2454         efx_oword_t temp;
2455         int rc;
2456
2457         /* Use on-chip SRAM */
2458         efx_reado(efx, &temp, FR_AB_NIC_STAT);
2459         EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2460         efx_writeo(efx, &temp, FR_AB_NIC_STAT);
2461
2462         rc = falcon_reset_sram(efx);
2463         if (rc)
2464                 return rc;
2465
2466         /* Clear the parity enables on the TX data fifos as
2467          * they produce false parity errors because of timing issues
2468          */
2469         if (EFX_WORKAROUND_5129(efx)) {
2470                 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
2471                 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
2472                 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
2473         }
2474
2475         if (EFX_WORKAROUND_7244(efx)) {
2476                 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
2477                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
2478                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
2479                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
2480                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
2481                 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
2482         }
2483
2484         /* XXX This is documented only for Falcon A0/A1 */
2485         /* Setup RX.  Wait for descriptor is broken and must
2486          * be disabled.  RXDP recovery shouldn't be needed, but is.
2487          */
2488         efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
2489         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
2490         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
2491         if (EFX_WORKAROUND_5583(efx))
2492                 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
2493         efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
2494
2495         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2496          * descriptors (which is bad).
2497          */
2498         efx_reado(efx, &temp, FR_AZ_TX_CFG);
2499         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
2500         efx_writeo(efx, &temp, FR_AZ_TX_CFG);
2501
2502         falcon_init_rx_cfg(efx);
2503
2504         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
2505                 falcon_b0_rx_push_rss_config(efx);
2506
2507                 /* Set destination of both TX and RX Flush events */
2508                 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
2509                 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
2510         }
2511
2512         efx_farch_init_common(efx);
2513
2514         return 0;
2515 }
2516
2517 static void falcon_remove_nic(struct efx_nic *efx)
2518 {
2519         struct falcon_nic_data *nic_data = efx->nic_data;
2520         struct falcon_board *board = falcon_board(efx);
2521
2522         board->type->fini(efx);
2523
2524         /* Remove I2C adapter and clear it in preparation for a retry */
2525         i2c_del_adapter(&board->i2c_adap);
2526         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2527
2528         efx_nic_free_buffer(efx, &efx->irq_status);
2529
2530         __falcon_reset_hw(efx, RESET_TYPE_ALL);
2531
2532         /* Release the second function after the reset */
2533         if (nic_data->pci_dev2) {
2534                 pci_dev_put(nic_data->pci_dev2);
2535                 nic_data->pci_dev2 = NULL;
2536         }
2537
2538         /* Tear down the private nic state */
2539         kfree(efx->nic_data);
2540         efx->nic_data = NULL;
2541 }
2542
2543 static size_t falcon_describe_nic_stats(struct efx_nic *efx, u8 *names)
2544 {
2545         return efx_nic_describe_stats(falcon_stat_desc, FALCON_STAT_COUNT,
2546                                       falcon_stat_mask, names);
2547 }
2548
2549 static size_t falcon_update_nic_stats(struct efx_nic *efx, u64 *full_stats,
2550                                       struct rtnl_link_stats64 *core_stats)
2551 {
2552         struct falcon_nic_data *nic_data = efx->nic_data;
2553         u64 *stats = nic_data->stats;
2554         efx_oword_t cnt;
2555
2556         if (!nic_data->stats_disable_count) {
2557                 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
2558                 stats[FALCON_STAT_rx_nodesc_drop_cnt] +=
2559                         EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
2560
2561                 if (nic_data->stats_pending &&
2562                     FALCON_XMAC_STATS_DMA_FLAG(efx)) {
2563                         nic_data->stats_pending = false;
2564                         rmb(); /* read the done flag before the stats */
2565                         efx_nic_update_stats(
2566                                 falcon_stat_desc, FALCON_STAT_COUNT,
2567                                 falcon_stat_mask,
2568                                 stats, efx->stats_buffer.addr, true);
2569                 }
2570
2571                 /* Update derived statistic */
2572                 efx_update_diff_stat(&stats[FALCON_STAT_rx_bad_bytes],
2573                                      stats[FALCON_STAT_rx_bytes] -
2574                                      stats[FALCON_STAT_rx_good_bytes] -
2575                                      stats[FALCON_STAT_rx_control] * 64);
2576         }
2577
2578         if (full_stats)
2579                 memcpy(full_stats, stats, sizeof(u64) * FALCON_STAT_COUNT);
2580
2581         if (core_stats) {
2582                 core_stats->rx_packets = stats[FALCON_STAT_rx_packets];
2583                 core_stats->tx_packets = stats[FALCON_STAT_tx_packets];
2584                 core_stats->rx_bytes = stats[FALCON_STAT_rx_bytes];
2585                 core_stats->tx_bytes = stats[FALCON_STAT_tx_bytes];
2586                 core_stats->rx_dropped = stats[FALCON_STAT_rx_nodesc_drop_cnt];
2587                 core_stats->multicast = stats[FALCON_STAT_rx_multicast];
2588                 core_stats->rx_length_errors =
2589                         stats[FALCON_STAT_rx_gtjumbo] +
2590                         stats[FALCON_STAT_rx_length_error];
2591                 core_stats->rx_crc_errors = stats[FALCON_STAT_rx_bad];
2592                 core_stats->rx_frame_errors = stats[FALCON_STAT_rx_align_error];
2593                 core_stats->rx_fifo_errors = stats[FALCON_STAT_rx_overflow];
2594
2595                 core_stats->rx_errors = (core_stats->rx_length_errors +
2596                                          core_stats->rx_crc_errors +
2597                                          core_stats->rx_frame_errors +
2598                                          stats[FALCON_STAT_rx_symbol_error]);
2599         }
2600
2601         return FALCON_STAT_COUNT;
2602 }
2603
2604 void falcon_start_nic_stats(struct efx_nic *efx)
2605 {
2606         struct falcon_nic_data *nic_data = efx->nic_data;
2607
2608         spin_lock_bh(&efx->stats_lock);
2609         if (--nic_data->stats_disable_count == 0)
2610                 falcon_stats_request(efx);
2611         spin_unlock_bh(&efx->stats_lock);
2612 }
2613
2614 /* We don't acutally pull stats on falcon. Wait 10ms so that
2615  * they arrive when we call this just after start_stats
2616  */
2617 static void falcon_pull_nic_stats(struct efx_nic *efx)
2618 {
2619         msleep(10);
2620 }
2621
2622 void falcon_stop_nic_stats(struct efx_nic *efx)
2623 {
2624         struct falcon_nic_data *nic_data = efx->nic_data;
2625         int i;
2626
2627         might_sleep();
2628
2629         spin_lock_bh(&efx->stats_lock);
2630         ++nic_data->stats_disable_count;
2631         spin_unlock_bh(&efx->stats_lock);
2632
2633         del_timer_sync(&nic_data->stats_timer);
2634
2635         /* Wait enough time for the most recent transfer to
2636          * complete. */
2637         for (i = 0; i < 4 && nic_data->stats_pending; i++) {
2638                 if (FALCON_XMAC_STATS_DMA_FLAG(efx))
2639                         break;
2640                 msleep(1);
2641         }
2642
2643         spin_lock_bh(&efx->stats_lock);
2644         falcon_stats_complete(efx);
2645         spin_unlock_bh(&efx->stats_lock);
2646 }
2647
2648 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
2649 {
2650         falcon_board(efx)->type->set_id_led(efx, mode);
2651 }
2652
2653 /**************************************************************************
2654  *
2655  * Wake on LAN
2656  *
2657  **************************************************************************
2658  */
2659
2660 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
2661 {
2662         wol->supported = 0;
2663         wol->wolopts = 0;
2664         memset(&wol->sopass, 0, sizeof(wol->sopass));
2665 }
2666
2667 static int falcon_set_wol(struct efx_nic *efx, u32 type)
2668 {
2669         if (type != 0)
2670                 return -EINVAL;
2671         return 0;
2672 }
2673
2674 /**************************************************************************
2675  *
2676  * Revision-dependent attributes used by efx.c and nic.c
2677  *
2678  **************************************************************************
2679  */
2680
2681 const struct efx_nic_type falcon_a1_nic_type = {
2682         .mem_map_size = falcon_a1_mem_map_size,
2683         .probe = falcon_probe_nic,
2684         .remove = falcon_remove_nic,
2685         .init = falcon_init_nic,
2686         .dimension_resources = falcon_dimension_resources,
2687         .fini = falcon_irq_ack_a1,
2688         .monitor = falcon_monitor,
2689         .map_reset_reason = falcon_map_reset_reason,
2690         .map_reset_flags = falcon_map_reset_flags,
2691         .reset = falcon_reset_hw,
2692         .probe_port = falcon_probe_port,
2693         .remove_port = falcon_remove_port,
2694         .handle_global_event = falcon_handle_global_event,
2695         .fini_dmaq = efx_farch_fini_dmaq,
2696         .prepare_flush = falcon_prepare_flush,
2697         .finish_flush = efx_port_dummy_op_void,
2698         .describe_stats = falcon_describe_nic_stats,
2699         .update_stats = falcon_update_nic_stats,
2700         .start_stats = falcon_start_nic_stats,
2701         .pull_stats = falcon_pull_nic_stats,
2702         .stop_stats = falcon_stop_nic_stats,
2703         .set_id_led = falcon_set_id_led,
2704         .push_irq_moderation = falcon_push_irq_moderation,
2705         .reconfigure_port = falcon_reconfigure_port,
2706         .prepare_enable_fc_tx = falcon_a1_prepare_enable_fc_tx,
2707         .reconfigure_mac = falcon_reconfigure_xmac,
2708         .check_mac_fault = falcon_xmac_check_fault,
2709         .get_wol = falcon_get_wol,
2710         .set_wol = falcon_set_wol,
2711         .resume_wol = efx_port_dummy_op_void,
2712         .test_nvram = falcon_test_nvram,
2713         .irq_enable_master = efx_farch_irq_enable_master,
2714         .irq_test_generate = efx_farch_irq_test_generate,
2715         .irq_disable_non_ev = efx_farch_irq_disable_master,
2716         .irq_handle_msi = efx_farch_msi_interrupt,
2717         .irq_handle_legacy = falcon_legacy_interrupt_a1,
2718         .tx_probe = efx_farch_tx_probe,
2719         .tx_init = efx_farch_tx_init,
2720         .tx_remove = efx_farch_tx_remove,
2721         .tx_write = efx_farch_tx_write,
2722         .rx_push_rss_config = efx_port_dummy_op_void,
2723         .rx_probe = efx_farch_rx_probe,
2724         .rx_init = efx_farch_rx_init,
2725         .rx_remove = efx_farch_rx_remove,
2726         .rx_write = efx_farch_rx_write,
2727         .rx_defer_refill = efx_farch_rx_defer_refill,
2728         .ev_probe = efx_farch_ev_probe,
2729         .ev_init = efx_farch_ev_init,
2730         .ev_fini = efx_farch_ev_fini,
2731         .ev_remove = efx_farch_ev_remove,
2732         .ev_process = efx_farch_ev_process,
2733         .ev_read_ack = efx_farch_ev_read_ack,
2734         .ev_test_generate = efx_farch_ev_test_generate,
2735
2736         /* We don't expose the filter table on Falcon A1 as it is not
2737          * mapped into function 0, but these implementations still
2738          * work with a degenerate case of all tables set to size 0.
2739          */
2740         .filter_table_probe = efx_farch_filter_table_probe,
2741         .filter_table_restore = efx_farch_filter_table_restore,
2742         .filter_table_remove = efx_farch_filter_table_remove,
2743         .filter_insert = efx_farch_filter_insert,
2744         .filter_remove_safe = efx_farch_filter_remove_safe,
2745         .filter_get_safe = efx_farch_filter_get_safe,
2746         .filter_clear_rx = efx_farch_filter_clear_rx,
2747         .filter_count_rx_used = efx_farch_filter_count_rx_used,
2748         .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
2749         .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
2750
2751 #ifdef CONFIG_SFC_MTD
2752         .mtd_probe = falcon_mtd_probe,
2753         .mtd_rename = falcon_mtd_rename,
2754         .mtd_read = falcon_mtd_read,
2755         .mtd_erase = falcon_mtd_erase,
2756         .mtd_write = falcon_mtd_write,
2757         .mtd_sync = falcon_mtd_sync,
2758 #endif
2759
2760         .revision = EFX_REV_FALCON_A1,
2761         .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
2762         .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
2763         .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
2764         .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
2765         .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
2766         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
2767         .rx_buffer_padding = 0x24,
2768         .can_rx_scatter = false,
2769         .max_interrupt_mode = EFX_INT_MODE_MSI,
2770         .timer_period_max =  1 << FRF_AB_TC_TIMER_VAL_WIDTH,
2771         .offload_features = NETIF_F_IP_CSUM,
2772         .mcdi_max_ver = -1,
2773 };
2774
2775 const struct efx_nic_type falcon_b0_nic_type = {
2776         .mem_map_size = falcon_b0_mem_map_size,
2777         .probe = falcon_probe_nic,
2778         .remove = falcon_remove_nic,
2779         .init = falcon_init_nic,
2780         .dimension_resources = falcon_dimension_resources,
2781         .fini = efx_port_dummy_op_void,
2782         .monitor = falcon_monitor,
2783         .map_reset_reason = falcon_map_reset_reason,
2784         .map_reset_flags = falcon_map_reset_flags,
2785         .reset = falcon_reset_hw,
2786         .probe_port = falcon_probe_port,
2787         .remove_port = falcon_remove_port,
2788         .handle_global_event = falcon_handle_global_event,
2789         .fini_dmaq = efx_farch_fini_dmaq,
2790         .prepare_flush = falcon_prepare_flush,
2791         .finish_flush = efx_port_dummy_op_void,
2792         .describe_stats = falcon_describe_nic_stats,
2793         .update_stats = falcon_update_nic_stats,
2794         .start_stats = falcon_start_nic_stats,
2795         .pull_stats = falcon_pull_nic_stats,
2796         .stop_stats = falcon_stop_nic_stats,
2797         .set_id_led = falcon_set_id_led,
2798         .push_irq_moderation = falcon_push_irq_moderation,
2799         .reconfigure_port = falcon_reconfigure_port,
2800         .prepare_enable_fc_tx = falcon_b0_prepare_enable_fc_tx,
2801         .reconfigure_mac = falcon_reconfigure_xmac,
2802         .check_mac_fault = falcon_xmac_check_fault,
2803         .get_wol = falcon_get_wol,
2804         .set_wol = falcon_set_wol,
2805         .resume_wol = efx_port_dummy_op_void,
2806         .test_chip = falcon_b0_test_chip,
2807         .test_nvram = falcon_test_nvram,
2808         .irq_enable_master = efx_farch_irq_enable_master,
2809         .irq_test_generate = efx_farch_irq_test_generate,
2810         .irq_disable_non_ev = efx_farch_irq_disable_master,
2811         .irq_handle_msi = efx_farch_msi_interrupt,
2812         .irq_handle_legacy = efx_farch_legacy_interrupt,
2813         .tx_probe = efx_farch_tx_probe,
2814         .tx_init = efx_farch_tx_init,
2815         .tx_remove = efx_farch_tx_remove,
2816         .tx_write = efx_farch_tx_write,
2817         .rx_push_rss_config = falcon_b0_rx_push_rss_config,
2818         .rx_probe = efx_farch_rx_probe,
2819         .rx_init = efx_farch_rx_init,
2820         .rx_remove = efx_farch_rx_remove,
2821         .rx_write = efx_farch_rx_write,
2822         .rx_defer_refill = efx_farch_rx_defer_refill,
2823         .ev_probe = efx_farch_ev_probe,
2824         .ev_init = efx_farch_ev_init,
2825         .ev_fini = efx_farch_ev_fini,
2826         .ev_remove = efx_farch_ev_remove,
2827         .ev_process = efx_farch_ev_process,
2828         .ev_read_ack = efx_farch_ev_read_ack,
2829         .ev_test_generate = efx_farch_ev_test_generate,
2830         .filter_table_probe = efx_farch_filter_table_probe,
2831         .filter_table_restore = efx_farch_filter_table_restore,
2832         .filter_table_remove = efx_farch_filter_table_remove,
2833         .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
2834         .filter_insert = efx_farch_filter_insert,
2835         .filter_remove_safe = efx_farch_filter_remove_safe,
2836         .filter_get_safe = efx_farch_filter_get_safe,
2837         .filter_clear_rx = efx_farch_filter_clear_rx,
2838         .filter_count_rx_used = efx_farch_filter_count_rx_used,
2839         .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
2840         .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
2841 #ifdef CONFIG_RFS_ACCEL
2842         .filter_rfs_insert = efx_farch_filter_rfs_insert,
2843         .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
2844 #endif
2845 #ifdef CONFIG_SFC_MTD
2846         .mtd_probe = falcon_mtd_probe,
2847         .mtd_rename = falcon_mtd_rename,
2848         .mtd_read = falcon_mtd_read,
2849         .mtd_erase = falcon_mtd_erase,
2850         .mtd_write = falcon_mtd_write,
2851         .mtd_sync = falcon_mtd_sync,
2852 #endif
2853
2854         .revision = EFX_REV_FALCON_B0,
2855         .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
2856         .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
2857         .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
2858         .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
2859         .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
2860         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
2861         .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE,
2862         .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST,
2863         .rx_buffer_padding = 0,
2864         .can_rx_scatter = true,
2865         .max_interrupt_mode = EFX_INT_MODE_MSIX,
2866         .timer_period_max =  1 << FRF_AB_TC_TIMER_VAL_WIDTH,
2867         .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE,
2868         .mcdi_max_ver = -1,
2869         .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
2870 };
2871