drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48
  49 #ifdef RTL8169_DEBUG
  50 #define assert(expr) \
  51         if (!(expr)) {                                  \
  52                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  53                 #expr,__FILE__,__func__,__LINE__);              \
  54         }
  55 #define dprintk(fmt, args...) \
  56         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  57 #else
  58 #define assert(expr) do {} while (0)
  59 #define dprintk(fmt, args...)   do {} while (0)
  60 #endif /* RTL8169_DEBUG */
  61
  62 #define R8169_MSG_DEFAULT \
  63         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  64
  65 #define TX_SLOTS_AVAIL(tp) \
  66         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  67
  68 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  69 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  70         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  71
  72 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  73    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  74 static const int multicast_filter_limit = 32;
  75
  76 /* MAC address length */
  77 #define MAC_ADDR_LEN    6
  78
  79 #define MAX_READ_REQUEST_SHIFT  12
  80 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  81 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  82 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  83
  84 #define R8169_REGS_SIZE         256
  85 #define R8169_NAPI_WEIGHT       64
  86 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  87 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  88 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  89 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  90 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  91
  92 #define RTL8169_TX_TIMEOUT      (6*HZ)
  93 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  94
  95 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  96 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  97 #define RTL_EEPROM_SIG_ADDR     0x0000
  98
  99 /* write/read MMIO register */
 100 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 101 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 102 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 103 #define RTL_R8(reg)             readb (ioaddr + (reg))
 104 #define RTL_R16(reg)            readw (ioaddr + (reg))
 105 #define RTL_R32(reg)            readl (ioaddr + (reg))
 106
 107 enum mac_version {
 108         RTL_GIGA_MAC_VER_01 = 0,
 109         RTL_GIGA_MAC_VER_02,
 110         RTL_GIGA_MAC_VER_03,
 111         RTL_GIGA_MAC_VER_04,
 112         RTL_GIGA_MAC_VER_05,
 113         RTL_GIGA_MAC_VER_06,
 114         RTL_GIGA_MAC_VER_07,
 115         RTL_GIGA_MAC_VER_08,
 116         RTL_GIGA_MAC_VER_09,
 117         RTL_GIGA_MAC_VER_10,
 118         RTL_GIGA_MAC_VER_11,
 119         RTL_GIGA_MAC_VER_12,
 120         RTL_GIGA_MAC_VER_13,
 121         RTL_GIGA_MAC_VER_14,
 122         RTL_GIGA_MAC_VER_15,
 123         RTL_GIGA_MAC_VER_16,
 124         RTL_GIGA_MAC_VER_17,
 125         RTL_GIGA_MAC_VER_18,
 126         RTL_GIGA_MAC_VER_19,
 127         RTL_GIGA_MAC_VER_20,
 128         RTL_GIGA_MAC_VER_21,
 129         RTL_GIGA_MAC_VER_22,
 130         RTL_GIGA_MAC_VER_23,
 131         RTL_GIGA_MAC_VER_24,
 132         RTL_GIGA_MAC_VER_25,
 133         RTL_GIGA_MAC_VER_26,
 134         RTL_GIGA_MAC_VER_27,
 135         RTL_GIGA_MAC_VER_28,
 136         RTL_GIGA_MAC_VER_29,
 137         RTL_GIGA_MAC_VER_30,
 138         RTL_GIGA_MAC_VER_31,
 139         RTL_GIGA_MAC_VER_32,
 140         RTL_GIGA_MAC_VER_33,
 141         RTL_GIGA_MAC_VER_34,
 142         RTL_GIGA_MAC_VER_35,
 143         RTL_GIGA_MAC_VER_36,
 144         RTL_GIGA_MAC_NONE   = 0xff,
 145 };
 146
 147 enum rtl_tx_desc_version {
 148         RTL_TD_0        = 0,
 149         RTL_TD_1        = 1,
 150 };
 151
 152 #define JUMBO_1K        ETH_DATA_LEN
 153 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 154 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 155 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 156 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 157
 158 #define _R(NAME,TD,FW,SZ,B) {   \
 159         .name = NAME,           \
 160         .txd_version = TD,      \
 161         .fw_name = FW,          \
 162         .jumbo_max = SZ,        \
 163         .jumbo_tx_csum = B      \
 164 }
 165
 166 static const struct {
 167         const char *name;
 168         enum rtl_tx_desc_version txd_version;
 169         const char *fw_name;
 170         u16 jumbo_max;
 171         bool jumbo_tx_csum;
 172 } rtl_chip_infos[] = {
 173         /* PCI devices. */
 174         [RTL_GIGA_MAC_VER_01] =
 175                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 176         [RTL_GIGA_MAC_VER_02] =
 177                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 178         [RTL_GIGA_MAC_VER_03] =
 179                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 180         [RTL_GIGA_MAC_VER_04] =
 181                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 182         [RTL_GIGA_MAC_VER_05] =
 183                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 184         [RTL_GIGA_MAC_VER_06] =
 185                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 186         /* PCI-E devices. */
 187         [RTL_GIGA_MAC_VER_07] =
 188                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 189         [RTL_GIGA_MAC_VER_08] =
 190                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 191         [RTL_GIGA_MAC_VER_09] =
 192                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 193         [RTL_GIGA_MAC_VER_10] =
 194                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 195         [RTL_GIGA_MAC_VER_11] =
 196                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 197         [RTL_GIGA_MAC_VER_12] =
 198                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 199         [RTL_GIGA_MAC_VER_13] =
 200                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 201         [RTL_GIGA_MAC_VER_14] =
 202                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 203         [RTL_GIGA_MAC_VER_15] =
 204                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 205         [RTL_GIGA_MAC_VER_16] =
 206                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 207         [RTL_GIGA_MAC_VER_17] =
 208                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 209         [RTL_GIGA_MAC_VER_18] =
 210                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 211         [RTL_GIGA_MAC_VER_19] =
 212                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 213         [RTL_GIGA_MAC_VER_20] =
 214                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 215         [RTL_GIGA_MAC_VER_21] =
 216                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 217         [RTL_GIGA_MAC_VER_22] =
 218                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 219         [RTL_GIGA_MAC_VER_23] =
 220                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 221         [RTL_GIGA_MAC_VER_24] =
 222                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 223         [RTL_GIGA_MAC_VER_25] =
 224                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 225                                                         JUMBO_9K, false),
 226         [RTL_GIGA_MAC_VER_26] =
 227                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 228                                                         JUMBO_9K, false),
 229         [RTL_GIGA_MAC_VER_27] =
 230                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 231         [RTL_GIGA_MAC_VER_28] =
 232                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 233         [RTL_GIGA_MAC_VER_29] =
 234                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 235                                                         JUMBO_1K, true),
 236         [RTL_GIGA_MAC_VER_30] =
 237                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 238                                                         JUMBO_1K, true),
 239         [RTL_GIGA_MAC_VER_31] =
 240                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 241         [RTL_GIGA_MAC_VER_32] =
 242                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 243                                                         JUMBO_9K, false),
 244         [RTL_GIGA_MAC_VER_33] =
 245                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 246                                                         JUMBO_9K, false),
 247         [RTL_GIGA_MAC_VER_34] =
 248                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 249                                                         JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_35] =
 251                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 252                                                         JUMBO_9K, false),
 253         [RTL_GIGA_MAC_VER_36] =
 254                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 255                                                         JUMBO_9K, false),
 256 };
 257 #undef _R
 258
 259 enum cfg_version {
 260         RTL_CFG_0 = 0x00,
 261         RTL_CFG_1,
 262         RTL_CFG_2
 263 };
 264
 265 static void rtl_hw_start_8169(struct net_device *);
 266 static void rtl_hw_start_8168(struct net_device *);
 267 static void rtl_hw_start_8101(struct net_device *);
 268
 269 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 270         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 271         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 272         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 273         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 274         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 275         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 276         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 277         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 278         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 279         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 280                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 281         { 0x0001,                               0x8168,
 282                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 283         {0,},
 284 };
 285
 286 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 287
 288 static int rx_buf_sz = 16383;
 289 static int use_dac;
 290 static struct {
 291         u32 msg_enable;
 292 } debug = { -1 };
 293
 294 enum rtl_registers {
 295         MAC0            = 0,    /* Ethernet hardware address. */
 296         MAC4            = 4,
 297         MAR0            = 8,    /* Multicast filter. */
 298         CounterAddrLow          = 0x10,
 299         CounterAddrHigh         = 0x14,
 300         TxDescStartAddrLow      = 0x20,
 301         TxDescStartAddrHigh     = 0x24,
 302         TxHDescStartAddrLow     = 0x28,
 303         TxHDescStartAddrHigh    = 0x2c,
 304         FLASH           = 0x30,
 305         ERSR            = 0x36,
 306         ChipCmd         = 0x37,
 307         TxPoll          = 0x38,
 308         IntrMask        = 0x3c,
 309         IntrStatus      = 0x3e,
 310
 311         TxConfig        = 0x40,
 312 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 313 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 314
 315         RxConfig        = 0x44,
 316 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 317 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 318 #define RXCFG_FIFO_SHIFT                13
 319                                         /* No threshold before first PCI xfer */
 320 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 321 #define RXCFG_DMA_SHIFT                 8
 322                                         /* Unlimited maximum PCI burst. */
 323 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 324
 325         RxMissed        = 0x4c,
 326         Cfg9346         = 0x50,
 327         Config0         = 0x51,
 328         Config1         = 0x52,
 329         Config2         = 0x53,
 330 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 331
 332         Config3         = 0x54,
 333         Config4         = 0x55,
 334         Config5         = 0x56,
 335         MultiIntr       = 0x5c,
 336         PHYAR           = 0x60,
 337         PHYstatus       = 0x6c,
 338         RxMaxSize       = 0xda,
 339         CPlusCmd        = 0xe0,
 340         IntrMitigate    = 0xe2,
 341         RxDescAddrLow   = 0xe4,
 342         RxDescAddrHigh  = 0xe8,
 343         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 344
 345 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 346
 347         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 348
 349 #define TxPacketMax     (8064 >> 7)
 350 #define EarlySize       0x27
 351
 352         FuncEvent       = 0xf0,
 353         FuncEventMask   = 0xf4,
 354         FuncPresetState = 0xf8,
 355         FuncForceEvent  = 0xfc,
 356 };
 357
 358 enum rtl8110_registers {
 359         TBICSR                  = 0x64,
 360         TBI_ANAR                = 0x68,
 361         TBI_LPAR                = 0x6a,
 362 };
 363
 364 enum rtl8168_8101_registers {
 365         CSIDR                   = 0x64,
 366         CSIAR                   = 0x68,
 367 #define CSIAR_FLAG                      0x80000000
 368 #define CSIAR_WRITE_CMD                 0x80000000
 369 #define CSIAR_BYTE_ENABLE               0x0f
 370 #define CSIAR_BYTE_ENABLE_SHIFT         12
 371 #define CSIAR_ADDR_MASK                 0x0fff
 372         PMCH                    = 0x6f,
 373         EPHYAR                  = 0x80,
 374 #define EPHYAR_FLAG                     0x80000000
 375 #define EPHYAR_WRITE_CMD                0x80000000
 376 #define EPHYAR_REG_MASK                 0x1f
 377 #define EPHYAR_REG_SHIFT                16
 378 #define EPHYAR_DATA_MASK                0xffff
 379         DLLPR                   = 0xd0,
 380 #define PFM_EN                          (1 << 6)
 381         DBG_REG                 = 0xd1,
 382 #define FIX_NAK_1                       (1 << 4)
 383 #define FIX_NAK_2                       (1 << 3)
 384         TWSI                    = 0xd2,
 385         MCU                     = 0xd3,
 386 #define NOW_IS_OOB                      (1 << 7)
 387 #define EN_NDP                          (1 << 3)
 388 #define EN_OOB_RESET                    (1 << 2)
 389         EFUSEAR                 = 0xdc,
 390 #define EFUSEAR_FLAG                    0x80000000
 391 #define EFUSEAR_WRITE_CMD               0x80000000
 392 #define EFUSEAR_READ_CMD                0x00000000
 393 #define EFUSEAR_REG_MASK                0x03ff
 394 #define EFUSEAR_REG_SHIFT               8
 395 #define EFUSEAR_DATA_MASK               0xff
 396 };
 397
 398 enum rtl8168_registers {
 399         LED_FREQ                = 0x1a,
 400         EEE_LED                 = 0x1b,
 401         ERIDR                   = 0x70,
 402         ERIAR                   = 0x74,
 403 #define ERIAR_FLAG                      0x80000000
 404 #define ERIAR_WRITE_CMD                 0x80000000
 405 #define ERIAR_READ_CMD                  0x00000000
 406 #define ERIAR_ADDR_BYTE_ALIGN           4
 407 #define ERIAR_TYPE_SHIFT                16
 408 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 409 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 410 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 411 #define ERIAR_MASK_SHIFT                12
 412 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 413 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 414 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 415         EPHY_RXER_NUM           = 0x7c,
 416         OCPDR                   = 0xb0, /* OCP GPHY access */
 417 #define OCPDR_WRITE_CMD                 0x80000000
 418 #define OCPDR_READ_CMD                  0x00000000
 419 #define OCPDR_REG_MASK                  0x7f
 420 #define OCPDR_GPHY_REG_SHIFT            16
 421 #define OCPDR_DATA_MASK                 0xffff
 422         OCPAR                   = 0xb4,
 423 #define OCPAR_FLAG                      0x80000000
 424 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 425 #define OCPAR_GPHY_READ_CMD             0x0000f060
 426         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 427         MISC                    = 0xf0, /* 8168e only. */
 428 #define TXPLA_RST                       (1 << 29)
 429 #define PWM_EN                          (1 << 22)
 430 };
 431
 432 enum rtl_register_content {
 433         /* InterruptStatusBits */
 434         SYSErr          = 0x8000,
 435         PCSTimeout      = 0x4000,
 436         SWInt           = 0x0100,
 437         TxDescUnavail   = 0x0080,
 438         RxFIFOOver      = 0x0040,
 439         LinkChg         = 0x0020,
 440         RxOverflow      = 0x0010,
 441         TxErr           = 0x0008,
 442         TxOK            = 0x0004,
 443         RxErr           = 0x0002,
 444         RxOK            = 0x0001,
 445
 446         /* RxStatusDesc */
 447         RxBOVF  = (1 << 24),
 448         RxFOVF  = (1 << 23),
 449         RxRWT   = (1 << 22),
 450         RxRES   = (1 << 21),
 451         RxRUNT  = (1 << 20),
 452         RxCRC   = (1 << 19),
 453
 454         /* ChipCmdBits */
 455         StopReq         = 0x80,
 456         CmdReset        = 0x10,
 457         CmdRxEnb        = 0x08,
 458         CmdTxEnb        = 0x04,
 459         RxBufEmpty      = 0x01,
 460
 461         /* TXPoll register p.5 */
 462         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 463         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 464         FSWInt          = 0x01,         /* Forced software interrupt */
 465
 466         /* Cfg9346Bits */
 467         Cfg9346_Lock    = 0x00,
 468         Cfg9346_Unlock  = 0xc0,
 469
 470         /* rx_mode_bits */
 471         AcceptErr       = 0x20,
 472         AcceptRunt      = 0x10,
 473         AcceptBroadcast = 0x08,
 474         AcceptMulticast = 0x04,
 475         AcceptMyPhys    = 0x02,
 476         AcceptAllPhys   = 0x01,
 477 #define RX_CONFIG_ACCEPT_MASK           0x3f
 478
 479         /* TxConfigBits */
 480         TxInterFrameGapShift = 24,
 481         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 482
 483         /* Config1 register p.24 */
 484         LEDS1           = (1 << 7),
 485         LEDS0           = (1 << 6),
 486         Speed_down      = (1 << 4),
 487         MEMMAP          = (1 << 3),
 488         IOMAP           = (1 << 2),
 489         VPD             = (1 << 1),
 490         PMEnable        = (1 << 0),     /* Power Management Enable */
 491
 492         /* Config2 register p. 25 */
 493         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 494         PCI_Clock_66MHz = 0x01,
 495         PCI_Clock_33MHz = 0x00,
 496
 497         /* Config3 register p.25 */
 498         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 499         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 500         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 501         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 502
 503         /* Config4 register */
 504         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 505
 506         /* Config5 register p.27 */
 507         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 508         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 509         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 510         Spi_en          = (1 << 3),
 511         LanWake         = (1 << 1),     /* LanWake enable/disable */
 512         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 513
 514         /* TBICSR p.28 */
 515         TBIReset        = 0x80000000,
 516         TBILoopback     = 0x40000000,
 517         TBINwEnable     = 0x20000000,
 518         TBINwRestart    = 0x10000000,
 519         TBILinkOk       = 0x02000000,
 520         TBINwComplete   = 0x01000000,
 521
 522         /* CPlusCmd p.31 */
 523         EnableBist      = (1 << 15),    // 8168 8101
 524         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 525         Normal_mode     = (1 << 13),    // unused
 526         Force_half_dup  = (1 << 12),    // 8168 8101
 527         Force_rxflow_en = (1 << 11),    // 8168 8101
 528         Force_txflow_en = (1 << 10),    // 8168 8101
 529         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 530         ASF             = (1 << 8),     // 8168 8101
 531         PktCntrDisable  = (1 << 7),     // 8168 8101
 532         Mac_dbgo_sel    = 0x001c,       // 8168
 533         RxVlan          = (1 << 6),
 534         RxChkSum        = (1 << 5),
 535         PCIDAC          = (1 << 4),
 536         PCIMulRW        = (1 << 3),
 537         INTT_0          = 0x0000,       // 8168
 538         INTT_1          = 0x0001,       // 8168
 539         INTT_2          = 0x0002,       // 8168
 540         INTT_3          = 0x0003,       // 8168
 541
 542         /* rtl8169_PHYstatus */
 543         TBI_Enable      = 0x80,
 544         TxFlowCtrl      = 0x40,
 545         RxFlowCtrl      = 0x20,
 546         _1000bpsF       = 0x10,
 547         _100bps         = 0x08,
 548         _10bps          = 0x04,
 549         LinkStatus      = 0x02,
 550         FullDup         = 0x01,
 551
 552         /* _TBICSRBit */
 553         TBILinkOK       = 0x02000000,
 554
 555         /* DumpCounterCommand */
 556         CounterDump     = 0x8,
 557 };
 558
 559 enum rtl_desc_bit {
 560         /* First doubleword. */
 561         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 562         RingEnd         = (1 << 30), /* End of descriptor ring */
 563         FirstFrag       = (1 << 29), /* First segment of a packet */
 564         LastFrag        = (1 << 28), /* Final segment of a packet */
 565 };
 566
 567 /* Generic case. */
 568 enum rtl_tx_desc_bit {
 569         /* First doubleword. */
 570         TD_LSO          = (1 << 27),            /* Large Send Offload */
 571 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 572
 573         /* Second doubleword. */
 574         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 575 };
 576
 577 /* 8169, 8168b and 810x except 8102e. */
 578 enum rtl_tx_desc_bit_0 {
 579         /* First doubleword. */
 580 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 581         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 582         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 583         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 584 };
 585
 586 /* 8102e, 8168c and beyond. */
 587 enum rtl_tx_desc_bit_1 {
 588         /* Second doubleword. */
 589 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 590         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 591         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 592         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 593 };
 594
 595 static const struct rtl_tx_desc_info {
 596         struct {
 597                 u32 udp;
 598                 u32 tcp;
 599         } checksum;
 600         u16 mss_shift;
 601         u16 opts_offset;
 602 } tx_desc_info [] = {
 603         [RTL_TD_0] = {
 604                 .checksum = {
 605                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 606                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 607                 },
 608                 .mss_shift      = TD0_MSS_SHIFT,
 609                 .opts_offset    = 0
 610         },
 611         [RTL_TD_1] = {
 612                 .checksum = {
 613                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 614                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 615                 },
 616                 .mss_shift      = TD1_MSS_SHIFT,
 617                 .opts_offset    = 1
 618         }
 619 };
 620
 621 enum rtl_rx_desc_bit {
 622         /* Rx private */
 623         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 624         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 625
 626 #define RxProtoUDP      (PID1)
 627 #define RxProtoTCP      (PID0)
 628 #define RxProtoIP       (PID1 | PID0)
 629 #define RxProtoMask     RxProtoIP
 630
 631         IPFail          = (1 << 16), /* IP checksum failed */
 632         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 633         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 634         RxVlanTag       = (1 << 16), /* VLAN tag available */
 635 };
 636
 637 #define RsvdMask        0x3fffc000
 638
 639 struct TxDesc {
 640         __le32 opts1;
 641         __le32 opts2;
 642         __le64 addr;
 643 };
 644
 645 struct RxDesc {
 646         __le32 opts1;
 647         __le32 opts2;
 648         __le64 addr;
 649 };
 650
 651 struct ring_info {
 652         struct sk_buff  *skb;
 653         u32             len;
 654         u8              __pad[sizeof(void *) - sizeof(u32)];
 655 };
 656
 657 enum features {
 658         RTL_FEATURE_WOL         = (1 << 0),
 659         RTL_FEATURE_MSI         = (1 << 1),
 660         RTL_FEATURE_GMII        = (1 << 2),
 661 };
 662
 663 struct rtl8169_counters {
 664         __le64  tx_packets;
 665         __le64  rx_packets;
 666         __le64  tx_errors;
 667         __le32  rx_errors;
 668         __le16  rx_missed;
 669         __le16  align_errors;
 670         __le32  tx_one_collision;
 671         __le32  tx_multi_collision;
 672         __le64  rx_unicast;
 673         __le64  rx_broadcast;
 674         __le32  rx_multicast;
 675         __le16  tx_aborted;
 676         __le16  tx_underun;
 677 };
 678
 679 struct rtl8169_private {
 680         void __iomem *mmio_addr;        /* memory map physical address */
 681         struct pci_dev *pci_dev;
 682         struct net_device *dev;
 683         struct napi_struct napi;
 684         spinlock_t lock;
 685         u32 msg_enable;
 686         u16 txd_version;
 687         u16 mac_version;
 688         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 689         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 690         u32 dirty_rx;
 691         u32 dirty_tx;
 692         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 693         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 694         dma_addr_t TxPhyAddr;
 695         dma_addr_t RxPhyAddr;
 696         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 697         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 698         struct timer_list timer;
 699         u16 cp_cmd;
 700         u16 intr_event;
 701         u16 napi_event;
 702         u16 intr_mask;
 703
 704         struct mdio_ops {
 705                 void (*write)(void __iomem *, int, int);
 706                 int (*read)(void __iomem *, int);
 707         } mdio_ops;
 708
 709         struct pll_power_ops {
 710                 void (*down)(struct rtl8169_private *);
 711                 void (*up)(struct rtl8169_private *);
 712         } pll_power_ops;
 713
 714         struct jumbo_ops {
 715                 void (*enable)(struct rtl8169_private *);
 716                 void (*disable)(struct rtl8169_private *);
 717         } jumbo_ops;
 718
 719         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 720         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 721         void (*phy_reset_enable)(struct rtl8169_private *tp);
 722         void (*hw_start)(struct net_device *);
 723         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 724         unsigned int (*link_ok)(void __iomem *);
 725         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 726         struct delayed_work task;
 727         unsigned features;
 728
 729         struct mii_if_info mii;
 730         struct rtl8169_counters counters;
 731         u32 saved_wolopts;
 732         u32 opts1_mask;
 733
 734         struct rtl_fw {
 735                 const struct firmware *fw;
 736
 737 #define RTL_VER_SIZE            32
 738
 739                 char version[RTL_VER_SIZE];
 740
 741                 struct rtl_fw_phy_action {
 742                         __le32 *code;
 743                         size_t size;
 744                 } phy_action;
 745         } *rtl_fw;
 746 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 747 };
 748
 749 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 750 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 751 module_param(use_dac, int, 0);
 752 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 753 module_param_named(debug, debug.msg_enable, int, 0);
 754 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 755 MODULE_LICENSE("GPL");
 756 MODULE_VERSION(RTL8169_VERSION);
 757 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 758 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 759 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 760 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 761 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 762 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 763 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 764 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 765
 766 static int rtl8169_open(struct net_device *dev);
 767 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 768                                       struct net_device *dev);
 769 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 770 static int rtl8169_init_ring(struct net_device *dev);
 771 static void rtl_hw_start(struct net_device *dev);
 772 static int rtl8169_close(struct net_device *dev);
 773 static void rtl_set_rx_mode(struct net_device *dev);
 774 static void rtl8169_tx_timeout(struct net_device *dev);
 775 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 776 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 777                                 void __iomem *, u32 budget);
 778 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 779 static void rtl8169_down(struct net_device *dev);
 780 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 781 static int rtl8169_poll(struct napi_struct *napi, int budget);
 782
 783 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 784 {
 785         int cap = pci_pcie_cap(pdev);
 786
 787         if (cap) {
 788                 u16 ctl;
 789
 790                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 791                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 792                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 793         }
 794 }
 795
 796 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 797 {
 798         void __iomem *ioaddr = tp->mmio_addr;
 799         int i;
 800
 801         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 802         for (i = 0; i < 20; i++) {
 803                 udelay(100);
 804                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 805                         break;
 806         }
 807         return RTL_R32(OCPDR);
 808 }
 809
 810 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 811 {
 812         void __iomem *ioaddr = tp->mmio_addr;
 813         int i;
 814
 815         RTL_W32(OCPDR, data);
 816         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 817         for (i = 0; i < 20; i++) {
 818                 udelay(100);
 819                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 820                         break;
 821         }
 822 }
 823
 824 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 825 {
 826         void __iomem *ioaddr = tp->mmio_addr;
 827         int i;
 828
 829         RTL_W8(ERIDR, cmd);
 830         RTL_W32(ERIAR, 0x800010e8);
 831         msleep(2);
 832         for (i = 0; i < 5; i++) {
 833                 udelay(100);
 834                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 835                         break;
 836         }
 837
 838         ocp_write(tp, 0x1, 0x30, 0x00000001);
 839 }
 840
 841 #define OOB_CMD_RESET           0x00
 842 #define OOB_CMD_DRIVER_START    0x05
 843 #define OOB_CMD_DRIVER_STOP     0x06
 844
 845 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 846 {
 847         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 848 }
 849
 850 static void rtl8168_driver_start(struct rtl8169_private *tp)
 851 {
 852         u16 reg;
 853         int i;
 854
 855         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 856
 857         reg = rtl8168_get_ocp_reg(tp);
 858
 859         for (i = 0; i < 10; i++) {
 860                 msleep(10);
 861                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 862                         break;
 863         }
 864 }
 865
 866 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 867 {
 868         u16 reg;
 869         int i;
 870
 871         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 872
 873         reg = rtl8168_get_ocp_reg(tp);
 874
 875         for (i = 0; i < 10; i++) {
 876                 msleep(10);
 877                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 878                         break;
 879         }
 880 }
 881
 882 static int r8168dp_check_dash(struct rtl8169_private *tp)
 883 {
 884         u16 reg = rtl8168_get_ocp_reg(tp);
 885
 886         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 887 }
 888
 889 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 890 {
 891         int i;
 892
 893         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 894
 895         for (i = 20; i > 0; i--) {
 896                 /*
 897                  * Check if the RTL8169 has completed writing to the specified
 898                  * MII register.
 899                  */
 900                 if (!(RTL_R32(PHYAR) & 0x80000000))
 901                         break;
 902                 udelay(25);
 903         }
 904         /*
 905          * According to hardware specs a 20us delay is required after write
 906          * complete indication, but before sending next command.
 907          */
 908         udelay(20);
 909 }
 910
 911 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 912 {
 913         int i, value = -1;
 914
 915         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 916
 917         for (i = 20; i > 0; i--) {
 918                 /*
 919                  * Check if the RTL8169 has completed retrieving data from
 920                  * the specified MII register.
 921                  */
 922                 if (RTL_R32(PHYAR) & 0x80000000) {
 923                         value = RTL_R32(PHYAR) & 0xffff;
 924                         break;
 925                 }
 926                 udelay(25);
 927         }
 928         /*
 929          * According to hardware specs a 20us delay is required after read
 930          * complete indication, but before sending next command.
 931          */
 932         udelay(20);
 933
 934         return value;
 935 }
 936
 937 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 938 {
 939         int i;
 940
 941         RTL_W32(OCPDR, data |
 942                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 943         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 944         RTL_W32(EPHY_RXER_NUM, 0);
 945
 946         for (i = 0; i < 100; i++) {
 947                 mdelay(1);
 948                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 949                         break;
 950         }
 951 }
 952
 953 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 954 {
 955         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 956                 (value & OCPDR_DATA_MASK));
 957 }
 958
 959 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 960 {
 961         int i;
 962
 963         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 964
 965         mdelay(1);
 966         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 967         RTL_W32(EPHY_RXER_NUM, 0);
 968
 969         for (i = 0; i < 100; i++) {
 970                 mdelay(1);
 971                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 972                         break;
 973         }
 974
 975         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 976 }
 977
 978 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 979
 980 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 981 {
 982         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 983 }
 984
 985 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 986 {
 987         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 988 }
 989
 990 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 991 {
 992         r8168dp_2_mdio_start(ioaddr);
 993
 994         r8169_mdio_write(ioaddr, reg_addr, value);
 995
 996         r8168dp_2_mdio_stop(ioaddr);
 997 }
 998
 999 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1000 {
1001         int value;
1002
1003         r8168dp_2_mdio_start(ioaddr);
1004
1005         value = r8169_mdio_read(ioaddr, reg_addr);
1006
1007         r8168dp_2_mdio_stop(ioaddr);
1008
1009         return value;
1010 }
1011
1012 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1013 {
1014         tp->mdio_ops.write(tp->mmio_addr, location, val);
1015 }
1016
1017 static int rtl_readphy(struct rtl8169_private *tp, int location)
1018 {
1019         return tp->mdio_ops.read(tp->mmio_addr, location);
1020 }
1021
1022 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1023 {
1024         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1025 }
1026
1027 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1028 {
1029         int val;
1030
1031         val = rtl_readphy(tp, reg_addr);
1032         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1033 }
1034
1035 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1036                            int val)
1037 {
1038         struct rtl8169_private *tp = netdev_priv(dev);
1039
1040         rtl_writephy(tp, location, val);
1041 }
1042
1043 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1044 {
1045         struct rtl8169_private *tp = netdev_priv(dev);
1046
1047         return rtl_readphy(tp, location);
1048 }
1049
1050 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1051 {
1052         unsigned int i;
1053
1054         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1055                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1056
1057         for (i = 0; i < 100; i++) {
1058                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1059                         break;
1060                 udelay(10);
1061         }
1062 }
1063
1064 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1065 {
1066         u16 value = 0xffff;
1067         unsigned int i;
1068
1069         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1070
1071         for (i = 0; i < 100; i++) {
1072                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1073                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1074                         break;
1075                 }
1076                 udelay(10);
1077         }
1078
1079         return value;
1080 }
1081
1082 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1083 {
1084         unsigned int i;
1085
1086         RTL_W32(CSIDR, value);
1087         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1088                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1089
1090         for (i = 0; i < 100; i++) {
1091                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1092                         break;
1093                 udelay(10);
1094         }
1095 }
1096
1097 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1098 {
1099         u32 value = ~0x00;
1100         unsigned int i;
1101
1102         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1103                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1104
1105         for (i = 0; i < 100; i++) {
1106                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1107                         value = RTL_R32(CSIDR);
1108                         break;
1109                 }
1110                 udelay(10);
1111         }
1112
1113         return value;
1114 }
1115
1116 static
1117 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1118 {
1119         unsigned int i;
1120
1121         BUG_ON((addr & 3) || (mask == 0));
1122         RTL_W32(ERIDR, val);
1123         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1124
1125         for (i = 0; i < 100; i++) {
1126                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1127                         break;
1128                 udelay(100);
1129         }
1130 }
1131
1132 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1133 {
1134         u32 value = ~0x00;
1135         unsigned int i;
1136
1137         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1138
1139         for (i = 0; i < 100; i++) {
1140                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1141                         value = RTL_R32(ERIDR);
1142                         break;
1143                 }
1144                 udelay(100);
1145         }
1146
1147         return value;
1148 }
1149
1150 static void
1151 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1152 {
1153         u32 val;
1154
1155         val = rtl_eri_read(ioaddr, addr, type);
1156         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1157 }
1158
1159 struct exgmac_reg {
1160         u16 addr;
1161         u16 mask;
1162         u32 val;
1163 };
1164
1165 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1166                                    const struct exgmac_reg *r, int len)
1167 {
1168         while (len-- > 0) {
1169                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1170                 r++;
1171         }
1172 }
1173
1174 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1175 {
1176         u8 value = 0xff;
1177         unsigned int i;
1178
1179         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1180
1181         for (i = 0; i < 300; i++) {
1182                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1183                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1184                         break;
1185                 }
1186                 udelay(100);
1187         }
1188
1189         return value;
1190 }
1191
1192 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1193 {
1194         void __iomem *ioaddr = tp->mmio_addr;
1195
1196         RTL_W16(IntrMask, 0x0000);
1197         RTL_W16(IntrStatus, tp->intr_event);
1198         RTL_R8(ChipCmd);
1199 }
1200
1201 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1202 {
1203         void __iomem *ioaddr = tp->mmio_addr;
1204
1205         return RTL_R32(TBICSR) & TBIReset;
1206 }
1207
1208 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1209 {
1210         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1211 }
1212
1213 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1214 {
1215         return RTL_R32(TBICSR) & TBILinkOk;
1216 }
1217
1218 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1219 {
1220         return RTL_R8(PHYstatus) & LinkStatus;
1221 }
1222
1223 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1224 {
1225         void __iomem *ioaddr = tp->mmio_addr;
1226
1227         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1228 }
1229
1230 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1231 {
1232         unsigned int val;
1233
1234         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1235         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1236 }
1237
1238 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1239 {
1240         void __iomem *ioaddr = tp->mmio_addr;
1241         struct net_device *dev = tp->dev;
1242
1243         if (!netif_running(dev))
1244                 return;
1245
1246         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1247                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1248                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1249                                       0x00000011, ERIAR_EXGMAC);
1250                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1251                                       0x00000005, ERIAR_EXGMAC);
1252                 } else if (RTL_R8(PHYstatus) & _100bps) {
1253                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1254                                       0x0000001f, ERIAR_EXGMAC);
1255                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1256                                       0x00000005, ERIAR_EXGMAC);
1257                 } else {
1258                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1259                                       0x0000001f, ERIAR_EXGMAC);
1260                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1261                                       0x0000003f, ERIAR_EXGMAC);
1262                 }
1263                 /* Reset packet filter */
1264                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1265                              ERIAR_EXGMAC);
1266                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1267                              ERIAR_EXGMAC);
1268         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1269                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1270                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1271                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1272                                       0x00000011, ERIAR_EXGMAC);
1273                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1274                                       0x00000005, ERIAR_EXGMAC);
1275                 } else {
1276                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1277                                       0x0000001f, ERIAR_EXGMAC);
1278                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1279                                       0x0000003f, ERIAR_EXGMAC);
1280                 }
1281         }
1282 }
1283
1284 static void __rtl8169_check_link_status(struct net_device *dev,
1285                                         struct rtl8169_private *tp,
1286                                         void __iomem *ioaddr, bool pm)
1287 {
1288         unsigned long flags;
1289
1290         spin_lock_irqsave(&tp->lock, flags);
1291         if (tp->link_ok(ioaddr)) {
1292                 rtl_link_chg_patch(tp);
1293                 /* This is to cancel a scheduled suspend if there's one. */
1294                 if (pm)
1295                         pm_request_resume(&tp->pci_dev->dev);
1296                 netif_carrier_on(dev);
1297                 if (net_ratelimit())
1298                         netif_info(tp, ifup, dev, "link up\n");
1299         } else {
1300                 netif_carrier_off(dev);
1301                 netif_info(tp, ifdown, dev, "link down\n");
1302                 if (pm)
1303                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1304         }
1305         spin_unlock_irqrestore(&tp->lock, flags);
1306 }
1307
1308 static void rtl8169_check_link_status(struct net_device *dev,
1309                                       struct rtl8169_private *tp,
1310                                       void __iomem *ioaddr)
1311 {
1312         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1313 }
1314
1315 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1316
1317 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1318 {
1319         void __iomem *ioaddr = tp->mmio_addr;
1320         u8 options;
1321         u32 wolopts = 0;
1322
1323         options = RTL_R8(Config1);
1324         if (!(options & PMEnable))
1325                 return 0;
1326
1327         options = RTL_R8(Config3);
1328         if (options & LinkUp)
1329                 wolopts |= WAKE_PHY;
1330         if (options & MagicPacket)
1331                 wolopts |= WAKE_MAGIC;
1332
1333         options = RTL_R8(Config5);
1334         if (options & UWF)
1335                 wolopts |= WAKE_UCAST;
1336         if (options & BWF)
1337                 wolopts |= WAKE_BCAST;
1338         if (options & MWF)
1339                 wolopts |= WAKE_MCAST;
1340
1341         return wolopts;
1342 }
1343
1344 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1345 {
1346         struct rtl8169_private *tp = netdev_priv(dev);
1347
1348         spin_lock_irq(&tp->lock);
1349
1350         wol->supported = WAKE_ANY;
1351         wol->wolopts = __rtl8169_get_wol(tp);
1352
1353         spin_unlock_irq(&tp->lock);
1354 }
1355
1356 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1357 {
1358         void __iomem *ioaddr = tp->mmio_addr;
1359         unsigned int i;
1360         static const struct {
1361                 u32 opt;
1362                 u16 reg;
1363                 u8  mask;
1364         } cfg[] = {
1365                 { WAKE_PHY,   Config3, LinkUp },
1366                 { WAKE_MAGIC, Config3, MagicPacket },
1367                 { WAKE_UCAST, Config5, UWF },
1368                 { WAKE_BCAST, Config5, BWF },
1369                 { WAKE_MCAST, Config5, MWF },
1370                 { WAKE_ANY,   Config5, LanWake }
1371         };
1372         u8 options;
1373
1374         RTL_W8(Cfg9346, Cfg9346_Unlock);
1375
1376         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1377                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1378                 if (wolopts & cfg[i].opt)
1379                         options |= cfg[i].mask;
1380                 RTL_W8(cfg[i].reg, options);
1381         }
1382
1383         switch (tp->mac_version) {
1384         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1385                 options = RTL_R8(Config1) & ~PMEnable;
1386                 if (wolopts)
1387                         options |= PMEnable;
1388                 RTL_W8(Config1, options);
1389                 break;
1390         default:
1391                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1392                 if (wolopts)
1393                         options |= PME_SIGNAL;
1394                 RTL_W8(Config2, options);
1395                 break;
1396         }
1397
1398         RTL_W8(Cfg9346, Cfg9346_Lock);
1399 }
1400
1401 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1402 {
1403         struct rtl8169_private *tp = netdev_priv(dev);
1404
1405         spin_lock_irq(&tp->lock);
1406
1407         if (wol->wolopts)
1408                 tp->features |= RTL_FEATURE_WOL;
1409         else
1410                 tp->features &= ~RTL_FEATURE_WOL;
1411         __rtl8169_set_wol(tp, wol->wolopts);
1412         spin_unlock_irq(&tp->lock);
1413
1414         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1415
1416         return 0;
1417 }
1418
1419 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1420 {
1421         return rtl_chip_infos[tp->mac_version].fw_name;
1422 }
1423
1424 static void rtl8169_get_drvinfo(struct net_device *dev,
1425                                 struct ethtool_drvinfo *info)
1426 {
1427         struct rtl8169_private *tp = netdev_priv(dev);
1428         struct rtl_fw *rtl_fw = tp->rtl_fw;
1429
1430         strcpy(info->driver, MODULENAME);
1431         strcpy(info->version, RTL8169_VERSION);
1432         strcpy(info->bus_info, pci_name(tp->pci_dev));
1433         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1434         strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1435                rtl_fw->version);
1436 }
1437
1438 static int rtl8169_get_regs_len(struct net_device *dev)
1439 {
1440         return R8169_REGS_SIZE;
1441 }
1442
1443 static int rtl8169_set_speed_tbi(struct net_device *dev,
1444                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1445 {
1446         struct rtl8169_private *tp = netdev_priv(dev);
1447         void __iomem *ioaddr = tp->mmio_addr;
1448         int ret = 0;
1449         u32 reg;
1450
1451         reg = RTL_R32(TBICSR);
1452         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1453             (duplex == DUPLEX_FULL)) {
1454                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1455         } else if (autoneg == AUTONEG_ENABLE)
1456                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1457         else {
1458                 netif_warn(tp, link, dev,
1459                            "incorrect speed setting refused in TBI mode\n");
1460                 ret = -EOPNOTSUPP;
1461         }
1462
1463         return ret;
1464 }
1465
1466 static int rtl8169_set_speed_xmii(struct net_device *dev,
1467                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1468 {
1469         struct rtl8169_private *tp = netdev_priv(dev);
1470         int giga_ctrl, bmcr;
1471         int rc = -EINVAL;
1472
1473         rtl_writephy(tp, 0x1f, 0x0000);
1474
1475         if (autoneg == AUTONEG_ENABLE) {
1476                 int auto_nego;
1477
1478                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1479                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1480                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1481
1482                 if (adv & ADVERTISED_10baseT_Half)
1483                         auto_nego |= ADVERTISE_10HALF;
1484                 if (adv & ADVERTISED_10baseT_Full)
1485                         auto_nego |= ADVERTISE_10FULL;
1486                 if (adv & ADVERTISED_100baseT_Half)
1487                         auto_nego |= ADVERTISE_100HALF;
1488                 if (adv & ADVERTISED_100baseT_Full)
1489                         auto_nego |= ADVERTISE_100FULL;
1490
1491                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1492
1493                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1494                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1495
1496                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1497                 if (tp->mii.supports_gmii) {
1498                         if (adv & ADVERTISED_1000baseT_Half)
1499                                 giga_ctrl |= ADVERTISE_1000HALF;
1500                         if (adv & ADVERTISED_1000baseT_Full)
1501                                 giga_ctrl |= ADVERTISE_1000FULL;
1502                 } else if (adv & (ADVERTISED_1000baseT_Half |
1503                                   ADVERTISED_1000baseT_Full)) {
1504                         netif_info(tp, link, dev,
1505                                    "PHY does not support 1000Mbps\n");
1506                         goto out;
1507                 }
1508
1509                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1510
1511                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1512                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1513         } else {
1514                 giga_ctrl = 0;
1515
1516                 if (speed == SPEED_10)
1517                         bmcr = 0;
1518                 else if (speed == SPEED_100)
1519                         bmcr = BMCR_SPEED100;
1520                 else
1521                         goto out;
1522
1523                 if (duplex == DUPLEX_FULL)
1524                         bmcr |= BMCR_FULLDPLX;
1525         }
1526
1527         rtl_writephy(tp, MII_BMCR, bmcr);
1528
1529         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1530             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1531                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1532                         rtl_writephy(tp, 0x17, 0x2138);
1533                         rtl_writephy(tp, 0x0e, 0x0260);
1534                 } else {
1535                         rtl_writephy(tp, 0x17, 0x2108);
1536                         rtl_writephy(tp, 0x0e, 0x0000);
1537                 }
1538         }
1539
1540         rc = 0;
1541 out:
1542         return rc;
1543 }
1544
1545 static int rtl8169_set_speed(struct net_device *dev,
1546                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1547 {
1548         struct rtl8169_private *tp = netdev_priv(dev);
1549         int ret;
1550
1551         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1552         if (ret < 0)
1553                 goto out;
1554
1555         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1556             (advertising & ADVERTISED_1000baseT_Full)) {
1557                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1558         }
1559 out:
1560         return ret;
1561 }
1562
1563 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1564 {
1565         struct rtl8169_private *tp = netdev_priv(dev);
1566         unsigned long flags;
1567         int ret;
1568
1569         del_timer_sync(&tp->timer);
1570
1571         spin_lock_irqsave(&tp->lock, flags);
1572         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1573                                 cmd->duplex, cmd->advertising);
1574         spin_unlock_irqrestore(&tp->lock, flags);
1575
1576         return ret;
1577 }
1578
1579 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1580 {
1581         struct rtl8169_private *tp = netdev_priv(dev);
1582
1583         if (dev->mtu > TD_MSS_MAX)
1584                 features &= ~NETIF_F_ALL_TSO;
1585
1586         if (dev->mtu > JUMBO_1K &&
1587             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1588                 features &= ~NETIF_F_IP_CSUM;
1589
1590         return features;
1591 }
1592
1593 static int rtl8169_set_features(struct net_device *dev, u32 features)
1594 {
1595         struct rtl8169_private *tp = netdev_priv(dev);
1596         void __iomem *ioaddr = tp->mmio_addr;
1597         unsigned long flags;
1598
1599         spin_lock_irqsave(&tp->lock, flags);
1600
1601         if (features & NETIF_F_RXCSUM)
1602                 tp->cp_cmd |= RxChkSum;
1603         else
1604                 tp->cp_cmd &= ~RxChkSum;
1605
1606         if (dev->features & NETIF_F_HW_VLAN_RX)
1607                 tp->cp_cmd |= RxVlan;
1608         else
1609                 tp->cp_cmd &= ~RxVlan;
1610
1611         RTL_W16(CPlusCmd, tp->cp_cmd);
1612         RTL_R16(CPlusCmd);
1613
1614         spin_unlock_irqrestore(&tp->lock, flags);
1615
1616         return 0;
1617 }
1618
1619 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1620                                       struct sk_buff *skb)
1621 {
1622         return (vlan_tx_tag_present(skb)) ?
1623                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1624 }
1625
1626 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1627 {
1628         u32 opts2 = le32_to_cpu(desc->opts2);
1629
1630         if (opts2 & RxVlanTag)
1631                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1632
1633         desc->opts2 = 0;
1634 }
1635
1636 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1637 {
1638         struct rtl8169_private *tp = netdev_priv(dev);
1639         void __iomem *ioaddr = tp->mmio_addr;
1640         u32 status;
1641
1642         cmd->supported =
1643                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1644         cmd->port = PORT_FIBRE;
1645         cmd->transceiver = XCVR_INTERNAL;
1646
1647         status = RTL_R32(TBICSR);
1648         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1649         cmd->autoneg = !!(status & TBINwEnable);
1650
1651         ethtool_cmd_speed_set(cmd, SPEED_1000);
1652         cmd->duplex = DUPLEX_FULL; /* Always set */
1653
1654         return 0;
1655 }
1656
1657 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1658 {
1659         struct rtl8169_private *tp = netdev_priv(dev);
1660
1661         return mii_ethtool_gset(&tp->mii, cmd);
1662 }
1663
1664 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1665 {
1666         struct rtl8169_private *tp = netdev_priv(dev);
1667         unsigned long flags;
1668         int rc;
1669
1670         spin_lock_irqsave(&tp->lock, flags);
1671
1672         rc = tp->get_settings(dev, cmd);
1673
1674         spin_unlock_irqrestore(&tp->lock, flags);
1675         return rc;
1676 }
1677
1678 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1679                              void *p)
1680 {
1681         struct rtl8169_private *tp = netdev_priv(dev);
1682         unsigned long flags;
1683
1684         if (regs->len > R8169_REGS_SIZE)
1685                 regs->len = R8169_REGS_SIZE;
1686
1687         spin_lock_irqsave(&tp->lock, flags);
1688         memcpy_fromio(p, tp->mmio_addr, regs->len);
1689         spin_unlock_irqrestore(&tp->lock, flags);
1690 }
1691
1692 static u32 rtl8169_get_msglevel(struct net_device *dev)
1693 {
1694         struct rtl8169_private *tp = netdev_priv(dev);
1695
1696         return tp->msg_enable;
1697 }
1698
1699 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1700 {
1701         struct rtl8169_private *tp = netdev_priv(dev);
1702
1703         tp->msg_enable = value;
1704 }
1705
1706 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1707         "tx_packets",
1708         "rx_packets",
1709         "tx_errors",
1710         "rx_errors",
1711         "rx_missed",
1712         "align_errors",
1713         "tx_single_collisions",
1714         "tx_multi_collisions",
1715         "unicast",
1716         "broadcast",
1717         "multicast",
1718         "tx_aborted",
1719         "tx_underrun",
1720 };
1721
1722 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1723 {
1724         switch (sset) {
1725         case ETH_SS_STATS:
1726                 return ARRAY_SIZE(rtl8169_gstrings);
1727         default:
1728                 return -EOPNOTSUPP;
1729         }
1730 }
1731
1732 static void rtl8169_update_counters(struct net_device *dev)
1733 {
1734         struct rtl8169_private *tp = netdev_priv(dev);
1735         void __iomem *ioaddr = tp->mmio_addr;
1736         struct device *d = &tp->pci_dev->dev;
1737         struct rtl8169_counters *counters;
1738         dma_addr_t paddr;
1739         u32 cmd;
1740         int wait = 1000;
1741
1742         /*
1743          * Some chips are unable to dump tally counters when the receiver
1744          * is disabled.
1745          */
1746         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1747                 return;
1748
1749         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1750         if (!counters)
1751                 return;
1752
1753         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1754         cmd = (u64)paddr & DMA_BIT_MASK(32);
1755         RTL_W32(CounterAddrLow, cmd);
1756         RTL_W32(CounterAddrLow, cmd | CounterDump);
1757
1758         while (wait--) {
1759                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1760                         memcpy(&tp->counters, counters, sizeof(*counters));
1761                         break;
1762                 }
1763                 udelay(10);
1764         }
1765
1766         RTL_W32(CounterAddrLow, 0);
1767         RTL_W32(CounterAddrHigh, 0);
1768
1769         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1770 }
1771
1772 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1773                                       struct ethtool_stats *stats, u64 *data)
1774 {
1775         struct rtl8169_private *tp = netdev_priv(dev);
1776
1777         ASSERT_RTNL();
1778
1779         rtl8169_update_counters(dev);
1780
1781         data[0] = le64_to_cpu(tp->counters.tx_packets);
1782         data[1] = le64_to_cpu(tp->counters.rx_packets);
1783         data[2] = le64_to_cpu(tp->counters.tx_errors);
1784         data[3] = le32_to_cpu(tp->counters.rx_errors);
1785         data[4] = le16_to_cpu(tp->counters.rx_missed);
1786         data[5] = le16_to_cpu(tp->counters.align_errors);
1787         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1788         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1789         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1790         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1791         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1792         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1793         data[12] = le16_to_cpu(tp->counters.tx_underun);
1794 }
1795
1796 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1797 {
1798         switch(stringset) {
1799         case ETH_SS_STATS:
1800                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1801                 break;
1802         }
1803 }
1804
1805 static const struct ethtool_ops rtl8169_ethtool_ops = {
1806         .get_drvinfo            = rtl8169_get_drvinfo,
1807         .get_regs_len           = rtl8169_get_regs_len,
1808         .get_link               = ethtool_op_get_link,
1809         .get_settings           = rtl8169_get_settings,
1810         .set_settings           = rtl8169_set_settings,
1811         .get_msglevel           = rtl8169_get_msglevel,
1812         .set_msglevel           = rtl8169_set_msglevel,
1813         .get_regs               = rtl8169_get_regs,
1814         .get_wol                = rtl8169_get_wol,
1815         .set_wol                = rtl8169_set_wol,
1816         .get_strings            = rtl8169_get_strings,
1817         .get_sset_count         = rtl8169_get_sset_count,
1818         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1819 };
1820
1821 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1822                                     struct net_device *dev, u8 default_version)
1823 {
1824         void __iomem *ioaddr = tp->mmio_addr;
1825         /*
1826          * The driver currently handles the 8168Bf and the 8168Be identically
1827          * but they can be identified more specifically through the test below
1828          * if needed:
1829          *
1830          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1831          *
1832          * Same thing for the 8101Eb and the 8101Ec:
1833          *
1834          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1835          */
1836         static const struct rtl_mac_info {
1837                 u32 mask;
1838                 u32 val;
1839                 int mac_version;
1840         } mac_info[] = {
1841                 /* 8168F family. */
1842                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1843                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1844
1845                 /* 8168E family. */
1846                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1847                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1848                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1849                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1850
1851                 /* 8168D family. */
1852                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1853                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1854                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1855
1856                 /* 8168DP family. */
1857                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1858                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1859                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1860
1861                 /* 8168C family. */
1862                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1863                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1864                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1865                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1866                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1867                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1868                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1869                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1870                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1871
1872                 /* 8168B family. */
1873                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1874                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1875                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1876                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1877
1878                 /* 8101 family. */
1879                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1880                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1881                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1882                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1883                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1884                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1885                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1886                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1887                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1888                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1889                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1890                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1891                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1892                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1893                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1894                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1895                 /* FIXME: where did these entries come from ? -- FR */
1896                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1897                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1898
1899                 /* 8110 family. */
1900                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1901                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1902                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1903                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1904                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1905                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1906
1907                 /* Catch-all */
1908                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1909         };
1910         const struct rtl_mac_info *p = mac_info;
1911         u32 reg;
1912
1913         reg = RTL_R32(TxConfig);
1914         while ((reg & p->mask) != p->val)
1915                 p++;
1916         tp->mac_version = p->mac_version;
1917
1918         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1919                 netif_notice(tp, probe, dev,
1920                              "unknown MAC, using family default\n");
1921                 tp->mac_version = default_version;
1922         }
1923 }
1924
1925 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1926 {
1927         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1928 }
1929
1930 struct phy_reg {
1931         u16 reg;
1932         u16 val;
1933 };
1934
1935 static void rtl_writephy_batch(struct rtl8169_private *tp,
1936                                const struct phy_reg *regs, int len)
1937 {
1938         while (len-- > 0) {
1939                 rtl_writephy(tp, regs->reg, regs->val);
1940                 regs++;
1941         }
1942 }
1943
1944 #define PHY_READ                0x00000000
1945 #define PHY_DATA_OR             0x10000000
1946 #define PHY_DATA_AND            0x20000000
1947 #define PHY_BJMPN               0x30000000
1948 #define PHY_READ_EFUSE          0x40000000
1949 #define PHY_READ_MAC_BYTE       0x50000000
1950 #define PHY_WRITE_MAC_BYTE      0x60000000
1951 #define PHY_CLEAR_READCOUNT     0x70000000
1952 #define PHY_WRITE               0x80000000
1953 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1954 #define PHY_COMP_EQ_SKIPN       0xa0000000
1955 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1956 #define PHY_WRITE_PREVIOUS      0xc0000000
1957 #define PHY_SKIPN               0xd0000000
1958 #define PHY_DELAY_MS            0xe0000000
1959 #define PHY_WRITE_ERI_WORD      0xf0000000
1960
1961 struct fw_info {
1962         u32     magic;
1963         char    version[RTL_VER_SIZE];
1964         __le32  fw_start;
1965         __le32  fw_len;
1966         u8      chksum;
1967 } __packed;
1968
1969 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1970
1971 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1972 {
1973         const struct firmware *fw = rtl_fw->fw;
1974         struct fw_info *fw_info = (struct fw_info *)fw->data;
1975         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1976         char *version = rtl_fw->version;
1977         bool rc = false;
1978
1979         if (fw->size < FW_OPCODE_SIZE)
1980                 goto out;
1981
1982         if (!fw_info->magic) {
1983                 size_t i, size, start;
1984                 u8 checksum = 0;
1985
1986                 if (fw->size < sizeof(*fw_info))
1987                         goto out;
1988
1989                 for (i = 0; i < fw->size; i++)
1990                         checksum += fw->data[i];
1991                 if (checksum != 0)
1992                         goto out;
1993
1994                 start = le32_to_cpu(fw_info->fw_start);
1995                 if (start > fw->size)
1996                         goto out;
1997
1998                 size = le32_to_cpu(fw_info->fw_len);
1999                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2000                         goto out;
2001
2002                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2003
2004                 pa->code = (__le32 *)(fw->data + start);
2005                 pa->size = size;
2006         } else {
2007                 if (fw->size % FW_OPCODE_SIZE)
2008                         goto out;
2009
2010                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2011
2012                 pa->code = (__le32 *)fw->data;
2013                 pa->size = fw->size / FW_OPCODE_SIZE;
2014         }
2015         version[RTL_VER_SIZE - 1] = 0;
2016
2017         rc = true;
2018 out:
2019         return rc;
2020 }
2021
2022 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2023                            struct rtl_fw_phy_action *pa)
2024 {
2025         bool rc = false;
2026         size_t index;
2027
2028         for (index = 0; index < pa->size; index++) {
2029                 u32 action = le32_to_cpu(pa->code[index]);
2030                 u32 regno = (action & 0x0fff0000) >> 16;
2031
2032                 switch(action & 0xf0000000) {
2033                 case PHY_READ:
2034                 case PHY_DATA_OR:
2035                 case PHY_DATA_AND:
2036                 case PHY_READ_EFUSE:
2037                 case PHY_CLEAR_READCOUNT:
2038                 case PHY_WRITE:
2039                 case PHY_WRITE_PREVIOUS:
2040                 case PHY_DELAY_MS:
2041                         break;
2042
2043                 case PHY_BJMPN:
2044                         if (regno > index) {
2045                                 netif_err(tp, ifup, tp->dev,
2046                                           "Out of range of firmware\n");
2047                                 goto out;
2048                         }
2049                         break;
2050                 case PHY_READCOUNT_EQ_SKIP:
2051                         if (index + 2 >= pa->size) {
2052                                 netif_err(tp, ifup, tp->dev,
2053                                           "Out of range of firmware\n");
2054                                 goto out;
2055                         }
2056                         break;
2057                 case PHY_COMP_EQ_SKIPN:
2058                 case PHY_COMP_NEQ_SKIPN:
2059                 case PHY_SKIPN:
2060                         if (index + 1 + regno >= pa->size) {
2061                                 netif_err(tp, ifup, tp->dev,
2062                                           "Out of range of firmware\n");
2063                                 goto out;
2064                         }
2065                         break;
2066
2067                 case PHY_READ_MAC_BYTE:
2068                 case PHY_WRITE_MAC_BYTE:
2069                 case PHY_WRITE_ERI_WORD:
2070                 default:
2071                         netif_err(tp, ifup, tp->dev,
2072                                   "Invalid action 0x%08x\n", action);
2073                         goto out;
2074                 }
2075         }
2076         rc = true;
2077 out:
2078         return rc;
2079 }
2080
2081 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2082 {
2083         struct net_device *dev = tp->dev;
2084         int rc = -EINVAL;
2085
2086         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2087                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2088                 goto out;
2089         }
2090
2091         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2092                 rc = 0;
2093 out:
2094         return rc;
2095 }
2096
2097 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2098 {
2099         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2100         u32 predata, count;
2101         size_t index;
2102
2103         predata = count = 0;
2104
2105         for (index = 0; index < pa->size; ) {
2106                 u32 action = le32_to_cpu(pa->code[index]);
2107                 u32 data = action & 0x0000ffff;
2108                 u32 regno = (action & 0x0fff0000) >> 16;
2109
2110                 if (!action)
2111                         break;
2112
2113                 switch(action & 0xf0000000) {
2114                 case PHY_READ:
2115                         predata = rtl_readphy(tp, regno);
2116                         count++;
2117                         index++;
2118                         break;
2119                 case PHY_DATA_OR:
2120                         predata |= data;
2121                         index++;
2122                         break;
2123                 case PHY_DATA_AND:
2124                         predata &= data;
2125                         index++;
2126                         break;
2127                 case PHY_BJMPN:
2128                         index -= regno;
2129                         break;
2130                 case PHY_READ_EFUSE:
2131                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2132                         index++;
2133                         break;
2134                 case PHY_CLEAR_READCOUNT:
2135                         count = 0;
2136                         index++;
2137                         break;
2138                 case PHY_WRITE:
2139                         rtl_writephy(tp, regno, data);
2140                         index++;
2141                         break;
2142                 case PHY_READCOUNT_EQ_SKIP:
2143                         index += (count == data) ? 2 : 1;
2144                         break;
2145                 case PHY_COMP_EQ_SKIPN:
2146                         if (predata == data)
2147                                 index += regno;
2148                         index++;
2149                         break;
2150                 case PHY_COMP_NEQ_SKIPN:
2151                         if (predata != data)
2152                                 index += regno;
2153                         index++;
2154                         break;
2155                 case PHY_WRITE_PREVIOUS:
2156                         rtl_writephy(tp, regno, predata);
2157                         index++;
2158                         break;
2159                 case PHY_SKIPN:
2160                         index += regno + 1;
2161                         break;
2162                 case PHY_DELAY_MS:
2163                         mdelay(data);
2164                         index++;
2165                         break;
2166
2167                 case PHY_READ_MAC_BYTE:
2168                 case PHY_WRITE_MAC_BYTE:
2169                 case PHY_WRITE_ERI_WORD:
2170                 default:
2171                         BUG();
2172                 }
2173         }
2174 }
2175
2176 static void rtl_release_firmware(struct rtl8169_private *tp)
2177 {
2178         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2179                 release_firmware(tp->rtl_fw->fw);
2180                 kfree(tp->rtl_fw);
2181         }
2182         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2183 }
2184
2185 static void rtl_apply_firmware(struct rtl8169_private *tp)
2186 {
2187         struct rtl_fw *rtl_fw = tp->rtl_fw;
2188
2189         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2190         if (!IS_ERR_OR_NULL(rtl_fw))
2191                 rtl_phy_write_fw(tp, rtl_fw);
2192 }
2193
2194 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2195 {
2196         if (rtl_readphy(tp, reg) != val)
2197                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2198         else
2199                 rtl_apply_firmware(tp);
2200 }
2201
2202 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2203 {
2204         static const struct phy_reg phy_reg_init[] = {
2205                 { 0x1f, 0x0001 },
2206                 { 0x06, 0x006e },
2207                 { 0x08, 0x0708 },
2208                 { 0x15, 0x4000 },
2209                 { 0x18, 0x65c7 },
2210
2211                 { 0x1f, 0x0001 },
2212                 { 0x03, 0x00a1 },
2213                 { 0x02, 0x0008 },
2214                 { 0x01, 0x0120 },
2215                 { 0x00, 0x1000 },
2216                 { 0x04, 0x0800 },
2217                 { 0x04, 0x0000 },
2218
2219                 { 0x03, 0xff41 },
2220                 { 0x02, 0xdf60 },
2221                 { 0x01, 0x0140 },
2222                 { 0x00, 0x0077 },
2223                 { 0x04, 0x7800 },
2224                 { 0x04, 0x7000 },
2225
2226                 { 0x03, 0x802f },
2227                 { 0x02, 0x4f02 },
2228                 { 0x01, 0x0409 },
2229                 { 0x00, 0xf0f9 },
2230                 { 0x04, 0x9800 },
2231                 { 0x04, 0x9000 },
2232
2233                 { 0x03, 0xdf01 },
2234                 { 0x02, 0xdf20 },
2235                 { 0x01, 0xff95 },
2236                 { 0x00, 0xba00 },
2237                 { 0x04, 0xa800 },
2238                 { 0x04, 0xa000 },
2239
2240                 { 0x03, 0xff41 },
2241                 { 0x02, 0xdf20 },
2242                 { 0x01, 0x0140 },
2243                 { 0x00, 0x00bb },
2244                 { 0x04, 0xb800 },
2245                 { 0x04, 0xb000 },
2246
2247                 { 0x03, 0xdf41 },
2248                 { 0x02, 0xdc60 },
2249                 { 0x01, 0x6340 },
2250                 { 0x00, 0x007d },
2251                 { 0x04, 0xd800 },
2252                 { 0x04, 0xd000 },
2253
2254                 { 0x03, 0xdf01 },
2255                 { 0x02, 0xdf20 },
2256                 { 0x01, 0x100a },
2257                 { 0x00, 0xa0ff },
2258                 { 0x04, 0xf800 },
2259                 { 0x04, 0xf000 },
2260
2261                 { 0x1f, 0x0000 },
2262                 { 0x0b, 0x0000 },
2263                 { 0x00, 0x9200 }
2264         };
2265
2266         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2267 }
2268
2269 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2270 {
2271         static const struct phy_reg phy_reg_init[] = {
2272                 { 0x1f, 0x0002 },
2273                 { 0x01, 0x90d0 },
2274                 { 0x1f, 0x0000 }
2275         };
2276
2277         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2278 }
2279
2280 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2281 {
2282         struct pci_dev *pdev = tp->pci_dev;
2283
2284         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2285             (pdev->subsystem_device != 0xe000))
2286                 return;
2287
2288         rtl_writephy(tp, 0x1f, 0x0001);
2289         rtl_writephy(tp, 0x10, 0xf01b);
2290         rtl_writephy(tp, 0x1f, 0x0000);
2291 }
2292
2293 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2294 {
2295         static const struct phy_reg phy_reg_init[] = {
2296                 { 0x1f, 0x0001 },
2297                 { 0x04, 0x0000 },
2298                 { 0x03, 0x00a1 },
2299                 { 0x02, 0x0008 },
2300                 { 0x01, 0x0120 },
2301                 { 0x00, 0x1000 },
2302                 { 0x04, 0x0800 },
2303                 { 0x04, 0x9000 },
2304                 { 0x03, 0x802f },
2305                 { 0x02, 0x4f02 },
2306                 { 0x01, 0x0409 },
2307                 { 0x00, 0xf099 },
2308                 { 0x04, 0x9800 },
2309                 { 0x04, 0xa000 },
2310                 { 0x03, 0xdf01 },
2311                 { 0x02, 0xdf20 },
2312                 { 0x01, 0xff95 },
2313                 { 0x00, 0xba00 },
2314                 { 0x04, 0xa800 },
2315                 { 0x04, 0xf000 },
2316                 { 0x03, 0xdf01 },
2317                 { 0x02, 0xdf20 },
2318                 { 0x01, 0x101a },
2319                 { 0x00, 0xa0ff },
2320                 { 0x04, 0xf800 },
2321                 { 0x04, 0x0000 },
2322                 { 0x1f, 0x0000 },
2323
2324                 { 0x1f, 0x0001 },
2325                 { 0x10, 0xf41b },
2326                 { 0x14, 0xfb54 },
2327                 { 0x18, 0xf5c7 },
2328                 { 0x1f, 0x0000 },
2329
2330                 { 0x1f, 0x0001 },
2331                 { 0x17, 0x0cc0 },
2332                 { 0x1f, 0x0000 }
2333         };
2334
2335         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2336
2337         rtl8169scd_hw_phy_config_quirk(tp);
2338 }
2339
2340 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2341 {
2342         static const struct phy_reg phy_reg_init[] = {
2343                 { 0x1f, 0x0001 },
2344                 { 0x04, 0x0000 },
2345                 { 0x03, 0x00a1 },
2346                 { 0x02, 0x0008 },
2347                 { 0x01, 0x0120 },
2348                 { 0x00, 0x1000 },
2349                 { 0x04, 0x0800 },
2350                 { 0x04, 0x9000 },
2351                 { 0x03, 0x802f },
2352                 { 0x02, 0x4f02 },
2353                 { 0x01, 0x0409 },
2354                 { 0x00, 0xf099 },
2355                 { 0x04, 0x9800 },
2356                 { 0x04, 0xa000 },
2357                 { 0x03, 0xdf01 },
2358                 { 0x02, 0xdf20 },
2359                 { 0x01, 0xff95 },
2360                 { 0x00, 0xba00 },
2361                 { 0x04, 0xa800 },
2362                 { 0x04, 0xf000 },
2363                 { 0x03, 0xdf01 },
2364                 { 0x02, 0xdf20 },
2365                 { 0x01, 0x101a },
2366                 { 0x00, 0xa0ff },
2367                 { 0x04, 0xf800 },
2368                 { 0x04, 0x0000 },
2369                 { 0x1f, 0x0000 },
2370
2371                 { 0x1f, 0x0001 },
2372                 { 0x0b, 0x8480 },
2373                 { 0x1f, 0x0000 },
2374
2375                 { 0x1f, 0x0001 },
2376                 { 0x18, 0x67c7 },
2377                 { 0x04, 0x2000 },
2378                 { 0x03, 0x002f },
2379                 { 0x02, 0x4360 },
2380                 { 0x01, 0x0109 },
2381                 { 0x00, 0x3022 },
2382                 { 0x04, 0x2800 },
2383                 { 0x1f, 0x0000 },
2384
2385                 { 0x1f, 0x0001 },
2386                 { 0x17, 0x0cc0 },
2387                 { 0x1f, 0x0000 }
2388         };
2389
2390         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2391 }
2392
2393 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2394 {
2395         static const struct phy_reg phy_reg_init[] = {
2396                 { 0x10, 0xf41b },
2397                 { 0x1f, 0x0000 }
2398         };
2399
2400         rtl_writephy(tp, 0x1f, 0x0001);
2401         rtl_patchphy(tp, 0x16, 1 << 0);
2402
2403         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2404 }
2405
2406 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2407 {
2408         static const struct phy_reg phy_reg_init[] = {
2409                 { 0x1f, 0x0001 },
2410                 { 0x10, 0xf41b },
2411                 { 0x1f, 0x0000 }
2412         };
2413
2414         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2415 }
2416
2417 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2418 {
2419         static const struct phy_reg phy_reg_init[] = {
2420                 { 0x1f, 0x0000 },
2421                 { 0x1d, 0x0f00 },
2422                 { 0x1f, 0x0002 },
2423                 { 0x0c, 0x1ec8 },
2424                 { 0x1f, 0x0000 }
2425         };
2426
2427         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2428 }
2429
2430 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2431 {
2432         static const struct phy_reg phy_reg_init[] = {
2433                 { 0x1f, 0x0001 },
2434                 { 0x1d, 0x3d98 },
2435                 { 0x1f, 0x0000 }
2436         };
2437
2438         rtl_writephy(tp, 0x1f, 0x0000);
2439         rtl_patchphy(tp, 0x14, 1 << 5);
2440         rtl_patchphy(tp, 0x0d, 1 << 5);
2441
2442         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2443 }
2444
2445 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2446 {
2447         static const struct phy_reg phy_reg_init[] = {
2448                 { 0x1f, 0x0001 },
2449                 { 0x12, 0x2300 },
2450                 { 0x1f, 0x0002 },
2451                 { 0x00, 0x88d4 },
2452                 { 0x01, 0x82b1 },
2453                 { 0x03, 0x7002 },
2454                 { 0x08, 0x9e30 },
2455                 { 0x09, 0x01f0 },
2456                 { 0x0a, 0x5500 },
2457                 { 0x0c, 0x00c8 },
2458                 { 0x1f, 0x0003 },
2459                 { 0x12, 0xc096 },
2460                 { 0x16, 0x000a },
2461                 { 0x1f, 0x0000 },
2462                 { 0x1f, 0x0000 },
2463                 { 0x09, 0x2000 },
2464                 { 0x09, 0x0000 }
2465         };
2466
2467         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2468
2469         rtl_patchphy(tp, 0x14, 1 << 5);
2470         rtl_patchphy(tp, 0x0d, 1 << 5);
2471         rtl_writephy(tp, 0x1f, 0x0000);
2472 }
2473
2474 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2475 {
2476         static const struct phy_reg phy_reg_init[] = {
2477                 { 0x1f, 0x0001 },
2478                 { 0x12, 0x2300 },
2479                 { 0x03, 0x802f },
2480                 { 0x02, 0x4f02 },
2481                 { 0x01, 0x0409 },
2482                 { 0x00, 0xf099 },
2483                 { 0x04, 0x9800 },
2484                 { 0x04, 0x9000 },
2485                 { 0x1d, 0x3d98 },
2486                 { 0x1f, 0x0002 },
2487                 { 0x0c, 0x7eb8 },
2488                 { 0x06, 0x0761 },
2489                 { 0x1f, 0x0003 },
2490                 { 0x16, 0x0f0a },
2491                 { 0x1f, 0x0000 }
2492         };
2493
2494         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2495
2496         rtl_patchphy(tp, 0x16, 1 << 0);
2497         rtl_patchphy(tp, 0x14, 1 << 5);
2498         rtl_patchphy(tp, 0x0d, 1 << 5);
2499         rtl_writephy(tp, 0x1f, 0x0000);
2500 }
2501
2502 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2503 {
2504         static const struct phy_reg phy_reg_init[] = {
2505                 { 0x1f, 0x0001 },
2506                 { 0x12, 0x2300 },
2507                 { 0x1d, 0x3d98 },
2508                 { 0x1f, 0x0002 },
2509                 { 0x0c, 0x7eb8 },
2510                 { 0x06, 0x5461 },
2511                 { 0x1f, 0x0003 },
2512                 { 0x16, 0x0f0a },
2513                 { 0x1f, 0x0000 }
2514         };
2515
2516         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2517
2518         rtl_patchphy(tp, 0x16, 1 << 0);
2519         rtl_patchphy(tp, 0x14, 1 << 5);
2520         rtl_patchphy(tp, 0x0d, 1 << 5);
2521         rtl_writephy(tp, 0x1f, 0x0000);
2522 }
2523
2524 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2525 {
2526         rtl8168c_3_hw_phy_config(tp);
2527 }
2528
2529 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2530 {
2531         static const struct phy_reg phy_reg_init_0[] = {
2532                 /* Channel Estimation */
2533                 { 0x1f, 0x0001 },
2534                 { 0x06, 0x4064 },
2535                 { 0x07, 0x2863 },
2536                 { 0x08, 0x059c },
2537                 { 0x09, 0x26b4 },
2538                 { 0x0a, 0x6a19 },
2539                 { 0x0b, 0xdcc8 },
2540                 { 0x10, 0xf06d },
2541                 { 0x14, 0x7f68 },
2542                 { 0x18, 0x7fd9 },
2543                 { 0x1c, 0xf0ff },
2544                 { 0x1d, 0x3d9c },
2545                 { 0x1f, 0x0003 },
2546                 { 0x12, 0xf49f },
2547                 { 0x13, 0x070b },
2548                 { 0x1a, 0x05ad },
2549                 { 0x14, 0x94c0 },
2550
2551                 /*
2552                  * Tx Error Issue
2553                  * Enhance line driver power
2554                  */
2555                 { 0x1f, 0x0002 },
2556                 { 0x06, 0x5561 },
2557                 { 0x1f, 0x0005 },
2558                 { 0x05, 0x8332 },
2559                 { 0x06, 0x5561 },
2560
2561                 /*
2562                  * Can not link to 1Gbps with bad cable
2563                  * Decrease SNR threshold form 21.07dB to 19.04dB
2564                  */
2565                 { 0x1f, 0x0001 },
2566                 { 0x17, 0x0cc0 },
2567
2568                 { 0x1f, 0x0000 },
2569                 { 0x0d, 0xf880 }
2570         };
2571         void __iomem *ioaddr = tp->mmio_addr;
2572
2573         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2574
2575         /*
2576          * Rx Error Issue
2577          * Fine Tune Switching regulator parameter
2578          */
2579         rtl_writephy(tp, 0x1f, 0x0002);
2580         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2581         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2582
2583         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2584                 static const struct phy_reg phy_reg_init[] = {
2585                         { 0x1f, 0x0002 },
2586                         { 0x05, 0x669a },
2587                         { 0x1f, 0x0005 },
2588                         { 0x05, 0x8330 },
2589                         { 0x06, 0x669a },
2590                         { 0x1f, 0x0002 }
2591                 };
2592                 int val;
2593
2594                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2595
2596                 val = rtl_readphy(tp, 0x0d);
2597
2598                 if ((val & 0x00ff) != 0x006c) {
2599                         static const u32 set[] = {
2600                                 0x0065, 0x0066, 0x0067, 0x0068,
2601                                 0x0069, 0x006a, 0x006b, 0x006c
2602                         };
2603                         int i;
2604
2605                         rtl_writephy(tp, 0x1f, 0x0002);
2606
2607                         val &= 0xff00;
2608                         for (i = 0; i < ARRAY_SIZE(set); i++)
2609                                 rtl_writephy(tp, 0x0d, val | set[i]);
2610                 }
2611         } else {
2612                 static const struct phy_reg phy_reg_init[] = {
2613                         { 0x1f, 0x0002 },
2614                         { 0x05, 0x6662 },
2615                         { 0x1f, 0x0005 },
2616                         { 0x05, 0x8330 },
2617                         { 0x06, 0x6662 }
2618                 };
2619
2620                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2621         }
2622
2623         /* RSET couple improve */
2624         rtl_writephy(tp, 0x1f, 0x0002);
2625         rtl_patchphy(tp, 0x0d, 0x0300);
2626         rtl_patchphy(tp, 0x0f, 0x0010);
2627
2628         /* Fine tune PLL performance */
2629         rtl_writephy(tp, 0x1f, 0x0002);
2630         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2631         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2632
2633         rtl_writephy(tp, 0x1f, 0x0005);
2634         rtl_writephy(tp, 0x05, 0x001b);
2635
2636         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2637
2638         rtl_writephy(tp, 0x1f, 0x0000);
2639 }
2640
2641 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2642 {
2643         static const struct phy_reg phy_reg_init_0[] = {
2644                 /* Channel Estimation */
2645                 { 0x1f, 0x0001 },
2646                 { 0x06, 0x4064 },
2647                 { 0x07, 0x2863 },
2648                 { 0x08, 0x059c },
2649                 { 0x09, 0x26b4 },
2650                 { 0x0a, 0x6a19 },
2651                 { 0x0b, 0xdcc8 },
2652                 { 0x10, 0xf06d },
2653                 { 0x14, 0x7f68 },
2654                 { 0x18, 0x7fd9 },
2655                 { 0x1c, 0xf0ff },
2656                 { 0x1d, 0x3d9c },
2657                 { 0x1f, 0x0003 },
2658                 { 0x12, 0xf49f },
2659                 { 0x13, 0x070b },
2660                 { 0x1a, 0x05ad },
2661                 { 0x14, 0x94c0 },
2662
2663                 /*
2664                  * Tx Error Issue
2665                  * Enhance line driver power
2666                  */
2667                 { 0x1f, 0x0002 },
2668                 { 0x06, 0x5561 },
2669                 { 0x1f, 0x0005 },
2670                 { 0x05, 0x8332 },
2671                 { 0x06, 0x5561 },
2672
2673                 /*
2674                  * Can not link to 1Gbps with bad cable
2675                  * Decrease SNR threshold form 21.07dB to 19.04dB
2676                  */
2677                 { 0x1f, 0x0001 },
2678                 { 0x17, 0x0cc0 },
2679
2680                 { 0x1f, 0x0000 },
2681                 { 0x0d, 0xf880 }
2682         };
2683         void __iomem *ioaddr = tp->mmio_addr;
2684
2685         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2686
2687         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2688                 static const struct phy_reg phy_reg_init[] = {
2689                         { 0x1f, 0x0002 },
2690                         { 0x05, 0x669a },
2691                         { 0x1f, 0x0005 },
2692                         { 0x05, 0x8330 },
2693                         { 0x06, 0x669a },
2694
2695                         { 0x1f, 0x0002 }
2696                 };
2697                 int val;
2698
2699                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2700
2701                 val = rtl_readphy(tp, 0x0d);
2702                 if ((val & 0x00ff) != 0x006c) {
2703                         static const u32 set[] = {
2704                                 0x0065, 0x0066, 0x0067, 0x0068,
2705                                 0x0069, 0x006a, 0x006b, 0x006c
2706                         };
2707                         int i;
2708
2709                         rtl_writephy(tp, 0x1f, 0x0002);
2710
2711                         val &= 0xff00;
2712                         for (i = 0; i < ARRAY_SIZE(set); i++)
2713                                 rtl_writephy(tp, 0x0d, val | set[i]);
2714                 }
2715         } else {
2716                 static const struct phy_reg phy_reg_init[] = {
2717                         { 0x1f, 0x0002 },
2718                         { 0x05, 0x2642 },
2719                         { 0x1f, 0x0005 },
2720                         { 0x05, 0x8330 },
2721                         { 0x06, 0x2642 }
2722                 };
2723
2724                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2725         }
2726
2727         /* Fine tune PLL performance */
2728         rtl_writephy(tp, 0x1f, 0x0002);
2729         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2730         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2731
2732         /* Switching regulator Slew rate */
2733         rtl_writephy(tp, 0x1f, 0x0002);
2734         rtl_patchphy(tp, 0x0f, 0x0017);
2735
2736         rtl_writephy(tp, 0x1f, 0x0005);
2737         rtl_writephy(tp, 0x05, 0x001b);
2738
2739         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2740
2741         rtl_writephy(tp, 0x1f, 0x0000);
2742 }
2743
2744 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2745 {
2746         static const struct phy_reg phy_reg_init[] = {
2747                 { 0x1f, 0x0002 },
2748                 { 0x10, 0x0008 },
2749                 { 0x0d, 0x006c },
2750
2751                 { 0x1f, 0x0000 },
2752                 { 0x0d, 0xf880 },
2753
2754                 { 0x1f, 0x0001 },
2755                 { 0x17, 0x0cc0 },
2756
2757                 { 0x1f, 0x0001 },
2758                 { 0x0b, 0xa4d8 },
2759                 { 0x09, 0x281c },
2760                 { 0x07, 0x2883 },
2761                 { 0x0a, 0x6b35 },
2762                 { 0x1d, 0x3da4 },
2763                 { 0x1c, 0xeffd },
2764                 { 0x14, 0x7f52 },
2765                 { 0x18, 0x7fc6 },
2766                 { 0x08, 0x0601 },
2767                 { 0x06, 0x4063 },
2768                 { 0x10, 0xf074 },
2769                 { 0x1f, 0x0003 },
2770                 { 0x13, 0x0789 },
2771                 { 0x12, 0xf4bd },
2772                 { 0x1a, 0x04fd },
2773                 { 0x14, 0x84b0 },
2774                 { 0x1f, 0x0000 },
2775                 { 0x00, 0x9200 },
2776
2777                 { 0x1f, 0x0005 },
2778                 { 0x01, 0x0340 },
2779                 { 0x1f, 0x0001 },
2780                 { 0x04, 0x4000 },
2781                 { 0x03, 0x1d21 },
2782                 { 0x02, 0x0c32 },
2783                 { 0x01, 0x0200 },
2784                 { 0x00, 0x5554 },
2785                 { 0x04, 0x4800 },
2786                 { 0x04, 0x4000 },
2787                 { 0x04, 0xf000 },
2788                 { 0x03, 0xdf01 },
2789                 { 0x02, 0xdf20 },
2790                 { 0x01, 0x101a },
2791                 { 0x00, 0xa0ff },
2792                 { 0x04, 0xf800 },
2793                 { 0x04, 0xf000 },
2794                 { 0x1f, 0x0000 },
2795
2796                 { 0x1f, 0x0007 },
2797                 { 0x1e, 0x0023 },
2798                 { 0x16, 0x0000 },
2799                 { 0x1f, 0x0000 }
2800         };
2801
2802         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2803 }
2804
2805 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2806 {
2807         static const struct phy_reg phy_reg_init[] = {
2808                 { 0x1f, 0x0001 },
2809                 { 0x17, 0x0cc0 },
2810
2811                 { 0x1f, 0x0007 },
2812                 { 0x1e, 0x002d },
2813                 { 0x18, 0x0040 },
2814                 { 0x1f, 0x0000 }
2815         };
2816
2817         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2818         rtl_patchphy(tp, 0x0d, 1 << 5);
2819 }
2820
2821 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2822 {
2823         static const struct phy_reg phy_reg_init[] = {
2824                 /* Enable Delay cap */
2825                 { 0x1f, 0x0005 },
2826                 { 0x05, 0x8b80 },
2827                 { 0x06, 0xc896 },
2828                 { 0x1f, 0x0000 },
2829
2830                 /* Channel estimation fine tune */
2831                 { 0x1f, 0x0001 },
2832                 { 0x0b, 0x6c20 },
2833                 { 0x07, 0x2872 },
2834                 { 0x1c, 0xefff },
2835                 { 0x1f, 0x0003 },
2836                 { 0x14, 0x6420 },
2837                 { 0x1f, 0x0000 },
2838
2839                 /* Update PFM & 10M TX idle timer */
2840                 { 0x1f, 0x0007 },
2841                 { 0x1e, 0x002f },
2842                 { 0x15, 0x1919 },
2843                 { 0x1f, 0x0000 },
2844
2845                 { 0x1f, 0x0007 },
2846                 { 0x1e, 0x00ac },
2847                 { 0x18, 0x0006 },
2848                 { 0x1f, 0x0000 }
2849         };
2850
2851         rtl_apply_firmware(tp);
2852
2853         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2854
2855         /* DCO enable for 10M IDLE Power */
2856         rtl_writephy(tp, 0x1f, 0x0007);
2857         rtl_writephy(tp, 0x1e, 0x0023);
2858         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2859         rtl_writephy(tp, 0x1f, 0x0000);
2860
2861         /* For impedance matching */
2862         rtl_writephy(tp, 0x1f, 0x0002);
2863         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2864         rtl_writephy(tp, 0x1f, 0x0000);
2865
2866         /* PHY auto speed down */
2867         rtl_writephy(tp, 0x1f, 0x0007);
2868         rtl_writephy(tp, 0x1e, 0x002d);
2869         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2870         rtl_writephy(tp, 0x1f, 0x0000);
2871         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2872
2873         rtl_writephy(tp, 0x1f, 0x0005);
2874         rtl_writephy(tp, 0x05, 0x8b86);
2875         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2876         rtl_writephy(tp, 0x1f, 0x0000);
2877
2878         rtl_writephy(tp, 0x1f, 0x0005);
2879         rtl_writephy(tp, 0x05, 0x8b85);
2880         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2881         rtl_writephy(tp, 0x1f, 0x0007);
2882         rtl_writephy(tp, 0x1e, 0x0020);
2883         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2884         rtl_writephy(tp, 0x1f, 0x0006);
2885         rtl_writephy(tp, 0x00, 0x5a00);
2886         rtl_writephy(tp, 0x1f, 0x0000);
2887         rtl_writephy(tp, 0x0d, 0x0007);
2888         rtl_writephy(tp, 0x0e, 0x003c);
2889         rtl_writephy(tp, 0x0d, 0x4007);
2890         rtl_writephy(tp, 0x0e, 0x0000);
2891         rtl_writephy(tp, 0x0d, 0x0000);
2892 }
2893
2894 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2895 {
2896         static const struct phy_reg phy_reg_init[] = {
2897                 /* Enable Delay cap */
2898                 { 0x1f, 0x0004 },
2899                 { 0x1f, 0x0007 },
2900                 { 0x1e, 0x00ac },
2901                 { 0x18, 0x0006 },
2902                 { 0x1f, 0x0002 },
2903                 { 0x1f, 0x0000 },
2904                 { 0x1f, 0x0000 },
2905
2906                 /* Channel estimation fine tune */
2907                 { 0x1f, 0x0003 },
2908                 { 0x09, 0xa20f },
2909                 { 0x1f, 0x0000 },
2910                 { 0x1f, 0x0000 },
2911
2912                 /* Green Setting */
2913                 { 0x1f, 0x0005 },
2914                 { 0x05, 0x8b5b },
2915                 { 0x06, 0x9222 },
2916                 { 0x05, 0x8b6d },
2917                 { 0x06, 0x8000 },
2918                 { 0x05, 0x8b76 },
2919                 { 0x06, 0x8000 },
2920                 { 0x1f, 0x0000 }
2921         };
2922
2923         rtl_apply_firmware(tp);
2924
2925         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2926
2927         /* For 4-corner performance improve */
2928         rtl_writephy(tp, 0x1f, 0x0005);
2929         rtl_writephy(tp, 0x05, 0x8b80);
2930         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2931         rtl_writephy(tp, 0x1f, 0x0000);
2932
2933         /* PHY auto speed down */
2934         rtl_writephy(tp, 0x1f, 0x0004);
2935         rtl_writephy(tp, 0x1f, 0x0007);
2936         rtl_writephy(tp, 0x1e, 0x002d);
2937         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2938         rtl_writephy(tp, 0x1f, 0x0002);
2939         rtl_writephy(tp, 0x1f, 0x0000);
2940         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2941
2942         /* improve 10M EEE waveform */
2943         rtl_writephy(tp, 0x1f, 0x0005);
2944         rtl_writephy(tp, 0x05, 0x8b86);
2945         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2946         rtl_writephy(tp, 0x1f, 0x0000);
2947
2948         /* Improve 2-pair detection performance */
2949         rtl_writephy(tp, 0x1f, 0x0005);
2950         rtl_writephy(tp, 0x05, 0x8b85);
2951         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2952         rtl_writephy(tp, 0x1f, 0x0000);
2953
2954         /* EEE setting */
2955         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2956                      ERIAR_EXGMAC);
2957         rtl_writephy(tp, 0x1f, 0x0005);
2958         rtl_writephy(tp, 0x05, 0x8b85);
2959         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2960         rtl_writephy(tp, 0x1f, 0x0004);
2961         rtl_writephy(tp, 0x1f, 0x0007);
2962         rtl_writephy(tp, 0x1e, 0x0020);
2963         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
2964         rtl_writephy(tp, 0x1f, 0x0002);
2965         rtl_writephy(tp, 0x1f, 0x0000);
2966         rtl_writephy(tp, 0x0d, 0x0007);
2967         rtl_writephy(tp, 0x0e, 0x003c);
2968         rtl_writephy(tp, 0x0d, 0x4007);
2969         rtl_writephy(tp, 0x0e, 0x0000);
2970         rtl_writephy(tp, 0x0d, 0x0000);
2971
2972         /* Green feature */
2973         rtl_writephy(tp, 0x1f, 0x0003);
2974         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2975         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2976         rtl_writephy(tp, 0x1f, 0x0000);
2977 }
2978
2979 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
2980 {
2981         static const struct phy_reg phy_reg_init[] = {
2982                 /* Channel estimation fine tune */
2983                 { 0x1f, 0x0003 },
2984                 { 0x09, 0xa20f },
2985                 { 0x1f, 0x0000 },
2986
2987                 /* Modify green table for giga & fnet */
2988                 { 0x1f, 0x0005 },
2989                 { 0x05, 0x8b55 },
2990                 { 0x06, 0x0000 },
2991                 { 0x05, 0x8b5e },
2992                 { 0x06, 0x0000 },
2993                 { 0x05, 0x8b67 },
2994                 { 0x06, 0x0000 },
2995                 { 0x05, 0x8b70 },
2996                 { 0x06, 0x0000 },
2997                 { 0x1f, 0x0000 },
2998                 { 0x1f, 0x0007 },
2999                 { 0x1e, 0x0078 },
3000                 { 0x17, 0x0000 },
3001                 { 0x19, 0x00fb },
3002                 { 0x1f, 0x0000 },
3003
3004                 /* Modify green table for 10M */
3005                 { 0x1f, 0x0005 },
3006                 { 0x05, 0x8b79 },
3007                 { 0x06, 0xaa00 },
3008                 { 0x1f, 0x0000 },
3009
3010                 /* Disable hiimpedance detection (RTCT) */
3011                 { 0x1f, 0x0003 },
3012                 { 0x01, 0x328a },
3013                 { 0x1f, 0x0000 }
3014         };
3015
3016         rtl_apply_firmware(tp);
3017
3018         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3019
3020         /* For 4-corner performance improve */
3021         rtl_writephy(tp, 0x1f, 0x0005);
3022         rtl_writephy(tp, 0x05, 0x8b80);
3023         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3024         rtl_writephy(tp, 0x1f, 0x0000);
3025
3026         /* PHY auto speed down */
3027         rtl_writephy(tp, 0x1f, 0x0007);
3028         rtl_writephy(tp, 0x1e, 0x002d);
3029         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3030         rtl_writephy(tp, 0x1f, 0x0000);
3031         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3032
3033         /* Improve 10M EEE waveform */
3034         rtl_writephy(tp, 0x1f, 0x0005);
3035         rtl_writephy(tp, 0x05, 0x8b86);
3036         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3037         rtl_writephy(tp, 0x1f, 0x0000);
3038
3039         /* Improve 2-pair detection performance */
3040         rtl_writephy(tp, 0x1f, 0x0005);
3041         rtl_writephy(tp, 0x05, 0x8b85);
3042         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3043         rtl_writephy(tp, 0x1f, 0x0000);
3044 }
3045
3046 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3047 {
3048         rtl_apply_firmware(tp);
3049
3050         /* For 4-corner performance improve */
3051         rtl_writephy(tp, 0x1f, 0x0005);
3052         rtl_writephy(tp, 0x05, 0x8b80);
3053         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3054         rtl_writephy(tp, 0x1f, 0x0000);
3055
3056         /* PHY auto speed down */
3057         rtl_writephy(tp, 0x1f, 0x0007);
3058         rtl_writephy(tp, 0x1e, 0x002d);
3059         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3060         rtl_writephy(tp, 0x1f, 0x0000);
3061         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3062
3063         /* Improve 10M EEE waveform */
3064         rtl_writephy(tp, 0x1f, 0x0005);
3065         rtl_writephy(tp, 0x05, 0x8b86);
3066         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3067         rtl_writephy(tp, 0x1f, 0x0000);
3068 }
3069
3070 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3071 {
3072         static const struct phy_reg phy_reg_init[] = {
3073                 { 0x1f, 0x0003 },
3074                 { 0x08, 0x441d },
3075                 { 0x01, 0x9100 },
3076                 { 0x1f, 0x0000 }
3077         };
3078
3079         rtl_writephy(tp, 0x1f, 0x0000);
3080         rtl_patchphy(tp, 0x11, 1 << 12);
3081         rtl_patchphy(tp, 0x19, 1 << 13);
3082         rtl_patchphy(tp, 0x10, 1 << 15);
3083
3084         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3085 }
3086
3087 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3088 {
3089         static const struct phy_reg phy_reg_init[] = {
3090                 { 0x1f, 0x0005 },
3091                 { 0x1a, 0x0000 },
3092                 { 0x1f, 0x0000 },
3093
3094                 { 0x1f, 0x0004 },
3095                 { 0x1c, 0x0000 },
3096                 { 0x1f, 0x0000 },
3097
3098                 { 0x1f, 0x0001 },
3099                 { 0x15, 0x7701 },
3100                 { 0x1f, 0x0000 }
3101         };
3102
3103         /* Disable ALDPS before ram code */
3104         rtl_writephy(tp, 0x1f, 0x0000);
3105         rtl_writephy(tp, 0x18, 0x0310);
3106         msleep(100);
3107
3108         rtl_apply_firmware(tp);
3109
3110         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3111 }
3112
3113 static void rtl_hw_phy_config(struct net_device *dev)
3114 {
3115         struct rtl8169_private *tp = netdev_priv(dev);
3116
3117         rtl8169_print_mac_version(tp);
3118
3119         switch (tp->mac_version) {
3120         case RTL_GIGA_MAC_VER_01:
3121                 break;
3122         case RTL_GIGA_MAC_VER_02:
3123         case RTL_GIGA_MAC_VER_03:
3124                 rtl8169s_hw_phy_config(tp);
3125                 break;
3126         case RTL_GIGA_MAC_VER_04:
3127                 rtl8169sb_hw_phy_config(tp);
3128                 break;
3129         case RTL_GIGA_MAC_VER_05:
3130                 rtl8169scd_hw_phy_config(tp);
3131                 break;
3132         case RTL_GIGA_MAC_VER_06:
3133                 rtl8169sce_hw_phy_config(tp);
3134                 break;
3135         case RTL_GIGA_MAC_VER_07:
3136         case RTL_GIGA_MAC_VER_08:
3137         case RTL_GIGA_MAC_VER_09:
3138                 rtl8102e_hw_phy_config(tp);
3139                 break;
3140         case RTL_GIGA_MAC_VER_11:
3141                 rtl8168bb_hw_phy_config(tp);
3142                 break;
3143         case RTL_GIGA_MAC_VER_12:
3144                 rtl8168bef_hw_phy_config(tp);
3145                 break;
3146         case RTL_GIGA_MAC_VER_17:
3147                 rtl8168bef_hw_phy_config(tp);
3148                 break;
3149         case RTL_GIGA_MAC_VER_18:
3150                 rtl8168cp_1_hw_phy_config(tp);
3151                 break;
3152         case RTL_GIGA_MAC_VER_19:
3153                 rtl8168c_1_hw_phy_config(tp);
3154                 break;
3155         case RTL_GIGA_MAC_VER_20:
3156                 rtl8168c_2_hw_phy_config(tp);
3157                 break;
3158         case RTL_GIGA_MAC_VER_21:
3159                 rtl8168c_3_hw_phy_config(tp);
3160                 break;
3161         case RTL_GIGA_MAC_VER_22:
3162                 rtl8168c_4_hw_phy_config(tp);
3163                 break;
3164         case RTL_GIGA_MAC_VER_23:
3165         case RTL_GIGA_MAC_VER_24:
3166                 rtl8168cp_2_hw_phy_config(tp);
3167                 break;
3168         case RTL_GIGA_MAC_VER_25:
3169                 rtl8168d_1_hw_phy_config(tp);
3170                 break;
3171         case RTL_GIGA_MAC_VER_26:
3172                 rtl8168d_2_hw_phy_config(tp);
3173                 break;
3174         case RTL_GIGA_MAC_VER_27:
3175                 rtl8168d_3_hw_phy_config(tp);
3176                 break;
3177         case RTL_GIGA_MAC_VER_28:
3178                 rtl8168d_4_hw_phy_config(tp);
3179                 break;
3180         case RTL_GIGA_MAC_VER_29:
3181         case RTL_GIGA_MAC_VER_30:
3182                 rtl8105e_hw_phy_config(tp);
3183                 break;
3184         case RTL_GIGA_MAC_VER_31:
3185                 /* None. */
3186                 break;
3187         case RTL_GIGA_MAC_VER_32:
3188         case RTL_GIGA_MAC_VER_33:
3189                 rtl8168e_1_hw_phy_config(tp);
3190                 break;
3191         case RTL_GIGA_MAC_VER_34:
3192                 rtl8168e_2_hw_phy_config(tp);
3193                 break;
3194         case RTL_GIGA_MAC_VER_35:
3195                 rtl8168f_1_hw_phy_config(tp);
3196                 break;
3197         case RTL_GIGA_MAC_VER_36:
3198                 rtl8168f_2_hw_phy_config(tp);
3199                 break;
3200
3201         default:
3202                 break;
3203         }
3204 }
3205
3206 static void rtl8169_phy_timer(unsigned long __opaque)
3207 {
3208         struct net_device *dev = (struct net_device *)__opaque;
3209         struct rtl8169_private *tp = netdev_priv(dev);
3210         struct timer_list *timer = &tp->timer;
3211         void __iomem *ioaddr = tp->mmio_addr;
3212         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3213
3214         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3215
3216         spin_lock_irq(&tp->lock);
3217
3218         if (tp->phy_reset_pending(tp)) {
3219                 /*
3220                  * A busy loop could burn quite a few cycles on nowadays CPU.
3221                  * Let's delay the execution of the timer for a few ticks.
3222                  */
3223                 timeout = HZ/10;
3224                 goto out_mod_timer;
3225         }
3226
3227         if (tp->link_ok(ioaddr))
3228                 goto out_unlock;
3229
3230         netif_warn(tp, link, dev, "PHY reset until link up\n");
3231
3232         tp->phy_reset_enable(tp);
3233
3234 out_mod_timer:
3235         mod_timer(timer, jiffies + timeout);
3236 out_unlock:
3237         spin_unlock_irq(&tp->lock);
3238 }
3239
3240 #ifdef CONFIG_NET_POLL_CONTROLLER
3241 /*
3242  * Polling 'interrupt' - used by things like netconsole to send skbs
3243  * without having to re-enable interrupts. It's not called while
3244  * the interrupt routine is executing.
3245  */
3246 static void rtl8169_netpoll(struct net_device *dev)
3247 {
3248         struct rtl8169_private *tp = netdev_priv(dev);
3249         struct pci_dev *pdev = tp->pci_dev;
3250
3251         disable_irq(pdev->irq);
3252         rtl8169_interrupt(pdev->irq, dev);
3253         enable_irq(pdev->irq);
3254 }
3255 #endif
3256
3257 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3258                                   void __iomem *ioaddr)
3259 {
3260         iounmap(ioaddr);
3261         pci_release_regions(pdev);
3262         pci_clear_mwi(pdev);
3263         pci_disable_device(pdev);
3264         free_netdev(dev);
3265 }
3266
3267 static void rtl8169_phy_reset(struct net_device *dev,
3268                               struct rtl8169_private *tp)
3269 {
3270         unsigned int i;
3271
3272         tp->phy_reset_enable(tp);
3273         for (i = 0; i < 100; i++) {
3274                 if (!tp->phy_reset_pending(tp))
3275                         return;
3276                 msleep(1);
3277         }
3278         netif_err(tp, link, dev, "PHY reset failed\n");
3279 }
3280
3281 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3282 {
3283         void __iomem *ioaddr = tp->mmio_addr;
3284
3285         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3286             (RTL_R8(PHYstatus) & TBI_Enable);
3287 }
3288
3289 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3290 {
3291         void __iomem *ioaddr = tp->mmio_addr;
3292
3293         rtl_hw_phy_config(dev);
3294
3295         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3296                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3297                 RTL_W8(0x82, 0x01);
3298         }
3299
3300         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3301
3302         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3303                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3304
3305         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3306                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3307                 RTL_W8(0x82, 0x01);
3308                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3309                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3310         }
3311
3312         rtl8169_phy_reset(dev, tp);
3313
3314         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3315                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3316                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3317                           (tp->mii.supports_gmii ?
3318                            ADVERTISED_1000baseT_Half |
3319                            ADVERTISED_1000baseT_Full : 0));
3320
3321         if (rtl_tbi_enabled(tp))
3322                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3323 }
3324
3325 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3326 {
3327         void __iomem *ioaddr = tp->mmio_addr;
3328         u32 high;
3329         u32 low;
3330
3331         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3332         high = addr[4] | (addr[5] << 8);
3333
3334         spin_lock_irq(&tp->lock);
3335
3336         RTL_W8(Cfg9346, Cfg9346_Unlock);
3337
3338         RTL_W32(MAC4, high);
3339         RTL_R32(MAC4);
3340
3341         RTL_W32(MAC0, low);
3342         RTL_R32(MAC0);
3343
3344         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3345                 const struct exgmac_reg e[] = {
3346                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3347                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3348                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3349                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3350                                                                 low  >> 16 },
3351                 };
3352
3353                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3354         }
3355
3356         RTL_W8(Cfg9346, Cfg9346_Lock);
3357
3358         spin_unlock_irq(&tp->lock);
3359 }
3360
3361 static int rtl_set_mac_address(struct net_device *dev, void *p)
3362 {
3363         struct rtl8169_private *tp = netdev_priv(dev);
3364         struct sockaddr *addr = p;
3365
3366         if (!is_valid_ether_addr(addr->sa_data))
3367                 return -EADDRNOTAVAIL;
3368
3369         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3370
3371         rtl_rar_set(tp, dev->dev_addr);
3372
3373         return 0;
3374 }
3375
3376 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3377 {
3378         struct rtl8169_private *tp = netdev_priv(dev);
3379         struct mii_ioctl_data *data = if_mii(ifr);
3380
3381         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3382 }
3383
3384 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3385                           struct mii_ioctl_data *data, int cmd)
3386 {
3387         switch (cmd) {
3388         case SIOCGMIIPHY:
3389                 data->phy_id = 32; /* Internal PHY */
3390                 return 0;
3391
3392         case SIOCGMIIREG:
3393                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3394                 return 0;
3395
3396         case SIOCSMIIREG:
3397                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3398                 return 0;
3399         }
3400         return -EOPNOTSUPP;
3401 }
3402
3403 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3404 {
3405         return -EOPNOTSUPP;
3406 }
3407
3408 static const struct rtl_cfg_info {
3409         void (*hw_start)(struct net_device *);
3410         unsigned int region;
3411         unsigned int align;
3412         u16 intr_event;
3413         u16 napi_event;
3414         unsigned features;
3415         u8 default_ver;
3416 } rtl_cfg_infos [] = {
3417         [RTL_CFG_0] = {
3418                 .hw_start       = rtl_hw_start_8169,
3419                 .region         = 1,
3420                 .align          = 0,
3421                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3422                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3423                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3424                 .features       = RTL_FEATURE_GMII,
3425                 .default_ver    = RTL_GIGA_MAC_VER_01,
3426         },
3427         [RTL_CFG_1] = {
3428                 .hw_start       = rtl_hw_start_8168,
3429                 .region         = 2,
3430                 .align          = 8,
3431                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3432                                   TxErr | TxOK | RxOK | RxErr,
3433                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
3434                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3435                 .default_ver    = RTL_GIGA_MAC_VER_11,
3436         },
3437         [RTL_CFG_2] = {
3438                 .hw_start       = rtl_hw_start_8101,
3439                 .region         = 2,
3440                 .align          = 8,
3441                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3442                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3443                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3444                 .features       = RTL_FEATURE_MSI,
3445                 .default_ver    = RTL_GIGA_MAC_VER_13,
3446         }
3447 };
3448
3449 /* Cfg9346_Unlock assumed. */
3450 static unsigned rtl_try_msi(struct rtl8169_private *tp,
3451                             const struct rtl_cfg_info *cfg)
3452 {
3453         void __iomem *ioaddr = tp->mmio_addr;
3454         unsigned msi = 0;
3455         u8 cfg2;
3456
3457         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3458         if (cfg->features & RTL_FEATURE_MSI) {
3459                 if (pci_enable_msi(tp->pci_dev)) {
3460                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
3461                 } else {
3462                         cfg2 |= MSIEnable;
3463                         msi = RTL_FEATURE_MSI;
3464                 }
3465         }
3466         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3467                 RTL_W8(Config2, cfg2);
3468         return msi;
3469 }
3470
3471 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3472 {
3473         if (tp->features & RTL_FEATURE_MSI) {
3474                 pci_disable_msi(pdev);
3475                 tp->features &= ~RTL_FEATURE_MSI;
3476         }
3477 }
3478
3479 static const struct net_device_ops rtl8169_netdev_ops = {
3480         .ndo_open               = rtl8169_open,
3481         .ndo_stop               = rtl8169_close,
3482         .ndo_get_stats          = rtl8169_get_stats,
3483         .ndo_start_xmit         = rtl8169_start_xmit,
3484         .ndo_tx_timeout         = rtl8169_tx_timeout,
3485         .ndo_validate_addr      = eth_validate_addr,
3486         .ndo_change_mtu         = rtl8169_change_mtu,
3487         .ndo_fix_features       = rtl8169_fix_features,
3488         .ndo_set_features       = rtl8169_set_features,
3489         .ndo_set_mac_address    = rtl_set_mac_address,
3490         .ndo_do_ioctl           = rtl8169_ioctl,
3491         .ndo_set_rx_mode        = rtl_set_rx_mode,
3492 #ifdef CONFIG_NET_POLL_CONTROLLER
3493         .ndo_poll_controller    = rtl8169_netpoll,
3494 #endif
3495
3496 };
3497
3498 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3499 {
3500         struct mdio_ops *ops = &tp->mdio_ops;
3501
3502         switch (tp->mac_version) {
3503         case RTL_GIGA_MAC_VER_27:
3504                 ops->write      = r8168dp_1_mdio_write;
3505                 ops->read       = r8168dp_1_mdio_read;
3506                 break;
3507         case RTL_GIGA_MAC_VER_28:
3508         case RTL_GIGA_MAC_VER_31:
3509                 ops->write      = r8168dp_2_mdio_write;
3510                 ops->read       = r8168dp_2_mdio_read;
3511                 break;
3512         default:
3513                 ops->write      = r8169_mdio_write;
3514                 ops->read       = r8169_mdio_read;
3515                 break;
3516         }
3517 }
3518
3519 static void rtl_speed_down(struct rtl8169_private *tp)
3520 {
3521         u32 adv;
3522         int lpa;
3523
3524         rtl_writephy(tp, 0x1f, 0x0000);
3525         lpa = rtl_readphy(tp, MII_LPA);
3526
3527         if (lpa & (LPA_10HALF | LPA_10FULL))
3528                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3529         else if (lpa & (LPA_100HALF | LPA_100FULL))
3530                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3531                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3532         else
3533                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3534                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3535                       (tp->mii.supports_gmii ?
3536                        ADVERTISED_1000baseT_Half |
3537                        ADVERTISED_1000baseT_Full : 0);
3538
3539         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3540                           adv);
3541 }
3542
3543 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3544 {
3545         void __iomem *ioaddr = tp->mmio_addr;
3546
3547         switch (tp->mac_version) {
3548         case RTL_GIGA_MAC_VER_25:
3549         case RTL_GIGA_MAC_VER_26:
3550         case RTL_GIGA_MAC_VER_29:
3551         case RTL_GIGA_MAC_VER_30:
3552         case RTL_GIGA_MAC_VER_32:
3553         case RTL_GIGA_MAC_VER_33:
3554         case RTL_GIGA_MAC_VER_34:
3555                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3556                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3557                 break;
3558         default:
3559                 break;
3560         }
3561 }
3562
3563 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3564 {
3565         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3566                 return false;
3567
3568         rtl_speed_down(tp);
3569         rtl_wol_suspend_quirk(tp);
3570
3571         return true;
3572 }
3573
3574 static void r810x_phy_power_down(struct rtl8169_private *tp)
3575 {
3576         rtl_writephy(tp, 0x1f, 0x0000);
3577         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3578 }
3579
3580 static void r810x_phy_power_up(struct rtl8169_private *tp)
3581 {
3582         rtl_writephy(tp, 0x1f, 0x0000);
3583         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3584 }
3585
3586 static void r810x_pll_power_down(struct rtl8169_private *tp)
3587 {
3588         if (rtl_wol_pll_power_down(tp))
3589                 return;
3590
3591         r810x_phy_power_down(tp);
3592 }
3593
3594 static void r810x_pll_power_up(struct rtl8169_private *tp)
3595 {
3596         r810x_phy_power_up(tp);
3597 }
3598
3599 static void r8168_phy_power_up(struct rtl8169_private *tp)
3600 {
3601         rtl_writephy(tp, 0x1f, 0x0000);
3602         switch (tp->mac_version) {
3603         case RTL_GIGA_MAC_VER_11:
3604         case RTL_GIGA_MAC_VER_12:
3605         case RTL_GIGA_MAC_VER_17:
3606         case RTL_GIGA_MAC_VER_18:
3607         case RTL_GIGA_MAC_VER_19:
3608         case RTL_GIGA_MAC_VER_20:
3609         case RTL_GIGA_MAC_VER_21:
3610         case RTL_GIGA_MAC_VER_22:
3611         case RTL_GIGA_MAC_VER_23:
3612         case RTL_GIGA_MAC_VER_24:
3613         case RTL_GIGA_MAC_VER_25:
3614         case RTL_GIGA_MAC_VER_26:
3615         case RTL_GIGA_MAC_VER_27:
3616         case RTL_GIGA_MAC_VER_28:
3617         case RTL_GIGA_MAC_VER_31:
3618                 rtl_writephy(tp, 0x0e, 0x0000);
3619                 break;
3620         default:
3621                 break;
3622         }
3623         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3624 }
3625
3626 static void r8168_phy_power_down(struct rtl8169_private *tp)
3627 {
3628         rtl_writephy(tp, 0x1f, 0x0000);
3629         switch (tp->mac_version) {
3630         case RTL_GIGA_MAC_VER_32:
3631         case RTL_GIGA_MAC_VER_33:
3632                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3633                 break;
3634
3635         case RTL_GIGA_MAC_VER_11:
3636         case RTL_GIGA_MAC_VER_12:
3637         case RTL_GIGA_MAC_VER_17:
3638         case RTL_GIGA_MAC_VER_18:
3639         case RTL_GIGA_MAC_VER_19:
3640         case RTL_GIGA_MAC_VER_20:
3641         case RTL_GIGA_MAC_VER_21:
3642         case RTL_GIGA_MAC_VER_22:
3643         case RTL_GIGA_MAC_VER_23:
3644         case RTL_GIGA_MAC_VER_24:
3645         case RTL_GIGA_MAC_VER_25:
3646         case RTL_GIGA_MAC_VER_26:
3647         case RTL_GIGA_MAC_VER_27:
3648         case RTL_GIGA_MAC_VER_28:
3649         case RTL_GIGA_MAC_VER_31:
3650                 rtl_writephy(tp, 0x0e, 0x0200);
3651         default:
3652                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3653                 break;
3654         }
3655 }
3656
3657 static void r8168_pll_power_down(struct rtl8169_private *tp)
3658 {
3659         void __iomem *ioaddr = tp->mmio_addr;
3660
3661         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3662              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3663              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3664             r8168dp_check_dash(tp)) {
3665                 return;
3666         }
3667
3668         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3669              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3670             (RTL_R16(CPlusCmd) & ASF)) {
3671                 return;
3672         }
3673
3674         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3675             tp->mac_version == RTL_GIGA_MAC_VER_33)
3676                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3677
3678         if (rtl_wol_pll_power_down(tp))
3679                 return;
3680
3681         r8168_phy_power_down(tp);
3682
3683         switch (tp->mac_version) {
3684         case RTL_GIGA_MAC_VER_25:
3685         case RTL_GIGA_MAC_VER_26:
3686         case RTL_GIGA_MAC_VER_27:
3687         case RTL_GIGA_MAC_VER_28:
3688         case RTL_GIGA_MAC_VER_31:
3689         case RTL_GIGA_MAC_VER_32:
3690         case RTL_GIGA_MAC_VER_33:
3691                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3692                 break;
3693         }
3694 }
3695
3696 static void r8168_pll_power_up(struct rtl8169_private *tp)
3697 {
3698         void __iomem *ioaddr = tp->mmio_addr;
3699
3700         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3701              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3702              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3703             r8168dp_check_dash(tp)) {
3704                 return;
3705         }
3706
3707         switch (tp->mac_version) {
3708         case RTL_GIGA_MAC_VER_25:
3709         case RTL_GIGA_MAC_VER_26:
3710         case RTL_GIGA_MAC_VER_27:
3711         case RTL_GIGA_MAC_VER_28:
3712         case RTL_GIGA_MAC_VER_31:
3713         case RTL_GIGA_MAC_VER_32:
3714         case RTL_GIGA_MAC_VER_33:
3715                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3716                 break;
3717         }
3718
3719         r8168_phy_power_up(tp);
3720 }
3721
3722 static void rtl_generic_op(struct rtl8169_private *tp,
3723                            void (*op)(struct rtl8169_private *))
3724 {
3725         if (op)
3726                 op(tp);
3727 }
3728
3729 static void rtl_pll_power_down(struct rtl8169_private *tp)
3730 {
3731         rtl_generic_op(tp, tp->pll_power_ops.down);
3732 }
3733
3734 static void rtl_pll_power_up(struct rtl8169_private *tp)
3735 {
3736         rtl_generic_op(tp, tp->pll_power_ops.up);
3737 }
3738
3739 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3740 {
3741         struct pll_power_ops *ops = &tp->pll_power_ops;
3742
3743         switch (tp->mac_version) {
3744         case RTL_GIGA_MAC_VER_07:
3745         case RTL_GIGA_MAC_VER_08:
3746         case RTL_GIGA_MAC_VER_09:
3747         case RTL_GIGA_MAC_VER_10:
3748         case RTL_GIGA_MAC_VER_16:
3749         case RTL_GIGA_MAC_VER_29:
3750         case RTL_GIGA_MAC_VER_30:
3751                 ops->down       = r810x_pll_power_down;
3752                 ops->up         = r810x_pll_power_up;
3753                 break;
3754
3755         case RTL_GIGA_MAC_VER_11:
3756         case RTL_GIGA_MAC_VER_12:
3757         case RTL_GIGA_MAC_VER_17:
3758         case RTL_GIGA_MAC_VER_18:
3759         case RTL_GIGA_MAC_VER_19:
3760         case RTL_GIGA_MAC_VER_20:
3761         case RTL_GIGA_MAC_VER_21:
3762         case RTL_GIGA_MAC_VER_22:
3763         case RTL_GIGA_MAC_VER_23:
3764         case RTL_GIGA_MAC_VER_24:
3765         case RTL_GIGA_MAC_VER_25:
3766         case RTL_GIGA_MAC_VER_26:
3767         case RTL_GIGA_MAC_VER_27:
3768         case RTL_GIGA_MAC_VER_28:
3769         case RTL_GIGA_MAC_VER_31:
3770         case RTL_GIGA_MAC_VER_32:
3771         case RTL_GIGA_MAC_VER_33:
3772         case RTL_GIGA_MAC_VER_34:
3773         case RTL_GIGA_MAC_VER_35:
3774         case RTL_GIGA_MAC_VER_36:
3775                 ops->down       = r8168_pll_power_down;
3776                 ops->up         = r8168_pll_power_up;
3777                 break;
3778
3779         default:
3780                 ops->down       = NULL;
3781                 ops->up         = NULL;
3782                 break;
3783         }
3784 }
3785
3786 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3787 {
3788         void __iomem *ioaddr = tp->mmio_addr;
3789
3790         switch (tp->mac_version) {
3791         case RTL_GIGA_MAC_VER_01:
3792         case RTL_GIGA_MAC_VER_02:
3793         case RTL_GIGA_MAC_VER_03:
3794         case RTL_GIGA_MAC_VER_04:
3795         case RTL_GIGA_MAC_VER_05:
3796         case RTL_GIGA_MAC_VER_06:
3797         case RTL_GIGA_MAC_VER_10:
3798         case RTL_GIGA_MAC_VER_11:
3799         case RTL_GIGA_MAC_VER_12:
3800         case RTL_GIGA_MAC_VER_13:
3801         case RTL_GIGA_MAC_VER_14:
3802         case RTL_GIGA_MAC_VER_15:
3803         case RTL_GIGA_MAC_VER_16:
3804         case RTL_GIGA_MAC_VER_17:
3805                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3806                 break;
3807         case RTL_GIGA_MAC_VER_18:
3808         case RTL_GIGA_MAC_VER_19:
3809         case RTL_GIGA_MAC_VER_20:
3810         case RTL_GIGA_MAC_VER_21:
3811         case RTL_GIGA_MAC_VER_22:
3812         case RTL_GIGA_MAC_VER_23:
3813         case RTL_GIGA_MAC_VER_24:
3814         case RTL_GIGA_MAC_VER_34:
3815                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3816                 break;
3817         default:
3818                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3819                 break;
3820         }
3821 }
3822
3823 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3824 {
3825         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3826 }
3827
3828 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3829 {
3830         void __iomem *ioaddr = tp->mmio_addr;
3831
3832         RTL_W8(Cfg9346, Cfg9346_Unlock);
3833         rtl_generic_op(tp, tp->jumbo_ops.enable);
3834         RTL_W8(Cfg9346, Cfg9346_Lock);
3835 }
3836
3837 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3838 {
3839         void __iomem *ioaddr = tp->mmio_addr;
3840
3841         RTL_W8(Cfg9346, Cfg9346_Unlock);
3842         rtl_generic_op(tp, tp->jumbo_ops.disable);
3843         RTL_W8(Cfg9346, Cfg9346_Lock);
3844 }
3845
3846 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3847 {
3848         void __iomem *ioaddr = tp->mmio_addr;
3849
3850         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3851         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3852         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3853 }
3854
3855 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3856 {
3857         void __iomem *ioaddr = tp->mmio_addr;
3858
3859         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3860         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3861         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3862 }
3863
3864 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3865 {
3866         void __iomem *ioaddr = tp->mmio_addr;
3867
3868         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3869 }
3870
3871 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3872 {
3873         void __iomem *ioaddr = tp->mmio_addr;
3874
3875         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3876 }
3877
3878 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3879 {
3880         void __iomem *ioaddr = tp->mmio_addr;
3881         struct pci_dev *pdev = tp->pci_dev;
3882
3883         RTL_W8(MaxTxPacketSize, 0x3f);
3884         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3885         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3886         pci_write_config_byte(pdev, 0x79, 0x20);
3887 }
3888
3889 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3890 {
3891         void __iomem *ioaddr = tp->mmio_addr;
3892         struct pci_dev *pdev = tp->pci_dev;
3893
3894         RTL_W8(MaxTxPacketSize, 0x0c);
3895         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3896         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3897         pci_write_config_byte(pdev, 0x79, 0x50);
3898 }
3899
3900 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3901 {
3902         rtl_tx_performance_tweak(tp->pci_dev,
3903                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3904 }
3905
3906 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3907 {
3908         rtl_tx_performance_tweak(tp->pci_dev,
3909                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3910 }
3911
3912 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3913 {
3914         void __iomem *ioaddr = tp->mmio_addr;
3915
3916         r8168b_0_hw_jumbo_enable(tp);
3917
3918         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3919 }
3920
3921 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3922 {
3923         void __iomem *ioaddr = tp->mmio_addr;
3924
3925         r8168b_0_hw_jumbo_disable(tp);
3926
3927         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3928 }
3929
3930 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3931 {
3932         struct jumbo_ops *ops = &tp->jumbo_ops;
3933
3934         switch (tp->mac_version) {
3935         case RTL_GIGA_MAC_VER_11:
3936                 ops->disable    = r8168b_0_hw_jumbo_disable;
3937                 ops->enable     = r8168b_0_hw_jumbo_enable;
3938                 break;
3939         case RTL_GIGA_MAC_VER_12:
3940         case RTL_GIGA_MAC_VER_17:
3941                 ops->disable    = r8168b_1_hw_jumbo_disable;
3942                 ops->enable     = r8168b_1_hw_jumbo_enable;
3943                 break;
3944         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3945         case RTL_GIGA_MAC_VER_19:
3946         case RTL_GIGA_MAC_VER_20:
3947         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3948         case RTL_GIGA_MAC_VER_22:
3949         case RTL_GIGA_MAC_VER_23:
3950         case RTL_GIGA_MAC_VER_24:
3951         case RTL_GIGA_MAC_VER_25:
3952         case RTL_GIGA_MAC_VER_26:
3953                 ops->disable    = r8168c_hw_jumbo_disable;
3954                 ops->enable     = r8168c_hw_jumbo_enable;
3955                 break;
3956         case RTL_GIGA_MAC_VER_27:
3957         case RTL_GIGA_MAC_VER_28:
3958                 ops->disable    = r8168dp_hw_jumbo_disable;
3959                 ops->enable     = r8168dp_hw_jumbo_enable;
3960                 break;
3961         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3962         case RTL_GIGA_MAC_VER_32:
3963         case RTL_GIGA_MAC_VER_33:
3964         case RTL_GIGA_MAC_VER_34:
3965                 ops->disable    = r8168e_hw_jumbo_disable;
3966                 ops->enable     = r8168e_hw_jumbo_enable;
3967                 break;
3968
3969         /*
3970          * No action needed for jumbo frames with 8169.
3971          * No jumbo for 810x at all.
3972          */
3973         default:
3974                 ops->disable    = NULL;
3975                 ops->enable     = NULL;
3976                 break;
3977         }
3978 }
3979
3980 static void rtl_hw_reset(struct rtl8169_private *tp)
3981 {
3982         void __iomem *ioaddr = tp->mmio_addr;
3983         int i;
3984
3985         /* Soft reset the chip. */
3986         RTL_W8(ChipCmd, CmdReset);
3987
3988         /* Check that the chip has finished the reset. */
3989         for (i = 0; i < 100; i++) {
3990                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3991                         break;
3992                 udelay(100);
3993         }
3994 }
3995
3996 static int __devinit
3997 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3998 {
3999         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
4000         const unsigned int region = cfg->region;
4001         struct rtl8169_private *tp;
4002         struct mii_if_info *mii;
4003         struct net_device *dev;
4004         void __iomem *ioaddr;
4005         int chipset, i;
4006         int rc;
4007
4008         if (netif_msg_drv(&debug)) {
4009                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
4010                        MODULENAME, RTL8169_VERSION);
4011         }
4012
4013         dev = alloc_etherdev(sizeof (*tp));
4014         if (!dev) {
4015                 if (netif_msg_drv(&debug))
4016                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4017                 rc = -ENOMEM;
4018                 goto out;
4019         }
4020
4021         SET_NETDEV_DEV(dev, &pdev->dev);
4022         dev->netdev_ops = &rtl8169_netdev_ops;
4023         tp = netdev_priv(dev);
4024         tp->dev = dev;
4025         tp->pci_dev = pdev;
4026         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
4027
4028         mii = &tp->mii;
4029         mii->dev = dev;
4030         mii->mdio_read = rtl_mdio_read;
4031         mii->mdio_write = rtl_mdio_write;
4032         mii->phy_id_mask = 0x1f;
4033         mii->reg_num_mask = 0x1f;
4034         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
4035
4036         /* disable ASPM completely as that cause random device stop working
4037          * problems as well as full system hangs for some PCIe devices users */
4038         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4039                                      PCIE_LINK_STATE_CLKPM);
4040
4041         /* enable device (incl. PCI PM wakeup and hotplug setup) */
4042         rc = pci_enable_device(pdev);
4043         if (rc < 0) {
4044                 netif_err(tp, probe, dev, "enable failure\n");
4045                 goto err_out_free_dev_1;
4046         }
4047
4048         if (pci_set_mwi(pdev) < 0)
4049                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
4050
4051         /* make sure PCI base addr 1 is MMIO */
4052         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4053                 netif_err(tp, probe, dev,
4054                           "region #%d not an MMIO resource, aborting\n",
4055                           region);
4056                 rc = -ENODEV;
4057                 goto err_out_mwi_2;
4058         }
4059
4060         /* check for weird/broken PCI region reporting */
4061         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4062                 netif_err(tp, probe, dev,
4063                           "Invalid PCI region size(s), aborting\n");
4064                 rc = -ENODEV;
4065                 goto err_out_mwi_2;
4066         }
4067
4068         rc = pci_request_regions(pdev, MODULENAME);
4069         if (rc < 0) {
4070                 netif_err(tp, probe, dev, "could not request regions\n");
4071                 goto err_out_mwi_2;
4072         }
4073
4074         tp->cp_cmd = RxChkSum;
4075
4076         if ((sizeof(dma_addr_t) > 4) &&
4077             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
4078                 tp->cp_cmd |= PCIDAC;
4079                 dev->features |= NETIF_F_HIGHDMA;
4080         } else {
4081                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4082                 if (rc < 0) {
4083                         netif_err(tp, probe, dev, "DMA configuration failed\n");
4084                         goto err_out_free_res_3;
4085                 }
4086         }
4087
4088         /* ioremap MMIO region */
4089         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4090         if (!ioaddr) {
4091                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
4092                 rc = -EIO;
4093                 goto err_out_free_res_3;
4094         }
4095         tp->mmio_addr = ioaddr;
4096
4097         if (!pci_is_pcie(pdev))
4098                 netif_info(tp, probe, dev, "not PCI Express\n");
4099
4100         /* Identify chip attached to board */
4101         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
4102
4103         rtl_init_rxcfg(tp);
4104
4105         RTL_W16(IntrMask, 0x0000);
4106
4107         rtl_hw_reset(tp);
4108
4109         RTL_W16(IntrStatus, 0xffff);
4110
4111         pci_set_master(pdev);
4112
4113         /*
4114          * Pretend we are using VLANs; This bypasses a nasty bug where
4115          * Interrupts stop flowing on high load on 8110SCd controllers.
4116          */
4117         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4118                 tp->cp_cmd |= RxVlan;
4119
4120         rtl_init_mdio_ops(tp);
4121         rtl_init_pll_power_ops(tp);
4122         rtl_init_jumbo_ops(tp);
4123
4124         rtl8169_print_mac_version(tp);
4125
4126         chipset = tp->mac_version;
4127         tp->txd_version = rtl_chip_infos[chipset].txd_version;
4128
4129         RTL_W8(Cfg9346, Cfg9346_Unlock);
4130         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
4131         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
4132         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
4133                 tp->features |= RTL_FEATURE_WOL;
4134         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
4135                 tp->features |= RTL_FEATURE_WOL;
4136         tp->features |= rtl_try_msi(tp, cfg);
4137         RTL_W8(Cfg9346, Cfg9346_Lock);
4138
4139         if (rtl_tbi_enabled(tp)) {
4140                 tp->set_speed = rtl8169_set_speed_tbi;
4141                 tp->get_settings = rtl8169_gset_tbi;
4142                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
4143                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
4144                 tp->link_ok = rtl8169_tbi_link_ok;
4145                 tp->do_ioctl = rtl_tbi_ioctl;
4146         } else {
4147                 tp->set_speed = rtl8169_set_speed_xmii;
4148                 tp->get_settings = rtl8169_gset_xmii;
4149                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
4150                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
4151                 tp->link_ok = rtl8169_xmii_link_ok;
4152                 tp->do_ioctl = rtl_xmii_ioctl;
4153         }
4154
4155         spin_lock_init(&tp->lock);
4156
4157         /* Get MAC address */
4158         for (i = 0; i < MAC_ADDR_LEN; i++)
4159                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
4160         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4161
4162         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
4163         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
4164         dev->irq = pdev->irq;
4165         dev->base_addr = (unsigned long) ioaddr;
4166
4167         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
4168
4169         /* don't enable SG, IP_CSUM and TSO by default - it might not work
4170          * properly for all devices */
4171         dev->features |= NETIF_F_RXCSUM |
4172                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4173
4174         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4175                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4176         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4177                 NETIF_F_HIGHDMA;
4178
4179         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4180                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4181                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
4182
4183         tp->intr_mask = 0xffff;
4184         tp->hw_start = cfg->hw_start;
4185         tp->intr_event = cfg->intr_event;
4186         tp->napi_event = cfg->napi_event;
4187
4188         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
4189                 ~(RxBOVF | RxFOVF) : ~0;
4190
4191         init_timer(&tp->timer);
4192         tp->timer.data = (unsigned long) dev;
4193         tp->timer.function = rtl8169_phy_timer;
4194
4195         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
4196
4197         rc = register_netdev(dev);
4198         if (rc < 0)
4199                 goto err_out_msi_4;
4200
4201         pci_set_drvdata(pdev, dev);
4202
4203         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
4204                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
4205                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
4206         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
4207                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
4208                            "tx checksumming: %s]\n",
4209                            rtl_chip_infos[chipset].jumbo_max,
4210                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
4211         }
4212
4213         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4214             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4215             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4216                 rtl8168_driver_start(tp);
4217         }
4218
4219         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
4220
4221         if (pci_dev_run_wake(pdev))
4222                 pm_runtime_put_noidle(&pdev->dev);
4223
4224         netif_carrier_off(dev);
4225
4226 out:
4227         return rc;
4228
4229 err_out_msi_4:
4230         netif_napi_del(&tp->napi);
4231         rtl_disable_msi(pdev, tp);
4232         iounmap(ioaddr);
4233 err_out_free_res_3:
4234         pci_release_regions(pdev);
4235 err_out_mwi_2:
4236         pci_clear_mwi(pdev);
4237         pci_disable_device(pdev);
4238 err_out_free_dev_1:
4239         free_netdev(dev);
4240         goto out;
4241 }
4242
4243 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
4244 {
4245         struct net_device *dev = pci_get_drvdata(pdev);
4246         struct rtl8169_private *tp = netdev_priv(dev);
4247
4248         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4249             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4250             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4251                 rtl8168_driver_stop(tp);
4252         }
4253
4254         cancel_delayed_work_sync(&tp->task);
4255
4256         netif_napi_del(&tp->napi);
4257
4258         unregister_netdev(dev);
4259
4260         rtl_release_firmware(tp);
4261
4262         if (pci_dev_run_wake(pdev))
4263                 pm_runtime_get_noresume(&pdev->dev);
4264
4265         /* restore original MAC address */
4266         rtl_rar_set(tp, dev->perm_addr);
4267
4268         rtl_disable_msi(pdev, tp);
4269         rtl8169_release_board(pdev, dev, tp->mmio_addr);
4270         pci_set_drvdata(pdev, NULL);
4271 }
4272
4273 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4274 {
4275         struct rtl_fw *rtl_fw;
4276         const char *name;
4277         int rc = -ENOMEM;
4278
4279         name = rtl_lookup_firmware_name(tp);
4280         if (!name)
4281                 goto out_no_firmware;
4282
4283         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4284         if (!rtl_fw)
4285                 goto err_warn;
4286
4287         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4288         if (rc < 0)
4289                 goto err_free;
4290
4291         rc = rtl_check_firmware(tp, rtl_fw);
4292         if (rc < 0)
4293                 goto err_release_firmware;
4294
4295         tp->rtl_fw = rtl_fw;
4296 out:
4297         return;
4298
4299 err_release_firmware:
4300         release_firmware(rtl_fw->fw);
4301 err_free:
4302         kfree(rtl_fw);
4303 err_warn:
4304         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4305                    name, rc);
4306 out_no_firmware:
4307         tp->rtl_fw = NULL;
4308         goto out;
4309 }
4310
4311 static void rtl_request_firmware(struct rtl8169_private *tp)
4312 {
4313         if (IS_ERR(tp->rtl_fw))
4314                 rtl_request_uncached_firmware(tp);
4315 }
4316
4317 static int rtl8169_open(struct net_device *dev)
4318 {
4319         struct rtl8169_private *tp = netdev_priv(dev);
4320         void __iomem *ioaddr = tp->mmio_addr;
4321         struct pci_dev *pdev = tp->pci_dev;
4322         int retval = -ENOMEM;
4323
4324         pm_runtime_get_sync(&pdev->dev);
4325
4326         /*
4327          * Rx and Tx desscriptors needs 256 bytes alignment.
4328          * dma_alloc_coherent provides more.
4329          */
4330         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4331                                              &tp->TxPhyAddr, GFP_KERNEL);
4332         if (!tp->TxDescArray)
4333                 goto err_pm_runtime_put;
4334
4335         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4336                                              &tp->RxPhyAddr, GFP_KERNEL);
4337         if (!tp->RxDescArray)
4338                 goto err_free_tx_0;
4339
4340         retval = rtl8169_init_ring(dev);
4341         if (retval < 0)
4342                 goto err_free_rx_1;
4343
4344         INIT_DELAYED_WORK(&tp->task, NULL);
4345
4346         smp_mb();
4347
4348         rtl_request_firmware(tp);
4349
4350         retval = request_irq(dev->irq, rtl8169_interrupt,
4351                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
4352                              dev->name, dev);
4353         if (retval < 0)
4354                 goto err_release_fw_2;
4355
4356         napi_enable(&tp->napi);
4357
4358         rtl8169_init_phy(dev, tp);
4359
4360         rtl8169_set_features(dev, dev->features);
4361
4362         rtl_pll_power_up(tp);
4363
4364         rtl_hw_start(dev);
4365
4366         tp->saved_wolopts = 0;
4367         pm_runtime_put_noidle(&pdev->dev);
4368
4369         rtl8169_check_link_status(dev, tp, ioaddr);
4370 out:
4371         return retval;
4372
4373 err_release_fw_2:
4374         rtl_release_firmware(tp);
4375         rtl8169_rx_clear(tp);
4376 err_free_rx_1:
4377         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4378                           tp->RxPhyAddr);
4379         tp->RxDescArray = NULL;
4380 err_free_tx_0:
4381         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4382                           tp->TxPhyAddr);
4383         tp->TxDescArray = NULL;
4384 err_pm_runtime_put:
4385         pm_runtime_put_noidle(&pdev->dev);
4386         goto out;
4387 }
4388
4389 static void rtl_rx_close(struct rtl8169_private *tp)
4390 {
4391         void __iomem *ioaddr = tp->mmio_addr;
4392
4393         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4394 }
4395
4396 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4397 {
4398         void __iomem *ioaddr = tp->mmio_addr;
4399
4400         /* Disable interrupts */
4401         rtl8169_irq_mask_and_ack(tp);
4402
4403         rtl_rx_close(tp);
4404
4405         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4406             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4407             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4408                 while (RTL_R8(TxPoll) & NPQ)
4409                         udelay(20);
4410         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4411                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4412                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
4413                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4414                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4415                         udelay(100);
4416         } else {
4417                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4418                 udelay(100);
4419         }
4420
4421         rtl_hw_reset(tp);
4422 }
4423
4424 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4425 {
4426         void __iomem *ioaddr = tp->mmio_addr;
4427
4428         /* Set DMA burst size and Interframe Gap Time */
4429         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4430                 (InterFrameGap << TxInterFrameGapShift));
4431 }
4432
4433 static void rtl_hw_start(struct net_device *dev)
4434 {
4435         struct rtl8169_private *tp = netdev_priv(dev);
4436
4437         tp->hw_start(dev);
4438
4439         netif_start_queue(dev);
4440 }
4441
4442 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4443                                          void __iomem *ioaddr)
4444 {
4445         /*
4446          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4447          * register to be written before TxDescAddrLow to work.
4448          * Switching from MMIO to I/O access fixes the issue as well.
4449          */
4450         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4451         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4452         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4453         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4454 }
4455
4456 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4457 {
4458         u16 cmd;
4459
4460         cmd = RTL_R16(CPlusCmd);
4461         RTL_W16(CPlusCmd, cmd);
4462         return cmd;
4463 }
4464
4465 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4466 {
4467         /* Low hurts. Let's disable the filtering. */
4468         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4469 }
4470
4471 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4472 {
4473         static const struct rtl_cfg2_info {
4474                 u32 mac_version;
4475                 u32 clk;
4476                 u32 val;
4477         } cfg2_info [] = {
4478                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4479                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4480                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4481                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4482         };
4483         const struct rtl_cfg2_info *p = cfg2_info;
4484         unsigned int i;
4485         u32 clk;
4486
4487         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4488         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4489                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4490                         RTL_W32(0x7c, p->val);
4491                         break;
4492                 }
4493         }
4494 }
4495
4496 static void rtl_hw_start_8169(struct net_device *dev)
4497 {
4498         struct rtl8169_private *tp = netdev_priv(dev);
4499         void __iomem *ioaddr = tp->mmio_addr;
4500         struct pci_dev *pdev = tp->pci_dev;
4501
4502         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4503                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4504                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4505         }
4506
4507         RTL_W8(Cfg9346, Cfg9346_Unlock);
4508         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4509             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4510             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4511             tp->mac_version == RTL_GIGA_MAC_VER_04)
4512                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4513
4514         rtl_init_rxcfg(tp);
4515
4516         RTL_W8(EarlyTxThres, NoEarlyTx);
4517
4518         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4519
4520         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4521             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4522             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4523             tp->mac_version == RTL_GIGA_MAC_VER_04)
4524                 rtl_set_rx_tx_config_registers(tp);
4525
4526         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4527
4528         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4529             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4530                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4531                         "Bit-3 and bit-14 MUST be 1\n");
4532                 tp->cp_cmd |= (1 << 14);
4533         }
4534
4535         RTL_W16(CPlusCmd, tp->cp_cmd);
4536
4537         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4538
4539         /*
4540          * Undocumented corner. Supposedly:
4541          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4542          */
4543         RTL_W16(IntrMitigate, 0x0000);
4544
4545         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4546
4547         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4548             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4549             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4550             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4551                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4552                 rtl_set_rx_tx_config_registers(tp);
4553         }
4554
4555         RTL_W8(Cfg9346, Cfg9346_Lock);
4556
4557         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4558         RTL_R8(IntrMask);
4559
4560         RTL_W32(RxMissed, 0);
4561
4562         rtl_set_rx_mode(dev);
4563
4564         /* no early-rx interrupts */
4565         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4566
4567         /* Enable all known interrupts by setting the interrupt mask. */
4568         RTL_W16(IntrMask, tp->intr_event);
4569 }
4570
4571 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4572 {
4573         u32 csi;
4574
4575         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4576         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4577 }
4578
4579 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4580 {
4581         rtl_csi_access_enable(ioaddr, 0x17000000);
4582 }
4583
4584 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4585 {
4586         rtl_csi_access_enable(ioaddr, 0x27000000);
4587 }
4588
4589 struct ephy_info {
4590         unsigned int offset;
4591         u16 mask;
4592         u16 bits;
4593 };
4594
4595 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4596 {
4597         u16 w;
4598
4599         while (len-- > 0) {
4600                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4601                 rtl_ephy_write(ioaddr, e->offset, w);
4602                 e++;
4603         }
4604 }
4605
4606 static void rtl_disable_clock_request(struct pci_dev *pdev)
4607 {
4608         int cap = pci_pcie_cap(pdev);
4609
4610         if (cap) {
4611                 u16 ctl;
4612
4613                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4614                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4615                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4616         }
4617 }
4618
4619 static void rtl_enable_clock_request(struct pci_dev *pdev)
4620 {
4621         int cap = pci_pcie_cap(pdev);
4622
4623         if (cap) {
4624                 u16 ctl;
4625
4626                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4627                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4628                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4629         }
4630 }
4631
4632 #define R8168_CPCMD_QUIRK_MASK (\
4633         EnableBist | \
4634         Mac_dbgo_oe | \
4635         Force_half_dup | \
4636         Force_rxflow_en | \
4637         Force_txflow_en | \
4638         Cxpl_dbg_sel | \
4639         ASF | \
4640         PktCntrDisable | \
4641         Mac_dbgo_sel)
4642
4643 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4644 {
4645         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4646
4647         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4648
4649         rtl_tx_performance_tweak(pdev,
4650                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4651 }
4652
4653 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4654 {
4655         rtl_hw_start_8168bb(ioaddr, pdev);
4656
4657         RTL_W8(MaxTxPacketSize, TxPacketMax);
4658
4659         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4660 }
4661
4662 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4663 {
4664         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4665
4666         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4667
4668         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4669
4670         rtl_disable_clock_request(pdev);
4671
4672         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4673 }
4674
4675 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4676 {
4677         static const struct ephy_info e_info_8168cp[] = {
4678                 { 0x01, 0,      0x0001 },
4679                 { 0x02, 0x0800, 0x1000 },
4680                 { 0x03, 0,      0x0042 },
4681                 { 0x06, 0x0080, 0x0000 },
4682                 { 0x07, 0,      0x2000 }
4683         };
4684
4685         rtl_csi_access_enable_2(ioaddr);
4686
4687         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4688
4689         __rtl_hw_start_8168cp(ioaddr, pdev);
4690 }
4691
4692 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4693 {
4694         rtl_csi_access_enable_2(ioaddr);
4695
4696         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4697
4698         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4699
4700         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4701 }
4702
4703 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4704 {
4705         rtl_csi_access_enable_2(ioaddr);
4706
4707         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4708
4709         /* Magic. */
4710         RTL_W8(DBG_REG, 0x20);
4711
4712         RTL_W8(MaxTxPacketSize, TxPacketMax);
4713
4714         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4715
4716         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4717 }
4718
4719 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4720 {
4721         static const struct ephy_info e_info_8168c_1[] = {
4722                 { 0x02, 0x0800, 0x1000 },
4723                 { 0x03, 0,      0x0002 },
4724                 { 0x06, 0x0080, 0x0000 }
4725         };
4726
4727         rtl_csi_access_enable_2(ioaddr);
4728
4729         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4730
4731         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4732
4733         __rtl_hw_start_8168cp(ioaddr, pdev);
4734 }
4735
4736 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4737 {
4738         static const struct ephy_info e_info_8168c_2[] = {
4739                 { 0x01, 0,      0x0001 },
4740                 { 0x03, 0x0400, 0x0220 }
4741         };
4742
4743         rtl_csi_access_enable_2(ioaddr);
4744
4745         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4746
4747         __rtl_hw_start_8168cp(ioaddr, pdev);
4748 }
4749
4750 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4751 {
4752         rtl_hw_start_8168c_2(ioaddr, pdev);
4753 }
4754
4755 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4756 {
4757         rtl_csi_access_enable_2(ioaddr);
4758
4759         __rtl_hw_start_8168cp(ioaddr, pdev);
4760 }
4761
4762 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4763 {
4764         rtl_csi_access_enable_2(ioaddr);
4765
4766         rtl_disable_clock_request(pdev);
4767
4768         RTL_W8(MaxTxPacketSize, TxPacketMax);
4769
4770         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4771
4772         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4773 }
4774
4775 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4776 {
4777         rtl_csi_access_enable_1(ioaddr);
4778
4779         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4780
4781         RTL_W8(MaxTxPacketSize, TxPacketMax);
4782
4783         rtl_disable_clock_request(pdev);
4784 }
4785
4786 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4787 {
4788         static const struct ephy_info e_info_8168d_4[] = {
4789                 { 0x0b, ~0,     0x48 },
4790                 { 0x19, 0x20,   0x50 },
4791                 { 0x0c, ~0,     0x20 }
4792         };
4793         int i;
4794
4795         rtl_csi_access_enable_1(ioaddr);
4796
4797         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4798
4799         RTL_W8(MaxTxPacketSize, TxPacketMax);
4800
4801         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4802                 const struct ephy_info *e = e_info_8168d_4 + i;
4803                 u16 w;
4804
4805                 w = rtl_ephy_read(ioaddr, e->offset);
4806                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4807         }
4808
4809         rtl_enable_clock_request(pdev);
4810 }
4811
4812 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4813 {
4814         static const struct ephy_info e_info_8168e_1[] = {
4815                 { 0x00, 0x0200, 0x0100 },
4816                 { 0x00, 0x0000, 0x0004 },
4817                 { 0x06, 0x0002, 0x0001 },
4818                 { 0x06, 0x0000, 0x0030 },
4819                 { 0x07, 0x0000, 0x2000 },
4820                 { 0x00, 0x0000, 0x0020 },
4821                 { 0x03, 0x5800, 0x2000 },
4822                 { 0x03, 0x0000, 0x0001 },
4823                 { 0x01, 0x0800, 0x1000 },
4824                 { 0x07, 0x0000, 0x4000 },
4825                 { 0x1e, 0x0000, 0x2000 },
4826                 { 0x19, 0xffff, 0xfe6c },
4827                 { 0x0a, 0x0000, 0x0040 }
4828         };
4829
4830         rtl_csi_access_enable_2(ioaddr);
4831
4832         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4833
4834         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4835
4836         RTL_W8(MaxTxPacketSize, TxPacketMax);
4837
4838         rtl_disable_clock_request(pdev);
4839
4840         /* Reset tx FIFO pointer */
4841         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4842         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4843
4844         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4845 }
4846
4847 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4848 {
4849         static const struct ephy_info e_info_8168e_2[] = {
4850                 { 0x09, 0x0000, 0x0080 },
4851                 { 0x19, 0x0000, 0x0224 }
4852         };
4853
4854         rtl_csi_access_enable_1(ioaddr);
4855
4856         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4857
4858         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4859
4860         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4861         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4862         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4863         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4864         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4865         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4866         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4867         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4868                      ERIAR_EXGMAC);
4869
4870         RTL_W8(MaxTxPacketSize, EarlySize);
4871
4872         rtl_disable_clock_request(pdev);
4873
4874         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4875         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4876
4877         /* Adjust EEE LED frequency */
4878         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4879
4880         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4881         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4882         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4883 }
4884
4885 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4886 {
4887         static const struct ephy_info e_info_8168f_1[] = {
4888                 { 0x06, 0x00c0, 0x0020 },
4889                 { 0x08, 0x0001, 0x0002 },
4890                 { 0x09, 0x0000, 0x0080 },
4891                 { 0x19, 0x0000, 0x0224 }
4892         };
4893
4894         rtl_csi_access_enable_1(ioaddr);
4895
4896         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4897
4898         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4899
4900         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4901         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4902         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4903         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4904         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4905         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4906         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4907         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4908         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4909         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4910         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4911                      ERIAR_EXGMAC);
4912
4913         RTL_W8(MaxTxPacketSize, EarlySize);
4914
4915         rtl_disable_clock_request(pdev);
4916
4917         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4918         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4919
4920         /* Adjust EEE LED frequency */
4921         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4922
4923         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4924         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4925         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4926 }
4927
4928 static void rtl_hw_start_8168(struct net_device *dev)
4929 {
4930         struct rtl8169_private *tp = netdev_priv(dev);
4931         void __iomem *ioaddr = tp->mmio_addr;
4932         struct pci_dev *pdev = tp->pci_dev;
4933
4934         RTL_W8(Cfg9346, Cfg9346_Unlock);
4935
4936         RTL_W8(MaxTxPacketSize, TxPacketMax);
4937
4938         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4939
4940         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4941
4942         RTL_W16(CPlusCmd, tp->cp_cmd);
4943
4944         RTL_W16(IntrMitigate, 0x5151);
4945
4946         /* Work around for RxFIFO overflow. */
4947         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4948                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4949                 tp->intr_event &= ~RxOverflow;
4950         }
4951
4952         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4953
4954         rtl_set_rx_mode(dev);
4955
4956         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4957                 (InterFrameGap << TxInterFrameGapShift));
4958
4959         RTL_R8(IntrMask);
4960
4961         switch (tp->mac_version) {
4962         case RTL_GIGA_MAC_VER_11:
4963                 rtl_hw_start_8168bb(ioaddr, pdev);
4964                 break;
4965
4966         case RTL_GIGA_MAC_VER_12:
4967         case RTL_GIGA_MAC_VER_17:
4968                 rtl_hw_start_8168bef(ioaddr, pdev);
4969                 break;
4970
4971         case RTL_GIGA_MAC_VER_18:
4972                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4973                 break;
4974
4975         case RTL_GIGA_MAC_VER_19:
4976                 rtl_hw_start_8168c_1(ioaddr, pdev);
4977                 break;
4978
4979         case RTL_GIGA_MAC_VER_20:
4980                 rtl_hw_start_8168c_2(ioaddr, pdev);
4981                 break;
4982
4983         case RTL_GIGA_MAC_VER_21:
4984                 rtl_hw_start_8168c_3(ioaddr, pdev);
4985                 break;
4986
4987         case RTL_GIGA_MAC_VER_22:
4988                 rtl_hw_start_8168c_4(ioaddr, pdev);
4989                 break;
4990
4991         case RTL_GIGA_MAC_VER_23:
4992                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4993                 break;
4994
4995         case RTL_GIGA_MAC_VER_24:
4996                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4997                 break;
4998
4999         case RTL_GIGA_MAC_VER_25:
5000         case RTL_GIGA_MAC_VER_26:
5001         case RTL_GIGA_MAC_VER_27:
5002                 rtl_hw_start_8168d(ioaddr, pdev);
5003                 break;
5004
5005         case RTL_GIGA_MAC_VER_28:
5006                 rtl_hw_start_8168d_4(ioaddr, pdev);
5007                 break;
5008
5009         case RTL_GIGA_MAC_VER_31:
5010                 rtl_hw_start_8168dp(ioaddr, pdev);
5011                 break;
5012
5013         case RTL_GIGA_MAC_VER_32:
5014         case RTL_GIGA_MAC_VER_33:
5015                 rtl_hw_start_8168e_1(ioaddr, pdev);
5016                 break;
5017         case RTL_GIGA_MAC_VER_34:
5018                 rtl_hw_start_8168e_2(ioaddr, pdev);
5019                 break;
5020
5021         case RTL_GIGA_MAC_VER_35:
5022         case RTL_GIGA_MAC_VER_36:
5023                 rtl_hw_start_8168f_1(ioaddr, pdev);
5024                 break;
5025
5026         default:
5027                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5028                         dev->name, tp->mac_version);
5029                 break;
5030         }
5031
5032         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5033
5034         RTL_W8(Cfg9346, Cfg9346_Lock);
5035
5036         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5037
5038         RTL_W16(IntrMask, tp->intr_event);
5039 }
5040
5041 #define R810X_CPCMD_QUIRK_MASK (\
5042         EnableBist | \
5043         Mac_dbgo_oe | \
5044         Force_half_dup | \
5045         Force_rxflow_en | \
5046         Force_txflow_en | \
5047         Cxpl_dbg_sel | \
5048         ASF | \
5049         PktCntrDisable | \
5050         Mac_dbgo_sel)
5051
5052 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5053 {
5054         static const struct ephy_info e_info_8102e_1[] = {
5055                 { 0x01, 0, 0x6e65 },
5056                 { 0x02, 0, 0x091f },
5057                 { 0x03, 0, 0xc2f9 },
5058                 { 0x06, 0, 0xafb5 },
5059                 { 0x07, 0, 0x0e00 },
5060                 { 0x19, 0, 0xec80 },
5061                 { 0x01, 0, 0x2e65 },
5062                 { 0x01, 0, 0x6e65 }
5063         };
5064         u8 cfg1;
5065
5066         rtl_csi_access_enable_2(ioaddr);
5067
5068         RTL_W8(DBG_REG, FIX_NAK_1);
5069
5070         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5071
5072         RTL_W8(Config1,
5073                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5074         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5075
5076         cfg1 = RTL_R8(Config1);
5077         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5078                 RTL_W8(Config1, cfg1 & ~LEDS0);
5079
5080         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5081 }
5082
5083 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5084 {
5085         rtl_csi_access_enable_2(ioaddr);
5086
5087         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5088
5089         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5090         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5091 }
5092
5093 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
5094 {
5095         rtl_hw_start_8102e_2(ioaddr, pdev);
5096
5097         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
5098 }
5099
5100 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5101 {
5102         static const struct ephy_info e_info_8105e_1[] = {
5103                 { 0x07, 0, 0x4000 },
5104                 { 0x19, 0, 0x0200 },
5105                 { 0x19, 0, 0x0020 },
5106                 { 0x1e, 0, 0x2000 },
5107                 { 0x03, 0, 0x0001 },
5108                 { 0x19, 0, 0x0100 },
5109                 { 0x19, 0, 0x0004 },
5110                 { 0x0a, 0, 0x0020 }
5111         };
5112
5113         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5114         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5115
5116         /* Disable Early Tally Counter */
5117         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5118
5119         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5120         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5121
5122         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5123 }
5124
5125 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5126 {
5127         rtl_hw_start_8105e_1(ioaddr, pdev);
5128         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5129 }
5130
5131 static void rtl_hw_start_8101(struct net_device *dev)
5132 {
5133         struct rtl8169_private *tp = netdev_priv(dev);
5134         void __iomem *ioaddr = tp->mmio_addr;
5135         struct pci_dev *pdev = tp->pci_dev;
5136
5137         if (tp->mac_version >= RTL_GIGA_MAC_VER_30) {
5138                 tp->intr_event &= ~RxFIFOOver;
5139                 tp->napi_event &= ~RxFIFOOver;
5140         }
5141
5142         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5143             tp->mac_version == RTL_GIGA_MAC_VER_16) {
5144                 int cap = pci_pcie_cap(pdev);
5145
5146                 if (cap) {
5147                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5148                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
5149                 }
5150         }
5151
5152         RTL_W8(Cfg9346, Cfg9346_Unlock);
5153
5154         switch (tp->mac_version) {
5155         case RTL_GIGA_MAC_VER_07:
5156                 rtl_hw_start_8102e_1(ioaddr, pdev);
5157                 break;
5158
5159         case RTL_GIGA_MAC_VER_08:
5160                 rtl_hw_start_8102e_3(ioaddr, pdev);
5161                 break;
5162
5163         case RTL_GIGA_MAC_VER_09:
5164                 rtl_hw_start_8102e_2(ioaddr, pdev);
5165                 break;
5166
5167         case RTL_GIGA_MAC_VER_29:
5168                 rtl_hw_start_8105e_1(ioaddr, pdev);
5169                 break;
5170         case RTL_GIGA_MAC_VER_30:
5171                 rtl_hw_start_8105e_2(ioaddr, pdev);
5172                 break;
5173         }
5174
5175         RTL_W8(Cfg9346, Cfg9346_Lock);
5176
5177         RTL_W8(MaxTxPacketSize, TxPacketMax);
5178
5179         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5180
5181         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5182         RTL_W16(CPlusCmd, tp->cp_cmd);
5183
5184         RTL_W16(IntrMitigate, 0x0000);
5185
5186         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5187
5188         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5189         rtl_set_rx_tx_config_registers(tp);
5190
5191         RTL_R8(IntrMask);
5192
5193         rtl_set_rx_mode(dev);
5194
5195         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5196
5197         RTL_W16(IntrMask, tp->intr_event);
5198 }
5199
5200 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5201 {
5202         struct rtl8169_private *tp = netdev_priv(dev);
5203
5204         if (new_mtu < ETH_ZLEN ||
5205             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5206                 return -EINVAL;
5207
5208         if (new_mtu > ETH_DATA_LEN)
5209                 rtl_hw_jumbo_enable(tp);
5210         else
5211                 rtl_hw_jumbo_disable(tp);
5212
5213         dev->mtu = new_mtu;
5214         netdev_update_features(dev);
5215
5216         return 0;
5217 }
5218
5219 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5220 {
5221         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5222         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5223 }
5224
5225 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5226                                      void **data_buff, struct RxDesc *desc)
5227 {
5228         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5229                          DMA_FROM_DEVICE);
5230
5231         kfree(*data_buff);
5232         *data_buff = NULL;
5233         rtl8169_make_unusable_by_asic(desc);
5234 }
5235
5236 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5237 {
5238         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5239
5240         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5241 }
5242
5243 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5244                                        u32 rx_buf_sz)
5245 {
5246         desc->addr = cpu_to_le64(mapping);
5247         wmb();
5248         rtl8169_mark_to_asic(desc, rx_buf_sz);
5249 }
5250
5251 static inline void *rtl8169_align(void *data)
5252 {
5253         return (void *)ALIGN((long)data, 16);
5254 }
5255
5256 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5257                                              struct RxDesc *desc)
5258 {
5259         void *data;
5260         dma_addr_t mapping;
5261         struct device *d = &tp->pci_dev->dev;
5262         struct net_device *dev = tp->dev;
5263         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5264
5265         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5266         if (!data)
5267                 return NULL;
5268
5269         if (rtl8169_align(data) != data) {
5270                 kfree(data);
5271                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5272                 if (!data)
5273                         return NULL;
5274         }
5275
5276         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5277                                  DMA_FROM_DEVICE);
5278         if (unlikely(dma_mapping_error(d, mapping))) {
5279                 if (net_ratelimit())
5280                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5281                 goto err_out;
5282         }
5283
5284         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5285         return data;
5286
5287 err_out:
5288         kfree(data);
5289         return NULL;
5290 }
5291
5292 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5293 {
5294         unsigned int i;
5295
5296         for (i = 0; i < NUM_RX_DESC; i++) {
5297                 if (tp->Rx_databuff[i]) {
5298                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5299                                             tp->RxDescArray + i);
5300                 }
5301         }
5302 }
5303
5304 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5305 {
5306         desc->opts1 |= cpu_to_le32(RingEnd);
5307 }
5308
5309 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5310 {
5311         unsigned int i;
5312
5313         for (i = 0; i < NUM_RX_DESC; i++) {
5314                 void *data;
5315
5316                 if (tp->Rx_databuff[i])
5317                         continue;
5318
5319                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5320                 if (!data) {
5321                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5322                         goto err_out;
5323                 }
5324                 tp->Rx_databuff[i] = data;
5325         }
5326
5327         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5328         return 0;
5329
5330 err_out:
5331         rtl8169_rx_clear(tp);
5332         return -ENOMEM;
5333 }
5334
5335 static int rtl8169_init_ring(struct net_device *dev)
5336 {
5337         struct rtl8169_private *tp = netdev_priv(dev);
5338
5339         rtl8169_init_ring_indexes(tp);
5340
5341         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5342         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5343
5344         return rtl8169_rx_fill(tp);
5345 }
5346
5347 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5348                                  struct TxDesc *desc)
5349 {
5350         unsigned int len = tx_skb->len;
5351
5352         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5353
5354         desc->opts1 = 0x00;
5355         desc->opts2 = 0x00;
5356         desc->addr = 0x00;
5357         tx_skb->len = 0;
5358 }
5359
5360 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5361                                    unsigned int n)
5362 {
5363         unsigned int i;
5364
5365         for (i = 0; i < n; i++) {
5366                 unsigned int entry = (start + i) % NUM_TX_DESC;
5367                 struct ring_info *tx_skb = tp->tx_skb + entry;
5368                 unsigned int len = tx_skb->len;
5369
5370                 if (len) {
5371                         struct sk_buff *skb = tx_skb->skb;
5372
5373                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5374                                              tp->TxDescArray + entry);
5375                         if (skb) {
5376                                 tp->dev->stats.tx_dropped++;
5377                                 dev_kfree_skb(skb);
5378                                 tx_skb->skb = NULL;
5379                         }
5380                 }
5381         }
5382 }
5383
5384 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5385 {
5386         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5387         tp->cur_tx = tp->dirty_tx = 0;
5388 }
5389
5390 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
5391 {
5392         struct rtl8169_private *tp = netdev_priv(dev);
5393
5394         PREPARE_DELAYED_WORK(&tp->task, task);
5395         schedule_delayed_work(&tp->task, 4);
5396 }
5397
5398 static void rtl8169_wait_for_quiescence(struct net_device *dev)
5399 {
5400         struct rtl8169_private *tp = netdev_priv(dev);
5401         void __iomem *ioaddr = tp->mmio_addr;
5402
5403         synchronize_irq(dev->irq);
5404
5405         /* Wait for any pending NAPI task to complete */
5406         napi_disable(&tp->napi);
5407
5408         rtl8169_irq_mask_and_ack(tp);
5409
5410         tp->intr_mask = 0xffff;
5411         RTL_W16(IntrMask, tp->intr_event);
5412         napi_enable(&tp->napi);
5413 }
5414
5415 static void rtl8169_reinit_task(struct work_struct *work)
5416 {
5417         struct rtl8169_private *tp =
5418                 container_of(work, struct rtl8169_private, task.work);
5419         struct net_device *dev = tp->dev;
5420         int ret;
5421
5422         rtnl_lock();
5423
5424         if (!netif_running(dev))
5425                 goto out_unlock;
5426
5427         rtl8169_wait_for_quiescence(dev);
5428         rtl8169_close(dev);
5429
5430         ret = rtl8169_open(dev);
5431         if (unlikely(ret < 0)) {
5432                 if (net_ratelimit())
5433                         netif_err(tp, drv, dev,
5434                                   "reinit failure (status = %d). Rescheduling\n",
5435                                   ret);
5436                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
5437         }
5438
5439 out_unlock:
5440         rtnl_unlock();
5441 }
5442
5443 static void rtl8169_reset_task(struct work_struct *work)
5444 {
5445         struct rtl8169_private *tp =
5446                 container_of(work, struct rtl8169_private, task.work);
5447         struct net_device *dev = tp->dev;
5448         int i;
5449
5450         rtnl_lock();
5451
5452         if (!netif_running(dev))
5453                 goto out_unlock;
5454
5455         rtl8169_hw_reset(tp);
5456
5457         rtl8169_wait_for_quiescence(dev);
5458
5459         for (i = 0; i < NUM_RX_DESC; i++)
5460                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5461
5462         rtl8169_tx_clear(tp);
5463         rtl8169_init_ring_indexes(tp);
5464
5465         rtl_hw_start(dev);
5466         netif_wake_queue(dev);
5467         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5468
5469 out_unlock:
5470         rtnl_unlock();
5471 }
5472
5473 static void rtl8169_tx_timeout(struct net_device *dev)
5474 {
5475         rtl8169_schedule_work(dev, rtl8169_reset_task);
5476 }
5477
5478 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5479                               u32 *opts)
5480 {
5481         struct skb_shared_info *info = skb_shinfo(skb);
5482         unsigned int cur_frag, entry;
5483         struct TxDesc * uninitialized_var(txd);
5484         struct device *d = &tp->pci_dev->dev;
5485
5486         entry = tp->cur_tx;
5487         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5488                 const skb_frag_t *frag = info->frags + cur_frag;
5489                 dma_addr_t mapping;
5490                 u32 status, len;
5491                 void *addr;
5492
5493                 entry = (entry + 1) % NUM_TX_DESC;
5494
5495                 txd = tp->TxDescArray + entry;
5496                 len = skb_frag_size(frag);
5497                 addr = skb_frag_address(frag);
5498                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5499                 if (unlikely(dma_mapping_error(d, mapping))) {
5500                         if (net_ratelimit())
5501                                 netif_err(tp, drv, tp->dev,
5502                                           "Failed to map TX fragments DMA!\n");
5503                         goto err_out;
5504                 }
5505
5506                 /* Anti gcc 2.95.3 bugware (sic) */
5507                 status = opts[0] | len |
5508                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5509
5510                 txd->opts1 = cpu_to_le32(status);
5511                 txd->opts2 = cpu_to_le32(opts[1]);
5512                 txd->addr = cpu_to_le64(mapping);
5513
5514                 tp->tx_skb[entry].len = len;
5515         }
5516
5517         if (cur_frag) {
5518                 tp->tx_skb[entry].skb = skb;
5519                 txd->opts1 |= cpu_to_le32(LastFrag);
5520         }
5521
5522         return cur_frag;
5523
5524 err_out:
5525         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5526         return -EIO;
5527 }
5528
5529 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5530                                     struct sk_buff *skb, u32 *opts)
5531 {
5532         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5533         u32 mss = skb_shinfo(skb)->gso_size;
5534         int offset = info->opts_offset;
5535
5536         if (mss) {
5537                 opts[0] |= TD_LSO;
5538                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5539         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5540                 const struct iphdr *ip = ip_hdr(skb);
5541
5542                 if (ip->protocol == IPPROTO_TCP)
5543                         opts[offset] |= info->checksum.tcp;
5544                 else if (ip->protocol == IPPROTO_UDP)
5545                         opts[offset] |= info->checksum.udp;
5546                 else
5547                         WARN_ON_ONCE(1);
5548         }
5549 }
5550
5551 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5552                                       struct net_device *dev)
5553 {
5554         struct rtl8169_private *tp = netdev_priv(dev);
5555         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5556         struct TxDesc *txd = tp->TxDescArray + entry;
5557         void __iomem *ioaddr = tp->mmio_addr;
5558         struct device *d = &tp->pci_dev->dev;
5559         dma_addr_t mapping;
5560         u32 status, len;
5561         u32 opts[2];
5562         int frags;
5563
5564         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5565                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5566                 goto err_stop_0;
5567         }
5568
5569         /* 8168evl does not automatically pad to minimum length. */
5570         if (unlikely(tp->mac_version == RTL_GIGA_MAC_VER_34 &&
5571                      skb->len < ETH_ZLEN)) {
5572                 if (skb_padto(skb, ETH_ZLEN))
5573                         goto err_update_stats;
5574                 skb_put(skb, ETH_ZLEN - skb->len);
5575         }
5576
5577         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5578                 goto err_stop_0;
5579
5580         len = skb_headlen(skb);
5581         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5582         if (unlikely(dma_mapping_error(d, mapping))) {
5583                 if (net_ratelimit())
5584                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5585                 goto err_dma_0;
5586         }
5587
5588         tp->tx_skb[entry].len = len;
5589         txd->addr = cpu_to_le64(mapping);
5590
5591         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5592         opts[0] = DescOwn;
5593
5594         rtl8169_tso_csum(tp, skb, opts);
5595
5596         frags = rtl8169_xmit_frags(tp, skb, opts);
5597         if (frags < 0)
5598                 goto err_dma_1;
5599         else if (frags)
5600                 opts[0] |= FirstFrag;
5601         else {
5602                 opts[0] |= FirstFrag | LastFrag;
5603                 tp->tx_skb[entry].skb = skb;
5604         }
5605
5606         txd->opts2 = cpu_to_le32(opts[1]);
5607
5608         wmb();
5609
5610         /* Anti gcc 2.95.3 bugware (sic) */
5611         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5612         txd->opts1 = cpu_to_le32(status);
5613
5614         tp->cur_tx += frags + 1;
5615
5616         wmb();
5617
5618         RTL_W8(TxPoll, NPQ);
5619
5620         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5621                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5622                  * not miss a ring update when it notices a stopped queue.
5623                  */
5624                 smp_wmb();
5625                 netif_stop_queue(dev);
5626                 /* Sync with rtl_tx:
5627                  * - publish queue status and cur_tx ring index (write barrier)
5628                  * - refresh dirty_tx ring index (read barrier).
5629                  * May the current thread have a pessimistic view of the ring
5630                  * status and forget to wake up queue, a racing rtl_tx thread
5631                  * can't.
5632                  */
5633                 smp_mb();
5634                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5635                         netif_wake_queue(dev);
5636         }
5637
5638         return NETDEV_TX_OK;
5639
5640 err_dma_1:
5641         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5642 err_dma_0:
5643         dev_kfree_skb(skb);
5644 err_update_stats:
5645         dev->stats.tx_dropped++;
5646         return NETDEV_TX_OK;
5647
5648 err_stop_0:
5649         netif_stop_queue(dev);
5650         dev->stats.tx_dropped++;
5651         return NETDEV_TX_BUSY;
5652 }
5653
5654 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5655 {
5656         struct rtl8169_private *tp = netdev_priv(dev);
5657         struct pci_dev *pdev = tp->pci_dev;
5658         u16 pci_status, pci_cmd;
5659
5660         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5661         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5662
5663         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5664                   pci_cmd, pci_status);
5665
5666         /*
5667          * The recovery sequence below admits a very elaborated explanation:
5668          * - it seems to work;
5669          * - I did not see what else could be done;
5670          * - it makes iop3xx happy.
5671          *
5672          * Feel free to adjust to your needs.
5673          */
5674         if (pdev->broken_parity_status)
5675                 pci_cmd &= ~PCI_COMMAND_PARITY;
5676         else
5677                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5678
5679         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5680
5681         pci_write_config_word(pdev, PCI_STATUS,
5682                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5683                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5684                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5685
5686         /* The infamous DAC f*ckup only happens at boot time */
5687         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5688                 void __iomem *ioaddr = tp->mmio_addr;
5689
5690                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5691                 tp->cp_cmd &= ~PCIDAC;
5692                 RTL_W16(CPlusCmd, tp->cp_cmd);
5693                 dev->features &= ~NETIF_F_HIGHDMA;
5694         }
5695
5696         rtl8169_hw_reset(tp);
5697
5698         rtl8169_schedule_work(dev, rtl8169_reinit_task);
5699 }
5700
5701 static void rtl8169_tx_interrupt(struct net_device *dev,
5702                                  struct rtl8169_private *tp,
5703                                  void __iomem *ioaddr)
5704 {
5705         unsigned int dirty_tx, tx_left;
5706
5707         dirty_tx = tp->dirty_tx;
5708         smp_rmb();
5709         tx_left = tp->cur_tx - dirty_tx;
5710
5711         while (tx_left > 0) {
5712                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5713                 struct ring_info *tx_skb = tp->tx_skb + entry;
5714                 u32 status;
5715
5716                 rmb();
5717                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5718                 if (status & DescOwn)
5719                         break;
5720
5721                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5722                                      tp->TxDescArray + entry);
5723                 if (status & LastFrag) {
5724                         dev->stats.tx_packets++;
5725                         dev->stats.tx_bytes += tx_skb->skb->len;
5726                         dev_kfree_skb(tx_skb->skb);
5727                         tx_skb->skb = NULL;
5728                 }
5729                 dirty_tx++;
5730                 tx_left--;
5731         }
5732
5733         if (tp->dirty_tx != dirty_tx) {
5734                 tp->dirty_tx = dirty_tx;
5735                 /* Sync with rtl8169_start_xmit:
5736                  * - publish dirty_tx ring index (write barrier)
5737                  * - refresh cur_tx ring index and queue status (read barrier)
5738                  * May the current thread miss the stopped queue condition,
5739                  * a racing xmit thread can only have a right view of the
5740                  * ring status.
5741                  */
5742                 smp_mb();
5743                 if (netif_queue_stopped(dev) &&
5744                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5745                         netif_wake_queue(dev);
5746                 }
5747                 /*
5748                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5749                  * too close. Let's kick an extra TxPoll request when a burst
5750                  * of start_xmit activity is detected (if it is not detected,
5751                  * it is slow enough). -- FR
5752                  */
5753                 if (tp->cur_tx != dirty_tx)
5754                         RTL_W8(TxPoll, NPQ);
5755         }
5756 }
5757
5758 static inline int rtl8169_fragmented_frame(u32 status)
5759 {
5760         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5761 }
5762
5763 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5764 {
5765         u32 status = opts1 & RxProtoMask;
5766
5767         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5768             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5769                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5770         else
5771                 skb_checksum_none_assert(skb);
5772 }
5773
5774 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5775                                            struct rtl8169_private *tp,
5776                                            int pkt_size,
5777                                            dma_addr_t addr)
5778 {
5779         struct sk_buff *skb;
5780         struct device *d = &tp->pci_dev->dev;
5781
5782         data = rtl8169_align(data);
5783         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5784         prefetch(data);
5785         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5786         if (skb)
5787                 memcpy(skb->data, data, pkt_size);
5788         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5789
5790         return skb;
5791 }
5792
5793 static int rtl8169_rx_interrupt(struct net_device *dev,
5794                                 struct rtl8169_private *tp,
5795                                 void __iomem *ioaddr, u32 budget)
5796 {
5797         unsigned int cur_rx, rx_left;
5798         unsigned int count;
5799
5800         cur_rx = tp->cur_rx;
5801         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5802         rx_left = min(rx_left, budget);
5803
5804         for (; rx_left > 0; rx_left--, cur_rx++) {
5805                 unsigned int entry = cur_rx % NUM_RX_DESC;
5806                 struct RxDesc *desc = tp->RxDescArray + entry;
5807                 u32 status;
5808
5809                 rmb();
5810                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5811
5812                 if (status & DescOwn)
5813                         break;
5814                 if (unlikely(status & RxRES)) {
5815                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5816                                    status);
5817                         dev->stats.rx_errors++;
5818                         if (status & (RxRWT | RxRUNT))
5819                                 dev->stats.rx_length_errors++;
5820                         if (status & RxCRC)
5821                                 dev->stats.rx_crc_errors++;
5822                         if (status & RxFOVF) {
5823                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5824                                 dev->stats.rx_fifo_errors++;
5825                         }
5826                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5827                 } else {
5828                         struct sk_buff *skb;
5829                         dma_addr_t addr = le64_to_cpu(desc->addr);
5830                         int pkt_size = (status & 0x00003fff) - 4;
5831
5832                         /*
5833                          * The driver does not support incoming fragmented
5834                          * frames. They are seen as a symptom of over-mtu
5835                          * sized frames.
5836                          */
5837                         if (unlikely(rtl8169_fragmented_frame(status))) {
5838                                 dev->stats.rx_dropped++;
5839                                 dev->stats.rx_length_errors++;
5840                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5841                                 continue;
5842                         }
5843
5844                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5845                                                   tp, pkt_size, addr);
5846                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5847                         if (!skb) {
5848                                 dev->stats.rx_dropped++;
5849                                 continue;
5850                         }
5851
5852                         rtl8169_rx_csum(skb, status);
5853                         skb_put(skb, pkt_size);
5854                         skb->protocol = eth_type_trans(skb, dev);
5855
5856                         rtl8169_rx_vlan_tag(desc, skb);
5857
5858                         napi_gro_receive(&tp->napi, skb);
5859
5860                         dev->stats.rx_bytes += pkt_size;
5861                         dev->stats.rx_packets++;
5862                 }
5863         }
5864
5865         count = cur_rx - tp->cur_rx;
5866         tp->cur_rx = cur_rx;
5867
5868         tp->dirty_rx += count;
5869
5870         return count;
5871 }
5872
5873 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5874 {
5875         struct net_device *dev = dev_instance;
5876         struct rtl8169_private *tp = netdev_priv(dev);
5877         void __iomem *ioaddr = tp->mmio_addr;
5878         int handled = 0;
5879         int status;
5880
5881         /* loop handling interrupts until we have no new ones or
5882          * we hit a invalid/hotplug case.
5883          */
5884         status = RTL_R16(IntrStatus);
5885         while (status && status != 0xffff) {
5886                 status &= tp->intr_event;
5887                 if (!status)
5888                         break;
5889
5890                 handled = 1;
5891
5892                 /* Handle all of the error cases first. These will reset
5893                  * the chip, so just exit the loop.
5894                  */
5895                 if (unlikely(!netif_running(dev))) {
5896                         rtl8169_hw_reset(tp);
5897                         break;
5898                 }
5899
5900                 if (unlikely(status & RxFIFOOver)) {
5901                         switch (tp->mac_version) {
5902                         /* Work around for rx fifo overflow */
5903                         case RTL_GIGA_MAC_VER_11:
5904                                 netif_stop_queue(dev);
5905                                 rtl8169_tx_timeout(dev);
5906                                 goto done;
5907                         default:
5908                                 break;
5909                         }
5910                 }
5911
5912                 if (unlikely(status & SYSErr)) {
5913                         rtl8169_pcierr_interrupt(dev);
5914                         break;
5915                 }
5916
5917                 if (status & LinkChg)
5918                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5919
5920                 /* We need to see the lastest version of tp->intr_mask to
5921                  * avoid ignoring an MSI interrupt and having to wait for
5922                  * another event which may never come.
5923                  */
5924                 smp_rmb();
5925                 if (status & tp->intr_mask & tp->napi_event) {
5926                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5927                         tp->intr_mask = ~tp->napi_event;
5928
5929                         if (likely(napi_schedule_prep(&tp->napi)))
5930                                 __napi_schedule(&tp->napi);
5931                         else
5932                                 netif_info(tp, intr, dev,
5933                                            "interrupt %04x in poll\n", status);
5934                 }
5935
5936                 /* We only get a new MSI interrupt when all active irq
5937                  * sources on the chip have been acknowledged. So, ack
5938                  * everything we've seen and check if new sources have become
5939                  * active to avoid blocking all interrupts from the chip.
5940                  */
5941                 RTL_W16(IntrStatus,
5942                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5943                 status = RTL_R16(IntrStatus);
5944         }
5945 done:
5946         return IRQ_RETVAL(handled);
5947 }
5948
5949 static int rtl8169_poll(struct napi_struct *napi, int budget)
5950 {
5951         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5952         struct net_device *dev = tp->dev;
5953         void __iomem *ioaddr = tp->mmio_addr;
5954         int work_done;
5955
5956         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5957         rtl8169_tx_interrupt(dev, tp, ioaddr);
5958
5959         if (work_done < budget) {
5960                 napi_complete(napi);
5961
5962                 /* We need for force the visibility of tp->intr_mask
5963                  * for other CPUs, as we can loose an MSI interrupt
5964                  * and potentially wait for a retransmit timeout if we don't.
5965                  * The posted write to IntrMask is safe, as it will
5966                  * eventually make it to the chip and we won't loose anything
5967                  * until it does.
5968                  */
5969                 tp->intr_mask = 0xffff;
5970                 wmb();
5971                 RTL_W16(IntrMask, tp->intr_event);
5972         }
5973
5974         return work_done;
5975 }
5976
5977 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5978 {
5979         struct rtl8169_private *tp = netdev_priv(dev);
5980
5981         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5982                 return;
5983
5984         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5985         RTL_W32(RxMissed, 0);
5986 }
5987
5988 static void rtl8169_down(struct net_device *dev)
5989 {
5990         struct rtl8169_private *tp = netdev_priv(dev);
5991         void __iomem *ioaddr = tp->mmio_addr;
5992
5993         del_timer_sync(&tp->timer);
5994
5995         netif_stop_queue(dev);
5996
5997         napi_disable(&tp->napi);
5998
5999         spin_lock_irq(&tp->lock);
6000
6001         rtl8169_hw_reset(tp);
6002         /*
6003          * At this point device interrupts can not be enabled in any function,
6004          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
6005          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
6006          */
6007         rtl8169_rx_missed(dev, ioaddr);
6008
6009         spin_unlock_irq(&tp->lock);
6010
6011         synchronize_irq(dev->irq);
6012
6013         /* Give a racing hard_start_xmit a few cycles to complete. */
6014         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
6015
6016         rtl8169_tx_clear(tp);
6017
6018         rtl8169_rx_clear(tp);
6019
6020         rtl_pll_power_down(tp);
6021 }
6022
6023 static int rtl8169_close(struct net_device *dev)
6024 {
6025         struct rtl8169_private *tp = netdev_priv(dev);
6026         struct pci_dev *pdev = tp->pci_dev;
6027
6028         pm_runtime_get_sync(&pdev->dev);
6029
6030         /* Update counters before going down */
6031         rtl8169_update_counters(dev);
6032
6033         rtl8169_down(dev);
6034
6035         free_irq(dev->irq, dev);
6036
6037         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6038                           tp->RxPhyAddr);
6039         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6040                           tp->TxPhyAddr);
6041         tp->TxDescArray = NULL;
6042         tp->RxDescArray = NULL;
6043
6044         pm_runtime_put_sync(&pdev->dev);
6045
6046         return 0;
6047 }
6048
6049 static void rtl_set_rx_mode(struct net_device *dev)
6050 {
6051         struct rtl8169_private *tp = netdev_priv(dev);
6052         void __iomem *ioaddr = tp->mmio_addr;
6053         unsigned long flags;
6054         u32 mc_filter[2];       /* Multicast hash filter */
6055         int rx_mode;
6056         u32 tmp = 0;
6057
6058         if (dev->flags & IFF_PROMISC) {
6059                 /* Unconditionally log net taps. */
6060                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
6061                 rx_mode =
6062                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
6063                     AcceptAllPhys;
6064                 mc_filter[1] = mc_filter[0] = 0xffffffff;
6065         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
6066                    (dev->flags & IFF_ALLMULTI)) {
6067                 /* Too many to filter perfectly -- accept all multicasts. */
6068                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
6069                 mc_filter[1] = mc_filter[0] = 0xffffffff;
6070         } else {
6071                 struct netdev_hw_addr *ha;
6072
6073                 rx_mode = AcceptBroadcast | AcceptMyPhys;
6074                 mc_filter[1] = mc_filter[0] = 0;
6075                 netdev_for_each_mc_addr(ha, dev) {
6076                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
6077                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
6078                         rx_mode |= AcceptMulticast;
6079                 }
6080         }
6081
6082         spin_lock_irqsave(&tp->lock, flags);
6083
6084         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
6085
6086         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
6087                 u32 data = mc_filter[0];
6088
6089                 mc_filter[0] = swab32(mc_filter[1]);
6090                 mc_filter[1] = swab32(data);
6091         }
6092
6093         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
6094                 mc_filter[1] = mc_filter[0] = 0xffffffff;
6095
6096         RTL_W32(MAR0 + 4, mc_filter[1]);
6097         RTL_W32(MAR0 + 0, mc_filter[0]);
6098
6099         RTL_W32(RxConfig, tmp);
6100
6101         spin_unlock_irqrestore(&tp->lock, flags);
6102 }
6103
6104 /**
6105  *  rtl8169_get_stats - Get rtl8169 read/write statistics
6106  *  @dev: The Ethernet Device to get statistics for
6107  *
6108  *  Get TX/RX statistics for rtl8169
6109  */
6110 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
6111 {
6112         struct rtl8169_private *tp = netdev_priv(dev);
6113         void __iomem *ioaddr = tp->mmio_addr;
6114         unsigned long flags;
6115
6116         if (netif_running(dev)) {
6117                 spin_lock_irqsave(&tp->lock, flags);
6118                 rtl8169_rx_missed(dev, ioaddr);
6119                 spin_unlock_irqrestore(&tp->lock, flags);
6120         }
6121
6122         return &dev->stats;
6123 }
6124
6125 static void rtl8169_net_suspend(struct net_device *dev)
6126 {
6127         struct rtl8169_private *tp = netdev_priv(dev);
6128
6129         if (!netif_running(dev))
6130                 return;
6131
6132         rtl_pll_power_down(tp);
6133
6134         netif_device_detach(dev);
6135         netif_stop_queue(dev);
6136 }
6137
6138 #ifdef CONFIG_PM
6139
6140 static int rtl8169_suspend(struct device *device)
6141 {
6142         struct pci_dev *pdev = to_pci_dev(device);
6143         struct net_device *dev = pci_get_drvdata(pdev);
6144
6145         rtl8169_net_suspend(dev);
6146
6147         return 0;
6148 }
6149
6150 static void __rtl8169_resume(struct net_device *dev)
6151 {
6152         struct rtl8169_private *tp = netdev_priv(dev);
6153
6154         netif_device_attach(dev);
6155
6156         rtl_pll_power_up(tp);
6157
6158         rtl8169_schedule_work(dev, rtl8169_reset_task);
6159 }
6160
6161 static int rtl8169_resume(struct device *device)
6162 {
6163         struct pci_dev *pdev = to_pci_dev(device);
6164         struct net_device *dev = pci_get_drvdata(pdev);
6165         struct rtl8169_private *tp = netdev_priv(dev);
6166
6167         rtl8169_init_phy(dev, tp);
6168
6169         if (netif_running(dev))
6170                 __rtl8169_resume(dev);
6171
6172         return 0;
6173 }
6174
6175 static int rtl8169_runtime_suspend(struct device *device)
6176 {
6177         struct pci_dev *pdev = to_pci_dev(device);
6178         struct net_device *dev = pci_get_drvdata(pdev);
6179         struct rtl8169_private *tp = netdev_priv(dev);
6180
6181         if (!tp->TxDescArray)
6182                 return 0;
6183
6184         spin_lock_irq(&tp->lock);
6185         tp->saved_wolopts = __rtl8169_get_wol(tp);
6186         __rtl8169_set_wol(tp, WAKE_ANY);
6187         spin_unlock_irq(&tp->lock);
6188
6189         rtl8169_net_suspend(dev);
6190
6191         return 0;
6192 }
6193
6194 static int rtl8169_runtime_resume(struct device *device)
6195 {
6196         struct pci_dev *pdev = to_pci_dev(device);
6197         struct net_device *dev = pci_get_drvdata(pdev);
6198         struct rtl8169_private *tp = netdev_priv(dev);
6199
6200         if (!tp->TxDescArray)
6201                 return 0;
6202
6203         spin_lock_irq(&tp->lock);
6204         __rtl8169_set_wol(tp, tp->saved_wolopts);
6205         tp->saved_wolopts = 0;
6206         spin_unlock_irq(&tp->lock);
6207
6208         rtl8169_init_phy(dev, tp);
6209
6210         __rtl8169_resume(dev);
6211
6212         return 0;
6213 }
6214
6215 static int rtl8169_runtime_idle(struct device *device)
6216 {
6217         struct pci_dev *pdev = to_pci_dev(device);
6218         struct net_device *dev = pci_get_drvdata(pdev);
6219         struct rtl8169_private *tp = netdev_priv(dev);
6220
6221         return tp->TxDescArray ? -EBUSY : 0;
6222 }
6223
6224 static const struct dev_pm_ops rtl8169_pm_ops = {
6225         .suspend                = rtl8169_suspend,
6226         .resume                 = rtl8169_resume,
6227         .freeze                 = rtl8169_suspend,
6228         .thaw                   = rtl8169_resume,
6229         .poweroff               = rtl8169_suspend,
6230         .restore                = rtl8169_resume,
6231         .runtime_suspend        = rtl8169_runtime_suspend,
6232         .runtime_resume         = rtl8169_runtime_resume,
6233         .runtime_idle           = rtl8169_runtime_idle,
6234 };
6235
6236 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6237
6238 #else /* !CONFIG_PM */
6239
6240 #define RTL8169_PM_OPS  NULL
6241
6242 #endif /* !CONFIG_PM */
6243
6244 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6245 {
6246         void __iomem *ioaddr = tp->mmio_addr;
6247
6248         /* WoL fails with 8168b when the receiver is disabled. */
6249         switch (tp->mac_version) {
6250         case RTL_GIGA_MAC_VER_11:
6251         case RTL_GIGA_MAC_VER_12:
6252         case RTL_GIGA_MAC_VER_17:
6253                 pci_clear_master(tp->pci_dev);
6254
6255                 RTL_W8(ChipCmd, CmdRxEnb);
6256                 /* PCI commit */
6257                 RTL_R8(ChipCmd);
6258                 break;
6259         default:
6260                 break;
6261         }
6262 }
6263
6264 static void rtl_shutdown(struct pci_dev *pdev)
6265 {
6266         struct net_device *dev = pci_get_drvdata(pdev);
6267         struct rtl8169_private *tp = netdev_priv(dev);
6268         struct device *d = &pdev->dev;
6269
6270         pm_runtime_get_sync(d);
6271
6272         rtl8169_net_suspend(dev);
6273
6274         /* Restore original MAC address */
6275         rtl_rar_set(tp, dev->perm_addr);
6276
6277         spin_lock_irq(&tp->lock);
6278
6279         rtl8169_hw_reset(tp);
6280
6281         spin_unlock_irq(&tp->lock);
6282
6283         if (system_state == SYSTEM_POWER_OFF) {
6284                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6285                         rtl_wol_suspend_quirk(tp);
6286                         rtl_wol_shutdown_quirk(tp);
6287                 }
6288
6289                 pci_wake_from_d3(pdev, true);
6290                 pci_set_power_state(pdev, PCI_D3hot);
6291         }
6292
6293         pm_runtime_put_noidle(d);
6294 }
6295
6296 static struct pci_driver rtl8169_pci_driver = {
6297         .name           = MODULENAME,
6298         .id_table       = rtl8169_pci_tbl,
6299         .probe          = rtl8169_init_one,
6300         .remove         = __devexit_p(rtl8169_remove_one),
6301         .shutdown       = rtl_shutdown,
6302         .driver.pm      = RTL8169_PM_OPS,
6303 };
6304
6305 static int __init rtl8169_init_module(void)
6306 {
6307         return pci_register_driver(&rtl8169_pci_driver);
6308 }
6309
6310 static void __exit rtl8169_cleanup_module(void)
6311 {
6312         pci_unregister_driver(&rtl8169_pci_driver);
6313 }
6314
6315 module_init(rtl8169_init_module);
6316 module_exit(rtl8169_cleanup_module);