drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48
  49 #ifdef RTL8169_DEBUG
  50 #define assert(expr) \
  51         if (!(expr)) {                                  \
  52                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  53                 #expr,__FILE__,__func__,__LINE__);              \
  54         }
  55 #define dprintk(fmt, args...) \
  56         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  57 #else
  58 #define assert(expr) do {} while (0)
  59 #define dprintk(fmt, args...)   do {} while (0)
  60 #endif /* RTL8169_DEBUG */
  61
  62 #define R8169_MSG_DEFAULT \
  63         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  64
  65 #define TX_SLOTS_AVAIL(tp) \
  66         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  67
  68 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  69 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  70         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  71
  72 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  73    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  74 static const int multicast_filter_limit = 32;
  75
  76 /* MAC address length */
  77 #define MAC_ADDR_LEN    6
  78
  79 #define MAX_READ_REQUEST_SHIFT  12
  80 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  81 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  82 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  83
  84 #define R8169_REGS_SIZE         256
  85 #define R8169_NAPI_WEIGHT       64
  86 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  87 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  88 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  89 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  90 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  91
  92 #define RTL8169_TX_TIMEOUT      (6*HZ)
  93 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  94
  95 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  96 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  97 #define RTL_EEPROM_SIG_ADDR     0x0000
  98
  99 /* write/read MMIO register */
 100 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 101 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 102 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 103 #define RTL_R8(reg)             readb (ioaddr + (reg))
 104 #define RTL_R16(reg)            readw (ioaddr + (reg))
 105 #define RTL_R32(reg)            readl (ioaddr + (reg))
 106
 107 enum mac_version {
 108         RTL_GIGA_MAC_VER_01 = 0,
 109         RTL_GIGA_MAC_VER_02,
 110         RTL_GIGA_MAC_VER_03,
 111         RTL_GIGA_MAC_VER_04,
 112         RTL_GIGA_MAC_VER_05,
 113         RTL_GIGA_MAC_VER_06,
 114         RTL_GIGA_MAC_VER_07,
 115         RTL_GIGA_MAC_VER_08,
 116         RTL_GIGA_MAC_VER_09,
 117         RTL_GIGA_MAC_VER_10,
 118         RTL_GIGA_MAC_VER_11,
 119         RTL_GIGA_MAC_VER_12,
 120         RTL_GIGA_MAC_VER_13,
 121         RTL_GIGA_MAC_VER_14,
 122         RTL_GIGA_MAC_VER_15,
 123         RTL_GIGA_MAC_VER_16,
 124         RTL_GIGA_MAC_VER_17,
 125         RTL_GIGA_MAC_VER_18,
 126         RTL_GIGA_MAC_VER_19,
 127         RTL_GIGA_MAC_VER_20,
 128         RTL_GIGA_MAC_VER_21,
 129         RTL_GIGA_MAC_VER_22,
 130         RTL_GIGA_MAC_VER_23,
 131         RTL_GIGA_MAC_VER_24,
 132         RTL_GIGA_MAC_VER_25,
 133         RTL_GIGA_MAC_VER_26,
 134         RTL_GIGA_MAC_VER_27,
 135         RTL_GIGA_MAC_VER_28,
 136         RTL_GIGA_MAC_VER_29,
 137         RTL_GIGA_MAC_VER_30,
 138         RTL_GIGA_MAC_VER_31,
 139         RTL_GIGA_MAC_VER_32,
 140         RTL_GIGA_MAC_VER_33,
 141         RTL_GIGA_MAC_VER_34,
 142         RTL_GIGA_MAC_VER_35,
 143         RTL_GIGA_MAC_VER_36,
 144         RTL_GIGA_MAC_NONE   = 0xff,
 145 };
 146
 147 enum rtl_tx_desc_version {
 148         RTL_TD_0        = 0,
 149         RTL_TD_1        = 1,
 150 };
 151
 152 #define JUMBO_1K        ETH_DATA_LEN
 153 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 154 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 155 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 156 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 157
 158 #define _R(NAME,TD,FW,SZ,B) {   \
 159         .name = NAME,           \
 160         .txd_version = TD,      \
 161         .fw_name = FW,          \
 162         .jumbo_max = SZ,        \
 163         .jumbo_tx_csum = B      \
 164 }
 165
 166 static const struct {
 167         const char *name;
 168         enum rtl_tx_desc_version txd_version;
 169         const char *fw_name;
 170         u16 jumbo_max;
 171         bool jumbo_tx_csum;
 172 } rtl_chip_infos[] = {
 173         /* PCI devices. */
 174         [RTL_GIGA_MAC_VER_01] =
 175                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 176         [RTL_GIGA_MAC_VER_02] =
 177                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 178         [RTL_GIGA_MAC_VER_03] =
 179                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 180         [RTL_GIGA_MAC_VER_04] =
 181                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 182         [RTL_GIGA_MAC_VER_05] =
 183                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 184         [RTL_GIGA_MAC_VER_06] =
 185                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 186         /* PCI-E devices. */
 187         [RTL_GIGA_MAC_VER_07] =
 188                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 189         [RTL_GIGA_MAC_VER_08] =
 190                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 191         [RTL_GIGA_MAC_VER_09] =
 192                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 193         [RTL_GIGA_MAC_VER_10] =
 194                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 195         [RTL_GIGA_MAC_VER_11] =
 196                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 197         [RTL_GIGA_MAC_VER_12] =
 198                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 199         [RTL_GIGA_MAC_VER_13] =
 200                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 201         [RTL_GIGA_MAC_VER_14] =
 202                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 203         [RTL_GIGA_MAC_VER_15] =
 204                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 205         [RTL_GIGA_MAC_VER_16] =
 206                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 207         [RTL_GIGA_MAC_VER_17] =
 208                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 209         [RTL_GIGA_MAC_VER_18] =
 210                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 211         [RTL_GIGA_MAC_VER_19] =
 212                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 213         [RTL_GIGA_MAC_VER_20] =
 214                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 215         [RTL_GIGA_MAC_VER_21] =
 216                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 217         [RTL_GIGA_MAC_VER_22] =
 218                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 219         [RTL_GIGA_MAC_VER_23] =
 220                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 221         [RTL_GIGA_MAC_VER_24] =
 222                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 223         [RTL_GIGA_MAC_VER_25] =
 224                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 225                                                         JUMBO_9K, false),
 226         [RTL_GIGA_MAC_VER_26] =
 227                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 228                                                         JUMBO_9K, false),
 229         [RTL_GIGA_MAC_VER_27] =
 230                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 231         [RTL_GIGA_MAC_VER_28] =
 232                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 233         [RTL_GIGA_MAC_VER_29] =
 234                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 235                                                         JUMBO_1K, true),
 236         [RTL_GIGA_MAC_VER_30] =
 237                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 238                                                         JUMBO_1K, true),
 239         [RTL_GIGA_MAC_VER_31] =
 240                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 241         [RTL_GIGA_MAC_VER_32] =
 242                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 243                                                         JUMBO_9K, false),
 244         [RTL_GIGA_MAC_VER_33] =
 245                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 246                                                         JUMBO_9K, false),
 247         [RTL_GIGA_MAC_VER_34] =
 248                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 249                                                         JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_35] =
 251                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 252                                                         JUMBO_9K, false),
 253         [RTL_GIGA_MAC_VER_36] =
 254                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 255                                                         JUMBO_9K, false),
 256 };
 257 #undef _R
 258
 259 enum cfg_version {
 260         RTL_CFG_0 = 0x00,
 261         RTL_CFG_1,
 262         RTL_CFG_2
 263 };
 264
 265 static void rtl_hw_start_8169(struct net_device *);
 266 static void rtl_hw_start_8168(struct net_device *);
 267 static void rtl_hw_start_8101(struct net_device *);
 268
 269 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 270         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 271         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 272         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 273         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 274         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 275         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 276         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 277         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 278         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 279         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 280                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 281         { 0x0001,                               0x8168,
 282                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 283         {0,},
 284 };
 285
 286 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 287
 288 static int rx_buf_sz = 16383;
 289 static int use_dac;
 290 static struct {
 291         u32 msg_enable;
 292 } debug = { -1 };
 293
 294 enum rtl_registers {
 295         MAC0            = 0,    /* Ethernet hardware address. */
 296         MAC4            = 4,
 297         MAR0            = 8,    /* Multicast filter. */
 298         CounterAddrLow          = 0x10,
 299         CounterAddrHigh         = 0x14,
 300         TxDescStartAddrLow      = 0x20,
 301         TxDescStartAddrHigh     = 0x24,
 302         TxHDescStartAddrLow     = 0x28,
 303         TxHDescStartAddrHigh    = 0x2c,
 304         FLASH           = 0x30,
 305         ERSR            = 0x36,
 306         ChipCmd         = 0x37,
 307         TxPoll          = 0x38,
 308         IntrMask        = 0x3c,
 309         IntrStatus      = 0x3e,
 310
 311         TxConfig        = 0x40,
 312 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 313 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 314
 315         RxConfig        = 0x44,
 316 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 317 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 318 #define RXCFG_FIFO_SHIFT                13
 319                                         /* No threshold before first PCI xfer */
 320 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 321 #define RXCFG_DMA_SHIFT                 8
 322                                         /* Unlimited maximum PCI burst. */
 323 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 324
 325         RxMissed        = 0x4c,
 326         Cfg9346         = 0x50,
 327         Config0         = 0x51,
 328         Config1         = 0x52,
 329         Config2         = 0x53,
 330 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 331
 332         Config3         = 0x54,
 333         Config4         = 0x55,
 334         Config5         = 0x56,
 335         MultiIntr       = 0x5c,
 336         PHYAR           = 0x60,
 337         PHYstatus       = 0x6c,
 338         RxMaxSize       = 0xda,
 339         CPlusCmd        = 0xe0,
 340         IntrMitigate    = 0xe2,
 341         RxDescAddrLow   = 0xe4,
 342         RxDescAddrHigh  = 0xe8,
 343         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 344
 345 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 346
 347         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 348
 349 #define TxPacketMax     (8064 >> 7)
 350 #define EarlySize       0x27
 351
 352         FuncEvent       = 0xf0,
 353         FuncEventMask   = 0xf4,
 354         FuncPresetState = 0xf8,
 355         FuncForceEvent  = 0xfc,
 356 };
 357
 358 enum rtl8110_registers {
 359         TBICSR                  = 0x64,
 360         TBI_ANAR                = 0x68,
 361         TBI_LPAR                = 0x6a,
 362 };
 363
 364 enum rtl8168_8101_registers {
 365         CSIDR                   = 0x64,
 366         CSIAR                   = 0x68,
 367 #define CSIAR_FLAG                      0x80000000
 368 #define CSIAR_WRITE_CMD                 0x80000000
 369 #define CSIAR_BYTE_ENABLE               0x0f
 370 #define CSIAR_BYTE_ENABLE_SHIFT         12
 371 #define CSIAR_ADDR_MASK                 0x0fff
 372         PMCH                    = 0x6f,
 373         EPHYAR                  = 0x80,
 374 #define EPHYAR_FLAG                     0x80000000
 375 #define EPHYAR_WRITE_CMD                0x80000000
 376 #define EPHYAR_REG_MASK                 0x1f
 377 #define EPHYAR_REG_SHIFT                16
 378 #define EPHYAR_DATA_MASK                0xffff
 379         DLLPR                   = 0xd0,
 380 #define PFM_EN                          (1 << 6)
 381         DBG_REG                 = 0xd1,
 382 #define FIX_NAK_1                       (1 << 4)
 383 #define FIX_NAK_2                       (1 << 3)
 384         TWSI                    = 0xd2,
 385         MCU                     = 0xd3,
 386 #define NOW_IS_OOB                      (1 << 7)
 387 #define EN_NDP                          (1 << 3)
 388 #define EN_OOB_RESET                    (1 << 2)
 389         EFUSEAR                 = 0xdc,
 390 #define EFUSEAR_FLAG                    0x80000000
 391 #define EFUSEAR_WRITE_CMD               0x80000000
 392 #define EFUSEAR_READ_CMD                0x00000000
 393 #define EFUSEAR_REG_MASK                0x03ff
 394 #define EFUSEAR_REG_SHIFT               8
 395 #define EFUSEAR_DATA_MASK               0xff
 396 };
 397
 398 enum rtl8168_registers {
 399         LED_FREQ                = 0x1a,
 400         EEE_LED                 = 0x1b,
 401         ERIDR                   = 0x70,
 402         ERIAR                   = 0x74,
 403 #define ERIAR_FLAG                      0x80000000
 404 #define ERIAR_WRITE_CMD                 0x80000000
 405 #define ERIAR_READ_CMD                  0x00000000
 406 #define ERIAR_ADDR_BYTE_ALIGN           4
 407 #define ERIAR_TYPE_SHIFT                16
 408 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 409 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 410 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 411 #define ERIAR_MASK_SHIFT                12
 412 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 413 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 414 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 415         EPHY_RXER_NUM           = 0x7c,
 416         OCPDR                   = 0xb0, /* OCP GPHY access */
 417 #define OCPDR_WRITE_CMD                 0x80000000
 418 #define OCPDR_READ_CMD                  0x00000000
 419 #define OCPDR_REG_MASK                  0x7f
 420 #define OCPDR_GPHY_REG_SHIFT            16
 421 #define OCPDR_DATA_MASK                 0xffff
 422         OCPAR                   = 0xb4,
 423 #define OCPAR_FLAG                      0x80000000
 424 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 425 #define OCPAR_GPHY_READ_CMD             0x0000f060
 426         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 427         MISC                    = 0xf0, /* 8168e only. */
 428 #define TXPLA_RST                       (1 << 29)
 429 #define PWM_EN                          (1 << 22)
 430 };
 431
 432 enum rtl_register_content {
 433         /* InterruptStatusBits */
 434         SYSErr          = 0x8000,
 435         PCSTimeout      = 0x4000,
 436         SWInt           = 0x0100,
 437         TxDescUnavail   = 0x0080,
 438         RxFIFOOver      = 0x0040,
 439         LinkChg         = 0x0020,
 440         RxOverflow      = 0x0010,
 441         TxErr           = 0x0008,
 442         TxOK            = 0x0004,
 443         RxErr           = 0x0002,
 444         RxOK            = 0x0001,
 445
 446         /* RxStatusDesc */
 447         RxBOVF  = (1 << 24),
 448         RxFOVF  = (1 << 23),
 449         RxRWT   = (1 << 22),
 450         RxRES   = (1 << 21),
 451         RxRUNT  = (1 << 20),
 452         RxCRC   = (1 << 19),
 453
 454         /* ChipCmdBits */
 455         StopReq         = 0x80,
 456         CmdReset        = 0x10,
 457         CmdRxEnb        = 0x08,
 458         CmdTxEnb        = 0x04,
 459         RxBufEmpty      = 0x01,
 460
 461         /* TXPoll register p.5 */
 462         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 463         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 464         FSWInt          = 0x01,         /* Forced software interrupt */
 465
 466         /* Cfg9346Bits */
 467         Cfg9346_Lock    = 0x00,
 468         Cfg9346_Unlock  = 0xc0,
 469
 470         /* rx_mode_bits */
 471         AcceptErr       = 0x20,
 472         AcceptRunt      = 0x10,
 473         AcceptBroadcast = 0x08,
 474         AcceptMulticast = 0x04,
 475         AcceptMyPhys    = 0x02,
 476         AcceptAllPhys   = 0x01,
 477 #define RX_CONFIG_ACCEPT_MASK           0x3f
 478
 479         /* TxConfigBits */
 480         TxInterFrameGapShift = 24,
 481         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 482
 483         /* Config1 register p.24 */
 484         LEDS1           = (1 << 7),
 485         LEDS0           = (1 << 6),
 486         Speed_down      = (1 << 4),
 487         MEMMAP          = (1 << 3),
 488         IOMAP           = (1 << 2),
 489         VPD             = (1 << 1),
 490         PMEnable        = (1 << 0),     /* Power Management Enable */
 491
 492         /* Config2 register p. 25 */
 493         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 494         PCI_Clock_66MHz = 0x01,
 495         PCI_Clock_33MHz = 0x00,
 496
 497         /* Config3 register p.25 */
 498         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 499         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 500         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 501         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 502
 503         /* Config4 register */
 504         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 505
 506         /* Config5 register p.27 */
 507         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 508         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 509         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 510         Spi_en          = (1 << 3),
 511         LanWake         = (1 << 1),     /* LanWake enable/disable */
 512         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 513
 514         /* TBICSR p.28 */
 515         TBIReset        = 0x80000000,
 516         TBILoopback     = 0x40000000,
 517         TBINwEnable     = 0x20000000,
 518         TBINwRestart    = 0x10000000,
 519         TBILinkOk       = 0x02000000,
 520         TBINwComplete   = 0x01000000,
 521
 522         /* CPlusCmd p.31 */
 523         EnableBist      = (1 << 15),    // 8168 8101
 524         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 525         Normal_mode     = (1 << 13),    // unused
 526         Force_half_dup  = (1 << 12),    // 8168 8101
 527         Force_rxflow_en = (1 << 11),    // 8168 8101
 528         Force_txflow_en = (1 << 10),    // 8168 8101
 529         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 530         ASF             = (1 << 8),     // 8168 8101
 531         PktCntrDisable  = (1 << 7),     // 8168 8101
 532         Mac_dbgo_sel    = 0x001c,       // 8168
 533         RxVlan          = (1 << 6),
 534         RxChkSum        = (1 << 5),
 535         PCIDAC          = (1 << 4),
 536         PCIMulRW        = (1 << 3),
 537         INTT_0          = 0x0000,       // 8168
 538         INTT_1          = 0x0001,       // 8168
 539         INTT_2          = 0x0002,       // 8168
 540         INTT_3          = 0x0003,       // 8168
 541
 542         /* rtl8169_PHYstatus */
 543         TBI_Enable      = 0x80,
 544         TxFlowCtrl      = 0x40,
 545         RxFlowCtrl      = 0x20,
 546         _1000bpsF       = 0x10,
 547         _100bps         = 0x08,
 548         _10bps          = 0x04,
 549         LinkStatus      = 0x02,
 550         FullDup         = 0x01,
 551
 552         /* _TBICSRBit */
 553         TBILinkOK       = 0x02000000,
 554
 555         /* DumpCounterCommand */
 556         CounterDump     = 0x8,
 557 };
 558
 559 enum rtl_desc_bit {
 560         /* First doubleword. */
 561         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 562         RingEnd         = (1 << 30), /* End of descriptor ring */
 563         FirstFrag       = (1 << 29), /* First segment of a packet */
 564         LastFrag        = (1 << 28), /* Final segment of a packet */
 565 };
 566
 567 /* Generic case. */
 568 enum rtl_tx_desc_bit {
 569         /* First doubleword. */
 570         TD_LSO          = (1 << 27),            /* Large Send Offload */
 571 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 572
 573         /* Second doubleword. */
 574         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 575 };
 576
 577 /* 8169, 8168b and 810x except 8102e. */
 578 enum rtl_tx_desc_bit_0 {
 579         /* First doubleword. */
 580 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 581         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 582         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 583         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 584 };
 585
 586 /* 8102e, 8168c and beyond. */
 587 enum rtl_tx_desc_bit_1 {
 588         /* Second doubleword. */
 589 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 590         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 591         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 592         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 593 };
 594
 595 static const struct rtl_tx_desc_info {
 596         struct {
 597                 u32 udp;
 598                 u32 tcp;
 599         } checksum;
 600         u16 mss_shift;
 601         u16 opts_offset;
 602 } tx_desc_info [] = {
 603         [RTL_TD_0] = {
 604                 .checksum = {
 605                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 606                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 607                 },
 608                 .mss_shift      = TD0_MSS_SHIFT,
 609                 .opts_offset    = 0
 610         },
 611         [RTL_TD_1] = {
 612                 .checksum = {
 613                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 614                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 615                 },
 616                 .mss_shift      = TD1_MSS_SHIFT,
 617                 .opts_offset    = 1
 618         }
 619 };
 620
 621 enum rtl_rx_desc_bit {
 622         /* Rx private */
 623         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 624         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 625
 626 #define RxProtoUDP      (PID1)
 627 #define RxProtoTCP      (PID0)
 628 #define RxProtoIP       (PID1 | PID0)
 629 #define RxProtoMask     RxProtoIP
 630
 631         IPFail          = (1 << 16), /* IP checksum failed */
 632         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 633         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 634         RxVlanTag       = (1 << 16), /* VLAN tag available */
 635 };
 636
 637 #define RsvdMask        0x3fffc000
 638
 639 struct TxDesc {
 640         __le32 opts1;
 641         __le32 opts2;
 642         __le64 addr;
 643 };
 644
 645 struct RxDesc {
 646         __le32 opts1;
 647         __le32 opts2;
 648         __le64 addr;
 649 };
 650
 651 struct ring_info {
 652         struct sk_buff  *skb;
 653         u32             len;
 654         u8              __pad[sizeof(void *) - sizeof(u32)];
 655 };
 656
 657 enum features {
 658         RTL_FEATURE_WOL         = (1 << 0),
 659         RTL_FEATURE_MSI         = (1 << 1),
 660         RTL_FEATURE_GMII        = (1 << 2),
 661 };
 662
 663 struct rtl8169_counters {
 664         __le64  tx_packets;
 665         __le64  rx_packets;
 666         __le64  tx_errors;
 667         __le32  rx_errors;
 668         __le16  rx_missed;
 669         __le16  align_errors;
 670         __le32  tx_one_collision;
 671         __le32  tx_multi_collision;
 672         __le64  rx_unicast;
 673         __le64  rx_broadcast;
 674         __le32  rx_multicast;
 675         __le16  tx_aborted;
 676         __le16  tx_underun;
 677 };
 678
 679 struct rtl8169_private {
 680         void __iomem *mmio_addr;        /* memory map physical address */
 681         struct pci_dev *pci_dev;
 682         struct net_device *dev;
 683         struct napi_struct napi;
 684         spinlock_t lock;
 685         u32 msg_enable;
 686         u16 txd_version;
 687         u16 mac_version;
 688         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 689         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 690         u32 dirty_rx;
 691         u32 dirty_tx;
 692         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 693         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 694         dma_addr_t TxPhyAddr;
 695         dma_addr_t RxPhyAddr;
 696         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 697         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 698         struct timer_list timer;
 699         u16 cp_cmd;
 700         u16 intr_event;
 701         u16 napi_event;
 702         u16 intr_mask;
 703
 704         struct mdio_ops {
 705                 void (*write)(void __iomem *, int, int);
 706                 int (*read)(void __iomem *, int);
 707         } mdio_ops;
 708
 709         struct pll_power_ops {
 710                 void (*down)(struct rtl8169_private *);
 711                 void (*up)(struct rtl8169_private *);
 712         } pll_power_ops;
 713
 714         struct jumbo_ops {
 715                 void (*enable)(struct rtl8169_private *);
 716                 void (*disable)(struct rtl8169_private *);
 717         } jumbo_ops;
 718
 719         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 720         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 721         void (*phy_reset_enable)(struct rtl8169_private *tp);
 722         void (*hw_start)(struct net_device *);
 723         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 724         unsigned int (*link_ok)(void __iomem *);
 725         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 726         struct delayed_work task;
 727         unsigned features;
 728
 729         struct mii_if_info mii;
 730         struct rtl8169_counters counters;
 731         u32 saved_wolopts;
 732         u32 opts1_mask;
 733
 734         struct rtl_fw {
 735                 const struct firmware *fw;
 736
 737 #define RTL_VER_SIZE            32
 738
 739                 char version[RTL_VER_SIZE];
 740
 741                 struct rtl_fw_phy_action {
 742                         __le32 *code;
 743                         size_t size;
 744                 } phy_action;
 745         } *rtl_fw;
 746 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 747 };
 748
 749 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 750 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 751 module_param(use_dac, int, 0);
 752 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 753 module_param_named(debug, debug.msg_enable, int, 0);
 754 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 755 MODULE_LICENSE("GPL");
 756 MODULE_VERSION(RTL8169_VERSION);
 757 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 758 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 759 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 760 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 761 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 762 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 763 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 764 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 765
 766 static int rtl8169_open(struct net_device *dev);
 767 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 768                                       struct net_device *dev);
 769 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 770 static int rtl8169_init_ring(struct net_device *dev);
 771 static void rtl_hw_start(struct net_device *dev);
 772 static int rtl8169_close(struct net_device *dev);
 773 static void rtl_set_rx_mode(struct net_device *dev);
 774 static void rtl8169_tx_timeout(struct net_device *dev);
 775 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 776 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 777                                 void __iomem *, u32 budget);
 778 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 779 static void rtl8169_down(struct net_device *dev);
 780 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 781 static int rtl8169_poll(struct napi_struct *napi, int budget);
 782
 783 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 784 {
 785         int cap = pci_pcie_cap(pdev);
 786
 787         if (cap) {
 788                 u16 ctl;
 789
 790                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 791                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 792                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 793         }
 794 }
 795
 796 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 797 {
 798         void __iomem *ioaddr = tp->mmio_addr;
 799         int i;
 800
 801         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 802         for (i = 0; i < 20; i++) {
 803                 udelay(100);
 804                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 805                         break;
 806         }
 807         return RTL_R32(OCPDR);
 808 }
 809
 810 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 811 {
 812         void __iomem *ioaddr = tp->mmio_addr;
 813         int i;
 814
 815         RTL_W32(OCPDR, data);
 816         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 817         for (i = 0; i < 20; i++) {
 818                 udelay(100);
 819                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 820                         break;
 821         }
 822 }
 823
 824 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 825 {
 826         void __iomem *ioaddr = tp->mmio_addr;
 827         int i;
 828
 829         RTL_W8(ERIDR, cmd);
 830         RTL_W32(ERIAR, 0x800010e8);
 831         msleep(2);
 832         for (i = 0; i < 5; i++) {
 833                 udelay(100);
 834                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 835                         break;
 836         }
 837
 838         ocp_write(tp, 0x1, 0x30, 0x00000001);
 839 }
 840
 841 #define OOB_CMD_RESET           0x00
 842 #define OOB_CMD_DRIVER_START    0x05
 843 #define OOB_CMD_DRIVER_STOP     0x06
 844
 845 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 846 {
 847         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 848 }
 849
 850 static void rtl8168_driver_start(struct rtl8169_private *tp)
 851 {
 852         u16 reg;
 853         int i;
 854
 855         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 856
 857         reg = rtl8168_get_ocp_reg(tp);
 858
 859         for (i = 0; i < 10; i++) {
 860                 msleep(10);
 861                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 862                         break;
 863         }
 864 }
 865
 866 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 867 {
 868         u16 reg;
 869         int i;
 870
 871         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 872
 873         reg = rtl8168_get_ocp_reg(tp);
 874
 875         for (i = 0; i < 10; i++) {
 876                 msleep(10);
 877                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 878                         break;
 879         }
 880 }
 881
 882 static int r8168dp_check_dash(struct rtl8169_private *tp)
 883 {
 884         u16 reg = rtl8168_get_ocp_reg(tp);
 885
 886         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 887 }
 888
 889 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 890 {
 891         int i;
 892
 893         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 894
 895         for (i = 20; i > 0; i--) {
 896                 /*
 897                  * Check if the RTL8169 has completed writing to the specified
 898                  * MII register.
 899                  */
 900                 if (!(RTL_R32(PHYAR) & 0x80000000))
 901                         break;
 902                 udelay(25);
 903         }
 904         /*
 905          * According to hardware specs a 20us delay is required after write
 906          * complete indication, but before sending next command.
 907          */
 908         udelay(20);
 909 }
 910
 911 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 912 {
 913         int i, value = -1;
 914
 915         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 916
 917         for (i = 20; i > 0; i--) {
 918                 /*
 919                  * Check if the RTL8169 has completed retrieving data from
 920                  * the specified MII register.
 921                  */
 922                 if (RTL_R32(PHYAR) & 0x80000000) {
 923                         value = RTL_R32(PHYAR) & 0xffff;
 924                         break;
 925                 }
 926                 udelay(25);
 927         }
 928         /*
 929          * According to hardware specs a 20us delay is required after read
 930          * complete indication, but before sending next command.
 931          */
 932         udelay(20);
 933
 934         return value;
 935 }
 936
 937 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 938 {
 939         int i;
 940
 941         RTL_W32(OCPDR, data |
 942                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 943         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 944         RTL_W32(EPHY_RXER_NUM, 0);
 945
 946         for (i = 0; i < 100; i++) {
 947                 mdelay(1);
 948                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 949                         break;
 950         }
 951 }
 952
 953 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 954 {
 955         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 956                 (value & OCPDR_DATA_MASK));
 957 }
 958
 959 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 960 {
 961         int i;
 962
 963         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 964
 965         mdelay(1);
 966         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 967         RTL_W32(EPHY_RXER_NUM, 0);
 968
 969         for (i = 0; i < 100; i++) {
 970                 mdelay(1);
 971                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 972                         break;
 973         }
 974
 975         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 976 }
 977
 978 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 979
 980 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 981 {
 982         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 983 }
 984
 985 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 986 {
 987         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 988 }
 989
 990 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 991 {
 992         r8168dp_2_mdio_start(ioaddr);
 993
 994         r8169_mdio_write(ioaddr, reg_addr, value);
 995
 996         r8168dp_2_mdio_stop(ioaddr);
 997 }
 998
 999 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1000 {
1001         int value;
1002
1003         r8168dp_2_mdio_start(ioaddr);
1004
1005         value = r8169_mdio_read(ioaddr, reg_addr);
1006
1007         r8168dp_2_mdio_stop(ioaddr);
1008
1009         return value;
1010 }
1011
1012 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1013 {
1014         tp->mdio_ops.write(tp->mmio_addr, location, val);
1015 }
1016
1017 static int rtl_readphy(struct rtl8169_private *tp, int location)
1018 {
1019         return tp->mdio_ops.read(tp->mmio_addr, location);
1020 }
1021
1022 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1023 {
1024         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1025 }
1026
1027 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1028 {
1029         int val;
1030
1031         val = rtl_readphy(tp, reg_addr);
1032         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1033 }
1034
1035 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1036                            int val)
1037 {
1038         struct rtl8169_private *tp = netdev_priv(dev);
1039
1040         rtl_writephy(tp, location, val);
1041 }
1042
1043 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1044 {
1045         struct rtl8169_private *tp = netdev_priv(dev);
1046
1047         return rtl_readphy(tp, location);
1048 }
1049
1050 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1051 {
1052         unsigned int i;
1053
1054         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1055                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1056
1057         for (i = 0; i < 100; i++) {
1058                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1059                         break;
1060                 udelay(10);
1061         }
1062 }
1063
1064 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1065 {
1066         u16 value = 0xffff;
1067         unsigned int i;
1068
1069         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1070
1071         for (i = 0; i < 100; i++) {
1072                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1073                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1074                         break;
1075                 }
1076                 udelay(10);
1077         }
1078
1079         return value;
1080 }
1081
1082 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1083 {
1084         unsigned int i;
1085
1086         RTL_W32(CSIDR, value);
1087         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1088                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1089
1090         for (i = 0; i < 100; i++) {
1091                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1092                         break;
1093                 udelay(10);
1094         }
1095 }
1096
1097 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1098 {
1099         u32 value = ~0x00;
1100         unsigned int i;
1101
1102         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1103                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1104
1105         for (i = 0; i < 100; i++) {
1106                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1107                         value = RTL_R32(CSIDR);
1108                         break;
1109                 }
1110                 udelay(10);
1111         }
1112
1113         return value;
1114 }
1115
1116 static
1117 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1118 {
1119         unsigned int i;
1120
1121         BUG_ON((addr & 3) || (mask == 0));
1122         RTL_W32(ERIDR, val);
1123         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1124
1125         for (i = 0; i < 100; i++) {
1126                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1127                         break;
1128                 udelay(100);
1129         }
1130 }
1131
1132 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1133 {
1134         u32 value = ~0x00;
1135         unsigned int i;
1136
1137         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1138
1139         for (i = 0; i < 100; i++) {
1140                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1141                         value = RTL_R32(ERIDR);
1142                         break;
1143                 }
1144                 udelay(100);
1145         }
1146
1147         return value;
1148 }
1149
1150 static void
1151 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1152 {
1153         u32 val;
1154
1155         val = rtl_eri_read(ioaddr, addr, type);
1156         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1157 }
1158
1159 struct exgmac_reg {
1160         u16 addr;
1161         u16 mask;
1162         u32 val;
1163 };
1164
1165 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1166                                    const struct exgmac_reg *r, int len)
1167 {
1168         while (len-- > 0) {
1169                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1170                 r++;
1171         }
1172 }
1173
1174 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1175 {
1176         u8 value = 0xff;
1177         unsigned int i;
1178
1179         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1180
1181         for (i = 0; i < 300; i++) {
1182                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1183                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1184                         break;
1185                 }
1186                 udelay(100);
1187         }
1188
1189         return value;
1190 }
1191
1192 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1193 {
1194         void __iomem *ioaddr = tp->mmio_addr;
1195
1196         RTL_W16(IntrMask, 0x0000);
1197         RTL_W16(IntrStatus, tp->intr_event);
1198         RTL_R8(ChipCmd);
1199 }
1200
1201 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1202 {
1203         void __iomem *ioaddr = tp->mmio_addr;
1204
1205         return RTL_R32(TBICSR) & TBIReset;
1206 }
1207
1208 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1209 {
1210         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1211 }
1212
1213 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1214 {
1215         return RTL_R32(TBICSR) & TBILinkOk;
1216 }
1217
1218 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1219 {
1220         return RTL_R8(PHYstatus) & LinkStatus;
1221 }
1222
1223 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1224 {
1225         void __iomem *ioaddr = tp->mmio_addr;
1226
1227         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1228 }
1229
1230 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1231 {
1232         unsigned int val;
1233
1234         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1235         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1236 }
1237
1238 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1239 {
1240         void __iomem *ioaddr = tp->mmio_addr;
1241         struct net_device *dev = tp->dev;
1242
1243         if (!netif_running(dev))
1244                 return;
1245
1246         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1247                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1248                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1249                                       0x00000011, ERIAR_EXGMAC);
1250                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1251                                       0x00000005, ERIAR_EXGMAC);
1252                 } else if (RTL_R8(PHYstatus) & _100bps) {
1253                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1254                                       0x0000001f, ERIAR_EXGMAC);
1255                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1256                                       0x00000005, ERIAR_EXGMAC);
1257                 } else {
1258                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1259                                       0x0000001f, ERIAR_EXGMAC);
1260                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1261                                       0x0000003f, ERIAR_EXGMAC);
1262                 }
1263                 /* Reset packet filter */
1264                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1265                              ERIAR_EXGMAC);
1266                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1267                              ERIAR_EXGMAC);
1268         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1269                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1270                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1271                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1272                                       0x00000011, ERIAR_EXGMAC);
1273                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1274                                       0x00000005, ERIAR_EXGMAC);
1275                 } else {
1276                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1277                                       0x0000001f, ERIAR_EXGMAC);
1278                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1279                                       0x0000003f, ERIAR_EXGMAC);
1280                 }
1281         }
1282 }
1283
1284 static void __rtl8169_check_link_status(struct net_device *dev,
1285                                         struct rtl8169_private *tp,
1286                                         void __iomem *ioaddr, bool pm)
1287 {
1288         unsigned long flags;
1289
1290         spin_lock_irqsave(&tp->lock, flags);
1291         if (tp->link_ok(ioaddr)) {
1292                 rtl_link_chg_patch(tp);
1293                 /* This is to cancel a scheduled suspend if there's one. */
1294                 if (pm)
1295                         pm_request_resume(&tp->pci_dev->dev);
1296                 netif_carrier_on(dev);
1297                 if (net_ratelimit())
1298                         netif_info(tp, ifup, dev, "link up\n");
1299         } else {
1300                 netif_carrier_off(dev);
1301                 netif_info(tp, ifdown, dev, "link down\n");
1302                 if (pm)
1303                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1304         }
1305         spin_unlock_irqrestore(&tp->lock, flags);
1306 }
1307
1308 static void rtl8169_check_link_status(struct net_device *dev,
1309                                       struct rtl8169_private *tp,
1310                                       void __iomem *ioaddr)
1311 {
1312         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1313 }
1314
1315 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1316
1317 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1318 {
1319         void __iomem *ioaddr = tp->mmio_addr;
1320         u8 options;
1321         u32 wolopts = 0;
1322
1323         options = RTL_R8(Config1);
1324         if (!(options & PMEnable))
1325                 return 0;
1326
1327         options = RTL_R8(Config3);
1328         if (options & LinkUp)
1329                 wolopts |= WAKE_PHY;
1330         if (options & MagicPacket)
1331                 wolopts |= WAKE_MAGIC;
1332
1333         options = RTL_R8(Config5);
1334         if (options & UWF)
1335                 wolopts |= WAKE_UCAST;
1336         if (options & BWF)
1337                 wolopts |= WAKE_BCAST;
1338         if (options & MWF)
1339                 wolopts |= WAKE_MCAST;
1340
1341         return wolopts;
1342 }
1343
1344 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1345 {
1346         struct rtl8169_private *tp = netdev_priv(dev);
1347
1348         spin_lock_irq(&tp->lock);
1349
1350         wol->supported = WAKE_ANY;
1351         wol->wolopts = __rtl8169_get_wol(tp);
1352
1353         spin_unlock_irq(&tp->lock);
1354 }
1355
1356 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1357 {
1358         void __iomem *ioaddr = tp->mmio_addr;
1359         unsigned int i;
1360         static const struct {
1361                 u32 opt;
1362                 u16 reg;
1363                 u8  mask;
1364         } cfg[] = {
1365                 { WAKE_PHY,   Config3, LinkUp },
1366                 { WAKE_MAGIC, Config3, MagicPacket },
1367                 { WAKE_UCAST, Config5, UWF },
1368                 { WAKE_BCAST, Config5, BWF },
1369                 { WAKE_MCAST, Config5, MWF },
1370                 { WAKE_ANY,   Config5, LanWake }
1371         };
1372         u8 options;
1373
1374         RTL_W8(Cfg9346, Cfg9346_Unlock);
1375
1376         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1377                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1378                 if (wolopts & cfg[i].opt)
1379                         options |= cfg[i].mask;
1380                 RTL_W8(cfg[i].reg, options);
1381         }
1382
1383         switch (tp->mac_version) {
1384         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1385                 options = RTL_R8(Config1) & ~PMEnable;
1386                 if (wolopts)
1387                         options |= PMEnable;
1388                 RTL_W8(Config1, options);
1389                 break;
1390         default:
1391                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1392                 if (wolopts)
1393                         options |= PME_SIGNAL;
1394                 RTL_W8(Config2, options);
1395                 break;
1396         }
1397
1398         RTL_W8(Cfg9346, Cfg9346_Lock);
1399 }
1400
1401 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1402 {
1403         struct rtl8169_private *tp = netdev_priv(dev);
1404
1405         spin_lock_irq(&tp->lock);
1406
1407         if (wol->wolopts)
1408                 tp->features |= RTL_FEATURE_WOL;
1409         else
1410                 tp->features &= ~RTL_FEATURE_WOL;
1411         __rtl8169_set_wol(tp, wol->wolopts);
1412         spin_unlock_irq(&tp->lock);
1413
1414         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1415
1416         return 0;
1417 }
1418
1419 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1420 {
1421         return rtl_chip_infos[tp->mac_version].fw_name;
1422 }
1423
1424 static void rtl8169_get_drvinfo(struct net_device *dev,
1425                                 struct ethtool_drvinfo *info)
1426 {
1427         struct rtl8169_private *tp = netdev_priv(dev);
1428         struct rtl_fw *rtl_fw = tp->rtl_fw;
1429
1430         strcpy(info->driver, MODULENAME);
1431         strcpy(info->version, RTL8169_VERSION);
1432         strcpy(info->bus_info, pci_name(tp->pci_dev));
1433         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1434         strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1435                rtl_fw->version);
1436 }
1437
1438 static int rtl8169_get_regs_len(struct net_device *dev)
1439 {
1440         return R8169_REGS_SIZE;
1441 }
1442
1443 static int rtl8169_set_speed_tbi(struct net_device *dev,
1444                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1445 {
1446         struct rtl8169_private *tp = netdev_priv(dev);
1447         void __iomem *ioaddr = tp->mmio_addr;
1448         int ret = 0;
1449         u32 reg;
1450
1451         reg = RTL_R32(TBICSR);
1452         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1453             (duplex == DUPLEX_FULL)) {
1454                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1455         } else if (autoneg == AUTONEG_ENABLE)
1456                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1457         else {
1458                 netif_warn(tp, link, dev,
1459                            "incorrect speed setting refused in TBI mode\n");
1460                 ret = -EOPNOTSUPP;
1461         }
1462
1463         return ret;
1464 }
1465
1466 static int rtl8169_set_speed_xmii(struct net_device *dev,
1467                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1468 {
1469         struct rtl8169_private *tp = netdev_priv(dev);
1470         int giga_ctrl, bmcr;
1471         int rc = -EINVAL;
1472
1473         rtl_writephy(tp, 0x1f, 0x0000);
1474
1475         if (autoneg == AUTONEG_ENABLE) {
1476                 int auto_nego;
1477
1478                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1479                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1480                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1481
1482                 if (adv & ADVERTISED_10baseT_Half)
1483                         auto_nego |= ADVERTISE_10HALF;
1484                 if (adv & ADVERTISED_10baseT_Full)
1485                         auto_nego |= ADVERTISE_10FULL;
1486                 if (adv & ADVERTISED_100baseT_Half)
1487                         auto_nego |= ADVERTISE_100HALF;
1488                 if (adv & ADVERTISED_100baseT_Full)
1489                         auto_nego |= ADVERTISE_100FULL;
1490
1491                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1492
1493                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1494                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1495
1496                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1497                 if (tp->mii.supports_gmii) {
1498                         if (adv & ADVERTISED_1000baseT_Half)
1499                                 giga_ctrl |= ADVERTISE_1000HALF;
1500                         if (adv & ADVERTISED_1000baseT_Full)
1501                                 giga_ctrl |= ADVERTISE_1000FULL;
1502                 } else if (adv & (ADVERTISED_1000baseT_Half |
1503                                   ADVERTISED_1000baseT_Full)) {
1504                         netif_info(tp, link, dev,
1505                                    "PHY does not support 1000Mbps\n");
1506                         goto out;
1507                 }
1508
1509                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1510
1511                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1512                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1513         } else {
1514                 giga_ctrl = 0;
1515
1516                 if (speed == SPEED_10)
1517                         bmcr = 0;
1518                 else if (speed == SPEED_100)
1519                         bmcr = BMCR_SPEED100;
1520                 else
1521                         goto out;
1522
1523                 if (duplex == DUPLEX_FULL)
1524                         bmcr |= BMCR_FULLDPLX;
1525         }
1526
1527         rtl_writephy(tp, MII_BMCR, bmcr);
1528
1529         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1530             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1531                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1532                         rtl_writephy(tp, 0x17, 0x2138);
1533                         rtl_writephy(tp, 0x0e, 0x0260);
1534                 } else {
1535                         rtl_writephy(tp, 0x17, 0x2108);
1536                         rtl_writephy(tp, 0x0e, 0x0000);
1537                 }
1538         }
1539
1540         rc = 0;
1541 out:
1542         return rc;
1543 }
1544
1545 static int rtl8169_set_speed(struct net_device *dev,
1546                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1547 {
1548         struct rtl8169_private *tp = netdev_priv(dev);
1549         int ret;
1550
1551         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1552         if (ret < 0)
1553                 goto out;
1554
1555         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1556             (advertising & ADVERTISED_1000baseT_Full)) {
1557                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1558         }
1559 out:
1560         return ret;
1561 }
1562
1563 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1564 {
1565         struct rtl8169_private *tp = netdev_priv(dev);
1566         unsigned long flags;
1567         int ret;
1568
1569         del_timer_sync(&tp->timer);
1570
1571         spin_lock_irqsave(&tp->lock, flags);
1572         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1573                                 cmd->duplex, cmd->advertising);
1574         spin_unlock_irqrestore(&tp->lock, flags);
1575
1576         return ret;
1577 }
1578
1579 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1580 {
1581         struct rtl8169_private *tp = netdev_priv(dev);
1582
1583         if (dev->mtu > TD_MSS_MAX)
1584                 features &= ~NETIF_F_ALL_TSO;
1585
1586         if (dev->mtu > JUMBO_1K &&
1587             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1588                 features &= ~NETIF_F_IP_CSUM;
1589
1590         return features;
1591 }
1592
1593 static int rtl8169_set_features(struct net_device *dev, u32 features)
1594 {
1595         struct rtl8169_private *tp = netdev_priv(dev);
1596         void __iomem *ioaddr = tp->mmio_addr;
1597         unsigned long flags;
1598
1599         spin_lock_irqsave(&tp->lock, flags);
1600
1601         if (features & NETIF_F_RXCSUM)
1602                 tp->cp_cmd |= RxChkSum;
1603         else
1604                 tp->cp_cmd &= ~RxChkSum;
1605
1606         if (dev->features & NETIF_F_HW_VLAN_RX)
1607                 tp->cp_cmd |= RxVlan;
1608         else
1609                 tp->cp_cmd &= ~RxVlan;
1610
1611         RTL_W16(CPlusCmd, tp->cp_cmd);
1612         RTL_R16(CPlusCmd);
1613
1614         spin_unlock_irqrestore(&tp->lock, flags);
1615
1616         return 0;
1617 }
1618
1619 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1620                                       struct sk_buff *skb)
1621 {
1622         return (vlan_tx_tag_present(skb)) ?
1623                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1624 }
1625
1626 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1627 {
1628         u32 opts2 = le32_to_cpu(desc->opts2);
1629
1630         if (opts2 & RxVlanTag)
1631                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1632 }
1633
1634 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1635 {
1636         struct rtl8169_private *tp = netdev_priv(dev);
1637         void __iomem *ioaddr = tp->mmio_addr;
1638         u32 status;
1639
1640         cmd->supported =
1641                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1642         cmd->port = PORT_FIBRE;
1643         cmd->transceiver = XCVR_INTERNAL;
1644
1645         status = RTL_R32(TBICSR);
1646         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1647         cmd->autoneg = !!(status & TBINwEnable);
1648
1649         ethtool_cmd_speed_set(cmd, SPEED_1000);
1650         cmd->duplex = DUPLEX_FULL; /* Always set */
1651
1652         return 0;
1653 }
1654
1655 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1656 {
1657         struct rtl8169_private *tp = netdev_priv(dev);
1658
1659         return mii_ethtool_gset(&tp->mii, cmd);
1660 }
1661
1662 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1663 {
1664         struct rtl8169_private *tp = netdev_priv(dev);
1665         unsigned long flags;
1666         int rc;
1667
1668         spin_lock_irqsave(&tp->lock, flags);
1669
1670         rc = tp->get_settings(dev, cmd);
1671
1672         spin_unlock_irqrestore(&tp->lock, flags);
1673         return rc;
1674 }
1675
1676 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1677                              void *p)
1678 {
1679         struct rtl8169_private *tp = netdev_priv(dev);
1680         unsigned long flags;
1681
1682         if (regs->len > R8169_REGS_SIZE)
1683                 regs->len = R8169_REGS_SIZE;
1684
1685         spin_lock_irqsave(&tp->lock, flags);
1686         memcpy_fromio(p, tp->mmio_addr, regs->len);
1687         spin_unlock_irqrestore(&tp->lock, flags);
1688 }
1689
1690 static u32 rtl8169_get_msglevel(struct net_device *dev)
1691 {
1692         struct rtl8169_private *tp = netdev_priv(dev);
1693
1694         return tp->msg_enable;
1695 }
1696
1697 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1698 {
1699         struct rtl8169_private *tp = netdev_priv(dev);
1700
1701         tp->msg_enable = value;
1702 }
1703
1704 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1705         "tx_packets",
1706         "rx_packets",
1707         "tx_errors",
1708         "rx_errors",
1709         "rx_missed",
1710         "align_errors",
1711         "tx_single_collisions",
1712         "tx_multi_collisions",
1713         "unicast",
1714         "broadcast",
1715         "multicast",
1716         "tx_aborted",
1717         "tx_underrun",
1718 };
1719
1720 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1721 {
1722         switch (sset) {
1723         case ETH_SS_STATS:
1724                 return ARRAY_SIZE(rtl8169_gstrings);
1725         default:
1726                 return -EOPNOTSUPP;
1727         }
1728 }
1729
1730 static void rtl8169_update_counters(struct net_device *dev)
1731 {
1732         struct rtl8169_private *tp = netdev_priv(dev);
1733         void __iomem *ioaddr = tp->mmio_addr;
1734         struct device *d = &tp->pci_dev->dev;
1735         struct rtl8169_counters *counters;
1736         dma_addr_t paddr;
1737         u32 cmd;
1738         int wait = 1000;
1739
1740         /*
1741          * Some chips are unable to dump tally counters when the receiver
1742          * is disabled.
1743          */
1744         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1745                 return;
1746
1747         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1748         if (!counters)
1749                 return;
1750
1751         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1752         cmd = (u64)paddr & DMA_BIT_MASK(32);
1753         RTL_W32(CounterAddrLow, cmd);
1754         RTL_W32(CounterAddrLow, cmd | CounterDump);
1755
1756         while (wait--) {
1757                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1758                         memcpy(&tp->counters, counters, sizeof(*counters));
1759                         break;
1760                 }
1761                 udelay(10);
1762         }
1763
1764         RTL_W32(CounterAddrLow, 0);
1765         RTL_W32(CounterAddrHigh, 0);
1766
1767         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1768 }
1769
1770 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1771                                       struct ethtool_stats *stats, u64 *data)
1772 {
1773         struct rtl8169_private *tp = netdev_priv(dev);
1774
1775         ASSERT_RTNL();
1776
1777         rtl8169_update_counters(dev);
1778
1779         data[0] = le64_to_cpu(tp->counters.tx_packets);
1780         data[1] = le64_to_cpu(tp->counters.rx_packets);
1781         data[2] = le64_to_cpu(tp->counters.tx_errors);
1782         data[3] = le32_to_cpu(tp->counters.rx_errors);
1783         data[4] = le16_to_cpu(tp->counters.rx_missed);
1784         data[5] = le16_to_cpu(tp->counters.align_errors);
1785         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1786         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1787         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1788         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1789         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1790         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1791         data[12] = le16_to_cpu(tp->counters.tx_underun);
1792 }
1793
1794 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1795 {
1796         switch(stringset) {
1797         case ETH_SS_STATS:
1798                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1799                 break;
1800         }
1801 }
1802
1803 static const struct ethtool_ops rtl8169_ethtool_ops = {
1804         .get_drvinfo            = rtl8169_get_drvinfo,
1805         .get_regs_len           = rtl8169_get_regs_len,
1806         .get_link               = ethtool_op_get_link,
1807         .get_settings           = rtl8169_get_settings,
1808         .set_settings           = rtl8169_set_settings,
1809         .get_msglevel           = rtl8169_get_msglevel,
1810         .set_msglevel           = rtl8169_set_msglevel,
1811         .get_regs               = rtl8169_get_regs,
1812         .get_wol                = rtl8169_get_wol,
1813         .set_wol                = rtl8169_set_wol,
1814         .get_strings            = rtl8169_get_strings,
1815         .get_sset_count         = rtl8169_get_sset_count,
1816         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1817 };
1818
1819 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1820                                     struct net_device *dev, u8 default_version)
1821 {
1822         void __iomem *ioaddr = tp->mmio_addr;
1823         /*
1824          * The driver currently handles the 8168Bf and the 8168Be identically
1825          * but they can be identified more specifically through the test below
1826          * if needed:
1827          *
1828          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1829          *
1830          * Same thing for the 8101Eb and the 8101Ec:
1831          *
1832          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1833          */
1834         static const struct rtl_mac_info {
1835                 u32 mask;
1836                 u32 val;
1837                 int mac_version;
1838         } mac_info[] = {
1839                 /* 8168F family. */
1840                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1841                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1842
1843                 /* 8168E family. */
1844                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1845                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1846                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1847                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1848
1849                 /* 8168D family. */
1850                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1851                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1852                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1853
1854                 /* 8168DP family. */
1855                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1856                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1857                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1858
1859                 /* 8168C family. */
1860                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1861                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1862                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1863                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1864                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1865                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1866                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1867                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1868                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1869
1870                 /* 8168B family. */
1871                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1872                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1873                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1874                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1875
1876                 /* 8101 family. */
1877                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1878                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1879                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1880                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1881                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1882                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1883                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1884                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1885                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1886                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1887                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1888                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1889                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1890                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1891                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1892                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1893                 /* FIXME: where did these entries come from ? -- FR */
1894                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1895                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1896
1897                 /* 8110 family. */
1898                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1899                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1900                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1901                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1902                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1903                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1904
1905                 /* Catch-all */
1906                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1907         };
1908         const struct rtl_mac_info *p = mac_info;
1909         u32 reg;
1910
1911         reg = RTL_R32(TxConfig);
1912         while ((reg & p->mask) != p->val)
1913                 p++;
1914         tp->mac_version = p->mac_version;
1915
1916         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1917                 netif_notice(tp, probe, dev,
1918                              "unknown MAC, using family default\n");
1919                 tp->mac_version = default_version;
1920         }
1921 }
1922
1923 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1924 {
1925         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1926 }
1927
1928 struct phy_reg {
1929         u16 reg;
1930         u16 val;
1931 };
1932
1933 static void rtl_writephy_batch(struct rtl8169_private *tp,
1934                                const struct phy_reg *regs, int len)
1935 {
1936         while (len-- > 0) {
1937                 rtl_writephy(tp, regs->reg, regs->val);
1938                 regs++;
1939         }
1940 }
1941
1942 #define PHY_READ                0x00000000
1943 #define PHY_DATA_OR             0x10000000
1944 #define PHY_DATA_AND            0x20000000
1945 #define PHY_BJMPN               0x30000000
1946 #define PHY_READ_EFUSE          0x40000000
1947 #define PHY_READ_MAC_BYTE       0x50000000
1948 #define PHY_WRITE_MAC_BYTE      0x60000000
1949 #define PHY_CLEAR_READCOUNT     0x70000000
1950 #define PHY_WRITE               0x80000000
1951 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1952 #define PHY_COMP_EQ_SKIPN       0xa0000000
1953 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1954 #define PHY_WRITE_PREVIOUS      0xc0000000
1955 #define PHY_SKIPN               0xd0000000
1956 #define PHY_DELAY_MS            0xe0000000
1957 #define PHY_WRITE_ERI_WORD      0xf0000000
1958
1959 struct fw_info {
1960         u32     magic;
1961         char    version[RTL_VER_SIZE];
1962         __le32  fw_start;
1963         __le32  fw_len;
1964         u8      chksum;
1965 } __packed;
1966
1967 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1968
1969 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1970 {
1971         const struct firmware *fw = rtl_fw->fw;
1972         struct fw_info *fw_info = (struct fw_info *)fw->data;
1973         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1974         char *version = rtl_fw->version;
1975         bool rc = false;
1976
1977         if (fw->size < FW_OPCODE_SIZE)
1978                 goto out;
1979
1980         if (!fw_info->magic) {
1981                 size_t i, size, start;
1982                 u8 checksum = 0;
1983
1984                 if (fw->size < sizeof(*fw_info))
1985                         goto out;
1986
1987                 for (i = 0; i < fw->size; i++)
1988                         checksum += fw->data[i];
1989                 if (checksum != 0)
1990                         goto out;
1991
1992                 start = le32_to_cpu(fw_info->fw_start);
1993                 if (start > fw->size)
1994                         goto out;
1995
1996                 size = le32_to_cpu(fw_info->fw_len);
1997                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1998                         goto out;
1999
2000                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2001
2002                 pa->code = (__le32 *)(fw->data + start);
2003                 pa->size = size;
2004         } else {
2005                 if (fw->size % FW_OPCODE_SIZE)
2006                         goto out;
2007
2008                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2009
2010                 pa->code = (__le32 *)fw->data;
2011                 pa->size = fw->size / FW_OPCODE_SIZE;
2012         }
2013         version[RTL_VER_SIZE - 1] = 0;
2014
2015         rc = true;
2016 out:
2017         return rc;
2018 }
2019
2020 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2021                            struct rtl_fw_phy_action *pa)
2022 {
2023         bool rc = false;
2024         size_t index;
2025
2026         for (index = 0; index < pa->size; index++) {
2027                 u32 action = le32_to_cpu(pa->code[index]);
2028                 u32 regno = (action & 0x0fff0000) >> 16;
2029
2030                 switch(action & 0xf0000000) {
2031                 case PHY_READ:
2032                 case PHY_DATA_OR:
2033                 case PHY_DATA_AND:
2034                 case PHY_READ_EFUSE:
2035                 case PHY_CLEAR_READCOUNT:
2036                 case PHY_WRITE:
2037                 case PHY_WRITE_PREVIOUS:
2038                 case PHY_DELAY_MS:
2039                         break;
2040
2041                 case PHY_BJMPN:
2042                         if (regno > index) {
2043                                 netif_err(tp, ifup, tp->dev,
2044                                           "Out of range of firmware\n");
2045                                 goto out;
2046                         }
2047                         break;
2048                 case PHY_READCOUNT_EQ_SKIP:
2049                         if (index + 2 >= pa->size) {
2050                                 netif_err(tp, ifup, tp->dev,
2051                                           "Out of range of firmware\n");
2052                                 goto out;
2053                         }
2054                         break;
2055                 case PHY_COMP_EQ_SKIPN:
2056                 case PHY_COMP_NEQ_SKIPN:
2057                 case PHY_SKIPN:
2058                         if (index + 1 + regno >= pa->size) {
2059                                 netif_err(tp, ifup, tp->dev,
2060                                           "Out of range of firmware\n");
2061                                 goto out;
2062                         }
2063                         break;
2064
2065                 case PHY_READ_MAC_BYTE:
2066                 case PHY_WRITE_MAC_BYTE:
2067                 case PHY_WRITE_ERI_WORD:
2068                 default:
2069                         netif_err(tp, ifup, tp->dev,
2070                                   "Invalid action 0x%08x\n", action);
2071                         goto out;
2072                 }
2073         }
2074         rc = true;
2075 out:
2076         return rc;
2077 }
2078
2079 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2080 {
2081         struct net_device *dev = tp->dev;
2082         int rc = -EINVAL;
2083
2084         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2085                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2086                 goto out;
2087         }
2088
2089         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2090                 rc = 0;
2091 out:
2092         return rc;
2093 }
2094
2095 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2096 {
2097         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2098         u32 predata, count;
2099         size_t index;
2100
2101         predata = count = 0;
2102
2103         for (index = 0; index < pa->size; ) {
2104                 u32 action = le32_to_cpu(pa->code[index]);
2105                 u32 data = action & 0x0000ffff;
2106                 u32 regno = (action & 0x0fff0000) >> 16;
2107
2108                 if (!action)
2109                         break;
2110
2111                 switch(action & 0xf0000000) {
2112                 case PHY_READ:
2113                         predata = rtl_readphy(tp, regno);
2114                         count++;
2115                         index++;
2116                         break;
2117                 case PHY_DATA_OR:
2118                         predata |= data;
2119                         index++;
2120                         break;
2121                 case PHY_DATA_AND:
2122                         predata &= data;
2123                         index++;
2124                         break;
2125                 case PHY_BJMPN:
2126                         index -= regno;
2127                         break;
2128                 case PHY_READ_EFUSE:
2129                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2130                         index++;
2131                         break;
2132                 case PHY_CLEAR_READCOUNT:
2133                         count = 0;
2134                         index++;
2135                         break;
2136                 case PHY_WRITE:
2137                         rtl_writephy(tp, regno, data);
2138                         index++;
2139                         break;
2140                 case PHY_READCOUNT_EQ_SKIP:
2141                         index += (count == data) ? 2 : 1;
2142                         break;
2143                 case PHY_COMP_EQ_SKIPN:
2144                         if (predata == data)
2145                                 index += regno;
2146                         index++;
2147                         break;
2148                 case PHY_COMP_NEQ_SKIPN:
2149                         if (predata != data)
2150                                 index += regno;
2151                         index++;
2152                         break;
2153                 case PHY_WRITE_PREVIOUS:
2154                         rtl_writephy(tp, regno, predata);
2155                         index++;
2156                         break;
2157                 case PHY_SKIPN:
2158                         index += regno + 1;
2159                         break;
2160                 case PHY_DELAY_MS:
2161                         mdelay(data);
2162                         index++;
2163                         break;
2164
2165                 case PHY_READ_MAC_BYTE:
2166                 case PHY_WRITE_MAC_BYTE:
2167                 case PHY_WRITE_ERI_WORD:
2168                 default:
2169                         BUG();
2170                 }
2171         }
2172 }
2173
2174 static void rtl_release_firmware(struct rtl8169_private *tp)
2175 {
2176         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2177                 release_firmware(tp->rtl_fw->fw);
2178                 kfree(tp->rtl_fw);
2179         }
2180         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2181 }
2182
2183 static void rtl_apply_firmware(struct rtl8169_private *tp)
2184 {
2185         struct rtl_fw *rtl_fw = tp->rtl_fw;
2186
2187         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2188         if (!IS_ERR_OR_NULL(rtl_fw))
2189                 rtl_phy_write_fw(tp, rtl_fw);
2190 }
2191
2192 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2193 {
2194         if (rtl_readphy(tp, reg) != val)
2195                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2196         else
2197                 rtl_apply_firmware(tp);
2198 }
2199
2200 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2201 {
2202         static const struct phy_reg phy_reg_init[] = {
2203                 { 0x1f, 0x0001 },
2204                 { 0x06, 0x006e },
2205                 { 0x08, 0x0708 },
2206                 { 0x15, 0x4000 },
2207                 { 0x18, 0x65c7 },
2208
2209                 { 0x1f, 0x0001 },
2210                 { 0x03, 0x00a1 },
2211                 { 0x02, 0x0008 },
2212                 { 0x01, 0x0120 },
2213                 { 0x00, 0x1000 },
2214                 { 0x04, 0x0800 },
2215                 { 0x04, 0x0000 },
2216
2217                 { 0x03, 0xff41 },
2218                 { 0x02, 0xdf60 },
2219                 { 0x01, 0x0140 },
2220                 { 0x00, 0x0077 },
2221                 { 0x04, 0x7800 },
2222                 { 0x04, 0x7000 },
2223
2224                 { 0x03, 0x802f },
2225                 { 0x02, 0x4f02 },
2226                 { 0x01, 0x0409 },
2227                 { 0x00, 0xf0f9 },
2228                 { 0x04, 0x9800 },
2229                 { 0x04, 0x9000 },
2230
2231                 { 0x03, 0xdf01 },
2232                 { 0x02, 0xdf20 },
2233                 { 0x01, 0xff95 },
2234                 { 0x00, 0xba00 },
2235                 { 0x04, 0xa800 },
2236                 { 0x04, 0xa000 },
2237
2238                 { 0x03, 0xff41 },
2239                 { 0x02, 0xdf20 },
2240                 { 0x01, 0x0140 },
2241                 { 0x00, 0x00bb },
2242                 { 0x04, 0xb800 },
2243                 { 0x04, 0xb000 },
2244
2245                 { 0x03, 0xdf41 },
2246                 { 0x02, 0xdc60 },
2247                 { 0x01, 0x6340 },
2248                 { 0x00, 0x007d },
2249                 { 0x04, 0xd800 },
2250                 { 0x04, 0xd000 },
2251
2252                 { 0x03, 0xdf01 },
2253                 { 0x02, 0xdf20 },
2254                 { 0x01, 0x100a },
2255                 { 0x00, 0xa0ff },
2256                 { 0x04, 0xf800 },
2257                 { 0x04, 0xf000 },
2258
2259                 { 0x1f, 0x0000 },
2260                 { 0x0b, 0x0000 },
2261                 { 0x00, 0x9200 }
2262         };
2263
2264         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2265 }
2266
2267 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2268 {
2269         static const struct phy_reg phy_reg_init[] = {
2270                 { 0x1f, 0x0002 },
2271                 { 0x01, 0x90d0 },
2272                 { 0x1f, 0x0000 }
2273         };
2274
2275         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2276 }
2277
2278 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2279 {
2280         struct pci_dev *pdev = tp->pci_dev;
2281
2282         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2283             (pdev->subsystem_device != 0xe000))
2284                 return;
2285
2286         rtl_writephy(tp, 0x1f, 0x0001);
2287         rtl_writephy(tp, 0x10, 0xf01b);
2288         rtl_writephy(tp, 0x1f, 0x0000);
2289 }
2290
2291 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2292 {
2293         static const struct phy_reg phy_reg_init[] = {
2294                 { 0x1f, 0x0001 },
2295                 { 0x04, 0x0000 },
2296                 { 0x03, 0x00a1 },
2297                 { 0x02, 0x0008 },
2298                 { 0x01, 0x0120 },
2299                 { 0x00, 0x1000 },
2300                 { 0x04, 0x0800 },
2301                 { 0x04, 0x9000 },
2302                 { 0x03, 0x802f },
2303                 { 0x02, 0x4f02 },
2304                 { 0x01, 0x0409 },
2305                 { 0x00, 0xf099 },
2306                 { 0x04, 0x9800 },
2307                 { 0x04, 0xa000 },
2308                 { 0x03, 0xdf01 },
2309                 { 0x02, 0xdf20 },
2310                 { 0x01, 0xff95 },
2311                 { 0x00, 0xba00 },
2312                 { 0x04, 0xa800 },
2313                 { 0x04, 0xf000 },
2314                 { 0x03, 0xdf01 },
2315                 { 0x02, 0xdf20 },
2316                 { 0x01, 0x101a },
2317                 { 0x00, 0xa0ff },
2318                 { 0x04, 0xf800 },
2319                 { 0x04, 0x0000 },
2320                 { 0x1f, 0x0000 },
2321
2322                 { 0x1f, 0x0001 },
2323                 { 0x10, 0xf41b },
2324                 { 0x14, 0xfb54 },
2325                 { 0x18, 0xf5c7 },
2326                 { 0x1f, 0x0000 },
2327
2328                 { 0x1f, 0x0001 },
2329                 { 0x17, 0x0cc0 },
2330                 { 0x1f, 0x0000 }
2331         };
2332
2333         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2334
2335         rtl8169scd_hw_phy_config_quirk(tp);
2336 }
2337
2338 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2339 {
2340         static const struct phy_reg phy_reg_init[] = {
2341                 { 0x1f, 0x0001 },
2342                 { 0x04, 0x0000 },
2343                 { 0x03, 0x00a1 },
2344                 { 0x02, 0x0008 },
2345                 { 0x01, 0x0120 },
2346                 { 0x00, 0x1000 },
2347                 { 0x04, 0x0800 },
2348                 { 0x04, 0x9000 },
2349                 { 0x03, 0x802f },
2350                 { 0x02, 0x4f02 },
2351                 { 0x01, 0x0409 },
2352                 { 0x00, 0xf099 },
2353                 { 0x04, 0x9800 },
2354                 { 0x04, 0xa000 },
2355                 { 0x03, 0xdf01 },
2356                 { 0x02, 0xdf20 },
2357                 { 0x01, 0xff95 },
2358                 { 0x00, 0xba00 },
2359                 { 0x04, 0xa800 },
2360                 { 0x04, 0xf000 },
2361                 { 0x03, 0xdf01 },
2362                 { 0x02, 0xdf20 },
2363                 { 0x01, 0x101a },
2364                 { 0x00, 0xa0ff },
2365                 { 0x04, 0xf800 },
2366                 { 0x04, 0x0000 },
2367                 { 0x1f, 0x0000 },
2368
2369                 { 0x1f, 0x0001 },
2370                 { 0x0b, 0x8480 },
2371                 { 0x1f, 0x0000 },
2372
2373                 { 0x1f, 0x0001 },
2374                 { 0x18, 0x67c7 },
2375                 { 0x04, 0x2000 },
2376                 { 0x03, 0x002f },
2377                 { 0x02, 0x4360 },
2378                 { 0x01, 0x0109 },
2379                 { 0x00, 0x3022 },
2380                 { 0x04, 0x2800 },
2381                 { 0x1f, 0x0000 },
2382
2383                 { 0x1f, 0x0001 },
2384                 { 0x17, 0x0cc0 },
2385                 { 0x1f, 0x0000 }
2386         };
2387
2388         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2389 }
2390
2391 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2392 {
2393         static const struct phy_reg phy_reg_init[] = {
2394                 { 0x10, 0xf41b },
2395                 { 0x1f, 0x0000 }
2396         };
2397
2398         rtl_writephy(tp, 0x1f, 0x0001);
2399         rtl_patchphy(tp, 0x16, 1 << 0);
2400
2401         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2402 }
2403
2404 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2405 {
2406         static const struct phy_reg phy_reg_init[] = {
2407                 { 0x1f, 0x0001 },
2408                 { 0x10, 0xf41b },
2409                 { 0x1f, 0x0000 }
2410         };
2411
2412         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2413 }
2414
2415 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2416 {
2417         static const struct phy_reg phy_reg_init[] = {
2418                 { 0x1f, 0x0000 },
2419                 { 0x1d, 0x0f00 },
2420                 { 0x1f, 0x0002 },
2421                 { 0x0c, 0x1ec8 },
2422                 { 0x1f, 0x0000 }
2423         };
2424
2425         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2426 }
2427
2428 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2429 {
2430         static const struct phy_reg phy_reg_init[] = {
2431                 { 0x1f, 0x0001 },
2432                 { 0x1d, 0x3d98 },
2433                 { 0x1f, 0x0000 }
2434         };
2435
2436         rtl_writephy(tp, 0x1f, 0x0000);
2437         rtl_patchphy(tp, 0x14, 1 << 5);
2438         rtl_patchphy(tp, 0x0d, 1 << 5);
2439
2440         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2441 }
2442
2443 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2444 {
2445         static const struct phy_reg phy_reg_init[] = {
2446                 { 0x1f, 0x0001 },
2447                 { 0x12, 0x2300 },
2448                 { 0x1f, 0x0002 },
2449                 { 0x00, 0x88d4 },
2450                 { 0x01, 0x82b1 },
2451                 { 0x03, 0x7002 },
2452                 { 0x08, 0x9e30 },
2453                 { 0x09, 0x01f0 },
2454                 { 0x0a, 0x5500 },
2455                 { 0x0c, 0x00c8 },
2456                 { 0x1f, 0x0003 },
2457                 { 0x12, 0xc096 },
2458                 { 0x16, 0x000a },
2459                 { 0x1f, 0x0000 },
2460                 { 0x1f, 0x0000 },
2461                 { 0x09, 0x2000 },
2462                 { 0x09, 0x0000 }
2463         };
2464
2465         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2466
2467         rtl_patchphy(tp, 0x14, 1 << 5);
2468         rtl_patchphy(tp, 0x0d, 1 << 5);
2469         rtl_writephy(tp, 0x1f, 0x0000);
2470 }
2471
2472 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2473 {
2474         static const struct phy_reg phy_reg_init[] = {
2475                 { 0x1f, 0x0001 },
2476                 { 0x12, 0x2300 },
2477                 { 0x03, 0x802f },
2478                 { 0x02, 0x4f02 },
2479                 { 0x01, 0x0409 },
2480                 { 0x00, 0xf099 },
2481                 { 0x04, 0x9800 },
2482                 { 0x04, 0x9000 },
2483                 { 0x1d, 0x3d98 },
2484                 { 0x1f, 0x0002 },
2485                 { 0x0c, 0x7eb8 },
2486                 { 0x06, 0x0761 },
2487                 { 0x1f, 0x0003 },
2488                 { 0x16, 0x0f0a },
2489                 { 0x1f, 0x0000 }
2490         };
2491
2492         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2493
2494         rtl_patchphy(tp, 0x16, 1 << 0);
2495         rtl_patchphy(tp, 0x14, 1 << 5);
2496         rtl_patchphy(tp, 0x0d, 1 << 5);
2497         rtl_writephy(tp, 0x1f, 0x0000);
2498 }
2499
2500 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2501 {
2502         static const struct phy_reg phy_reg_init[] = {
2503                 { 0x1f, 0x0001 },
2504                 { 0x12, 0x2300 },
2505                 { 0x1d, 0x3d98 },
2506                 { 0x1f, 0x0002 },
2507                 { 0x0c, 0x7eb8 },
2508                 { 0x06, 0x5461 },
2509                 { 0x1f, 0x0003 },
2510                 { 0x16, 0x0f0a },
2511                 { 0x1f, 0x0000 }
2512         };
2513
2514         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2515
2516         rtl_patchphy(tp, 0x16, 1 << 0);
2517         rtl_patchphy(tp, 0x14, 1 << 5);
2518         rtl_patchphy(tp, 0x0d, 1 << 5);
2519         rtl_writephy(tp, 0x1f, 0x0000);
2520 }
2521
2522 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2523 {
2524         rtl8168c_3_hw_phy_config(tp);
2525 }
2526
2527 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2528 {
2529         static const struct phy_reg phy_reg_init_0[] = {
2530                 /* Channel Estimation */
2531                 { 0x1f, 0x0001 },
2532                 { 0x06, 0x4064 },
2533                 { 0x07, 0x2863 },
2534                 { 0x08, 0x059c },
2535                 { 0x09, 0x26b4 },
2536                 { 0x0a, 0x6a19 },
2537                 { 0x0b, 0xdcc8 },
2538                 { 0x10, 0xf06d },
2539                 { 0x14, 0x7f68 },
2540                 { 0x18, 0x7fd9 },
2541                 { 0x1c, 0xf0ff },
2542                 { 0x1d, 0x3d9c },
2543                 { 0x1f, 0x0003 },
2544                 { 0x12, 0xf49f },
2545                 { 0x13, 0x070b },
2546                 { 0x1a, 0x05ad },
2547                 { 0x14, 0x94c0 },
2548
2549                 /*
2550                  * Tx Error Issue
2551                  * Enhance line driver power
2552                  */
2553                 { 0x1f, 0x0002 },
2554                 { 0x06, 0x5561 },
2555                 { 0x1f, 0x0005 },
2556                 { 0x05, 0x8332 },
2557                 { 0x06, 0x5561 },
2558
2559                 /*
2560                  * Can not link to 1Gbps with bad cable
2561                  * Decrease SNR threshold form 21.07dB to 19.04dB
2562                  */
2563                 { 0x1f, 0x0001 },
2564                 { 0x17, 0x0cc0 },
2565
2566                 { 0x1f, 0x0000 },
2567                 { 0x0d, 0xf880 }
2568         };
2569         void __iomem *ioaddr = tp->mmio_addr;
2570
2571         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2572
2573         /*
2574          * Rx Error Issue
2575          * Fine Tune Switching regulator parameter
2576          */
2577         rtl_writephy(tp, 0x1f, 0x0002);
2578         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2579         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2580
2581         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2582                 static const struct phy_reg phy_reg_init[] = {
2583                         { 0x1f, 0x0002 },
2584                         { 0x05, 0x669a },
2585                         { 0x1f, 0x0005 },
2586                         { 0x05, 0x8330 },
2587                         { 0x06, 0x669a },
2588                         { 0x1f, 0x0002 }
2589                 };
2590                 int val;
2591
2592                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2593
2594                 val = rtl_readphy(tp, 0x0d);
2595
2596                 if ((val & 0x00ff) != 0x006c) {
2597                         static const u32 set[] = {
2598                                 0x0065, 0x0066, 0x0067, 0x0068,
2599                                 0x0069, 0x006a, 0x006b, 0x006c
2600                         };
2601                         int i;
2602
2603                         rtl_writephy(tp, 0x1f, 0x0002);
2604
2605                         val &= 0xff00;
2606                         for (i = 0; i < ARRAY_SIZE(set); i++)
2607                                 rtl_writephy(tp, 0x0d, val | set[i]);
2608                 }
2609         } else {
2610                 static const struct phy_reg phy_reg_init[] = {
2611                         { 0x1f, 0x0002 },
2612                         { 0x05, 0x6662 },
2613                         { 0x1f, 0x0005 },
2614                         { 0x05, 0x8330 },
2615                         { 0x06, 0x6662 }
2616                 };
2617
2618                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2619         }
2620
2621         /* RSET couple improve */
2622         rtl_writephy(tp, 0x1f, 0x0002);
2623         rtl_patchphy(tp, 0x0d, 0x0300);
2624         rtl_patchphy(tp, 0x0f, 0x0010);
2625
2626         /* Fine tune PLL performance */
2627         rtl_writephy(tp, 0x1f, 0x0002);
2628         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2629         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2630
2631         rtl_writephy(tp, 0x1f, 0x0005);
2632         rtl_writephy(tp, 0x05, 0x001b);
2633
2634         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2635
2636         rtl_writephy(tp, 0x1f, 0x0000);
2637 }
2638
2639 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2640 {
2641         static const struct phy_reg phy_reg_init_0[] = {
2642                 /* Channel Estimation */
2643                 { 0x1f, 0x0001 },
2644                 { 0x06, 0x4064 },
2645                 { 0x07, 0x2863 },
2646                 { 0x08, 0x059c },
2647                 { 0x09, 0x26b4 },
2648                 { 0x0a, 0x6a19 },
2649                 { 0x0b, 0xdcc8 },
2650                 { 0x10, 0xf06d },
2651                 { 0x14, 0x7f68 },
2652                 { 0x18, 0x7fd9 },
2653                 { 0x1c, 0xf0ff },
2654                 { 0x1d, 0x3d9c },
2655                 { 0x1f, 0x0003 },
2656                 { 0x12, 0xf49f },
2657                 { 0x13, 0x070b },
2658                 { 0x1a, 0x05ad },
2659                 { 0x14, 0x94c0 },
2660
2661                 /*
2662                  * Tx Error Issue
2663                  * Enhance line driver power
2664                  */
2665                 { 0x1f, 0x0002 },
2666                 { 0x06, 0x5561 },
2667                 { 0x1f, 0x0005 },
2668                 { 0x05, 0x8332 },
2669                 { 0x06, 0x5561 },
2670
2671                 /*
2672                  * Can not link to 1Gbps with bad cable
2673                  * Decrease SNR threshold form 21.07dB to 19.04dB
2674                  */
2675                 { 0x1f, 0x0001 },
2676                 { 0x17, 0x0cc0 },
2677
2678                 { 0x1f, 0x0000 },
2679                 { 0x0d, 0xf880 }
2680         };
2681         void __iomem *ioaddr = tp->mmio_addr;
2682
2683         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2684
2685         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2686                 static const struct phy_reg phy_reg_init[] = {
2687                         { 0x1f, 0x0002 },
2688                         { 0x05, 0x669a },
2689                         { 0x1f, 0x0005 },
2690                         { 0x05, 0x8330 },
2691                         { 0x06, 0x669a },
2692
2693                         { 0x1f, 0x0002 }
2694                 };
2695                 int val;
2696
2697                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2698
2699                 val = rtl_readphy(tp, 0x0d);
2700                 if ((val & 0x00ff) != 0x006c) {
2701                         static const u32 set[] = {
2702                                 0x0065, 0x0066, 0x0067, 0x0068,
2703                                 0x0069, 0x006a, 0x006b, 0x006c
2704                         };
2705                         int i;
2706
2707                         rtl_writephy(tp, 0x1f, 0x0002);
2708
2709                         val &= 0xff00;
2710                         for (i = 0; i < ARRAY_SIZE(set); i++)
2711                                 rtl_writephy(tp, 0x0d, val | set[i]);
2712                 }
2713         } else {
2714                 static const struct phy_reg phy_reg_init[] = {
2715                         { 0x1f, 0x0002 },
2716                         { 0x05, 0x2642 },
2717                         { 0x1f, 0x0005 },
2718                         { 0x05, 0x8330 },
2719                         { 0x06, 0x2642 }
2720                 };
2721
2722                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2723         }
2724
2725         /* Fine tune PLL performance */
2726         rtl_writephy(tp, 0x1f, 0x0002);
2727         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2728         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2729
2730         /* Switching regulator Slew rate */
2731         rtl_writephy(tp, 0x1f, 0x0002);
2732         rtl_patchphy(tp, 0x0f, 0x0017);
2733
2734         rtl_writephy(tp, 0x1f, 0x0005);
2735         rtl_writephy(tp, 0x05, 0x001b);
2736
2737         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2738
2739         rtl_writephy(tp, 0x1f, 0x0000);
2740 }
2741
2742 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2743 {
2744         static const struct phy_reg phy_reg_init[] = {
2745                 { 0x1f, 0x0002 },
2746                 { 0x10, 0x0008 },
2747                 { 0x0d, 0x006c },
2748
2749                 { 0x1f, 0x0000 },
2750                 { 0x0d, 0xf880 },
2751
2752                 { 0x1f, 0x0001 },
2753                 { 0x17, 0x0cc0 },
2754
2755                 { 0x1f, 0x0001 },
2756                 { 0x0b, 0xa4d8 },
2757                 { 0x09, 0x281c },
2758                 { 0x07, 0x2883 },
2759                 { 0x0a, 0x6b35 },
2760                 { 0x1d, 0x3da4 },
2761                 { 0x1c, 0xeffd },
2762                 { 0x14, 0x7f52 },
2763                 { 0x18, 0x7fc6 },
2764                 { 0x08, 0x0601 },
2765                 { 0x06, 0x4063 },
2766                 { 0x10, 0xf074 },
2767                 { 0x1f, 0x0003 },
2768                 { 0x13, 0x0789 },
2769                 { 0x12, 0xf4bd },
2770                 { 0x1a, 0x04fd },
2771                 { 0x14, 0x84b0 },
2772                 { 0x1f, 0x0000 },
2773                 { 0x00, 0x9200 },
2774
2775                 { 0x1f, 0x0005 },
2776                 { 0x01, 0x0340 },
2777                 { 0x1f, 0x0001 },
2778                 { 0x04, 0x4000 },
2779                 { 0x03, 0x1d21 },
2780                 { 0x02, 0x0c32 },
2781                 { 0x01, 0x0200 },
2782                 { 0x00, 0x5554 },
2783                 { 0x04, 0x4800 },
2784                 { 0x04, 0x4000 },
2785                 { 0x04, 0xf000 },
2786                 { 0x03, 0xdf01 },
2787                 { 0x02, 0xdf20 },
2788                 { 0x01, 0x101a },
2789                 { 0x00, 0xa0ff },
2790                 { 0x04, 0xf800 },
2791                 { 0x04, 0xf000 },
2792                 { 0x1f, 0x0000 },
2793
2794                 { 0x1f, 0x0007 },
2795                 { 0x1e, 0x0023 },
2796                 { 0x16, 0x0000 },
2797                 { 0x1f, 0x0000 }
2798         };
2799
2800         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2801 }
2802
2803 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2804 {
2805         static const struct phy_reg phy_reg_init[] = {
2806                 { 0x1f, 0x0001 },
2807                 { 0x17, 0x0cc0 },
2808
2809                 { 0x1f, 0x0007 },
2810                 { 0x1e, 0x002d },
2811                 { 0x18, 0x0040 },
2812                 { 0x1f, 0x0000 }
2813         };
2814
2815         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2816         rtl_patchphy(tp, 0x0d, 1 << 5);
2817 }
2818
2819 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2820 {
2821         static const struct phy_reg phy_reg_init[] = {
2822                 /* Enable Delay cap */
2823                 { 0x1f, 0x0005 },
2824                 { 0x05, 0x8b80 },
2825                 { 0x06, 0xc896 },
2826                 { 0x1f, 0x0000 },
2827
2828                 /* Channel estimation fine tune */
2829                 { 0x1f, 0x0001 },
2830                 { 0x0b, 0x6c20 },
2831                 { 0x07, 0x2872 },
2832                 { 0x1c, 0xefff },
2833                 { 0x1f, 0x0003 },
2834                 { 0x14, 0x6420 },
2835                 { 0x1f, 0x0000 },
2836
2837                 /* Update PFM & 10M TX idle timer */
2838                 { 0x1f, 0x0007 },
2839                 { 0x1e, 0x002f },
2840                 { 0x15, 0x1919 },
2841                 { 0x1f, 0x0000 },
2842
2843                 { 0x1f, 0x0007 },
2844                 { 0x1e, 0x00ac },
2845                 { 0x18, 0x0006 },
2846                 { 0x1f, 0x0000 }
2847         };
2848
2849         rtl_apply_firmware(tp);
2850
2851         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2852
2853         /* DCO enable for 10M IDLE Power */
2854         rtl_writephy(tp, 0x1f, 0x0007);
2855         rtl_writephy(tp, 0x1e, 0x0023);
2856         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2857         rtl_writephy(tp, 0x1f, 0x0000);
2858
2859         /* For impedance matching */
2860         rtl_writephy(tp, 0x1f, 0x0002);
2861         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2862         rtl_writephy(tp, 0x1f, 0x0000);
2863
2864         /* PHY auto speed down */
2865         rtl_writephy(tp, 0x1f, 0x0007);
2866         rtl_writephy(tp, 0x1e, 0x002d);
2867         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2868         rtl_writephy(tp, 0x1f, 0x0000);
2869         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2870
2871         rtl_writephy(tp, 0x1f, 0x0005);
2872         rtl_writephy(tp, 0x05, 0x8b86);
2873         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2874         rtl_writephy(tp, 0x1f, 0x0000);
2875
2876         rtl_writephy(tp, 0x1f, 0x0005);
2877         rtl_writephy(tp, 0x05, 0x8b85);
2878         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2879         rtl_writephy(tp, 0x1f, 0x0007);
2880         rtl_writephy(tp, 0x1e, 0x0020);
2881         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2882         rtl_writephy(tp, 0x1f, 0x0006);
2883         rtl_writephy(tp, 0x00, 0x5a00);
2884         rtl_writephy(tp, 0x1f, 0x0000);
2885         rtl_writephy(tp, 0x0d, 0x0007);
2886         rtl_writephy(tp, 0x0e, 0x003c);
2887         rtl_writephy(tp, 0x0d, 0x4007);
2888         rtl_writephy(tp, 0x0e, 0x0000);
2889         rtl_writephy(tp, 0x0d, 0x0000);
2890 }
2891
2892 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2893 {
2894         static const struct phy_reg phy_reg_init[] = {
2895                 /* Enable Delay cap */
2896                 { 0x1f, 0x0004 },
2897                 { 0x1f, 0x0007 },
2898                 { 0x1e, 0x00ac },
2899                 { 0x18, 0x0006 },
2900                 { 0x1f, 0x0002 },
2901                 { 0x1f, 0x0000 },
2902                 { 0x1f, 0x0000 },
2903
2904                 /* Channel estimation fine tune */
2905                 { 0x1f, 0x0003 },
2906                 { 0x09, 0xa20f },
2907                 { 0x1f, 0x0000 },
2908                 { 0x1f, 0x0000 },
2909
2910                 /* Green Setting */
2911                 { 0x1f, 0x0005 },
2912                 { 0x05, 0x8b5b },
2913                 { 0x06, 0x9222 },
2914                 { 0x05, 0x8b6d },
2915                 { 0x06, 0x8000 },
2916                 { 0x05, 0x8b76 },
2917                 { 0x06, 0x8000 },
2918                 { 0x1f, 0x0000 }
2919         };
2920
2921         rtl_apply_firmware(tp);
2922
2923         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2924
2925         /* For 4-corner performance improve */
2926         rtl_writephy(tp, 0x1f, 0x0005);
2927         rtl_writephy(tp, 0x05, 0x8b80);
2928         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2929         rtl_writephy(tp, 0x1f, 0x0000);
2930
2931         /* PHY auto speed down */
2932         rtl_writephy(tp, 0x1f, 0x0004);
2933         rtl_writephy(tp, 0x1f, 0x0007);
2934         rtl_writephy(tp, 0x1e, 0x002d);
2935         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2936         rtl_writephy(tp, 0x1f, 0x0002);
2937         rtl_writephy(tp, 0x1f, 0x0000);
2938         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2939
2940         /* improve 10M EEE waveform */
2941         rtl_writephy(tp, 0x1f, 0x0005);
2942         rtl_writephy(tp, 0x05, 0x8b86);
2943         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2944         rtl_writephy(tp, 0x1f, 0x0000);
2945
2946         /* Improve 2-pair detection performance */
2947         rtl_writephy(tp, 0x1f, 0x0005);
2948         rtl_writephy(tp, 0x05, 0x8b85);
2949         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2950         rtl_writephy(tp, 0x1f, 0x0000);
2951
2952         /* EEE setting */
2953         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2954                      ERIAR_EXGMAC);
2955         rtl_writephy(tp, 0x1f, 0x0005);
2956         rtl_writephy(tp, 0x05, 0x8b85);
2957         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2958         rtl_writephy(tp, 0x1f, 0x0004);
2959         rtl_writephy(tp, 0x1f, 0x0007);
2960         rtl_writephy(tp, 0x1e, 0x0020);
2961         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
2962         rtl_writephy(tp, 0x1f, 0x0002);
2963         rtl_writephy(tp, 0x1f, 0x0000);
2964         rtl_writephy(tp, 0x0d, 0x0007);
2965         rtl_writephy(tp, 0x0e, 0x003c);
2966         rtl_writephy(tp, 0x0d, 0x4007);
2967         rtl_writephy(tp, 0x0e, 0x0000);
2968         rtl_writephy(tp, 0x0d, 0x0000);
2969
2970         /* Green feature */
2971         rtl_writephy(tp, 0x1f, 0x0003);
2972         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2973         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2974         rtl_writephy(tp, 0x1f, 0x0000);
2975 }
2976
2977 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
2978 {
2979         static const struct phy_reg phy_reg_init[] = {
2980                 /* Channel estimation fine tune */
2981                 { 0x1f, 0x0003 },
2982                 { 0x09, 0xa20f },
2983                 { 0x1f, 0x0000 },
2984
2985                 /* Modify green table for giga & fnet */
2986                 { 0x1f, 0x0005 },
2987                 { 0x05, 0x8b55 },
2988                 { 0x06, 0x0000 },
2989                 { 0x05, 0x8b5e },
2990                 { 0x06, 0x0000 },
2991                 { 0x05, 0x8b67 },
2992                 { 0x06, 0x0000 },
2993                 { 0x05, 0x8b70 },
2994                 { 0x06, 0x0000 },
2995                 { 0x1f, 0x0000 },
2996                 { 0x1f, 0x0007 },
2997                 { 0x1e, 0x0078 },
2998                 { 0x17, 0x0000 },
2999                 { 0x19, 0x00fb },
3000                 { 0x1f, 0x0000 },
3001
3002                 /* Modify green table for 10M */
3003                 { 0x1f, 0x0005 },
3004                 { 0x05, 0x8b79 },
3005                 { 0x06, 0xaa00 },
3006                 { 0x1f, 0x0000 },
3007
3008                 /* Disable hiimpedance detection (RTCT) */
3009                 { 0x1f, 0x0003 },
3010                 { 0x01, 0x328a },
3011                 { 0x1f, 0x0000 }
3012         };
3013
3014         rtl_apply_firmware(tp);
3015
3016         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3017
3018         /* For 4-corner performance improve */
3019         rtl_writephy(tp, 0x1f, 0x0005);
3020         rtl_writephy(tp, 0x05, 0x8b80);
3021         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3022         rtl_writephy(tp, 0x1f, 0x0000);
3023
3024         /* PHY auto speed down */
3025         rtl_writephy(tp, 0x1f, 0x0007);
3026         rtl_writephy(tp, 0x1e, 0x002d);
3027         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3028         rtl_writephy(tp, 0x1f, 0x0000);
3029         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3030
3031         /* Improve 10M EEE waveform */
3032         rtl_writephy(tp, 0x1f, 0x0005);
3033         rtl_writephy(tp, 0x05, 0x8b86);
3034         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3035         rtl_writephy(tp, 0x1f, 0x0000);
3036
3037         /* Improve 2-pair detection performance */
3038         rtl_writephy(tp, 0x1f, 0x0005);
3039         rtl_writephy(tp, 0x05, 0x8b85);
3040         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3041         rtl_writephy(tp, 0x1f, 0x0000);
3042 }
3043
3044 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3045 {
3046         rtl_apply_firmware(tp);
3047
3048         /* For 4-corner performance improve */
3049         rtl_writephy(tp, 0x1f, 0x0005);
3050         rtl_writephy(tp, 0x05, 0x8b80);
3051         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3052         rtl_writephy(tp, 0x1f, 0x0000);
3053
3054         /* PHY auto speed down */
3055         rtl_writephy(tp, 0x1f, 0x0007);
3056         rtl_writephy(tp, 0x1e, 0x002d);
3057         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3058         rtl_writephy(tp, 0x1f, 0x0000);
3059         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3060
3061         /* Improve 10M EEE waveform */
3062         rtl_writephy(tp, 0x1f, 0x0005);
3063         rtl_writephy(tp, 0x05, 0x8b86);
3064         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3065         rtl_writephy(tp, 0x1f, 0x0000);
3066 }
3067
3068 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3069 {
3070         static const struct phy_reg phy_reg_init[] = {
3071                 { 0x1f, 0x0003 },
3072                 { 0x08, 0x441d },
3073                 { 0x01, 0x9100 },
3074                 { 0x1f, 0x0000 }
3075         };
3076
3077         rtl_writephy(tp, 0x1f, 0x0000);
3078         rtl_patchphy(tp, 0x11, 1 << 12);
3079         rtl_patchphy(tp, 0x19, 1 << 13);
3080         rtl_patchphy(tp, 0x10, 1 << 15);
3081
3082         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3083 }
3084
3085 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3086 {
3087         static const struct phy_reg phy_reg_init[] = {
3088                 { 0x1f, 0x0005 },
3089                 { 0x1a, 0x0000 },
3090                 { 0x1f, 0x0000 },
3091
3092                 { 0x1f, 0x0004 },
3093                 { 0x1c, 0x0000 },
3094                 { 0x1f, 0x0000 },
3095
3096                 { 0x1f, 0x0001 },
3097                 { 0x15, 0x7701 },
3098                 { 0x1f, 0x0000 }
3099         };
3100
3101         /* Disable ALDPS before ram code */
3102         rtl_writephy(tp, 0x1f, 0x0000);
3103         rtl_writephy(tp, 0x18, 0x0310);
3104         msleep(100);
3105
3106         rtl_apply_firmware(tp);
3107
3108         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3109 }
3110
3111 static void rtl_hw_phy_config(struct net_device *dev)
3112 {
3113         struct rtl8169_private *tp = netdev_priv(dev);
3114
3115         rtl8169_print_mac_version(tp);
3116
3117         switch (tp->mac_version) {
3118         case RTL_GIGA_MAC_VER_01:
3119                 break;
3120         case RTL_GIGA_MAC_VER_02:
3121         case RTL_GIGA_MAC_VER_03:
3122                 rtl8169s_hw_phy_config(tp);
3123                 break;
3124         case RTL_GIGA_MAC_VER_04:
3125                 rtl8169sb_hw_phy_config(tp);
3126                 break;
3127         case RTL_GIGA_MAC_VER_05:
3128                 rtl8169scd_hw_phy_config(tp);
3129                 break;
3130         case RTL_GIGA_MAC_VER_06:
3131                 rtl8169sce_hw_phy_config(tp);
3132                 break;
3133         case RTL_GIGA_MAC_VER_07:
3134         case RTL_GIGA_MAC_VER_08:
3135         case RTL_GIGA_MAC_VER_09:
3136                 rtl8102e_hw_phy_config(tp);
3137                 break;
3138         case RTL_GIGA_MAC_VER_11:
3139                 rtl8168bb_hw_phy_config(tp);
3140                 break;
3141         case RTL_GIGA_MAC_VER_12:
3142                 rtl8168bef_hw_phy_config(tp);
3143                 break;
3144         case RTL_GIGA_MAC_VER_17:
3145                 rtl8168bef_hw_phy_config(tp);
3146                 break;
3147         case RTL_GIGA_MAC_VER_18:
3148                 rtl8168cp_1_hw_phy_config(tp);
3149                 break;
3150         case RTL_GIGA_MAC_VER_19:
3151                 rtl8168c_1_hw_phy_config(tp);
3152                 break;
3153         case RTL_GIGA_MAC_VER_20:
3154                 rtl8168c_2_hw_phy_config(tp);
3155                 break;
3156         case RTL_GIGA_MAC_VER_21:
3157                 rtl8168c_3_hw_phy_config(tp);
3158                 break;
3159         case RTL_GIGA_MAC_VER_22:
3160                 rtl8168c_4_hw_phy_config(tp);
3161                 break;
3162         case RTL_GIGA_MAC_VER_23:
3163         case RTL_GIGA_MAC_VER_24:
3164                 rtl8168cp_2_hw_phy_config(tp);
3165                 break;
3166         case RTL_GIGA_MAC_VER_25:
3167                 rtl8168d_1_hw_phy_config(tp);
3168                 break;
3169         case RTL_GIGA_MAC_VER_26:
3170                 rtl8168d_2_hw_phy_config(tp);
3171                 break;
3172         case RTL_GIGA_MAC_VER_27:
3173                 rtl8168d_3_hw_phy_config(tp);
3174                 break;
3175         case RTL_GIGA_MAC_VER_28:
3176                 rtl8168d_4_hw_phy_config(tp);
3177                 break;
3178         case RTL_GIGA_MAC_VER_29:
3179         case RTL_GIGA_MAC_VER_30:
3180                 rtl8105e_hw_phy_config(tp);
3181                 break;
3182         case RTL_GIGA_MAC_VER_31:
3183                 /* None. */
3184                 break;
3185         case RTL_GIGA_MAC_VER_32:
3186         case RTL_GIGA_MAC_VER_33:
3187                 rtl8168e_1_hw_phy_config(tp);
3188                 break;
3189         case RTL_GIGA_MAC_VER_34:
3190                 rtl8168e_2_hw_phy_config(tp);
3191                 break;
3192         case RTL_GIGA_MAC_VER_35:
3193                 rtl8168f_1_hw_phy_config(tp);
3194                 break;
3195         case RTL_GIGA_MAC_VER_36:
3196                 rtl8168f_2_hw_phy_config(tp);
3197                 break;
3198
3199         default:
3200                 break;
3201         }
3202 }
3203
3204 static void rtl8169_phy_timer(unsigned long __opaque)
3205 {
3206         struct net_device *dev = (struct net_device *)__opaque;
3207         struct rtl8169_private *tp = netdev_priv(dev);
3208         struct timer_list *timer = &tp->timer;
3209         void __iomem *ioaddr = tp->mmio_addr;
3210         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3211
3212         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3213
3214         spin_lock_irq(&tp->lock);
3215
3216         if (tp->phy_reset_pending(tp)) {
3217                 /*
3218                  * A busy loop could burn quite a few cycles on nowadays CPU.
3219                  * Let's delay the execution of the timer for a few ticks.
3220                  */
3221                 timeout = HZ/10;
3222                 goto out_mod_timer;
3223         }
3224
3225         if (tp->link_ok(ioaddr))
3226                 goto out_unlock;
3227
3228         netif_warn(tp, link, dev, "PHY reset until link up\n");
3229
3230         tp->phy_reset_enable(tp);
3231
3232 out_mod_timer:
3233         mod_timer(timer, jiffies + timeout);
3234 out_unlock:
3235         spin_unlock_irq(&tp->lock);
3236 }
3237
3238 #ifdef CONFIG_NET_POLL_CONTROLLER
3239 /*
3240  * Polling 'interrupt' - used by things like netconsole to send skbs
3241  * without having to re-enable interrupts. It's not called while
3242  * the interrupt routine is executing.
3243  */
3244 static void rtl8169_netpoll(struct net_device *dev)
3245 {
3246         struct rtl8169_private *tp = netdev_priv(dev);
3247         struct pci_dev *pdev = tp->pci_dev;
3248
3249         disable_irq(pdev->irq);
3250         rtl8169_interrupt(pdev->irq, dev);
3251         enable_irq(pdev->irq);
3252 }
3253 #endif
3254
3255 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3256                                   void __iomem *ioaddr)
3257 {
3258         iounmap(ioaddr);
3259         pci_release_regions(pdev);
3260         pci_clear_mwi(pdev);
3261         pci_disable_device(pdev);
3262         free_netdev(dev);
3263 }
3264
3265 static void rtl8169_phy_reset(struct net_device *dev,
3266                               struct rtl8169_private *tp)
3267 {
3268         unsigned int i;
3269
3270         tp->phy_reset_enable(tp);
3271         for (i = 0; i < 100; i++) {
3272                 if (!tp->phy_reset_pending(tp))
3273                         return;
3274                 msleep(1);
3275         }
3276         netif_err(tp, link, dev, "PHY reset failed\n");
3277 }
3278
3279 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3280 {
3281         void __iomem *ioaddr = tp->mmio_addr;
3282
3283         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3284             (RTL_R8(PHYstatus) & TBI_Enable);
3285 }
3286
3287 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3288 {
3289         void __iomem *ioaddr = tp->mmio_addr;
3290
3291         rtl_hw_phy_config(dev);
3292
3293         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3294                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3295                 RTL_W8(0x82, 0x01);
3296         }
3297
3298         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3299
3300         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3301                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3302
3303         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3304                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3305                 RTL_W8(0x82, 0x01);
3306                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3307                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3308         }
3309
3310         rtl8169_phy_reset(dev, tp);
3311
3312         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3313                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3314                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3315                           (tp->mii.supports_gmii ?
3316                            ADVERTISED_1000baseT_Half |
3317                            ADVERTISED_1000baseT_Full : 0));
3318
3319         if (rtl_tbi_enabled(tp))
3320                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3321 }
3322
3323 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3324 {
3325         void __iomem *ioaddr = tp->mmio_addr;
3326         u32 high;
3327         u32 low;
3328
3329         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3330         high = addr[4] | (addr[5] << 8);
3331
3332         spin_lock_irq(&tp->lock);
3333
3334         RTL_W8(Cfg9346, Cfg9346_Unlock);
3335
3336         RTL_W32(MAC4, high);
3337         RTL_R32(MAC4);
3338
3339         RTL_W32(MAC0, low);
3340         RTL_R32(MAC0);
3341
3342         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3343                 const struct exgmac_reg e[] = {
3344                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3345                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3346                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3347                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3348                                                                 low  >> 16 },
3349                 };
3350
3351                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3352         }
3353
3354         RTL_W8(Cfg9346, Cfg9346_Lock);
3355
3356         spin_unlock_irq(&tp->lock);
3357 }
3358
3359 static int rtl_set_mac_address(struct net_device *dev, void *p)
3360 {
3361         struct rtl8169_private *tp = netdev_priv(dev);
3362         struct sockaddr *addr = p;
3363
3364         if (!is_valid_ether_addr(addr->sa_data))
3365                 return -EADDRNOTAVAIL;
3366
3367         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3368
3369         rtl_rar_set(tp, dev->dev_addr);
3370
3371         return 0;
3372 }
3373
3374 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3375 {
3376         struct rtl8169_private *tp = netdev_priv(dev);
3377         struct mii_ioctl_data *data = if_mii(ifr);
3378
3379         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3380 }
3381
3382 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3383                           struct mii_ioctl_data *data, int cmd)
3384 {
3385         switch (cmd) {
3386         case SIOCGMIIPHY:
3387                 data->phy_id = 32; /* Internal PHY */
3388                 return 0;
3389
3390         case SIOCGMIIREG:
3391                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3392                 return 0;
3393
3394         case SIOCSMIIREG:
3395                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3396                 return 0;
3397         }
3398         return -EOPNOTSUPP;
3399 }
3400
3401 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3402 {
3403         return -EOPNOTSUPP;
3404 }
3405
3406 static const struct rtl_cfg_info {
3407         void (*hw_start)(struct net_device *);
3408         unsigned int region;
3409         unsigned int align;
3410         u16 intr_event;
3411         u16 napi_event;
3412         unsigned features;
3413         u8 default_ver;
3414 } rtl_cfg_infos [] = {
3415         [RTL_CFG_0] = {
3416                 .hw_start       = rtl_hw_start_8169,
3417                 .region         = 1,
3418                 .align          = 0,
3419                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3420                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3421                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3422                 .features       = RTL_FEATURE_GMII,
3423                 .default_ver    = RTL_GIGA_MAC_VER_01,
3424         },
3425         [RTL_CFG_1] = {
3426                 .hw_start       = rtl_hw_start_8168,
3427                 .region         = 2,
3428                 .align          = 8,
3429                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3430                                   TxErr | TxOK | RxOK | RxErr,
3431                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
3432                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3433                 .default_ver    = RTL_GIGA_MAC_VER_11,
3434         },
3435         [RTL_CFG_2] = {
3436                 .hw_start       = rtl_hw_start_8101,
3437                 .region         = 2,
3438                 .align          = 8,
3439                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3440                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3441                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3442                 .features       = RTL_FEATURE_MSI,
3443                 .default_ver    = RTL_GIGA_MAC_VER_13,
3444         }
3445 };
3446
3447 /* Cfg9346_Unlock assumed. */
3448 static unsigned rtl_try_msi(struct rtl8169_private *tp,
3449                             const struct rtl_cfg_info *cfg)
3450 {
3451         void __iomem *ioaddr = tp->mmio_addr;
3452         unsigned msi = 0;
3453         u8 cfg2;
3454
3455         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3456         if (cfg->features & RTL_FEATURE_MSI) {
3457                 if (pci_enable_msi(tp->pci_dev)) {
3458                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
3459                 } else {
3460                         cfg2 |= MSIEnable;
3461                         msi = RTL_FEATURE_MSI;
3462                 }
3463         }
3464         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3465                 RTL_W8(Config2, cfg2);
3466         return msi;
3467 }
3468
3469 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3470 {
3471         if (tp->features & RTL_FEATURE_MSI) {
3472                 pci_disable_msi(pdev);
3473                 tp->features &= ~RTL_FEATURE_MSI;
3474         }
3475 }
3476
3477 static const struct net_device_ops rtl8169_netdev_ops = {
3478         .ndo_open               = rtl8169_open,
3479         .ndo_stop               = rtl8169_close,
3480         .ndo_get_stats          = rtl8169_get_stats,
3481         .ndo_start_xmit         = rtl8169_start_xmit,
3482         .ndo_tx_timeout         = rtl8169_tx_timeout,
3483         .ndo_validate_addr      = eth_validate_addr,
3484         .ndo_change_mtu         = rtl8169_change_mtu,
3485         .ndo_fix_features       = rtl8169_fix_features,
3486         .ndo_set_features       = rtl8169_set_features,
3487         .ndo_set_mac_address    = rtl_set_mac_address,
3488         .ndo_do_ioctl           = rtl8169_ioctl,
3489         .ndo_set_rx_mode        = rtl_set_rx_mode,
3490 #ifdef CONFIG_NET_POLL_CONTROLLER
3491         .ndo_poll_controller    = rtl8169_netpoll,
3492 #endif
3493
3494 };
3495
3496 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3497 {
3498         struct mdio_ops *ops = &tp->mdio_ops;
3499
3500         switch (tp->mac_version) {
3501         case RTL_GIGA_MAC_VER_27:
3502                 ops->write      = r8168dp_1_mdio_write;
3503                 ops->read       = r8168dp_1_mdio_read;
3504                 break;
3505         case RTL_GIGA_MAC_VER_28:
3506         case RTL_GIGA_MAC_VER_31:
3507                 ops->write      = r8168dp_2_mdio_write;
3508                 ops->read       = r8168dp_2_mdio_read;
3509                 break;
3510         default:
3511                 ops->write      = r8169_mdio_write;
3512                 ops->read       = r8169_mdio_read;
3513                 break;
3514         }
3515 }
3516
3517 static void rtl_speed_down(struct rtl8169_private *tp)
3518 {
3519         u32 adv;
3520         int lpa;
3521
3522         rtl_writephy(tp, 0x1f, 0x0000);
3523         lpa = rtl_readphy(tp, MII_LPA);
3524
3525         if (lpa & (LPA_10HALF | LPA_10FULL))
3526                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3527         else if (lpa & (LPA_100HALF | LPA_100FULL))
3528                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3529                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3530         else
3531                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3532                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3533                       (tp->mii.supports_gmii ?
3534                        ADVERTISED_1000baseT_Half |
3535                        ADVERTISED_1000baseT_Full : 0);
3536
3537         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3538                           adv);
3539 }
3540
3541 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3542 {
3543         void __iomem *ioaddr = tp->mmio_addr;
3544
3545         switch (tp->mac_version) {
3546         case RTL_GIGA_MAC_VER_25:
3547         case RTL_GIGA_MAC_VER_26:
3548         case RTL_GIGA_MAC_VER_29:
3549         case RTL_GIGA_MAC_VER_30:
3550         case RTL_GIGA_MAC_VER_32:
3551         case RTL_GIGA_MAC_VER_33:
3552         case RTL_GIGA_MAC_VER_34:
3553                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3554                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3555                 break;
3556         default:
3557                 break;
3558         }
3559 }
3560
3561 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3562 {
3563         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3564                 return false;
3565
3566         rtl_speed_down(tp);
3567         rtl_wol_suspend_quirk(tp);
3568
3569         return true;
3570 }
3571
3572 static void r810x_phy_power_down(struct rtl8169_private *tp)
3573 {
3574         rtl_writephy(tp, 0x1f, 0x0000);
3575         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3576 }
3577
3578 static void r810x_phy_power_up(struct rtl8169_private *tp)
3579 {
3580         rtl_writephy(tp, 0x1f, 0x0000);
3581         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3582 }
3583
3584 static void r810x_pll_power_down(struct rtl8169_private *tp)
3585 {
3586         if (rtl_wol_pll_power_down(tp))
3587                 return;
3588
3589         r810x_phy_power_down(tp);
3590 }
3591
3592 static void r810x_pll_power_up(struct rtl8169_private *tp)
3593 {
3594         r810x_phy_power_up(tp);
3595 }
3596
3597 static void r8168_phy_power_up(struct rtl8169_private *tp)
3598 {
3599         rtl_writephy(tp, 0x1f, 0x0000);
3600         switch (tp->mac_version) {
3601         case RTL_GIGA_MAC_VER_11:
3602         case RTL_GIGA_MAC_VER_12:
3603         case RTL_GIGA_MAC_VER_17:
3604         case RTL_GIGA_MAC_VER_18:
3605         case RTL_GIGA_MAC_VER_19:
3606         case RTL_GIGA_MAC_VER_20:
3607         case RTL_GIGA_MAC_VER_21:
3608         case RTL_GIGA_MAC_VER_22:
3609         case RTL_GIGA_MAC_VER_23:
3610         case RTL_GIGA_MAC_VER_24:
3611         case RTL_GIGA_MAC_VER_25:
3612         case RTL_GIGA_MAC_VER_26:
3613         case RTL_GIGA_MAC_VER_27:
3614         case RTL_GIGA_MAC_VER_28:
3615         case RTL_GIGA_MAC_VER_31:
3616                 rtl_writephy(tp, 0x0e, 0x0000);
3617                 break;
3618         default:
3619                 break;
3620         }
3621         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3622 }
3623
3624 static void r8168_phy_power_down(struct rtl8169_private *tp)
3625 {
3626         rtl_writephy(tp, 0x1f, 0x0000);
3627         switch (tp->mac_version) {
3628         case RTL_GIGA_MAC_VER_32:
3629         case RTL_GIGA_MAC_VER_33:
3630                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3631                 break;
3632
3633         case RTL_GIGA_MAC_VER_11:
3634         case RTL_GIGA_MAC_VER_12:
3635         case RTL_GIGA_MAC_VER_17:
3636         case RTL_GIGA_MAC_VER_18:
3637         case RTL_GIGA_MAC_VER_19:
3638         case RTL_GIGA_MAC_VER_20:
3639         case RTL_GIGA_MAC_VER_21:
3640         case RTL_GIGA_MAC_VER_22:
3641         case RTL_GIGA_MAC_VER_23:
3642         case RTL_GIGA_MAC_VER_24:
3643         case RTL_GIGA_MAC_VER_25:
3644         case RTL_GIGA_MAC_VER_26:
3645         case RTL_GIGA_MAC_VER_27:
3646         case RTL_GIGA_MAC_VER_28:
3647         case RTL_GIGA_MAC_VER_31:
3648                 rtl_writephy(tp, 0x0e, 0x0200);
3649         default:
3650                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3651                 break;
3652         }
3653 }
3654
3655 static void r8168_pll_power_down(struct rtl8169_private *tp)
3656 {
3657         void __iomem *ioaddr = tp->mmio_addr;
3658
3659         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3660              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3661              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3662             r8168dp_check_dash(tp)) {
3663                 return;
3664         }
3665
3666         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3667              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3668             (RTL_R16(CPlusCmd) & ASF)) {
3669                 return;
3670         }
3671
3672         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3673             tp->mac_version == RTL_GIGA_MAC_VER_33)
3674                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3675
3676         if (rtl_wol_pll_power_down(tp))
3677                 return;
3678
3679         r8168_phy_power_down(tp);
3680
3681         switch (tp->mac_version) {
3682         case RTL_GIGA_MAC_VER_25:
3683         case RTL_GIGA_MAC_VER_26:
3684         case RTL_GIGA_MAC_VER_27:
3685         case RTL_GIGA_MAC_VER_28:
3686         case RTL_GIGA_MAC_VER_31:
3687         case RTL_GIGA_MAC_VER_32:
3688         case RTL_GIGA_MAC_VER_33:
3689                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3690                 break;
3691         }
3692 }
3693
3694 static void r8168_pll_power_up(struct rtl8169_private *tp)
3695 {
3696         void __iomem *ioaddr = tp->mmio_addr;
3697
3698         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3699              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3700              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3701             r8168dp_check_dash(tp)) {
3702                 return;
3703         }
3704
3705         switch (tp->mac_version) {
3706         case RTL_GIGA_MAC_VER_25:
3707         case RTL_GIGA_MAC_VER_26:
3708         case RTL_GIGA_MAC_VER_27:
3709         case RTL_GIGA_MAC_VER_28:
3710         case RTL_GIGA_MAC_VER_31:
3711         case RTL_GIGA_MAC_VER_32:
3712         case RTL_GIGA_MAC_VER_33:
3713                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3714                 break;
3715         }
3716
3717         r8168_phy_power_up(tp);
3718 }
3719
3720 static void rtl_generic_op(struct rtl8169_private *tp,
3721                            void (*op)(struct rtl8169_private *))
3722 {
3723         if (op)
3724                 op(tp);
3725 }
3726
3727 static void rtl_pll_power_down(struct rtl8169_private *tp)
3728 {
3729         rtl_generic_op(tp, tp->pll_power_ops.down);
3730 }
3731
3732 static void rtl_pll_power_up(struct rtl8169_private *tp)
3733 {
3734         rtl_generic_op(tp, tp->pll_power_ops.up);
3735 }
3736
3737 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3738 {
3739         struct pll_power_ops *ops = &tp->pll_power_ops;
3740
3741         switch (tp->mac_version) {
3742         case RTL_GIGA_MAC_VER_07:
3743         case RTL_GIGA_MAC_VER_08:
3744         case RTL_GIGA_MAC_VER_09:
3745         case RTL_GIGA_MAC_VER_10:
3746         case RTL_GIGA_MAC_VER_16:
3747         case RTL_GIGA_MAC_VER_29:
3748         case RTL_GIGA_MAC_VER_30:
3749                 ops->down       = r810x_pll_power_down;
3750                 ops->up         = r810x_pll_power_up;
3751                 break;
3752
3753         case RTL_GIGA_MAC_VER_11:
3754         case RTL_GIGA_MAC_VER_12:
3755         case RTL_GIGA_MAC_VER_17:
3756         case RTL_GIGA_MAC_VER_18:
3757         case RTL_GIGA_MAC_VER_19:
3758         case RTL_GIGA_MAC_VER_20:
3759         case RTL_GIGA_MAC_VER_21:
3760         case RTL_GIGA_MAC_VER_22:
3761         case RTL_GIGA_MAC_VER_23:
3762         case RTL_GIGA_MAC_VER_24:
3763         case RTL_GIGA_MAC_VER_25:
3764         case RTL_GIGA_MAC_VER_26:
3765         case RTL_GIGA_MAC_VER_27:
3766         case RTL_GIGA_MAC_VER_28:
3767         case RTL_GIGA_MAC_VER_31:
3768         case RTL_GIGA_MAC_VER_32:
3769         case RTL_GIGA_MAC_VER_33:
3770         case RTL_GIGA_MAC_VER_34:
3771         case RTL_GIGA_MAC_VER_35:
3772         case RTL_GIGA_MAC_VER_36:
3773                 ops->down       = r8168_pll_power_down;
3774                 ops->up         = r8168_pll_power_up;
3775                 break;
3776
3777         default:
3778                 ops->down       = NULL;
3779                 ops->up         = NULL;
3780                 break;
3781         }
3782 }
3783
3784 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3785 {
3786         void __iomem *ioaddr = tp->mmio_addr;
3787
3788         switch (tp->mac_version) {
3789         case RTL_GIGA_MAC_VER_01:
3790         case RTL_GIGA_MAC_VER_02:
3791         case RTL_GIGA_MAC_VER_03:
3792         case RTL_GIGA_MAC_VER_04:
3793         case RTL_GIGA_MAC_VER_05:
3794         case RTL_GIGA_MAC_VER_06:
3795         case RTL_GIGA_MAC_VER_10:
3796         case RTL_GIGA_MAC_VER_11:
3797         case RTL_GIGA_MAC_VER_12:
3798         case RTL_GIGA_MAC_VER_13:
3799         case RTL_GIGA_MAC_VER_14:
3800         case RTL_GIGA_MAC_VER_15:
3801         case RTL_GIGA_MAC_VER_16:
3802         case RTL_GIGA_MAC_VER_17:
3803                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3804                 break;
3805         case RTL_GIGA_MAC_VER_18:
3806         case RTL_GIGA_MAC_VER_19:
3807         case RTL_GIGA_MAC_VER_20:
3808         case RTL_GIGA_MAC_VER_21:
3809         case RTL_GIGA_MAC_VER_22:
3810         case RTL_GIGA_MAC_VER_23:
3811         case RTL_GIGA_MAC_VER_24:
3812         case RTL_GIGA_MAC_VER_34:
3813                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3814                 break;
3815         default:
3816                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3817                 break;
3818         }
3819 }
3820
3821 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3822 {
3823         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3824 }
3825
3826 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3827 {
3828         void __iomem *ioaddr = tp->mmio_addr;
3829
3830         RTL_W8(Cfg9346, Cfg9346_Unlock);
3831         rtl_generic_op(tp, tp->jumbo_ops.enable);
3832         RTL_W8(Cfg9346, Cfg9346_Lock);
3833 }
3834
3835 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3836 {
3837         void __iomem *ioaddr = tp->mmio_addr;
3838
3839         RTL_W8(Cfg9346, Cfg9346_Unlock);
3840         rtl_generic_op(tp, tp->jumbo_ops.disable);
3841         RTL_W8(Cfg9346, Cfg9346_Lock);
3842 }
3843
3844 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3845 {
3846         void __iomem *ioaddr = tp->mmio_addr;
3847
3848         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3849         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3850         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3851 }
3852
3853 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3854 {
3855         void __iomem *ioaddr = tp->mmio_addr;
3856
3857         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3858         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3859         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3860 }
3861
3862 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3863 {
3864         void __iomem *ioaddr = tp->mmio_addr;
3865
3866         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3867 }
3868
3869 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3870 {
3871         void __iomem *ioaddr = tp->mmio_addr;
3872
3873         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3874 }
3875
3876 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3877 {
3878         void __iomem *ioaddr = tp->mmio_addr;
3879         struct pci_dev *pdev = tp->pci_dev;
3880
3881         RTL_W8(MaxTxPacketSize, 0x3f);
3882         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3883         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3884         pci_write_config_byte(pdev, 0x79, 0x20);
3885 }
3886
3887 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3888 {
3889         void __iomem *ioaddr = tp->mmio_addr;
3890         struct pci_dev *pdev = tp->pci_dev;
3891
3892         RTL_W8(MaxTxPacketSize, 0x0c);
3893         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3894         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3895         pci_write_config_byte(pdev, 0x79, 0x50);
3896 }
3897
3898 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3899 {
3900         rtl_tx_performance_tweak(tp->pci_dev,
3901                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3902 }
3903
3904 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3905 {
3906         rtl_tx_performance_tweak(tp->pci_dev,
3907                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3908 }
3909
3910 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3911 {
3912         void __iomem *ioaddr = tp->mmio_addr;
3913
3914         r8168b_0_hw_jumbo_enable(tp);
3915
3916         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3917 }
3918
3919 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3920 {
3921         void __iomem *ioaddr = tp->mmio_addr;
3922
3923         r8168b_0_hw_jumbo_disable(tp);
3924
3925         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3926 }
3927
3928 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3929 {
3930         struct jumbo_ops *ops = &tp->jumbo_ops;
3931
3932         switch (tp->mac_version) {
3933         case RTL_GIGA_MAC_VER_11:
3934                 ops->disable    = r8168b_0_hw_jumbo_disable;
3935                 ops->enable     = r8168b_0_hw_jumbo_enable;
3936                 break;
3937         case RTL_GIGA_MAC_VER_12:
3938         case RTL_GIGA_MAC_VER_17:
3939                 ops->disable    = r8168b_1_hw_jumbo_disable;
3940                 ops->enable     = r8168b_1_hw_jumbo_enable;
3941                 break;
3942         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3943         case RTL_GIGA_MAC_VER_19:
3944         case RTL_GIGA_MAC_VER_20:
3945         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3946         case RTL_GIGA_MAC_VER_22:
3947         case RTL_GIGA_MAC_VER_23:
3948         case RTL_GIGA_MAC_VER_24:
3949         case RTL_GIGA_MAC_VER_25:
3950         case RTL_GIGA_MAC_VER_26:
3951                 ops->disable    = r8168c_hw_jumbo_disable;
3952                 ops->enable     = r8168c_hw_jumbo_enable;
3953                 break;
3954         case RTL_GIGA_MAC_VER_27:
3955         case RTL_GIGA_MAC_VER_28:
3956                 ops->disable    = r8168dp_hw_jumbo_disable;
3957                 ops->enable     = r8168dp_hw_jumbo_enable;
3958                 break;
3959         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3960         case RTL_GIGA_MAC_VER_32:
3961         case RTL_GIGA_MAC_VER_33:
3962         case RTL_GIGA_MAC_VER_34:
3963                 ops->disable    = r8168e_hw_jumbo_disable;
3964                 ops->enable     = r8168e_hw_jumbo_enable;
3965                 break;
3966
3967         /*
3968          * No action needed for jumbo frames with 8169.
3969          * No jumbo for 810x at all.
3970          */
3971         default:
3972                 ops->disable    = NULL;
3973                 ops->enable     = NULL;
3974                 break;
3975         }
3976 }
3977
3978 static void rtl_hw_reset(struct rtl8169_private *tp)
3979 {
3980         void __iomem *ioaddr = tp->mmio_addr;
3981         int i;
3982
3983         /* Soft reset the chip. */
3984         RTL_W8(ChipCmd, CmdReset);
3985
3986         /* Check that the chip has finished the reset. */
3987         for (i = 0; i < 100; i++) {
3988                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3989                         break;
3990                 udelay(100);
3991         }
3992 }
3993
3994 static int __devinit
3995 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3996 {
3997         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3998         const unsigned int region = cfg->region;
3999         struct rtl8169_private *tp;
4000         struct mii_if_info *mii;
4001         struct net_device *dev;
4002         void __iomem *ioaddr;
4003         int chipset, i;
4004         int rc;
4005
4006         if (netif_msg_drv(&debug)) {
4007                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
4008                        MODULENAME, RTL8169_VERSION);
4009         }
4010
4011         dev = alloc_etherdev(sizeof (*tp));
4012         if (!dev) {
4013                 if (netif_msg_drv(&debug))
4014                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4015                 rc = -ENOMEM;
4016                 goto out;
4017         }
4018
4019         SET_NETDEV_DEV(dev, &pdev->dev);
4020         dev->netdev_ops = &rtl8169_netdev_ops;
4021         tp = netdev_priv(dev);
4022         tp->dev = dev;
4023         tp->pci_dev = pdev;
4024         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
4025
4026         mii = &tp->mii;
4027         mii->dev = dev;
4028         mii->mdio_read = rtl_mdio_read;
4029         mii->mdio_write = rtl_mdio_write;
4030         mii->phy_id_mask = 0x1f;
4031         mii->reg_num_mask = 0x1f;
4032         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
4033
4034         /* disable ASPM completely as that cause random device stop working
4035          * problems as well as full system hangs for some PCIe devices users */
4036         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4037                                      PCIE_LINK_STATE_CLKPM);
4038
4039         /* enable device (incl. PCI PM wakeup and hotplug setup) */
4040         rc = pci_enable_device(pdev);
4041         if (rc < 0) {
4042                 netif_err(tp, probe, dev, "enable failure\n");
4043                 goto err_out_free_dev_1;
4044         }
4045
4046         if (pci_set_mwi(pdev) < 0)
4047                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
4048
4049         /* make sure PCI base addr 1 is MMIO */
4050         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4051                 netif_err(tp, probe, dev,
4052                           "region #%d not an MMIO resource, aborting\n",
4053                           region);
4054                 rc = -ENODEV;
4055                 goto err_out_mwi_2;
4056         }
4057
4058         /* check for weird/broken PCI region reporting */
4059         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4060                 netif_err(tp, probe, dev,
4061                           "Invalid PCI region size(s), aborting\n");
4062                 rc = -ENODEV;
4063                 goto err_out_mwi_2;
4064         }
4065
4066         rc = pci_request_regions(pdev, MODULENAME);
4067         if (rc < 0) {
4068                 netif_err(tp, probe, dev, "could not request regions\n");
4069                 goto err_out_mwi_2;
4070         }
4071
4072         tp->cp_cmd = RxChkSum;
4073
4074         if ((sizeof(dma_addr_t) > 4) &&
4075             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
4076                 tp->cp_cmd |= PCIDAC;
4077                 dev->features |= NETIF_F_HIGHDMA;
4078         } else {
4079                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4080                 if (rc < 0) {
4081                         netif_err(tp, probe, dev, "DMA configuration failed\n");
4082                         goto err_out_free_res_3;
4083                 }
4084         }
4085
4086         /* ioremap MMIO region */
4087         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4088         if (!ioaddr) {
4089                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
4090                 rc = -EIO;
4091                 goto err_out_free_res_3;
4092         }
4093         tp->mmio_addr = ioaddr;
4094
4095         if (!pci_is_pcie(pdev))
4096                 netif_info(tp, probe, dev, "not PCI Express\n");
4097
4098         /* Identify chip attached to board */
4099         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
4100
4101         rtl_init_rxcfg(tp);
4102
4103         RTL_W16(IntrMask, 0x0000);
4104
4105         rtl_hw_reset(tp);
4106
4107         RTL_W16(IntrStatus, 0xffff);
4108
4109         pci_set_master(pdev);
4110
4111         /*
4112          * Pretend we are using VLANs; This bypasses a nasty bug where
4113          * Interrupts stop flowing on high load on 8110SCd controllers.
4114          */
4115         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4116                 tp->cp_cmd |= RxVlan;
4117
4118         rtl_init_mdio_ops(tp);
4119         rtl_init_pll_power_ops(tp);
4120         rtl_init_jumbo_ops(tp);
4121
4122         rtl8169_print_mac_version(tp);
4123
4124         chipset = tp->mac_version;
4125         tp->txd_version = rtl_chip_infos[chipset].txd_version;
4126
4127         RTL_W8(Cfg9346, Cfg9346_Unlock);
4128         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
4129         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
4130         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
4131                 tp->features |= RTL_FEATURE_WOL;
4132         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
4133                 tp->features |= RTL_FEATURE_WOL;
4134         tp->features |= rtl_try_msi(tp, cfg);
4135         RTL_W8(Cfg9346, Cfg9346_Lock);
4136
4137         if (rtl_tbi_enabled(tp)) {
4138                 tp->set_speed = rtl8169_set_speed_tbi;
4139                 tp->get_settings = rtl8169_gset_tbi;
4140                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
4141                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
4142                 tp->link_ok = rtl8169_tbi_link_ok;
4143                 tp->do_ioctl = rtl_tbi_ioctl;
4144         } else {
4145                 tp->set_speed = rtl8169_set_speed_xmii;
4146                 tp->get_settings = rtl8169_gset_xmii;
4147                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
4148                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
4149                 tp->link_ok = rtl8169_xmii_link_ok;
4150                 tp->do_ioctl = rtl_xmii_ioctl;
4151         }
4152
4153         spin_lock_init(&tp->lock);
4154
4155         /* Get MAC address */
4156         for (i = 0; i < MAC_ADDR_LEN; i++)
4157                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
4158         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4159
4160         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
4161         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
4162         dev->irq = pdev->irq;
4163         dev->base_addr = (unsigned long) ioaddr;
4164
4165         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
4166
4167         /* don't enable SG, IP_CSUM and TSO by default - it might not work
4168          * properly for all devices */
4169         dev->features |= NETIF_F_RXCSUM |
4170                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4171
4172         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4173                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4174         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4175                 NETIF_F_HIGHDMA;
4176
4177         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4178                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4179                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
4180
4181         tp->intr_mask = 0xffff;
4182         tp->hw_start = cfg->hw_start;
4183         tp->intr_event = cfg->intr_event;
4184         tp->napi_event = cfg->napi_event;
4185
4186         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
4187                 ~(RxBOVF | RxFOVF) : ~0;
4188
4189         init_timer(&tp->timer);
4190         tp->timer.data = (unsigned long) dev;
4191         tp->timer.function = rtl8169_phy_timer;
4192
4193         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
4194
4195         rc = register_netdev(dev);
4196         if (rc < 0)
4197                 goto err_out_msi_4;
4198
4199         pci_set_drvdata(pdev, dev);
4200
4201         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
4202                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
4203                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
4204         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
4205                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
4206                            "tx checksumming: %s]\n",
4207                            rtl_chip_infos[chipset].jumbo_max,
4208                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
4209         }
4210
4211         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4212             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4213             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4214                 rtl8168_driver_start(tp);
4215         }
4216
4217         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
4218
4219         if (pci_dev_run_wake(pdev))
4220                 pm_runtime_put_noidle(&pdev->dev);
4221
4222         netif_carrier_off(dev);
4223
4224 out:
4225         return rc;
4226
4227 err_out_msi_4:
4228         netif_napi_del(&tp->napi);
4229         rtl_disable_msi(pdev, tp);
4230         iounmap(ioaddr);
4231 err_out_free_res_3:
4232         pci_release_regions(pdev);
4233 err_out_mwi_2:
4234         pci_clear_mwi(pdev);
4235         pci_disable_device(pdev);
4236 err_out_free_dev_1:
4237         free_netdev(dev);
4238         goto out;
4239 }
4240
4241 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
4242 {
4243         struct net_device *dev = pci_get_drvdata(pdev);
4244         struct rtl8169_private *tp = netdev_priv(dev);
4245
4246         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4247             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4248             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4249                 rtl8168_driver_stop(tp);
4250         }
4251
4252         cancel_delayed_work_sync(&tp->task);
4253
4254         netif_napi_del(&tp->napi);
4255
4256         unregister_netdev(dev);
4257
4258         rtl_release_firmware(tp);
4259
4260         if (pci_dev_run_wake(pdev))
4261                 pm_runtime_get_noresume(&pdev->dev);
4262
4263         /* restore original MAC address */
4264         rtl_rar_set(tp, dev->perm_addr);
4265
4266         rtl_disable_msi(pdev, tp);
4267         rtl8169_release_board(pdev, dev, tp->mmio_addr);
4268         pci_set_drvdata(pdev, NULL);
4269 }
4270
4271 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4272 {
4273         struct rtl_fw *rtl_fw;
4274         const char *name;
4275         int rc = -ENOMEM;
4276
4277         name = rtl_lookup_firmware_name(tp);
4278         if (!name)
4279                 goto out_no_firmware;
4280
4281         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4282         if (!rtl_fw)
4283                 goto err_warn;
4284
4285         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4286         if (rc < 0)
4287                 goto err_free;
4288
4289         rc = rtl_check_firmware(tp, rtl_fw);
4290         if (rc < 0)
4291                 goto err_release_firmware;
4292
4293         tp->rtl_fw = rtl_fw;
4294 out:
4295         return;
4296
4297 err_release_firmware:
4298         release_firmware(rtl_fw->fw);
4299 err_free:
4300         kfree(rtl_fw);
4301 err_warn:
4302         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4303                    name, rc);
4304 out_no_firmware:
4305         tp->rtl_fw = NULL;
4306         goto out;
4307 }
4308
4309 static void rtl_request_firmware(struct rtl8169_private *tp)
4310 {
4311         if (IS_ERR(tp->rtl_fw))
4312                 rtl_request_uncached_firmware(tp);
4313 }
4314
4315 static int rtl8169_open(struct net_device *dev)
4316 {
4317         struct rtl8169_private *tp = netdev_priv(dev);
4318         void __iomem *ioaddr = tp->mmio_addr;
4319         struct pci_dev *pdev = tp->pci_dev;
4320         int retval = -ENOMEM;
4321
4322         pm_runtime_get_sync(&pdev->dev);
4323
4324         /*
4325          * Rx and Tx desscriptors needs 256 bytes alignment.
4326          * dma_alloc_coherent provides more.
4327          */
4328         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4329                                              &tp->TxPhyAddr, GFP_KERNEL);
4330         if (!tp->TxDescArray)
4331                 goto err_pm_runtime_put;
4332
4333         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4334                                              &tp->RxPhyAddr, GFP_KERNEL);
4335         if (!tp->RxDescArray)
4336                 goto err_free_tx_0;
4337
4338         retval = rtl8169_init_ring(dev);
4339         if (retval < 0)
4340                 goto err_free_rx_1;
4341
4342         INIT_DELAYED_WORK(&tp->task, NULL);
4343
4344         smp_mb();
4345
4346         rtl_request_firmware(tp);
4347
4348         retval = request_irq(dev->irq, rtl8169_interrupt,
4349                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
4350                              dev->name, dev);
4351         if (retval < 0)
4352                 goto err_release_fw_2;
4353
4354         napi_enable(&tp->napi);
4355
4356         rtl8169_init_phy(dev, tp);
4357
4358         rtl8169_set_features(dev, dev->features);
4359
4360         rtl_pll_power_up(tp);
4361
4362         rtl_hw_start(dev);
4363
4364         tp->saved_wolopts = 0;
4365         pm_runtime_put_noidle(&pdev->dev);
4366
4367         rtl8169_check_link_status(dev, tp, ioaddr);
4368 out:
4369         return retval;
4370
4371 err_release_fw_2:
4372         rtl_release_firmware(tp);
4373         rtl8169_rx_clear(tp);
4374 err_free_rx_1:
4375         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4376                           tp->RxPhyAddr);
4377         tp->RxDescArray = NULL;
4378 err_free_tx_0:
4379         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4380                           tp->TxPhyAddr);
4381         tp->TxDescArray = NULL;
4382 err_pm_runtime_put:
4383         pm_runtime_put_noidle(&pdev->dev);
4384         goto out;
4385 }
4386
4387 static void rtl_rx_close(struct rtl8169_private *tp)
4388 {
4389         void __iomem *ioaddr = tp->mmio_addr;
4390
4391         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4392 }
4393
4394 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4395 {
4396         void __iomem *ioaddr = tp->mmio_addr;
4397
4398         /* Disable interrupts */
4399         rtl8169_irq_mask_and_ack(tp);
4400
4401         rtl_rx_close(tp);
4402
4403         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4404             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4405             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4406                 while (RTL_R8(TxPoll) & NPQ)
4407                         udelay(20);
4408         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4409                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4410                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
4411                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4412                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4413                         udelay(100);
4414         } else {
4415                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4416                 udelay(100);
4417         }
4418
4419         rtl_hw_reset(tp);
4420 }
4421
4422 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4423 {
4424         void __iomem *ioaddr = tp->mmio_addr;
4425
4426         /* Set DMA burst size and Interframe Gap Time */
4427         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4428                 (InterFrameGap << TxInterFrameGapShift));
4429 }
4430
4431 static void rtl_hw_start(struct net_device *dev)
4432 {
4433         struct rtl8169_private *tp = netdev_priv(dev);
4434
4435         tp->hw_start(dev);
4436
4437         netif_start_queue(dev);
4438 }
4439
4440 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4441                                          void __iomem *ioaddr)
4442 {
4443         /*
4444          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4445          * register to be written before TxDescAddrLow to work.
4446          * Switching from MMIO to I/O access fixes the issue as well.
4447          */
4448         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4449         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4450         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4451         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4452 }
4453
4454 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4455 {
4456         u16 cmd;
4457
4458         cmd = RTL_R16(CPlusCmd);
4459         RTL_W16(CPlusCmd, cmd);
4460         return cmd;
4461 }
4462
4463 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4464 {
4465         /* Low hurts. Let's disable the filtering. */
4466         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4467 }
4468
4469 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4470 {
4471         static const struct rtl_cfg2_info {
4472                 u32 mac_version;
4473                 u32 clk;
4474                 u32 val;
4475         } cfg2_info [] = {
4476                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4477                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4478                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4479                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4480         };
4481         const struct rtl_cfg2_info *p = cfg2_info;
4482         unsigned int i;
4483         u32 clk;
4484
4485         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4486         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4487                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4488                         RTL_W32(0x7c, p->val);
4489                         break;
4490                 }
4491         }
4492 }
4493
4494 static void rtl_hw_start_8169(struct net_device *dev)
4495 {
4496         struct rtl8169_private *tp = netdev_priv(dev);
4497         void __iomem *ioaddr = tp->mmio_addr;
4498         struct pci_dev *pdev = tp->pci_dev;
4499
4500         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4501                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4502                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4503         }
4504
4505         RTL_W8(Cfg9346, Cfg9346_Unlock);
4506         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4507             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4508             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4509             tp->mac_version == RTL_GIGA_MAC_VER_04)
4510                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4511
4512         rtl_init_rxcfg(tp);
4513
4514         RTL_W8(EarlyTxThres, NoEarlyTx);
4515
4516         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4517
4518         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4519             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4520             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4521             tp->mac_version == RTL_GIGA_MAC_VER_04)
4522                 rtl_set_rx_tx_config_registers(tp);
4523
4524         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4525
4526         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4527             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4528                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4529                         "Bit-3 and bit-14 MUST be 1\n");
4530                 tp->cp_cmd |= (1 << 14);
4531         }
4532
4533         RTL_W16(CPlusCmd, tp->cp_cmd);
4534
4535         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4536
4537         /*
4538          * Undocumented corner. Supposedly:
4539          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4540          */
4541         RTL_W16(IntrMitigate, 0x0000);
4542
4543         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4544
4545         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4546             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4547             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4548             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4549                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4550                 rtl_set_rx_tx_config_registers(tp);
4551         }
4552
4553         RTL_W8(Cfg9346, Cfg9346_Lock);
4554
4555         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4556         RTL_R8(IntrMask);
4557
4558         RTL_W32(RxMissed, 0);
4559
4560         rtl_set_rx_mode(dev);
4561
4562         /* no early-rx interrupts */
4563         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4564
4565         /* Enable all known interrupts by setting the interrupt mask. */
4566         RTL_W16(IntrMask, tp->intr_event);
4567 }
4568
4569 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4570 {
4571         u32 csi;
4572
4573         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4574         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4575 }
4576
4577 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4578 {
4579         rtl_csi_access_enable(ioaddr, 0x17000000);
4580 }
4581
4582 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4583 {
4584         rtl_csi_access_enable(ioaddr, 0x27000000);
4585 }
4586
4587 struct ephy_info {
4588         unsigned int offset;
4589         u16 mask;
4590         u16 bits;
4591 };
4592
4593 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4594 {
4595         u16 w;
4596
4597         while (len-- > 0) {
4598                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4599                 rtl_ephy_write(ioaddr, e->offset, w);
4600                 e++;
4601         }
4602 }
4603
4604 static void rtl_disable_clock_request(struct pci_dev *pdev)
4605 {
4606         int cap = pci_pcie_cap(pdev);
4607
4608         if (cap) {
4609                 u16 ctl;
4610
4611                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4612                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4613                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4614         }
4615 }
4616
4617 static void rtl_enable_clock_request(struct pci_dev *pdev)
4618 {
4619         int cap = pci_pcie_cap(pdev);
4620
4621         if (cap) {
4622                 u16 ctl;
4623
4624                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4625                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4626                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4627         }
4628 }
4629
4630 #define R8168_CPCMD_QUIRK_MASK (\
4631         EnableBist | \
4632         Mac_dbgo_oe | \
4633         Force_half_dup | \
4634         Force_rxflow_en | \
4635         Force_txflow_en | \
4636         Cxpl_dbg_sel | \
4637         ASF | \
4638         PktCntrDisable | \
4639         Mac_dbgo_sel)
4640
4641 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4642 {
4643         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4644
4645         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4646
4647         rtl_tx_performance_tweak(pdev,
4648                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4649 }
4650
4651 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4652 {
4653         rtl_hw_start_8168bb(ioaddr, pdev);
4654
4655         RTL_W8(MaxTxPacketSize, TxPacketMax);
4656
4657         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4658 }
4659
4660 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4661 {
4662         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4663
4664         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4665
4666         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4667
4668         rtl_disable_clock_request(pdev);
4669
4670         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4671 }
4672
4673 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4674 {
4675         static const struct ephy_info e_info_8168cp[] = {
4676                 { 0x01, 0,      0x0001 },
4677                 { 0x02, 0x0800, 0x1000 },
4678                 { 0x03, 0,      0x0042 },
4679                 { 0x06, 0x0080, 0x0000 },
4680                 { 0x07, 0,      0x2000 }
4681         };
4682
4683         rtl_csi_access_enable_2(ioaddr);
4684
4685         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4686
4687         __rtl_hw_start_8168cp(ioaddr, pdev);
4688 }
4689
4690 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4691 {
4692         rtl_csi_access_enable_2(ioaddr);
4693
4694         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4695
4696         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4697
4698         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4699 }
4700
4701 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4702 {
4703         rtl_csi_access_enable_2(ioaddr);
4704
4705         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4706
4707         /* Magic. */
4708         RTL_W8(DBG_REG, 0x20);
4709
4710         RTL_W8(MaxTxPacketSize, TxPacketMax);
4711
4712         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4713
4714         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4715 }
4716
4717 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4718 {
4719         static const struct ephy_info e_info_8168c_1[] = {
4720                 { 0x02, 0x0800, 0x1000 },
4721                 { 0x03, 0,      0x0002 },
4722                 { 0x06, 0x0080, 0x0000 }
4723         };
4724
4725         rtl_csi_access_enable_2(ioaddr);
4726
4727         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4728
4729         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4730
4731         __rtl_hw_start_8168cp(ioaddr, pdev);
4732 }
4733
4734 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4735 {
4736         static const struct ephy_info e_info_8168c_2[] = {
4737                 { 0x01, 0,      0x0001 },
4738                 { 0x03, 0x0400, 0x0220 }
4739         };
4740
4741         rtl_csi_access_enable_2(ioaddr);
4742
4743         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4744
4745         __rtl_hw_start_8168cp(ioaddr, pdev);
4746 }
4747
4748 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4749 {
4750         rtl_hw_start_8168c_2(ioaddr, pdev);
4751 }
4752
4753 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4754 {
4755         rtl_csi_access_enable_2(ioaddr);
4756
4757         __rtl_hw_start_8168cp(ioaddr, pdev);
4758 }
4759
4760 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4761 {
4762         rtl_csi_access_enable_2(ioaddr);
4763
4764         rtl_disable_clock_request(pdev);
4765
4766         RTL_W8(MaxTxPacketSize, TxPacketMax);
4767
4768         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4769
4770         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4771 }
4772
4773 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4774 {
4775         rtl_csi_access_enable_1(ioaddr);
4776
4777         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4778
4779         RTL_W8(MaxTxPacketSize, TxPacketMax);
4780
4781         rtl_disable_clock_request(pdev);
4782 }
4783
4784 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4785 {
4786         static const struct ephy_info e_info_8168d_4[] = {
4787                 { 0x0b, ~0,     0x48 },
4788                 { 0x19, 0x20,   0x50 },
4789                 { 0x0c, ~0,     0x20 }
4790         };
4791         int i;
4792
4793         rtl_csi_access_enable_1(ioaddr);
4794
4795         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4796
4797         RTL_W8(MaxTxPacketSize, TxPacketMax);
4798
4799         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4800                 const struct ephy_info *e = e_info_8168d_4 + i;
4801                 u16 w;
4802
4803                 w = rtl_ephy_read(ioaddr, e->offset);
4804                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4805         }
4806
4807         rtl_enable_clock_request(pdev);
4808 }
4809
4810 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4811 {
4812         static const struct ephy_info e_info_8168e_1[] = {
4813                 { 0x00, 0x0200, 0x0100 },
4814                 { 0x00, 0x0000, 0x0004 },
4815                 { 0x06, 0x0002, 0x0001 },
4816                 { 0x06, 0x0000, 0x0030 },
4817                 { 0x07, 0x0000, 0x2000 },
4818                 { 0x00, 0x0000, 0x0020 },
4819                 { 0x03, 0x5800, 0x2000 },
4820                 { 0x03, 0x0000, 0x0001 },
4821                 { 0x01, 0x0800, 0x1000 },
4822                 { 0x07, 0x0000, 0x4000 },
4823                 { 0x1e, 0x0000, 0x2000 },
4824                 { 0x19, 0xffff, 0xfe6c },
4825                 { 0x0a, 0x0000, 0x0040 }
4826         };
4827
4828         rtl_csi_access_enable_2(ioaddr);
4829
4830         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4831
4832         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4833
4834         RTL_W8(MaxTxPacketSize, TxPacketMax);
4835
4836         rtl_disable_clock_request(pdev);
4837
4838         /* Reset tx FIFO pointer */
4839         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4840         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4841
4842         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4843 }
4844
4845 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4846 {
4847         static const struct ephy_info e_info_8168e_2[] = {
4848                 { 0x09, 0x0000, 0x0080 },
4849                 { 0x19, 0x0000, 0x0224 }
4850         };
4851
4852         rtl_csi_access_enable_1(ioaddr);
4853
4854         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4855
4856         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4857
4858         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4859         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4860         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4861         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4862         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4863         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4864         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4865         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4866                      ERIAR_EXGMAC);
4867
4868         RTL_W8(MaxTxPacketSize, EarlySize);
4869
4870         rtl_disable_clock_request(pdev);
4871
4872         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4873         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4874
4875         /* Adjust EEE LED frequency */
4876         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4877
4878         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4879         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4880         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4881 }
4882
4883 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4884 {
4885         static const struct ephy_info e_info_8168f_1[] = {
4886                 { 0x06, 0x00c0, 0x0020 },
4887                 { 0x08, 0x0001, 0x0002 },
4888                 { 0x09, 0x0000, 0x0080 },
4889                 { 0x19, 0x0000, 0x0224 }
4890         };
4891
4892         rtl_csi_access_enable_1(ioaddr);
4893
4894         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4895
4896         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4897
4898         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4899         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4900         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4901         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4902         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4903         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4904         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4905         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4906         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4907         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4908         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4909                      ERIAR_EXGMAC);
4910
4911         RTL_W8(MaxTxPacketSize, EarlySize);
4912
4913         rtl_disable_clock_request(pdev);
4914
4915         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4916         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4917
4918         /* Adjust EEE LED frequency */
4919         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4920
4921         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4922         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4923         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4924 }
4925
4926 static void rtl_hw_start_8168(struct net_device *dev)
4927 {
4928         struct rtl8169_private *tp = netdev_priv(dev);
4929         void __iomem *ioaddr = tp->mmio_addr;
4930         struct pci_dev *pdev = tp->pci_dev;
4931
4932         RTL_W8(Cfg9346, Cfg9346_Unlock);
4933
4934         RTL_W8(MaxTxPacketSize, TxPacketMax);
4935
4936         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4937
4938         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4939
4940         RTL_W16(CPlusCmd, tp->cp_cmd);
4941
4942         RTL_W16(IntrMitigate, 0x5151);
4943
4944         /* Work around for RxFIFO overflow. */
4945         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4946                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4947                 tp->intr_event &= ~RxOverflow;
4948         }
4949
4950         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4951
4952         rtl_set_rx_mode(dev);
4953
4954         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4955                 (InterFrameGap << TxInterFrameGapShift));
4956
4957         RTL_R8(IntrMask);
4958
4959         switch (tp->mac_version) {
4960         case RTL_GIGA_MAC_VER_11:
4961                 rtl_hw_start_8168bb(ioaddr, pdev);
4962                 break;
4963
4964         case RTL_GIGA_MAC_VER_12:
4965         case RTL_GIGA_MAC_VER_17:
4966                 rtl_hw_start_8168bef(ioaddr, pdev);
4967                 break;
4968
4969         case RTL_GIGA_MAC_VER_18:
4970                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4971                 break;
4972
4973         case RTL_GIGA_MAC_VER_19:
4974                 rtl_hw_start_8168c_1(ioaddr, pdev);
4975                 break;
4976
4977         case RTL_GIGA_MAC_VER_20:
4978                 rtl_hw_start_8168c_2(ioaddr, pdev);
4979                 break;
4980
4981         case RTL_GIGA_MAC_VER_21:
4982                 rtl_hw_start_8168c_3(ioaddr, pdev);
4983                 break;
4984
4985         case RTL_GIGA_MAC_VER_22:
4986                 rtl_hw_start_8168c_4(ioaddr, pdev);
4987                 break;
4988
4989         case RTL_GIGA_MAC_VER_23:
4990                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4991                 break;
4992
4993         case RTL_GIGA_MAC_VER_24:
4994                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4995                 break;
4996
4997         case RTL_GIGA_MAC_VER_25:
4998         case RTL_GIGA_MAC_VER_26:
4999         case RTL_GIGA_MAC_VER_27:
5000                 rtl_hw_start_8168d(ioaddr, pdev);
5001                 break;
5002
5003         case RTL_GIGA_MAC_VER_28:
5004                 rtl_hw_start_8168d_4(ioaddr, pdev);
5005                 break;
5006
5007         case RTL_GIGA_MAC_VER_31:
5008                 rtl_hw_start_8168dp(ioaddr, pdev);
5009                 break;
5010
5011         case RTL_GIGA_MAC_VER_32:
5012         case RTL_GIGA_MAC_VER_33:
5013                 rtl_hw_start_8168e_1(ioaddr, pdev);
5014                 break;
5015         case RTL_GIGA_MAC_VER_34:
5016                 rtl_hw_start_8168e_2(ioaddr, pdev);
5017                 break;
5018
5019         case RTL_GIGA_MAC_VER_35:
5020         case RTL_GIGA_MAC_VER_36:
5021                 rtl_hw_start_8168f_1(ioaddr, pdev);
5022                 break;
5023
5024         default:
5025                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5026                         dev->name, tp->mac_version);
5027                 break;
5028         }
5029
5030         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5031
5032         RTL_W8(Cfg9346, Cfg9346_Lock);
5033
5034         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5035
5036         RTL_W16(IntrMask, tp->intr_event);
5037 }
5038
5039 #define R810X_CPCMD_QUIRK_MASK (\
5040         EnableBist | \
5041         Mac_dbgo_oe | \
5042         Force_half_dup | \
5043         Force_rxflow_en | \
5044         Force_txflow_en | \
5045         Cxpl_dbg_sel | \
5046         ASF | \
5047         PktCntrDisable | \
5048         Mac_dbgo_sel)
5049
5050 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5051 {
5052         static const struct ephy_info e_info_8102e_1[] = {
5053                 { 0x01, 0, 0x6e65 },
5054                 { 0x02, 0, 0x091f },
5055                 { 0x03, 0, 0xc2f9 },
5056                 { 0x06, 0, 0xafb5 },
5057                 { 0x07, 0, 0x0e00 },
5058                 { 0x19, 0, 0xec80 },
5059                 { 0x01, 0, 0x2e65 },
5060                 { 0x01, 0, 0x6e65 }
5061         };
5062         u8 cfg1;
5063
5064         rtl_csi_access_enable_2(ioaddr);
5065
5066         RTL_W8(DBG_REG, FIX_NAK_1);
5067
5068         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5069
5070         RTL_W8(Config1,
5071                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5072         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5073
5074         cfg1 = RTL_R8(Config1);
5075         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5076                 RTL_W8(Config1, cfg1 & ~LEDS0);
5077
5078         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5079 }
5080
5081 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5082 {
5083         rtl_csi_access_enable_2(ioaddr);
5084
5085         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5086
5087         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5088         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5089 }
5090
5091 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
5092 {
5093         rtl_hw_start_8102e_2(ioaddr, pdev);
5094
5095         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
5096 }
5097
5098 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5099 {
5100         static const struct ephy_info e_info_8105e_1[] = {
5101                 { 0x07, 0, 0x4000 },
5102                 { 0x19, 0, 0x0200 },
5103                 { 0x19, 0, 0x0020 },
5104                 { 0x1e, 0, 0x2000 },
5105                 { 0x03, 0, 0x0001 },
5106                 { 0x19, 0, 0x0100 },
5107                 { 0x19, 0, 0x0004 },
5108                 { 0x0a, 0, 0x0020 }
5109         };
5110
5111         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5112         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5113
5114         /* Disable Early Tally Counter */
5115         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5116
5117         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5118         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5119
5120         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5121 }
5122
5123 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5124 {
5125         rtl_hw_start_8105e_1(ioaddr, pdev);
5126         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5127 }
5128
5129 static void rtl_hw_start_8101(struct net_device *dev)
5130 {
5131         struct rtl8169_private *tp = netdev_priv(dev);
5132         void __iomem *ioaddr = tp->mmio_addr;
5133         struct pci_dev *pdev = tp->pci_dev;
5134
5135         if (tp->mac_version >= RTL_GIGA_MAC_VER_30) {
5136                 tp->intr_event &= ~RxFIFOOver;
5137                 tp->napi_event &= ~RxFIFOOver;
5138         }
5139
5140         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5141             tp->mac_version == RTL_GIGA_MAC_VER_16) {
5142                 int cap = pci_pcie_cap(pdev);
5143
5144                 if (cap) {
5145                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5146                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
5147                 }
5148         }
5149
5150         RTL_W8(Cfg9346, Cfg9346_Unlock);
5151
5152         switch (tp->mac_version) {
5153         case RTL_GIGA_MAC_VER_07:
5154                 rtl_hw_start_8102e_1(ioaddr, pdev);
5155                 break;
5156
5157         case RTL_GIGA_MAC_VER_08:
5158                 rtl_hw_start_8102e_3(ioaddr, pdev);
5159                 break;
5160
5161         case RTL_GIGA_MAC_VER_09:
5162                 rtl_hw_start_8102e_2(ioaddr, pdev);
5163                 break;
5164
5165         case RTL_GIGA_MAC_VER_29:
5166                 rtl_hw_start_8105e_1(ioaddr, pdev);
5167                 break;
5168         case RTL_GIGA_MAC_VER_30:
5169                 rtl_hw_start_8105e_2(ioaddr, pdev);
5170                 break;
5171         }
5172
5173         RTL_W8(Cfg9346, Cfg9346_Lock);
5174
5175         RTL_W8(MaxTxPacketSize, TxPacketMax);
5176
5177         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5178
5179         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5180         RTL_W16(CPlusCmd, tp->cp_cmd);
5181
5182         RTL_W16(IntrMitigate, 0x0000);
5183
5184         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5185
5186         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5187         rtl_set_rx_tx_config_registers(tp);
5188
5189         RTL_R8(IntrMask);
5190
5191         rtl_set_rx_mode(dev);
5192
5193         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5194
5195         RTL_W16(IntrMask, tp->intr_event);
5196 }
5197
5198 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5199 {
5200         struct rtl8169_private *tp = netdev_priv(dev);
5201
5202         if (new_mtu < ETH_ZLEN ||
5203             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5204                 return -EINVAL;
5205
5206         if (new_mtu > ETH_DATA_LEN)
5207                 rtl_hw_jumbo_enable(tp);
5208         else
5209                 rtl_hw_jumbo_disable(tp);
5210
5211         dev->mtu = new_mtu;
5212         netdev_update_features(dev);
5213
5214         return 0;
5215 }
5216
5217 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5218 {
5219         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5220         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5221 }
5222
5223 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5224                                      void **data_buff, struct RxDesc *desc)
5225 {
5226         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5227                          DMA_FROM_DEVICE);
5228
5229         kfree(*data_buff);
5230         *data_buff = NULL;
5231         rtl8169_make_unusable_by_asic(desc);
5232 }
5233
5234 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5235 {
5236         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5237
5238         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5239 }
5240
5241 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5242                                        u32 rx_buf_sz)
5243 {
5244         desc->addr = cpu_to_le64(mapping);
5245         wmb();
5246         rtl8169_mark_to_asic(desc, rx_buf_sz);
5247 }
5248
5249 static inline void *rtl8169_align(void *data)
5250 {
5251         return (void *)ALIGN((long)data, 16);
5252 }
5253
5254 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5255                                              struct RxDesc *desc)
5256 {
5257         void *data;
5258         dma_addr_t mapping;
5259         struct device *d = &tp->pci_dev->dev;
5260         struct net_device *dev = tp->dev;
5261         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5262
5263         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5264         if (!data)
5265                 return NULL;
5266
5267         if (rtl8169_align(data) != data) {
5268                 kfree(data);
5269                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5270                 if (!data)
5271                         return NULL;
5272         }
5273
5274         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5275                                  DMA_FROM_DEVICE);
5276         if (unlikely(dma_mapping_error(d, mapping))) {
5277                 if (net_ratelimit())
5278                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5279                 goto err_out;
5280         }
5281
5282         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5283         return data;
5284
5285 err_out:
5286         kfree(data);
5287         return NULL;
5288 }
5289
5290 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5291 {
5292         unsigned int i;
5293
5294         for (i = 0; i < NUM_RX_DESC; i++) {
5295                 if (tp->Rx_databuff[i]) {
5296                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5297                                             tp->RxDescArray + i);
5298                 }
5299         }
5300 }
5301
5302 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5303 {
5304         desc->opts1 |= cpu_to_le32(RingEnd);
5305 }
5306
5307 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5308 {
5309         unsigned int i;
5310
5311         for (i = 0; i < NUM_RX_DESC; i++) {
5312                 void *data;
5313
5314                 if (tp->Rx_databuff[i])
5315                         continue;
5316
5317                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5318                 if (!data) {
5319                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5320                         goto err_out;
5321                 }
5322                 tp->Rx_databuff[i] = data;
5323         }
5324
5325         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5326         return 0;
5327
5328 err_out:
5329         rtl8169_rx_clear(tp);
5330         return -ENOMEM;
5331 }
5332
5333 static int rtl8169_init_ring(struct net_device *dev)
5334 {
5335         struct rtl8169_private *tp = netdev_priv(dev);
5336
5337         rtl8169_init_ring_indexes(tp);
5338
5339         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5340         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5341
5342         return rtl8169_rx_fill(tp);
5343 }
5344
5345 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5346                                  struct TxDesc *desc)
5347 {
5348         unsigned int len = tx_skb->len;
5349
5350         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5351
5352         desc->opts1 = 0x00;
5353         desc->opts2 = 0x00;
5354         desc->addr = 0x00;
5355         tx_skb->len = 0;
5356 }
5357
5358 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5359                                    unsigned int n)
5360 {
5361         unsigned int i;
5362
5363         for (i = 0; i < n; i++) {
5364                 unsigned int entry = (start + i) % NUM_TX_DESC;
5365                 struct ring_info *tx_skb = tp->tx_skb + entry;
5366                 unsigned int len = tx_skb->len;
5367
5368                 if (len) {
5369                         struct sk_buff *skb = tx_skb->skb;
5370
5371                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5372                                              tp->TxDescArray + entry);
5373                         if (skb) {
5374                                 tp->dev->stats.tx_dropped++;
5375                                 dev_kfree_skb(skb);
5376                                 tx_skb->skb = NULL;
5377                         }
5378                 }
5379         }
5380 }
5381
5382 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5383 {
5384         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5385         tp->cur_tx = tp->dirty_tx = 0;
5386 }
5387
5388 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
5389 {
5390         struct rtl8169_private *tp = netdev_priv(dev);
5391
5392         PREPARE_DELAYED_WORK(&tp->task, task);
5393         schedule_delayed_work(&tp->task, 4);
5394 }
5395
5396 static void rtl8169_wait_for_quiescence(struct net_device *dev)
5397 {
5398         struct rtl8169_private *tp = netdev_priv(dev);
5399         void __iomem *ioaddr = tp->mmio_addr;
5400
5401         synchronize_irq(dev->irq);
5402
5403         /* Wait for any pending NAPI task to complete */
5404         napi_disable(&tp->napi);
5405
5406         rtl8169_irq_mask_and_ack(tp);
5407
5408         tp->intr_mask = 0xffff;
5409         RTL_W16(IntrMask, tp->intr_event);
5410         napi_enable(&tp->napi);
5411 }
5412
5413 static void rtl8169_reinit_task(struct work_struct *work)
5414 {
5415         struct rtl8169_private *tp =
5416                 container_of(work, struct rtl8169_private, task.work);
5417         struct net_device *dev = tp->dev;
5418         int ret;
5419
5420         rtnl_lock();
5421
5422         if (!netif_running(dev))
5423                 goto out_unlock;
5424
5425         rtl8169_wait_for_quiescence(dev);
5426         rtl8169_close(dev);
5427
5428         ret = rtl8169_open(dev);
5429         if (unlikely(ret < 0)) {
5430                 if (net_ratelimit())
5431                         netif_err(tp, drv, dev,
5432                                   "reinit failure (status = %d). Rescheduling\n",
5433                                   ret);
5434                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
5435         }
5436
5437 out_unlock:
5438         rtnl_unlock();
5439 }
5440
5441 static void rtl8169_reset_task(struct work_struct *work)
5442 {
5443         struct rtl8169_private *tp =
5444                 container_of(work, struct rtl8169_private, task.work);
5445         struct net_device *dev = tp->dev;
5446         int i;
5447
5448         rtnl_lock();
5449
5450         if (!netif_running(dev))
5451                 goto out_unlock;
5452
5453         rtl8169_hw_reset(tp);
5454
5455         rtl8169_wait_for_quiescence(dev);
5456
5457         for (i = 0; i < NUM_RX_DESC; i++)
5458                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5459
5460         rtl8169_tx_clear(tp);
5461         rtl8169_init_ring_indexes(tp);
5462
5463         rtl_hw_start(dev);
5464         netif_wake_queue(dev);
5465         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5466
5467 out_unlock:
5468         rtnl_unlock();
5469 }
5470
5471 static void rtl8169_tx_timeout(struct net_device *dev)
5472 {
5473         rtl8169_schedule_work(dev, rtl8169_reset_task);
5474 }
5475
5476 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5477                               u32 *opts)
5478 {
5479         struct skb_shared_info *info = skb_shinfo(skb);
5480         unsigned int cur_frag, entry;
5481         struct TxDesc * uninitialized_var(txd);
5482         struct device *d = &tp->pci_dev->dev;
5483
5484         entry = tp->cur_tx;
5485         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5486                 const skb_frag_t *frag = info->frags + cur_frag;
5487                 dma_addr_t mapping;
5488                 u32 status, len;
5489                 void *addr;
5490
5491                 entry = (entry + 1) % NUM_TX_DESC;
5492
5493                 txd = tp->TxDescArray + entry;
5494                 len = skb_frag_size(frag);
5495                 addr = skb_frag_address(frag);
5496                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5497                 if (unlikely(dma_mapping_error(d, mapping))) {
5498                         if (net_ratelimit())
5499                                 netif_err(tp, drv, tp->dev,
5500                                           "Failed to map TX fragments DMA!\n");
5501                         goto err_out;
5502                 }
5503
5504                 /* Anti gcc 2.95.3 bugware (sic) */
5505                 status = opts[0] | len |
5506                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5507
5508                 txd->opts1 = cpu_to_le32(status);
5509                 txd->opts2 = cpu_to_le32(opts[1]);
5510                 txd->addr = cpu_to_le64(mapping);
5511
5512                 tp->tx_skb[entry].len = len;
5513         }
5514
5515         if (cur_frag) {
5516                 tp->tx_skb[entry].skb = skb;
5517                 txd->opts1 |= cpu_to_le32(LastFrag);
5518         }
5519
5520         return cur_frag;
5521
5522 err_out:
5523         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5524         return -EIO;
5525 }
5526
5527 static bool rtl_skb_pad(struct sk_buff *skb)
5528 {
5529         if (skb_padto(skb, ETH_ZLEN))
5530                 return false;
5531         skb_put(skb, ETH_ZLEN - skb->len);
5532         return true;
5533 }
5534
5535 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5536 {
5537         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5538 }
5539
5540 static inline bool rtl8169_tso_csum(struct rtl8169_private *tp,
5541                                     struct sk_buff *skb, u32 *opts)
5542 {
5543         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5544         u32 mss = skb_shinfo(skb)->gso_size;
5545         int offset = info->opts_offset;
5546
5547         if (mss) {
5548                 opts[0] |= TD_LSO;
5549                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5550         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5551                 const struct iphdr *ip = ip_hdr(skb);
5552
5553                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5554                         return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
5555
5556                 if (ip->protocol == IPPROTO_TCP)
5557                         opts[offset] |= info->checksum.tcp;
5558                 else if (ip->protocol == IPPROTO_UDP)
5559                         opts[offset] |= info->checksum.udp;
5560                 else
5561                         WARN_ON_ONCE(1);
5562         } else {
5563                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5564                         return rtl_skb_pad(skb);
5565         }
5566         return true;
5567 }
5568
5569 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5570                                       struct net_device *dev)
5571 {
5572         struct rtl8169_private *tp = netdev_priv(dev);
5573         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5574         struct TxDesc *txd = tp->TxDescArray + entry;
5575         void __iomem *ioaddr = tp->mmio_addr;
5576         struct device *d = &tp->pci_dev->dev;
5577         dma_addr_t mapping;
5578         u32 status, len;
5579         u32 opts[2];
5580         int frags;
5581
5582         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5583                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5584                 goto err_stop_0;
5585         }
5586
5587         /* 8168evl does not automatically pad to minimum length. */
5588         if (unlikely(tp->mac_version == RTL_GIGA_MAC_VER_34 &&
5589                      skb->len < ETH_ZLEN)) {
5590                 if (skb_padto(skb, ETH_ZLEN))
5591                         goto err_update_stats;
5592                 skb_put(skb, ETH_ZLEN - skb->len);
5593         }
5594
5595         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5596                 goto err_stop_0;
5597
5598         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5599         opts[0] = DescOwn;
5600
5601         if (!rtl8169_tso_csum(tp, skb, opts))
5602                 goto err_update_stats;
5603
5604         len = skb_headlen(skb);
5605         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5606         if (unlikely(dma_mapping_error(d, mapping))) {
5607                 if (net_ratelimit())
5608                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5609                 goto err_dma_0;
5610         }
5611
5612         tp->tx_skb[entry].len = len;
5613         txd->addr = cpu_to_le64(mapping);
5614
5615         frags = rtl8169_xmit_frags(tp, skb, opts);
5616         if (frags < 0)
5617                 goto err_dma_1;
5618         else if (frags)
5619                 opts[0] |= FirstFrag;
5620         else {
5621                 opts[0] |= FirstFrag | LastFrag;
5622                 tp->tx_skb[entry].skb = skb;
5623         }
5624
5625         txd->opts2 = cpu_to_le32(opts[1]);
5626
5627         wmb();
5628
5629         /* Anti gcc 2.95.3 bugware (sic) */
5630         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5631         txd->opts1 = cpu_to_le32(status);
5632
5633         tp->cur_tx += frags + 1;
5634
5635         wmb();
5636
5637         RTL_W8(TxPoll, NPQ);
5638
5639         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5640                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5641                  * not miss a ring update when it notices a stopped queue.
5642                  */
5643                 smp_wmb();
5644                 netif_stop_queue(dev);
5645                 /* Sync with rtl_tx:
5646                  * - publish queue status and cur_tx ring index (write barrier)
5647                  * - refresh dirty_tx ring index (read barrier).
5648                  * May the current thread have a pessimistic view of the ring
5649                  * status and forget to wake up queue, a racing rtl_tx thread
5650                  * can't.
5651                  */
5652                 smp_mb();
5653                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5654                         netif_wake_queue(dev);
5655         }
5656
5657         return NETDEV_TX_OK;
5658
5659 err_dma_1:
5660         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5661 err_dma_0:
5662         dev_kfree_skb(skb);
5663 err_update_stats:
5664         dev->stats.tx_dropped++;
5665         return NETDEV_TX_OK;
5666
5667 err_stop_0:
5668         netif_stop_queue(dev);
5669         dev->stats.tx_dropped++;
5670         return NETDEV_TX_BUSY;
5671 }
5672
5673 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5674 {
5675         struct rtl8169_private *tp = netdev_priv(dev);
5676         struct pci_dev *pdev = tp->pci_dev;
5677         u16 pci_status, pci_cmd;
5678
5679         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5680         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5681
5682         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5683                   pci_cmd, pci_status);
5684
5685         /*
5686          * The recovery sequence below admits a very elaborated explanation:
5687          * - it seems to work;
5688          * - I did not see what else could be done;
5689          * - it makes iop3xx happy.
5690          *
5691          * Feel free to adjust to your needs.
5692          */
5693         if (pdev->broken_parity_status)
5694                 pci_cmd &= ~PCI_COMMAND_PARITY;
5695         else
5696                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5697
5698         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5699
5700         pci_write_config_word(pdev, PCI_STATUS,
5701                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5702                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5703                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5704
5705         /* The infamous DAC f*ckup only happens at boot time */
5706         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5707                 void __iomem *ioaddr = tp->mmio_addr;
5708
5709                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5710                 tp->cp_cmd &= ~PCIDAC;
5711                 RTL_W16(CPlusCmd, tp->cp_cmd);
5712                 dev->features &= ~NETIF_F_HIGHDMA;
5713         }
5714
5715         rtl8169_hw_reset(tp);
5716
5717         rtl8169_schedule_work(dev, rtl8169_reinit_task);
5718 }
5719
5720 static void rtl8169_tx_interrupt(struct net_device *dev,
5721                                  struct rtl8169_private *tp,
5722                                  void __iomem *ioaddr)
5723 {
5724         unsigned int dirty_tx, tx_left;
5725
5726         dirty_tx = tp->dirty_tx;
5727         smp_rmb();
5728         tx_left = tp->cur_tx - dirty_tx;
5729
5730         while (tx_left > 0) {
5731                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5732                 struct ring_info *tx_skb = tp->tx_skb + entry;
5733                 u32 status;
5734
5735                 rmb();
5736                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5737                 if (status & DescOwn)
5738                         break;
5739
5740                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5741                                      tp->TxDescArray + entry);
5742                 if (status & LastFrag) {
5743                         dev->stats.tx_packets++;
5744                         dev->stats.tx_bytes += tx_skb->skb->len;
5745                         dev_kfree_skb(tx_skb->skb);
5746                         tx_skb->skb = NULL;
5747                 }
5748                 dirty_tx++;
5749                 tx_left--;
5750         }
5751
5752         if (tp->dirty_tx != dirty_tx) {
5753                 tp->dirty_tx = dirty_tx;
5754                 /* Sync with rtl8169_start_xmit:
5755                  * - publish dirty_tx ring index (write barrier)
5756                  * - refresh cur_tx ring index and queue status (read barrier)
5757                  * May the current thread miss the stopped queue condition,
5758                  * a racing xmit thread can only have a right view of the
5759                  * ring status.
5760                  */
5761                 smp_mb();
5762                 if (netif_queue_stopped(dev) &&
5763                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5764                         netif_wake_queue(dev);
5765                 }
5766                 /*
5767                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5768                  * too close. Let's kick an extra TxPoll request when a burst
5769                  * of start_xmit activity is detected (if it is not detected,
5770                  * it is slow enough). -- FR
5771                  */
5772                 if (tp->cur_tx != dirty_tx)
5773                         RTL_W8(TxPoll, NPQ);
5774         }
5775 }
5776
5777 static inline int rtl8169_fragmented_frame(u32 status)
5778 {
5779         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5780 }
5781
5782 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5783 {
5784         u32 status = opts1 & RxProtoMask;
5785
5786         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5787             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5788                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5789         else
5790                 skb_checksum_none_assert(skb);
5791 }
5792
5793 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5794                                            struct rtl8169_private *tp,
5795                                            int pkt_size,
5796                                            dma_addr_t addr)
5797 {
5798         struct sk_buff *skb;
5799         struct device *d = &tp->pci_dev->dev;
5800
5801         data = rtl8169_align(data);
5802         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5803         prefetch(data);
5804         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5805         if (skb)
5806                 memcpy(skb->data, data, pkt_size);
5807         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5808
5809         return skb;
5810 }
5811
5812 static int rtl8169_rx_interrupt(struct net_device *dev,
5813                                 struct rtl8169_private *tp,
5814                                 void __iomem *ioaddr, u32 budget)
5815 {
5816         unsigned int cur_rx, rx_left;
5817         unsigned int count;
5818
5819         cur_rx = tp->cur_rx;
5820         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5821         rx_left = min(rx_left, budget);
5822
5823         for (; rx_left > 0; rx_left--, cur_rx++) {
5824                 unsigned int entry = cur_rx % NUM_RX_DESC;
5825                 struct RxDesc *desc = tp->RxDescArray + entry;
5826                 u32 status;
5827
5828                 rmb();
5829                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5830
5831                 if (status & DescOwn)
5832                         break;
5833                 if (unlikely(status & RxRES)) {
5834                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5835                                    status);
5836                         dev->stats.rx_errors++;
5837                         if (status & (RxRWT | RxRUNT))
5838                                 dev->stats.rx_length_errors++;
5839                         if (status & RxCRC)
5840                                 dev->stats.rx_crc_errors++;
5841                         if (status & RxFOVF) {
5842                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5843                                 dev->stats.rx_fifo_errors++;
5844                         }
5845                 } else {
5846                         struct sk_buff *skb;
5847                         dma_addr_t addr = le64_to_cpu(desc->addr);
5848                         int pkt_size = (status & 0x00003fff) - 4;
5849
5850                         /*
5851                          * The driver does not support incoming fragmented
5852                          * frames. They are seen as a symptom of over-mtu
5853                          * sized frames.
5854                          */
5855                         if (unlikely(rtl8169_fragmented_frame(status))) {
5856                                 dev->stats.rx_dropped++;
5857                                 dev->stats.rx_length_errors++;
5858                                 goto release_descriptor;
5859                         }
5860
5861                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5862                                                   tp, pkt_size, addr);
5863                         if (!skb) {
5864                                 dev->stats.rx_dropped++;
5865                                 goto release_descriptor;
5866                         }
5867
5868                         rtl8169_rx_csum(skb, status);
5869                         skb_put(skb, pkt_size);
5870                         skb->protocol = eth_type_trans(skb, dev);
5871
5872                         rtl8169_rx_vlan_tag(desc, skb);
5873
5874                         napi_gro_receive(&tp->napi, skb);
5875
5876                         dev->stats.rx_bytes += pkt_size;
5877                         dev->stats.rx_packets++;
5878                 }
5879 release_descriptor:
5880                 desc->opts2 = 0;
5881                 wmb();
5882                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5883         }
5884
5885         count = cur_rx - tp->cur_rx;
5886         tp->cur_rx = cur_rx;
5887
5888         tp->dirty_rx += count;
5889
5890         return count;
5891 }
5892
5893 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5894 {
5895         struct net_device *dev = dev_instance;
5896         struct rtl8169_private *tp = netdev_priv(dev);
5897         void __iomem *ioaddr = tp->mmio_addr;
5898         int handled = 0;
5899         int status;
5900
5901         /* loop handling interrupts until we have no new ones or
5902          * we hit a invalid/hotplug case.
5903          */
5904         status = RTL_R16(IntrStatus);
5905         while (status && status != 0xffff) {
5906                 status &= tp->intr_event;
5907                 if (!status)
5908                         break;
5909
5910                 handled = 1;
5911
5912                 /* Handle all of the error cases first. These will reset
5913                  * the chip, so just exit the loop.
5914                  */
5915                 if (unlikely(!netif_running(dev))) {
5916                         rtl8169_hw_reset(tp);
5917                         break;
5918                 }
5919
5920                 if (unlikely(status & RxFIFOOver)) {
5921                         switch (tp->mac_version) {
5922                         /* Work around for rx fifo overflow */
5923                         case RTL_GIGA_MAC_VER_11:
5924                                 netif_stop_queue(dev);
5925                                 rtl8169_tx_timeout(dev);
5926                                 goto done;
5927                         default:
5928                                 break;
5929                         }
5930                 }
5931
5932                 if (unlikely(status & SYSErr)) {
5933                         rtl8169_pcierr_interrupt(dev);
5934                         break;
5935                 }
5936
5937                 if (status & LinkChg)
5938                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5939
5940                 /* We need to see the lastest version of tp->intr_mask to
5941                  * avoid ignoring an MSI interrupt and having to wait for
5942                  * another event which may never come.
5943                  */
5944                 smp_rmb();
5945                 if (status & tp->intr_mask & tp->napi_event) {
5946                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5947                         tp->intr_mask = ~tp->napi_event;
5948
5949                         if (likely(napi_schedule_prep(&tp->napi)))
5950                                 __napi_schedule(&tp->napi);
5951                         else
5952                                 netif_info(tp, intr, dev,
5953                                            "interrupt %04x in poll\n", status);
5954                 }
5955
5956                 /* We only get a new MSI interrupt when all active irq
5957                  * sources on the chip have been acknowledged. So, ack
5958                  * everything we've seen and check if new sources have become
5959                  * active to avoid blocking all interrupts from the chip.
5960                  */
5961                 RTL_W16(IntrStatus,
5962                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5963                 status = RTL_R16(IntrStatus);
5964         }
5965 done:
5966         return IRQ_RETVAL(handled);
5967 }
5968
5969 static int rtl8169_poll(struct napi_struct *napi, int budget)
5970 {
5971         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5972         struct net_device *dev = tp->dev;
5973         void __iomem *ioaddr = tp->mmio_addr;
5974         int work_done;
5975
5976         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5977         rtl8169_tx_interrupt(dev, tp, ioaddr);
5978
5979         if (work_done < budget) {
5980                 napi_complete(napi);
5981
5982                 /* We need for force the visibility of tp->intr_mask
5983                  * for other CPUs, as we can loose an MSI interrupt
5984                  * and potentially wait for a retransmit timeout if we don't.
5985                  * The posted write to IntrMask is safe, as it will
5986                  * eventually make it to the chip and we won't loose anything
5987                  * until it does.
5988                  */
5989                 tp->intr_mask = 0xffff;
5990                 wmb();
5991                 RTL_W16(IntrMask, tp->intr_event);
5992         }
5993
5994         return work_done;
5995 }
5996
5997 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5998 {
5999         struct rtl8169_private *tp = netdev_priv(dev);
6000
6001         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6002                 return;
6003
6004         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6005         RTL_W32(RxMissed, 0);
6006 }
6007
6008 static void rtl8169_down(struct net_device *dev)
6009 {
6010         struct rtl8169_private *tp = netdev_priv(dev);
6011         void __iomem *ioaddr = tp->mmio_addr;
6012
6013         del_timer_sync(&tp->timer);
6014
6015         netif_stop_queue(dev);
6016
6017         napi_disable(&tp->napi);
6018
6019         spin_lock_irq(&tp->lock);
6020
6021         rtl8169_hw_reset(tp);
6022         /*
6023          * At this point device interrupts can not be enabled in any function,
6024          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
6025          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
6026          */
6027         rtl8169_rx_missed(dev, ioaddr);
6028
6029         spin_unlock_irq(&tp->lock);
6030
6031         synchronize_irq(dev->irq);
6032
6033         /* Give a racing hard_start_xmit a few cycles to complete. */
6034         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
6035
6036         rtl8169_tx_clear(tp);
6037
6038         rtl8169_rx_clear(tp);
6039
6040         rtl_pll_power_down(tp);
6041 }
6042
6043 static int rtl8169_close(struct net_device *dev)
6044 {
6045         struct rtl8169_private *tp = netdev_priv(dev);
6046         struct pci_dev *pdev = tp->pci_dev;
6047
6048         pm_runtime_get_sync(&pdev->dev);
6049
6050         /* Update counters before going down */
6051         rtl8169_update_counters(dev);
6052
6053         rtl8169_down(dev);
6054
6055         free_irq(dev->irq, dev);
6056
6057         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6058                           tp->RxPhyAddr);
6059         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6060                           tp->TxPhyAddr);
6061         tp->TxDescArray = NULL;
6062         tp->RxDescArray = NULL;
6063
6064         pm_runtime_put_sync(&pdev->dev);
6065
6066         return 0;
6067 }
6068
6069 static void rtl_set_rx_mode(struct net_device *dev)
6070 {
6071         struct rtl8169_private *tp = netdev_priv(dev);
6072         void __iomem *ioaddr = tp->mmio_addr;
6073         unsigned long flags;
6074         u32 mc_filter[2];       /* Multicast hash filter */
6075         int rx_mode;
6076         u32 tmp = 0;
6077
6078         if (dev->flags & IFF_PROMISC) {
6079                 /* Unconditionally log net taps. */
6080                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
6081                 rx_mode =
6082                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
6083                     AcceptAllPhys;
6084                 mc_filter[1] = mc_filter[0] = 0xffffffff;
6085         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
6086                    (dev->flags & IFF_ALLMULTI)) {
6087                 /* Too many to filter perfectly -- accept all multicasts. */
6088                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
6089                 mc_filter[1] = mc_filter[0] = 0xffffffff;
6090         } else {
6091                 struct netdev_hw_addr *ha;
6092
6093                 rx_mode = AcceptBroadcast | AcceptMyPhys;
6094                 mc_filter[1] = mc_filter[0] = 0;
6095                 netdev_for_each_mc_addr(ha, dev) {
6096                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
6097                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
6098                         rx_mode |= AcceptMulticast;
6099                 }
6100         }
6101
6102         spin_lock_irqsave(&tp->lock, flags);
6103
6104         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
6105
6106         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
6107                 u32 data = mc_filter[0];
6108
6109                 mc_filter[0] = swab32(mc_filter[1]);
6110                 mc_filter[1] = swab32(data);
6111         }
6112
6113         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
6114                 mc_filter[1] = mc_filter[0] = 0xffffffff;
6115
6116         RTL_W32(MAR0 + 4, mc_filter[1]);
6117         RTL_W32(MAR0 + 0, mc_filter[0]);
6118
6119         RTL_W32(RxConfig, tmp);
6120
6121         spin_unlock_irqrestore(&tp->lock, flags);
6122 }
6123
6124 /**
6125  *  rtl8169_get_stats - Get rtl8169 read/write statistics
6126  *  @dev: The Ethernet Device to get statistics for
6127  *
6128  *  Get TX/RX statistics for rtl8169
6129  */
6130 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
6131 {
6132         struct rtl8169_private *tp = netdev_priv(dev);
6133         void __iomem *ioaddr = tp->mmio_addr;
6134         unsigned long flags;
6135
6136         if (netif_running(dev)) {
6137                 spin_lock_irqsave(&tp->lock, flags);
6138                 rtl8169_rx_missed(dev, ioaddr);
6139                 spin_unlock_irqrestore(&tp->lock, flags);
6140         }
6141
6142         return &dev->stats;
6143 }
6144
6145 static void rtl8169_net_suspend(struct net_device *dev)
6146 {
6147         struct rtl8169_private *tp = netdev_priv(dev);
6148
6149         if (!netif_running(dev))
6150                 return;
6151
6152         rtl_pll_power_down(tp);
6153
6154         netif_device_detach(dev);
6155         netif_stop_queue(dev);
6156 }
6157
6158 #ifdef CONFIG_PM
6159
6160 static int rtl8169_suspend(struct device *device)
6161 {
6162         struct pci_dev *pdev = to_pci_dev(device);
6163         struct net_device *dev = pci_get_drvdata(pdev);
6164
6165         rtl8169_net_suspend(dev);
6166
6167         return 0;
6168 }
6169
6170 static void __rtl8169_resume(struct net_device *dev)
6171 {
6172         struct rtl8169_private *tp = netdev_priv(dev);
6173
6174         netif_device_attach(dev);
6175
6176         rtl_pll_power_up(tp);
6177
6178         rtl8169_schedule_work(dev, rtl8169_reset_task);
6179 }
6180
6181 static int rtl8169_resume(struct device *device)
6182 {
6183         struct pci_dev *pdev = to_pci_dev(device);
6184         struct net_device *dev = pci_get_drvdata(pdev);
6185         struct rtl8169_private *tp = netdev_priv(dev);
6186
6187         rtl8169_init_phy(dev, tp);
6188
6189         if (netif_running(dev))
6190                 __rtl8169_resume(dev);
6191
6192         return 0;
6193 }
6194
6195 static int rtl8169_runtime_suspend(struct device *device)
6196 {
6197         struct pci_dev *pdev = to_pci_dev(device);
6198         struct net_device *dev = pci_get_drvdata(pdev);
6199         struct rtl8169_private *tp = netdev_priv(dev);
6200
6201         if (!tp->TxDescArray)
6202                 return 0;
6203
6204         spin_lock_irq(&tp->lock);
6205         tp->saved_wolopts = __rtl8169_get_wol(tp);
6206         __rtl8169_set_wol(tp, WAKE_ANY);
6207         spin_unlock_irq(&tp->lock);
6208
6209         rtl8169_net_suspend(dev);
6210
6211         return 0;
6212 }
6213
6214 static int rtl8169_runtime_resume(struct device *device)
6215 {
6216         struct pci_dev *pdev = to_pci_dev(device);
6217         struct net_device *dev = pci_get_drvdata(pdev);
6218         struct rtl8169_private *tp = netdev_priv(dev);
6219
6220         if (!tp->TxDescArray)
6221                 return 0;
6222
6223         spin_lock_irq(&tp->lock);
6224         __rtl8169_set_wol(tp, tp->saved_wolopts);
6225         tp->saved_wolopts = 0;
6226         spin_unlock_irq(&tp->lock);
6227
6228         rtl8169_init_phy(dev, tp);
6229
6230         __rtl8169_resume(dev);
6231
6232         return 0;
6233 }
6234
6235 static int rtl8169_runtime_idle(struct device *device)
6236 {
6237         struct pci_dev *pdev = to_pci_dev(device);
6238         struct net_device *dev = pci_get_drvdata(pdev);
6239         struct rtl8169_private *tp = netdev_priv(dev);
6240
6241         return tp->TxDescArray ? -EBUSY : 0;
6242 }
6243
6244 static const struct dev_pm_ops rtl8169_pm_ops = {
6245         .suspend                = rtl8169_suspend,
6246         .resume                 = rtl8169_resume,
6247         .freeze                 = rtl8169_suspend,
6248         .thaw                   = rtl8169_resume,
6249         .poweroff               = rtl8169_suspend,
6250         .restore                = rtl8169_resume,
6251         .runtime_suspend        = rtl8169_runtime_suspend,
6252         .runtime_resume         = rtl8169_runtime_resume,
6253         .runtime_idle           = rtl8169_runtime_idle,
6254 };
6255
6256 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6257
6258 #else /* !CONFIG_PM */
6259
6260 #define RTL8169_PM_OPS  NULL
6261
6262 #endif /* !CONFIG_PM */
6263
6264 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6265 {
6266         void __iomem *ioaddr = tp->mmio_addr;
6267
6268         /* WoL fails with 8168b when the receiver is disabled. */
6269         switch (tp->mac_version) {
6270         case RTL_GIGA_MAC_VER_11:
6271         case RTL_GIGA_MAC_VER_12:
6272         case RTL_GIGA_MAC_VER_17:
6273                 pci_clear_master(tp->pci_dev);
6274
6275                 RTL_W8(ChipCmd, CmdRxEnb);
6276                 /* PCI commit */
6277                 RTL_R8(ChipCmd);
6278                 break;
6279         default:
6280                 break;
6281         }
6282 }
6283
6284 static void rtl_shutdown(struct pci_dev *pdev)
6285 {
6286         struct net_device *dev = pci_get_drvdata(pdev);
6287         struct rtl8169_private *tp = netdev_priv(dev);
6288         struct device *d = &pdev->dev;
6289
6290         pm_runtime_get_sync(d);
6291
6292         rtl8169_net_suspend(dev);
6293
6294         /* Restore original MAC address */
6295         rtl_rar_set(tp, dev->perm_addr);
6296
6297         spin_lock_irq(&tp->lock);
6298
6299         rtl8169_hw_reset(tp);
6300
6301         spin_unlock_irq(&tp->lock);
6302
6303         if (system_state == SYSTEM_POWER_OFF) {
6304                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6305                         rtl_wol_suspend_quirk(tp);
6306                         rtl_wol_shutdown_quirk(tp);
6307                 }
6308
6309                 pci_wake_from_d3(pdev, true);
6310                 pci_set_power_state(pdev, PCI_D3hot);
6311         }
6312
6313         pm_runtime_put_noidle(d);
6314 }
6315
6316 static struct pci_driver rtl8169_pci_driver = {
6317         .name           = MODULENAME,
6318         .id_table       = rtl8169_pci_tbl,
6319         .probe          = rtl8169_init_one,
6320         .remove         = __devexit_p(rtl8169_remove_one),
6321         .shutdown       = rtl_shutdown,
6322         .driver.pm      = RTL8169_PM_OPS,
6323 };
6324
6325 static int __init rtl8169_init_module(void)
6326 {
6327         return pci_register_driver(&rtl8169_pci_driver);
6328 }
6329
6330 static void __exit rtl8169_cleanup_module(void)
6331 {
6332         pci_unregister_driver(&rtl8169_pci_driver);
6333 }
6334
6335 module_init(rtl8169_init_module);
6336 module_exit(rtl8169_cleanup_module);