2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/hardirq.h>
38 #include <linux/export.h>
39 #include <linux/gfp.h>
41 #include <linux/mlx4/cmd.h>
42 #include <linux/mlx4/cq.h>
47 struct mlx4_cq_context {
51 __be32 logsize_usrpage;
59 __be32 mtt_base_addr_l;
60 __be32 last_notified_index;
61 __be32 solicit_producer_index;
62 __be32 consumer_index;
63 __be32 producer_index;
68 #define MLX4_CQ_STATUS_OK ( 0 << 28)
69 #define MLX4_CQ_STATUS_OVERFLOW ( 9 << 28)
70 #define MLX4_CQ_STATUS_WRITE_FAIL (10 << 28)
71 #define MLX4_CQ_FLAG_CC ( 1 << 18)
72 #define MLX4_CQ_FLAG_OI ( 1 << 17)
73 #define MLX4_CQ_STATE_ARMED ( 9 << 8)
74 #define MLX4_CQ_STATE_ARMED_SOL ( 6 << 8)
75 #define MLX4_EQ_STATE_FIRED (10 << 8)
77 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn)
82 cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree,
83 cqn & (dev->caps.num_cqs - 1));
87 mlx4_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
91 /* Acessing the CQ outside of rcu_read_lock is safe, because
92 * the CQ is freed only after interrupt handling is completed.
99 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type)
101 struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
105 cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1));
109 mlx4_dbg(dev, "Async event for bogus CQ %08x\n", cqn);
113 /* Acessing the CQ outside of rcu_read_lock is safe, because
114 * the CQ is freed only after interrupt handling is completed.
116 cq->event(cq, event_type);
119 static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
122 return mlx4_cmd(dev, mailbox->dma, cq_num, 0, MLX4_CMD_SW2HW_CQ,
123 MLX4_CMD_TIME_CLASS_A);
126 static int mlx4_MODIFY_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
127 int cq_num, u32 opmod)
129 return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
130 MLX4_CMD_TIME_CLASS_A);
133 static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
136 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, cq_num,
137 mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ,
138 MLX4_CMD_TIME_CLASS_A);
141 int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
142 u16 count, u16 period)
144 struct mlx4_cmd_mailbox *mailbox;
145 struct mlx4_cq_context *cq_context;
148 mailbox = mlx4_alloc_cmd_mailbox(dev);
150 return PTR_ERR(mailbox);
152 cq_context = mailbox->buf;
153 memset(cq_context, 0, sizeof *cq_context);
155 cq_context->cq_max_count = cpu_to_be16(count);
156 cq_context->cq_period = cpu_to_be16(period);
158 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1);
160 mlx4_free_cmd_mailbox(dev, mailbox);
163 EXPORT_SYMBOL_GPL(mlx4_cq_modify);
165 int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq,
166 int entries, struct mlx4_mtt *mtt)
168 struct mlx4_cmd_mailbox *mailbox;
169 struct mlx4_cq_context *cq_context;
173 mailbox = mlx4_alloc_cmd_mailbox(dev);
175 return PTR_ERR(mailbox);
177 cq_context = mailbox->buf;
178 memset(cq_context, 0, sizeof *cq_context);
180 cq_context->logsize_usrpage = cpu_to_be32(ilog2(entries) << 24);
181 cq_context->log_page_size = mtt->page_shift - 12;
182 mtt_addr = mlx4_mtt_addr(dev, mtt);
183 cq_context->mtt_base_addr_h = mtt_addr >> 32;
184 cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
186 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 0);
188 mlx4_free_cmd_mailbox(dev, mailbox);
191 EXPORT_SYMBOL_GPL(mlx4_cq_resize);
193 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
194 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
195 unsigned vector, int collapsed)
197 struct mlx4_priv *priv = mlx4_priv(dev);
198 struct mlx4_cq_table *cq_table = &priv->cq_table;
199 struct mlx4_cmd_mailbox *mailbox;
200 struct mlx4_cq_context *cq_context;
204 if (vector > dev->caps.num_comp_vectors + dev->caps.comp_pool)
209 cq->cqn = mlx4_bitmap_alloc(&cq_table->bitmap);
213 err = mlx4_table_get(dev, &cq_table->table, cq->cqn);
217 err = mlx4_table_get(dev, &cq_table->cmpt_table, cq->cqn);
221 spin_lock(&cq_table->lock);
222 err = radix_tree_insert(&cq_table->tree, cq->cqn, cq);
223 spin_unlock(&cq_table->lock);
227 mailbox = mlx4_alloc_cmd_mailbox(dev);
228 if (IS_ERR(mailbox)) {
229 err = PTR_ERR(mailbox);
233 cq_context = mailbox->buf;
234 memset(cq_context, 0, sizeof *cq_context);
236 cq_context->flags = cpu_to_be32(!!collapsed << 18);
237 cq_context->logsize_usrpage = cpu_to_be32((ilog2(nent) << 24) | uar->index);
238 cq_context->comp_eqn = priv->eq_table.eq[vector].eqn;
239 cq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
241 mtt_addr = mlx4_mtt_addr(dev, mtt);
242 cq_context->mtt_base_addr_h = mtt_addr >> 32;
243 cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
244 cq_context->db_rec_addr = cpu_to_be64(db_rec);
246 err = mlx4_SW2HW_CQ(dev, mailbox, cq->cqn);
247 mlx4_free_cmd_mailbox(dev, mailbox);
254 atomic_set(&cq->refcount, 1);
255 init_completion(&cq->free);
260 spin_lock(&cq_table->lock);
261 radix_tree_delete(&cq_table->tree, cq->cqn);
262 spin_unlock(&cq_table->lock);
265 mlx4_table_put(dev, &cq_table->cmpt_table, cq->cqn);
268 mlx4_table_put(dev, &cq_table->table, cq->cqn);
271 mlx4_bitmap_free(&cq_table->bitmap, cq->cqn);
275 EXPORT_SYMBOL_GPL(mlx4_cq_alloc);
277 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq)
279 struct mlx4_priv *priv = mlx4_priv(dev);
280 struct mlx4_cq_table *cq_table = &priv->cq_table;
283 err = mlx4_HW2SW_CQ(dev, NULL, cq->cqn);
285 mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn);
287 spin_lock(&cq_table->lock);
288 radix_tree_delete(&cq_table->tree, cq->cqn);
289 spin_unlock(&cq_table->lock);
291 synchronize_irq(priv->eq_table.eq[cq->vector].irq);
293 if (atomic_dec_and_test(&cq->refcount))
295 wait_for_completion(&cq->free);
297 mlx4_table_put(dev, &cq_table->table, cq->cqn);
298 mlx4_bitmap_free(&cq_table->bitmap, cq->cqn);
300 EXPORT_SYMBOL_GPL(mlx4_cq_free);
302 int mlx4_init_cq_table(struct mlx4_dev *dev)
304 struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
307 spin_lock_init(&cq_table->lock);
308 INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
310 err = mlx4_bitmap_init(&cq_table->bitmap, dev->caps.num_cqs,
311 dev->caps.num_cqs - 1, dev->caps.reserved_cqs, 0);
318 void mlx4_cleanup_cq_table(struct mlx4_dev *dev)
320 /* Nothing to do to clean up radix_tree */
321 mlx4_bitmap_cleanup(&mlx4_priv(dev)->cq_table.bitmap);