drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/sctp.h>
  39 #include <linux/pkt_sched.h>
  40 #include <linux/ipv6.h>
  41 #include <linux/slab.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <linux/ethtool.h>
  45 #include <linux/if.h>
  46 #include <linux/if_vlan.h>
  47 #include <linux/prefetch.h>
  48 #include <scsi/fc/fc_fcoe.h>
  49
  50 #include "ixgbe.h"
  51 #include "ixgbe_common.h"
  52 #include "ixgbe_dcb_82599.h"
  53 #include "ixgbe_sriov.h"
  54
  55 char ixgbe_driver_name[] = "ixgbe";
  56 static const char ixgbe_driver_string[] =
  57                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  58 #define MAJ 3
  59 #define MIN 6
  60 #define BUILD 7
  61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  62         __stringify(BUILD) "-k"
  63 const char ixgbe_driver_version[] = DRV_VERSION;
  64 static const char ixgbe_copyright[] =
  65                                 "Copyright (c) 1999-2011 Intel Corporation.";
  66
  67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  68         [board_82598] = &ixgbe_82598_info,
  69         [board_82599] = &ixgbe_82599_info,
  70         [board_X540] = &ixgbe_X540_info,
  71 };
  72
  73 /* ixgbe_pci_tbl - PCI Device ID Table
  74  *
  75  * Wildcard entries (PCI_ANY_ID) should come last
  76  * Last entry must be all 0s
  77  *
  78  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  79  *   Class, Class Mask, private data (not used) }
  80  */
  81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
 106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
 108         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
 110         /* required last entry */
 111         {0, }
 112 };
 113 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 114
 115 #ifdef CONFIG_IXGBE_DCA
 116 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 117                             void *p);
 118 static struct notifier_block dca_notifier = {
 119         .notifier_call = ixgbe_notify_dca,
 120         .next          = NULL,
 121         .priority      = 0
 122 };
 123 #endif
 124
 125 #ifdef CONFIG_PCI_IOV
 126 static unsigned int max_vfs;
 127 module_param(max_vfs, uint, 0);
 128 MODULE_PARM_DESC(max_vfs,
 129                  "Maximum number of virtual functions to allocate per physical function");
 130 #endif /* CONFIG_PCI_IOV */
 131
 132 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 133 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 134 MODULE_LICENSE("GPL");
 135 MODULE_VERSION(DRV_VERSION);
 136
 137 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 138
 139 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
 140 {
 141         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
 142             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
 143                 schedule_work(&adapter->service_task);
 144 }
 145
 146 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
 147 {
 148         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
 149
 150         /* flush memory to make sure state is correct before next watchog */
 151         smp_mb__before_clear_bit();
 152         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
 153 }
 154
 155 struct ixgbe_reg_info {
 156         u32 ofs;
 157         char *name;
 158 };
 159
 160 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 161
 162         /* General Registers */
 163         {IXGBE_CTRL, "CTRL"},
 164         {IXGBE_STATUS, "STATUS"},
 165         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 166
 167         /* Interrupt Registers */
 168         {IXGBE_EICR, "EICR"},
 169
 170         /* RX Registers */
 171         {IXGBE_SRRCTL(0), "SRRCTL"},
 172         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 173         {IXGBE_RDLEN(0), "RDLEN"},
 174         {IXGBE_RDH(0), "RDH"},
 175         {IXGBE_RDT(0), "RDT"},
 176         {IXGBE_RXDCTL(0), "RXDCTL"},
 177         {IXGBE_RDBAL(0), "RDBAL"},
 178         {IXGBE_RDBAH(0), "RDBAH"},
 179
 180         /* TX Registers */
 181         {IXGBE_TDBAL(0), "TDBAL"},
 182         {IXGBE_TDBAH(0), "TDBAH"},
 183         {IXGBE_TDLEN(0), "TDLEN"},
 184         {IXGBE_TDH(0), "TDH"},
 185         {IXGBE_TDT(0), "TDT"},
 186         {IXGBE_TXDCTL(0), "TXDCTL"},
 187
 188         /* List Terminator */
 189         {}
 190 };
 191
 192
 193 /*
 194  * ixgbe_regdump - register printout routine
 195  */
 196 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 197 {
 198         int i = 0, j = 0;
 199         char rname[16];
 200         u32 regs[64];
 201
 202         switch (reginfo->ofs) {
 203         case IXGBE_SRRCTL(0):
 204                 for (i = 0; i < 64; i++)
 205                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 206                 break;
 207         case IXGBE_DCA_RXCTRL(0):
 208                 for (i = 0; i < 64; i++)
 209                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 210                 break;
 211         case IXGBE_RDLEN(0):
 212                 for (i = 0; i < 64; i++)
 213                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 214                 break;
 215         case IXGBE_RDH(0):
 216                 for (i = 0; i < 64; i++)
 217                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 218                 break;
 219         case IXGBE_RDT(0):
 220                 for (i = 0; i < 64; i++)
 221                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 222                 break;
 223         case IXGBE_RXDCTL(0):
 224                 for (i = 0; i < 64; i++)
 225                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 226                 break;
 227         case IXGBE_RDBAL(0):
 228                 for (i = 0; i < 64; i++)
 229                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 230                 break;
 231         case IXGBE_RDBAH(0):
 232                 for (i = 0; i < 64; i++)
 233                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 234                 break;
 235         case IXGBE_TDBAL(0):
 236                 for (i = 0; i < 64; i++)
 237                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 238                 break;
 239         case IXGBE_TDBAH(0):
 240                 for (i = 0; i < 64; i++)
 241                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 242                 break;
 243         case IXGBE_TDLEN(0):
 244                 for (i = 0; i < 64; i++)
 245                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 246                 break;
 247         case IXGBE_TDH(0):
 248                 for (i = 0; i < 64; i++)
 249                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 250                 break;
 251         case IXGBE_TDT(0):
 252                 for (i = 0; i < 64; i++)
 253                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 254                 break;
 255         case IXGBE_TXDCTL(0):
 256                 for (i = 0; i < 64; i++)
 257                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 258                 break;
 259         default:
 260                 pr_info("%-15s %08x\n", reginfo->name,
 261                         IXGBE_READ_REG(hw, reginfo->ofs));
 262                 return;
 263         }
 264
 265         for (i = 0; i < 8; i++) {
 266                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 267                 pr_err("%-15s", rname);
 268                 for (j = 0; j < 8; j++)
 269                         pr_cont(" %08x", regs[i*8+j]);
 270                 pr_cont("\n");
 271         }
 272
 273 }
 274
 275 /*
 276  * ixgbe_dump - Print registers, tx-rings and rx-rings
 277  */
 278 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 279 {
 280         struct net_device *netdev = adapter->netdev;
 281         struct ixgbe_hw *hw = &adapter->hw;
 282         struct ixgbe_reg_info *reginfo;
 283         int n = 0;
 284         struct ixgbe_ring *tx_ring;
 285         struct ixgbe_tx_buffer *tx_buffer_info;
 286         union ixgbe_adv_tx_desc *tx_desc;
 287         struct my_u0 { u64 a; u64 b; } *u0;
 288         struct ixgbe_ring *rx_ring;
 289         union ixgbe_adv_rx_desc *rx_desc;
 290         struct ixgbe_rx_buffer *rx_buffer_info;
 291         u32 staterr;
 292         int i = 0;
 293
 294         if (!netif_msg_hw(adapter))
 295                 return;
 296
 297         /* Print netdevice Info */
 298         if (netdev) {
 299                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 300                 pr_info("Device Name     state            "
 301                         "trans_start      last_rx\n");
 302                 pr_info("%-15s %016lX %016lX %016lX\n",
 303                         netdev->name,
 304                         netdev->state,
 305                         netdev->trans_start,
 306                         netdev->last_rx);
 307         }
 308
 309         /* Print Registers */
 310         dev_info(&adapter->pdev->dev, "Register Dump\n");
 311         pr_info(" Register Name   Value\n");
 312         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 313              reginfo->name; reginfo++) {
 314                 ixgbe_regdump(hw, reginfo);
 315         }
 316
 317         /* Print TX Ring Summary */
 318         if (!netdev || !netif_running(netdev))
 319                 goto exit;
 320
 321         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 322         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 323         for (n = 0; n < adapter->num_tx_queues; n++) {
 324                 tx_ring = adapter->tx_ring[n];
 325                 tx_buffer_info =
 326                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 327                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 328                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 329                            (u64)tx_buffer_info->dma,
 330                            tx_buffer_info->length,
 331                            tx_buffer_info->next_to_watch,
 332                            (u64)tx_buffer_info->time_stamp);
 333         }
 334
 335         /* Print TX Rings */
 336         if (!netif_msg_tx_done(adapter))
 337                 goto rx_ring_summary;
 338
 339         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 340
 341         /* Transmit Descriptor Formats
 342          *
 343          * Advanced Transmit Descriptor
 344          *   +--------------------------------------------------------------+
 345          * 0 |         Buffer Address [63:0]                                |
 346          *   +--------------------------------------------------------------+
 347          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 348          *   +--------------------------------------------------------------+
 349          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 350          */
 351
 352         for (n = 0; n < adapter->num_tx_queues; n++) {
 353                 tx_ring = adapter->tx_ring[n];
 354                 pr_info("------------------------------------\n");
 355                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 356                 pr_info("------------------------------------\n");
 357                 pr_info("T [desc]     [address 63:0  ] "
 358                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 359                         "leng  ntw timestamp        bi->skb\n");
 360
 361                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 362                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 363                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 364                         u0 = (struct my_u0 *)tx_desc;
 365                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 366                                 " %04X  %p %016llX %p", i,
 367                                 le64_to_cpu(u0->a),
 368                                 le64_to_cpu(u0->b),
 369                                 (u64)tx_buffer_info->dma,
 370                                 tx_buffer_info->length,
 371                                 tx_buffer_info->next_to_watch,
 372                                 (u64)tx_buffer_info->time_stamp,
 373                                 tx_buffer_info->skb);
 374                         if (i == tx_ring->next_to_use &&
 375                                 i == tx_ring->next_to_clean)
 376                                 pr_cont(" NTC/U\n");
 377                         else if (i == tx_ring->next_to_use)
 378                                 pr_cont(" NTU\n");
 379                         else if (i == tx_ring->next_to_clean)
 380                                 pr_cont(" NTC\n");
 381                         else
 382                                 pr_cont("\n");
 383
 384                         if (netif_msg_pktdata(adapter) &&
 385                                 tx_buffer_info->dma != 0)
 386                                 print_hex_dump(KERN_INFO, "",
 387                                         DUMP_PREFIX_ADDRESS, 16, 1,
 388                                         phys_to_virt(tx_buffer_info->dma),
 389                                         tx_buffer_info->length, true);
 390                 }
 391         }
 392
 393         /* Print RX Rings Summary */
 394 rx_ring_summary:
 395         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 396         pr_info("Queue [NTU] [NTC]\n");
 397         for (n = 0; n < adapter->num_rx_queues; n++) {
 398                 rx_ring = adapter->rx_ring[n];
 399                 pr_info("%5d %5X %5X\n",
 400                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 401         }
 402
 403         /* Print RX Rings */
 404         if (!netif_msg_rx_status(adapter))
 405                 goto exit;
 406
 407         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 408
 409         /* Advanced Receive Descriptor (Read) Format
 410          *    63                                           1        0
 411          *    +-----------------------------------------------------+
 412          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 413          *    +----------------------------------------------+------+
 414          *  8 |       Header Buffer Address [63:1]           |  DD  |
 415          *    +-----------------------------------------------------+
 416          *
 417          *
 418          * Advanced Receive Descriptor (Write-Back) Format
 419          *
 420          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 421          *   +------------------------------------------------------+
 422          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 423          *   | Checksum   Ident  |   |           |    | Type | Type |
 424          *   +------------------------------------------------------+
 425          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 426          *   +------------------------------------------------------+
 427          *   63       48 47    32 31            20 19               0
 428          */
 429         for (n = 0; n < adapter->num_rx_queues; n++) {
 430                 rx_ring = adapter->rx_ring[n];
 431                 pr_info("------------------------------------\n");
 432                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 433                 pr_info("------------------------------------\n");
 434                 pr_info("R  [desc]      [ PktBuf     A0] "
 435                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 436                         "<-- Adv Rx Read format\n");
 437                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 438                         "[vl er S cks ln] ---------------- [bi->skb] "
 439                         "<-- Adv Rx Write-Back format\n");
 440
 441                 for (i = 0; i < rx_ring->count; i++) {
 442                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 443                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 444                         u0 = (struct my_u0 *)rx_desc;
 445                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 446                         if (staterr & IXGBE_RXD_STAT_DD) {
 447                                 /* Descriptor Done */
 448                                 pr_info("RWB[0x%03X]     %016llX "
 449                                         "%016llX ---------------- %p", i,
 450                                         le64_to_cpu(u0->a),
 451                                         le64_to_cpu(u0->b),
 452                                         rx_buffer_info->skb);
 453                         } else {
 454                                 pr_info("R  [0x%03X]     %016llX "
 455                                         "%016llX %016llX %p", i,
 456                                         le64_to_cpu(u0->a),
 457                                         le64_to_cpu(u0->b),
 458                                         (u64)rx_buffer_info->dma,
 459                                         rx_buffer_info->skb);
 460
 461                                 if (netif_msg_pktdata(adapter)) {
 462                                         print_hex_dump(KERN_INFO, "",
 463                                            DUMP_PREFIX_ADDRESS, 16, 1,
 464                                            phys_to_virt(rx_buffer_info->dma),
 465                                            rx_ring->rx_buf_len, true);
 466
 467                                         if (rx_ring->rx_buf_len
 468                                                 < IXGBE_RXBUFFER_2K)
 469                                                 print_hex_dump(KERN_INFO, "",
 470                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 471                                                   phys_to_virt(
 472                                                     rx_buffer_info->page_dma +
 473                                                     rx_buffer_info->page_offset
 474                                                   ),
 475                                                   PAGE_SIZE/2, true);
 476                                 }
 477                         }
 478
 479                         if (i == rx_ring->next_to_use)
 480                                 pr_cont(" NTU\n");
 481                         else if (i == rx_ring->next_to_clean)
 482                                 pr_cont(" NTC\n");
 483                         else
 484                                 pr_cont("\n");
 485
 486                 }
 487         }
 488
 489 exit:
 490         return;
 491 }
 492
 493 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 494 {
 495         u32 ctrl_ext;
 496
 497         /* Let firmware take over control of h/w */
 498         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 499         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 500                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 501 }
 502
 503 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 504 {
 505         u32 ctrl_ext;
 506
 507         /* Let firmware know the driver has taken over */
 508         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 509         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 510                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 511 }
 512
 513 /*
 514  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 515  * @adapter: pointer to adapter struct
 516  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 517  * @queue: queue to map the corresponding interrupt to
 518  * @msix_vector: the vector to map to the corresponding queue
 519  *
 520  */
 521 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 522                            u8 queue, u8 msix_vector)
 523 {
 524         u32 ivar, index;
 525         struct ixgbe_hw *hw = &adapter->hw;
 526         switch (hw->mac.type) {
 527         case ixgbe_mac_82598EB:
 528                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 529                 if (direction == -1)
 530                         direction = 0;
 531                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 532                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 533                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 534                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 535                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 536                 break;
 537         case ixgbe_mac_82599EB:
 538         case ixgbe_mac_X540:
 539                 if (direction == -1) {
 540                         /* other causes */
 541                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 542                         index = ((queue & 1) * 8);
 543                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 544                         ivar &= ~(0xFF << index);
 545                         ivar |= (msix_vector << index);
 546                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 547                         break;
 548                 } else {
 549                         /* tx or rx causes */
 550                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 551                         index = ((16 * (queue & 1)) + (8 * direction));
 552                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 553                         ivar &= ~(0xFF << index);
 554                         ivar |= (msix_vector << index);
 555                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 556                         break;
 557                 }
 558         default:
 559                 break;
 560         }
 561 }
 562
 563 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 564                                           u64 qmask)
 565 {
 566         u32 mask;
 567
 568         switch (adapter->hw.mac.type) {
 569         case ixgbe_mac_82598EB:
 570                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 571                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 572                 break;
 573         case ixgbe_mac_82599EB:
 574         case ixgbe_mac_X540:
 575                 mask = (qmask & 0xFFFFFFFF);
 576                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 577                 mask = (qmask >> 32);
 578                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 579                 break;
 580         default:
 581                 break;
 582         }
 583 }
 584
 585 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
 586                                            struct ixgbe_tx_buffer *tx_buffer)
 587 {
 588         if (tx_buffer->dma) {
 589                 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
 590                         dma_unmap_page(ring->dev,
 591                                        tx_buffer->dma,
 592                                        tx_buffer->length,
 593                                        DMA_TO_DEVICE);
 594                 else
 595                         dma_unmap_single(ring->dev,
 596                                          tx_buffer->dma,
 597                                          tx_buffer->length,
 598                                          DMA_TO_DEVICE);
 599         }
 600         tx_buffer->dma = 0;
 601 }
 602
 603 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 604                                       struct ixgbe_tx_buffer *tx_buffer_info)
 605 {
 606         ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
 607         if (tx_buffer_info->skb)
 608                 dev_kfree_skb_any(tx_buffer_info->skb);
 609         tx_buffer_info->skb = NULL;
 610         /* tx_buffer_info must be completely set up in the transmit path */
 611 }
 612
 613 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 614 {
 615         struct ixgbe_hw *hw = &adapter->hw;
 616         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 617         u32 data = 0;
 618         u32 xoff[8] = {0};
 619         int i;
 620
 621         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 622             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 623                 switch (hw->mac.type) {
 624                 case ixgbe_mac_82598EB:
 625                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 626                         break;
 627                 default:
 628                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 629                 }
 630                 hwstats->lxoffrxc += data;
 631
 632                 /* refill credits (no tx hang) if we received xoff */
 633                 if (!data)
 634                         return;
 635
 636                 for (i = 0; i < adapter->num_tx_queues; i++)
 637                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 638                                   &adapter->tx_ring[i]->state);
 639                 return;
 640         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 641                 return;
 642
 643         /* update stats for each tc, only valid with PFC enabled */
 644         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 645                 switch (hw->mac.type) {
 646                 case ixgbe_mac_82598EB:
 647                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 648                         break;
 649                 default:
 650                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 651                 }
 652                 hwstats->pxoffrxc[i] += xoff[i];
 653         }
 654
 655         /* disarm tx queues that have received xoff frames */
 656         for (i = 0; i < adapter->num_tx_queues; i++) {
 657                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 658                 u8 tc = tx_ring->dcb_tc;
 659
 660                 if (xoff[tc])
 661                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 662         }
 663 }
 664
 665 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 666 {
 667         return ring->tx_stats.completed;
 668 }
 669
 670 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 671 {
 672         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 673         struct ixgbe_hw *hw = &adapter->hw;
 674
 675         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 676         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 677
 678         if (head != tail)
 679                 return (head < tail) ?
 680                         tail - head : (tail + ring->count - head);
 681
 682         return 0;
 683 }
 684
 685 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 686 {
 687         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 688         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 689         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 690         bool ret = false;
 691
 692         clear_check_for_tx_hang(tx_ring);
 693
 694         /*
 695          * Check for a hung queue, but be thorough. This verifies
 696          * that a transmit has been completed since the previous
 697          * check AND there is at least one packet pending. The
 698          * ARMED bit is set to indicate a potential hang. The
 699          * bit is cleared if a pause frame is received to remove
 700          * false hang detection due to PFC or 802.3x frames. By
 701          * requiring this to fail twice we avoid races with
 702          * pfc clearing the ARMED bit and conditions where we
 703          * run the check_tx_hang logic with a transmit completion
 704          * pending but without time to complete it yet.
 705          */
 706         if ((tx_done_old == tx_done) && tx_pending) {
 707                 /* make sure it is true for two checks in a row */
 708                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 709                                        &tx_ring->state);
 710         } else {
 711                 /* update completed stats and continue */
 712                 tx_ring->tx_stats.tx_done_old = tx_done;
 713                 /* reset the countdown */
 714                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 715         }
 716
 717         return ret;
 718 }
 719
 720 /**
 721  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 722  * @adapter: driver private struct
 723  **/
 724 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
 725 {
 726
 727         /* Do the reset outside of interrupt context */
 728         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 729                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
 730                 ixgbe_service_event_schedule(adapter);
 731         }
 732 }
 733
 734 /**
 735  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 736  * @q_vector: structure containing interrupt and ring information
 737  * @tx_ring: tx ring to clean
 738  **/
 739 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 740                                struct ixgbe_ring *tx_ring)
 741 {
 742         struct ixgbe_adapter *adapter = q_vector->adapter;
 743         struct ixgbe_tx_buffer *tx_buffer;
 744         union ixgbe_adv_tx_desc *tx_desc;
 745         unsigned int total_bytes = 0, total_packets = 0;
 746         unsigned int budget = q_vector->tx.work_limit;
 747         u16 i = tx_ring->next_to_clean;
 748
 749         tx_buffer = &tx_ring->tx_buffer_info[i];
 750         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 751
 752         for (; budget; budget--) {
 753                 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
 754
 755                 /* if next_to_watch is not set then there is no work pending */
 756                 if (!eop_desc)
 757                         break;
 758
 759                 /* if DD is not set pending work has not been completed */
 760                 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
 761                         break;
 762
 763                 /* count the packet as being completed */
 764                 tx_ring->tx_stats.completed++;
 765
 766                 /* clear next_to_watch to prevent false hangs */
 767                 tx_buffer->next_to_watch = NULL;
 768
 769                 /* prevent any other reads prior to eop_desc being verified */
 770                 rmb();
 771
 772                 do {
 773                         ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
 774                         tx_desc->wb.status = 0;
 775                         if (likely(tx_desc == eop_desc)) {
 776                                 eop_desc = NULL;
 777                                 dev_kfree_skb_any(tx_buffer->skb);
 778                                 tx_buffer->skb = NULL;
 779
 780                                 total_bytes += tx_buffer->bytecount;
 781                                 total_packets += tx_buffer->gso_segs;
 782                         }
 783
 784                         tx_buffer++;
 785                         tx_desc++;
 786                         i++;
 787                         if (unlikely(i == tx_ring->count)) {
 788                                 i = 0;
 789
 790                                 tx_buffer = tx_ring->tx_buffer_info;
 791                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
 792                         }
 793
 794                 } while (eop_desc);
 795         }
 796
 797         tx_ring->next_to_clean = i;
 798         u64_stats_update_begin(&tx_ring->syncp);
 799         tx_ring->stats.bytes += total_bytes;
 800         tx_ring->stats.packets += total_packets;
 801         u64_stats_update_end(&tx_ring->syncp);
 802         q_vector->tx.total_bytes += total_bytes;
 803         q_vector->tx.total_packets += total_packets;
 804
 805         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 806                 /* schedule immediate reset if we believe we hung */
 807                 struct ixgbe_hw *hw = &adapter->hw;
 808                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 809                 e_err(drv, "Detected Tx Unit Hang\n"
 810                         "  Tx Queue             <%d>\n"
 811                         "  TDH, TDT             <%x>, <%x>\n"
 812                         "  next_to_use          <%x>\n"
 813                         "  next_to_clean        <%x>\n"
 814                         "tx_buffer_info[next_to_clean]\n"
 815                         "  time_stamp           <%lx>\n"
 816                         "  jiffies              <%lx>\n",
 817                         tx_ring->queue_index,
 818                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 819                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 820                         tx_ring->next_to_use, i,
 821                         tx_ring->tx_buffer_info[i].time_stamp, jiffies);
 822
 823                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 824
 825                 e_info(probe,
 826                        "tx hang %d detected on queue %d, resetting adapter\n",
 827                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 828
 829                 /* schedule immediate reset if we believe we hung */
 830                 ixgbe_tx_timeout_reset(adapter);
 831
 832                 /* the adapter is about to reset, no point in enabling stuff */
 833                 return true;
 834         }
 835
 836 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 837         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 838                      (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
 839                 /* Make sure that anybody stopping the queue after this
 840                  * sees the new next_to_clean.
 841                  */
 842                 smp_mb();
 843                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 844                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 845                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 846                         ++tx_ring->tx_stats.restart_queue;
 847                 }
 848         }
 849
 850         return !!budget;
 851 }
 852
 853 #ifdef CONFIG_IXGBE_DCA
 854 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 855                                 struct ixgbe_ring *rx_ring,
 856                                 int cpu)
 857 {
 858         struct ixgbe_hw *hw = &adapter->hw;
 859         u32 rxctrl;
 860         u8 reg_idx = rx_ring->reg_idx;
 861
 862         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 863         switch (hw->mac.type) {
 864         case ixgbe_mac_82598EB:
 865                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 866                 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
 867                 break;
 868         case ixgbe_mac_82599EB:
 869         case ixgbe_mac_X540:
 870                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 871                 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
 872                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 873                 break;
 874         default:
 875                 break;
 876         }
 877         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 878         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 879         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 880         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 881 }
 882
 883 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 884                                 struct ixgbe_ring *tx_ring,
 885                                 int cpu)
 886 {
 887         struct ixgbe_hw *hw = &adapter->hw;
 888         u32 txctrl;
 889         u8 reg_idx = tx_ring->reg_idx;
 890
 891         switch (hw->mac.type) {
 892         case ixgbe_mac_82598EB:
 893                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 894                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 895                 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
 896                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 897                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 898                 break;
 899         case ixgbe_mac_82599EB:
 900         case ixgbe_mac_X540:
 901                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 902                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 903                 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
 904                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 905                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 906                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 907                 break;
 908         default:
 909                 break;
 910         }
 911 }
 912
 913 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 914 {
 915         struct ixgbe_adapter *adapter = q_vector->adapter;
 916         struct ixgbe_ring *ring;
 917         int cpu = get_cpu();
 918
 919         if (q_vector->cpu == cpu)
 920                 goto out_no_update;
 921
 922         for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
 923                 ixgbe_update_tx_dca(adapter, ring, cpu);
 924
 925         for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
 926                 ixgbe_update_rx_dca(adapter, ring, cpu);
 927
 928         q_vector->cpu = cpu;
 929 out_no_update:
 930         put_cpu();
 931 }
 932
 933 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 934 {
 935         int num_q_vectors;
 936         int i;
 937
 938         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 939                 return;
 940
 941         /* always use CB2 mode, difference is masked in the CB driver */
 942         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 943
 944         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 945                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 946         else
 947                 num_q_vectors = 1;
 948
 949         for (i = 0; i < num_q_vectors; i++) {
 950                 adapter->q_vector[i]->cpu = -1;
 951                 ixgbe_update_dca(adapter->q_vector[i]);
 952         }
 953 }
 954
 955 static int __ixgbe_notify_dca(struct device *dev, void *data)
 956 {
 957         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
 958         unsigned long event = *(unsigned long *)data;
 959
 960         if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
 961                 return 0;
 962
 963         switch (event) {
 964         case DCA_PROVIDER_ADD:
 965                 /* if we're already enabled, don't do it again */
 966                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 967                         break;
 968                 if (dca_add_requester(dev) == 0) {
 969                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 970                         ixgbe_setup_dca(adapter);
 971                         break;
 972                 }
 973                 /* Fall Through since DCA is disabled. */
 974         case DCA_PROVIDER_REMOVE:
 975                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 976                         dca_remove_requester(dev);
 977                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 978                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 979                 }
 980                 break;
 981         }
 982
 983         return 0;
 984 }
 985 #endif /* CONFIG_IXGBE_DCA */
 986
 987 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
 988                                  struct sk_buff *skb)
 989 {
 990         skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
 991 }
 992
 993 /**
 994  * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
 995  * @adapter: address of board private structure
 996  * @rx_desc: advanced rx descriptor
 997  *
 998  * Returns : true if it is FCoE pkt
 999  */
1000 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1001                                     union ixgbe_adv_rx_desc *rx_desc)
1002 {
1003         __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1004
1005         return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1006                ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1007                 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1008                              IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1009 }
1010
1011 /**
1012  * ixgbe_receive_skb - Send a completed packet up the stack
1013  * @adapter: board private structure
1014  * @skb: packet to send up
1015  * @status: hardware indication of status of receive
1016  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1017  * @rx_desc: rx descriptor
1018  **/
1019 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1020                               struct sk_buff *skb, u8 status,
1021                               struct ixgbe_ring *ring,
1022                               union ixgbe_adv_rx_desc *rx_desc)
1023 {
1024         struct ixgbe_adapter *adapter = q_vector->adapter;
1025         struct napi_struct *napi = &q_vector->napi;
1026         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1027         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1028
1029         if (is_vlan && (tag & VLAN_VID_MASK))
1030                 __vlan_hwaccel_put_tag(skb, tag);
1031
1032         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1033                 napi_gro_receive(napi, skb);
1034         else
1035                 netif_rx(skb);
1036 }
1037
1038 /**
1039  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1040  * @adapter: address of board private structure
1041  * @status_err: hardware indication of status of receive
1042  * @skb: skb currently being received and modified
1043  * @status_err: status error value of last descriptor in packet
1044  **/
1045 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1046                                      union ixgbe_adv_rx_desc *rx_desc,
1047                                      struct sk_buff *skb,
1048                                      u32 status_err)
1049 {
1050         skb->ip_summed = CHECKSUM_NONE;
1051
1052         /* Rx csum disabled */
1053         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1054                 return;
1055
1056         /* if IP and error */
1057         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1058             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1059                 adapter->hw_csum_rx_error++;
1060                 return;
1061         }
1062
1063         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1064                 return;
1065
1066         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1067                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1068
1069                 /*
1070                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1071                  * checksum errors.
1072                  */
1073                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1074                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1075                         return;
1076
1077                 adapter->hw_csum_rx_error++;
1078                 return;
1079         }
1080
1081         /* It must be a TCP or UDP packet with a valid checksum */
1082         skb->ip_summed = CHECKSUM_UNNECESSARY;
1083 }
1084
1085 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1086 {
1087         /*
1088          * Force memory writes to complete before letting h/w
1089          * know there are new descriptors to fetch.  (Only
1090          * applicable for weak-ordered memory model archs,
1091          * such as IA-64).
1092          */
1093         wmb();
1094         writel(val, rx_ring->tail);
1095 }
1096
1097 /**
1098  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1099  * @rx_ring: ring to place buffers on
1100  * @cleaned_count: number of buffers to replace
1101  **/
1102 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1103 {
1104         union ixgbe_adv_rx_desc *rx_desc;
1105         struct ixgbe_rx_buffer *bi;
1106         struct sk_buff *skb;
1107         u16 i = rx_ring->next_to_use;
1108
1109         /* do nothing if no valid netdev defined */
1110         if (!rx_ring->netdev)
1111                 return;
1112
1113         while (cleaned_count--) {
1114                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1115                 bi = &rx_ring->rx_buffer_info[i];
1116                 skb = bi->skb;
1117
1118                 if (!skb) {
1119                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1120                                                         rx_ring->rx_buf_len);
1121                         if (!skb) {
1122                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1123                                 goto no_buffers;
1124                         }
1125                         /* initialize queue mapping */
1126                         skb_record_rx_queue(skb, rx_ring->queue_index);
1127                         bi->skb = skb;
1128                 }
1129
1130                 if (!bi->dma) {
1131                         bi->dma = dma_map_single(rx_ring->dev,
1132                                                  skb->data,
1133                                                  rx_ring->rx_buf_len,
1134                                                  DMA_FROM_DEVICE);
1135                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1136                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1137                                 bi->dma = 0;
1138                                 goto no_buffers;
1139                         }
1140                 }
1141
1142                 if (ring_is_ps_enabled(rx_ring)) {
1143                         if (!bi->page) {
1144                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1145                                 if (!bi->page) {
1146                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1147                                         goto no_buffers;
1148                                 }
1149                         }
1150
1151                         if (!bi->page_dma) {
1152                                 /* use a half page if we're re-using */
1153                                 bi->page_offset ^= PAGE_SIZE / 2;
1154                                 bi->page_dma = dma_map_page(rx_ring->dev,
1155                                                             bi->page,
1156                                                             bi->page_offset,
1157                                                             PAGE_SIZE / 2,
1158                                                             DMA_FROM_DEVICE);
1159                                 if (dma_mapping_error(rx_ring->dev,
1160                                                       bi->page_dma)) {
1161                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1162                                         bi->page_dma = 0;
1163                                         goto no_buffers;
1164                                 }
1165                         }
1166
1167                         /* Refresh the desc even if buffer_addrs didn't change
1168                          * because each write-back erases this info. */
1169                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1170                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1171                 } else {
1172                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1173                         rx_desc->read.hdr_addr = 0;
1174                 }
1175
1176                 i++;
1177                 if (i == rx_ring->count)
1178                         i = 0;
1179         }
1180
1181 no_buffers:
1182         if (rx_ring->next_to_use != i) {
1183                 rx_ring->next_to_use = i;
1184                 ixgbe_release_rx_desc(rx_ring, i);
1185         }
1186 }
1187
1188 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1189 {
1190         /* HW will not DMA in data larger than the given buffer, even if it
1191          * parses the (NFS, of course) header to be larger.  In that case, it
1192          * fills the header buffer and spills the rest into the page.
1193          */
1194         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1195         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1196                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1197         if (hlen > IXGBE_RX_HDR_SIZE)
1198                 hlen = IXGBE_RX_HDR_SIZE;
1199         return hlen;
1200 }
1201
1202 /**
1203  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1204  * @skb: pointer to the last skb in the rsc queue
1205  *
1206  * This function changes a queue full of hw rsc buffers into a completed
1207  * packet.  It uses the ->prev pointers to find the first packet and then
1208  * turns it into the frag list owner.
1209  **/
1210 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1211 {
1212         unsigned int frag_list_size = 0;
1213         unsigned int skb_cnt = 1;
1214
1215         while (skb->prev) {
1216                 struct sk_buff *prev = skb->prev;
1217                 frag_list_size += skb->len;
1218                 skb->prev = NULL;
1219                 skb = prev;
1220                 skb_cnt++;
1221         }
1222
1223         skb_shinfo(skb)->frag_list = skb->next;
1224         skb->next = NULL;
1225         skb->len += frag_list_size;
1226         skb->data_len += frag_list_size;
1227         skb->truesize += frag_list_size;
1228         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1229
1230         return skb;
1231 }
1232
1233 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1234 {
1235         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1236                 IXGBE_RXDADV_RSCCNT_MASK);
1237 }
1238
1239 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1240                                struct ixgbe_ring *rx_ring,
1241                                int budget)
1242 {
1243         struct ixgbe_adapter *adapter = q_vector->adapter;
1244         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1245         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1246         struct sk_buff *skb;
1247         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1248         const int current_node = numa_node_id();
1249 #ifdef IXGBE_FCOE
1250         int ddp_bytes = 0;
1251 #endif /* IXGBE_FCOE */
1252         u32 staterr;
1253         u16 i;
1254         u16 cleaned_count = 0;
1255         bool pkt_is_rsc = false;
1256
1257         i = rx_ring->next_to_clean;
1258         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1259         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1260
1261         while (staterr & IXGBE_RXD_STAT_DD) {
1262                 u32 upper_len = 0;
1263
1264                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1265
1266                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1267
1268                 skb = rx_buffer_info->skb;
1269                 rx_buffer_info->skb = NULL;
1270                 prefetch(skb->data);
1271
1272                 if (ring_is_rsc_enabled(rx_ring))
1273                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1274
1275                 /* linear means we are building an skb from multiple pages */
1276                 if (!skb_is_nonlinear(skb)) {
1277                         u16 hlen;
1278                         if (pkt_is_rsc &&
1279                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1280                             !skb->prev) {
1281                                 /*
1282                                  * When HWRSC is enabled, delay unmapping
1283                                  * of the first packet. It carries the
1284                                  * header information, HW may still
1285                                  * access the header after the writeback.
1286                                  * Only unmap it when EOP is reached
1287                                  */
1288                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1289                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1290                         } else {
1291                                 dma_unmap_single(rx_ring->dev,
1292                                                  rx_buffer_info->dma,
1293                                                  rx_ring->rx_buf_len,
1294                                                  DMA_FROM_DEVICE);
1295                         }
1296                         rx_buffer_info->dma = 0;
1297
1298                         if (ring_is_ps_enabled(rx_ring)) {
1299                                 hlen = ixgbe_get_hlen(rx_desc);
1300                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1301                         } else {
1302                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1303                         }
1304
1305                         skb_put(skb, hlen);
1306                 } else {
1307                         /* assume packet split since header is unmapped */
1308                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1309                 }
1310
1311                 if (upper_len) {
1312                         dma_unmap_page(rx_ring->dev,
1313                                        rx_buffer_info->page_dma,
1314                                        PAGE_SIZE / 2,
1315                                        DMA_FROM_DEVICE);
1316                         rx_buffer_info->page_dma = 0;
1317                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1318                                            rx_buffer_info->page,
1319                                            rx_buffer_info->page_offset,
1320                                            upper_len);
1321
1322                         if ((page_count(rx_buffer_info->page) == 1) &&
1323                             (page_to_nid(rx_buffer_info->page) == current_node))
1324                                 get_page(rx_buffer_info->page);
1325                         else
1326                                 rx_buffer_info->page = NULL;
1327
1328                         skb->len += upper_len;
1329                         skb->data_len += upper_len;
1330                         skb->truesize += PAGE_SIZE / 2;
1331                 }
1332
1333                 i++;
1334                 if (i == rx_ring->count)
1335                         i = 0;
1336
1337                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1338                 prefetch(next_rxd);
1339                 cleaned_count++;
1340
1341                 if (pkt_is_rsc) {
1342                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1343                                      IXGBE_RXDADV_NEXTP_SHIFT;
1344                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1345                 } else {
1346                         next_buffer = &rx_ring->rx_buffer_info[i];
1347                 }
1348
1349                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1350                         if (ring_is_ps_enabled(rx_ring)) {
1351                                 rx_buffer_info->skb = next_buffer->skb;
1352                                 rx_buffer_info->dma = next_buffer->dma;
1353                                 next_buffer->skb = skb;
1354                                 next_buffer->dma = 0;
1355                         } else {
1356                                 skb->next = next_buffer->skb;
1357                                 skb->next->prev = skb;
1358                         }
1359                         rx_ring->rx_stats.non_eop_descs++;
1360                         goto next_desc;
1361                 }
1362
1363                 if (skb->prev) {
1364                         skb = ixgbe_transform_rsc_queue(skb);
1365                         /* if we got here without RSC the packet is invalid */
1366                         if (!pkt_is_rsc) {
1367                                 __pskb_trim(skb, 0);
1368                                 rx_buffer_info->skb = skb;
1369                                 goto next_desc;
1370                         }
1371                 }
1372
1373                 if (ring_is_rsc_enabled(rx_ring)) {
1374                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1375                                 dma_unmap_single(rx_ring->dev,
1376                                                  IXGBE_RSC_CB(skb)->dma,
1377                                                  rx_ring->rx_buf_len,
1378                                                  DMA_FROM_DEVICE);
1379                                 IXGBE_RSC_CB(skb)->dma = 0;
1380                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1381                         }
1382                 }
1383                 if (pkt_is_rsc) {
1384                         if (ring_is_ps_enabled(rx_ring))
1385                                 rx_ring->rx_stats.rsc_count +=
1386                                         skb_shinfo(skb)->nr_frags;
1387                         else
1388                                 rx_ring->rx_stats.rsc_count +=
1389                                         IXGBE_RSC_CB(skb)->skb_cnt;
1390                         rx_ring->rx_stats.rsc_flush++;
1391                 }
1392
1393                 /* ERR_MASK will only have valid bits if EOP set */
1394                 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1395                         dev_kfree_skb_any(skb);
1396                         goto next_desc;
1397                 }
1398
1399                 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1400                 if (adapter->netdev->features & NETIF_F_RXHASH)
1401                         ixgbe_rx_hash(rx_desc, skb);
1402
1403                 /* probably a little skewed due to removing CRC */
1404                 total_rx_bytes += skb->len;
1405                 total_rx_packets++;
1406
1407                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1408 #ifdef IXGBE_FCOE
1409                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1410                 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1411                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1412                                                    staterr);
1413                         if (!ddp_bytes) {
1414                                 dev_kfree_skb_any(skb);
1415                                 goto next_desc;
1416                         }
1417                 }
1418 #endif /* IXGBE_FCOE */
1419                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1420
1421                 budget--;
1422 next_desc:
1423                 rx_desc->wb.upper.status_error = 0;
1424
1425                 if (!budget)
1426                         break;
1427
1428                 /* return some buffers to hardware, one at a time is too slow */
1429                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1430                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1431                         cleaned_count = 0;
1432                 }
1433
1434                 /* use prefetched values */
1435                 rx_desc = next_rxd;
1436                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1437         }
1438
1439         rx_ring->next_to_clean = i;
1440         cleaned_count = ixgbe_desc_unused(rx_ring);
1441
1442         if (cleaned_count)
1443                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1444
1445 #ifdef IXGBE_FCOE
1446         /* include DDPed FCoE data */
1447         if (ddp_bytes > 0) {
1448                 unsigned int mss;
1449
1450                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1451                         sizeof(struct fc_frame_header) -
1452                         sizeof(struct fcoe_crc_eof);
1453                 if (mss > 512)
1454                         mss &= ~511;
1455                 total_rx_bytes += ddp_bytes;
1456                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1457         }
1458 #endif /* IXGBE_FCOE */
1459
1460         u64_stats_update_begin(&rx_ring->syncp);
1461         rx_ring->stats.packets += total_rx_packets;
1462         rx_ring->stats.bytes += total_rx_bytes;
1463         u64_stats_update_end(&rx_ring->syncp);
1464         q_vector->rx.total_packets += total_rx_packets;
1465         q_vector->rx.total_bytes += total_rx_bytes;
1466
1467         return !!budget;
1468 }
1469
1470 /**
1471  * ixgbe_configure_msix - Configure MSI-X hardware
1472  * @adapter: board private structure
1473  *
1474  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1475  * interrupts.
1476  **/
1477 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1478 {
1479         struct ixgbe_q_vector *q_vector;
1480         int q_vectors, v_idx;
1481         u32 mask;
1482
1483         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1484
1485         /* Populate MSIX to EITR Select */
1486         if (adapter->num_vfs > 32) {
1487                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1488                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1489         }
1490
1491         /*
1492          * Populate the IVAR table and set the ITR values to the
1493          * corresponding register.
1494          */
1495         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1496                 struct ixgbe_ring *ring;
1497                 q_vector = adapter->q_vector[v_idx];
1498
1499                 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1500                         ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1501
1502                 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1503                         ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1504
1505                 if (q_vector->tx.ring && !q_vector->rx.ring) {
1506                         /* tx only vector */
1507                         if (adapter->tx_itr_setting == 1)
1508                                 q_vector->itr = IXGBE_10K_ITR;
1509                         else
1510                                 q_vector->itr = adapter->tx_itr_setting;
1511                 } else {
1512                         /* rx or rx/tx vector */
1513                         if (adapter->rx_itr_setting == 1)
1514                                 q_vector->itr = IXGBE_20K_ITR;
1515                         else
1516                                 q_vector->itr = adapter->rx_itr_setting;
1517                 }
1518
1519                 ixgbe_write_eitr(q_vector);
1520         }
1521
1522         switch (adapter->hw.mac.type) {
1523         case ixgbe_mac_82598EB:
1524                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1525                                v_idx);
1526                 break;
1527         case ixgbe_mac_82599EB:
1528         case ixgbe_mac_X540:
1529                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1530                 break;
1531         default:
1532                 break;
1533         }
1534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1535
1536         /* set up to autoclear timer, and the vectors */
1537         mask = IXGBE_EIMS_ENABLE_MASK;
1538         mask &= ~(IXGBE_EIMS_OTHER |
1539                   IXGBE_EIMS_MAILBOX |
1540                   IXGBE_EIMS_LSC);
1541
1542         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1543 }
1544
1545 enum latency_range {
1546         lowest_latency = 0,
1547         low_latency = 1,
1548         bulk_latency = 2,
1549         latency_invalid = 255
1550 };
1551
1552 /**
1553  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1554  * @q_vector: structure containing interrupt and ring information
1555  * @ring_container: structure containing ring performance data
1556  *
1557  *      Stores a new ITR value based on packets and byte
1558  *      counts during the last interrupt.  The advantage of per interrupt
1559  *      computation is faster updates and more accurate ITR for the current
1560  *      traffic pattern.  Constants in this function were computed
1561  *      based on theoretical maximum wire speed and thresholds were set based
1562  *      on testing data as well as attempting to minimize response time
1563  *      while increasing bulk throughput.
1564  *      this functionality is controlled by the InterruptThrottleRate module
1565  *      parameter (see ixgbe_param.c)
1566  **/
1567 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1568                              struct ixgbe_ring_container *ring_container)
1569 {
1570         u64 bytes_perint;
1571         struct ixgbe_adapter *adapter = q_vector->adapter;
1572         int bytes = ring_container->total_bytes;
1573         int packets = ring_container->total_packets;
1574         u32 timepassed_us;
1575         u8 itr_setting = ring_container->itr;
1576
1577         if (packets == 0)
1578                 return;
1579
1580         /* simple throttlerate management
1581          *    0-20MB/s lowest (100000 ints/s)
1582          *   20-100MB/s low   (20000 ints/s)
1583          *  100-1249MB/s bulk (8000 ints/s)
1584          */
1585         /* what was last interrupt timeslice? */
1586         timepassed_us = q_vector->itr >> 2;
1587         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1588
1589         switch (itr_setting) {
1590         case lowest_latency:
1591                 if (bytes_perint > adapter->eitr_low)
1592                         itr_setting = low_latency;
1593                 break;
1594         case low_latency:
1595                 if (bytes_perint > adapter->eitr_high)
1596                         itr_setting = bulk_latency;
1597                 else if (bytes_perint <= adapter->eitr_low)
1598                         itr_setting = lowest_latency;
1599                 break;
1600         case bulk_latency:
1601                 if (bytes_perint <= adapter->eitr_high)
1602                         itr_setting = low_latency;
1603                 break;
1604         }
1605
1606         /* clear work counters since we have the values we need */
1607         ring_container->total_bytes = 0;
1608         ring_container->total_packets = 0;
1609
1610         /* write updated itr to ring container */
1611         ring_container->itr = itr_setting;
1612 }
1613
1614 /**
1615  * ixgbe_write_eitr - write EITR register in hardware specific way
1616  * @q_vector: structure containing interrupt and ring information
1617  *
1618  * This function is made to be called by ethtool and by the driver
1619  * when it needs to update EITR registers at runtime.  Hardware
1620  * specific quirks/differences are taken care of here.
1621  */
1622 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1623 {
1624         struct ixgbe_adapter *adapter = q_vector->adapter;
1625         struct ixgbe_hw *hw = &adapter->hw;
1626         int v_idx = q_vector->v_idx;
1627         u32 itr_reg = q_vector->itr;
1628
1629         switch (adapter->hw.mac.type) {
1630         case ixgbe_mac_82598EB:
1631                 /* must write high and low 16 bits to reset counter */
1632                 itr_reg |= (itr_reg << 16);
1633                 break;
1634         case ixgbe_mac_82599EB:
1635         case ixgbe_mac_X540:
1636                 /*
1637                  * set the WDIS bit to not clear the timer bits and cause an
1638                  * immediate assertion of the interrupt
1639                  */
1640                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1641                 break;
1642         default:
1643                 break;
1644         }
1645         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1646 }
1647
1648 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1649 {
1650         u32 new_itr = q_vector->itr;
1651         u8 current_itr;
1652
1653         ixgbe_update_itr(q_vector, &q_vector->tx);
1654         ixgbe_update_itr(q_vector, &q_vector->rx);
1655
1656         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1657
1658         switch (current_itr) {
1659         /* counts and packets in update_itr are dependent on these numbers */
1660         case lowest_latency:
1661                 new_itr = IXGBE_100K_ITR;
1662                 break;
1663         case low_latency:
1664                 new_itr = IXGBE_20K_ITR;
1665                 break;
1666         case bulk_latency:
1667                 new_itr = IXGBE_8K_ITR;
1668                 break;
1669         default:
1670                 break;
1671         }
1672
1673         if (new_itr != q_vector->itr) {
1674                 /* do an exponential smoothing */
1675                 new_itr = (10 * new_itr * q_vector->itr) /
1676                           ((9 * new_itr) + q_vector->itr);
1677
1678                 /* save the algorithm value here */
1679                 q_vector->itr = new_itr & IXGBE_MAX_EITR;
1680
1681                 ixgbe_write_eitr(q_vector);
1682         }
1683 }
1684
1685 /**
1686  * ixgbe_check_overtemp_subtask - check for over tempurature
1687  * @adapter: pointer to adapter
1688  **/
1689 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1690 {
1691         struct ixgbe_hw *hw = &adapter->hw;
1692         u32 eicr = adapter->interrupt_event;
1693
1694         if (test_bit(__IXGBE_DOWN, &adapter->state))
1695                 return;
1696
1697         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1698             !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1699                 return;
1700
1701         adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1702
1703         switch (hw->device_id) {
1704         case IXGBE_DEV_ID_82599_T3_LOM:
1705                 /*
1706                  * Since the warning interrupt is for both ports
1707                  * we don't have to check if:
1708                  *  - This interrupt wasn't for our port.
1709                  *  - We may have missed the interrupt so always have to
1710                  *    check if we  got a LSC
1711                  */
1712                 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1713                     !(eicr & IXGBE_EICR_LSC))
1714                         return;
1715
1716                 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1717                         u32 autoneg;
1718                         bool link_up = false;
1719
1720                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1721
1722                         if (link_up)
1723                                 return;
1724                 }
1725
1726                 /* Check if this is not due to overtemp */
1727                 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1728                         return;
1729
1730                 break;
1731         default:
1732                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1733                         return;
1734                 break;
1735         }
1736         e_crit(drv,
1737                "Network adapter has been stopped because it has over heated. "
1738                "Restart the computer. If the problem persists, "
1739                "power off the system and replace the adapter\n");
1740
1741         adapter->interrupt_event = 0;
1742 }
1743
1744 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1745 {
1746         struct ixgbe_hw *hw = &adapter->hw;
1747
1748         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1749             (eicr & IXGBE_EICR_GPI_SDP1)) {
1750                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1751                 /* write to clear the interrupt */
1752                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1753         }
1754 }
1755
1756 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1757 {
1758         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1759                 return;
1760
1761         switch (adapter->hw.mac.type) {
1762         case ixgbe_mac_82599EB:
1763                 /*
1764                  * Need to check link state so complete overtemp check
1765                  * on service task
1766                  */
1767                 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1768                     (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1769                         adapter->interrupt_event = eicr;
1770                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1771                         ixgbe_service_event_schedule(adapter);
1772                         return;
1773                 }
1774                 return;
1775         case ixgbe_mac_X540:
1776                 if (!(eicr & IXGBE_EICR_TS))
1777                         return;
1778                 break;
1779         default:
1780                 return;
1781         }
1782
1783         e_crit(drv,
1784                "Network adapter has been stopped because it has over heated. "
1785                "Restart the computer. If the problem persists, "
1786                "power off the system and replace the adapter\n");
1787 }
1788
1789 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1790 {
1791         struct ixgbe_hw *hw = &adapter->hw;
1792
1793         if (eicr & IXGBE_EICR_GPI_SDP2) {
1794                 /* Clear the interrupt */
1795                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1796                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1797                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1798                         ixgbe_service_event_schedule(adapter);
1799                 }
1800         }
1801
1802         if (eicr & IXGBE_EICR_GPI_SDP1) {
1803                 /* Clear the interrupt */
1804                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1805                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1806                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1807                         ixgbe_service_event_schedule(adapter);
1808                 }
1809         }
1810 }
1811
1812 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1813 {
1814         struct ixgbe_hw *hw = &adapter->hw;
1815
1816         adapter->lsc_int++;
1817         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1818         adapter->link_check_timeout = jiffies;
1819         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1820                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1821                 IXGBE_WRITE_FLUSH(hw);
1822                 ixgbe_service_event_schedule(adapter);
1823         }
1824 }
1825
1826 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1827                                            u64 qmask)
1828 {
1829         u32 mask;
1830         struct ixgbe_hw *hw = &adapter->hw;
1831
1832         switch (hw->mac.type) {
1833         case ixgbe_mac_82598EB:
1834                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1835                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1836                 break;
1837         case ixgbe_mac_82599EB:
1838         case ixgbe_mac_X540:
1839                 mask = (qmask & 0xFFFFFFFF);
1840                 if (mask)
1841                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1842                 mask = (qmask >> 32);
1843                 if (mask)
1844                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1845                 break;
1846         default:
1847                 break;
1848         }
1849         /* skip the flush */
1850 }
1851
1852 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1853                                             u64 qmask)
1854 {
1855         u32 mask;
1856         struct ixgbe_hw *hw = &adapter->hw;
1857
1858         switch (hw->mac.type) {
1859         case ixgbe_mac_82598EB:
1860                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1861                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1862                 break;
1863         case ixgbe_mac_82599EB:
1864         case ixgbe_mac_X540:
1865                 mask = (qmask & 0xFFFFFFFF);
1866                 if (mask)
1867                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1868                 mask = (qmask >> 32);
1869                 if (mask)
1870                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1871                 break;
1872         default:
1873                 break;
1874         }
1875         /* skip the flush */
1876 }
1877
1878 /**
1879  * ixgbe_irq_enable - Enable default interrupt generation settings
1880  * @adapter: board private structure
1881  **/
1882 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1883                                     bool flush)
1884 {
1885         u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1886
1887         /* don't reenable LSC while waiting for link */
1888         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1889                 mask &= ~IXGBE_EIMS_LSC;
1890
1891         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
1892                 switch (adapter->hw.mac.type) {
1893                 case ixgbe_mac_82599EB:
1894                         mask |= IXGBE_EIMS_GPI_SDP0;
1895                         break;
1896                 case ixgbe_mac_X540:
1897                         mask |= IXGBE_EIMS_TS;
1898                         break;
1899                 default:
1900                         break;
1901                 }
1902         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1903                 mask |= IXGBE_EIMS_GPI_SDP1;
1904         switch (adapter->hw.mac.type) {
1905         case ixgbe_mac_82599EB:
1906                 mask |= IXGBE_EIMS_GPI_SDP1;
1907                 mask |= IXGBE_EIMS_GPI_SDP2;
1908         case ixgbe_mac_X540:
1909                 mask |= IXGBE_EIMS_ECC;
1910                 mask |= IXGBE_EIMS_MAILBOX;
1911                 break;
1912         default:
1913                 break;
1914         }
1915         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1916             !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1917                 mask |= IXGBE_EIMS_FLOW_DIR;
1918
1919         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1920         if (queues)
1921                 ixgbe_irq_enable_queues(adapter, ~0);
1922         if (flush)
1923                 IXGBE_WRITE_FLUSH(&adapter->hw);
1924 }
1925
1926 static irqreturn_t ixgbe_msix_other(int irq, void *data)
1927 {
1928         struct ixgbe_adapter *adapter = data;
1929         struct ixgbe_hw *hw = &adapter->hw;
1930         u32 eicr;
1931
1932         /*
1933          * Workaround for Silicon errata.  Use clear-by-write instead
1934          * of clear-by-read.  Reading with EICS will return the
1935          * interrupt causes without clearing, which later be done
1936          * with the write to EICR.
1937          */
1938         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1939         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1940
1941         if (eicr & IXGBE_EICR_LSC)
1942                 ixgbe_check_lsc(adapter);
1943
1944         if (eicr & IXGBE_EICR_MAILBOX)
1945                 ixgbe_msg_task(adapter);
1946
1947         switch (hw->mac.type) {
1948         case ixgbe_mac_82599EB:
1949         case ixgbe_mac_X540:
1950                 if (eicr & IXGBE_EICR_ECC)
1951                         e_info(link, "Received unrecoverable ECC Err, please "
1952                                "reboot\n");
1953                 /* Handle Flow Director Full threshold interrupt */
1954                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1955                         int reinit_count = 0;
1956                         int i;
1957                         for (i = 0; i < adapter->num_tx_queues; i++) {
1958                                 struct ixgbe_ring *ring = adapter->tx_ring[i];
1959                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1960                                                        &ring->state))
1961                                         reinit_count++;
1962                         }
1963                         if (reinit_count) {
1964                                 /* no more flow director interrupts until after init */
1965                                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1966                                 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1967                                 ixgbe_service_event_schedule(adapter);
1968                         }
1969                 }
1970                 ixgbe_check_sfp_event(adapter, eicr);
1971                 ixgbe_check_overtemp_event(adapter, eicr);
1972                 break;
1973         default:
1974                 break;
1975         }
1976
1977         ixgbe_check_fan_failure(adapter, eicr);
1978
1979         /* re-enable the original interrupt state, no lsc, no queues */
1980         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1981                 ixgbe_irq_enable(adapter, false, false);
1982
1983         return IRQ_HANDLED;
1984 }
1985
1986 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
1987 {
1988         struct ixgbe_q_vector *q_vector = data;
1989
1990         /* EIAM disabled interrupts (on this vector) for us */
1991
1992         if (q_vector->rx.ring || q_vector->tx.ring)
1993                 napi_schedule(&q_vector->napi);
1994
1995         return IRQ_HANDLED;
1996 }
1997
1998 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1999                                      int r_idx)
2000 {
2001         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2002         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2003
2004         rx_ring->q_vector = q_vector;
2005         rx_ring->next = q_vector->rx.ring;
2006         q_vector->rx.ring = rx_ring;
2007         q_vector->rx.count++;
2008 }
2009
2010 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2011                                      int t_idx)
2012 {
2013         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2014         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2015
2016         tx_ring->q_vector = q_vector;
2017         tx_ring->next = q_vector->tx.ring;
2018         q_vector->tx.ring = tx_ring;
2019         q_vector->tx.count++;
2020         q_vector->tx.work_limit = a->tx_work_limit;
2021 }
2022
2023 /**
2024  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2025  * @adapter: board private structure to initialize
2026  *
2027  * This function maps descriptor rings to the queue-specific vectors
2028  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2029  * one vector per ring/queue, but on a constrained vector budget, we
2030  * group the rings as "efficiently" as possible.  You would add new
2031  * mapping configurations in here.
2032  **/
2033 static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2034 {
2035         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2036         int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2037         int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
2038         int v_start = 0;
2039
2040         /* only one q_vector if MSI-X is disabled. */
2041         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2042                 q_vectors = 1;
2043
2044         /*
2045          * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2046          * group them so there are multiple queues per vector.
2047          *
2048          * Re-adjusting *qpv takes care of the remainder.
2049          */
2050         for (; v_start < q_vectors && rxr_remaining; v_start++) {
2051                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2052                 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
2053                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2054         }
2055
2056         /*
2057          * If there are not enough q_vectors for each ring to have it's own
2058          * vector then we must pair up Rx/Tx on a each vector
2059          */
2060         if ((v_start + txr_remaining) > q_vectors)
2061                 v_start = 0;
2062
2063         for (; v_start < q_vectors && txr_remaining; v_start++) {
2064                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2065                 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2066                         map_vector_to_txq(adapter, v_start, txr_idx);
2067         }
2068 }
2069
2070 /**
2071  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2072  * @adapter: board private structure
2073  *
2074  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2075  * interrupts from the kernel.
2076  **/
2077 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2078 {
2079         struct net_device *netdev = adapter->netdev;
2080         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2081         int vector, err;
2082         int ri = 0, ti = 0;
2083
2084         for (vector = 0; vector < q_vectors; vector++) {
2085                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2086                 struct msix_entry *entry = &adapter->msix_entries[vector];
2087
2088                 if (q_vector->tx.ring && q_vector->rx.ring) {
2089                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2090                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2091                         ti++;
2092                 } else if (q_vector->rx.ring) {
2093                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2094                                  "%s-%s-%d", netdev->name, "rx", ri++);
2095                 } else if (q_vector->tx.ring) {
2096                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2097                                  "%s-%s-%d", netdev->name, "tx", ti++);
2098                 } else {
2099                         /* skip this unused q_vector */
2100                         continue;
2101                 }
2102                 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2103                                   q_vector->name, q_vector);
2104                 if (err) {
2105                         e_err(probe, "request_irq failed for MSIX interrupt "
2106                               "Error: %d\n", err);
2107                         goto free_queue_irqs;
2108                 }
2109                 /* If Flow Director is enabled, set interrupt affinity */
2110                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2111                         /* assign the mask for this irq */
2112                         irq_set_affinity_hint(entry->vector,
2113                                               q_vector->affinity_mask);
2114                 }
2115         }
2116
2117         err = request_irq(adapter->msix_entries[vector].vector,
2118                           ixgbe_msix_other, 0, netdev->name, adapter);
2119         if (err) {
2120                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2121                 goto free_queue_irqs;
2122         }
2123
2124         return 0;
2125
2126 free_queue_irqs:
2127         while (vector) {
2128                 vector--;
2129                 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2130                                       NULL);
2131                 free_irq(adapter->msix_entries[vector].vector,
2132                          adapter->q_vector[vector]);
2133         }
2134         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2135         pci_disable_msix(adapter->pdev);
2136         kfree(adapter->msix_entries);
2137         adapter->msix_entries = NULL;
2138         return err;
2139 }
2140
2141 /**
2142  * ixgbe_intr - legacy mode Interrupt Handler
2143  * @irq: interrupt number
2144  * @data: pointer to a network interface device structure
2145  **/
2146 static irqreturn_t ixgbe_intr(int irq, void *data)
2147 {
2148         struct ixgbe_adapter *adapter = data;
2149         struct ixgbe_hw *hw = &adapter->hw;
2150         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2151         u32 eicr;
2152
2153         /*
2154          * Workaround for silicon errata on 82598.  Mask the interrupts
2155          * before the read of EICR.
2156          */
2157         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2158
2159         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2160          * therefore no explict interrupt disable is necessary */
2161         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2162         if (!eicr) {
2163                 /*
2164                  * shared interrupt alert!
2165                  * make sure interrupts are enabled because the read will
2166                  * have disabled interrupts due to EIAM
2167                  * finish the workaround of silicon errata on 82598.  Unmask
2168                  * the interrupt that we masked before the EICR read.
2169                  */
2170                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2171                         ixgbe_irq_enable(adapter, true, true);
2172                 return IRQ_NONE;        /* Not our interrupt */
2173         }
2174
2175         if (eicr & IXGBE_EICR_LSC)
2176                 ixgbe_check_lsc(adapter);
2177
2178         switch (hw->mac.type) {
2179         case ixgbe_mac_82599EB:
2180                 ixgbe_check_sfp_event(adapter, eicr);
2181                 /* Fall through */
2182         case ixgbe_mac_X540:
2183                 if (eicr & IXGBE_EICR_ECC)
2184                         e_info(link, "Received unrecoverable ECC err, please "
2185                                      "reboot\n");
2186                 ixgbe_check_overtemp_event(adapter, eicr);
2187                 break;
2188         default:
2189                 break;
2190         }
2191
2192         ixgbe_check_fan_failure(adapter, eicr);
2193
2194         if (napi_schedule_prep(&(q_vector->napi))) {
2195                 /* would disable interrupts here but EIAM disabled it */
2196                 __napi_schedule(&(q_vector->napi));
2197         }
2198
2199         /*
2200          * re-enable link(maybe) and non-queue interrupts, no flush.
2201          * ixgbe_poll will re-enable the queue interrupts
2202          */
2203
2204         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2205                 ixgbe_irq_enable(adapter, false, false);
2206
2207         return IRQ_HANDLED;
2208 }
2209
2210 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2211 {
2212         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2213         int i;
2214
2215         /* legacy and MSI only use one vector */
2216         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2217                 q_vectors = 1;
2218
2219         for (i = 0; i < adapter->num_rx_queues; i++) {
2220                 adapter->rx_ring[i]->q_vector = NULL;
2221                 adapter->rx_ring[i]->next = NULL;
2222         }
2223         for (i = 0; i < adapter->num_tx_queues; i++) {
2224                 adapter->tx_ring[i]->q_vector = NULL;
2225                 adapter->tx_ring[i]->next = NULL;
2226         }
2227
2228         for (i = 0; i < q_vectors; i++) {
2229                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2230                 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2231                 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
2232         }
2233 }
2234
2235 /**
2236  * ixgbe_request_irq - initialize interrupts
2237  * @adapter: board private structure
2238  *
2239  * Attempts to configure interrupts using the best available
2240  * capabilities of the hardware and kernel.
2241  **/
2242 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2243 {
2244         struct net_device *netdev = adapter->netdev;
2245         int err;
2246
2247         /* map all of the rings to the q_vectors */
2248         ixgbe_map_rings_to_vectors(adapter);
2249
2250         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2251                 err = ixgbe_request_msix_irqs(adapter);
2252         else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2253                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2254                                   netdev->name, adapter);
2255         else
2256                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2257                                   netdev->name, adapter);
2258
2259         if (err) {
2260                 e_err(probe, "request_irq failed, Error %d\n", err);
2261
2262                 /* place q_vectors and rings back into a known good state */
2263                 ixgbe_reset_q_vectors(adapter);
2264         }
2265
2266         return err;
2267 }
2268
2269 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2270 {
2271         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2272                 int i, q_vectors;
2273
2274                 q_vectors = adapter->num_msix_vectors;
2275                 i = q_vectors - 1;
2276                 free_irq(adapter->msix_entries[i].vector, adapter);
2277                 i--;
2278
2279                 for (; i >= 0; i--) {
2280                         /* free only the irqs that were actually requested */
2281                         if (!adapter->q_vector[i]->rx.ring &&
2282                             !adapter->q_vector[i]->tx.ring)
2283                                 continue;
2284
2285                         /* clear the affinity_mask in the IRQ descriptor */
2286                         irq_set_affinity_hint(adapter->msix_entries[i].vector,
2287                                               NULL);
2288
2289                         free_irq(adapter->msix_entries[i].vector,
2290                                  adapter->q_vector[i]);
2291                 }
2292         } else {
2293                 free_irq(adapter->pdev->irq, adapter);
2294         }
2295
2296         /* clear q_vector state information */
2297         ixgbe_reset_q_vectors(adapter);
2298 }
2299
2300 /**
2301  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2302  * @adapter: board private structure
2303  **/
2304 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2305 {
2306         switch (adapter->hw.mac.type) {
2307         case ixgbe_mac_82598EB:
2308                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2309                 break;
2310         case ixgbe_mac_82599EB:
2311         case ixgbe_mac_X540:
2312                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2313                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2314                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2315                 break;
2316         default:
2317                 break;
2318         }
2319         IXGBE_WRITE_FLUSH(&adapter->hw);
2320         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2321                 int i;
2322                 for (i = 0; i < adapter->num_msix_vectors; i++)
2323                         synchronize_irq(adapter->msix_entries[i].vector);
2324         } else {
2325                 synchronize_irq(adapter->pdev->irq);
2326         }
2327 }
2328
2329 /**
2330  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2331  *
2332  **/
2333 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2334 {
2335         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2336
2337         /* rx/tx vector */
2338         if (adapter->rx_itr_setting == 1)
2339                 q_vector->itr = IXGBE_20K_ITR;
2340         else
2341                 q_vector->itr = adapter->rx_itr_setting;
2342
2343         ixgbe_write_eitr(q_vector);
2344
2345         ixgbe_set_ivar(adapter, 0, 0, 0);
2346         ixgbe_set_ivar(adapter, 1, 0, 0);
2347
2348         e_info(hw, "Legacy interrupt IVAR setup done\n");
2349 }
2350
2351 /**
2352  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2353  * @adapter: board private structure
2354  * @ring: structure containing ring specific data
2355  *
2356  * Configure the Tx descriptor ring after a reset.
2357  **/
2358 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2359                              struct ixgbe_ring *ring)
2360 {
2361         struct ixgbe_hw *hw = &adapter->hw;
2362         u64 tdba = ring->dma;
2363         int wait_loop = 10;
2364         u32 txdctl = IXGBE_TXDCTL_ENABLE;
2365         u8 reg_idx = ring->reg_idx;
2366
2367         /* disable queue to avoid issues while updating state */
2368         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2369         IXGBE_WRITE_FLUSH(hw);
2370
2371         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2372                         (tdba & DMA_BIT_MASK(32)));
2373         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2374         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2375                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2376         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2377         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2378         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2379
2380         /*
2381          * set WTHRESH to encourage burst writeback, it should not be set
2382          * higher than 1 when ITR is 0 as it could cause false TX hangs
2383          *
2384          * In order to avoid issues WTHRESH + PTHRESH should always be equal
2385          * to or less than the number of on chip descriptors, which is
2386          * currently 40.
2387          */
2388         if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2389                 txdctl |= (1 << 16);    /* WTHRESH = 1 */
2390         else
2391                 txdctl |= (8 << 16);    /* WTHRESH = 8 */
2392
2393         /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2394         txdctl |= (1 << 8) |    /* HTHRESH = 1 */
2395                    32;          /* PTHRESH = 32 */
2396
2397         /* reinitialize flowdirector state */
2398         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2399             adapter->atr_sample_rate) {
2400                 ring->atr_sample_rate = adapter->atr_sample_rate;
2401                 ring->atr_count = 0;
2402                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2403         } else {
2404                 ring->atr_sample_rate = 0;
2405         }
2406
2407         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2408
2409         /* enable queue */
2410         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2411
2412         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2413         if (hw->mac.type == ixgbe_mac_82598EB &&
2414             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2415                 return;
2416
2417         /* poll to verify queue is enabled */
2418         do {
2419                 usleep_range(1000, 2000);
2420                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2421         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2422         if (!wait_loop)
2423                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2424 }
2425
2426 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2427 {
2428         struct ixgbe_hw *hw = &adapter->hw;
2429         u32 rttdcs;
2430         u32 reg;
2431         u8 tcs = netdev_get_num_tc(adapter->netdev);
2432
2433         if (hw->mac.type == ixgbe_mac_82598EB)
2434                 return;
2435
2436         /* disable the arbiter while setting MTQC */
2437         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2438         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2439         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2440
2441         /* set transmit pool layout */
2442         switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2443         case (IXGBE_FLAG_SRIOV_ENABLED):
2444                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2445                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2446                 break;
2447         default:
2448                 if (!tcs)
2449                         reg = IXGBE_MTQC_64Q_1PB;
2450                 else if (tcs <= 4)
2451                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2452                 else
2453                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2454
2455                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2456
2457                 /* Enable Security TX Buffer IFG for multiple pb */
2458                 if (tcs) {
2459                         reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2460                         reg |= IXGBE_SECTX_DCB;
2461                         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2462                 }
2463                 break;
2464         }
2465
2466         /* re-enable the arbiter */
2467         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2468         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2469 }
2470
2471 /**
2472  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2473  * @adapter: board private structure
2474  *
2475  * Configure the Tx unit of the MAC after a reset.
2476  **/
2477 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2478 {
2479         struct ixgbe_hw *hw = &adapter->hw;
2480         u32 dmatxctl;
2481         u32 i;
2482
2483         ixgbe_setup_mtqc(adapter);
2484
2485         if (hw->mac.type != ixgbe_mac_82598EB) {
2486                 /* DMATXCTL.EN must be before Tx queues are enabled */
2487                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2488                 dmatxctl |= IXGBE_DMATXCTL_TE;
2489                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2490         }
2491
2492         /* Setup the HW Tx Head and Tail descriptor pointers */
2493         for (i = 0; i < adapter->num_tx_queues; i++)
2494                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2495 }
2496
2497 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2498
2499 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2500                                    struct ixgbe_ring *rx_ring)
2501 {
2502         u32 srrctl;
2503         u8 reg_idx = rx_ring->reg_idx;
2504
2505         switch (adapter->hw.mac.type) {
2506         case ixgbe_mac_82598EB: {
2507                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2508                 const int mask = feature[RING_F_RSS].mask;
2509                 reg_idx = reg_idx & mask;
2510         }
2511                 break;
2512         case ixgbe_mac_82599EB:
2513         case ixgbe_mac_X540:
2514         default:
2515                 break;
2516         }
2517
2518         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2519
2520         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2521         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2522         if (adapter->num_vfs)
2523                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2524
2525         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2526                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2527
2528         if (ring_is_ps_enabled(rx_ring)) {
2529 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2530                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2531 #else
2532                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2533 #endif
2534                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2535         } else {
2536                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2537                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2538                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2539         }
2540
2541         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2542 }
2543
2544 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2545 {
2546         struct ixgbe_hw *hw = &adapter->hw;
2547         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2548                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2549                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2550         u32 mrqc = 0, reta = 0;
2551         u32 rxcsum;
2552         int i, j;
2553         u8 tcs = netdev_get_num_tc(adapter->netdev);
2554         int maxq = adapter->ring_feature[RING_F_RSS].indices;
2555
2556         if (tcs)
2557                 maxq = min(maxq, adapter->num_tx_queues / tcs);
2558
2559         /* Fill out hash function seeds */
2560         for (i = 0; i < 10; i++)
2561                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2562
2563         /* Fill out redirection table */
2564         for (i = 0, j = 0; i < 128; i++, j++) {
2565                 if (j == maxq)
2566                         j = 0;
2567                 /* reta = 4-byte sliding window of
2568                  * 0x00..(indices-1)(indices-1)00..etc. */
2569                 reta = (reta << 8) | (j * 0x11);
2570                 if ((i & 3) == 3)
2571                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2572         }
2573
2574         /* Disable indicating checksum in descriptor, enables RSS hash */
2575         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2576         rxcsum |= IXGBE_RXCSUM_PCSD;
2577         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2578
2579         if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2580             (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2581                 mrqc = IXGBE_MRQC_RSSEN;
2582         } else {
2583                 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2584                                              | IXGBE_FLAG_SRIOV_ENABLED);
2585
2586                 switch (mask) {
2587                 case (IXGBE_FLAG_RSS_ENABLED):
2588                         if (!tcs)
2589                                 mrqc = IXGBE_MRQC_RSSEN;
2590                         else if (tcs <= 4)
2591                                 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2592                         else
2593                                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2594                         break;
2595                 case (IXGBE_FLAG_SRIOV_ENABLED):
2596                         mrqc = IXGBE_MRQC_VMDQEN;
2597                         break;
2598                 default:
2599                         break;
2600                 }
2601         }
2602
2603         /* Perform hash on these packet types */
2604         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2605               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2606               | IXGBE_MRQC_RSS_FIELD_IPV6
2607               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2608
2609         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2610 }
2611
2612 /**
2613  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2614  * @adapter:    address of board private structure
2615  * @index:      index of ring to set
2616  **/
2617 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2618                                    struct ixgbe_ring *ring)
2619 {
2620         struct ixgbe_hw *hw = &adapter->hw;
2621         u32 rscctrl;
2622         int rx_buf_len;
2623         u8 reg_idx = ring->reg_idx;
2624
2625         if (!ring_is_rsc_enabled(ring))
2626                 return;
2627
2628         rx_buf_len = ring->rx_buf_len;
2629         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2630         rscctrl |= IXGBE_RSCCTL_RSCEN;
2631         /*
2632          * we must limit the number of descriptors so that the
2633          * total size of max desc * buf_len is not greater
2634          * than 65535
2635          */
2636         if (ring_is_ps_enabled(ring)) {
2637 #if (MAX_SKB_FRAGS > 16)
2638                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2639 #elif (MAX_SKB_FRAGS > 8)
2640                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2641 #elif (MAX_SKB_FRAGS > 4)
2642                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2643 #else
2644                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2645 #endif
2646         } else {
2647                 if (rx_buf_len < IXGBE_RXBUFFER_4K)
2648                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2649                 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
2650                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2651                 else
2652                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2653         }
2654         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2655 }
2656
2657 /**
2658  *  ixgbe_set_uta - Set unicast filter table address
2659  *  @adapter: board private structure
2660  *
2661  *  The unicast table address is a register array of 32-bit registers.
2662  *  The table is meant to be used in a way similar to how the MTA is used
2663  *  however due to certain limitations in the hardware it is necessary to
2664  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2665  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2666  **/
2667 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2668 {
2669         struct ixgbe_hw *hw = &adapter->hw;
2670         int i;
2671
2672         /* The UTA table only exists on 82599 hardware and newer */
2673         if (hw->mac.type < ixgbe_mac_82599EB)
2674                 return;
2675
2676         /* we only need to do this if VMDq is enabled */
2677         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2678                 return;
2679
2680         for (i = 0; i < 128; i++)
2681                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2682 }
2683
2684 #define IXGBE_MAX_RX_DESC_POLL 10
2685 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2686                                        struct ixgbe_ring *ring)
2687 {
2688         struct ixgbe_hw *hw = &adapter->hw;
2689         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2690         u32 rxdctl;
2691         u8 reg_idx = ring->reg_idx;
2692
2693         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2694         if (hw->mac.type == ixgbe_mac_82598EB &&
2695             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2696                 return;
2697
2698         do {
2699                 usleep_range(1000, 2000);
2700                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2701         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2702
2703         if (!wait_loop) {
2704                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2705                       "the polling period\n", reg_idx);
2706         }
2707 }
2708
2709 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2710                             struct ixgbe_ring *ring)
2711 {
2712         struct ixgbe_hw *hw = &adapter->hw;
2713         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2714         u32 rxdctl;
2715         u8 reg_idx = ring->reg_idx;
2716
2717         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2718         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2719
2720         /* write value back with RXDCTL.ENABLE bit cleared */
2721         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2722
2723         if (hw->mac.type == ixgbe_mac_82598EB &&
2724             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2725                 return;
2726
2727         /* the hardware may take up to 100us to really disable the rx queue */
2728         do {
2729                 udelay(10);
2730                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2731         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2732
2733         if (!wait_loop) {
2734                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2735                       "the polling period\n", reg_idx);
2736         }
2737 }
2738
2739 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2740                              struct ixgbe_ring *ring)
2741 {
2742         struct ixgbe_hw *hw = &adapter->hw;
2743         u64 rdba = ring->dma;
2744         u32 rxdctl;
2745         u8 reg_idx = ring->reg_idx;
2746
2747         /* disable queue to avoid issues while updating state */
2748         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2749         ixgbe_disable_rx_queue(adapter, ring);
2750
2751         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2752         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2753         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2754                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2755         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2756         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2757         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2758
2759         ixgbe_configure_srrctl(adapter, ring);
2760         ixgbe_configure_rscctl(adapter, ring);
2761
2762         /* If operating in IOV mode set RLPML for X540 */
2763         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2764             hw->mac.type == ixgbe_mac_X540) {
2765                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2766                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2767                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2768         }
2769
2770         if (hw->mac.type == ixgbe_mac_82598EB) {
2771                 /*
2772                  * enable cache line friendly hardware writes:
2773                  * PTHRESH=32 descriptors (half the internal cache),
2774                  * this also removes ugly rx_no_buffer_count increment
2775                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2776                  * WTHRESH=8 burst writeback up to two cache lines
2777                  */
2778                 rxdctl &= ~0x3FFFFF;
2779                 rxdctl |=  0x080420;
2780         }
2781
2782         /* enable receive descriptor ring */
2783         rxdctl |= IXGBE_RXDCTL_ENABLE;
2784         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2785
2786         ixgbe_rx_desc_queue_enable(adapter, ring);
2787         ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
2788 }
2789
2790 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2791 {
2792         struct ixgbe_hw *hw = &adapter->hw;
2793         int p;
2794
2795         /* PSRTYPE must be initialized in non 82598 adapters */
2796         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2797                       IXGBE_PSRTYPE_UDPHDR |
2798                       IXGBE_PSRTYPE_IPV4HDR |
2799                       IXGBE_PSRTYPE_L2HDR |
2800                       IXGBE_PSRTYPE_IPV6HDR;
2801
2802         if (hw->mac.type == ixgbe_mac_82598EB)
2803                 return;
2804
2805         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2806                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2807
2808         for (p = 0; p < adapter->num_rx_pools; p++)
2809                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2810                                 psrtype);
2811 }
2812
2813 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2814 {
2815         struct ixgbe_hw *hw = &adapter->hw;
2816         u32 gcr_ext;
2817         u32 vt_reg_bits;
2818         u32 reg_offset, vf_shift;
2819         u32 vmdctl;
2820         int i;
2821
2822         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2823                 return;
2824
2825         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2826         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2827         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2828         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2829
2830         vf_shift = adapter->num_vfs % 32;
2831         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2832
2833         /* Enable only the PF's pool for Tx/Rx */
2834         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2835         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2836         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2837         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2838         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2839
2840         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2841         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2842
2843         /*
2844          * Set up VF register offsets for selected VT Mode,
2845          * i.e. 32 or 64 VFs for SR-IOV
2846          */
2847         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2848         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2849         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2850         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2851
2852         /* enable Tx loopback for VF/PF communication */
2853         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2854         /* Enable MAC Anti-Spoofing */
2855         hw->mac.ops.set_mac_anti_spoofing(hw,
2856                                            (adapter->num_vfs != 0),
2857                                           adapter->num_vfs);
2858         /* For VFs that have spoof checking turned off */
2859         for (i = 0; i < adapter->num_vfs; i++) {
2860                 if (!adapter->vfinfo[i].spoofchk_enabled)
2861                         ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
2862         }
2863 }
2864
2865 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2866 {
2867         struct ixgbe_hw *hw = &adapter->hw;
2868         struct net_device *netdev = adapter->netdev;
2869         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2870         int rx_buf_len;
2871         struct ixgbe_ring *rx_ring;
2872         int i;
2873         u32 mhadd, hlreg0;
2874
2875         /* Decide whether to use packet split mode or not */
2876         /* On by default */
2877         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2878
2879         /* Do not use packet split if we're in SR-IOV Mode */
2880         if (adapter->num_vfs)
2881                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2882
2883         /* Disable packet split due to 82599 erratum #45 */
2884         if (hw->mac.type == ixgbe_mac_82599EB)
2885                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2886
2887 #ifdef IXGBE_FCOE
2888         /* adjust max frame to be able to do baby jumbo for FCoE */
2889         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2890             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2891                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2892
2893 #endif /* IXGBE_FCOE */
2894         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2895         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2896                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2897                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2898
2899                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2900         }
2901
2902         /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2903         max_frame += VLAN_HLEN;
2904
2905         /* Set the RX buffer length according to the mode */
2906         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2907                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2908         } else {
2909                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2910                     (netdev->mtu <= ETH_DATA_LEN))
2911                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2912                 /*
2913                  * Make best use of allocation by using all but 1K of a
2914                  * power of 2 allocation that will be used for skb->head.
2915                  */
2916                 else if (max_frame <= IXGBE_RXBUFFER_3K)
2917                         rx_buf_len = IXGBE_RXBUFFER_3K;
2918                 else if (max_frame <= IXGBE_RXBUFFER_7K)
2919                         rx_buf_len = IXGBE_RXBUFFER_7K;
2920                 else if (max_frame <= IXGBE_RXBUFFER_15K)
2921                         rx_buf_len = IXGBE_RXBUFFER_15K;
2922                 else
2923                         rx_buf_len = IXGBE_MAX_RXBUFFER;
2924         }
2925
2926         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2927         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2928         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2929         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2930
2931         /*
2932          * Setup the HW Rx Head and Tail Descriptor Pointers and
2933          * the Base and Length of the Rx Descriptor Ring
2934          */
2935         for (i = 0; i < adapter->num_rx_queues; i++) {
2936                 rx_ring = adapter->rx_ring[i];
2937                 rx_ring->rx_buf_len = rx_buf_len;
2938
2939                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2940                         set_ring_ps_enabled(rx_ring);
2941                 else
2942                         clear_ring_ps_enabled(rx_ring);
2943
2944                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2945                         set_ring_rsc_enabled(rx_ring);
2946                 else
2947                         clear_ring_rsc_enabled(rx_ring);
2948
2949 #ifdef IXGBE_FCOE
2950                 if (netdev->features & NETIF_F_FCOE_MTU) {
2951                         struct ixgbe_ring_feature *f;
2952                         f = &adapter->ring_feature[RING_F_FCOE];
2953                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2954                                 clear_ring_ps_enabled(rx_ring);
2955                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2956                                         rx_ring->rx_buf_len =
2957                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2958                         } else if (!ring_is_rsc_enabled(rx_ring) &&
2959                                    !ring_is_ps_enabled(rx_ring)) {
2960                                 rx_ring->rx_buf_len =
2961                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2962                         }
2963                 }
2964 #endif /* IXGBE_FCOE */
2965         }
2966 }
2967
2968 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2969 {
2970         struct ixgbe_hw *hw = &adapter->hw;
2971         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2972
2973         switch (hw->mac.type) {
2974         case ixgbe_mac_82598EB:
2975                 /*
2976                  * For VMDq support of different descriptor types or
2977                  * buffer sizes through the use of multiple SRRCTL
2978                  * registers, RDRXCTL.MVMEN must be set to 1
2979                  *
2980                  * also, the manual doesn't mention it clearly but DCA hints
2981                  * will only use queue 0's tags unless this bit is set.  Side
2982                  * effects of setting this bit are only that SRRCTL must be
2983                  * fully programmed [0..15]
2984                  */
2985                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2986                 break;
2987         case ixgbe_mac_82599EB:
2988         case ixgbe_mac_X540:
2989                 /* Disable RSC for ACK packets */
2990                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2991                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2992                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2993                 /* hardware requires some bits to be set by default */
2994                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2995                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2996                 break;
2997         default:
2998                 /* We should do nothing since we don't know this hardware */
2999                 return;
3000         }
3001
3002         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3003 }
3004
3005 /**
3006  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3007  * @adapter: board private structure
3008  *
3009  * Configure the Rx unit of the MAC after a reset.
3010  **/
3011 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3012 {
3013         struct ixgbe_hw *hw = &adapter->hw;
3014         int i;
3015         u32 rxctrl;
3016
3017         /* disable receives while setting up the descriptors */
3018         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3019         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3020
3021         ixgbe_setup_psrtype(adapter);
3022         ixgbe_setup_rdrxctl(adapter);
3023
3024         /* Program registers for the distribution of queues */
3025         ixgbe_setup_mrqc(adapter);
3026
3027         ixgbe_set_uta(adapter);
3028
3029         /* set_rx_buffer_len must be called before ring initialization */
3030         ixgbe_set_rx_buffer_len(adapter);
3031
3032         /*
3033          * Setup the HW Rx Head and Tail Descriptor Pointers and
3034          * the Base and Length of the Rx Descriptor Ring
3035          */
3036         for (i = 0; i < adapter->num_rx_queues; i++)
3037                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3038
3039         /* disable drop enable for 82598 parts */
3040         if (hw->mac.type == ixgbe_mac_82598EB)
3041                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3042
3043         /* enable all receives */
3044         rxctrl |= IXGBE_RXCTRL_RXEN;
3045         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3046 }
3047
3048 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3049 {
3050         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3051         struct ixgbe_hw *hw = &adapter->hw;
3052         int pool_ndx = adapter->num_vfs;
3053
3054         /* add VID to filter table */
3055         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3056         set_bit(vid, adapter->active_vlans);
3057 }
3058
3059 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3060 {
3061         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3062         struct ixgbe_hw *hw = &adapter->hw;
3063         int pool_ndx = adapter->num_vfs;
3064
3065         /* remove VID from filter table */
3066         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3067         clear_bit(vid, adapter->active_vlans);
3068 }
3069
3070 /**
3071  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3072  * @adapter: driver data
3073  */
3074 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3075 {
3076         struct ixgbe_hw *hw = &adapter->hw;
3077         u32 vlnctrl;
3078
3079         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3080         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3081         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3082 }
3083
3084 /**
3085  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3086  * @adapter: driver data
3087  */
3088 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3089 {
3090         struct ixgbe_hw *hw = &adapter->hw;
3091         u32 vlnctrl;
3092
3093         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3094         vlnctrl |= IXGBE_VLNCTRL_VFE;
3095         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3096         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3097 }
3098
3099 /**
3100  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3101  * @adapter: driver data
3102  */
3103 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3104 {
3105         struct ixgbe_hw *hw = &adapter->hw;
3106         u32 vlnctrl;
3107         int i, j;
3108
3109         switch (hw->mac.type) {
3110         case ixgbe_mac_82598EB:
3111                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3112                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3113                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3114                 break;
3115         case ixgbe_mac_82599EB:
3116         case ixgbe_mac_X540:
3117                 for (i = 0; i < adapter->num_rx_queues; i++) {
3118                         j = adapter->rx_ring[i]->reg_idx;
3119                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3120                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3121                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3122                 }
3123                 break;
3124         default:
3125                 break;
3126         }
3127 }
3128
3129 /**
3130  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3131  * @adapter: driver data
3132  */
3133 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3134 {
3135         struct ixgbe_hw *hw = &adapter->hw;
3136         u32 vlnctrl;
3137         int i, j;
3138
3139         switch (hw->mac.type) {
3140         case ixgbe_mac_82598EB:
3141                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3142                 vlnctrl |= IXGBE_VLNCTRL_VME;
3143                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3144                 break;
3145         case ixgbe_mac_82599EB:
3146         case ixgbe_mac_X540:
3147                 for (i = 0; i < adapter->num_rx_queues; i++) {
3148                         j = adapter->rx_ring[i]->reg_idx;
3149                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3150                         vlnctrl |= IXGBE_RXDCTL_VME;
3151                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3152                 }
3153                 break;
3154         default:
3155                 break;
3156         }
3157 }
3158
3159 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3160 {
3161         u16 vid;
3162
3163         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3164
3165         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3166                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3167 }
3168
3169 /**
3170  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3171  * @netdev: network interface device structure
3172  *
3173  * Writes unicast address list to the RAR table.
3174  * Returns: -ENOMEM on failure/insufficient address space
3175  *                0 on no addresses written
3176  *                X on writing X addresses to the RAR table
3177  **/
3178 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3179 {
3180         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3181         struct ixgbe_hw *hw = &adapter->hw;
3182         unsigned int vfn = adapter->num_vfs;
3183         unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3184         int count = 0;
3185
3186         /* return ENOMEM indicating insufficient memory for addresses */
3187         if (netdev_uc_count(netdev) > rar_entries)
3188                 return -ENOMEM;
3189
3190         if (!netdev_uc_empty(netdev) && rar_entries) {
3191                 struct netdev_hw_addr *ha;
3192                 /* return error if we do not support writing to RAR table */
3193                 if (!hw->mac.ops.set_rar)
3194                         return -ENOMEM;
3195
3196                 netdev_for_each_uc_addr(ha, netdev) {
3197                         if (!rar_entries)
3198                                 break;
3199                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3200                                             vfn, IXGBE_RAH_AV);
3201                         count++;
3202                 }
3203         }
3204         /* write the addresses in reverse order to avoid write combining */
3205         for (; rar_entries > 0 ; rar_entries--)
3206                 hw->mac.ops.clear_rar(hw, rar_entries);
3207
3208         return count;
3209 }
3210
3211 /**
3212  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3213  * @netdev: network interface device structure
3214  *
3215  * The set_rx_method entry point is called whenever the unicast/multicast
3216  * address list or the network interface flags are updated.  This routine is
3217  * responsible for configuring the hardware for proper unicast, multicast and
3218  * promiscuous mode.
3219  **/
3220 void ixgbe_set_rx_mode(struct net_device *netdev)
3221 {
3222         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3223         struct ixgbe_hw *hw = &adapter->hw;
3224         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3225         int count;
3226
3227         /* Check for Promiscuous and All Multicast modes */
3228
3229         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3230
3231         /* set all bits that we expect to always be set */
3232         fctrl |= IXGBE_FCTRL_BAM;
3233         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3234         fctrl |= IXGBE_FCTRL_PMCF;
3235
3236         /* clear the bits we are changing the status of */
3237         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3238
3239         if (netdev->flags & IFF_PROMISC) {
3240                 hw->addr_ctrl.user_set_promisc = true;
3241                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3242                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3243                 /* don't hardware filter vlans in promisc mode */
3244                 ixgbe_vlan_filter_disable(adapter);
3245         } else {
3246                 if (netdev->flags & IFF_ALLMULTI) {
3247                         fctrl |= IXGBE_FCTRL_MPE;
3248                         vmolr |= IXGBE_VMOLR_MPE;
3249                 } else {
3250                         /*
3251                          * Write addresses to the MTA, if the attempt fails
3252                          * then we should just turn on promiscuous mode so
3253                          * that we can at least receive multicast traffic
3254                          */
3255                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3256                         vmolr |= IXGBE_VMOLR_ROMPE;
3257                 }
3258                 ixgbe_vlan_filter_enable(adapter);
3259                 hw->addr_ctrl.user_set_promisc = false;
3260                 /*
3261                  * Write addresses to available RAR registers, if there is not
3262                  * sufficient space to store all the addresses then enable
3263                  * unicast promiscuous mode
3264                  */
3265                 count = ixgbe_write_uc_addr_list(netdev);
3266                 if (count < 0) {
3267                         fctrl |= IXGBE_FCTRL_UPE;
3268                         vmolr |= IXGBE_VMOLR_ROPE;
3269                 }
3270         }
3271
3272         if (adapter->num_vfs) {
3273                 ixgbe_restore_vf_multicasts(adapter);
3274                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3275                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3276                            IXGBE_VMOLR_ROPE);
3277                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3278         }
3279
3280         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3281
3282         if (netdev->features & NETIF_F_HW_VLAN_RX)
3283                 ixgbe_vlan_strip_enable(adapter);
3284         else
3285                 ixgbe_vlan_strip_disable(adapter);
3286 }
3287
3288 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3289 {
3290         int q_idx;
3291         struct ixgbe_q_vector *q_vector;
3292         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3293
3294         /* legacy and MSI only use one vector */
3295         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3296                 q_vectors = 1;
3297
3298         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3299                 q_vector = adapter->q_vector[q_idx];
3300                 napi_enable(&q_vector->napi);
3301         }
3302 }
3303
3304 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3305 {
3306         int q_idx;
3307         struct ixgbe_q_vector *q_vector;
3308         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3309
3310         /* legacy and MSI only use one vector */
3311         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3312                 q_vectors = 1;
3313
3314         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3315                 q_vector = adapter->q_vector[q_idx];
3316                 napi_disable(&q_vector->napi);
3317         }
3318 }
3319
3320 #ifdef CONFIG_IXGBE_DCB
3321 /*
3322  * ixgbe_configure_dcb - Configure DCB hardware
3323  * @adapter: ixgbe adapter struct
3324  *
3325  * This is called by the driver on open to configure the DCB hardware.
3326  * This is also called by the gennetlink interface when reconfiguring
3327  * the DCB state.
3328  */
3329 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3330 {
3331         struct ixgbe_hw *hw = &adapter->hw;
3332         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3333
3334         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3335                 if (hw->mac.type == ixgbe_mac_82598EB)
3336                         netif_set_gso_max_size(adapter->netdev, 65536);
3337                 return;
3338         }
3339
3340         if (hw->mac.type == ixgbe_mac_82598EB)
3341                 netif_set_gso_max_size(adapter->netdev, 32768);
3342
3343
3344         /* Enable VLAN tag insert/strip */
3345         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3346
3347         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3348
3349 #ifdef IXGBE_FCOE
3350         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3351                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3352 #endif
3353
3354         /* reconfigure the hardware */
3355         if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3356                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3357                                                 DCB_TX_CONFIG);
3358                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3359                                                 DCB_RX_CONFIG);
3360                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3361         } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3362                 ixgbe_dcb_hw_ets(&adapter->hw,
3363                                  adapter->ixgbe_ieee_ets,
3364                                  max_frame);
3365                 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3366                                         adapter->ixgbe_ieee_pfc->pfc_en,
3367                                         adapter->ixgbe_ieee_ets->prio_tc);
3368         }
3369
3370         /* Enable RSS Hash per TC */
3371         if (hw->mac.type != ixgbe_mac_82598EB) {
3372                 int i;
3373                 u32 reg = 0;
3374
3375                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3376                         u8 msb = 0;
3377                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3378
3379                         while (cnt >>= 1)
3380                                 msb++;
3381
3382                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3383                 }
3384                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3385         }
3386 }
3387 #endif
3388
3389 /* Additional bittime to account for IXGBE framing */
3390 #define IXGBE_ETH_FRAMING 20
3391
3392 /*
3393  * ixgbe_hpbthresh - calculate high water mark for flow control
3394  *
3395  * @adapter: board private structure to calculate for
3396  * @pb - packet buffer to calculate
3397  */
3398 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3399 {
3400         struct ixgbe_hw *hw = &adapter->hw;
3401         struct net_device *dev = adapter->netdev;
3402         int link, tc, kb, marker;
3403         u32 dv_id, rx_pba;
3404
3405         /* Calculate max LAN frame size */
3406         tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3407
3408 #ifdef IXGBE_FCOE
3409         /* FCoE traffic class uses FCOE jumbo frames */
3410         if (dev->features & NETIF_F_FCOE_MTU) {
3411                 int fcoe_pb = 0;
3412
3413 #ifdef CONFIG_IXGBE_DCB
3414                 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3415
3416 #endif
3417                 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3418                         tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3419         }
3420 #endif
3421
3422         /* Calculate delay value for device */
3423         switch (hw->mac.type) {
3424         case ixgbe_mac_X540:
3425                 dv_id = IXGBE_DV_X540(link, tc);
3426                 break;
3427         default:
3428                 dv_id = IXGBE_DV(link, tc);
3429                 break;
3430         }
3431
3432         /* Loopback switch introduces additional latency */
3433         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3434                 dv_id += IXGBE_B2BT(tc);
3435
3436         /* Delay value is calculated in bit times convert to KB */
3437         kb = IXGBE_BT2KB(dv_id);
3438         rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3439
3440         marker = rx_pba - kb;
3441
3442         /* It is possible that the packet buffer is not large enough
3443          * to provide required headroom. In this case throw an error
3444          * to user and a do the best we can.
3445          */
3446         if (marker < 0) {
3447                 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3448                             "headroom to support flow control."
3449                             "Decrease MTU or number of traffic classes\n", pb);
3450                 marker = tc + 1;
3451         }
3452
3453         return marker;
3454 }
3455
3456 /*
3457  * ixgbe_lpbthresh - calculate low water mark for for flow control
3458  *
3459  * @adapter: board private structure to calculate for
3460  * @pb - packet buffer to calculate
3461  */
3462 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3463 {
3464         struct ixgbe_hw *hw = &adapter->hw;
3465         struct net_device *dev = adapter->netdev;
3466         int tc;
3467         u32 dv_id;
3468
3469         /* Calculate max LAN frame size */
3470         tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3471
3472         /* Calculate delay value for device */
3473         switch (hw->mac.type) {
3474         case ixgbe_mac_X540:
3475                 dv_id = IXGBE_LOW_DV_X540(tc);
3476                 break;
3477         default:
3478                 dv_id = IXGBE_LOW_DV(tc);
3479                 break;
3480         }
3481
3482         /* Delay value is calculated in bit times convert to KB */
3483         return IXGBE_BT2KB(dv_id);
3484 }
3485
3486 /*
3487  * ixgbe_pbthresh_setup - calculate and setup high low water marks
3488  */
3489 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3490 {
3491         struct ixgbe_hw *hw = &adapter->hw;
3492         int num_tc = netdev_get_num_tc(adapter->netdev);
3493         int i;
3494
3495         if (!num_tc)
3496                 num_tc = 1;
3497
3498         hw->fc.low_water = ixgbe_lpbthresh(adapter);
3499
3500         for (i = 0; i < num_tc; i++) {
3501                 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3502
3503                 /* Low water marks must not be larger than high water marks */
3504                 if (hw->fc.low_water > hw->fc.high_water[i])
3505                         hw->fc.low_water = 0;
3506         }
3507 }
3508
3509 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3510 {
3511         struct ixgbe_hw *hw = &adapter->hw;
3512         int hdrm;
3513         u8 tc = netdev_get_num_tc(adapter->netdev);
3514
3515         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3516             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3517                 hdrm = 32 << adapter->fdir_pballoc;
3518         else
3519                 hdrm = 0;
3520
3521         hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3522         ixgbe_pbthresh_setup(adapter);
3523 }
3524
3525 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3526 {
3527         struct ixgbe_hw *hw = &adapter->hw;
3528         struct hlist_node *node, *node2;
3529         struct ixgbe_fdir_filter *filter;
3530
3531         spin_lock(&adapter->fdir_perfect_lock);
3532
3533         if (!hlist_empty(&adapter->fdir_filter_list))
3534                 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3535
3536         hlist_for_each_entry_safe(filter, node, node2,
3537                                   &adapter->fdir_filter_list, fdir_node) {
3538                 ixgbe_fdir_write_perfect_filter_82599(hw,
3539                                 &filter->filter,
3540                                 filter->sw_idx,
3541                                 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3542                                 IXGBE_FDIR_DROP_QUEUE :
3543                                 adapter->rx_ring[filter->action]->reg_idx);
3544         }
3545
3546         spin_unlock(&adapter->fdir_perfect_lock);
3547 }
3548
3549 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3550 {
3551         ixgbe_configure_pb(adapter);
3552 #ifdef CONFIG_IXGBE_DCB
3553         ixgbe_configure_dcb(adapter);
3554 #endif
3555
3556         ixgbe_set_rx_mode(adapter->netdev);
3557         ixgbe_restore_vlan(adapter);
3558
3559 #ifdef IXGBE_FCOE
3560         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3561                 ixgbe_configure_fcoe(adapter);
3562
3563 #endif /* IXGBE_FCOE */
3564         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3565                 ixgbe_init_fdir_signature_82599(&adapter->hw,
3566                                                 adapter->fdir_pballoc);
3567         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3568                 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3569                                               adapter->fdir_pballoc);
3570                 ixgbe_fdir_filter_restore(adapter);
3571         }
3572
3573         ixgbe_configure_virtualization(adapter);
3574
3575         ixgbe_configure_tx(adapter);
3576         ixgbe_configure_rx(adapter);
3577 }
3578
3579 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3580 {
3581         switch (hw->phy.type) {
3582         case ixgbe_phy_sfp_avago:
3583         case ixgbe_phy_sfp_ftl:
3584         case ixgbe_phy_sfp_intel:
3585         case ixgbe_phy_sfp_unknown:
3586         case ixgbe_phy_sfp_passive_tyco:
3587         case ixgbe_phy_sfp_passive_unknown:
3588         case ixgbe_phy_sfp_active_unknown:
3589         case ixgbe_phy_sfp_ftl_active:
3590                 return true;
3591         case ixgbe_phy_nl:
3592                 if (hw->mac.type == ixgbe_mac_82598EB)
3593                         return true;
3594         default:
3595                 return false;
3596         }
3597 }
3598
3599 /**
3600  * ixgbe_sfp_link_config - set up SFP+ link
3601  * @adapter: pointer to private adapter struct
3602  **/
3603 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3604 {
3605         /*
3606          * We are assuming the worst case scenerio here, and that
3607          * is that an SFP was inserted/removed after the reset
3608          * but before SFP detection was enabled.  As such the best
3609          * solution is to just start searching as soon as we start
3610          */
3611         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3612                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3613
3614         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3615 }
3616
3617 /**
3618  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3619  * @hw: pointer to private hardware struct
3620  *
3621  * Returns 0 on success, negative on failure
3622  **/
3623 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3624 {
3625         u32 autoneg;
3626         bool negotiation, link_up = false;
3627         u32 ret = IXGBE_ERR_LINK_SETUP;
3628
3629         if (hw->mac.ops.check_link)
3630                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3631
3632         if (ret)
3633                 goto link_cfg_out;
3634
3635         autoneg = hw->phy.autoneg_advertised;
3636         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3637                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3638                                                         &negotiation);
3639         if (ret)
3640                 goto link_cfg_out;
3641
3642         if (hw->mac.ops.setup_link)
3643                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3644 link_cfg_out:
3645         return ret;
3646 }
3647
3648 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3649 {
3650         struct ixgbe_hw *hw = &adapter->hw;
3651         u32 gpie = 0;
3652
3653         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3654                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3655                        IXGBE_GPIE_OCD;
3656                 gpie |= IXGBE_GPIE_EIAME;
3657                 /*
3658                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3659                  * this saves a register write for every interrupt
3660                  */
3661                 switch (hw->mac.type) {
3662                 case ixgbe_mac_82598EB:
3663                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3664                         break;
3665                 case ixgbe_mac_82599EB:
3666                 case ixgbe_mac_X540:
3667                 default:
3668                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3669                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3670                         break;
3671                 }
3672         } else {
3673                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3674                  * specifically only auto mask tx and rx interrupts */
3675                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3676         }
3677
3678         /* XXX: to interrupt immediately for EICS writes, enable this */
3679         /* gpie |= IXGBE_GPIE_EIMEN; */
3680
3681         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3682                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3683                 gpie |= IXGBE_GPIE_VTMODE_64;
3684         }
3685
3686         /* Enable Thermal over heat sensor interrupt */
3687         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3688                 switch (adapter->hw.mac.type) {
3689                 case ixgbe_mac_82599EB:
3690                         gpie |= IXGBE_SDP0_GPIEN;
3691                         break;
3692                 case ixgbe_mac_X540:
3693                         gpie |= IXGBE_EIMS_TS;
3694                         break;
3695                 default:
3696                         break;
3697                 }
3698         }
3699
3700         /* Enable fan failure interrupt */
3701         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3702                 gpie |= IXGBE_SDP1_GPIEN;
3703
3704         if (hw->mac.type == ixgbe_mac_82599EB) {
3705                 gpie |= IXGBE_SDP1_GPIEN;
3706                 gpie |= IXGBE_SDP2_GPIEN;
3707         }
3708
3709         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3710 }
3711
3712 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3713 {
3714         struct ixgbe_hw *hw = &adapter->hw;
3715         int err;
3716         u32 ctrl_ext;
3717
3718         ixgbe_get_hw_control(adapter);
3719         ixgbe_setup_gpie(adapter);
3720
3721         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3722                 ixgbe_configure_msix(adapter);
3723         else
3724                 ixgbe_configure_msi_and_legacy(adapter);
3725
3726         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3727         if (hw->mac.ops.enable_tx_laser &&
3728             ((hw->phy.multispeed_fiber) ||
3729              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3730               (hw->mac.type == ixgbe_mac_82599EB))))
3731                 hw->mac.ops.enable_tx_laser(hw);
3732
3733         clear_bit(__IXGBE_DOWN, &adapter->state);
3734         ixgbe_napi_enable_all(adapter);
3735
3736         if (ixgbe_is_sfp(hw)) {
3737                 ixgbe_sfp_link_config(adapter);
3738         } else {
3739                 err = ixgbe_non_sfp_link_config(hw);
3740                 if (err)
3741                         e_err(probe, "link_config FAILED %d\n", err);
3742         }
3743
3744         /* clear any pending interrupts, may auto mask */
3745         IXGBE_READ_REG(hw, IXGBE_EICR);
3746         ixgbe_irq_enable(adapter, true, true);
3747
3748         /*
3749          * If this adapter has a fan, check to see if we had a failure
3750          * before we enabled the interrupt.
3751          */
3752         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3753                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3754                 if (esdp & IXGBE_ESDP_SDP1)
3755                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3756         }
3757
3758         /* enable transmits */
3759         netif_tx_start_all_queues(adapter->netdev);
3760
3761         /* bring the link up in the watchdog, this could race with our first
3762          * link up interrupt but shouldn't be a problem */
3763         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3764         adapter->link_check_timeout = jiffies;
3765         mod_timer(&adapter->service_timer, jiffies);
3766
3767         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3768         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3769         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3770         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3771 }
3772
3773 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3774 {
3775         WARN_ON(in_interrupt());
3776         /* put off any impending NetWatchDogTimeout */
3777         adapter->netdev->trans_start = jiffies;
3778
3779         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3780                 usleep_range(1000, 2000);
3781         ixgbe_down(adapter);
3782         /*
3783          * If SR-IOV enabled then wait a bit before bringing the adapter
3784          * back up to give the VFs time to respond to the reset.  The
3785          * two second wait is based upon the watchdog timer cycle in
3786          * the VF driver.
3787          */
3788         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3789                 msleep(2000);
3790         ixgbe_up(adapter);
3791         clear_bit(__IXGBE_RESETTING, &adapter->state);
3792 }
3793
3794 void ixgbe_up(struct ixgbe_adapter *adapter)
3795 {
3796         /* hardware has been reset, we need to reload some things */
3797         ixgbe_configure(adapter);
3798
3799         ixgbe_up_complete(adapter);
3800 }
3801
3802 void ixgbe_reset(struct ixgbe_adapter *adapter)
3803 {
3804         struct ixgbe_hw *hw = &adapter->hw;
3805         int err;
3806
3807         /* lock SFP init bit to prevent race conditions with the watchdog */
3808         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3809                 usleep_range(1000, 2000);
3810
3811         /* clear all SFP and link config related flags while holding SFP_INIT */
3812         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3813                              IXGBE_FLAG2_SFP_NEEDS_RESET);
3814         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3815
3816         err = hw->mac.ops.init_hw(hw);
3817         switch (err) {
3818         case 0:
3819         case IXGBE_ERR_SFP_NOT_PRESENT:
3820         case IXGBE_ERR_SFP_NOT_SUPPORTED:
3821                 break;
3822         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3823                 e_dev_err("master disable timed out\n");
3824                 break;
3825         case IXGBE_ERR_EEPROM_VERSION:
3826                 /* We are running on a pre-production device, log a warning */
3827                 e_dev_warn("This device is a pre-production adapter/LOM. "
3828                            "Please be aware there may be issuesassociated with "
3829                            "your hardware.  If you are experiencing problems "
3830                            "please contact your Intel or hardware "
3831                            "representative who provided you with this "
3832                            "hardware.\n");
3833                 break;
3834         default:
3835                 e_dev_err("Hardware Error: %d\n", err);
3836         }
3837
3838         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3839
3840         /* reprogram the RAR[0] in case user changed it. */
3841         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3842                             IXGBE_RAH_AV);
3843 }
3844
3845 /**
3846  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3847  * @rx_ring: ring to free buffers from
3848  **/
3849 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3850 {
3851         struct device *dev = rx_ring->dev;
3852         unsigned long size;
3853         u16 i;
3854
3855         /* ring already cleared, nothing to do */
3856         if (!rx_ring->rx_buffer_info)
3857                 return;
3858
3859         /* Free all the Rx ring sk_buffs */
3860         for (i = 0; i < rx_ring->count; i++) {
3861                 struct ixgbe_rx_buffer *rx_buffer_info;
3862
3863                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3864                 if (rx_buffer_info->dma) {
3865                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3866                                          rx_ring->rx_buf_len,
3867                                          DMA_FROM_DEVICE);
3868                         rx_buffer_info->dma = 0;
3869                 }
3870                 if (rx_buffer_info->skb) {
3871                         struct sk_buff *skb = rx_buffer_info->skb;
3872                         rx_buffer_info->skb = NULL;
3873                         do {
3874                                 struct sk_buff *this = skb;
3875                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3876                                         dma_unmap_single(dev,
3877                                                          IXGBE_RSC_CB(this)->dma,
3878                                                          rx_ring->rx_buf_len,
3879                                                          DMA_FROM_DEVICE);
3880                                         IXGBE_RSC_CB(this)->dma = 0;
3881                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3882                                 }
3883                                 skb = skb->prev;
3884                                 dev_kfree_skb(this);
3885                         } while (skb);
3886                 }
3887                 if (!rx_buffer_info->page)
3888                         continue;
3889                 if (rx_buffer_info->page_dma) {
3890                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3891                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3892                         rx_buffer_info->page_dma = 0;
3893                 }
3894                 put_page(rx_buffer_info->page);
3895                 rx_buffer_info->page = NULL;
3896                 rx_buffer_info->page_offset = 0;
3897         }
3898
3899         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3900         memset(rx_ring->rx_buffer_info, 0, size);
3901
3902         /* Zero out the descriptor ring */
3903         memset(rx_ring->desc, 0, rx_ring->size);
3904
3905         rx_ring->next_to_clean = 0;
3906         rx_ring->next_to_use = 0;
3907 }
3908
3909 /**
3910  * ixgbe_clean_tx_ring - Free Tx Buffers
3911  * @tx_ring: ring to be cleaned
3912  **/
3913 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3914 {
3915         struct ixgbe_tx_buffer *tx_buffer_info;
3916         unsigned long size;
3917         u16 i;
3918
3919         /* ring already cleared, nothing to do */
3920         if (!tx_ring->tx_buffer_info)
3921                 return;
3922
3923         /* Free all the Tx ring sk_buffs */
3924         for (i = 0; i < tx_ring->count; i++) {
3925                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3926                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3927         }
3928
3929         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3930         memset(tx_ring->tx_buffer_info, 0, size);
3931
3932         /* Zero out the descriptor ring */
3933         memset(tx_ring->desc, 0, tx_ring->size);
3934
3935         tx_ring->next_to_use = 0;
3936         tx_ring->next_to_clean = 0;
3937 }
3938
3939 /**
3940  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3941  * @adapter: board private structure
3942  **/
3943 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3944 {
3945         int i;
3946
3947         for (i = 0; i < adapter->num_rx_queues; i++)
3948                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3949 }
3950
3951 /**
3952  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3953  * @adapter: board private structure
3954  **/
3955 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3956 {
3957         int i;
3958
3959         for (i = 0; i < adapter->num_tx_queues; i++)
3960                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3961 }
3962
3963 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3964 {
3965         struct hlist_node *node, *node2;
3966         struct ixgbe_fdir_filter *filter;
3967
3968         spin_lock(&adapter->fdir_perfect_lock);
3969
3970         hlist_for_each_entry_safe(filter, node, node2,
3971                                   &adapter->fdir_filter_list, fdir_node) {
3972                 hlist_del(&filter->fdir_node);
3973                 kfree(filter);
3974         }
3975         adapter->fdir_filter_count = 0;
3976
3977         spin_unlock(&adapter->fdir_perfect_lock);
3978 }
3979
3980 void ixgbe_down(struct ixgbe_adapter *adapter)
3981 {
3982         struct net_device *netdev = adapter->netdev;
3983         struct ixgbe_hw *hw = &adapter->hw;
3984         u32 rxctrl;
3985         int i;
3986
3987         /* signal that we are down to the interrupt handler */
3988         set_bit(__IXGBE_DOWN, &adapter->state);
3989
3990         /* disable receives */
3991         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3992         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3993
3994         /* disable all enabled rx queues */
3995         for (i = 0; i < adapter->num_rx_queues; i++)
3996                 /* this call also flushes the previous write */
3997                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
3998
3999         usleep_range(10000, 20000);
4000
4001         netif_tx_stop_all_queues(netdev);
4002
4003         /* call carrier off first to avoid false dev_watchdog timeouts */
4004         netif_carrier_off(netdev);
4005         netif_tx_disable(netdev);
4006
4007         ixgbe_irq_disable(adapter);
4008
4009         ixgbe_napi_disable_all(adapter);
4010
4011         adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4012                              IXGBE_FLAG2_RESET_REQUESTED);
4013         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4014
4015         del_timer_sync(&adapter->service_timer);
4016
4017         if (adapter->num_vfs) {
4018                 /* Clear EITR Select mapping */
4019                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4020
4021                 /* Mark all the VFs as inactive */
4022                 for (i = 0 ; i < adapter->num_vfs; i++)
4023                         adapter->vfinfo[i].clear_to_send = 0;
4024
4025                 /* ping all the active vfs to let them know we are going down */
4026                 ixgbe_ping_all_vfs(adapter);
4027
4028                 /* Disable all VFTE/VFRE TX/RX */
4029                 ixgbe_disable_tx_rx(adapter);
4030         }
4031
4032         /* disable transmits in the hardware now that interrupts are off */
4033         for (i = 0; i < adapter->num_tx_queues; i++) {
4034                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4035                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4036         }
4037
4038         /* Disable the Tx DMA engine on 82599 and X540 */
4039         switch (hw->mac.type) {
4040         case ixgbe_mac_82599EB:
4041         case ixgbe_mac_X540:
4042                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4043                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4044                                  ~IXGBE_DMATXCTL_TE));
4045                 break;
4046         default:
4047                 break;
4048         }
4049
4050         if (!pci_channel_offline(adapter->pdev))
4051                 ixgbe_reset(adapter);
4052
4053         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4054         if (hw->mac.ops.disable_tx_laser &&
4055             ((hw->phy.multispeed_fiber) ||
4056              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4057               (hw->mac.type == ixgbe_mac_82599EB))))
4058                 hw->mac.ops.disable_tx_laser(hw);
4059
4060         ixgbe_clean_all_tx_rings(adapter);
4061         ixgbe_clean_all_rx_rings(adapter);
4062
4063 #ifdef CONFIG_IXGBE_DCA
4064         /* since we reset the hardware DCA settings were cleared */
4065         ixgbe_setup_dca(adapter);
4066 #endif
4067 }
4068
4069 /**
4070  * ixgbe_poll - NAPI Rx polling callback
4071  * @napi: structure for representing this polling device
4072  * @budget: how many packets driver is allowed to clean
4073  *
4074  * This function is used for legacy and MSI, NAPI mode
4075  **/
4076 static int ixgbe_poll(struct napi_struct *napi, int budget)
4077 {
4078         struct ixgbe_q_vector *q_vector =
4079                                 container_of(napi, struct ixgbe_q_vector, napi);
4080         struct ixgbe_adapter *adapter = q_vector->adapter;
4081         struct ixgbe_ring *ring;
4082         int per_ring_budget;
4083         bool clean_complete = true;
4084
4085 #ifdef CONFIG_IXGBE_DCA
4086         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4087                 ixgbe_update_dca(q_vector);
4088 #endif
4089
4090         for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4091                 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
4092
4093         /* attempt to distribute budget to each queue fairly, but don't allow
4094          * the budget to go below 1 because we'll exit polling */
4095         if (q_vector->rx.count > 1)
4096                 per_ring_budget = max(budget/q_vector->rx.count, 1);
4097         else
4098                 per_ring_budget = budget;
4099
4100         for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4101                 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4102                                                      per_ring_budget);
4103
4104         /* If all work not completed, return budget and keep polling */
4105         if (!clean_complete)
4106                 return budget;
4107
4108         /* all work done, exit the polling mode */
4109         napi_complete(napi);
4110         if (adapter->rx_itr_setting & 1)
4111                 ixgbe_set_itr(q_vector);
4112         if (!test_bit(__IXGBE_DOWN, &adapter->state))
4113                 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4114
4115         return 0;
4116 }
4117
4118 /**
4119  * ixgbe_tx_timeout - Respond to a Tx Hang
4120  * @netdev: network interface device structure
4121  **/
4122 static void ixgbe_tx_timeout(struct net_device *netdev)
4123 {
4124         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4125
4126         /* Do the reset outside of interrupt context */
4127         ixgbe_tx_timeout_reset(adapter);
4128 }
4129
4130 /**
4131  * ixgbe_set_rss_queues: Allocate queues for RSS
4132  * @adapter: board private structure to initialize
4133  *
4134  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4135  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4136  *
4137  **/
4138 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4139 {
4140         bool ret = false;
4141         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4142
4143         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4144                 f->mask = 0xF;
4145                 adapter->num_rx_queues = f->indices;
4146                 adapter->num_tx_queues = f->indices;
4147                 ret = true;
4148         } else {
4149                 ret = false;
4150         }
4151
4152         return ret;
4153 }
4154
4155 /**
4156  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4157  * @adapter: board private structure to initialize
4158  *
4159  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4160  * to the original CPU that initiated the Tx session.  This runs in addition
4161  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4162  * Rx load across CPUs using RSS.
4163  *
4164  **/
4165 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4166 {
4167         bool ret = false;
4168         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4169
4170         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4171         f_fdir->mask = 0;
4172
4173         /* Flow Director must have RSS enabled */
4174         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4175             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4176                 adapter->num_tx_queues = f_fdir->indices;
4177                 adapter->num_rx_queues = f_fdir->indices;
4178                 ret = true;
4179         } else {
4180                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4181         }
4182         return ret;
4183 }
4184
4185 #ifdef IXGBE_FCOE
4186 /**
4187  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4188  * @adapter: board private structure to initialize
4189  *
4190  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4191  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4192  * rx queues out of the max number of rx queues, instead, it is used as the
4193  * index of the first rx queue used by FCoE.
4194  *
4195  **/
4196 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4197 {
4198         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4199
4200         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4201                 return false;
4202
4203         f->indices = min((int)num_online_cpus(), f->indices);
4204
4205         adapter->num_rx_queues = 1;
4206         adapter->num_tx_queues = 1;
4207
4208         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4209                 e_info(probe, "FCoE enabled with RSS\n");
4210                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4211                         ixgbe_set_fdir_queues(adapter);
4212                 else
4213                         ixgbe_set_rss_queues(adapter);
4214         }
4215
4216         /* adding FCoE rx rings to the end */
4217         f->mask = adapter->num_rx_queues;
4218         adapter->num_rx_queues += f->indices;
4219         adapter->num_tx_queues += f->indices;
4220
4221         return true;
4222 }
4223 #endif /* IXGBE_FCOE */
4224
4225 /* Artificial max queue cap per traffic class in DCB mode */
4226 #define DCB_QUEUE_CAP 8
4227
4228 #ifdef CONFIG_IXGBE_DCB
4229 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4230 {
4231         int per_tc_q, q, i, offset = 0;
4232         struct net_device *dev = adapter->netdev;
4233         int tcs = netdev_get_num_tc(dev);
4234
4235         if (!tcs)
4236                 return false;
4237
4238         /* Map queue offset and counts onto allocated tx queues */
4239         per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4240         q = min((int)num_online_cpus(), per_tc_q);
4241
4242         for (i = 0; i < tcs; i++) {
4243                 netdev_set_tc_queue(dev, i, q, offset);
4244                 offset += q;
4245         }
4246
4247         adapter->num_tx_queues = q * tcs;
4248         adapter->num_rx_queues = q * tcs;
4249
4250 #ifdef IXGBE_FCOE
4251         /* FCoE enabled queues require special configuration indexed
4252          * by feature specific indices and mask. Here we map FCoE
4253          * indices onto the DCB queue pairs allowing FCoE to own
4254          * configuration later.
4255          */
4256         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4257                 int tc;
4258                 struct ixgbe_ring_feature *f =
4259                                         &adapter->ring_feature[RING_F_FCOE];
4260
4261                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4262                 f->indices = dev->tc_to_txq[tc].count;
4263                 f->mask = dev->tc_to_txq[tc].offset;
4264         }
4265 #endif
4266
4267         return true;
4268 }
4269 #endif
4270
4271 /**
4272  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4273  * @adapter: board private structure to initialize
4274  *
4275  * IOV doesn't actually use anything, so just NAK the
4276  * request for now and let the other queue routines
4277  * figure out what to do.
4278  */
4279 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4280 {
4281         return false;
4282 }
4283
4284 /*
4285  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4286  * @adapter: board private structure to initialize
4287  *
4288  * This is the top level queue allocation routine.  The order here is very
4289  * important, starting with the "most" number of features turned on at once,
4290  * and ending with the smallest set of features.  This way large combinations
4291  * can be allocated if they're turned on, and smaller combinations are the
4292  * fallthrough conditions.
4293  *
4294  **/
4295 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4296 {
4297         /* Start with base case */
4298         adapter->num_rx_queues = 1;
4299         adapter->num_tx_queues = 1;
4300         adapter->num_rx_pools = adapter->num_rx_queues;
4301         adapter->num_rx_queues_per_pool = 1;
4302
4303         if (ixgbe_set_sriov_queues(adapter))
4304                 goto done;
4305
4306 #ifdef CONFIG_IXGBE_DCB
4307         if (ixgbe_set_dcb_queues(adapter))
4308                 goto done;
4309
4310 #endif
4311 #ifdef IXGBE_FCOE
4312         if (ixgbe_set_fcoe_queues(adapter))
4313                 goto done;
4314
4315 #endif /* IXGBE_FCOE */
4316         if (ixgbe_set_fdir_queues(adapter))
4317                 goto done;
4318
4319         if (ixgbe_set_rss_queues(adapter))
4320                 goto done;
4321
4322         /* fallback to base case */
4323         adapter->num_rx_queues = 1;
4324         adapter->num_tx_queues = 1;
4325
4326 done:
4327         /* Notify the stack of the (possibly) reduced queue counts. */
4328         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4329         return netif_set_real_num_rx_queues(adapter->netdev,
4330                                             adapter->num_rx_queues);
4331 }
4332
4333 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4334                                        int vectors)
4335 {
4336         int err, vector_threshold;
4337
4338         /* We'll want at least 3 (vector_threshold):
4339          * 1) TxQ[0] Cleanup
4340          * 2) RxQ[0] Cleanup
4341          * 3) Other (Link Status Change, etc.)
4342          * 4) TCP Timer (optional)
4343          */
4344         vector_threshold = MIN_MSIX_COUNT;
4345
4346         /* The more we get, the more we will assign to Tx/Rx Cleanup
4347          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4348          * Right now, we simply care about how many we'll get; we'll
4349          * set them up later while requesting irq's.
4350          */
4351         while (vectors >= vector_threshold) {
4352                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4353                                       vectors);
4354                 if (!err) /* Success in acquiring all requested vectors. */
4355                         break;
4356                 else if (err < 0)
4357                         vectors = 0; /* Nasty failure, quit now */
4358                 else /* err == number of vectors we should try again with */
4359                         vectors = err;
4360         }
4361
4362         if (vectors < vector_threshold) {
4363                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4364                  * This just means we'll go with either a single MSI
4365                  * vector or fall back to legacy interrupts.
4366                  */
4367                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4368                              "Unable to allocate MSI-X interrupts\n");
4369                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4370                 kfree(adapter->msix_entries);
4371                 adapter->msix_entries = NULL;
4372         } else {
4373                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4374                 /*
4375                  * Adjust for only the vectors we'll use, which is minimum
4376                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4377                  * vectors we were allocated.
4378                  */
4379                 adapter->num_msix_vectors = min(vectors,
4380                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4381         }
4382 }
4383
4384 /**
4385  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4386  * @adapter: board private structure to initialize
4387  *
4388  * Cache the descriptor ring offsets for RSS to the assigned rings.
4389  *
4390  **/
4391 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4392 {
4393         int i;
4394
4395         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4396                 return false;
4397
4398         for (i = 0; i < adapter->num_rx_queues; i++)
4399                 adapter->rx_ring[i]->reg_idx = i;
4400         for (i = 0; i < adapter->num_tx_queues; i++)
4401                 adapter->tx_ring[i]->reg_idx = i;
4402
4403         return true;
4404 }
4405
4406 #ifdef CONFIG_IXGBE_DCB
4407
4408 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4409 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4410                                     unsigned int *tx, unsigned int *rx)
4411 {
4412         struct net_device *dev = adapter->netdev;
4413         struct ixgbe_hw *hw = &adapter->hw;
4414         u8 num_tcs = netdev_get_num_tc(dev);
4415
4416         *tx = 0;
4417         *rx = 0;
4418
4419         switch (hw->mac.type) {
4420         case ixgbe_mac_82598EB:
4421                 *tx = tc << 2;
4422                 *rx = tc << 3;
4423                 break;
4424         case ixgbe_mac_82599EB:
4425         case ixgbe_mac_X540:
4426                 if (num_tcs > 4) {
4427                         if (tc < 3) {
4428                                 *tx = tc << 5;
4429                                 *rx = tc << 4;
4430                         } else if (tc <  5) {
4431                                 *tx = ((tc + 2) << 4);
4432                                 *rx = tc << 4;
4433                         } else if (tc < num_tcs) {
4434                                 *tx = ((tc + 8) << 3);
4435                                 *rx = tc << 4;
4436                         }
4437                 } else {
4438                         *rx =  tc << 5;
4439                         switch (tc) {
4440                         case 0:
4441                                 *tx =  0;
4442                                 break;
4443                         case 1:
4444                                 *tx = 64;
4445                                 break;
4446                         case 2:
4447                                 *tx = 96;
4448                                 break;
4449                         case 3:
4450                                 *tx = 112;
4451                                 break;
4452                         default:
4453                                 break;
4454                         }
4455                 }
4456                 break;
4457         default:
4458                 break;
4459         }
4460 }
4461
4462 /**
4463  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4464  * @adapter: board private structure to initialize
4465  *
4466  * Cache the descriptor ring offsets for DCB to the assigned rings.
4467  *
4468  **/
4469 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4470 {
4471         struct net_device *dev = adapter->netdev;
4472         int i, j, k;
4473         u8 num_tcs = netdev_get_num_tc(dev);
4474
4475         if (!num_tcs)
4476                 return false;
4477
4478         for (i = 0, k = 0; i < num_tcs; i++) {
4479                 unsigned int tx_s, rx_s;
4480                 u16 count = dev->tc_to_txq[i].count;
4481
4482                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4483                 for (j = 0; j < count; j++, k++) {
4484                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4485                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4486                         adapter->tx_ring[k]->dcb_tc = i;
4487                         adapter->rx_ring[k]->dcb_tc = i;
4488                 }
4489         }
4490
4491         return true;
4492 }
4493 #endif
4494
4495 /**
4496  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4497  * @adapter: board private structure to initialize
4498  *
4499  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4500  *
4501  **/
4502 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4503 {
4504         int i;
4505         bool ret = false;
4506
4507         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4508             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4509                 for (i = 0; i < adapter->num_rx_queues; i++)
4510                         adapter->rx_ring[i]->reg_idx = i;
4511                 for (i = 0; i < adapter->num_tx_queues; i++)
4512                         adapter->tx_ring[i]->reg_idx = i;
4513                 ret = true;
4514         }
4515
4516         return ret;
4517 }
4518
4519 #ifdef IXGBE_FCOE
4520 /**
4521  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4522  * @adapter: board private structure to initialize
4523  *
4524  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4525  *
4526  */
4527 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4528 {
4529         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4530         int i;
4531         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4532
4533         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4534                 return false;
4535
4536         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4537                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4538                         ixgbe_cache_ring_fdir(adapter);
4539                 else
4540                         ixgbe_cache_ring_rss(adapter);
4541
4542                 fcoe_rx_i = f->mask;
4543                 fcoe_tx_i = f->mask;
4544         }
4545         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4546                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4547                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4548         }
4549         return true;
4550 }
4551
4552 #endif /* IXGBE_FCOE */
4553 /**
4554  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4555  * @adapter: board private structure to initialize
4556  *
4557  * SR-IOV doesn't use any descriptor rings but changes the default if
4558  * no other mapping is used.
4559  *
4560  */
4561 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4562 {
4563         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4564         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4565         if (adapter->num_vfs)
4566                 return true;
4567         else
4568                 return false;
4569 }
4570
4571 /**
4572  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4573  * @adapter: board private structure to initialize
4574  *
4575  * Once we know the feature-set enabled for the device, we'll cache
4576  * the register offset the descriptor ring is assigned to.
4577  *
4578  * Note, the order the various feature calls is important.  It must start with
4579  * the "most" features enabled at the same time, then trickle down to the
4580  * least amount of features turned on at once.
4581  **/
4582 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4583 {
4584         /* start with default case */
4585         adapter->rx_ring[0]->reg_idx = 0;
4586         adapter->tx_ring[0]->reg_idx = 0;
4587
4588         if (ixgbe_cache_ring_sriov(adapter))
4589                 return;
4590
4591 #ifdef CONFIG_IXGBE_DCB
4592         if (ixgbe_cache_ring_dcb(adapter))
4593                 return;
4594 #endif
4595
4596 #ifdef IXGBE_FCOE
4597         if (ixgbe_cache_ring_fcoe(adapter))
4598                 return;
4599 #endif /* IXGBE_FCOE */
4600
4601         if (ixgbe_cache_ring_fdir(adapter))
4602                 return;
4603
4604         if (ixgbe_cache_ring_rss(adapter))
4605                 return;
4606 }
4607
4608 /**
4609  * ixgbe_alloc_queues - Allocate memory for all rings
4610  * @adapter: board private structure to initialize
4611  *
4612  * We allocate one ring per queue at run-time since we don't know the
4613  * number of queues at compile-time.  The polling_netdev array is
4614  * intended for Multiqueue, but should work fine with a single queue.
4615  **/
4616 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4617 {
4618         int rx = 0, tx = 0, nid = adapter->node;
4619
4620         if (nid < 0 || !node_online(nid))
4621                 nid = first_online_node;
4622
4623         for (; tx < adapter->num_tx_queues; tx++) {
4624                 struct ixgbe_ring *ring;
4625
4626                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4627                 if (!ring)
4628                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4629                 if (!ring)
4630                         goto err_allocation;
4631                 ring->count = adapter->tx_ring_count;
4632                 ring->queue_index = tx;
4633                 ring->numa_node = nid;
4634                 ring->dev = &adapter->pdev->dev;
4635                 ring->netdev = adapter->netdev;
4636
4637                 adapter->tx_ring[tx] = ring;
4638         }
4639
4640         for (; rx < adapter->num_rx_queues; rx++) {
4641                 struct ixgbe_ring *ring;
4642
4643                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4644                 if (!ring)
4645                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4646                 if (!ring)
4647                         goto err_allocation;
4648                 ring->count = adapter->rx_ring_count;
4649                 ring->queue_index = rx;
4650                 ring->numa_node = nid;
4651                 ring->dev = &adapter->pdev->dev;
4652                 ring->netdev = adapter->netdev;
4653
4654                 adapter->rx_ring[rx] = ring;
4655         }
4656
4657         ixgbe_cache_ring_register(adapter);
4658
4659         return 0;
4660
4661 err_allocation:
4662         while (tx)
4663                 kfree(adapter->tx_ring[--tx]);
4664
4665         while (rx)
4666                 kfree(adapter->rx_ring[--rx]);
4667         return -ENOMEM;
4668 }
4669
4670 /**
4671  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4672  * @adapter: board private structure to initialize
4673  *
4674  * Attempt to configure the interrupts using the best available
4675  * capabilities of the hardware and the kernel.
4676  **/
4677 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4678 {
4679         struct ixgbe_hw *hw = &adapter->hw;
4680         int err = 0;
4681         int vector, v_budget;
4682
4683         /*
4684          * It's easy to be greedy for MSI-X vectors, but it really
4685          * doesn't do us much good if we have a lot more vectors
4686          * than CPU's.  So let's be conservative and only ask for
4687          * (roughly) the same number of vectors as there are CPU's.
4688          */
4689         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4690                        (int)num_online_cpus()) + NON_Q_VECTORS;
4691
4692         /*
4693          * At the same time, hardware can only support a maximum of
4694          * hw.mac->max_msix_vectors vectors.  With features
4695          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4696          * descriptor queues supported by our device.  Thus, we cap it off in
4697          * those rare cases where the cpu count also exceeds our vector limit.
4698          */
4699         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4700
4701         /* A failure in MSI-X entry allocation isn't fatal, but it does
4702          * mean we disable MSI-X capabilities of the adapter. */
4703         adapter->msix_entries = kcalloc(v_budget,
4704                                         sizeof(struct msix_entry), GFP_KERNEL);
4705         if (adapter->msix_entries) {
4706                 for (vector = 0; vector < v_budget; vector++)
4707                         adapter->msix_entries[vector].entry = vector;
4708
4709                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4710
4711                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4712                         goto out;
4713         }
4714
4715         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4716         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4717         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4718                 e_err(probe,
4719                       "ATR is not supported while multiple "
4720                       "queues are disabled.  Disabling Flow Director\n");
4721         }
4722         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4723         adapter->atr_sample_rate = 0;
4724         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4725                 ixgbe_disable_sriov(adapter);
4726
4727         err = ixgbe_set_num_queues(adapter);
4728         if (err)
4729                 return err;
4730
4731         err = pci_enable_msi(adapter->pdev);
4732         if (!err) {
4733                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4734         } else {
4735                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4736                              "Unable to allocate MSI interrupt, "
4737                              "falling back to legacy.  Error: %d\n", err);
4738                 /* reset err */
4739                 err = 0;
4740         }
4741
4742 out:
4743         return err;
4744 }
4745
4746 /**
4747  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4748  * @adapter: board private structure to initialize
4749  *
4750  * We allocate one q_vector per queue interrupt.  If allocation fails we
4751  * return -ENOMEM.
4752  **/
4753 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4754 {
4755         int v_idx, num_q_vectors;
4756         struct ixgbe_q_vector *q_vector;
4757
4758         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4759                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4760         else
4761                 num_q_vectors = 1;
4762
4763         for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4764                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4765                                         GFP_KERNEL, adapter->node);
4766                 if (!q_vector)
4767                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4768                                            GFP_KERNEL);
4769                 if (!q_vector)
4770                         goto err_out;
4771
4772                 q_vector->adapter = adapter;
4773                 q_vector->v_idx = v_idx;
4774
4775                 /* Allocate the affinity_hint cpumask, configure the mask */
4776                 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4777                         goto err_out;
4778                 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4779                 netif_napi_add(adapter->netdev, &q_vector->napi,
4780                                ixgbe_poll, 64);
4781                 adapter->q_vector[v_idx] = q_vector;
4782         }
4783
4784         return 0;
4785
4786 err_out:
4787         while (v_idx) {
4788                 v_idx--;
4789                 q_vector = adapter->q_vector[v_idx];
4790                 netif_napi_del(&q_vector->napi);
4791                 free_cpumask_var(q_vector->affinity_mask);
4792                 kfree(q_vector);
4793                 adapter->q_vector[v_idx] = NULL;
4794         }
4795         return -ENOMEM;
4796 }
4797
4798 /**
4799  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4800  * @adapter: board private structure to initialize
4801  *
4802  * This function frees the memory allocated to the q_vectors.  In addition if
4803  * NAPI is enabled it will delete any references to the NAPI struct prior
4804  * to freeing the q_vector.
4805  **/
4806 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4807 {
4808         int v_idx, num_q_vectors;
4809
4810         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4811                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4812         else
4813                 num_q_vectors = 1;
4814
4815         for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4816                 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4817                 adapter->q_vector[v_idx] = NULL;
4818                 netif_napi_del(&q_vector->napi);
4819                 free_cpumask_var(q_vector->affinity_mask);
4820                 kfree(q_vector);
4821         }
4822 }
4823
4824 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4825 {
4826         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4827                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4828                 pci_disable_msix(adapter->pdev);
4829                 kfree(adapter->msix_entries);
4830                 adapter->msix_entries = NULL;
4831         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4832                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4833                 pci_disable_msi(adapter->pdev);
4834         }
4835 }
4836
4837 /**
4838  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4839  * @adapter: board private structure to initialize
4840  *
4841  * We determine which interrupt scheme to use based on...
4842  * - Kernel support (MSI, MSI-X)
4843  *   - which can be user-defined (via MODULE_PARAM)
4844  * - Hardware queue count (num_*_queues)
4845  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4846  **/
4847 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4848 {
4849         int err;
4850
4851         /* Number of supported queues */
4852         err = ixgbe_set_num_queues(adapter);
4853         if (err)
4854                 return err;
4855
4856         err = ixgbe_set_interrupt_capability(adapter);
4857         if (err) {
4858                 e_dev_err("Unable to setup interrupt capabilities\n");
4859                 goto err_set_interrupt;
4860         }
4861
4862         err = ixgbe_alloc_q_vectors(adapter);
4863         if (err) {
4864                 e_dev_err("Unable to allocate memory for queue vectors\n");
4865                 goto err_alloc_q_vectors;
4866         }
4867
4868         err = ixgbe_alloc_queues(adapter);
4869         if (err) {
4870                 e_dev_err("Unable to allocate memory for queues\n");
4871                 goto err_alloc_queues;
4872         }
4873
4874         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4875                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4876                    adapter->num_rx_queues, adapter->num_tx_queues);
4877
4878         set_bit(__IXGBE_DOWN, &adapter->state);
4879
4880         return 0;
4881
4882 err_alloc_queues:
4883         ixgbe_free_q_vectors(adapter);
4884 err_alloc_q_vectors:
4885         ixgbe_reset_interrupt_capability(adapter);
4886 err_set_interrupt:
4887         return err;
4888 }
4889
4890 /**
4891  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4892  * @adapter: board private structure to clear interrupt scheme on
4893  *
4894  * We go through and clear interrupt specific resources and reset the structure
4895  * to pre-load conditions
4896  **/
4897 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4898 {
4899         int i;
4900
4901         for (i = 0; i < adapter->num_tx_queues; i++) {
4902                 kfree(adapter->tx_ring[i]);
4903                 adapter->tx_ring[i] = NULL;
4904         }
4905         for (i = 0; i < adapter->num_rx_queues; i++) {
4906                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4907
4908                 /* ixgbe_get_stats64() might access this ring, we must wait
4909                  * a grace period before freeing it.
4910                  */
4911                 kfree_rcu(ring, rcu);
4912                 adapter->rx_ring[i] = NULL;
4913         }
4914
4915         adapter->num_tx_queues = 0;
4916         adapter->num_rx_queues = 0;
4917
4918         ixgbe_free_q_vectors(adapter);
4919         ixgbe_reset_interrupt_capability(adapter);
4920 }
4921
4922 /**
4923  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4924  * @adapter: board private structure to initialize
4925  *
4926  * ixgbe_sw_init initializes the Adapter private data structure.
4927  * Fields are initialized based on PCI device information and
4928  * OS network device settings (MTU size).
4929  **/
4930 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4931 {
4932         struct ixgbe_hw *hw = &adapter->hw;
4933         struct pci_dev *pdev = adapter->pdev;
4934         unsigned int rss;
4935 #ifdef CONFIG_IXGBE_DCB
4936         int j;
4937         struct tc_configuration *tc;
4938 #endif
4939
4940         /* PCI config space info */
4941
4942         hw->vendor_id = pdev->vendor;
4943         hw->device_id = pdev->device;
4944         hw->revision_id = pdev->revision;
4945         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4946         hw->subsystem_device_id = pdev->subsystem_device;
4947
4948         /* Set capability flags */
4949         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4950         adapter->ring_feature[RING_F_RSS].indices = rss;
4951         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4952         switch (hw->mac.type) {
4953         case ixgbe_mac_82598EB:
4954                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4955                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4956                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4957                 break;
4958         case ixgbe_mac_X540:
4959                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4960         case ixgbe_mac_82599EB:
4961                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4962                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4963                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4964                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4965                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4966                 /* Flow Director hash filters enabled */
4967                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4968                 adapter->atr_sample_rate = 20;
4969                 adapter->ring_feature[RING_F_FDIR].indices =
4970                                                          IXGBE_MAX_FDIR_INDICES;
4971                 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4972 #ifdef IXGBE_FCOE
4973                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4974                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4975                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4976 #ifdef CONFIG_IXGBE_DCB
4977                 /* Default traffic class to use for FCoE */
4978                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4979 #endif
4980 #endif /* IXGBE_FCOE */
4981                 break;
4982         default:
4983                 break;
4984         }
4985
4986         /* n-tuple support exists, always init our spinlock */
4987         spin_lock_init(&adapter->fdir_perfect_lock);
4988
4989 #ifdef CONFIG_IXGBE_DCB
4990         switch (hw->mac.type) {
4991         case ixgbe_mac_X540:
4992                 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4993                 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4994                 break;
4995         default:
4996                 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4997                 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4998                 break;
4999         }
5000
5001         /* Configure DCB traffic classes */
5002         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5003                 tc = &adapter->dcb_cfg.tc_config[j];
5004                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5005                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5006                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5007                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5008                 tc->dcb_pfc = pfc_disabled;
5009         }
5010
5011         /* Initialize default user to priority mapping, UPx->TC0 */
5012         tc = &adapter->dcb_cfg.tc_config[0];
5013         tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5014         tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5015
5016         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5017         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5018         adapter->dcb_cfg.pfc_mode_enable = false;
5019         adapter->dcb_set_bitmap = 0x00;
5020         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5021         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5022                            MAX_TRAFFIC_CLASS);
5023
5024 #endif
5025
5026         /* default flow control settings */
5027         hw->fc.requested_mode = ixgbe_fc_full;
5028         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5029 #ifdef CONFIG_DCB
5030         adapter->last_lfc_mode = hw->fc.current_mode;
5031 #endif
5032         ixgbe_pbthresh_setup(adapter);
5033         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5034         hw->fc.send_xon = true;
5035         hw->fc.disable_fc_autoneg = false;
5036
5037         /* enable itr by default in dynamic mode */
5038         adapter->rx_itr_setting = 1;
5039         adapter->tx_itr_setting = 1;
5040
5041         /* set defaults for eitr in MegaBytes */
5042         adapter->eitr_low = 10;
5043         adapter->eitr_high = 20;
5044
5045         /* set default ring sizes */
5046         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5047         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5048
5049         /* set default work limits */
5050         adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5051
5052         /* initialize eeprom parameters */
5053         if (ixgbe_init_eeprom_params_generic(hw)) {
5054                 e_dev_err("EEPROM initialization failed\n");
5055                 return -EIO;
5056         }
5057
5058         /* enable rx csum by default */
5059         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5060
5061         /* get assigned NUMA node */
5062         adapter->node = dev_to_node(&pdev->dev);
5063
5064         set_bit(__IXGBE_DOWN, &adapter->state);
5065
5066         return 0;
5067 }
5068
5069 /**
5070  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5071  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5072  *
5073  * Return 0 on success, negative on failure
5074  **/
5075 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5076 {
5077         struct device *dev = tx_ring->dev;
5078         int size;
5079
5080         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5081         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5082         if (!tx_ring->tx_buffer_info)
5083                 tx_ring->tx_buffer_info = vzalloc(size);
5084         if (!tx_ring->tx_buffer_info)
5085                 goto err;
5086
5087         /* round up to nearest 4K */
5088         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5089         tx_ring->size = ALIGN(tx_ring->size, 4096);
5090
5091         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5092                                            &tx_ring->dma, GFP_KERNEL);
5093         if (!tx_ring->desc)
5094                 goto err;
5095
5096         tx_ring->next_to_use = 0;
5097         tx_ring->next_to_clean = 0;
5098         return 0;
5099
5100 err:
5101         vfree(tx_ring->tx_buffer_info);
5102         tx_ring->tx_buffer_info = NULL;
5103         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5104         return -ENOMEM;
5105 }
5106
5107 /**
5108  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5109  * @adapter: board private structure
5110  *
5111  * If this function returns with an error, then it's possible one or
5112  * more of the rings is populated (while the rest are not).  It is the
5113  * callers duty to clean those orphaned rings.
5114  *
5115  * Return 0 on success, negative on failure
5116  **/
5117 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5118 {
5119         int i, err = 0;
5120
5121         for (i = 0; i < adapter->num_tx_queues; i++) {
5122                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5123                 if (!err)
5124                         continue;
5125                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5126                 break;
5127         }
5128
5129         return err;
5130 }
5131
5132 /**
5133  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5134  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5135  *
5136  * Returns 0 on success, negative on failure
5137  **/
5138 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5139 {
5140         struct device *dev = rx_ring->dev;
5141         int size;
5142
5143         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5144         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5145         if (!rx_ring->rx_buffer_info)
5146                 rx_ring->rx_buffer_info = vzalloc(size);
5147         if (!rx_ring->rx_buffer_info)
5148                 goto err;
5149
5150         /* Round up to nearest 4K */
5151         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5152         rx_ring->size = ALIGN(rx_ring->size, 4096);
5153
5154         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5155                                            &rx_ring->dma, GFP_KERNEL);
5156
5157         if (!rx_ring->desc)
5158                 goto err;
5159
5160         rx_ring->next_to_clean = 0;
5161         rx_ring->next_to_use = 0;
5162
5163         return 0;
5164 err:
5165         vfree(rx_ring->rx_buffer_info);
5166         rx_ring->rx_buffer_info = NULL;
5167         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5168         return -ENOMEM;
5169 }
5170
5171 /**
5172  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5173  * @adapter: board private structure
5174  *
5175  * If this function returns with an error, then it's possible one or
5176  * more of the rings is populated (while the rest are not).  It is the
5177  * callers duty to clean those orphaned rings.
5178  *
5179  * Return 0 on success, negative on failure
5180  **/
5181 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5182 {
5183         int i, err = 0;
5184
5185         for (i = 0; i < adapter->num_rx_queues; i++) {
5186                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5187                 if (!err)
5188                         continue;
5189                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5190                 break;
5191         }
5192
5193         return err;
5194 }
5195
5196 /**
5197  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5198  * @tx_ring: Tx descriptor ring for a specific queue
5199  *
5200  * Free all transmit software resources
5201  **/
5202 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5203 {
5204         ixgbe_clean_tx_ring(tx_ring);
5205
5206         vfree(tx_ring->tx_buffer_info);
5207         tx_ring->tx_buffer_info = NULL;
5208
5209         /* if not set, then don't free */
5210         if (!tx_ring->desc)
5211                 return;
5212
5213         dma_free_coherent(tx_ring->dev, tx_ring->size,
5214                           tx_ring->desc, tx_ring->dma);
5215
5216         tx_ring->desc = NULL;
5217 }
5218
5219 /**
5220  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5221  * @adapter: board private structure
5222  *
5223  * Free all transmit software resources
5224  **/
5225 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5226 {
5227         int i;
5228
5229         for (i = 0; i < adapter->num_tx_queues; i++)
5230                 if (adapter->tx_ring[i]->desc)
5231                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5232 }
5233
5234 /**
5235  * ixgbe_free_rx_resources - Free Rx Resources
5236  * @rx_ring: ring to clean the resources from
5237  *
5238  * Free all receive software resources
5239  **/
5240 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5241 {
5242         ixgbe_clean_rx_ring(rx_ring);
5243
5244         vfree(rx_ring->rx_buffer_info);
5245         rx_ring->rx_buffer_info = NULL;
5246
5247         /* if not set, then don't free */
5248         if (!rx_ring->desc)
5249                 return;
5250
5251         dma_free_coherent(rx_ring->dev, rx_ring->size,
5252                           rx_ring->desc, rx_ring->dma);
5253
5254         rx_ring->desc = NULL;
5255 }
5256
5257 /**
5258  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5259  * @adapter: board private structure
5260  *
5261  * Free all receive software resources
5262  **/
5263 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5264 {
5265         int i;
5266
5267         for (i = 0; i < adapter->num_rx_queues; i++)
5268                 if (adapter->rx_ring[i]->desc)
5269                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5270 }
5271
5272 /**
5273  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5274  * @netdev: network interface device structure
5275  * @new_mtu: new value for maximum frame size
5276  *
5277  * Returns 0 on success, negative on failure
5278  **/
5279 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5280 {
5281         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5282         struct ixgbe_hw *hw = &adapter->hw;
5283         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5284
5285         /* MTU < 68 is an error and causes problems on some kernels */
5286         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5287             hw->mac.type != ixgbe_mac_X540) {
5288                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5289                         return -EINVAL;
5290         } else {
5291                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5292                         return -EINVAL;
5293         }
5294
5295         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5296         /* must set new MTU before calling down or up */
5297         netdev->mtu = new_mtu;
5298
5299         if (netif_running(netdev))
5300                 ixgbe_reinit_locked(adapter);
5301
5302         return 0;
5303 }
5304
5305 /**
5306  * ixgbe_open - Called when a network interface is made active
5307  * @netdev: network interface device structure
5308  *
5309  * Returns 0 on success, negative value on failure
5310  *
5311  * The open entry point is called when a network interface is made
5312  * active by the system (IFF_UP).  At this point all resources needed
5313  * for transmit and receive operations are allocated, the interrupt
5314  * handler is registered with the OS, the watchdog timer is started,
5315  * and the stack is notified that the interface is ready.
5316  **/
5317 static int ixgbe_open(struct net_device *netdev)
5318 {
5319         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5320         int err;
5321
5322         /* disallow open during test */
5323         if (test_bit(__IXGBE_TESTING, &adapter->state))
5324                 return -EBUSY;
5325
5326         netif_carrier_off(netdev);
5327
5328         /* allocate transmit descriptors */
5329         err = ixgbe_setup_all_tx_resources(adapter);
5330         if (err)
5331                 goto err_setup_tx;
5332
5333         /* allocate receive descriptors */
5334         err = ixgbe_setup_all_rx_resources(adapter);
5335         if (err)
5336                 goto err_setup_rx;
5337
5338         ixgbe_configure(adapter);
5339
5340         err = ixgbe_request_irq(adapter);
5341         if (err)
5342                 goto err_req_irq;
5343
5344         ixgbe_up_complete(adapter);
5345
5346         return 0;
5347
5348 err_req_irq:
5349 err_setup_rx:
5350         ixgbe_free_all_rx_resources(adapter);
5351 err_setup_tx:
5352         ixgbe_free_all_tx_resources(adapter);
5353         ixgbe_reset(adapter);
5354
5355         return err;
5356 }
5357
5358 /**
5359  * ixgbe_close - Disables a network interface
5360  * @netdev: network interface device structure
5361  *
5362  * Returns 0, this is not allowed to fail
5363  *
5364  * The close entry point is called when an interface is de-activated
5365  * by the OS.  The hardware is still under the drivers control, but
5366  * needs to be disabled.  A global MAC reset is issued to stop the
5367  * hardware, and all transmit and receive resources are freed.
5368  **/
5369 static int ixgbe_close(struct net_device *netdev)
5370 {
5371         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5372
5373         ixgbe_down(adapter);
5374         ixgbe_free_irq(adapter);
5375
5376         ixgbe_fdir_filter_exit(adapter);
5377
5378         ixgbe_free_all_tx_resources(adapter);
5379         ixgbe_free_all_rx_resources(adapter);
5380
5381         ixgbe_release_hw_control(adapter);
5382
5383         return 0;
5384 }
5385
5386 #ifdef CONFIG_PM
5387 static int ixgbe_resume(struct pci_dev *pdev)
5388 {
5389         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5390         struct net_device *netdev = adapter->netdev;
5391         u32 err;
5392
5393         pci_set_power_state(pdev, PCI_D0);
5394         pci_restore_state(pdev);
5395         /*
5396          * pci_restore_state clears dev->state_saved so call
5397          * pci_save_state to restore it.
5398          */
5399         pci_save_state(pdev);
5400
5401         err = pci_enable_device_mem(pdev);
5402         if (err) {
5403                 e_dev_err("Cannot enable PCI device from suspend\n");
5404                 return err;
5405         }
5406         pci_set_master(pdev);
5407
5408         pci_wake_from_d3(pdev, false);
5409
5410         err = ixgbe_init_interrupt_scheme(adapter);
5411         if (err) {
5412                 e_dev_err("Cannot initialize interrupts for device\n");
5413                 return err;
5414         }
5415
5416         ixgbe_reset(adapter);
5417
5418         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5419
5420         if (netif_running(netdev)) {
5421                 err = ixgbe_open(netdev);
5422                 if (err)
5423                         return err;
5424         }
5425
5426         netif_device_attach(netdev);
5427
5428         return 0;
5429 }
5430 #endif /* CONFIG_PM */
5431
5432 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5433 {
5434         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5435         struct net_device *netdev = adapter->netdev;
5436         struct ixgbe_hw *hw = &adapter->hw;
5437         u32 ctrl, fctrl;
5438         u32 wufc = adapter->wol;
5439 #ifdef CONFIG_PM
5440         int retval = 0;
5441 #endif
5442
5443         netif_device_detach(netdev);
5444
5445         if (netif_running(netdev)) {
5446                 ixgbe_down(adapter);
5447                 ixgbe_free_irq(adapter);
5448                 ixgbe_free_all_tx_resources(adapter);
5449                 ixgbe_free_all_rx_resources(adapter);
5450         }
5451
5452         ixgbe_clear_interrupt_scheme(adapter);
5453 #ifdef CONFIG_DCB
5454         kfree(adapter->ixgbe_ieee_pfc);
5455         kfree(adapter->ixgbe_ieee_ets);
5456 #endif
5457
5458 #ifdef CONFIG_PM
5459         retval = pci_save_state(pdev);
5460         if (retval)
5461                 return retval;
5462
5463 #endif
5464         if (wufc) {
5465                 ixgbe_set_rx_mode(netdev);
5466
5467                 /* turn on all-multi mode if wake on multicast is enabled */
5468                 if (wufc & IXGBE_WUFC_MC) {
5469                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5470                         fctrl |= IXGBE_FCTRL_MPE;
5471                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5472                 }
5473
5474                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5475                 ctrl |= IXGBE_CTRL_GIO_DIS;
5476                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5477
5478                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5479         } else {
5480                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5481                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5482         }
5483
5484         switch (hw->mac.type) {
5485         case ixgbe_mac_82598EB:
5486                 pci_wake_from_d3(pdev, false);
5487                 break;
5488         case ixgbe_mac_82599EB:
5489         case ixgbe_mac_X540:
5490                 pci_wake_from_d3(pdev, !!wufc);
5491                 break;
5492         default:
5493                 break;
5494         }
5495
5496         *enable_wake = !!wufc;
5497
5498         ixgbe_release_hw_control(adapter);
5499
5500         pci_disable_device(pdev);
5501
5502         return 0;
5503 }
5504
5505 #ifdef CONFIG_PM
5506 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5507 {
5508         int retval;
5509         bool wake;
5510
5511         retval = __ixgbe_shutdown(pdev, &wake);
5512         if (retval)
5513                 return retval;
5514
5515         if (wake) {
5516                 pci_prepare_to_sleep(pdev);
5517         } else {
5518                 pci_wake_from_d3(pdev, false);
5519                 pci_set_power_state(pdev, PCI_D3hot);
5520         }
5521
5522         return 0;
5523 }
5524 #endif /* CONFIG_PM */
5525
5526 static void ixgbe_shutdown(struct pci_dev *pdev)
5527 {
5528         bool wake;
5529
5530         __ixgbe_shutdown(pdev, &wake);
5531
5532         if (system_state == SYSTEM_POWER_OFF) {
5533                 pci_wake_from_d3(pdev, wake);
5534                 pci_set_power_state(pdev, PCI_D3hot);
5535         }
5536 }
5537
5538 /**
5539  * ixgbe_update_stats - Update the board statistics counters.
5540  * @adapter: board private structure
5541  **/
5542 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5543 {
5544         struct net_device *netdev = adapter->netdev;
5545         struct ixgbe_hw *hw = &adapter->hw;
5546         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5547         u64 total_mpc = 0;
5548         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5549         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5550         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5551         u64 bytes = 0, packets = 0;
5552 #ifdef IXGBE_FCOE
5553         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5554         unsigned int cpu;
5555         u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5556 #endif /* IXGBE_FCOE */
5557
5558         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5559             test_bit(__IXGBE_RESETTING, &adapter->state))
5560                 return;
5561
5562         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5563                 u64 rsc_count = 0;
5564                 u64 rsc_flush = 0;
5565                 for (i = 0; i < 16; i++)
5566                         adapter->hw_rx_no_dma_resources +=
5567                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5568                 for (i = 0; i < adapter->num_rx_queues; i++) {
5569                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5570                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5571                 }
5572                 adapter->rsc_total_count = rsc_count;
5573                 adapter->rsc_total_flush = rsc_flush;
5574         }
5575
5576         for (i = 0; i < adapter->num_rx_queues; i++) {
5577                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5578                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5579                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5580                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5581                 bytes += rx_ring->stats.bytes;
5582                 packets += rx_ring->stats.packets;
5583         }
5584         adapter->non_eop_descs = non_eop_descs;
5585         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5586         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5587         netdev->stats.rx_bytes = bytes;
5588         netdev->stats.rx_packets = packets;
5589
5590         bytes = 0;
5591         packets = 0;
5592         /* gather some stats to the adapter struct that are per queue */
5593         for (i = 0; i < adapter->num_tx_queues; i++) {
5594                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5595                 restart_queue += tx_ring->tx_stats.restart_queue;
5596                 tx_busy += tx_ring->tx_stats.tx_busy;
5597                 bytes += tx_ring->stats.bytes;
5598                 packets += tx_ring->stats.packets;
5599         }
5600         adapter->restart_queue = restart_queue;
5601         adapter->tx_busy = tx_busy;
5602         netdev->stats.tx_bytes = bytes;
5603         netdev->stats.tx_packets = packets;
5604
5605         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5606
5607         /* 8 register reads */
5608         for (i = 0; i < 8; i++) {
5609                 /* for packet buffers not used, the register should read 0 */
5610                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5611                 missed_rx += mpc;
5612                 hwstats->mpc[i] += mpc;
5613                 total_mpc += hwstats->mpc[i];
5614                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5615                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5616                 switch (hw->mac.type) {
5617                 case ixgbe_mac_82598EB:
5618                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5619                         hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5620                         hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5621                         hwstats->pxonrxc[i] +=
5622                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5623                         break;
5624                 case ixgbe_mac_82599EB:
5625                 case ixgbe_mac_X540:
5626                         hwstats->pxonrxc[i] +=
5627                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5628                         break;
5629                 default:
5630                         break;
5631                 }
5632         }
5633
5634         /*16 register reads */
5635         for (i = 0; i < 16; i++) {
5636                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5637                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5638                 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5639                     (hw->mac.type == ixgbe_mac_X540)) {
5640                         hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5641                         IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5642                         hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5643                         IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5644                 }
5645         }
5646
5647         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5648         /* work around hardware counting issue */
5649         hwstats->gprc -= missed_rx;
5650
5651         ixgbe_update_xoff_received(adapter);
5652
5653         /* 82598 hardware only has a 32 bit counter in the high register */
5654         switch (hw->mac.type) {
5655         case ixgbe_mac_82598EB:
5656                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5657                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5658                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5659                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5660                 break;
5661         case ixgbe_mac_X540:
5662                 /* OS2BMC stats are X540 only*/
5663                 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5664                 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5665                 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5666                 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5667         case ixgbe_mac_82599EB:
5668                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5669                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5670                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5671                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5672                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5673                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5674                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5675                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5676                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5677 #ifdef IXGBE_FCOE
5678                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5679                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5680                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5681                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5682                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5683                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5684                 /* Add up per cpu counters for total ddp aloc fail */
5685                 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5686                         for_each_possible_cpu(cpu) {
5687                                 fcoe_noddp_counts_sum +=
5688                                         *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5689                                 fcoe_noddp_ext_buff_counts_sum +=
5690                                         *per_cpu_ptr(fcoe->
5691                                                 pcpu_noddp_ext_buff, cpu);
5692                         }
5693                 }
5694                 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5695                 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
5696 #endif /* IXGBE_FCOE */
5697                 break;
5698         default:
5699                 break;
5700         }
5701         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5702         hwstats->bprc += bprc;
5703         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5704         if (hw->mac.type == ixgbe_mac_82598EB)
5705                 hwstats->mprc -= bprc;
5706         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5707         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5708         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5709         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5710         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5711         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5712         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5713         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5714         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5715         hwstats->lxontxc += lxon;
5716         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5717         hwstats->lxofftxc += lxoff;
5718         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5719         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5720         /*
5721          * 82598 errata - tx of flow control packets is included in tx counters
5722          */
5723         xon_off_tot = lxon + lxoff;
5724         hwstats->gptc -= xon_off_tot;
5725         hwstats->mptc -= xon_off_tot;
5726         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5727         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5728         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5729         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5730         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5731         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5732         hwstats->ptc64 -= xon_off_tot;
5733         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5734         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5735         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5736         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5737         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5738         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5739
5740         /* Fill out the OS statistics structure */
5741         netdev->stats.multicast = hwstats->mprc;
5742
5743         /* Rx Errors */
5744         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5745         netdev->stats.rx_dropped = 0;
5746         netdev->stats.rx_length_errors = hwstats->rlec;
5747         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5748         netdev->stats.rx_missed_errors = total_mpc;
5749 }
5750
5751 /**
5752  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5753  * @adapter - pointer to the device adapter structure
5754  **/
5755 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5756 {
5757         struct ixgbe_hw *hw = &adapter->hw;
5758         int i;
5759
5760         if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5761                 return;
5762
5763         adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5764
5765         /* if interface is down do nothing */
5766         if (test_bit(__IXGBE_DOWN, &adapter->state))
5767                 return;
5768
5769         /* do nothing if we are not using signature filters */
5770         if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5771                 return;
5772
5773         adapter->fdir_overflow++;
5774
5775         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5776                 for (i = 0; i < adapter->num_tx_queues; i++)
5777                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5778                                 &(adapter->tx_ring[i]->state));
5779                 /* re-enable flow director interrupts */
5780                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5781         } else {
5782                 e_err(probe, "failed to finish FDIR re-initialization, "
5783                       "ignored adding FDIR ATR filters\n");
5784         }
5785 }
5786
5787 /**
5788  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5789  * @adapter - pointer to the device adapter structure
5790  *
5791  * This function serves two purposes.  First it strobes the interrupt lines
5792  * in order to make certain interrupts are occuring.  Secondly it sets the
5793  * bits needed to check for TX hangs.  As a result we should immediately
5794  * determine if a hang has occured.
5795  */
5796 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5797 {
5798         struct ixgbe_hw *hw = &adapter->hw;
5799         u64 eics = 0;
5800         int i;
5801
5802         /* If we're down or resetting, just bail */
5803         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5804             test_bit(__IXGBE_RESETTING, &adapter->state))
5805                 return;
5806
5807         /* Force detection of hung controller */
5808         if (netif_carrier_ok(adapter->netdev)) {
5809                 for (i = 0; i < adapter->num_tx_queues; i++)
5810                         set_check_for_tx_hang(adapter->tx_ring[i]);
5811         }
5812
5813         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5814                 /*
5815                  * for legacy and MSI interrupts don't set any bits
5816                  * that are enabled for EIAM, because this operation
5817                  * would set *both* EIMS and EICS for any bit in EIAM
5818                  */
5819                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5820                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5821         } else {
5822                 /* get one bit for every active tx/rx interrupt vector */
5823                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5824                         struct ixgbe_q_vector *qv = adapter->q_vector[i];
5825                         if (qv->rx.ring || qv->tx.ring)
5826                                 eics |= ((u64)1 << i);
5827                 }
5828         }
5829
5830         /* Cause software interrupt to ensure rings are cleaned */
5831         ixgbe_irq_rearm_queues(adapter, eics);
5832
5833 }
5834
5835 /**
5836  * ixgbe_watchdog_update_link - update the link status
5837  * @adapter - pointer to the device adapter structure
5838  * @link_speed - pointer to a u32 to store the link_speed
5839  **/
5840 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5841 {
5842         struct ixgbe_hw *hw = &adapter->hw;
5843         u32 link_speed = adapter->link_speed;
5844         bool link_up = adapter->link_up;
5845         int i;
5846
5847         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5848                 return;
5849
5850         if (hw->mac.ops.check_link) {
5851                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5852         } else {
5853                 /* always assume link is up, if no check link function */
5854                 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5855                 link_up = true;
5856         }
5857         if (link_up) {
5858                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5859                         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5860                                 hw->mac.ops.fc_enable(hw, i);
5861                 } else {
5862                         hw->mac.ops.fc_enable(hw, 0);
5863                 }
5864         }
5865
5866         if (link_up ||
5867             time_after(jiffies, (adapter->link_check_timeout +
5868                                  IXGBE_TRY_LINK_TIMEOUT))) {
5869                 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5870                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5871                 IXGBE_WRITE_FLUSH(hw);
5872         }
5873
5874         adapter->link_up = link_up;
5875         adapter->link_speed = link_speed;
5876 }
5877
5878 /**
5879  * ixgbe_watchdog_link_is_up - update netif_carrier status and
5880  *                             print link up message
5881  * @adapter - pointer to the device adapter structure
5882  **/
5883 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5884 {
5885         struct net_device *netdev = adapter->netdev;
5886         struct ixgbe_hw *hw = &adapter->hw;
5887         u32 link_speed = adapter->link_speed;
5888         bool flow_rx, flow_tx;
5889
5890         /* only continue if link was previously down */
5891         if (netif_carrier_ok(netdev))
5892                 return;
5893
5894         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5895
5896         switch (hw->mac.type) {
5897         case ixgbe_mac_82598EB: {
5898                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5899                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5900                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5901                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5902         }
5903                 break;
5904         case ixgbe_mac_X540:
5905         case ixgbe_mac_82599EB: {
5906                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5907                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5908                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5909                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5910         }
5911                 break;
5912         default:
5913                 flow_tx = false;
5914                 flow_rx = false;
5915                 break;
5916         }
5917         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5918                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5919                "10 Gbps" :
5920                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5921                "1 Gbps" :
5922                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5923                "100 Mbps" :
5924                "unknown speed"))),
5925                ((flow_rx && flow_tx) ? "RX/TX" :
5926                (flow_rx ? "RX" :
5927                (flow_tx ? "TX" : "None"))));
5928
5929         netif_carrier_on(netdev);
5930         ixgbe_check_vf_rate_limit(adapter);
5931 }
5932
5933 /**
5934  * ixgbe_watchdog_link_is_down - update netif_carrier status and
5935  *                               print link down message
5936  * @adapter - pointer to the adapter structure
5937  **/
5938 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
5939 {
5940         struct net_device *netdev = adapter->netdev;
5941         struct ixgbe_hw *hw = &adapter->hw;
5942
5943         adapter->link_up = false;
5944         adapter->link_speed = 0;
5945
5946         /* only continue if link was up previously */
5947         if (!netif_carrier_ok(netdev))
5948                 return;
5949
5950         /* poll for SFP+ cable when link is down */
5951         if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5952                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5953
5954         e_info(drv, "NIC Link is Down\n");
5955         netif_carrier_off(netdev);
5956 }
5957
5958 /**
5959  * ixgbe_watchdog_flush_tx - flush queues on link down
5960  * @adapter - pointer to the device adapter structure
5961  **/
5962 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5963 {
5964         int i;
5965         int some_tx_pending = 0;
5966
5967         if (!netif_carrier_ok(adapter->netdev)) {
5968                 for (i = 0; i < adapter->num_tx_queues; i++) {
5969                         struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5970                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5971                                 some_tx_pending = 1;
5972                                 break;
5973                         }
5974                 }
5975
5976                 if (some_tx_pending) {
5977                         /* We've lost link, so the controller stops DMA,
5978                          * but we've got queued Tx work that's never going
5979                          * to get done, so reset controller to flush Tx.
5980                          * (Do the reset outside of interrupt context).
5981                          */
5982                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5983                 }
5984         }
5985 }
5986
5987 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5988 {
5989         u32 ssvpc;
5990
5991         /* Do not perform spoof check for 82598 */
5992         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5993                 return;
5994
5995         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5996
5997         /*
5998          * ssvpc register is cleared on read, if zero then no
5999          * spoofed packets in the last interval.
6000          */
6001         if (!ssvpc)
6002                 return;
6003
6004         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6005 }
6006
6007 /**
6008  * ixgbe_watchdog_subtask - check and bring link up
6009  * @adapter - pointer to the device adapter structure
6010  **/
6011 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6012 {
6013         /* if interface is down do nothing */
6014         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6015             test_bit(__IXGBE_RESETTING, &adapter->state))
6016                 return;
6017
6018         ixgbe_watchdog_update_link(adapter);
6019
6020         if (adapter->link_up)
6021                 ixgbe_watchdog_link_is_up(adapter);
6022         else
6023                 ixgbe_watchdog_link_is_down(adapter);
6024
6025         ixgbe_spoof_check(adapter);
6026         ixgbe_update_stats(adapter);
6027
6028         ixgbe_watchdog_flush_tx(adapter);
6029 }
6030
6031 /**
6032  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6033  * @adapter - the ixgbe adapter structure
6034  **/
6035 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6036 {
6037         struct ixgbe_hw *hw = &adapter->hw;
6038         s32 err;
6039
6040         /* not searching for SFP so there is nothing to do here */
6041         if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6042             !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6043                 return;
6044
6045         /* someone else is in init, wait until next service event */
6046         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6047                 return;
6048
6049         err = hw->phy.ops.identify_sfp(hw);
6050         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6051                 goto sfp_out;
6052
6053         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6054                 /* If no cable is present, then we need to reset
6055                  * the next time we find a good cable. */
6056                 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6057         }
6058
6059         /* exit on error */
6060         if (err)
6061                 goto sfp_out;
6062
6063         /* exit if reset not needed */
6064         if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6065                 goto sfp_out;
6066
6067         adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6068
6069         /*
6070          * A module may be identified correctly, but the EEPROM may not have
6071          * support for that module.  setup_sfp() will fail in that case, so
6072          * we should not allow that module to load.
6073          */
6074         if (hw->mac.type == ixgbe_mac_82598EB)
6075                 err = hw->phy.ops.reset(hw);
6076         else
6077                 err = hw->mac.ops.setup_sfp(hw);
6078
6079         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6080                 goto sfp_out;
6081
6082         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6083         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6084
6085 sfp_out:
6086         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6087
6088         if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6089             (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6090                 e_dev_err("failed to initialize because an unsupported "
6091                           "SFP+ module type was detected.\n");
6092                 e_dev_err("Reload the driver after installing a "
6093                           "supported module.\n");
6094                 unregister_netdev(adapter->netdev);
6095         }
6096 }
6097
6098 /**
6099  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6100  * @adapter - the ixgbe adapter structure
6101  **/
6102 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6103 {
6104         struct ixgbe_hw *hw = &adapter->hw;
6105         u32 autoneg;
6106         bool negotiation;
6107
6108         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6109                 return;
6110
6111         /* someone else is in init, wait until next service event */
6112         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6113                 return;
6114
6115         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6116
6117         autoneg = hw->phy.autoneg_advertised;
6118         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6119                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6120         if (hw->mac.ops.setup_link)
6121                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6122
6123         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6124         adapter->link_check_timeout = jiffies;
6125         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6126 }
6127
6128 #ifdef CONFIG_PCI_IOV
6129 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6130 {
6131         int vf;
6132         struct ixgbe_hw *hw = &adapter->hw;
6133         struct net_device *netdev = adapter->netdev;
6134         u32 gpc;
6135         u32 ciaa, ciad;
6136
6137         gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6138         if (gpc) /* If incrementing then no need for the check below */
6139                 return;
6140         /*
6141          * Check to see if a bad DMA write target from an errant or
6142          * malicious VF has caused a PCIe error.  If so then we can
6143          * issue a VFLR to the offending VF(s) and then resume without
6144          * requesting a full slot reset.
6145          */
6146
6147         for (vf = 0; vf < adapter->num_vfs; vf++) {
6148                 ciaa = (vf << 16) | 0x80000000;
6149                 /* 32 bit read so align, we really want status at offset 6 */
6150                 ciaa |= PCI_COMMAND;
6151                 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6152                 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6153                 ciaa &= 0x7FFFFFFF;
6154                 /* disable debug mode asap after reading data */
6155                 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6156                 /* Get the upper 16 bits which will be the PCI status reg */
6157                 ciad >>= 16;
6158                 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6159                         netdev_err(netdev, "VF %d Hung DMA\n", vf);
6160                         /* Issue VFLR */
6161                         ciaa = (vf << 16) | 0x80000000;
6162                         ciaa |= 0xA8;
6163                         IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6164                         ciad = 0x00008000;  /* VFLR */
6165                         IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6166                         ciaa &= 0x7FFFFFFF;
6167                         IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6168                 }
6169         }
6170 }
6171
6172 #endif
6173 /**
6174  * ixgbe_service_timer - Timer Call-back
6175  * @data: pointer to adapter cast into an unsigned long
6176  **/
6177 static void ixgbe_service_timer(unsigned long data)
6178 {
6179         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6180         unsigned long next_event_offset;
6181         bool ready = true;
6182
6183 #ifdef CONFIG_PCI_IOV
6184         ready = false;
6185
6186         /*
6187          * don't bother with SR-IOV VF DMA hang check if there are
6188          * no VFs or the link is down
6189          */
6190         if (!adapter->num_vfs ||
6191             (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6192                 ready = true;
6193                 goto normal_timer_service;
6194         }
6195
6196         /* If we have VFs allocated then we must check for DMA hangs */
6197         ixgbe_check_for_bad_vf(adapter);
6198         next_event_offset = HZ / 50;
6199         adapter->timer_event_accumulator++;
6200
6201         if (adapter->timer_event_accumulator >= 100) {
6202                 ready = true;
6203                 adapter->timer_event_accumulator = 0;
6204         }
6205
6206         goto schedule_event;
6207
6208 normal_timer_service:
6209 #endif
6210         /* poll faster when waiting for link */
6211         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6212                 next_event_offset = HZ / 10;
6213         else
6214                 next_event_offset = HZ * 2;
6215
6216 #ifdef CONFIG_PCI_IOV
6217 schedule_event:
6218 #endif
6219         /* Reset the timer */
6220         mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6221
6222         if (ready)
6223                 ixgbe_service_event_schedule(adapter);
6224 }
6225
6226 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6227 {
6228         if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6229                 return;
6230
6231         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6232
6233         /* If we're already down or resetting, just bail */
6234         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6235             test_bit(__IXGBE_RESETTING, &adapter->state))
6236                 return;
6237
6238         ixgbe_dump(adapter);
6239         netdev_err(adapter->netdev, "Reset adapter\n");
6240         adapter->tx_timeout_count++;
6241
6242         ixgbe_reinit_locked(adapter);
6243 }
6244
6245 /**
6246  * ixgbe_service_task - manages and runs subtasks
6247  * @work: pointer to work_struct containing our data
6248  **/
6249 static void ixgbe_service_task(struct work_struct *work)
6250 {
6251         struct ixgbe_adapter *adapter = container_of(work,
6252                                                      struct ixgbe_adapter,
6253                                                      service_task);
6254
6255         ixgbe_reset_subtask(adapter);
6256         ixgbe_sfp_detection_subtask(adapter);
6257         ixgbe_sfp_link_config_subtask(adapter);
6258         ixgbe_check_overtemp_subtask(adapter);
6259         ixgbe_watchdog_subtask(adapter);
6260         ixgbe_fdir_reinit_subtask(adapter);
6261         ixgbe_check_hang_subtask(adapter);
6262
6263         ixgbe_service_event_complete(adapter);
6264 }
6265
6266 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6267                        u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6268 {
6269         struct ixgbe_adv_tx_context_desc *context_desc;
6270         u16 i = tx_ring->next_to_use;
6271
6272         context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6273
6274         i++;
6275         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6276
6277         /* set bits to identify this as an advanced context descriptor */
6278         type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6279
6280         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
6281         context_desc->seqnum_seed       = cpu_to_le32(fcoe_sof_eof);
6282         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
6283         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
6284 }
6285
6286 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6287                      u32 tx_flags, __be16 protocol, u8 *hdr_len)
6288 {
6289         int err;
6290         u32 vlan_macip_lens, type_tucmd;
6291         u32 mss_l4len_idx, l4len;
6292
6293         if (!skb_is_gso(skb))
6294                 return 0;
6295
6296         if (skb_header_cloned(skb)) {
6297                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6298                 if (err)
6299                         return err;
6300         }
6301
6302         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6303         type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6304
6305         if (protocol == __constant_htons(ETH_P_IP)) {
6306                 struct iphdr *iph = ip_hdr(skb);
6307                 iph->tot_len = 0;
6308                 iph->check = 0;
6309                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6310                                                          iph->daddr, 0,
6311                                                          IPPROTO_TCP,
6312                                                          0);
6313                 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6314         } else if (skb_is_gso_v6(skb)) {
6315                 ipv6_hdr(skb)->payload_len = 0;
6316                 tcp_hdr(skb)->check =
6317                     ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6318                                      &ipv6_hdr(skb)->daddr,
6319                                      0, IPPROTO_TCP, 0);
6320         }
6321
6322         l4len = tcp_hdrlen(skb);
6323         *hdr_len = skb_transport_offset(skb) + l4len;
6324
6325         /* mss_l4len_id: use 1 as index for TSO */
6326         mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6327         mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6328         mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6329
6330         /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6331         vlan_macip_lens = skb_network_header_len(skb);
6332         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6333         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6334
6335         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6336                           mss_l4len_idx);
6337
6338         return 1;
6339 }
6340
6341 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6342                           struct sk_buff *skb, u32 tx_flags,
6343                           __be16 protocol)
6344 {
6345         u32 vlan_macip_lens = 0;
6346         u32 mss_l4len_idx = 0;
6347         u32 type_tucmd = 0;
6348
6349         if (skb->ip_summed != CHECKSUM_PARTIAL) {
6350             if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6351                 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
6352                         return false;
6353         } else {
6354                 u8 l4_hdr = 0;
6355                 switch (protocol) {
6356                 case __constant_htons(ETH_P_IP):
6357                         vlan_macip_lens |= skb_network_header_len(skb);
6358                         type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6359                         l4_hdr = ip_hdr(skb)->protocol;
6360                         break;
6361                 case __constant_htons(ETH_P_IPV6):
6362                         vlan_macip_lens |= skb_network_header_len(skb);
6363                         l4_hdr = ipv6_hdr(skb)->nexthdr;
6364                         break;
6365                 default:
6366                         if (unlikely(net_ratelimit())) {
6367                                 dev_warn(tx_ring->dev,
6368                                  "partial checksum but proto=%x!\n",
6369                                  skb->protocol);
6370                         }
6371                         break;
6372                 }
6373
6374                 switch (l4_hdr) {
6375                 case IPPROTO_TCP:
6376                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6377                         mss_l4len_idx = tcp_hdrlen(skb) <<
6378                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6379                         break;
6380                 case IPPROTO_SCTP:
6381                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6382                         mss_l4len_idx = sizeof(struct sctphdr) <<
6383                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6384                         break;
6385                 case IPPROTO_UDP:
6386                         mss_l4len_idx = sizeof(struct udphdr) <<
6387                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6388                         break;
6389                 default:
6390                         if (unlikely(net_ratelimit())) {
6391                                 dev_warn(tx_ring->dev,
6392                                  "partial checksum but l4 proto=%x!\n",
6393                                  skb->protocol);
6394                         }
6395                         break;
6396                 }
6397         }
6398
6399         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6400         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6401
6402         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6403                           type_tucmd, mss_l4len_idx);
6404
6405         return (skb->ip_summed == CHECKSUM_PARTIAL);
6406 }
6407
6408 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6409 {
6410         /* set type for advanced descriptor with frame checksum insertion */
6411         __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6412                                       IXGBE_ADVTXD_DCMD_IFCS |
6413                                       IXGBE_ADVTXD_DCMD_DEXT);
6414
6415         /* set HW vlan bit if vlan is present */
6416         if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6417                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6418
6419         /* set segmentation enable bits for TSO/FSO */
6420 #ifdef IXGBE_FCOE
6421         if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6422 #else
6423         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6424 #endif
6425                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6426
6427         return cmd_type;
6428 }
6429
6430 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6431 {
6432         __le32 olinfo_status =
6433                 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6434
6435         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6436                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6437                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6438                 /* enble IPv4 checksum for TSO */
6439                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6440                         olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6441         }
6442
6443         /* enable L4 checksum for TSO and TX checksum offload */
6444         if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6445                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6446
6447 #ifdef IXGBE_FCOE
6448         /* use index 1 context for FCOE/FSO */
6449         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6450                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6451                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6452
6453 #endif
6454         /*
6455          * Check Context must be set if Tx switch is enabled, which it
6456          * always is for case where virtual functions are running
6457          */
6458         if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6459                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6460
6461         return olinfo_status;
6462 }
6463
6464 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6465                        IXGBE_TXD_CMD_RS)
6466
6467 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6468                          struct sk_buff *skb,
6469                          struct ixgbe_tx_buffer *first,
6470                          u32 tx_flags,
6471                          const u8 hdr_len)
6472 {
6473         struct device *dev = tx_ring->dev;
6474         struct ixgbe_tx_buffer *tx_buffer_info;
6475         union ixgbe_adv_tx_desc *tx_desc;
6476         dma_addr_t dma;
6477         __le32 cmd_type, olinfo_status;
6478         struct skb_frag_struct *frag;
6479         unsigned int f = 0;
6480         unsigned int data_len = skb->data_len;
6481         unsigned int size = skb_headlen(skb);
6482         u32 offset = 0;
6483         u32 paylen = skb->len - hdr_len;
6484         u16 i = tx_ring->next_to_use;
6485         u16 gso_segs;
6486
6487 #ifdef IXGBE_FCOE
6488         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6489                 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6490                         data_len -= sizeof(struct fcoe_crc_eof);
6491                 } else {
6492                         size -= sizeof(struct fcoe_crc_eof) - data_len;
6493                         data_len = 0;
6494                 }
6495         }
6496
6497 #endif
6498         dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6499         if (dma_mapping_error(dev, dma))
6500                 goto dma_error;
6501
6502         cmd_type = ixgbe_tx_cmd_type(tx_flags);
6503         olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6504
6505         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6506
6507         for (;;) {
6508                 while (size > IXGBE_MAX_DATA_PER_TXD) {
6509                         tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6510                         tx_desc->read.cmd_type_len =
6511                                 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6512                         tx_desc->read.olinfo_status = olinfo_status;
6513
6514                         offset += IXGBE_MAX_DATA_PER_TXD;
6515                         size -= IXGBE_MAX_DATA_PER_TXD;
6516
6517                         tx_desc++;
6518                         i++;
6519                         if (i == tx_ring->count) {
6520                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6521                                 i = 0;
6522                         }
6523                 }
6524
6525                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6526                 tx_buffer_info->length = offset + size;
6527                 tx_buffer_info->tx_flags = tx_flags;
6528                 tx_buffer_info->dma = dma;
6529
6530                 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6531                 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6532                 tx_desc->read.olinfo_status = olinfo_status;
6533
6534                 if (!data_len)
6535                         break;
6536
6537                 frag = &skb_shinfo(skb)->frags[f];
6538 #ifdef IXGBE_FCOE
6539                 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6540 #else
6541                 size = skb_frag_size(frag);
6542 #endif
6543                 data_len -= size;
6544                 f++;
6545
6546                 offset = 0;
6547                 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6548
6549                 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
6550                 if (dma_mapping_error(dev, dma))
6551                         goto dma_error;
6552
6553                 tx_desc++;
6554                 i++;
6555                 if (i == tx_ring->count) {
6556                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6557                         i = 0;
6558                 }
6559         }
6560
6561         tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6562
6563         i++;
6564         if (i == tx_ring->count)
6565                 i = 0;
6566
6567         tx_ring->next_to_use = i;
6568
6569         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6570                 gso_segs = skb_shinfo(skb)->gso_segs;
6571 #ifdef IXGBE_FCOE
6572         /* adjust for FCoE Sequence Offload */
6573         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6574                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6575                                         skb_shinfo(skb)->gso_size);
6576 #endif /* IXGBE_FCOE */
6577         else
6578                 gso_segs = 1;
6579
6580         /* multiply data chunks by size of headers */
6581         tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6582         tx_buffer_info->gso_segs = gso_segs;
6583         tx_buffer_info->skb = skb;
6584
6585         /* set the timestamp */
6586         first->time_stamp = jiffies;
6587
6588         /*
6589          * Force memory writes to complete before letting h/w
6590          * know there are new descriptors to fetch.  (Only
6591          * applicable for weak-ordered memory model archs,
6592          * such as IA-64).
6593          */
6594         wmb();
6595
6596         /* set next_to_watch value indicating a packet is present */
6597         first->next_to_watch = tx_desc;
6598
6599         /* notify HW of packet */
6600         writel(i, tx_ring->tail);
6601
6602         return;
6603 dma_error:
6604         dev_err(dev, "TX DMA map failed\n");
6605
6606         /* clear dma mappings for failed tx_buffer_info map */
6607         for (;;) {
6608                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6609                 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6610                 if (tx_buffer_info == first)
6611                         break;
6612                 if (i == 0)
6613                         i = tx_ring->count;
6614                 i--;
6615         }
6616
6617         dev_kfree_skb_any(skb);
6618
6619         tx_ring->next_to_use = i;
6620 }
6621
6622 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6623                       u32 tx_flags, __be16 protocol)
6624 {
6625         struct ixgbe_q_vector *q_vector = ring->q_vector;
6626         union ixgbe_atr_hash_dword input = { .dword = 0 };
6627         union ixgbe_atr_hash_dword common = { .dword = 0 };
6628         union {
6629                 unsigned char *network;
6630                 struct iphdr *ipv4;
6631                 struct ipv6hdr *ipv6;
6632         } hdr;
6633         struct tcphdr *th;
6634         __be16 vlan_id;
6635
6636         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6637         if (!q_vector)
6638                 return;
6639
6640         /* do nothing if sampling is disabled */
6641         if (!ring->atr_sample_rate)
6642                 return;
6643
6644         ring->atr_count++;
6645
6646         /* snag network header to get L4 type and address */
6647         hdr.network = skb_network_header(skb);
6648
6649         /* Currently only IPv4/IPv6 with TCP is supported */
6650         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6651              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6652             (protocol != __constant_htons(ETH_P_IP) ||
6653              hdr.ipv4->protocol != IPPROTO_TCP))
6654                 return;
6655
6656         th = tcp_hdr(skb);
6657
6658         /* skip this packet since it is invalid or the socket is closing */
6659         if (!th || th->fin)
6660                 return;
6661
6662         /* sample on all syn packets or once every atr sample count */
6663         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6664                 return;
6665
6666         /* reset sample count */
6667         ring->atr_count = 0;
6668
6669         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6670
6671         /*
6672          * src and dst are inverted, think how the receiver sees them
6673          *
6674          * The input is broken into two sections, a non-compressed section
6675          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6676          * is XORed together and stored in the compressed dword.
6677          */
6678         input.formatted.vlan_id = vlan_id;
6679
6680         /*
6681          * since src port and flex bytes occupy the same word XOR them together
6682          * and write the value to source port portion of compressed dword
6683          */
6684         if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6685                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6686         else
6687                 common.port.src ^= th->dest ^ protocol;
6688         common.port.dst ^= th->source;
6689
6690         if (protocol == __constant_htons(ETH_P_IP)) {
6691                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6692                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6693         } else {
6694                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6695                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6696                              hdr.ipv6->saddr.s6_addr32[1] ^
6697                              hdr.ipv6->saddr.s6_addr32[2] ^
6698                              hdr.ipv6->saddr.s6_addr32[3] ^
6699                              hdr.ipv6->daddr.s6_addr32[0] ^
6700                              hdr.ipv6->daddr.s6_addr32[1] ^
6701                              hdr.ipv6->daddr.s6_addr32[2] ^
6702                              hdr.ipv6->daddr.s6_addr32[3];
6703         }
6704
6705         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6706         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6707                                               input, common, ring->queue_index);
6708 }
6709
6710 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6711 {
6712         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6713         /* Herbert's original patch had:
6714          *  smp_mb__after_netif_stop_queue();
6715          * but since that doesn't exist yet, just open code it. */
6716         smp_mb();
6717
6718         /* We need to check again in a case another CPU has just
6719          * made room available. */
6720         if (likely(ixgbe_desc_unused(tx_ring) < size))
6721                 return -EBUSY;
6722
6723         /* A reprieve! - use start_queue because it doesn't call schedule */
6724         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6725         ++tx_ring->tx_stats.restart_queue;
6726         return 0;
6727 }
6728
6729 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6730 {
6731         if (likely(ixgbe_desc_unused(tx_ring) >= size))
6732                 return 0;
6733         return __ixgbe_maybe_stop_tx(tx_ring, size);
6734 }
6735
6736 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6737 {
6738         struct ixgbe_adapter *adapter = netdev_priv(dev);
6739         int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6740                                                smp_processor_id();
6741 #ifdef IXGBE_FCOE
6742         __be16 protocol = vlan_get_protocol(skb);
6743
6744         if (((protocol == htons(ETH_P_FCOE)) ||
6745             (protocol == htons(ETH_P_FIP))) &&
6746             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6747                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6748                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6749                 return txq;
6750         }
6751 #endif
6752
6753         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6754                 while (unlikely(txq >= dev->real_num_tx_queues))
6755                         txq -= dev->real_num_tx_queues;
6756                 return txq;
6757         }
6758
6759         return skb_tx_hash(dev, skb);
6760 }
6761
6762 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6763                           struct ixgbe_adapter *adapter,
6764                           struct ixgbe_ring *tx_ring)
6765 {
6766         struct ixgbe_tx_buffer *first;
6767         int tso;
6768         u32 tx_flags = 0;
6769 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6770         unsigned short f;
6771 #endif
6772         u16 count = TXD_USE_COUNT(skb_headlen(skb));
6773         __be16 protocol = skb->protocol;
6774         u8 hdr_len = 0;
6775
6776         /*
6777          * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6778          *       + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6779          *       + 2 desc gap to keep tail from touching head,
6780          *       + 1 desc for context descriptor,
6781          * otherwise try next time
6782          */
6783 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6784         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6785                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6786 #else
6787         count += skb_shinfo(skb)->nr_frags;
6788 #endif
6789         if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6790                 tx_ring->tx_stats.tx_busy++;
6791                 return NETDEV_TX_BUSY;
6792         }
6793
6794 #ifdef CONFIG_PCI_IOV
6795         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6796                 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6797
6798 #endif
6799         /* if we have a HW VLAN tag being added default to the HW one */
6800         if (vlan_tx_tag_present(skb)) {
6801                 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6802                 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6803         /* else if it is a SW VLAN check the next protocol and store the tag */
6804         } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6805                 struct vlan_hdr *vhdr, _vhdr;
6806                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6807                 if (!vhdr)
6808                         goto out_drop;
6809
6810                 protocol = vhdr->h_vlan_encapsulated_proto;
6811                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6812                 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6813         }
6814
6815         /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6816         if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6817             ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6818              (skb->priority != TC_PRIO_CONTROL))) {
6819                 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6820                 tx_flags |= (skb->priority & 0x7) <<
6821                                         IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6822                 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6823                         struct vlan_ethhdr *vhdr;
6824                         if (skb_header_cloned(skb) &&
6825                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6826                                 goto out_drop;
6827                         vhdr = (struct vlan_ethhdr *)skb->data;
6828                         vhdr->h_vlan_TCI = htons(tx_flags >>
6829                                                  IXGBE_TX_FLAGS_VLAN_SHIFT);
6830                 } else {
6831                         tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6832                 }
6833         }
6834
6835         /* record the location of the first descriptor for this packet */
6836         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6837
6838 #ifdef IXGBE_FCOE
6839         /* setup tx offload for FCoE */
6840         if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6841             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6842                 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6843                 if (tso < 0)
6844                         goto out_drop;
6845                 else if (tso)
6846                         tx_flags |= IXGBE_TX_FLAGS_FSO |
6847                                     IXGBE_TX_FLAGS_FCOE;
6848                 else
6849                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6850
6851                 goto xmit_fcoe;
6852         }
6853
6854 #endif /* IXGBE_FCOE */
6855         /* setup IPv4/IPv6 offloads */
6856         if (protocol == __constant_htons(ETH_P_IP))
6857                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6858
6859         tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6860         if (tso < 0)
6861                 goto out_drop;
6862         else if (tso)
6863                 tx_flags |= IXGBE_TX_FLAGS_TSO;
6864         else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6865                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6866
6867         /* add the ATR filter if ATR is on */
6868         if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6869                 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6870
6871 #ifdef IXGBE_FCOE
6872 xmit_fcoe:
6873 #endif /* IXGBE_FCOE */
6874         ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6875
6876         ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6877
6878         return NETDEV_TX_OK;
6879
6880 out_drop:
6881         dev_kfree_skb_any(skb);
6882         return NETDEV_TX_OK;
6883 }
6884
6885 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6886 {
6887         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6888         struct ixgbe_ring *tx_ring;
6889
6890         tx_ring = adapter->tx_ring[skb->queue_mapping];
6891         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6892 }
6893
6894 /**
6895  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6896  * @netdev: network interface device structure
6897  * @p: pointer to an address structure
6898  *
6899  * Returns 0 on success, negative on failure
6900  **/
6901 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6902 {
6903         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6904         struct ixgbe_hw *hw = &adapter->hw;
6905         struct sockaddr *addr = p;
6906
6907         if (!is_valid_ether_addr(addr->sa_data))
6908                 return -EADDRNOTAVAIL;
6909
6910         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6911         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6912
6913         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6914                             IXGBE_RAH_AV);
6915
6916         return 0;
6917 }
6918
6919 static int
6920 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6921 {
6922         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6923         struct ixgbe_hw *hw = &adapter->hw;
6924         u16 value;
6925         int rc;
6926
6927         if (prtad != hw->phy.mdio.prtad)
6928                 return -EINVAL;
6929         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6930         if (!rc)
6931                 rc = value;
6932         return rc;
6933 }
6934
6935 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6936                             u16 addr, u16 value)
6937 {
6938         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6939         struct ixgbe_hw *hw = &adapter->hw;
6940
6941         if (prtad != hw->phy.mdio.prtad)
6942                 return -EINVAL;
6943         return hw->phy.ops.write_reg(hw, addr, devad, value);
6944 }
6945
6946 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6947 {
6948         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6949
6950         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6951 }
6952
6953 /**
6954  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6955  * netdev->dev_addrs
6956  * @netdev: network interface device structure
6957  *
6958  * Returns non-zero on failure
6959  **/
6960 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6961 {
6962         int err = 0;
6963         struct ixgbe_adapter *adapter = netdev_priv(dev);
6964         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6965
6966         if (is_valid_ether_addr(mac->san_addr)) {
6967                 rtnl_lock();
6968                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6969                 rtnl_unlock();
6970         }
6971         return err;
6972 }
6973
6974 /**
6975  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6976  * netdev->dev_addrs
6977  * @netdev: network interface device structure
6978  *
6979  * Returns non-zero on failure
6980  **/
6981 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6982 {
6983         int err = 0;
6984         struct ixgbe_adapter *adapter = netdev_priv(dev);
6985         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6986
6987         if (is_valid_ether_addr(mac->san_addr)) {
6988                 rtnl_lock();
6989                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6990                 rtnl_unlock();
6991         }
6992         return err;
6993 }
6994
6995 #ifdef CONFIG_NET_POLL_CONTROLLER
6996 /*
6997  * Polling 'interrupt' - used by things like netconsole to send skbs
6998  * without having to re-enable interrupts. It's not called while
6999  * the interrupt routine is executing.
7000  */
7001 static void ixgbe_netpoll(struct net_device *netdev)
7002 {
7003         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7004         int i;
7005
7006         /* if interface is down do nothing */
7007         if (test_bit(__IXGBE_DOWN, &adapter->state))
7008                 return;
7009
7010         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7011         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7012                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7013                 for (i = 0; i < num_q_vectors; i++) {
7014                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7015                         ixgbe_msix_clean_rings(0, q_vector);
7016                 }
7017         } else {
7018                 ixgbe_intr(adapter->pdev->irq, netdev);
7019         }
7020         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7021 }
7022 #endif
7023
7024 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7025                                                    struct rtnl_link_stats64 *stats)
7026 {
7027         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7028         int i;
7029
7030         rcu_read_lock();
7031         for (i = 0; i < adapter->num_rx_queues; i++) {
7032                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7033                 u64 bytes, packets;
7034                 unsigned int start;
7035
7036                 if (ring) {
7037                         do {
7038                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7039                                 packets = ring->stats.packets;
7040                                 bytes   = ring->stats.bytes;
7041                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7042                         stats->rx_packets += packets;
7043                         stats->rx_bytes   += bytes;
7044                 }
7045         }
7046
7047         for (i = 0; i < adapter->num_tx_queues; i++) {
7048                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7049                 u64 bytes, packets;
7050                 unsigned int start;
7051
7052                 if (ring) {
7053                         do {
7054                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7055                                 packets = ring->stats.packets;
7056                                 bytes   = ring->stats.bytes;
7057                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7058                         stats->tx_packets += packets;
7059                         stats->tx_bytes   += bytes;
7060                 }
7061         }
7062         rcu_read_unlock();
7063         /* following stats updated by ixgbe_watchdog_task() */
7064         stats->multicast        = netdev->stats.multicast;
7065         stats->rx_errors        = netdev->stats.rx_errors;
7066         stats->rx_length_errors = netdev->stats.rx_length_errors;
7067         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
7068         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7069         return stats;
7070 }
7071
7072 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7073  * #adapter: pointer to ixgbe_adapter
7074  * @tc: number of traffic classes currently enabled
7075  *
7076  * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7077  * 802.1Q priority maps to a packet buffer that exists.
7078  */
7079 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7080 {
7081         struct ixgbe_hw *hw = &adapter->hw;
7082         u32 reg, rsave;
7083         int i;
7084
7085         /* 82598 have a static priority to TC mapping that can not
7086          * be changed so no validation is needed.
7087          */
7088         if (hw->mac.type == ixgbe_mac_82598EB)
7089                 return;
7090
7091         reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7092         rsave = reg;
7093
7094         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7095                 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7096
7097                 /* If up2tc is out of bounds default to zero */
7098                 if (up2tc > tc)
7099                         reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7100         }
7101
7102         if (reg != rsave)
7103                 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7104
7105         return;
7106 }
7107
7108
7109 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7110  * classes.
7111  *
7112  * @netdev: net device to configure
7113  * @tc: number of traffic classes to enable
7114  */
7115 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7116 {
7117         struct ixgbe_adapter *adapter = netdev_priv(dev);
7118         struct ixgbe_hw *hw = &adapter->hw;
7119
7120         /* Multiple traffic classes requires multiple queues */
7121         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7122                 e_err(drv, "Enable failed, needs MSI-X\n");
7123                 return -EINVAL;
7124         }
7125
7126         /* Hardware supports up to 8 traffic classes */
7127         if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
7128             (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7129                 return -EINVAL;
7130
7131         /* Hardware has to reinitialize queues and interrupts to
7132          * match packet buffer alignment. Unfortunantly, the
7133          * hardware is not flexible enough to do this dynamically.
7134          */
7135         if (netif_running(dev))
7136                 ixgbe_close(dev);
7137         ixgbe_clear_interrupt_scheme(adapter);
7138
7139         if (tc) {
7140                 netdev_set_num_tc(dev, tc);
7141                 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7142
7143                 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7144                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7145
7146                 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7147                         adapter->hw.fc.requested_mode = ixgbe_fc_none;
7148         } else {
7149                 netdev_reset_tc(dev);
7150
7151                 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7152
7153                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7154                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7155
7156                 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7157                 adapter->dcb_cfg.pfc_mode_enable = false;
7158         }
7159
7160         ixgbe_init_interrupt_scheme(adapter);
7161         ixgbe_validate_rtr(adapter, tc);
7162         if (netif_running(dev))
7163                 ixgbe_open(dev);
7164
7165         return 0;
7166 }
7167
7168 void ixgbe_do_reset(struct net_device *netdev)
7169 {
7170         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7171
7172         if (netif_running(netdev))
7173                 ixgbe_reinit_locked(adapter);
7174         else
7175                 ixgbe_reset(adapter);
7176 }
7177
7178 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7179 {
7180         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7181
7182 #ifdef CONFIG_DCB
7183         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7184                 data &= ~NETIF_F_HW_VLAN_RX;
7185 #endif
7186
7187         /* return error if RXHASH is being enabled when RSS is not supported */
7188         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7189                 data &= ~NETIF_F_RXHASH;
7190
7191         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7192         if (!(data & NETIF_F_RXCSUM))
7193                 data &= ~NETIF_F_LRO;
7194
7195         /* Turn off LRO if not RSC capable or invalid ITR settings */
7196         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7197                 data &= ~NETIF_F_LRO;
7198         } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7199                    (adapter->rx_itr_setting != 1 &&
7200                     adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7201                 data &= ~NETIF_F_LRO;
7202                 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7203         }
7204
7205         return data;
7206 }
7207
7208 static int ixgbe_set_features(struct net_device *netdev, u32 data)
7209 {
7210         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7211         bool need_reset = false;
7212
7213         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7214         if (!(data & NETIF_F_RXCSUM))
7215                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7216         else
7217                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7218
7219         /* Make sure RSC matches LRO, reset if change */
7220         if (!!(data & NETIF_F_LRO) !=
7221              !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7222                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7223                 switch (adapter->hw.mac.type) {
7224                 case ixgbe_mac_X540:
7225                 case ixgbe_mac_82599EB:
7226                         need_reset = true;
7227                         break;
7228                 default:
7229                         break;
7230                 }
7231         }
7232
7233         /*
7234          * Check if Flow Director n-tuple support was enabled or disabled.  If
7235          * the state changed, we need to reset.
7236          */
7237         if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7238                 /* turn off ATR, enable perfect filters and reset */
7239                 if (data & NETIF_F_NTUPLE) {
7240                         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7241                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7242                         need_reset = true;
7243                 }
7244         } else if (!(data & NETIF_F_NTUPLE)) {
7245                 /* turn off Flow Director, set ATR and reset */
7246                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7247                 if ((adapter->flags &  IXGBE_FLAG_RSS_ENABLED) &&
7248                     !(adapter->flags &  IXGBE_FLAG_DCB_ENABLED))
7249                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7250                 need_reset = true;
7251         }
7252
7253         if (need_reset)
7254                 ixgbe_do_reset(netdev);
7255
7256         return 0;
7257
7258 }
7259
7260 static const struct net_device_ops ixgbe_netdev_ops = {
7261         .ndo_open               = ixgbe_open,
7262         .ndo_stop               = ixgbe_close,
7263         .ndo_start_xmit         = ixgbe_xmit_frame,
7264         .ndo_select_queue       = ixgbe_select_queue,
7265         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7266         .ndo_validate_addr      = eth_validate_addr,
7267         .ndo_set_mac_address    = ixgbe_set_mac,
7268         .ndo_change_mtu         = ixgbe_change_mtu,
7269         .ndo_tx_timeout         = ixgbe_tx_timeout,
7270         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7271         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7272         .ndo_do_ioctl           = ixgbe_ioctl,
7273         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7274         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7275         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7276         .ndo_set_vf_spoofchk    = ixgbe_ndo_set_vf_spoofchk,
7277         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7278         .ndo_get_stats64        = ixgbe_get_stats64,
7279         .ndo_setup_tc           = ixgbe_setup_tc,
7280 #ifdef CONFIG_NET_POLL_CONTROLLER
7281         .ndo_poll_controller    = ixgbe_netpoll,
7282 #endif
7283 #ifdef IXGBE_FCOE
7284         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7285         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7286         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7287         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7288         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7289         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7290 #endif /* IXGBE_FCOE */
7291         .ndo_set_features = ixgbe_set_features,
7292         .ndo_fix_features = ixgbe_fix_features,
7293 };
7294
7295 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7296                            const struct ixgbe_info *ii)
7297 {
7298 #ifdef CONFIG_PCI_IOV
7299         struct ixgbe_hw *hw = &adapter->hw;
7300
7301         if (hw->mac.type == ixgbe_mac_82598EB)
7302                 return;
7303
7304         /* The 82599 supports up to 64 VFs per physical function
7305          * but this implementation limits allocation to 63 so that
7306          * basic networking resources are still available to the
7307          * physical function
7308          */
7309         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7310         ixgbe_enable_sriov(adapter, ii);
7311 #endif /* CONFIG_PCI_IOV */
7312 }
7313
7314 /**
7315  * ixgbe_probe - Device Initialization Routine
7316  * @pdev: PCI device information struct
7317  * @ent: entry in ixgbe_pci_tbl
7318  *
7319  * Returns 0 on success, negative on failure
7320  *
7321  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7322  * The OS initialization, configuring of the adapter private structure,
7323  * and a hardware reset occur.
7324  **/
7325 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7326                                  const struct pci_device_id *ent)
7327 {
7328         struct net_device *netdev;
7329         struct ixgbe_adapter *adapter = NULL;
7330         struct ixgbe_hw *hw;
7331         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7332         static int cards_found;
7333         int i, err, pci_using_dac;
7334         u8 part_str[IXGBE_PBANUM_LENGTH];
7335         unsigned int indices = num_possible_cpus();
7336 #ifdef IXGBE_FCOE
7337         u16 device_caps;
7338 #endif
7339         u32 eec;
7340         u16 wol_cap;
7341
7342         /* Catch broken hardware that put the wrong VF device ID in
7343          * the PCIe SR-IOV capability.
7344          */
7345         if (pdev->is_virtfn) {
7346                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7347                      pci_name(pdev), pdev->vendor, pdev->device);
7348                 return -EINVAL;
7349         }
7350
7351         err = pci_enable_device_mem(pdev);
7352         if (err)
7353                 return err;
7354
7355         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7356             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7357                 pci_using_dac = 1;
7358         } else {
7359                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7360                 if (err) {
7361                         err = dma_set_coherent_mask(&pdev->dev,
7362                                                     DMA_BIT_MASK(32));
7363                         if (err) {
7364                                 dev_err(&pdev->dev,
7365                                         "No usable DMA configuration, aborting\n");
7366                                 goto err_dma;
7367                         }
7368                 }
7369                 pci_using_dac = 0;
7370         }
7371
7372         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7373                                            IORESOURCE_MEM), ixgbe_driver_name);
7374         if (err) {
7375                 dev_err(&pdev->dev,
7376                         "pci_request_selected_regions failed 0x%x\n", err);
7377                 goto err_pci_reg;
7378         }
7379
7380         pci_enable_pcie_error_reporting(pdev);
7381
7382         pci_set_master(pdev);
7383         pci_save_state(pdev);
7384
7385 #ifdef CONFIG_IXGBE_DCB
7386         indices *= MAX_TRAFFIC_CLASS;
7387 #endif
7388
7389         if (ii->mac == ixgbe_mac_82598EB)
7390                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7391         else
7392                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7393
7394 #ifdef IXGBE_FCOE
7395         indices += min_t(unsigned int, num_possible_cpus(),
7396                          IXGBE_MAX_FCOE_INDICES);
7397 #endif
7398         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7399         if (!netdev) {
7400                 err = -ENOMEM;
7401                 goto err_alloc_etherdev;
7402         }
7403
7404         SET_NETDEV_DEV(netdev, &pdev->dev);
7405
7406         adapter = netdev_priv(netdev);
7407         pci_set_drvdata(pdev, adapter);
7408
7409         adapter->netdev = netdev;
7410         adapter->pdev = pdev;
7411         hw = &adapter->hw;
7412         hw->back = adapter;
7413         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7414
7415         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7416                               pci_resource_len(pdev, 0));
7417         if (!hw->hw_addr) {
7418                 err = -EIO;
7419                 goto err_ioremap;
7420         }
7421
7422         for (i = 1; i <= 5; i++) {
7423                 if (pci_resource_len(pdev, i) == 0)
7424                         continue;
7425         }
7426
7427         netdev->netdev_ops = &ixgbe_netdev_ops;
7428         ixgbe_set_ethtool_ops(netdev);
7429         netdev->watchdog_timeo = 5 * HZ;
7430         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7431
7432         adapter->bd_number = cards_found;
7433
7434         /* Setup hw api */
7435         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7436         hw->mac.type  = ii->mac;
7437
7438         /* EEPROM */
7439         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7440         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7441         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7442         if (!(eec & (1 << 8)))
7443                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7444
7445         /* PHY */
7446         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7447         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7448         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7449         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7450         hw->phy.mdio.mmds = 0;
7451         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7452         hw->phy.mdio.dev = netdev;
7453         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7454         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7455
7456         ii->get_invariants(hw);
7457
7458         /* setup the private structure */
7459         err = ixgbe_sw_init(adapter);
7460         if (err)
7461                 goto err_sw_init;
7462
7463         /* Make it possible the adapter to be woken up via WOL */
7464         switch (adapter->hw.mac.type) {
7465         case ixgbe_mac_82599EB:
7466         case ixgbe_mac_X540:
7467                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7468                 break;
7469         default:
7470                 break;
7471         }
7472
7473         /*
7474          * If there is a fan on this device and it has failed log the
7475          * failure.
7476          */
7477         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7478                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7479                 if (esdp & IXGBE_ESDP_SDP1)
7480                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7481         }
7482
7483         /* reset_hw fills in the perm_addr as well */
7484         hw->phy.reset_if_overtemp = true;
7485         err = hw->mac.ops.reset_hw(hw);
7486         hw->phy.reset_if_overtemp = false;
7487         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7488             hw->mac.type == ixgbe_mac_82598EB) {
7489                 err = 0;
7490         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7491                 e_dev_err("failed to load because an unsupported SFP+ "
7492                           "module type was detected.\n");
7493                 e_dev_err("Reload the driver after installing a supported "
7494                           "module.\n");
7495                 goto err_sw_init;
7496         } else if (err) {
7497                 e_dev_err("HW Init failed: %d\n", err);
7498                 goto err_sw_init;
7499         }
7500
7501         ixgbe_probe_vf(adapter, ii);
7502
7503         netdev->features = NETIF_F_SG |
7504                            NETIF_F_IP_CSUM |
7505                            NETIF_F_IPV6_CSUM |
7506                            NETIF_F_HW_VLAN_TX |
7507                            NETIF_F_HW_VLAN_RX |
7508                            NETIF_F_HW_VLAN_FILTER |
7509                            NETIF_F_TSO |
7510                            NETIF_F_TSO6 |
7511                            NETIF_F_RXHASH |
7512                            NETIF_F_RXCSUM;
7513
7514         netdev->hw_features = netdev->features;
7515
7516         switch (adapter->hw.mac.type) {
7517         case ixgbe_mac_82599EB:
7518         case ixgbe_mac_X540:
7519                 netdev->features |= NETIF_F_SCTP_CSUM;
7520                 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7521                                        NETIF_F_NTUPLE;
7522                 break;
7523         default:
7524                 break;
7525         }
7526
7527         netdev->vlan_features |= NETIF_F_TSO;
7528         netdev->vlan_features |= NETIF_F_TSO6;
7529         netdev->vlan_features |= NETIF_F_IP_CSUM;
7530         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7531         netdev->vlan_features |= NETIF_F_SG;
7532
7533         netdev->priv_flags |= IFF_UNICAST_FLT;
7534
7535         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7536                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7537                                     IXGBE_FLAG_DCB_ENABLED);
7538
7539 #ifdef CONFIG_IXGBE_DCB
7540         netdev->dcbnl_ops = &dcbnl_ops;
7541 #endif
7542
7543 #ifdef IXGBE_FCOE
7544         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7545                 if (hw->mac.ops.get_device_caps) {
7546                         hw->mac.ops.get_device_caps(hw, &device_caps);
7547                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7548                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7549                 }
7550         }
7551         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7552                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7553                 netdev->vlan_features |= NETIF_F_FSO;
7554                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7555         }
7556 #endif /* IXGBE_FCOE */
7557         if (pci_using_dac) {
7558                 netdev->features |= NETIF_F_HIGHDMA;
7559                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7560         }
7561
7562         if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7563                 netdev->hw_features |= NETIF_F_LRO;
7564         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7565                 netdev->features |= NETIF_F_LRO;
7566
7567         /* make sure the EEPROM is good */
7568         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7569                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7570                 err = -EIO;
7571                 goto err_eeprom;
7572         }
7573
7574         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7575         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7576
7577         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7578                 e_dev_err("invalid MAC address\n");
7579                 err = -EIO;
7580                 goto err_eeprom;
7581         }
7582
7583         setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7584                     (unsigned long) adapter);
7585
7586         INIT_WORK(&adapter->service_task, ixgbe_service_task);
7587         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7588
7589         err = ixgbe_init_interrupt_scheme(adapter);
7590         if (err)
7591                 goto err_sw_init;
7592
7593         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7594                 netdev->hw_features &= ~NETIF_F_RXHASH;
7595                 netdev->features &= ~NETIF_F_RXHASH;
7596         }
7597
7598         /* WOL not supported for all but the following */
7599         adapter->wol = 0;
7600         switch (pdev->device) {
7601         case IXGBE_DEV_ID_82599_SFP:
7602                 /* Only this subdevice supports WOL */
7603                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7604                         adapter->wol = IXGBE_WUFC_MAG;
7605                 break;
7606         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7607                 /* All except this subdevice support WOL */
7608                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7609                         adapter->wol = IXGBE_WUFC_MAG;
7610                 break;
7611         case IXGBE_DEV_ID_82599_KX4:
7612                 adapter->wol = IXGBE_WUFC_MAG;
7613                 break;
7614         case IXGBE_DEV_ID_X540T:
7615                 /* Check eeprom to see if it is enabled */
7616                 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7617                 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7618
7619                 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7620                     ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7621                      (hw->bus.func == 0)))
7622                         adapter->wol = IXGBE_WUFC_MAG;
7623                 break;
7624         }
7625         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7626
7627         /* save off EEPROM version number */
7628         hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7629         hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7630
7631         /* pick up the PCI bus settings for reporting later */
7632         hw->mac.ops.get_bus_info(hw);
7633
7634         /* print bus type/speed/width info */
7635         e_dev_info("(PCI Express:%s:%s) %pM\n",
7636                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7637                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7638                     "Unknown"),
7639                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7640                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7641                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7642                     "Unknown"),
7643                    netdev->dev_addr);
7644
7645         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7646         if (err)
7647                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7648         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7649                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7650                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7651                            part_str);
7652         else
7653                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7654                            hw->mac.type, hw->phy.type, part_str);
7655
7656         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7657                 e_dev_warn("PCI-Express bandwidth available for this card is "
7658                            "not sufficient for optimal performance.\n");
7659                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7660                            "is required.\n");
7661         }
7662
7663         /* reset the hardware with the new settings */
7664         err = hw->mac.ops.start_hw(hw);
7665
7666         if (err == IXGBE_ERR_EEPROM_VERSION) {
7667                 /* We are running on a pre-production device, log a warning */
7668                 e_dev_warn("This device is a pre-production adapter/LOM. "
7669                            "Please be aware there may be issues associated "
7670                            "with your hardware.  If you are experiencing "
7671                            "problems please contact your Intel or hardware "
7672                            "representative who provided you with this "
7673                            "hardware.\n");
7674         }
7675         strcpy(netdev->name, "eth%d");
7676         err = register_netdev(netdev);
7677         if (err)
7678                 goto err_register;
7679
7680         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7681         if (hw->mac.ops.disable_tx_laser &&
7682             ((hw->phy.multispeed_fiber) ||
7683              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7684               (hw->mac.type == ixgbe_mac_82599EB))))
7685                 hw->mac.ops.disable_tx_laser(hw);
7686
7687         /* carrier off reporting is important to ethtool even BEFORE open */
7688         netif_carrier_off(netdev);
7689
7690 #ifdef CONFIG_IXGBE_DCA
7691         if (dca_add_requester(&pdev->dev) == 0) {
7692                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7693                 ixgbe_setup_dca(adapter);
7694         }
7695 #endif
7696         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7697                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7698                 for (i = 0; i < adapter->num_vfs; i++)
7699                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7700         }
7701
7702         /* firmware requires driver version to be 0xFFFFFFFF
7703          * since os does not support feature
7704          */
7705         if (hw->mac.ops.set_fw_drv_ver)
7706                 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7707                                            0xFF);
7708
7709         /* add san mac addr to netdev */
7710         ixgbe_add_sanmac_netdev(netdev);
7711
7712         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7713         cards_found++;
7714         return 0;
7715
7716 err_register:
7717         ixgbe_release_hw_control(adapter);
7718         ixgbe_clear_interrupt_scheme(adapter);
7719 err_sw_init:
7720 err_eeprom:
7721         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7722                 ixgbe_disable_sriov(adapter);
7723         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7724         iounmap(hw->hw_addr);
7725 err_ioremap:
7726         free_netdev(netdev);
7727 err_alloc_etherdev:
7728         pci_release_selected_regions(pdev,
7729                                      pci_select_bars(pdev, IORESOURCE_MEM));
7730 err_pci_reg:
7731 err_dma:
7732         pci_disable_device(pdev);
7733         return err;
7734 }
7735
7736 /**
7737  * ixgbe_remove - Device Removal Routine
7738  * @pdev: PCI device information struct
7739  *
7740  * ixgbe_remove is called by the PCI subsystem to alert the driver
7741  * that it should release a PCI device.  The could be caused by a
7742  * Hot-Plug event, or because the driver is going to be removed from
7743  * memory.
7744  **/
7745 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7746 {
7747         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7748         struct net_device *netdev = adapter->netdev;
7749
7750         set_bit(__IXGBE_DOWN, &adapter->state);
7751         cancel_work_sync(&adapter->service_task);
7752
7753 #ifdef CONFIG_IXGBE_DCA
7754         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7755                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7756                 dca_remove_requester(&pdev->dev);
7757                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7758         }
7759
7760 #endif
7761 #ifdef IXGBE_FCOE
7762         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7763                 ixgbe_cleanup_fcoe(adapter);
7764
7765 #endif /* IXGBE_FCOE */
7766
7767         /* remove the added san mac */
7768         ixgbe_del_sanmac_netdev(netdev);
7769
7770         if (netdev->reg_state == NETREG_REGISTERED)
7771                 unregister_netdev(netdev);
7772
7773         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7774                 if (!(ixgbe_check_vf_assignment(adapter)))
7775                         ixgbe_disable_sriov(adapter);
7776                 else
7777                         e_dev_warn("Unloading driver while VFs are assigned "
7778                                    "- VFs will not be deallocated\n");
7779         }
7780
7781         ixgbe_clear_interrupt_scheme(adapter);
7782
7783         ixgbe_release_hw_control(adapter);
7784
7785         iounmap(adapter->hw.hw_addr);
7786         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7787                                      IORESOURCE_MEM));
7788
7789         e_dev_info("complete\n");
7790
7791         free_netdev(netdev);
7792
7793         pci_disable_pcie_error_reporting(pdev);
7794
7795         pci_disable_device(pdev);
7796 }
7797
7798 /**
7799  * ixgbe_io_error_detected - called when PCI error is detected
7800  * @pdev: Pointer to PCI device
7801  * @state: The current pci connection state
7802  *
7803  * This function is called after a PCI bus error affecting
7804  * this device has been detected.
7805  */
7806 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7807                                                 pci_channel_state_t state)
7808 {
7809         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7810         struct net_device *netdev = adapter->netdev;
7811
7812 #ifdef CONFIG_PCI_IOV
7813         struct pci_dev *bdev, *vfdev;
7814         u32 dw0, dw1, dw2, dw3;
7815         int vf, pos;
7816         u16 req_id, pf_func;
7817
7818         if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7819             adapter->num_vfs == 0)
7820                 goto skip_bad_vf_detection;
7821
7822         bdev = pdev->bus->self;
7823         while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7824                 bdev = bdev->bus->self;
7825
7826         if (!bdev)
7827                 goto skip_bad_vf_detection;
7828
7829         pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7830         if (!pos)
7831                 goto skip_bad_vf_detection;
7832
7833         pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7834         pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7835         pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7836         pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7837
7838         req_id = dw1 >> 16;
7839         /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7840         if (!(req_id & 0x0080))
7841                 goto skip_bad_vf_detection;
7842
7843         pf_func = req_id & 0x01;
7844         if ((pf_func & 1) == (pdev->devfn & 1)) {
7845                 unsigned int device_id;
7846
7847                 vf = (req_id & 0x7F) >> 1;
7848                 e_dev_err("VF %d has caused a PCIe error\n", vf);
7849                 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7850                                 "%8.8x\tdw3: %8.8x\n",
7851                 dw0, dw1, dw2, dw3);
7852                 switch (adapter->hw.mac.type) {
7853                 case ixgbe_mac_82599EB:
7854                         device_id = IXGBE_82599_VF_DEVICE_ID;
7855                         break;
7856                 case ixgbe_mac_X540:
7857                         device_id = IXGBE_X540_VF_DEVICE_ID;
7858                         break;
7859                 default:
7860                         device_id = 0;
7861                         break;
7862                 }
7863
7864                 /* Find the pci device of the offending VF */
7865                 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7866                 while (vfdev) {
7867                         if (vfdev->devfn == (req_id & 0xFF))
7868                                 break;
7869                         vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7870                                                device_id, vfdev);
7871                 }
7872                 /*
7873                  * There's a slim chance the VF could have been hot plugged,
7874                  * so if it is no longer present we don't need to issue the
7875                  * VFLR.  Just clean up the AER in that case.
7876                  */
7877                 if (vfdev) {
7878                         e_dev_err("Issuing VFLR to VF %d\n", vf);
7879                         pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7880                 }
7881
7882                 pci_cleanup_aer_uncorrect_error_status(pdev);
7883         }
7884
7885         /*
7886          * Even though the error may have occurred on the other port
7887          * we still need to increment the vf error reference count for
7888          * both ports because the I/O resume function will be called
7889          * for both of them.
7890          */
7891         adapter->vferr_refcount++;
7892
7893         return PCI_ERS_RESULT_RECOVERED;
7894
7895 skip_bad_vf_detection:
7896 #endif /* CONFIG_PCI_IOV */
7897         netif_device_detach(netdev);
7898
7899         if (state == pci_channel_io_perm_failure)
7900                 return PCI_ERS_RESULT_DISCONNECT;
7901
7902         if (netif_running(netdev))
7903                 ixgbe_down(adapter);
7904         pci_disable_device(pdev);
7905
7906         /* Request a slot reset. */
7907         return PCI_ERS_RESULT_NEED_RESET;
7908 }
7909
7910 /**
7911  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7912  * @pdev: Pointer to PCI device
7913  *
7914  * Restart the card from scratch, as if from a cold-boot.
7915  */
7916 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7917 {
7918         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7919         pci_ers_result_t result;
7920         int err;
7921
7922         if (pci_enable_device_mem(pdev)) {
7923                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7924                 result = PCI_ERS_RESULT_DISCONNECT;
7925         } else {
7926                 pci_set_master(pdev);
7927                 pci_restore_state(pdev);
7928                 pci_save_state(pdev);
7929
7930                 pci_wake_from_d3(pdev, false);
7931
7932                 ixgbe_reset(adapter);
7933                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7934                 result = PCI_ERS_RESULT_RECOVERED;
7935         }
7936
7937         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7938         if (err) {
7939                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7940                           "failed 0x%0x\n", err);
7941                 /* non-fatal, continue */
7942         }
7943
7944         return result;
7945 }
7946
7947 /**
7948  * ixgbe_io_resume - called when traffic can start flowing again.
7949  * @pdev: Pointer to PCI device
7950  *
7951  * This callback is called when the error recovery driver tells us that
7952  * its OK to resume normal operation.
7953  */
7954 static void ixgbe_io_resume(struct pci_dev *pdev)
7955 {
7956         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7957         struct net_device *netdev = adapter->netdev;
7958
7959 #ifdef CONFIG_PCI_IOV
7960         if (adapter->vferr_refcount) {
7961                 e_info(drv, "Resuming after VF err\n");
7962                 adapter->vferr_refcount--;
7963                 return;
7964         }
7965
7966 #endif
7967         if (netif_running(netdev))
7968                 ixgbe_up(adapter);
7969
7970         netif_device_attach(netdev);
7971 }
7972
7973 static struct pci_error_handlers ixgbe_err_handler = {
7974         .error_detected = ixgbe_io_error_detected,
7975         .slot_reset = ixgbe_io_slot_reset,
7976         .resume = ixgbe_io_resume,
7977 };
7978
7979 static struct pci_driver ixgbe_driver = {
7980         .name     = ixgbe_driver_name,
7981         .id_table = ixgbe_pci_tbl,
7982         .probe    = ixgbe_probe,
7983         .remove   = __devexit_p(ixgbe_remove),
7984 #ifdef CONFIG_PM
7985         .suspend  = ixgbe_suspend,
7986         .resume   = ixgbe_resume,
7987 #endif
7988         .shutdown = ixgbe_shutdown,
7989         .err_handler = &ixgbe_err_handler
7990 };
7991
7992 /**
7993  * ixgbe_init_module - Driver Registration Routine
7994  *
7995  * ixgbe_init_module is the first routine called when the driver is
7996  * loaded. All it does is register with the PCI subsystem.
7997  **/
7998 static int __init ixgbe_init_module(void)
7999 {
8000         int ret;
8001         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
8002         pr_info("%s\n", ixgbe_copyright);
8003
8004 #ifdef CONFIG_IXGBE_DCA
8005         dca_register_notify(&dca_notifier);
8006 #endif
8007
8008         ret = pci_register_driver(&ixgbe_driver);
8009         return ret;
8010 }
8011
8012 module_init(ixgbe_init_module);
8013
8014 /**
8015  * ixgbe_exit_module - Driver Exit Cleanup Routine
8016  *
8017  * ixgbe_exit_module is called just before the driver is removed
8018  * from memory.
8019  **/
8020 static void __exit ixgbe_exit_module(void)
8021 {
8022 #ifdef CONFIG_IXGBE_DCA
8023         dca_unregister_notify(&dca_notifier);
8024 #endif
8025         pci_unregister_driver(&ixgbe_driver);
8026         rcu_barrier(); /* Wait for completion of call_rcu()'s */
8027 }
8028
8029 #ifdef CONFIG_IXGBE_DCA
8030 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
8031                             void *p)
8032 {
8033         int ret_val;
8034
8035         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8036                                          __ixgbe_notify_dca);
8037
8038         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8039 }
8040
8041 #endif /* CONFIG_IXGBE_DCA */
8042
8043 module_exit(ixgbe_exit_module);
8044
8045 /* ixgbe_main.c */