drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 111
 112 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 113
 114 #define E1000_ICH_RAR_ENTRIES           7
 115
 116 #define PHY_PAGE_SHIFT 5
 117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 118                            ((reg) & MAX_PHY_REG_ADDRESS))
 119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 121
 122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 124 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 125
 126 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 127
 128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 129
 130 /* SMBus Address Phy Register */
 131 #define HV_SMB_ADDR            PHY_REG(768, 26)
 132 #define HV_SMB_ADDR_MASK       0x007F
 133 #define HV_SMB_ADDR_PEC_EN     0x0200
 134 #define HV_SMB_ADDR_VALID      0x0080
 135
 136 /* PHY Power Management Control */
 137 #define HV_PM_CTRL              PHY_REG(770, 17)
 138
 139 /* PHY Low Power Idle Control */
 140 #define I82579_LPI_CTRL                         PHY_REG(772, 20)
 141 #define I82579_LPI_CTRL_ENABLE_MASK             0x6000
 142 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT    0x80
 143
 144 /* EMI Registers */
 145 #define I82579_EMI_ADDR         0x10
 146 #define I82579_EMI_DATA         0x11
 147 #define I82579_LPI_UPDATE_TIMER 0x4805  /* in 40ns units + 40 ns base value */
 148
 149 /* Strapping Option Register - RO */
 150 #define E1000_STRAP                     0x0000C
 151 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 152 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 153
 154 /* OEM Bits Phy Register */
 155 #define HV_OEM_BITS            PHY_REG(768, 25)
 156 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 157 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 158 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 159
 160 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 161 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 162
 163 /* KMRN Mode Control */
 164 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 165 #define HV_KMRN_MDIO_SLOW      0x0400
 166
 167 /* KMRN FIFO Control and Status */
 168 #define HV_KMRN_FIFO_CTRLSTA                  PHY_REG(770, 16)
 169 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK    0x7000
 170 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT   12
 171
 172 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 173 /* Offset 04h HSFSTS */
 174 union ich8_hws_flash_status {
 175         struct ich8_hsfsts {
 176                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 177                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 178                 u16 dael       :1; /* bit 2 Direct Access error Log */
 179                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 180                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 181                 u16 reserved1  :2; /* bit 13:6 Reserved */
 182                 u16 reserved2  :6; /* bit 13:6 Reserved */
 183                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 184                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 185         } hsf_status;
 186         u16 regval;
 187 };
 188
 189 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 190 /* Offset 06h FLCTL */
 191 union ich8_hws_flash_ctrl {
 192         struct ich8_hsflctl {
 193                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 194                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 195                 u16 reserved   :5;   /* 7:3 Reserved  */
 196                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 197                 u16 flockdn    :6;   /* 15:10 Reserved */
 198         } hsf_ctrl;
 199         u16 regval;
 200 };
 201
 202 /* ICH Flash Region Access Permissions */
 203 union ich8_hws_flash_regacc {
 204         struct ich8_flracc {
 205                 u32 grra      :8; /* 0:7 GbE region Read Access */
 206                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 207                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 208                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 209         } hsf_flregacc;
 210         u16 regval;
 211 };
 212
 213 /* ICH Flash Protected Region */
 214 union ich8_flash_protected_range {
 215         struct ich8_pr {
 216                 u32 base:13;     /* 0:12 Protected Range Base */
 217                 u32 reserved1:2; /* 13:14 Reserved */
 218                 u32 rpe:1;       /* 15 Read Protection Enable */
 219                 u32 limit:13;    /* 16:28 Protected Range Limit */
 220                 u32 reserved2:2; /* 29:30 Reserved */
 221                 u32 wpe:1;       /* 31 Write Protection Enable */
 222         } range;
 223         u32 regval;
 224 };
 225
 226 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 227 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 228 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 229 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 230 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 231                                                 u32 offset, u8 byte);
 232 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 233                                          u8 *data);
 234 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 235                                          u16 *data);
 236 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 237                                          u8 size, u16 *data);
 238 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 239 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 240 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 241 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 242 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 243 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 244 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 245 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 246 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 247 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 248 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 249 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 250 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 251 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 252 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 253 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 254 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 255 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 256 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 257 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 258
 259 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 260 {
 261         return readw(hw->flash_address + reg);
 262 }
 263
 264 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 265 {
 266         return readl(hw->flash_address + reg);
 267 }
 268
 269 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 270 {
 271         writew(val, hw->flash_address + reg);
 272 }
 273
 274 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 275 {
 276         writel(val, hw->flash_address + reg);
 277 }
 278
 279 #define er16flash(reg)          __er16flash(hw, (reg))
 280 #define er32flash(reg)          __er32flash(hw, (reg))
 281 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 282 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 283
 284 static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
 285 {
 286         u32 ctrl;
 287
 288         ctrl = er32(CTRL);
 289         ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
 290         ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 291         ew32(CTRL, ctrl);
 292         e1e_flush();
 293         udelay(10);
 294         ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 295         ew32(CTRL, ctrl);
 296 }
 297
 298 /**
 299  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 300  *  @hw: pointer to the HW structure
 301  *
 302  *  Initialize family-specific PHY parameters and function pointers.
 303  **/
 304 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 305 {
 306         struct e1000_phy_info *phy = &hw->phy;
 307         u32 fwsm;
 308         s32 ret_val = 0;
 309
 310         phy->addr                     = 1;
 311         phy->reset_delay_us           = 100;
 312
 313         phy->ops.set_page             = e1000_set_page_igp;
 314         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 315         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 316         phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;
 317         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 318         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 319         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 320         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 321         phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;
 322         phy->ops.power_up             = e1000_power_up_phy_copper;
 323         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 324         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 325
 326         /*
 327          * The MAC-PHY interconnect may still be in SMBus mode
 328          * after Sx->S0.  If the manageability engine (ME) is
 329          * disabled, then toggle the LANPHYPC Value bit to force
 330          * the interconnect to PCIe mode.
 331          */
 332         fwsm = er32(FWSM);
 333         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {
 334                 e1000_toggle_lanphypc_value_ich8lan(hw);
 335                 msleep(50);
 336
 337                 /*
 338                  * Gate automatic PHY configuration by hardware on
 339                  * non-managed 82579
 340                  */
 341                 if (hw->mac.type == e1000_pch2lan)
 342                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 343         }
 344
 345         /*
 346          * Reset the PHY before any access to it.  Doing so, ensures that
 347          * the PHY is in a known good state before we read/write PHY registers.
 348          * The generic reset is sufficient here, because we haven't determined
 349          * the PHY type yet.
 350          */
 351         ret_val = e1000e_phy_hw_reset_generic(hw);
 352         if (ret_val)
 353                 goto out;
 354
 355         /* Ungate automatic PHY configuration on non-managed 82579 */
 356         if ((hw->mac.type == e1000_pch2lan) &&
 357             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 358                 usleep_range(10000, 20000);
 359                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 360         }
 361
 362         phy->id = e1000_phy_unknown;
 363         switch (hw->mac.type) {
 364         default:
 365                 ret_val = e1000e_get_phy_id(hw);
 366                 if (ret_val)
 367                         goto out;
 368                 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 369                         break;
 370                 /* fall-through */
 371         case e1000_pch2lan:
 372                 /*
 373                  * In case the PHY needs to be in mdio slow mode,
 374                  * set slow mode and try to get the PHY id again.
 375                  */
 376                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 377                 if (ret_val)
 378                         goto out;
 379                 ret_val = e1000e_get_phy_id(hw);
 380                 if (ret_val)
 381                         goto out;
 382                 break;
 383         }
 384         phy->type = e1000e_get_phy_type_from_id(phy->id);
 385
 386         switch (phy->type) {
 387         case e1000_phy_82577:
 388         case e1000_phy_82579:
 389                 phy->ops.check_polarity = e1000_check_polarity_82577;
 390                 phy->ops.force_speed_duplex =
 391                     e1000_phy_force_speed_duplex_82577;
 392                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 393                 phy->ops.get_info = e1000_get_phy_info_82577;
 394                 phy->ops.commit = e1000e_phy_sw_reset;
 395                 break;
 396         case e1000_phy_82578:
 397                 phy->ops.check_polarity = e1000_check_polarity_m88;
 398                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 399                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 400                 phy->ops.get_info = e1000e_get_phy_info_m88;
 401                 break;
 402         default:
 403                 ret_val = -E1000_ERR_PHY;
 404                 break;
 405         }
 406
 407 out:
 408         return ret_val;
 409 }
 410
 411 /**
 412  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 413  *  @hw: pointer to the HW structure
 414  *
 415  *  Initialize family-specific PHY parameters and function pointers.
 416  **/
 417 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 418 {
 419         struct e1000_phy_info *phy = &hw->phy;
 420         s32 ret_val;
 421         u16 i = 0;
 422
 423         phy->addr                       = 1;
 424         phy->reset_delay_us             = 100;
 425
 426         phy->ops.power_up               = e1000_power_up_phy_copper;
 427         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 428
 429         /*
 430          * We may need to do this twice - once for IGP and if that fails,
 431          * we'll set BM func pointers and try again
 432          */
 433         ret_val = e1000e_determine_phy_address(hw);
 434         if (ret_val) {
 435                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 436                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 437                 ret_val = e1000e_determine_phy_address(hw);
 438                 if (ret_val) {
 439                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 440                         return ret_val;
 441                 }
 442         }
 443
 444         phy->id = 0;
 445         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 446                (i++ < 100)) {
 447                 usleep_range(1000, 2000);
 448                 ret_val = e1000e_get_phy_id(hw);
 449                 if (ret_val)
 450                         return ret_val;
 451         }
 452
 453         /* Verify phy id */
 454         switch (phy->id) {
 455         case IGP03E1000_E_PHY_ID:
 456                 phy->type = e1000_phy_igp_3;
 457                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 458                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 459                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 460                 phy->ops.get_info = e1000e_get_phy_info_igp;
 461                 phy->ops.check_polarity = e1000_check_polarity_igp;
 462                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 463                 break;
 464         case IFE_E_PHY_ID:
 465         case IFE_PLUS_E_PHY_ID:
 466         case IFE_C_E_PHY_ID:
 467                 phy->type = e1000_phy_ife;
 468                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 469                 phy->ops.get_info = e1000_get_phy_info_ife;
 470                 phy->ops.check_polarity = e1000_check_polarity_ife;
 471                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 472                 break;
 473         case BME1000_E_PHY_ID:
 474                 phy->type = e1000_phy_bm;
 475                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 476                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 477                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 478                 phy->ops.commit = e1000e_phy_sw_reset;
 479                 phy->ops.get_info = e1000e_get_phy_info_m88;
 480                 phy->ops.check_polarity = e1000_check_polarity_m88;
 481                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 482                 break;
 483         default:
 484                 return -E1000_ERR_PHY;
 485                 break;
 486         }
 487
 488         return 0;
 489 }
 490
 491 /**
 492  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 493  *  @hw: pointer to the HW structure
 494  *
 495  *  Initialize family-specific NVM parameters and function
 496  *  pointers.
 497  **/
 498 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 499 {
 500         struct e1000_nvm_info *nvm = &hw->nvm;
 501         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 502         u32 gfpreg, sector_base_addr, sector_end_addr;
 503         u16 i;
 504
 505         /* Can't read flash registers if the register set isn't mapped. */
 506         if (!hw->flash_address) {
 507                 e_dbg("ERROR: Flash registers not mapped\n");
 508                 return -E1000_ERR_CONFIG;
 509         }
 510
 511         nvm->type = e1000_nvm_flash_sw;
 512
 513         gfpreg = er32flash(ICH_FLASH_GFPREG);
 514
 515         /*
 516          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 517          * Add 1 to sector_end_addr since this sector is included in
 518          * the overall size.
 519          */
 520         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 521         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 522
 523         /* flash_base_addr is byte-aligned */
 524         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 525
 526         /*
 527          * find total size of the NVM, then cut in half since the total
 528          * size represents two separate NVM banks.
 529          */
 530         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 531                                 << FLASH_SECTOR_ADDR_SHIFT;
 532         nvm->flash_bank_size /= 2;
 533         /* Adjust to word count */
 534         nvm->flash_bank_size /= sizeof(u16);
 535
 536         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 537
 538         /* Clear shadow ram */
 539         for (i = 0; i < nvm->word_size; i++) {
 540                 dev_spec->shadow_ram[i].modified = false;
 541                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 542         }
 543
 544         return 0;
 545 }
 546
 547 /**
 548  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 549  *  @hw: pointer to the HW structure
 550  *
 551  *  Initialize family-specific MAC parameters and function
 552  *  pointers.
 553  **/
 554 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 555 {
 556         struct e1000_hw *hw = &adapter->hw;
 557         struct e1000_mac_info *mac = &hw->mac;
 558
 559         /* Set media type function pointer */
 560         hw->phy.media_type = e1000_media_type_copper;
 561
 562         /* Set mta register count */
 563         mac->mta_reg_count = 32;
 564         /* Set rar entry count */
 565         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 566         if (mac->type == e1000_ich8lan)
 567                 mac->rar_entry_count--;
 568         /* FWSM register */
 569         mac->has_fwsm = true;
 570         /* ARC subsystem not supported */
 571         mac->arc_subsystem_valid = false;
 572         /* Adaptive IFS supported */
 573         mac->adaptive_ifs = true;
 574
 575         /* LED operations */
 576         switch (mac->type) {
 577         case e1000_ich8lan:
 578         case e1000_ich9lan:
 579         case e1000_ich10lan:
 580                 /* check management mode */
 581                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 582                 /* ID LED init */
 583                 mac->ops.id_led_init = e1000e_id_led_init;
 584                 /* blink LED */
 585                 mac->ops.blink_led = e1000e_blink_led_generic;
 586                 /* setup LED */
 587                 mac->ops.setup_led = e1000e_setup_led_generic;
 588                 /* cleanup LED */
 589                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 590                 /* turn on/off LED */
 591                 mac->ops.led_on = e1000_led_on_ich8lan;
 592                 mac->ops.led_off = e1000_led_off_ich8lan;
 593                 break;
 594         case e1000_pchlan:
 595         case e1000_pch2lan:
 596                 /* check management mode */
 597                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 598                 /* ID LED init */
 599                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 600                 /* setup LED */
 601                 mac->ops.setup_led = e1000_setup_led_pchlan;
 602                 /* cleanup LED */
 603                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 604                 /* turn on/off LED */
 605                 mac->ops.led_on = e1000_led_on_pchlan;
 606                 mac->ops.led_off = e1000_led_off_pchlan;
 607                 break;
 608         default:
 609                 break;
 610         }
 611
 612         /* Enable PCS Lock-loss workaround for ICH8 */
 613         if (mac->type == e1000_ich8lan)
 614                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 615
 616         /* Gate automatic PHY configuration by hardware on managed 82579 */
 617         if ((mac->type == e1000_pch2lan) &&
 618             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 619                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 620
 621         return 0;
 622 }
 623
 624 /**
 625  *  e1000_set_eee_pchlan - Enable/disable EEE support
 626  *  @hw: pointer to the HW structure
 627  *
 628  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 629  *  the LPI Control register will remain set only if/when link is up.
 630  **/
 631 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 632 {
 633         s32 ret_val = 0;
 634         u16 phy_reg;
 635
 636         if (hw->phy.type != e1000_phy_82579)
 637                 goto out;
 638
 639         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 640         if (ret_val)
 641                 goto out;
 642
 643         if (hw->dev_spec.ich8lan.eee_disable)
 644                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 645         else
 646                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 647
 648         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 649 out:
 650         return ret_val;
 651 }
 652
 653 /**
 654  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 655  *  @hw: pointer to the HW structure
 656  *
 657  *  Checks to see of the link status of the hardware has changed.  If a
 658  *  change in link status has been detected, then we read the PHY registers
 659  *  to get the current speed/duplex if link exists.
 660  **/
 661 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 662 {
 663         struct e1000_mac_info *mac = &hw->mac;
 664         s32 ret_val;
 665         bool link;
 666         u16 phy_reg;
 667
 668         /*
 669          * We only want to go out to the PHY registers to see if Auto-Neg
 670          * has completed and/or if our link status has changed.  The
 671          * get_link_status flag is set upon receiving a Link Status
 672          * Change or Rx Sequence Error interrupt.
 673          */
 674         if (!mac->get_link_status) {
 675                 ret_val = 0;
 676                 goto out;
 677         }
 678
 679         /*
 680          * First we want to see if the MII Status Register reports
 681          * link.  If so, then we want to get the current speed/duplex
 682          * of the PHY.
 683          */
 684         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 685         if (ret_val)
 686                 goto out;
 687
 688         if (hw->mac.type == e1000_pchlan) {
 689                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 690                 if (ret_val)
 691                         goto out;
 692         }
 693
 694         if (!link)
 695                 goto out; /* No link detected */
 696
 697         mac->get_link_status = false;
 698
 699         switch (hw->mac.type) {
 700         case e1000_pch2lan:
 701                 ret_val = e1000_k1_workaround_lv(hw);
 702                 if (ret_val)
 703                         goto out;
 704                 /* fall-thru */
 705         case e1000_pchlan:
 706                 if (hw->phy.type == e1000_phy_82578) {
 707                         ret_val = e1000_link_stall_workaround_hv(hw);
 708                         if (ret_val)
 709                                 goto out;
 710                 }
 711
 712                 /*
 713                  * Workaround for PCHx parts in half-duplex:
 714                  * Set the number of preambles removed from the packet
 715                  * when it is passed from the PHY to the MAC to prevent
 716                  * the MAC from misinterpreting the packet type.
 717                  */
 718                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
 719                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
 720
 721                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
 722                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
 723
 724                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
 725                 break;
 726         default:
 727                 break;
 728         }
 729
 730         /*
 731          * Check if there was DownShift, must be checked
 732          * immediately after link-up
 733          */
 734         e1000e_check_downshift(hw);
 735
 736         /* Enable/Disable EEE after link up */
 737         ret_val = e1000_set_eee_pchlan(hw);
 738         if (ret_val)
 739                 goto out;
 740
 741         /*
 742          * If we are forcing speed/duplex, then we simply return since
 743          * we have already determined whether we have link or not.
 744          */
 745         if (!mac->autoneg) {
 746                 ret_val = -E1000_ERR_CONFIG;
 747                 goto out;
 748         }
 749
 750         /*
 751          * Auto-Neg is enabled.  Auto Speed Detection takes care
 752          * of MAC speed/duplex configuration.  So we only need to
 753          * configure Collision Distance in the MAC.
 754          */
 755         e1000e_config_collision_dist(hw);
 756
 757         /*
 758          * Configure Flow Control now that Auto-Neg has completed.
 759          * First, we need to restore the desired flow control
 760          * settings because we may have had to re-autoneg with a
 761          * different link partner.
 762          */
 763         ret_val = e1000e_config_fc_after_link_up(hw);
 764         if (ret_val)
 765                 e_dbg("Error configuring flow control\n");
 766
 767 out:
 768         return ret_val;
 769 }
 770
 771 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 772 {
 773         struct e1000_hw *hw = &adapter->hw;
 774         s32 rc;
 775
 776         rc = e1000_init_mac_params_ich8lan(adapter);
 777         if (rc)
 778                 return rc;
 779
 780         rc = e1000_init_nvm_params_ich8lan(hw);
 781         if (rc)
 782                 return rc;
 783
 784         switch (hw->mac.type) {
 785         case e1000_ich8lan:
 786         case e1000_ich9lan:
 787         case e1000_ich10lan:
 788                 rc = e1000_init_phy_params_ich8lan(hw);
 789                 break;
 790         case e1000_pchlan:
 791         case e1000_pch2lan:
 792                 rc = e1000_init_phy_params_pchlan(hw);
 793                 break;
 794         default:
 795                 break;
 796         }
 797         if (rc)
 798                 return rc;
 799
 800         /*
 801          * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
 802          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
 803          */
 804         if ((adapter->hw.phy.type == e1000_phy_ife) ||
 805             ((adapter->hw.mac.type >= e1000_pch2lan) &&
 806              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
 807                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 808                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 809
 810                 hw->mac.ops.blink_led = NULL;
 811         }
 812
 813         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 814             (adapter->hw.phy.type != e1000_phy_ife))
 815                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 816
 817         /* Enable workaround for 82579 w/ ME enabled */
 818         if ((adapter->hw.mac.type == e1000_pch2lan) &&
 819             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 820                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
 821
 822         /* Disable EEE by default until IEEE802.3az spec is finalized */
 823         if (adapter->flags2 & FLAG2_HAS_EEE)
 824                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 825
 826         return 0;
 827 }
 828
 829 static DEFINE_MUTEX(nvm_mutex);
 830
 831 /**
 832  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 833  *  @hw: pointer to the HW structure
 834  *
 835  *  Acquires the mutex for performing NVM operations.
 836  **/
 837 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 838 {
 839         mutex_lock(&nvm_mutex);
 840
 841         return 0;
 842 }
 843
 844 /**
 845  *  e1000_release_nvm_ich8lan - Release NVM mutex
 846  *  @hw: pointer to the HW structure
 847  *
 848  *  Releases the mutex used while performing NVM operations.
 849  **/
 850 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 851 {
 852         mutex_unlock(&nvm_mutex);
 853 }
 854
 855 static DEFINE_MUTEX(swflag_mutex);
 856
 857 /**
 858  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 859  *  @hw: pointer to the HW structure
 860  *
 861  *  Acquires the software control flag for performing PHY and select
 862  *  MAC CSR accesses.
 863  **/
 864 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 865 {
 866         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 867         s32 ret_val = 0;
 868
 869         mutex_lock(&swflag_mutex);
 870
 871         while (timeout) {
 872                 extcnf_ctrl = er32(EXTCNF_CTRL);
 873                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 874                         break;
 875
 876                 mdelay(1);
 877                 timeout--;
 878         }
 879
 880         if (!timeout) {
 881                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
 882                 ret_val = -E1000_ERR_CONFIG;
 883                 goto out;
 884         }
 885
 886         timeout = SW_FLAG_TIMEOUT;
 887
 888         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 889         ew32(EXTCNF_CTRL, extcnf_ctrl);
 890
 891         while (timeout) {
 892                 extcnf_ctrl = er32(EXTCNF_CTRL);
 893                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 894                         break;
 895
 896                 mdelay(1);
 897                 timeout--;
 898         }
 899
 900         if (!timeout) {
 901                 e_dbg("Failed to acquire the semaphore.\n");
 902                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 903                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 904                 ret_val = -E1000_ERR_CONFIG;
 905                 goto out;
 906         }
 907
 908 out:
 909         if (ret_val)
 910                 mutex_unlock(&swflag_mutex);
 911
 912         return ret_val;
 913 }
 914
 915 /**
 916  *  e1000_release_swflag_ich8lan - Release software control flag
 917  *  @hw: pointer to the HW structure
 918  *
 919  *  Releases the software control flag for performing PHY and select
 920  *  MAC CSR accesses.
 921  **/
 922 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 923 {
 924         u32 extcnf_ctrl;
 925
 926         extcnf_ctrl = er32(EXTCNF_CTRL);
 927
 928         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
 929                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 930                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 931         } else {
 932                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
 933         }
 934
 935         mutex_unlock(&swflag_mutex);
 936 }
 937
 938 /**
 939  *  e1000_check_mng_mode_ich8lan - Checks management mode
 940  *  @hw: pointer to the HW structure
 941  *
 942  *  This checks if the adapter has any manageability enabled.
 943  *  This is a function pointer entry point only called by read/write
 944  *  routines for the PHY and NVM parts.
 945  **/
 946 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 947 {
 948         u32 fwsm;
 949
 950         fwsm = er32(FWSM);
 951         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 952                ((fwsm & E1000_FWSM_MODE_MASK) ==
 953                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 954 }
 955
 956 /**
 957  *  e1000_check_mng_mode_pchlan - Checks management mode
 958  *  @hw: pointer to the HW structure
 959  *
 960  *  This checks if the adapter has iAMT enabled.
 961  *  This is a function pointer entry point only called by read/write
 962  *  routines for the PHY and NVM parts.
 963  **/
 964 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 965 {
 966         u32 fwsm;
 967
 968         fwsm = er32(FWSM);
 969         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 970                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 971 }
 972
 973 /**
 974  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 975  *  @hw: pointer to the HW structure
 976  *
 977  *  Checks if firmware is blocking the reset of the PHY.
 978  *  This is a function pointer entry point only called by
 979  *  reset routines.
 980  **/
 981 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 982 {
 983         u32 fwsm;
 984
 985         fwsm = er32(FWSM);
 986
 987         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 988 }
 989
 990 /**
 991  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 992  *  @hw: pointer to the HW structure
 993  *
 994  *  Assumes semaphore already acquired.
 995  *
 996  **/
 997 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
 998 {
 999         u16 phy_data;
1000         u32 strap = er32(STRAP);
1001         s32 ret_val = 0;
1002
1003         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1004
1005         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1006         if (ret_val)
1007                 goto out;
1008
1009         phy_data &= ~HV_SMB_ADDR_MASK;
1010         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1011         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1012         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1013
1014 out:
1015         return ret_val;
1016 }
1017
1018 /**
1019  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1020  *  @hw:   pointer to the HW structure
1021  *
1022  *  SW should configure the LCD from the NVM extended configuration region
1023  *  as a workaround for certain parts.
1024  **/
1025 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1026 {
1027         struct e1000_phy_info *phy = &hw->phy;
1028         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1029         s32 ret_val = 0;
1030         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1031
1032         /*
1033          * Initialize the PHY from the NVM on ICH platforms.  This
1034          * is needed due to an issue where the NVM configuration is
1035          * not properly autoloaded after power transitions.
1036          * Therefore, after each PHY reset, we will load the
1037          * configuration data out of the NVM manually.
1038          */
1039         switch (hw->mac.type) {
1040         case e1000_ich8lan:
1041                 if (phy->type != e1000_phy_igp_3)
1042                         return ret_val;
1043
1044                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1045                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1046                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1047                         break;
1048                 }
1049                 /* Fall-thru */
1050         case e1000_pchlan:
1051         case e1000_pch2lan:
1052                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1053                 break;
1054         default:
1055                 return ret_val;
1056         }
1057
1058         ret_val = hw->phy.ops.acquire(hw);
1059         if (ret_val)
1060                 return ret_val;
1061
1062         data = er32(FEXTNVM);
1063         if (!(data & sw_cfg_mask))
1064                 goto out;
1065
1066         /*
1067          * Make sure HW does not configure LCD from PHY
1068          * extended configuration before SW configuration
1069          */
1070         data = er32(EXTCNF_CTRL);
1071         if (!(hw->mac.type == e1000_pch2lan)) {
1072                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1073                         goto out;
1074         }
1075
1076         cnf_size = er32(EXTCNF_SIZE);
1077         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1078         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1079         if (!cnf_size)
1080                 goto out;
1081
1082         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1083         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1084
1085         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1086             (hw->mac.type == e1000_pchlan)) ||
1087              (hw->mac.type == e1000_pch2lan)) {
1088                 /*
1089                  * HW configures the SMBus address and LEDs when the
1090                  * OEM and LCD Write Enable bits are set in the NVM.
1091                  * When both NVM bits are cleared, SW will configure
1092                  * them instead.
1093                  */
1094                 ret_val = e1000_write_smbus_addr(hw);
1095                 if (ret_val)
1096                         goto out;
1097
1098                 data = er32(LEDCTL);
1099                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1100                                                         (u16)data);
1101                 if (ret_val)
1102                         goto out;
1103         }
1104
1105         /* Configure LCD from extended configuration region. */
1106
1107         /* cnf_base_addr is in DWORD */
1108         word_addr = (u16)(cnf_base_addr << 1);
1109
1110         for (i = 0; i < cnf_size; i++) {
1111                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1112                                          &reg_data);
1113                 if (ret_val)
1114                         goto out;
1115
1116                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1117                                          1, &reg_addr);
1118                 if (ret_val)
1119                         goto out;
1120
1121                 /* Save off the PHY page for future writes. */
1122                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1123                         phy_page = reg_data;
1124                         continue;
1125                 }
1126
1127                 reg_addr &= PHY_REG_MASK;
1128                 reg_addr |= phy_page;
1129
1130                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1131                                                     reg_data);
1132                 if (ret_val)
1133                         goto out;
1134         }
1135
1136 out:
1137         hw->phy.ops.release(hw);
1138         return ret_val;
1139 }
1140
1141 /**
1142  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1143  *  @hw:   pointer to the HW structure
1144  *  @link: link up bool flag
1145  *
1146  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1147  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1148  *  If link is down, the function will restore the default K1 setting located
1149  *  in the NVM.
1150  **/
1151 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1152 {
1153         s32 ret_val = 0;
1154         u16 status_reg = 0;
1155         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1156
1157         if (hw->mac.type != e1000_pchlan)
1158                 goto out;
1159
1160         /* Wrap the whole flow with the sw flag */
1161         ret_val = hw->phy.ops.acquire(hw);
1162         if (ret_val)
1163                 goto out;
1164
1165         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1166         if (link) {
1167                 if (hw->phy.type == e1000_phy_82578) {
1168                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1169                                                                   &status_reg);
1170                         if (ret_val)
1171                                 goto release;
1172
1173                         status_reg &= BM_CS_STATUS_LINK_UP |
1174                                       BM_CS_STATUS_RESOLVED |
1175                                       BM_CS_STATUS_SPEED_MASK;
1176
1177                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1178                                            BM_CS_STATUS_RESOLVED |
1179                                            BM_CS_STATUS_SPEED_1000))
1180                                 k1_enable = false;
1181                 }
1182
1183                 if (hw->phy.type == e1000_phy_82577) {
1184                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1185                                                                   &status_reg);
1186                         if (ret_val)
1187                                 goto release;
1188
1189                         status_reg &= HV_M_STATUS_LINK_UP |
1190                                       HV_M_STATUS_AUTONEG_COMPLETE |
1191                                       HV_M_STATUS_SPEED_MASK;
1192
1193                         if (status_reg == (HV_M_STATUS_LINK_UP |
1194                                            HV_M_STATUS_AUTONEG_COMPLETE |
1195                                            HV_M_STATUS_SPEED_1000))
1196                                 k1_enable = false;
1197                 }
1198
1199                 /* Link stall fix for link up */
1200                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1201                                                            0x0100);
1202                 if (ret_val)
1203                         goto release;
1204
1205         } else {
1206                 /* Link stall fix for link down */
1207                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1208                                                            0x4100);
1209                 if (ret_val)
1210                         goto release;
1211         }
1212
1213         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1214
1215 release:
1216         hw->phy.ops.release(hw);
1217 out:
1218         return ret_val;
1219 }
1220
1221 /**
1222  *  e1000_configure_k1_ich8lan - Configure K1 power state
1223  *  @hw: pointer to the HW structure
1224  *  @enable: K1 state to configure
1225  *
1226  *  Configure the K1 power state based on the provided parameter.
1227  *  Assumes semaphore already acquired.
1228  *
1229  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1230  **/
1231 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1232 {
1233         s32 ret_val = 0;
1234         u32 ctrl_reg = 0;
1235         u32 ctrl_ext = 0;
1236         u32 reg = 0;
1237         u16 kmrn_reg = 0;
1238
1239         ret_val = e1000e_read_kmrn_reg_locked(hw,
1240                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1241                                              &kmrn_reg);
1242         if (ret_val)
1243                 goto out;
1244
1245         if (k1_enable)
1246                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1247         else
1248                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1249
1250         ret_val = e1000e_write_kmrn_reg_locked(hw,
1251                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1252                                               kmrn_reg);
1253         if (ret_val)
1254                 goto out;
1255
1256         udelay(20);
1257         ctrl_ext = er32(CTRL_EXT);
1258         ctrl_reg = er32(CTRL);
1259
1260         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1261         reg |= E1000_CTRL_FRCSPD;
1262         ew32(CTRL, reg);
1263
1264         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1265         e1e_flush();
1266         udelay(20);
1267         ew32(CTRL, ctrl_reg);
1268         ew32(CTRL_EXT, ctrl_ext);
1269         e1e_flush();
1270         udelay(20);
1271
1272 out:
1273         return ret_val;
1274 }
1275
1276 /**
1277  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1278  *  @hw:       pointer to the HW structure
1279  *  @d0_state: boolean if entering d0 or d3 device state
1280  *
1281  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1282  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1283  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1284  **/
1285 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1286 {
1287         s32 ret_val = 0;
1288         u32 mac_reg;
1289         u16 oem_reg;
1290
1291         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1292                 return ret_val;
1293
1294         ret_val = hw->phy.ops.acquire(hw);
1295         if (ret_val)
1296                 return ret_val;
1297
1298         if (!(hw->mac.type == e1000_pch2lan)) {
1299                 mac_reg = er32(EXTCNF_CTRL);
1300                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1301                         goto out;
1302         }
1303
1304         mac_reg = er32(FEXTNVM);
1305         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1306                 goto out;
1307
1308         mac_reg = er32(PHY_CTRL);
1309
1310         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1311         if (ret_val)
1312                 goto out;
1313
1314         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1315
1316         if (d0_state) {
1317                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1318                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1319
1320                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1321                         oem_reg |= HV_OEM_BITS_LPLU;
1322
1323                 /* Set Restart auto-neg to activate the bits */
1324                 if (!e1000_check_reset_block(hw))
1325                         oem_reg |= HV_OEM_BITS_RESTART_AN;
1326         } else {
1327                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1328                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1329                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1330
1331                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1332                                E1000_PHY_CTRL_NOND0A_LPLU))
1333                         oem_reg |= HV_OEM_BITS_LPLU;
1334         }
1335
1336         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1337
1338 out:
1339         hw->phy.ops.release(hw);
1340
1341         return ret_val;
1342 }
1343
1344
1345 /**
1346  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1347  *  @hw:   pointer to the HW structure
1348  **/
1349 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1350 {
1351         s32 ret_val;
1352         u16 data;
1353
1354         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1355         if (ret_val)
1356                 return ret_val;
1357
1358         data |= HV_KMRN_MDIO_SLOW;
1359
1360         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1361
1362         return ret_val;
1363 }
1364
1365 /**
1366  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1367  *  done after every PHY reset.
1368  **/
1369 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1370 {
1371         s32 ret_val = 0;
1372         u16 phy_data;
1373
1374         if (hw->mac.type != e1000_pchlan)
1375                 return ret_val;
1376
1377         /* Set MDIO slow mode before any other MDIO access */
1378         if (hw->phy.type == e1000_phy_82577) {
1379                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1380                 if (ret_val)
1381                         goto out;
1382         }
1383
1384         if (((hw->phy.type == e1000_phy_82577) &&
1385              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1386             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1387                 /* Disable generation of early preamble */
1388                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1389                 if (ret_val)
1390                         return ret_val;
1391
1392                 /* Preamble tuning for SSC */
1393                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1394                 if (ret_val)
1395                         return ret_val;
1396         }
1397
1398         if (hw->phy.type == e1000_phy_82578) {
1399                 /*
1400                  * Return registers to default by doing a soft reset then
1401                  * writing 0x3140 to the control register.
1402                  */
1403                 if (hw->phy.revision < 2) {
1404                         e1000e_phy_sw_reset(hw);
1405                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1406                 }
1407         }
1408
1409         /* Select page 0 */
1410         ret_val = hw->phy.ops.acquire(hw);
1411         if (ret_val)
1412                 return ret_val;
1413
1414         hw->phy.addr = 1;
1415         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1416         hw->phy.ops.release(hw);
1417         if (ret_val)
1418                 goto out;
1419
1420         /*
1421          * Configure the K1 Si workaround during phy reset assuming there is
1422          * link so that it disables K1 if link is in 1Gbps.
1423          */
1424         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1425         if (ret_val)
1426                 goto out;
1427
1428         /* Workaround for link disconnects on a busy hub in half duplex */
1429         ret_val = hw->phy.ops.acquire(hw);
1430         if (ret_val)
1431                 goto out;
1432         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1433         if (ret_val)
1434                 goto release;
1435         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1436                                                phy_data & 0x00FF);
1437 release:
1438         hw->phy.ops.release(hw);
1439 out:
1440         return ret_val;
1441 }
1442
1443 /**
1444  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1445  *  @hw:   pointer to the HW structure
1446  **/
1447 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1448 {
1449         u32 mac_reg;
1450         u16 i, phy_reg = 0;
1451         s32 ret_val;
1452
1453         ret_val = hw->phy.ops.acquire(hw);
1454         if (ret_val)
1455                 return;
1456         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1457         if (ret_val)
1458                 goto release;
1459
1460         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1461         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1462                 mac_reg = er32(RAL(i));
1463                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1464                                            (u16)(mac_reg & 0xFFFF));
1465                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1466                                            (u16)((mac_reg >> 16) & 0xFFFF));
1467
1468                 mac_reg = er32(RAH(i));
1469                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1470                                            (u16)(mac_reg & 0xFFFF));
1471                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1472                                            (u16)((mac_reg & E1000_RAH_AV)
1473                                                  >> 16));
1474         }
1475
1476         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1477
1478 release:
1479         hw->phy.ops.release(hw);
1480 }
1481
1482 /**
1483  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1484  *  with 82579 PHY
1485  *  @hw: pointer to the HW structure
1486  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1487  **/
1488 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1489 {
1490         s32 ret_val = 0;
1491         u16 phy_reg, data;
1492         u32 mac_reg;
1493         u16 i;
1494
1495         if (hw->mac.type != e1000_pch2lan)
1496                 goto out;
1497
1498         /* disable Rx path while enabling/disabling workaround */
1499         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1500         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1501         if (ret_val)
1502                 goto out;
1503
1504         if (enable) {
1505                 /*
1506                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1507                  * SHRAL/H) and initial CRC values to the MAC
1508                  */
1509                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1510                         u8 mac_addr[ETH_ALEN] = {0};
1511                         u32 addr_high, addr_low;
1512
1513                         addr_high = er32(RAH(i));
1514                         if (!(addr_high & E1000_RAH_AV))
1515                                 continue;
1516                         addr_low = er32(RAL(i));
1517                         mac_addr[0] = (addr_low & 0xFF);
1518                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1519                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1520                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1521                         mac_addr[4] = (addr_high & 0xFF);
1522                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1523
1524                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1525                 }
1526
1527                 /* Write Rx addresses to the PHY */
1528                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1529
1530                 /* Enable jumbo frame workaround in the MAC */
1531                 mac_reg = er32(FFLT_DBG);
1532                 mac_reg &= ~(1 << 14);
1533                 mac_reg |= (7 << 15);
1534                 ew32(FFLT_DBG, mac_reg);
1535
1536                 mac_reg = er32(RCTL);
1537                 mac_reg |= E1000_RCTL_SECRC;
1538                 ew32(RCTL, mac_reg);
1539
1540                 ret_val = e1000e_read_kmrn_reg(hw,
1541                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1542                                                 &data);
1543                 if (ret_val)
1544                         goto out;
1545                 ret_val = e1000e_write_kmrn_reg(hw,
1546                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1547                                                 data | (1 << 0));
1548                 if (ret_val)
1549                         goto out;
1550                 ret_val = e1000e_read_kmrn_reg(hw,
1551                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1552                                                 &data);
1553                 if (ret_val)
1554                         goto out;
1555                 data &= ~(0xF << 8);
1556                 data |= (0xB << 8);
1557                 ret_val = e1000e_write_kmrn_reg(hw,
1558                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1559                                                 data);
1560                 if (ret_val)
1561                         goto out;
1562
1563                 /* Enable jumbo frame workaround in the PHY */
1564                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1565                 data &= ~(0x7F << 5);
1566                 data |= (0x37 << 5);
1567                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1568                 if (ret_val)
1569                         goto out;
1570                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1571                 data &= ~(1 << 13);
1572                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1573                 if (ret_val)
1574                         goto out;
1575                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1576                 data &= ~(0x3FF << 2);
1577                 data |= (0x1A << 2);
1578                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1579                 if (ret_val)
1580                         goto out;
1581                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
1582                 if (ret_val)
1583                         goto out;
1584                 e1e_rphy(hw, HV_PM_CTRL, &data);
1585                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1586                 if (ret_val)
1587                         goto out;
1588         } else {
1589                 /* Write MAC register values back to h/w defaults */
1590                 mac_reg = er32(FFLT_DBG);
1591                 mac_reg &= ~(0xF << 14);
1592                 ew32(FFLT_DBG, mac_reg);
1593
1594                 mac_reg = er32(RCTL);
1595                 mac_reg &= ~E1000_RCTL_SECRC;
1596                 ew32(RCTL, mac_reg);
1597
1598                 ret_val = e1000e_read_kmrn_reg(hw,
1599                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1600                                                 &data);
1601                 if (ret_val)
1602                         goto out;
1603                 ret_val = e1000e_write_kmrn_reg(hw,
1604                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1605                                                 data & ~(1 << 0));
1606                 if (ret_val)
1607                         goto out;
1608                 ret_val = e1000e_read_kmrn_reg(hw,
1609                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1610                                                 &data);
1611                 if (ret_val)
1612                         goto out;
1613                 data &= ~(0xF << 8);
1614                 data |= (0xB << 8);
1615                 ret_val = e1000e_write_kmrn_reg(hw,
1616                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1617                                                 data);
1618                 if (ret_val)
1619                         goto out;
1620
1621                 /* Write PHY register values back to h/w defaults */
1622                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1623                 data &= ~(0x7F << 5);
1624                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1625                 if (ret_val)
1626                         goto out;
1627                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1628                 data |= (1 << 13);
1629                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1630                 if (ret_val)
1631                         goto out;
1632                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1633                 data &= ~(0x3FF << 2);
1634                 data |= (0x8 << 2);
1635                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1636                 if (ret_val)
1637                         goto out;
1638                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1639                 if (ret_val)
1640                         goto out;
1641                 e1e_rphy(hw, HV_PM_CTRL, &data);
1642                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1643                 if (ret_val)
1644                         goto out;
1645         }
1646
1647         /* re-enable Rx path after enabling/disabling workaround */
1648         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1649
1650 out:
1651         return ret_val;
1652 }
1653
1654 /**
1655  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1656  *  done after every PHY reset.
1657  **/
1658 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1659 {
1660         s32 ret_val = 0;
1661
1662         if (hw->mac.type != e1000_pch2lan)
1663                 goto out;
1664
1665         /* Set MDIO slow mode before any other MDIO access */
1666         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1667
1668 out:
1669         return ret_val;
1670 }
1671
1672 /**
1673  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1674  *  @hw:   pointer to the HW structure
1675  *
1676  *  Workaround to set the K1 beacon duration for 82579 parts
1677  **/
1678 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1679 {
1680         s32 ret_val = 0;
1681         u16 status_reg = 0;
1682         u32 mac_reg;
1683         u16 phy_reg;
1684
1685         if (hw->mac.type != e1000_pch2lan)
1686                 goto out;
1687
1688         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1689         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1690         if (ret_val)
1691                 goto out;
1692
1693         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1694             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1695                 mac_reg = er32(FEXTNVM4);
1696                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1697
1698                 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
1699                 if (ret_val)
1700                         goto out;
1701
1702                 if (status_reg & HV_M_STATUS_SPEED_1000) {
1703                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1704                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1705                 } else {
1706                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1707                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1708                 }
1709                 ew32(FEXTNVM4, mac_reg);
1710                 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
1711         }
1712
1713 out:
1714         return ret_val;
1715 }
1716
1717 /**
1718  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1719  *  @hw:   pointer to the HW structure
1720  *  @gate: boolean set to true to gate, false to ungate
1721  *
1722  *  Gate/ungate the automatic PHY configuration via hardware; perform
1723  *  the configuration via software instead.
1724  **/
1725 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1726 {
1727         u32 extcnf_ctrl;
1728
1729         if (hw->mac.type != e1000_pch2lan)
1730                 return;
1731
1732         extcnf_ctrl = er32(EXTCNF_CTRL);
1733
1734         if (gate)
1735                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1736         else
1737                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1738
1739         ew32(EXTCNF_CTRL, extcnf_ctrl);
1740         return;
1741 }
1742
1743 /**
1744  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1745  *  @hw: pointer to the HW structure
1746  *
1747  *  Check the appropriate indication the MAC has finished configuring the
1748  *  PHY after a software reset.
1749  **/
1750 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1751 {
1752         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1753
1754         /* Wait for basic configuration completes before proceeding */
1755         do {
1756                 data = er32(STATUS);
1757                 data &= E1000_STATUS_LAN_INIT_DONE;
1758                 udelay(100);
1759         } while ((!data) && --loop);
1760
1761         /*
1762          * If basic configuration is incomplete before the above loop
1763          * count reaches 0, loading the configuration from NVM will
1764          * leave the PHY in a bad state possibly resulting in no link.
1765          */
1766         if (loop == 0)
1767                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1768
1769         /* Clear the Init Done bit for the next init event */
1770         data = er32(STATUS);
1771         data &= ~E1000_STATUS_LAN_INIT_DONE;
1772         ew32(STATUS, data);
1773 }
1774
1775 /**
1776  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1777  *  @hw: pointer to the HW structure
1778  **/
1779 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1780 {
1781         s32 ret_val = 0;
1782         u16 reg;
1783
1784         if (e1000_check_reset_block(hw))
1785                 goto out;
1786
1787         /* Allow time for h/w to get to quiescent state after reset */
1788         usleep_range(10000, 20000);
1789
1790         /* Perform any necessary post-reset workarounds */
1791         switch (hw->mac.type) {
1792         case e1000_pchlan:
1793                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1794                 if (ret_val)
1795                         goto out;
1796                 break;
1797         case e1000_pch2lan:
1798                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1799                 if (ret_val)
1800                         goto out;
1801                 break;
1802         default:
1803                 break;
1804         }
1805
1806         /* Clear the host wakeup bit after lcd reset */
1807         if (hw->mac.type >= e1000_pchlan) {
1808                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
1809                 reg &= ~BM_WUC_HOST_WU_BIT;
1810                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
1811         }
1812
1813         /* Configure the LCD with the extended configuration region in NVM */
1814         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1815         if (ret_val)
1816                 goto out;
1817
1818         /* Configure the LCD with the OEM bits in NVM */
1819         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1820
1821         if (hw->mac.type == e1000_pch2lan) {
1822                 /* Ungate automatic PHY configuration on non-managed 82579 */
1823                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1824                         usleep_range(10000, 20000);
1825                         e1000_gate_hw_phy_config_ich8lan(hw, false);
1826                 }
1827
1828                 /* Set EEE LPI Update Timer to 200usec */
1829                 ret_val = hw->phy.ops.acquire(hw);
1830                 if (ret_val)
1831                         goto out;
1832                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1833                                                        I82579_LPI_UPDATE_TIMER);
1834                 if (ret_val)
1835                         goto release;
1836                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1837                                                        0x1387);
1838 release:
1839                 hw->phy.ops.release(hw);
1840         }
1841
1842 out:
1843         return ret_val;
1844 }
1845
1846 /**
1847  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1848  *  @hw: pointer to the HW structure
1849  *
1850  *  Resets the PHY
1851  *  This is a function pointer entry point called by drivers
1852  *  or other shared routines.
1853  **/
1854 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1855 {
1856         s32 ret_val = 0;
1857
1858         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1859         if ((hw->mac.type == e1000_pch2lan) &&
1860             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1861                 e1000_gate_hw_phy_config_ich8lan(hw, true);
1862
1863         ret_val = e1000e_phy_hw_reset_generic(hw);
1864         if (ret_val)
1865                 goto out;
1866
1867         ret_val = e1000_post_phy_reset_ich8lan(hw);
1868
1869 out:
1870         return ret_val;
1871 }
1872
1873 /**
1874  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1875  *  @hw: pointer to the HW structure
1876  *  @active: true to enable LPLU, false to disable
1877  *
1878  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1879  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1880  *  the phy speed. This function will manually set the LPLU bit and restart
1881  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1882  *  since it configures the same bit.
1883  **/
1884 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1885 {
1886         s32 ret_val = 0;
1887         u16 oem_reg;
1888
1889         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1890         if (ret_val)
1891                 goto out;
1892
1893         if (active)
1894                 oem_reg |= HV_OEM_BITS_LPLU;
1895         else
1896                 oem_reg &= ~HV_OEM_BITS_LPLU;
1897
1898         oem_reg |= HV_OEM_BITS_RESTART_AN;
1899         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1900
1901 out:
1902         return ret_val;
1903 }
1904
1905 /**
1906  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1907  *  @hw: pointer to the HW structure
1908  *  @active: true to enable LPLU, false to disable
1909  *
1910  *  Sets the LPLU D0 state according to the active flag.  When
1911  *  activating LPLU this function also disables smart speed
1912  *  and vice versa.  LPLU will not be activated unless the
1913  *  device autonegotiation advertisement meets standards of
1914  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1915  *  This is a function pointer entry point only called by
1916  *  PHY setup routines.
1917  **/
1918 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1919 {
1920         struct e1000_phy_info *phy = &hw->phy;
1921         u32 phy_ctrl;
1922         s32 ret_val = 0;
1923         u16 data;
1924
1925         if (phy->type == e1000_phy_ife)
1926                 return ret_val;
1927
1928         phy_ctrl = er32(PHY_CTRL);
1929
1930         if (active) {
1931                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1932                 ew32(PHY_CTRL, phy_ctrl);
1933
1934                 if (phy->type != e1000_phy_igp_3)
1935                         return 0;
1936
1937                 /*
1938                  * Call gig speed drop workaround on LPLU before accessing
1939                  * any PHY registers
1940                  */
1941                 if (hw->mac.type == e1000_ich8lan)
1942                         e1000e_gig_downshift_workaround_ich8lan(hw);
1943
1944                 /* When LPLU is enabled, we should disable SmartSpeed */
1945                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1946                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1947                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1948                 if (ret_val)
1949                         return ret_val;
1950         } else {
1951                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1952                 ew32(PHY_CTRL, phy_ctrl);
1953
1954                 if (phy->type != e1000_phy_igp_3)
1955                         return 0;
1956
1957                 /*
1958                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1959                  * during Dx states where the power conservation is most
1960                  * important.  During driver activity we should enable
1961                  * SmartSpeed, so performance is maintained.
1962                  */
1963                 if (phy->smart_speed == e1000_smart_speed_on) {
1964                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1965                                            &data);
1966                         if (ret_val)
1967                                 return ret_val;
1968
1969                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1970                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1971                                            data);
1972                         if (ret_val)
1973                                 return ret_val;
1974                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1975                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1976                                            &data);
1977                         if (ret_val)
1978                                 return ret_val;
1979
1980                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1981                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1982                                            data);
1983                         if (ret_val)
1984                                 return ret_val;
1985                 }
1986         }
1987
1988         return 0;
1989 }
1990
1991 /**
1992  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1993  *  @hw: pointer to the HW structure
1994  *  @active: true to enable LPLU, false to disable
1995  *
1996  *  Sets the LPLU D3 state according to the active flag.  When
1997  *  activating LPLU this function also disables smart speed
1998  *  and vice versa.  LPLU will not be activated unless the
1999  *  device autonegotiation advertisement meets standards of
2000  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2001  *  This is a function pointer entry point only called by
2002  *  PHY setup routines.
2003  **/
2004 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2005 {
2006         struct e1000_phy_info *phy = &hw->phy;
2007         u32 phy_ctrl;
2008         s32 ret_val;
2009         u16 data;
2010
2011         phy_ctrl = er32(PHY_CTRL);
2012
2013         if (!active) {
2014                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2015                 ew32(PHY_CTRL, phy_ctrl);
2016
2017                 if (phy->type != e1000_phy_igp_3)
2018                         return 0;
2019
2020                 /*
2021                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2022                  * during Dx states where the power conservation is most
2023                  * important.  During driver activity we should enable
2024                  * SmartSpeed, so performance is maintained.
2025                  */
2026                 if (phy->smart_speed == e1000_smart_speed_on) {
2027                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2028                                            &data);
2029                         if (ret_val)
2030                                 return ret_val;
2031
2032                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2033                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2034                                            data);
2035                         if (ret_val)
2036                                 return ret_val;
2037                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2038                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2039                                            &data);
2040                         if (ret_val)
2041                                 return ret_val;
2042
2043                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2044                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2045                                            data);
2046                         if (ret_val)
2047                                 return ret_val;
2048                 }
2049         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2050                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2051                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2052                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2053                 ew32(PHY_CTRL, phy_ctrl);
2054
2055                 if (phy->type != e1000_phy_igp_3)
2056                         return 0;
2057
2058                 /*
2059                  * Call gig speed drop workaround on LPLU before accessing
2060                  * any PHY registers
2061                  */
2062                 if (hw->mac.type == e1000_ich8lan)
2063                         e1000e_gig_downshift_workaround_ich8lan(hw);
2064
2065                 /* When LPLU is enabled, we should disable SmartSpeed */
2066                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2067                 if (ret_val)
2068                         return ret_val;
2069
2070                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2071                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2072         }
2073
2074         return 0;
2075 }
2076
2077 /**
2078  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2079  *  @hw: pointer to the HW structure
2080  *  @bank:  pointer to the variable that returns the active bank
2081  *
2082  *  Reads signature byte from the NVM using the flash access registers.
2083  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2084  **/
2085 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2086 {
2087         u32 eecd;
2088         struct e1000_nvm_info *nvm = &hw->nvm;
2089         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2090         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2091         u8 sig_byte = 0;
2092         s32 ret_val = 0;
2093
2094         switch (hw->mac.type) {
2095         case e1000_ich8lan:
2096         case e1000_ich9lan:
2097                 eecd = er32(EECD);
2098                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2099                     E1000_EECD_SEC1VAL_VALID_MASK) {
2100                         if (eecd & E1000_EECD_SEC1VAL)
2101                                 *bank = 1;
2102                         else
2103                                 *bank = 0;
2104
2105                         return 0;
2106                 }
2107                 e_dbg("Unable to determine valid NVM bank via EEC - "
2108                        "reading flash signature\n");
2109                 /* fall-thru */
2110         default:
2111                 /* set bank to 0 in case flash read fails */
2112                 *bank = 0;
2113
2114                 /* Check bank 0 */
2115                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2116                                                         &sig_byte);
2117                 if (ret_val)
2118                         return ret_val;
2119                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2120                     E1000_ICH_NVM_SIG_VALUE) {
2121                         *bank = 0;
2122                         return 0;
2123                 }
2124
2125                 /* Check bank 1 */
2126                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2127                                                         bank1_offset,
2128                                                         &sig_byte);
2129                 if (ret_val)
2130                         return ret_val;
2131                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2132                     E1000_ICH_NVM_SIG_VALUE) {
2133                         *bank = 1;
2134                         return 0;
2135                 }
2136
2137                 e_dbg("ERROR: No valid NVM bank present\n");
2138                 return -E1000_ERR_NVM;
2139         }
2140
2141         return 0;
2142 }
2143
2144 /**
2145  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2146  *  @hw: pointer to the HW structure
2147  *  @offset: The offset (in bytes) of the word(s) to read.
2148  *  @words: Size of data to read in words
2149  *  @data: Pointer to the word(s) to read at offset.
2150  *
2151  *  Reads a word(s) from the NVM using the flash access registers.
2152  **/
2153 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2154                                   u16 *data)
2155 {
2156         struct e1000_nvm_info *nvm = &hw->nvm;
2157         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2158         u32 act_offset;
2159         s32 ret_val = 0;
2160         u32 bank = 0;
2161         u16 i, word;
2162
2163         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2164             (words == 0)) {
2165                 e_dbg("nvm parameter(s) out of bounds\n");
2166                 ret_val = -E1000_ERR_NVM;
2167                 goto out;
2168         }
2169
2170         nvm->ops.acquire(hw);
2171
2172         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2173         if (ret_val) {
2174                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2175                 bank = 0;
2176         }
2177
2178         act_offset = (bank) ? nvm->flash_bank_size : 0;
2179         act_offset += offset;
2180
2181         ret_val = 0;
2182         for (i = 0; i < words; i++) {
2183                 if (dev_spec->shadow_ram[offset+i].modified) {
2184                         data[i] = dev_spec->shadow_ram[offset+i].value;
2185                 } else {
2186                         ret_val = e1000_read_flash_word_ich8lan(hw,
2187                                                                 act_offset + i,
2188                                                                 &word);
2189                         if (ret_val)
2190                                 break;
2191                         data[i] = word;
2192                 }
2193         }
2194
2195         nvm->ops.release(hw);
2196
2197 out:
2198         if (ret_val)
2199                 e_dbg("NVM read error: %d\n", ret_val);
2200
2201         return ret_val;
2202 }
2203
2204 /**
2205  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2206  *  @hw: pointer to the HW structure
2207  *
2208  *  This function does initial flash setup so that a new read/write/erase cycle
2209  *  can be started.
2210  **/
2211 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2212 {
2213         union ich8_hws_flash_status hsfsts;
2214         s32 ret_val = -E1000_ERR_NVM;
2215
2216         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2217
2218         /* Check if the flash descriptor is valid */
2219         if (hsfsts.hsf_status.fldesvalid == 0) {
2220                 e_dbg("Flash descriptor invalid.  "
2221                          "SW Sequencing must be used.\n");
2222                 return -E1000_ERR_NVM;
2223         }
2224
2225         /* Clear FCERR and DAEL in hw status by writing 1 */
2226         hsfsts.hsf_status.flcerr = 1;
2227         hsfsts.hsf_status.dael = 1;
2228
2229         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2230
2231         /*
2232          * Either we should have a hardware SPI cycle in progress
2233          * bit to check against, in order to start a new cycle or
2234          * FDONE bit should be changed in the hardware so that it
2235          * is 1 after hardware reset, which can then be used as an
2236          * indication whether a cycle is in progress or has been
2237          * completed.
2238          */
2239
2240         if (hsfsts.hsf_status.flcinprog == 0) {
2241                 /*
2242                  * There is no cycle running at present,
2243                  * so we can start a cycle.
2244                  * Begin by setting Flash Cycle Done.
2245                  */
2246                 hsfsts.hsf_status.flcdone = 1;
2247                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2248                 ret_val = 0;
2249         } else {
2250                 s32 i = 0;
2251
2252                 /*
2253                  * Otherwise poll for sometime so the current
2254                  * cycle has a chance to end before giving up.
2255                  */
2256                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2257                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2258                         if (hsfsts.hsf_status.flcinprog == 0) {
2259                                 ret_val = 0;
2260                                 break;
2261                         }
2262                         udelay(1);
2263                 }
2264                 if (ret_val == 0) {
2265                         /*
2266                          * Successful in waiting for previous cycle to timeout,
2267                          * now set the Flash Cycle Done.
2268                          */
2269                         hsfsts.hsf_status.flcdone = 1;
2270                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2271                 } else {
2272                         e_dbg("Flash controller busy, cannot get access\n");
2273                 }
2274         }
2275
2276         return ret_val;
2277 }
2278
2279 /**
2280  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2281  *  @hw: pointer to the HW structure
2282  *  @timeout: maximum time to wait for completion
2283  *
2284  *  This function starts a flash cycle and waits for its completion.
2285  **/
2286 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2287 {
2288         union ich8_hws_flash_ctrl hsflctl;
2289         union ich8_hws_flash_status hsfsts;
2290         s32 ret_val = -E1000_ERR_NVM;
2291         u32 i = 0;
2292
2293         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2294         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2295         hsflctl.hsf_ctrl.flcgo = 1;
2296         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2297
2298         /* wait till FDONE bit is set to 1 */
2299         do {
2300                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2301                 if (hsfsts.hsf_status.flcdone == 1)
2302                         break;
2303                 udelay(1);
2304         } while (i++ < timeout);
2305
2306         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2307                 return 0;
2308
2309         return ret_val;
2310 }
2311
2312 /**
2313  *  e1000_read_flash_word_ich8lan - Read word from flash
2314  *  @hw: pointer to the HW structure
2315  *  @offset: offset to data location
2316  *  @data: pointer to the location for storing the data
2317  *
2318  *  Reads the flash word at offset into data.  Offset is converted
2319  *  to bytes before read.
2320  **/
2321 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2322                                          u16 *data)
2323 {
2324         /* Must convert offset into bytes. */
2325         offset <<= 1;
2326
2327         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2328 }
2329
2330 /**
2331  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2332  *  @hw: pointer to the HW structure
2333  *  @offset: The offset of the byte to read.
2334  *  @data: Pointer to a byte to store the value read.
2335  *
2336  *  Reads a single byte from the NVM using the flash access registers.
2337  **/
2338 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2339                                          u8 *data)
2340 {
2341         s32 ret_val;
2342         u16 word = 0;
2343
2344         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2345         if (ret_val)
2346                 return ret_val;
2347
2348         *data = (u8)word;
2349
2350         return 0;
2351 }
2352
2353 /**
2354  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2355  *  @hw: pointer to the HW structure
2356  *  @offset: The offset (in bytes) of the byte or word to read.
2357  *  @size: Size of data to read, 1=byte 2=word
2358  *  @data: Pointer to the word to store the value read.
2359  *
2360  *  Reads a byte or word from the NVM using the flash access registers.
2361  **/
2362 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2363                                          u8 size, u16 *data)
2364 {
2365         union ich8_hws_flash_status hsfsts;
2366         union ich8_hws_flash_ctrl hsflctl;
2367         u32 flash_linear_addr;
2368         u32 flash_data = 0;
2369         s32 ret_val = -E1000_ERR_NVM;
2370         u8 count = 0;
2371
2372         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2373                 return -E1000_ERR_NVM;
2374
2375         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2376                             hw->nvm.flash_base_addr;
2377
2378         do {
2379                 udelay(1);
2380                 /* Steps */
2381                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2382                 if (ret_val != 0)
2383                         break;
2384
2385                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2386                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2387                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2388                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2389                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2390
2391                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2392
2393                 ret_val = e1000_flash_cycle_ich8lan(hw,
2394                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2395
2396                 /*
2397                  * Check if FCERR is set to 1, if set to 1, clear it
2398                  * and try the whole sequence a few more times, else
2399                  * read in (shift in) the Flash Data0, the order is
2400                  * least significant byte first msb to lsb
2401                  */
2402                 if (ret_val == 0) {
2403                         flash_data = er32flash(ICH_FLASH_FDATA0);
2404                         if (size == 1)
2405                                 *data = (u8)(flash_data & 0x000000FF);
2406                         else if (size == 2)
2407                                 *data = (u16)(flash_data & 0x0000FFFF);
2408                         break;
2409                 } else {
2410                         /*
2411                          * If we've gotten here, then things are probably
2412                          * completely hosed, but if the error condition is
2413                          * detected, it won't hurt to give it another try...
2414                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2415                          */
2416                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2417                         if (hsfsts.hsf_status.flcerr == 1) {
2418                                 /* Repeat for some time before giving up. */
2419                                 continue;
2420                         } else if (hsfsts.hsf_status.flcdone == 0) {
2421                                 e_dbg("Timeout error - flash cycle "
2422                                          "did not complete.\n");
2423                                 break;
2424                         }
2425                 }
2426         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2427
2428         return ret_val;
2429 }
2430
2431 /**
2432  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2433  *  @hw: pointer to the HW structure
2434  *  @offset: The offset (in bytes) of the word(s) to write.
2435  *  @words: Size of data to write in words
2436  *  @data: Pointer to the word(s) to write at offset.
2437  *
2438  *  Writes a byte or word to the NVM using the flash access registers.
2439  **/
2440 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2441                                    u16 *data)
2442 {
2443         struct e1000_nvm_info *nvm = &hw->nvm;
2444         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2445         u16 i;
2446
2447         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2448             (words == 0)) {
2449                 e_dbg("nvm parameter(s) out of bounds\n");
2450                 return -E1000_ERR_NVM;
2451         }
2452
2453         nvm->ops.acquire(hw);
2454
2455         for (i = 0; i < words; i++) {
2456                 dev_spec->shadow_ram[offset+i].modified = true;
2457                 dev_spec->shadow_ram[offset+i].value = data[i];
2458         }
2459
2460         nvm->ops.release(hw);
2461
2462         return 0;
2463 }
2464
2465 /**
2466  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2467  *  @hw: pointer to the HW structure
2468  *
2469  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2470  *  which writes the checksum to the shadow ram.  The changes in the shadow
2471  *  ram are then committed to the EEPROM by processing each bank at a time
2472  *  checking for the modified bit and writing only the pending changes.
2473  *  After a successful commit, the shadow ram is cleared and is ready for
2474  *  future writes.
2475  **/
2476 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2477 {
2478         struct e1000_nvm_info *nvm = &hw->nvm;
2479         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2480         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2481         s32 ret_val;
2482         u16 data;
2483
2484         ret_val = e1000e_update_nvm_checksum_generic(hw);
2485         if (ret_val)
2486                 goto out;
2487
2488         if (nvm->type != e1000_nvm_flash_sw)
2489                 goto out;
2490
2491         nvm->ops.acquire(hw);
2492
2493         /*
2494          * We're writing to the opposite bank so if we're on bank 1,
2495          * write to bank 0 etc.  We also need to erase the segment that
2496          * is going to be written
2497          */
2498         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2499         if (ret_val) {
2500                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2501                 bank = 0;
2502         }
2503
2504         if (bank == 0) {
2505                 new_bank_offset = nvm->flash_bank_size;
2506                 old_bank_offset = 0;
2507                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2508                 if (ret_val)
2509                         goto release;
2510         } else {
2511                 old_bank_offset = nvm->flash_bank_size;
2512                 new_bank_offset = 0;
2513                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2514                 if (ret_val)
2515                         goto release;
2516         }
2517
2518         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2519                 /*
2520                  * Determine whether to write the value stored
2521                  * in the other NVM bank or a modified value stored
2522                  * in the shadow RAM
2523                  */
2524                 if (dev_spec->shadow_ram[i].modified) {
2525                         data = dev_spec->shadow_ram[i].value;
2526                 } else {
2527                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2528                                                                 old_bank_offset,
2529                                                                 &data);
2530                         if (ret_val)
2531                                 break;
2532                 }
2533
2534                 /*
2535                  * If the word is 0x13, then make sure the signature bits
2536                  * (15:14) are 11b until the commit has completed.
2537                  * This will allow us to write 10b which indicates the
2538                  * signature is valid.  We want to do this after the write
2539                  * has completed so that we don't mark the segment valid
2540                  * while the write is still in progress
2541                  */
2542                 if (i == E1000_ICH_NVM_SIG_WORD)
2543                         data |= E1000_ICH_NVM_SIG_MASK;
2544
2545                 /* Convert offset to bytes. */
2546                 act_offset = (i + new_bank_offset) << 1;
2547
2548                 udelay(100);
2549                 /* Write the bytes to the new bank. */
2550                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2551                                                                act_offset,
2552                                                                (u8)data);
2553                 if (ret_val)
2554                         break;
2555
2556                 udelay(100);
2557                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2558                                                           act_offset + 1,
2559                                                           (u8)(data >> 8));
2560                 if (ret_val)
2561                         break;
2562         }
2563
2564         /*
2565          * Don't bother writing the segment valid bits if sector
2566          * programming failed.
2567          */
2568         if (ret_val) {
2569                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2570                 e_dbg("Flash commit failed.\n");
2571                 goto release;
2572         }
2573
2574         /*
2575          * Finally validate the new segment by setting bit 15:14
2576          * to 10b in word 0x13 , this can be done without an
2577          * erase as well since these bits are 11 to start with
2578          * and we need to change bit 14 to 0b
2579          */
2580         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2581         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2582         if (ret_val)
2583                 goto release;
2584
2585         data &= 0xBFFF;
2586         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2587                                                        act_offset * 2 + 1,
2588                                                        (u8)(data >> 8));
2589         if (ret_val)
2590                 goto release;
2591
2592         /*
2593          * And invalidate the previously valid segment by setting
2594          * its signature word (0x13) high_byte to 0b. This can be
2595          * done without an erase because flash erase sets all bits
2596          * to 1's. We can write 1's to 0's without an erase
2597          */
2598         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2599         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2600         if (ret_val)
2601                 goto release;
2602
2603         /* Great!  Everything worked, we can now clear the cached entries. */
2604         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2605                 dev_spec->shadow_ram[i].modified = false;
2606                 dev_spec->shadow_ram[i].value = 0xFFFF;
2607         }
2608
2609 release:
2610         nvm->ops.release(hw);
2611
2612         /*
2613          * Reload the EEPROM, or else modifications will not appear
2614          * until after the next adapter reset.
2615          */
2616         if (!ret_val) {
2617                 e1000e_reload_nvm(hw);
2618                 usleep_range(10000, 20000);
2619         }
2620
2621 out:
2622         if (ret_val)
2623                 e_dbg("NVM update error: %d\n", ret_val);
2624
2625         return ret_val;
2626 }
2627
2628 /**
2629  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2630  *  @hw: pointer to the HW structure
2631  *
2632  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2633  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2634  *  calculated, in which case we need to calculate the checksum and set bit 6.
2635  **/
2636 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2637 {
2638         s32 ret_val;
2639         u16 data;
2640
2641         /*
2642          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2643          * needs to be fixed.  This bit is an indication that the NVM
2644          * was prepared by OEM software and did not calculate the
2645          * checksum...a likely scenario.
2646          */
2647         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2648         if (ret_val)
2649                 return ret_val;
2650
2651         if ((data & 0x40) == 0) {
2652                 data |= 0x40;
2653                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2654                 if (ret_val)
2655                         return ret_val;
2656                 ret_val = e1000e_update_nvm_checksum(hw);
2657                 if (ret_val)
2658                         return ret_val;
2659         }
2660
2661         return e1000e_validate_nvm_checksum_generic(hw);
2662 }
2663
2664 /**
2665  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2666  *  @hw: pointer to the HW structure
2667  *
2668  *  To prevent malicious write/erase of the NVM, set it to be read-only
2669  *  so that the hardware ignores all write/erase cycles of the NVM via
2670  *  the flash control registers.  The shadow-ram copy of the NVM will
2671  *  still be updated, however any updates to this copy will not stick
2672  *  across driver reloads.
2673  **/
2674 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2675 {
2676         struct e1000_nvm_info *nvm = &hw->nvm;
2677         union ich8_flash_protected_range pr0;
2678         union ich8_hws_flash_status hsfsts;
2679         u32 gfpreg;
2680
2681         nvm->ops.acquire(hw);
2682
2683         gfpreg = er32flash(ICH_FLASH_GFPREG);
2684
2685         /* Write-protect GbE Sector of NVM */
2686         pr0.regval = er32flash(ICH_FLASH_PR0);
2687         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2688         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2689         pr0.range.wpe = true;
2690         ew32flash(ICH_FLASH_PR0, pr0.regval);
2691
2692         /*
2693          * Lock down a subset of GbE Flash Control Registers, e.g.
2694          * PR0 to prevent the write-protection from being lifted.
2695          * Once FLOCKDN is set, the registers protected by it cannot
2696          * be written until FLOCKDN is cleared by a hardware reset.
2697          */
2698         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2699         hsfsts.hsf_status.flockdn = true;
2700         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2701
2702         nvm->ops.release(hw);
2703 }
2704
2705 /**
2706  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2707  *  @hw: pointer to the HW structure
2708  *  @offset: The offset (in bytes) of the byte/word to read.
2709  *  @size: Size of data to read, 1=byte 2=word
2710  *  @data: The byte(s) to write to the NVM.
2711  *
2712  *  Writes one/two bytes to the NVM using the flash access registers.
2713  **/
2714 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2715                                           u8 size, u16 data)
2716 {
2717         union ich8_hws_flash_status hsfsts;
2718         union ich8_hws_flash_ctrl hsflctl;
2719         u32 flash_linear_addr;
2720         u32 flash_data = 0;
2721         s32 ret_val;
2722         u8 count = 0;
2723
2724         if (size < 1 || size > 2 || data > size * 0xff ||
2725             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2726                 return -E1000_ERR_NVM;
2727
2728         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2729                             hw->nvm.flash_base_addr;
2730
2731         do {
2732                 udelay(1);
2733                 /* Steps */
2734                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2735                 if (ret_val)
2736                         break;
2737
2738                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2739                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2740                 hsflctl.hsf_ctrl.fldbcount = size -1;
2741                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2742                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2743
2744                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2745
2746                 if (size == 1)
2747                         flash_data = (u32)data & 0x00FF;
2748                 else
2749                         flash_data = (u32)data;
2750
2751                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2752
2753                 /*
2754                  * check if FCERR is set to 1 , if set to 1, clear it
2755                  * and try the whole sequence a few more times else done
2756                  */
2757                 ret_val = e1000_flash_cycle_ich8lan(hw,
2758                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2759                 if (!ret_val)
2760                         break;
2761
2762                 /*
2763                  * If we're here, then things are most likely
2764                  * completely hosed, but if the error condition
2765                  * is detected, it won't hurt to give it another
2766                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2767                  */
2768                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2769                 if (hsfsts.hsf_status.flcerr == 1)
2770                         /* Repeat for some time before giving up. */
2771                         continue;
2772                 if (hsfsts.hsf_status.flcdone == 0) {
2773                         e_dbg("Timeout error - flash cycle "
2774                                  "did not complete.");
2775                         break;
2776                 }
2777         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2778
2779         return ret_val;
2780 }
2781
2782 /**
2783  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2784  *  @hw: pointer to the HW structure
2785  *  @offset: The index of the byte to read.
2786  *  @data: The byte to write to the NVM.
2787  *
2788  *  Writes a single byte to the NVM using the flash access registers.
2789  **/
2790 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2791                                           u8 data)
2792 {
2793         u16 word = (u16)data;
2794
2795         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2796 }
2797
2798 /**
2799  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2800  *  @hw: pointer to the HW structure
2801  *  @offset: The offset of the byte to write.
2802  *  @byte: The byte to write to the NVM.
2803  *
2804  *  Writes a single byte to the NVM using the flash access registers.
2805  *  Goes through a retry algorithm before giving up.
2806  **/
2807 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2808                                                 u32 offset, u8 byte)
2809 {
2810         s32 ret_val;
2811         u16 program_retries;
2812
2813         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2814         if (!ret_val)
2815                 return ret_val;
2816
2817         for (program_retries = 0; program_retries < 100; program_retries++) {
2818                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2819                 udelay(100);
2820                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2821                 if (!ret_val)
2822                         break;
2823         }
2824         if (program_retries == 100)
2825                 return -E1000_ERR_NVM;
2826
2827         return 0;
2828 }
2829
2830 /**
2831  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2832  *  @hw: pointer to the HW structure
2833  *  @bank: 0 for first bank, 1 for second bank, etc.
2834  *
2835  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2836  *  bank N is 4096 * N + flash_reg_addr.
2837  **/
2838 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2839 {
2840         struct e1000_nvm_info *nvm = &hw->nvm;
2841         union ich8_hws_flash_status hsfsts;
2842         union ich8_hws_flash_ctrl hsflctl;
2843         u32 flash_linear_addr;
2844         /* bank size is in 16bit words - adjust to bytes */
2845         u32 flash_bank_size = nvm->flash_bank_size * 2;
2846         s32 ret_val;
2847         s32 count = 0;
2848         s32 j, iteration, sector_size;
2849
2850         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2851
2852         /*
2853          * Determine HW Sector size: Read BERASE bits of hw flash status
2854          * register
2855          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2856          *     consecutive sectors.  The start index for the nth Hw sector
2857          *     can be calculated as = bank * 4096 + n * 256
2858          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2859          *     The start index for the nth Hw sector can be calculated
2860          *     as = bank * 4096
2861          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2862          *     (ich9 only, otherwise error condition)
2863          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2864          */
2865         switch (hsfsts.hsf_status.berasesz) {
2866         case 0:
2867                 /* Hw sector size 256 */
2868                 sector_size = ICH_FLASH_SEG_SIZE_256;
2869                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2870                 break;
2871         case 1:
2872                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2873                 iteration = 1;
2874                 break;
2875         case 2:
2876                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2877                 iteration = 1;
2878                 break;
2879         case 3:
2880                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2881                 iteration = 1;
2882                 break;
2883         default:
2884                 return -E1000_ERR_NVM;
2885         }
2886
2887         /* Start with the base address, then add the sector offset. */
2888         flash_linear_addr = hw->nvm.flash_base_addr;
2889         flash_linear_addr += (bank) ? flash_bank_size : 0;
2890
2891         for (j = 0; j < iteration ; j++) {
2892                 do {
2893                         /* Steps */
2894                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2895                         if (ret_val)
2896                                 return ret_val;
2897
2898                         /*
2899                          * Write a value 11 (block Erase) in Flash
2900                          * Cycle field in hw flash control
2901                          */
2902                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2903                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2904                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2905
2906                         /*
2907                          * Write the last 24 bits of an index within the
2908                          * block into Flash Linear address field in Flash
2909                          * Address.
2910                          */
2911                         flash_linear_addr += (j * sector_size);
2912                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2913
2914                         ret_val = e1000_flash_cycle_ich8lan(hw,
2915                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2916                         if (ret_val == 0)
2917                                 break;
2918
2919                         /*
2920                          * Check if FCERR is set to 1.  If 1,
2921                          * clear it and try the whole sequence
2922                          * a few more times else Done
2923                          */
2924                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2925                         if (hsfsts.hsf_status.flcerr == 1)
2926                                 /* repeat for some time before giving up */
2927                                 continue;
2928                         else if (hsfsts.hsf_status.flcdone == 0)
2929                                 return ret_val;
2930                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2931         }
2932
2933         return 0;
2934 }
2935
2936 /**
2937  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2938  *  @hw: pointer to the HW structure
2939  *  @data: Pointer to the LED settings
2940  *
2941  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2942  *  settings is all 0's or F's, set the LED default to a valid LED default
2943  *  setting.
2944  **/
2945 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2946 {
2947         s32 ret_val;
2948
2949         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2950         if (ret_val) {
2951                 e_dbg("NVM Read Error\n");
2952                 return ret_val;
2953         }
2954
2955         if (*data == ID_LED_RESERVED_0000 ||
2956             *data == ID_LED_RESERVED_FFFF)
2957                 *data = ID_LED_DEFAULT_ICH8LAN;
2958
2959         return 0;
2960 }
2961
2962 /**
2963  *  e1000_id_led_init_pchlan - store LED configurations
2964  *  @hw: pointer to the HW structure
2965  *
2966  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2967  *  the PHY LED configuration register.
2968  *
2969  *  PCH also does not have an "always on" or "always off" mode which
2970  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2971  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2972  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2973  *  link based on logic in e1000_led_[on|off]_pchlan().
2974  **/
2975 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2976 {
2977         struct e1000_mac_info *mac = &hw->mac;
2978         s32 ret_val;
2979         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2980         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2981         u16 data, i, temp, shift;
2982
2983         /* Get default ID LED modes */
2984         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2985         if (ret_val)
2986                 goto out;
2987
2988         mac->ledctl_default = er32(LEDCTL);
2989         mac->ledctl_mode1 = mac->ledctl_default;
2990         mac->ledctl_mode2 = mac->ledctl_default;
2991
2992         for (i = 0; i < 4; i++) {
2993                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2994                 shift = (i * 5);
2995                 switch (temp) {
2996                 case ID_LED_ON1_DEF2:
2997                 case ID_LED_ON1_ON2:
2998                 case ID_LED_ON1_OFF2:
2999                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3000                         mac->ledctl_mode1 |= (ledctl_on << shift);
3001                         break;
3002                 case ID_LED_OFF1_DEF2:
3003                 case ID_LED_OFF1_ON2:
3004                 case ID_LED_OFF1_OFF2:
3005                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3006                         mac->ledctl_mode1 |= (ledctl_off << shift);
3007                         break;
3008                 default:
3009                         /* Do nothing */
3010                         break;
3011                 }
3012                 switch (temp) {
3013                 case ID_LED_DEF1_ON2:
3014                 case ID_LED_ON1_ON2:
3015                 case ID_LED_OFF1_ON2:
3016                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3017                         mac->ledctl_mode2 |= (ledctl_on << shift);
3018                         break;
3019                 case ID_LED_DEF1_OFF2:
3020                 case ID_LED_ON1_OFF2:
3021                 case ID_LED_OFF1_OFF2:
3022                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3023                         mac->ledctl_mode2 |= (ledctl_off << shift);
3024                         break;
3025                 default:
3026                         /* Do nothing */
3027                         break;
3028                 }
3029         }
3030
3031 out:
3032         return ret_val;
3033 }
3034
3035 /**
3036  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3037  *  @hw: pointer to the HW structure
3038  *
3039  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3040  *  register, so the the bus width is hard coded.
3041  **/
3042 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3043 {
3044         struct e1000_bus_info *bus = &hw->bus;
3045         s32 ret_val;
3046
3047         ret_val = e1000e_get_bus_info_pcie(hw);
3048
3049         /*
3050          * ICH devices are "PCI Express"-ish.  They have
3051          * a configuration space, but do not contain
3052          * PCI Express Capability registers, so bus width
3053          * must be hardcoded.
3054          */
3055         if (bus->width == e1000_bus_width_unknown)
3056                 bus->width = e1000_bus_width_pcie_x1;
3057
3058         return ret_val;
3059 }
3060
3061 /**
3062  *  e1000_reset_hw_ich8lan - Reset the hardware
3063  *  @hw: pointer to the HW structure
3064  *
3065  *  Does a full reset of the hardware which includes a reset of the PHY and
3066  *  MAC.
3067  **/
3068 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3069 {
3070         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3071         u16 reg;
3072         u32 ctrl, kab;
3073         s32 ret_val;
3074
3075         /*
3076          * Prevent the PCI-E bus from sticking if there is no TLP connection
3077          * on the last TLP read/write transaction when MAC is reset.
3078          */
3079         ret_val = e1000e_disable_pcie_master(hw);
3080         if (ret_val)
3081                 e_dbg("PCI-E Master disable polling has failed.\n");
3082
3083         e_dbg("Masking off all interrupts\n");
3084         ew32(IMC, 0xffffffff);
3085
3086         /*
3087          * Disable the Transmit and Receive units.  Then delay to allow
3088          * any pending transactions to complete before we hit the MAC
3089          * with the global reset.
3090          */
3091         ew32(RCTL, 0);
3092         ew32(TCTL, E1000_TCTL_PSP);
3093         e1e_flush();
3094
3095         usleep_range(10000, 20000);
3096
3097         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3098         if (hw->mac.type == e1000_ich8lan) {
3099                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3100                 ew32(PBA, E1000_PBA_8K);
3101                 /* Set Packet Buffer Size to 16k. */
3102                 ew32(PBS, E1000_PBS_16K);
3103         }
3104
3105         if (hw->mac.type == e1000_pchlan) {
3106                 /* Save the NVM K1 bit setting*/
3107                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3108                 if (ret_val)
3109                         return ret_val;
3110
3111                 if (reg & E1000_NVM_K1_ENABLE)
3112                         dev_spec->nvm_k1_enabled = true;
3113                 else
3114                         dev_spec->nvm_k1_enabled = false;
3115         }
3116
3117         ctrl = er32(CTRL);
3118
3119         if (!e1000_check_reset_block(hw)) {
3120                 /*
3121                  * Full-chip reset requires MAC and PHY reset at the same
3122                  * time to make sure the interface between MAC and the
3123                  * external PHY is reset.
3124                  */
3125                 ctrl |= E1000_CTRL_PHY_RST;
3126
3127                 /*
3128                  * Gate automatic PHY configuration by hardware on
3129                  * non-managed 82579
3130                  */
3131                 if ((hw->mac.type == e1000_pch2lan) &&
3132                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3133                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3134         }
3135         ret_val = e1000_acquire_swflag_ich8lan(hw);
3136         e_dbg("Issuing a global reset to ich8lan\n");
3137         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3138         /* cannot issue a flush here because it hangs the hardware */
3139         msleep(20);
3140
3141         if (!ret_val)
3142                 mutex_unlock(&swflag_mutex);
3143
3144         if (ctrl & E1000_CTRL_PHY_RST) {
3145                 ret_val = hw->phy.ops.get_cfg_done(hw);
3146                 if (ret_val)
3147                         goto out;
3148
3149                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3150                 if (ret_val)
3151                         goto out;
3152         }
3153
3154         /*
3155          * For PCH, this write will make sure that any noise
3156          * will be detected as a CRC error and be dropped rather than show up
3157          * as a bad packet to the DMA engine.
3158          */
3159         if (hw->mac.type == e1000_pchlan)
3160                 ew32(CRC_OFFSET, 0x65656565);
3161
3162         ew32(IMC, 0xffffffff);
3163         er32(ICR);
3164
3165         kab = er32(KABGTXD);
3166         kab |= E1000_KABGTXD_BGSQLBIAS;
3167         ew32(KABGTXD, kab);
3168
3169 out:
3170         return ret_val;
3171 }
3172
3173 /**
3174  *  e1000_init_hw_ich8lan - Initialize the hardware
3175  *  @hw: pointer to the HW structure
3176  *
3177  *  Prepares the hardware for transmit and receive by doing the following:
3178  *   - initialize hardware bits
3179  *   - initialize LED identification
3180  *   - setup receive address registers
3181  *   - setup flow control
3182  *   - setup transmit descriptors
3183  *   - clear statistics
3184  **/
3185 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3186 {
3187         struct e1000_mac_info *mac = &hw->mac;
3188         u32 ctrl_ext, txdctl, snoop;
3189         s32 ret_val;
3190         u16 i;
3191
3192         e1000_initialize_hw_bits_ich8lan(hw);
3193
3194         /* Initialize identification LED */
3195         ret_val = mac->ops.id_led_init(hw);
3196         if (ret_val)
3197                 e_dbg("Error initializing identification LED\n");
3198                 /* This is not fatal and we should not stop init due to this */
3199
3200         /* Setup the receive address. */
3201         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3202
3203         /* Zero out the Multicast HASH table */
3204         e_dbg("Zeroing the MTA\n");
3205         for (i = 0; i < mac->mta_reg_count; i++)
3206                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3207
3208         /*
3209          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3210          * the ME.  Disable wakeup by clearing the host wakeup bit.
3211          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3212          */
3213         if (hw->phy.type == e1000_phy_82578) {
3214                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3215                 i &= ~BM_WUC_HOST_WU_BIT;
3216                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3217                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3218                 if (ret_val)
3219                         return ret_val;
3220         }
3221
3222         /* Setup link and flow control */
3223         ret_val = e1000_setup_link_ich8lan(hw);
3224
3225         /* Set the transmit descriptor write-back policy for both queues */
3226         txdctl = er32(TXDCTL(0));
3227         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3228                  E1000_TXDCTL_FULL_TX_DESC_WB;
3229         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3230                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3231         ew32(TXDCTL(0), txdctl);
3232         txdctl = er32(TXDCTL(1));
3233         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3234                  E1000_TXDCTL_FULL_TX_DESC_WB;
3235         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3236                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3237         ew32(TXDCTL(1), txdctl);
3238
3239         /*
3240          * ICH8 has opposite polarity of no_snoop bits.
3241          * By default, we should use snoop behavior.
3242          */
3243         if (mac->type == e1000_ich8lan)
3244                 snoop = PCIE_ICH8_SNOOP_ALL;
3245         else
3246                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3247         e1000e_set_pcie_no_snoop(hw, snoop);
3248
3249         ctrl_ext = er32(CTRL_EXT);
3250         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3251         ew32(CTRL_EXT, ctrl_ext);
3252
3253         /*
3254          * Clear all of the statistics registers (clear on read).  It is
3255          * important that we do this after we have tried to establish link
3256          * because the symbol error count will increment wildly if there
3257          * is no link.
3258          */
3259         e1000_clear_hw_cntrs_ich8lan(hw);
3260
3261         return 0;
3262 }
3263 /**
3264  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3265  *  @hw: pointer to the HW structure
3266  *
3267  *  Sets/Clears required hardware bits necessary for correctly setting up the
3268  *  hardware for transmit and receive.
3269  **/
3270 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3271 {
3272         u32 reg;
3273
3274         /* Extended Device Control */
3275         reg = er32(CTRL_EXT);
3276         reg |= (1 << 22);
3277         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3278         if (hw->mac.type >= e1000_pchlan)
3279                 reg |= E1000_CTRL_EXT_PHYPDEN;
3280         ew32(CTRL_EXT, reg);
3281
3282         /* Transmit Descriptor Control 0 */
3283         reg = er32(TXDCTL(0));
3284         reg |= (1 << 22);
3285         ew32(TXDCTL(0), reg);
3286
3287         /* Transmit Descriptor Control 1 */
3288         reg = er32(TXDCTL(1));
3289         reg |= (1 << 22);
3290         ew32(TXDCTL(1), reg);
3291
3292         /* Transmit Arbitration Control 0 */
3293         reg = er32(TARC(0));
3294         if (hw->mac.type == e1000_ich8lan)
3295                 reg |= (1 << 28) | (1 << 29);
3296         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3297         ew32(TARC(0), reg);
3298
3299         /* Transmit Arbitration Control 1 */
3300         reg = er32(TARC(1));
3301         if (er32(TCTL) & E1000_TCTL_MULR)
3302                 reg &= ~(1 << 28);
3303         else
3304                 reg |= (1 << 28);
3305         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3306         ew32(TARC(1), reg);
3307
3308         /* Device Status */
3309         if (hw->mac.type == e1000_ich8lan) {
3310                 reg = er32(STATUS);
3311                 reg &= ~(1 << 31);
3312                 ew32(STATUS, reg);
3313         }
3314
3315         /*
3316          * work-around descriptor data corruption issue during nfs v2 udp
3317          * traffic, just disable the nfs filtering capability
3318          */
3319         reg = er32(RFCTL);
3320         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3321         ew32(RFCTL, reg);
3322 }
3323
3324 /**
3325  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3326  *  @hw: pointer to the HW structure
3327  *
3328  *  Determines which flow control settings to use, then configures flow
3329  *  control.  Calls the appropriate media-specific link configuration
3330  *  function.  Assuming the adapter has a valid link partner, a valid link
3331  *  should be established.  Assumes the hardware has previously been reset
3332  *  and the transmitter and receiver are not enabled.
3333  **/
3334 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3335 {
3336         s32 ret_val;
3337
3338         if (e1000_check_reset_block(hw))
3339                 return 0;
3340
3341         /*
3342          * ICH parts do not have a word in the NVM to determine
3343          * the default flow control setting, so we explicitly
3344          * set it to full.
3345          */
3346         if (hw->fc.requested_mode == e1000_fc_default) {
3347                 /* Workaround h/w hang when Tx flow control enabled */
3348                 if (hw->mac.type == e1000_pchlan)
3349                         hw->fc.requested_mode = e1000_fc_rx_pause;
3350                 else
3351                         hw->fc.requested_mode = e1000_fc_full;
3352         }
3353
3354         /*
3355          * Save off the requested flow control mode for use later.  Depending
3356          * on the link partner's capabilities, we may or may not use this mode.
3357          */
3358         hw->fc.current_mode = hw->fc.requested_mode;
3359
3360         e_dbg("After fix-ups FlowControl is now = %x\n",
3361                 hw->fc.current_mode);
3362
3363         /* Continue to configure the copper link. */
3364         ret_val = e1000_setup_copper_link_ich8lan(hw);
3365         if (ret_val)
3366                 return ret_val;
3367
3368         ew32(FCTTV, hw->fc.pause_time);
3369         if ((hw->phy.type == e1000_phy_82578) ||
3370             (hw->phy.type == e1000_phy_82579) ||
3371             (hw->phy.type == e1000_phy_82577)) {
3372                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3373
3374                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3375                                    hw->fc.pause_time);
3376                 if (ret_val)
3377                         return ret_val;
3378         }
3379
3380         return e1000e_set_fc_watermarks(hw);
3381 }
3382
3383 /**
3384  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3385  *  @hw: pointer to the HW structure
3386  *
3387  *  Configures the kumeran interface to the PHY to wait the appropriate time
3388  *  when polling the PHY, then call the generic setup_copper_link to finish
3389  *  configuring the copper link.
3390  **/
3391 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3392 {
3393         u32 ctrl;
3394         s32 ret_val;
3395         u16 reg_data;
3396
3397         ctrl = er32(CTRL);
3398         ctrl |= E1000_CTRL_SLU;
3399         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3400         ew32(CTRL, ctrl);
3401
3402         /*
3403          * Set the mac to wait the maximum time between each iteration
3404          * and increase the max iterations when polling the phy;
3405          * this fixes erroneous timeouts at 10Mbps.
3406          */
3407         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3408         if (ret_val)
3409                 return ret_val;
3410         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3411                                        &reg_data);
3412         if (ret_val)
3413                 return ret_val;
3414         reg_data |= 0x3F;
3415         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3416                                         reg_data);
3417         if (ret_val)
3418                 return ret_val;
3419
3420         switch (hw->phy.type) {
3421         case e1000_phy_igp_3:
3422                 ret_val = e1000e_copper_link_setup_igp(hw);
3423                 if (ret_val)
3424                         return ret_val;
3425                 break;
3426         case e1000_phy_bm:
3427         case e1000_phy_82578:
3428                 ret_val = e1000e_copper_link_setup_m88(hw);
3429                 if (ret_val)
3430                         return ret_val;
3431                 break;
3432         case e1000_phy_82577:
3433         case e1000_phy_82579:
3434                 ret_val = e1000_copper_link_setup_82577(hw);
3435                 if (ret_val)
3436                         return ret_val;
3437                 break;
3438         case e1000_phy_ife:
3439                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3440                 if (ret_val)
3441                         return ret_val;
3442
3443                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3444
3445                 switch (hw->phy.mdix) {
3446                 case 1:
3447                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3448                         break;
3449                 case 2:
3450                         reg_data |= IFE_PMC_FORCE_MDIX;
3451                         break;
3452                 case 0:
3453                 default:
3454                         reg_data |= IFE_PMC_AUTO_MDIX;
3455                         break;
3456                 }
3457                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3458                 if (ret_val)
3459                         return ret_val;
3460                 break;
3461         default:
3462                 break;
3463         }
3464         return e1000e_setup_copper_link(hw);
3465 }
3466
3467 /**
3468  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3469  *  @hw: pointer to the HW structure
3470  *  @speed: pointer to store current link speed
3471  *  @duplex: pointer to store the current link duplex
3472  *
3473  *  Calls the generic get_speed_and_duplex to retrieve the current link
3474  *  information and then calls the Kumeran lock loss workaround for links at
3475  *  gigabit speeds.
3476  **/
3477 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3478                                           u16 *duplex)
3479 {
3480         s32 ret_val;
3481
3482         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3483         if (ret_val)
3484                 return ret_val;
3485
3486         if ((hw->mac.type == e1000_ich8lan) &&
3487             (hw->phy.type == e1000_phy_igp_3) &&
3488             (*speed == SPEED_1000)) {
3489                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3490         }
3491
3492         return ret_val;
3493 }
3494
3495 /**
3496  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3497  *  @hw: pointer to the HW structure
3498  *
3499  *  Work-around for 82566 Kumeran PCS lock loss:
3500  *  On link status change (i.e. PCI reset, speed change) and link is up and
3501  *  speed is gigabit-
3502  *    0) if workaround is optionally disabled do nothing
3503  *    1) wait 1ms for Kumeran link to come up
3504  *    2) check Kumeran Diagnostic register PCS lock loss bit
3505  *    3) if not set the link is locked (all is good), otherwise...
3506  *    4) reset the PHY
3507  *    5) repeat up to 10 times
3508  *  Note: this is only called for IGP3 copper when speed is 1gb.
3509  **/
3510 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3511 {
3512         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3513         u32 phy_ctrl;
3514         s32 ret_val;
3515         u16 i, data;
3516         bool link;
3517
3518         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3519                 return 0;
3520
3521         /*
3522          * Make sure link is up before proceeding.  If not just return.
3523          * Attempting this while link is negotiating fouled up link
3524          * stability
3525          */
3526         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3527         if (!link)
3528                 return 0;
3529
3530         for (i = 0; i < 10; i++) {
3531                 /* read once to clear */
3532                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3533                 if (ret_val)
3534                         return ret_val;
3535                 /* and again to get new status */
3536                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3537                 if (ret_val)
3538                         return ret_val;
3539
3540                 /* check for PCS lock */
3541                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3542                         return 0;
3543
3544                 /* Issue PHY reset */
3545                 e1000_phy_hw_reset(hw);
3546                 mdelay(5);
3547         }
3548         /* Disable GigE link negotiation */
3549         phy_ctrl = er32(PHY_CTRL);
3550         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3551                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3552         ew32(PHY_CTRL, phy_ctrl);
3553
3554         /*
3555          * Call gig speed drop workaround on Gig disable before accessing
3556          * any PHY registers
3557          */
3558         e1000e_gig_downshift_workaround_ich8lan(hw);
3559
3560         /* unable to acquire PCS lock */
3561         return -E1000_ERR_PHY;
3562 }
3563
3564 /**
3565  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3566  *  @hw: pointer to the HW structure
3567  *  @state: boolean value used to set the current Kumeran workaround state
3568  *
3569  *  If ICH8, set the current Kumeran workaround state (enabled - true
3570  *  /disabled - false).
3571  **/
3572 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3573                                                  bool state)
3574 {
3575         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3576
3577         if (hw->mac.type != e1000_ich8lan) {
3578                 e_dbg("Workaround applies to ICH8 only.\n");
3579                 return;
3580         }
3581
3582         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3583 }
3584
3585 /**
3586  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3587  *  @hw: pointer to the HW structure
3588  *
3589  *  Workaround for 82566 power-down on D3 entry:
3590  *    1) disable gigabit link
3591  *    2) write VR power-down enable
3592  *    3) read it back
3593  *  Continue if successful, else issue LCD reset and repeat
3594  **/
3595 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3596 {
3597         u32 reg;
3598         u16 data;
3599         u8  retry = 0;
3600
3601         if (hw->phy.type != e1000_phy_igp_3)
3602                 return;
3603
3604         /* Try the workaround twice (if needed) */
3605         do {
3606                 /* Disable link */
3607                 reg = er32(PHY_CTRL);
3608                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3609                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3610                 ew32(PHY_CTRL, reg);
3611
3612                 /*
3613                  * Call gig speed drop workaround on Gig disable before
3614                  * accessing any PHY registers
3615                  */
3616                 if (hw->mac.type == e1000_ich8lan)
3617                         e1000e_gig_downshift_workaround_ich8lan(hw);
3618
3619                 /* Write VR power-down enable */
3620                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3621                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3622                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3623
3624                 /* Read it back and test */
3625                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3626                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3627                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3628                         break;
3629
3630                 /* Issue PHY reset and repeat at most one more time */
3631                 reg = er32(CTRL);
3632                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3633                 retry++;
3634         } while (retry);
3635 }
3636
3637 /**
3638  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3639  *  @hw: pointer to the HW structure
3640  *
3641  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3642  *  LPLU, Gig disable, MDIC PHY reset):
3643  *    1) Set Kumeran Near-end loopback
3644  *    2) Clear Kumeran Near-end loopback
3645  *  Should only be called for ICH8[m] devices with any 1G Phy.
3646  **/
3647 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3648 {
3649         s32 ret_val;
3650         u16 reg_data;
3651
3652         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
3653                 return;
3654
3655         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3656                                       &reg_data);
3657         if (ret_val)
3658                 return;
3659         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3660         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3661                                        reg_data);
3662         if (ret_val)
3663                 return;
3664         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3665         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3666                                        reg_data);
3667 }
3668
3669 /**
3670  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3671  *  @hw: pointer to the HW structure
3672  *
3673  *  During S0 to Sx transition, it is possible the link remains at gig
3674  *  instead of negotiating to a lower speed.  Before going to Sx, set
3675  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3676  *  to a lower speed.  For PCH and newer parts, the OEM bits PHY register
3677  *  (LED, GbE disable and LPLU configurations) also needs to be written.
3678  **/
3679 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3680 {
3681         u32 phy_ctrl;
3682         s32 ret_val;
3683
3684         phy_ctrl = er32(PHY_CTRL);
3685         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3686         ew32(PHY_CTRL, phy_ctrl);
3687
3688         if (hw->mac.type == e1000_ich8lan)
3689                 e1000e_gig_downshift_workaround_ich8lan(hw);
3690
3691         if (hw->mac.type >= e1000_pchlan) {
3692                 e1000_oem_bits_config_ich8lan(hw, false);
3693                 e1000_phy_hw_reset_ich8lan(hw);
3694                 ret_val = hw->phy.ops.acquire(hw);
3695                 if (ret_val)
3696                         return;
3697                 e1000_write_smbus_addr(hw);
3698                 hw->phy.ops.release(hw);
3699         }
3700 }
3701
3702 /**
3703  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3704  *  @hw: pointer to the HW structure
3705  *
3706  *  During Sx to S0 transitions on non-managed devices or managed devices
3707  *  on which PHY resets are not blocked, if the PHY registers cannot be
3708  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
3709  *  the PHY.
3710  **/
3711 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3712 {
3713         u32 fwsm;
3714
3715         if (hw->mac.type != e1000_pch2lan)
3716                 return;
3717
3718         fwsm = er32(FWSM);
3719         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) || !e1000_check_reset_block(hw)) {
3720                 u16 phy_id1, phy_id2;
3721                 s32 ret_val;
3722
3723                 ret_val = hw->phy.ops.acquire(hw);
3724                 if (ret_val) {
3725                         e_dbg("Failed to acquire PHY semaphore in resume\n");
3726                         return;
3727                 }
3728
3729                 /* Test access to the PHY registers by reading the ID regs */
3730                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
3731                 if (ret_val)
3732                         goto release;
3733                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
3734                 if (ret_val)
3735                         goto release;
3736
3737                 if (hw->phy.id == ((u32)(phy_id1 << 16) |
3738                                    (u32)(phy_id2 & PHY_REVISION_MASK)))
3739                         goto release;
3740
3741                 e1000_toggle_lanphypc_value_ich8lan(hw);
3742
3743                 hw->phy.ops.release(hw);
3744                 msleep(50);
3745                 e1000_phy_hw_reset(hw);
3746                 msleep(50);
3747                 return;
3748         }
3749
3750 release:
3751         hw->phy.ops.release(hw);
3752
3753         return;
3754 }
3755
3756 /**
3757  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3758  *  @hw: pointer to the HW structure
3759  *
3760  *  Return the LED back to the default configuration.
3761  **/
3762 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3763 {
3764         if (hw->phy.type == e1000_phy_ife)
3765                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3766
3767         ew32(LEDCTL, hw->mac.ledctl_default);
3768         return 0;
3769 }
3770
3771 /**
3772  *  e1000_led_on_ich8lan - Turn LEDs on
3773  *  @hw: pointer to the HW structure
3774  *
3775  *  Turn on the LEDs.
3776  **/
3777 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3778 {
3779         if (hw->phy.type == e1000_phy_ife)
3780                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3781                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3782
3783         ew32(LEDCTL, hw->mac.ledctl_mode2);
3784         return 0;
3785 }
3786
3787 /**
3788  *  e1000_led_off_ich8lan - Turn LEDs off
3789  *  @hw: pointer to the HW structure
3790  *
3791  *  Turn off the LEDs.
3792  **/
3793 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3794 {
3795         if (hw->phy.type == e1000_phy_ife)
3796                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3797                                 (IFE_PSCL_PROBE_MODE |
3798                                  IFE_PSCL_PROBE_LEDS_OFF));
3799
3800         ew32(LEDCTL, hw->mac.ledctl_mode1);
3801         return 0;
3802 }
3803
3804 /**
3805  *  e1000_setup_led_pchlan - Configures SW controllable LED
3806  *  @hw: pointer to the HW structure
3807  *
3808  *  This prepares the SW controllable LED for use.
3809  **/
3810 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3811 {
3812         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3813 }
3814
3815 /**
3816  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3817  *  @hw: pointer to the HW structure
3818  *
3819  *  Return the LED back to the default configuration.
3820  **/
3821 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3822 {
3823         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3824 }
3825
3826 /**
3827  *  e1000_led_on_pchlan - Turn LEDs on
3828  *  @hw: pointer to the HW structure
3829  *
3830  *  Turn on the LEDs.
3831  **/
3832 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3833 {
3834         u16 data = (u16)hw->mac.ledctl_mode2;
3835         u32 i, led;
3836
3837         /*
3838          * If no link, then turn LED on by setting the invert bit
3839          * for each LED that's mode is "link_up" in ledctl_mode2.
3840          */
3841         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3842                 for (i = 0; i < 3; i++) {
3843                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3844                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3845                             E1000_LEDCTL_MODE_LINK_UP)
3846                                 continue;
3847                         if (led & E1000_PHY_LED0_IVRT)
3848                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3849                         else
3850                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3851                 }
3852         }
3853
3854         return e1e_wphy(hw, HV_LED_CONFIG, data);
3855 }
3856
3857 /**
3858  *  e1000_led_off_pchlan - Turn LEDs off
3859  *  @hw: pointer to the HW structure
3860  *
3861  *  Turn off the LEDs.
3862  **/
3863 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3864 {
3865         u16 data = (u16)hw->mac.ledctl_mode1;
3866         u32 i, led;
3867
3868         /*
3869          * If no link, then turn LED off by clearing the invert bit
3870          * for each LED that's mode is "link_up" in ledctl_mode1.
3871          */
3872         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3873                 for (i = 0; i < 3; i++) {
3874                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3875                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3876                             E1000_LEDCTL_MODE_LINK_UP)
3877                                 continue;
3878                         if (led & E1000_PHY_LED0_IVRT)
3879                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3880                         else
3881                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3882                 }
3883         }
3884
3885         return e1e_wphy(hw, HV_LED_CONFIG, data);
3886 }
3887
3888 /**
3889  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3890  *  @hw: pointer to the HW structure
3891  *
3892  *  Read appropriate register for the config done bit for completion status
3893  *  and configure the PHY through s/w for EEPROM-less parts.
3894  *
3895  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3896  *  config done bit, so only an error is logged and continues.  If we were
3897  *  to return with error, EEPROM-less silicon would not be able to be reset
3898  *  or change link.
3899  **/
3900 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3901 {
3902         s32 ret_val = 0;
3903         u32 bank = 0;
3904         u32 status;
3905
3906         e1000e_get_cfg_done(hw);
3907
3908         /* Wait for indication from h/w that it has completed basic config */
3909         if (hw->mac.type >= e1000_ich10lan) {
3910                 e1000_lan_init_done_ich8lan(hw);
3911         } else {
3912                 ret_val = e1000e_get_auto_rd_done(hw);
3913                 if (ret_val) {
3914                         /*
3915                          * When auto config read does not complete, do not
3916                          * return with an error. This can happen in situations
3917                          * where there is no eeprom and prevents getting link.
3918                          */
3919                         e_dbg("Auto Read Done did not complete\n");
3920                         ret_val = 0;
3921                 }
3922         }
3923
3924         /* Clear PHY Reset Asserted bit */
3925         status = er32(STATUS);
3926         if (status & E1000_STATUS_PHYRA)
3927                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3928         else
3929                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3930
3931         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3932         if (hw->mac.type <= e1000_ich9lan) {
3933                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3934                     (hw->phy.type == e1000_phy_igp_3)) {
3935                         e1000e_phy_init_script_igp3(hw);
3936                 }
3937         } else {
3938                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3939                         /* Maybe we should do a basic PHY config */
3940                         e_dbg("EEPROM not present\n");
3941                         ret_val = -E1000_ERR_CONFIG;
3942                 }
3943         }
3944
3945         return ret_val;
3946 }
3947
3948 /**
3949  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3950  * @hw: pointer to the HW structure
3951  *
3952  * In the case of a PHY power down to save power, or to turn off link during a
3953  * driver unload, or wake on lan is not enabled, remove the link.
3954  **/
3955 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3956 {
3957         /* If the management interface is not enabled, then power down */
3958         if (!(hw->mac.ops.check_mng_mode(hw) ||
3959               hw->phy.ops.check_reset_block(hw)))
3960                 e1000_power_down_phy_copper(hw);
3961 }
3962
3963 /**
3964  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3965  *  @hw: pointer to the HW structure
3966  *
3967  *  Clears hardware counters specific to the silicon family and calls
3968  *  clear_hw_cntrs_generic to clear all general purpose counters.
3969  **/
3970 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3971 {
3972         u16 phy_data;
3973         s32 ret_val;
3974
3975         e1000e_clear_hw_cntrs_base(hw);
3976
3977         er32(ALGNERRC);
3978         er32(RXERRC);
3979         er32(TNCRS);
3980         er32(CEXTERR);
3981         er32(TSCTC);
3982         er32(TSCTFC);
3983
3984         er32(MGTPRC);
3985         er32(MGTPDC);
3986         er32(MGTPTC);
3987
3988         er32(IAC);
3989         er32(ICRXOC);
3990
3991         /* Clear PHY statistics registers */
3992         if ((hw->phy.type == e1000_phy_82578) ||
3993             (hw->phy.type == e1000_phy_82579) ||
3994             (hw->phy.type == e1000_phy_82577)) {
3995                 ret_val = hw->phy.ops.acquire(hw);
3996                 if (ret_val)
3997                         return;
3998                 ret_val = hw->phy.ops.set_page(hw,
3999                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4000                 if (ret_val)
4001                         goto release;
4002                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4003                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4004                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4005                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4006                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4007                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4008                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4009                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4010                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4011                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4012                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4013                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4014                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4015                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4016 release:
4017                 hw->phy.ops.release(hw);
4018         }
4019 }
4020
4021 static const struct e1000_mac_operations ich8_mac_ops = {
4022         .id_led_init            = e1000e_id_led_init,
4023         /* check_mng_mode dependent on mac type */
4024         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4025         /* cleanup_led dependent on mac type */
4026         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4027         .get_bus_info           = e1000_get_bus_info_ich8lan,
4028         .set_lan_id             = e1000_set_lan_id_single_port,
4029         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4030         /* led_on dependent on mac type */
4031         /* led_off dependent on mac type */
4032         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4033         .reset_hw               = e1000_reset_hw_ich8lan,
4034         .init_hw                = e1000_init_hw_ich8lan,
4035         .setup_link             = e1000_setup_link_ich8lan,
4036         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
4037         /* id_led_init dependent on mac type */
4038 };
4039
4040 static const struct e1000_phy_operations ich8_phy_ops = {
4041         .acquire                = e1000_acquire_swflag_ich8lan,
4042         .check_reset_block      = e1000_check_reset_block_ich8lan,
4043         .commit                 = NULL,
4044         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4045         .get_cable_length       = e1000e_get_cable_length_igp_2,
4046         .read_reg               = e1000e_read_phy_reg_igp,
4047         .release                = e1000_release_swflag_ich8lan,
4048         .reset                  = e1000_phy_hw_reset_ich8lan,
4049         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4050         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4051         .write_reg              = e1000e_write_phy_reg_igp,
4052 };
4053
4054 static const struct e1000_nvm_operations ich8_nvm_ops = {
4055         .acquire                = e1000_acquire_nvm_ich8lan,
4056         .read                   = e1000_read_nvm_ich8lan,
4057         .release                = e1000_release_nvm_ich8lan,
4058         .update                 = e1000_update_nvm_checksum_ich8lan,
4059         .valid_led_default      = e1000_valid_led_default_ich8lan,
4060         .validate               = e1000_validate_nvm_checksum_ich8lan,
4061         .write                  = e1000_write_nvm_ich8lan,
4062 };
4063
4064 const struct e1000_info e1000_ich8_info = {
4065         .mac                    = e1000_ich8lan,
4066         .flags                  = FLAG_HAS_WOL
4067                                   | FLAG_IS_ICH
4068                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4069                                   | FLAG_HAS_AMT
4070                                   | FLAG_HAS_FLASH
4071                                   | FLAG_APME_IN_WUC,
4072         .pba                    = 8,
4073         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4074         .get_variants           = e1000_get_variants_ich8lan,
4075         .mac_ops                = &ich8_mac_ops,
4076         .phy_ops                = &ich8_phy_ops,
4077         .nvm_ops                = &ich8_nvm_ops,
4078 };
4079
4080 const struct e1000_info e1000_ich9_info = {
4081         .mac                    = e1000_ich9lan,
4082         .flags                  = FLAG_HAS_JUMBO_FRAMES
4083                                   | FLAG_IS_ICH
4084                                   | FLAG_HAS_WOL
4085                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4086                                   | FLAG_HAS_AMT
4087                                   | FLAG_HAS_ERT
4088                                   | FLAG_HAS_FLASH
4089                                   | FLAG_APME_IN_WUC,
4090         .pba                    = 10,
4091         .max_hw_frame_size      = DEFAULT_JUMBO,
4092         .get_variants           = e1000_get_variants_ich8lan,
4093         .mac_ops                = &ich8_mac_ops,
4094         .phy_ops                = &ich8_phy_ops,
4095         .nvm_ops                = &ich8_nvm_ops,
4096 };
4097
4098 const struct e1000_info e1000_ich10_info = {
4099         .mac                    = e1000_ich10lan,
4100         .flags                  = FLAG_HAS_JUMBO_FRAMES
4101                                   | FLAG_IS_ICH
4102                                   | FLAG_HAS_WOL
4103                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4104                                   | FLAG_HAS_AMT
4105                                   | FLAG_HAS_ERT
4106                                   | FLAG_HAS_FLASH
4107                                   | FLAG_APME_IN_WUC,
4108         .pba                    = 10,
4109         .max_hw_frame_size      = DEFAULT_JUMBO,
4110         .get_variants           = e1000_get_variants_ich8lan,
4111         .mac_ops                = &ich8_mac_ops,
4112         .phy_ops                = &ich8_phy_ops,
4113         .nvm_ops                = &ich8_nvm_ops,
4114 };
4115
4116 const struct e1000_info e1000_pch_info = {
4117         .mac                    = e1000_pchlan,
4118         .flags                  = FLAG_IS_ICH
4119                                   | FLAG_HAS_WOL
4120                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4121                                   | FLAG_HAS_AMT
4122                                   | FLAG_HAS_FLASH
4123                                   | FLAG_HAS_JUMBO_FRAMES
4124                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4125                                   | FLAG_APME_IN_WUC,
4126         .flags2                 = FLAG2_HAS_PHY_STATS,
4127         .pba                    = 26,
4128         .max_hw_frame_size      = 4096,
4129         .get_variants           = e1000_get_variants_ich8lan,
4130         .mac_ops                = &ich8_mac_ops,
4131         .phy_ops                = &ich8_phy_ops,
4132         .nvm_ops                = &ich8_nvm_ops,
4133 };
4134
4135 const struct e1000_info e1000_pch2_info = {
4136         .mac                    = e1000_pch2lan,
4137         .flags                  = FLAG_IS_ICH
4138                                   | FLAG_HAS_WOL
4139                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4140                                   | FLAG_HAS_AMT
4141                                   | FLAG_HAS_FLASH
4142                                   | FLAG_HAS_JUMBO_FRAMES
4143                                   | FLAG_APME_IN_WUC,
4144         .flags2                 = FLAG2_HAS_PHY_STATS
4145                                   | FLAG2_HAS_EEE,
4146         .pba                    = 26,
4147         .max_hw_frame_size      = DEFAULT_JUMBO,
4148         .get_variants           = e1000_get_variants_ich8lan,
4149         .mac_ops                = &ich8_mac_ops,
4150         .phy_ops                = &ich8_phy_ops,
4151         .nvm_ops                = &ich8_nvm_ops,
4152 };