1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
81 #include <linux/of_mdio.h>
82 #include <linux/of_platform.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
87 #include <linux/net_tstamp.h>
92 #include <asm/uaccess.h>
93 #include <linux/module.h>
94 #include <linux/dma-mapping.h>
95 #include <linux/crc32.h>
96 #include <linux/mii.h>
97 #include <linux/phy.h>
98 #include <linux/phy_fixed.h>
100 #include <linux/of_net.h>
104 #define TX_TIMEOUT (1*HZ)
106 const char gfar_driver_version[] = "1.3";
108 static int gfar_enet_open(struct net_device *dev);
109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
110 static void gfar_reset_task(struct work_struct *work);
111 static void gfar_timeout(struct net_device *dev);
112 static int gfar_close(struct net_device *dev);
113 struct sk_buff *gfar_new_skb(struct net_device *dev);
114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
115 struct sk_buff *skb);
116 static int gfar_set_mac_address(struct net_device *dev);
117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
118 static irqreturn_t gfar_error(int irq, void *dev_id);
119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
121 static void adjust_link(struct net_device *dev);
122 static void init_registers(struct net_device *dev);
123 static int init_phy(struct net_device *dev);
124 static int gfar_probe(struct platform_device *ofdev);
125 static int gfar_remove(struct platform_device *ofdev);
126 static void free_skb_resources(struct gfar_private *priv);
127 static void gfar_set_multi(struct net_device *dev);
128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
129 static void gfar_configure_serdes(struct net_device *dev);
130 static int gfar_poll(struct napi_struct *napi, int budget);
131 #ifdef CONFIG_NET_POLL_CONTROLLER
132 static void gfar_netpoll(struct net_device *dev);
134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
136 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 int amount_pull, struct napi_struct *napi);
138 void gfar_halt(struct net_device *dev);
139 static void gfar_halt_nodisable(struct net_device *dev);
140 void gfar_start(struct net_device *dev);
141 static void gfar_clear_exact_match(struct net_device *dev);
142 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
157 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
158 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
159 lstatus |= BD_LFLAG(RXBD_WRAP);
163 bdp->lstatus = lstatus;
166 static int gfar_init_bds(struct net_device *ndev)
168 struct gfar_private *priv = netdev_priv(ndev);
169 struct gfar_priv_tx_q *tx_queue = NULL;
170 struct gfar_priv_rx_q *rx_queue = NULL;
175 for (i = 0; i < priv->num_tx_queues; i++) {
176 tx_queue = priv->tx_queue[i];
177 /* Initialize some variables in our dev structure */
178 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
179 tx_queue->dirty_tx = tx_queue->tx_bd_base;
180 tx_queue->cur_tx = tx_queue->tx_bd_base;
181 tx_queue->skb_curtx = 0;
182 tx_queue->skb_dirtytx = 0;
184 /* Initialize Transmit Descriptor Ring */
185 txbdp = tx_queue->tx_bd_base;
186 for (j = 0; j < tx_queue->tx_ring_size; j++) {
192 /* Set the last descriptor in the ring to indicate wrap */
194 txbdp->status |= TXBD_WRAP;
197 for (i = 0; i < priv->num_rx_queues; i++) {
198 rx_queue = priv->rx_queue[i];
199 rx_queue->cur_rx = rx_queue->rx_bd_base;
200 rx_queue->skb_currx = 0;
201 rxbdp = rx_queue->rx_bd_base;
203 for (j = 0; j < rx_queue->rx_ring_size; j++) {
204 struct sk_buff *skb = rx_queue->rx_skbuff[j];
207 gfar_init_rxbdp(rx_queue, rxbdp,
210 skb = gfar_new_skb(ndev);
212 netdev_err(ndev, "Can't allocate RX buffers\n");
215 rx_queue->rx_skbuff[j] = skb;
217 gfar_new_rxbdp(rx_queue, rxbdp, skb);
228 static int gfar_alloc_skb_resources(struct net_device *ndev)
233 struct gfar_private *priv = netdev_priv(ndev);
234 struct device *dev = &priv->ofdev->dev;
235 struct gfar_priv_tx_q *tx_queue = NULL;
236 struct gfar_priv_rx_q *rx_queue = NULL;
238 priv->total_tx_ring_size = 0;
239 for (i = 0; i < priv->num_tx_queues; i++)
240 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
242 priv->total_rx_ring_size = 0;
243 for (i = 0; i < priv->num_rx_queues; i++)
244 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
246 /* Allocate memory for the buffer descriptors */
247 vaddr = dma_alloc_coherent(dev,
248 sizeof(struct txbd8) * priv->total_tx_ring_size +
249 sizeof(struct rxbd8) * priv->total_rx_ring_size,
252 netif_err(priv, ifup, ndev,
253 "Could not allocate buffer descriptors!\n");
257 for (i = 0; i < priv->num_tx_queues; i++) {
258 tx_queue = priv->tx_queue[i];
259 tx_queue->tx_bd_base = vaddr;
260 tx_queue->tx_bd_dma_base = addr;
261 tx_queue->dev = ndev;
262 /* enet DMA only understands physical addresses */
263 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
264 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
267 /* Start the rx descriptor ring where the tx ring leaves off */
268 for (i = 0; i < priv->num_rx_queues; i++) {
269 rx_queue = priv->rx_queue[i];
270 rx_queue->rx_bd_base = vaddr;
271 rx_queue->rx_bd_dma_base = addr;
272 rx_queue->dev = ndev;
273 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
274 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
277 /* Setup the skbuff rings */
278 for (i = 0; i < priv->num_tx_queues; i++) {
279 tx_queue = priv->tx_queue[i];
280 tx_queue->tx_skbuff =
281 kmalloc_array(tx_queue->tx_ring_size,
282 sizeof(*tx_queue->tx_skbuff),
284 if (!tx_queue->tx_skbuff)
287 for (k = 0; k < tx_queue->tx_ring_size; k++)
288 tx_queue->tx_skbuff[k] = NULL;
291 for (i = 0; i < priv->num_rx_queues; i++) {
292 rx_queue = priv->rx_queue[i];
293 rx_queue->rx_skbuff =
294 kmalloc_array(rx_queue->rx_ring_size,
295 sizeof(*rx_queue->rx_skbuff),
297 if (!rx_queue->rx_skbuff)
300 for (j = 0; j < rx_queue->rx_ring_size; j++)
301 rx_queue->rx_skbuff[j] = NULL;
304 if (gfar_init_bds(ndev))
310 free_skb_resources(priv);
314 static void gfar_init_tx_rx_base(struct gfar_private *priv)
316 struct gfar __iomem *regs = priv->gfargrp[0].regs;
320 baddr = ®s->tbase0;
321 for (i = 0; i < priv->num_tx_queues; i++) {
322 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
326 baddr = ®s->rbase0;
327 for (i = 0; i < priv->num_rx_queues; i++) {
328 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
333 static void gfar_init_mac(struct net_device *ndev)
335 struct gfar_private *priv = netdev_priv(ndev);
336 struct gfar __iomem *regs = priv->gfargrp[0].regs;
341 /* write the tx/rx base registers */
342 gfar_init_tx_rx_base(priv);
344 /* Configure the coalescing support */
345 gfar_configure_coalescing(priv, 0xFF, 0xFF);
347 if (priv->rx_filer_enable) {
348 rctrl |= RCTRL_FILREN;
349 /* Program the RIR0 reg with the required distribution */
350 gfar_write(®s->rir0, DEFAULT_RIR0);
353 /* Restore PROMISC mode */
354 if (ndev->flags & IFF_PROMISC)
357 if (ndev->features & NETIF_F_RXCSUM)
358 rctrl |= RCTRL_CHECKSUMMING;
360 if (priv->extended_hash) {
361 rctrl |= RCTRL_EXTHASH;
363 gfar_clear_exact_match(ndev);
368 rctrl &= ~RCTRL_PAL_MASK;
369 rctrl |= RCTRL_PADDING(priv->padding);
372 /* Insert receive time stamps into padding alignment bytes */
373 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
374 rctrl &= ~RCTRL_PAL_MASK;
375 rctrl |= RCTRL_PADDING(8);
379 /* Enable HW time stamping if requested from user space */
380 if (priv->hwts_rx_en)
381 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
383 if (ndev->features & NETIF_F_HW_VLAN_RX)
384 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
386 /* Init rctrl based on our settings */
387 gfar_write(®s->rctrl, rctrl);
389 if (ndev->features & NETIF_F_IP_CSUM)
390 tctrl |= TCTRL_INIT_CSUM;
392 if (priv->prio_sched_en)
393 tctrl |= TCTRL_TXSCHED_PRIO;
395 tctrl |= TCTRL_TXSCHED_WRRS;
396 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
397 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
400 gfar_write(®s->tctrl, tctrl);
402 /* Set the extraction length and index */
403 attrs = ATTRELI_EL(priv->rx_stash_size) |
404 ATTRELI_EI(priv->rx_stash_index);
406 gfar_write(®s->attreli, attrs);
408 /* Start with defaults, and add stashing or locking
409 * depending on the approprate variables
411 attrs = ATTR_INIT_SETTINGS;
413 if (priv->bd_stash_en)
414 attrs |= ATTR_BDSTASH;
416 if (priv->rx_stash_size != 0)
417 attrs |= ATTR_BUFSTASH;
419 gfar_write(®s->attr, attrs);
421 gfar_write(®s->fifo_tx_thr, priv->fifo_threshold);
422 gfar_write(®s->fifo_tx_starve, priv->fifo_starve);
423 gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off);
426 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
428 struct gfar_private *priv = netdev_priv(dev);
429 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
430 unsigned long tx_packets = 0, tx_bytes = 0;
433 for (i = 0; i < priv->num_rx_queues; i++) {
434 rx_packets += priv->rx_queue[i]->stats.rx_packets;
435 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
436 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
439 dev->stats.rx_packets = rx_packets;
440 dev->stats.rx_bytes = rx_bytes;
441 dev->stats.rx_dropped = rx_dropped;
443 for (i = 0; i < priv->num_tx_queues; i++) {
444 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
445 tx_packets += priv->tx_queue[i]->stats.tx_packets;
448 dev->stats.tx_bytes = tx_bytes;
449 dev->stats.tx_packets = tx_packets;
454 static const struct net_device_ops gfar_netdev_ops = {
455 .ndo_open = gfar_enet_open,
456 .ndo_start_xmit = gfar_start_xmit,
457 .ndo_stop = gfar_close,
458 .ndo_change_mtu = gfar_change_mtu,
459 .ndo_set_features = gfar_set_features,
460 .ndo_set_rx_mode = gfar_set_multi,
461 .ndo_tx_timeout = gfar_timeout,
462 .ndo_do_ioctl = gfar_ioctl,
463 .ndo_get_stats = gfar_get_stats,
464 .ndo_set_mac_address = eth_mac_addr,
465 .ndo_validate_addr = eth_validate_addr,
466 #ifdef CONFIG_NET_POLL_CONTROLLER
467 .ndo_poll_controller = gfar_netpoll,
471 void lock_rx_qs(struct gfar_private *priv)
475 for (i = 0; i < priv->num_rx_queues; i++)
476 spin_lock(&priv->rx_queue[i]->rxlock);
479 void lock_tx_qs(struct gfar_private *priv)
483 for (i = 0; i < priv->num_tx_queues; i++)
484 spin_lock(&priv->tx_queue[i]->txlock);
487 void unlock_rx_qs(struct gfar_private *priv)
491 for (i = 0; i < priv->num_rx_queues; i++)
492 spin_unlock(&priv->rx_queue[i]->rxlock);
495 void unlock_tx_qs(struct gfar_private *priv)
499 for (i = 0; i < priv->num_tx_queues; i++)
500 spin_unlock(&priv->tx_queue[i]->txlock);
503 static bool gfar_is_vlan_on(struct gfar_private *priv)
505 return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
506 (priv->ndev->features & NETIF_F_HW_VLAN_TX);
509 /* Returns 1 if incoming frames use an FCB */
510 static inline int gfar_uses_fcb(struct gfar_private *priv)
512 return gfar_is_vlan_on(priv) ||
513 (priv->ndev->features & NETIF_F_RXCSUM) ||
514 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
517 static void free_tx_pointers(struct gfar_private *priv)
521 for (i = 0; i < priv->num_tx_queues; i++)
522 kfree(priv->tx_queue[i]);
525 static void free_rx_pointers(struct gfar_private *priv)
529 for (i = 0; i < priv->num_rx_queues; i++)
530 kfree(priv->rx_queue[i]);
533 static void unmap_group_regs(struct gfar_private *priv)
537 for (i = 0; i < MAXGROUPS; i++)
538 if (priv->gfargrp[i].regs)
539 iounmap(priv->gfargrp[i].regs);
542 static void free_gfar_dev(struct gfar_private *priv)
546 for (i = 0; i < priv->num_grps; i++)
547 for (j = 0; j < GFAR_NUM_IRQS; j++) {
548 kfree(priv->gfargrp[i].irqinfo[j]);
549 priv->gfargrp[i].irqinfo[j] = NULL;
552 free_netdev(priv->ndev);
555 static void disable_napi(struct gfar_private *priv)
559 for (i = 0; i < priv->num_grps; i++)
560 napi_disable(&priv->gfargrp[i].napi);
563 static void enable_napi(struct gfar_private *priv)
567 for (i = 0; i < priv->num_grps; i++)
568 napi_enable(&priv->gfargrp[i].napi);
571 static int gfar_parse_group(struct device_node *np,
572 struct gfar_private *priv, const char *model)
574 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
578 for (i = 0; i < GFAR_NUM_IRQS; i++) {
579 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
581 if (!grp->irqinfo[i])
585 grp->regs = of_iomap(np, 0);
589 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
591 /* If we aren't the FEC we have multiple interrupts */
592 if (model && strcasecmp(model, "FEC")) {
593 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
594 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
595 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
596 gfar_irq(grp, RX)->irq == NO_IRQ ||
597 gfar_irq(grp, ER)->irq == NO_IRQ)
601 grp->grp_id = priv->num_grps;
603 spin_lock_init(&grp->grplock);
604 if (priv->mode == MQ_MG_MODE) {
605 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
606 grp->rx_bit_map = queue_mask ?
607 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
608 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
609 grp->tx_bit_map = queue_mask ?
610 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
612 grp->rx_bit_map = 0xFF;
613 grp->tx_bit_map = 0xFF;
620 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
624 const void *mac_addr;
626 struct net_device *dev = NULL;
627 struct gfar_private *priv = NULL;
628 struct device_node *np = ofdev->dev.of_node;
629 struct device_node *child = NULL;
631 const u32 *stash_len;
632 const u32 *stash_idx;
633 unsigned int num_tx_qs, num_rx_qs;
634 u32 *tx_queues, *rx_queues;
636 if (!np || !of_device_is_available(np))
639 /* parse the num of tx and rx queues */
640 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
641 num_tx_qs = tx_queues ? *tx_queues : 1;
643 if (num_tx_qs > MAX_TX_QS) {
644 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
645 num_tx_qs, MAX_TX_QS);
646 pr_err("Cannot do alloc_etherdev, aborting\n");
650 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
651 num_rx_qs = rx_queues ? *rx_queues : 1;
653 if (num_rx_qs > MAX_RX_QS) {
654 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
655 num_rx_qs, MAX_RX_QS);
656 pr_err("Cannot do alloc_etherdev, aborting\n");
660 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
665 priv = netdev_priv(dev);
668 priv->num_tx_queues = num_tx_qs;
669 netif_set_real_num_rx_queues(dev, num_rx_qs);
670 priv->num_rx_queues = num_rx_qs;
671 priv->num_grps = 0x0;
673 /* Init Rx queue filer rule set linked list */
674 INIT_LIST_HEAD(&priv->rx_list.list);
675 priv->rx_list.count = 0;
676 mutex_init(&priv->rx_queue_access);
678 model = of_get_property(np, "model", NULL);
680 for (i = 0; i < MAXGROUPS; i++)
681 priv->gfargrp[i].regs = NULL;
683 /* Parse and initialize group specific information */
684 if (of_device_is_compatible(np, "fsl,etsec2")) {
685 priv->mode = MQ_MG_MODE;
686 for_each_child_of_node(np, child) {
687 err = gfar_parse_group(child, priv, model);
692 priv->mode = SQ_SG_MODE;
693 err = gfar_parse_group(np, priv, model);
698 for (i = 0; i < priv->num_tx_queues; i++)
699 priv->tx_queue[i] = NULL;
700 for (i = 0; i < priv->num_rx_queues; i++)
701 priv->rx_queue[i] = NULL;
703 for (i = 0; i < priv->num_tx_queues; i++) {
704 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
706 if (!priv->tx_queue[i]) {
708 goto tx_alloc_failed;
710 priv->tx_queue[i]->tx_skbuff = NULL;
711 priv->tx_queue[i]->qindex = i;
712 priv->tx_queue[i]->dev = dev;
713 spin_lock_init(&(priv->tx_queue[i]->txlock));
716 for (i = 0; i < priv->num_rx_queues; i++) {
717 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
719 if (!priv->rx_queue[i]) {
721 goto rx_alloc_failed;
723 priv->rx_queue[i]->rx_skbuff = NULL;
724 priv->rx_queue[i]->qindex = i;
725 priv->rx_queue[i]->dev = dev;
726 spin_lock_init(&(priv->rx_queue[i]->rxlock));
730 stash = of_get_property(np, "bd-stash", NULL);
733 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
734 priv->bd_stash_en = 1;
737 stash_len = of_get_property(np, "rx-stash-len", NULL);
740 priv->rx_stash_size = *stash_len;
742 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
745 priv->rx_stash_index = *stash_idx;
747 if (stash_len || stash_idx)
748 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
750 mac_addr = of_get_mac_address(np);
753 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
755 if (model && !strcasecmp(model, "TSEC"))
756 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
757 FSL_GIANFAR_DEV_HAS_COALESCE |
758 FSL_GIANFAR_DEV_HAS_RMON |
759 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
761 if (model && !strcasecmp(model, "eTSEC"))
762 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
763 FSL_GIANFAR_DEV_HAS_COALESCE |
764 FSL_GIANFAR_DEV_HAS_RMON |
765 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
766 FSL_GIANFAR_DEV_HAS_PADDING |
767 FSL_GIANFAR_DEV_HAS_CSUM |
768 FSL_GIANFAR_DEV_HAS_VLAN |
769 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
770 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
771 FSL_GIANFAR_DEV_HAS_TIMER;
773 ctype = of_get_property(np, "phy-connection-type", NULL);
775 /* We only care about rgmii-id. The rest are autodetected */
776 if (ctype && !strcmp(ctype, "rgmii-id"))
777 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
779 priv->interface = PHY_INTERFACE_MODE_MII;
781 if (of_get_property(np, "fsl,magic-packet", NULL))
782 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
784 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
786 /* Find the TBI PHY. If it's not there, we don't support SGMII */
787 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
792 free_rx_pointers(priv);
794 free_tx_pointers(priv);
796 unmap_group_regs(priv);
801 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
802 struct ifreq *ifr, int cmd)
804 struct hwtstamp_config config;
805 struct gfar_private *priv = netdev_priv(netdev);
807 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
810 /* reserved for future extensions */
814 switch (config.tx_type) {
815 case HWTSTAMP_TX_OFF:
816 priv->hwts_tx_en = 0;
819 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
821 priv->hwts_tx_en = 1;
827 switch (config.rx_filter) {
828 case HWTSTAMP_FILTER_NONE:
829 if (priv->hwts_rx_en) {
831 priv->hwts_rx_en = 0;
832 startup_gfar(netdev);
836 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
838 if (!priv->hwts_rx_en) {
840 priv->hwts_rx_en = 1;
841 startup_gfar(netdev);
843 config.rx_filter = HWTSTAMP_FILTER_ALL;
847 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
851 /* Ioctl MII Interface */
852 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
854 struct gfar_private *priv = netdev_priv(dev);
856 if (!netif_running(dev))
859 if (cmd == SIOCSHWTSTAMP)
860 return gfar_hwtstamp_ioctl(dev, rq, cmd);
865 return phy_mii_ioctl(priv->phydev, rq, cmd);
868 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
870 unsigned int new_bit_map = 0x0;
871 int mask = 0x1 << (max_qs - 1), i;
873 for (i = 0; i < max_qs; i++) {
875 new_bit_map = new_bit_map + (1 << i);
881 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
884 u32 rqfpr = FPR_FILER_MASK;
888 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
889 priv->ftp_rqfpr[rqfar] = rqfpr;
890 priv->ftp_rqfcr[rqfar] = rqfcr;
891 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
894 rqfcr = RQFCR_CMP_NOMATCH;
895 priv->ftp_rqfpr[rqfar] = rqfpr;
896 priv->ftp_rqfcr[rqfar] = rqfcr;
897 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
900 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
902 priv->ftp_rqfcr[rqfar] = rqfcr;
903 priv->ftp_rqfpr[rqfar] = rqfpr;
904 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
907 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
909 priv->ftp_rqfcr[rqfar] = rqfcr;
910 priv->ftp_rqfpr[rqfar] = rqfpr;
911 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
916 static void gfar_init_filer_table(struct gfar_private *priv)
919 u32 rqfar = MAX_FILER_IDX;
921 u32 rqfpr = FPR_FILER_MASK;
924 rqfcr = RQFCR_CMP_MATCH;
925 priv->ftp_rqfcr[rqfar] = rqfcr;
926 priv->ftp_rqfpr[rqfar] = rqfpr;
927 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
929 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
930 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
931 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
932 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
933 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
934 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
936 /* cur_filer_idx indicated the first non-masked rule */
937 priv->cur_filer_idx = rqfar;
939 /* Rest are masked rules */
940 rqfcr = RQFCR_CMP_NOMATCH;
941 for (i = 0; i < rqfar; i++) {
942 priv->ftp_rqfcr[i] = rqfcr;
943 priv->ftp_rqfpr[i] = rqfpr;
944 gfar_write_filer(priv, i, rqfcr, rqfpr);
948 static void gfar_detect_errata(struct gfar_private *priv)
950 struct device *dev = &priv->ofdev->dev;
951 unsigned int pvr = mfspr(SPRN_PVR);
952 unsigned int svr = mfspr(SPRN_SVR);
953 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
954 unsigned int rev = svr & 0xffff;
956 /* MPC8313 Rev 2.0 and higher; All MPC837x */
957 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
958 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
959 priv->errata |= GFAR_ERRATA_74;
961 /* MPC8313 and MPC837x all rev */
962 if ((pvr == 0x80850010 && mod == 0x80b0) ||
963 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
964 priv->errata |= GFAR_ERRATA_76;
966 /* MPC8313 and MPC837x all rev */
967 if ((pvr == 0x80850010 && mod == 0x80b0) ||
968 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
969 priv->errata |= GFAR_ERRATA_A002;
971 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
972 if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
973 (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
974 priv->errata |= GFAR_ERRATA_12;
977 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
981 /* Set up the ethernet device structure, private data,
982 * and anything else we need before we start
984 static int gfar_probe(struct platform_device *ofdev)
987 struct net_device *dev = NULL;
988 struct gfar_private *priv = NULL;
989 struct gfar __iomem *regs = NULL;
990 int err = 0, i, grp_idx = 0;
991 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
995 err = gfar_of_init(ofdev, &dev);
1000 priv = netdev_priv(dev);
1002 priv->ofdev = ofdev;
1003 SET_NETDEV_DEV(dev, &ofdev->dev);
1005 spin_lock_init(&priv->bflock);
1006 INIT_WORK(&priv->reset_task, gfar_reset_task);
1008 dev_set_drvdata(&ofdev->dev, priv);
1009 regs = priv->gfargrp[0].regs;
1011 gfar_detect_errata(priv);
1013 /* Stop the DMA engine now, in case it was running before
1014 * (The firmware could have used it, and left it running).
1018 /* Reset MAC layer */
1019 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
1021 /* We need to delay at least 3 TX clocks */
1024 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1025 gfar_write(®s->maccfg1, tempval);
1027 /* Initialize MACCFG2. */
1028 tempval = MACCFG2_INIT_SETTINGS;
1029 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1030 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1031 gfar_write(®s->maccfg2, tempval);
1033 /* Initialize ECNTRL */
1034 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1036 /* Set the dev->base_addr to the gfar reg region */
1037 dev->base_addr = (unsigned long) regs;
1039 /* Fill in the dev structure */
1040 dev->watchdog_timeo = TX_TIMEOUT;
1042 dev->netdev_ops = &gfar_netdev_ops;
1043 dev->ethtool_ops = &gfar_ethtool_ops;
1045 /* Register for napi ...We are registering NAPI for each grp */
1046 for (i = 0; i < priv->num_grps; i++)
1047 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1050 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1051 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1053 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1054 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1057 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1058 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1059 dev->features |= NETIF_F_HW_VLAN_RX;
1062 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1063 priv->extended_hash = 1;
1064 priv->hash_width = 9;
1066 priv->hash_regs[0] = ®s->igaddr0;
1067 priv->hash_regs[1] = ®s->igaddr1;
1068 priv->hash_regs[2] = ®s->igaddr2;
1069 priv->hash_regs[3] = ®s->igaddr3;
1070 priv->hash_regs[4] = ®s->igaddr4;
1071 priv->hash_regs[5] = ®s->igaddr5;
1072 priv->hash_regs[6] = ®s->igaddr6;
1073 priv->hash_regs[7] = ®s->igaddr7;
1074 priv->hash_regs[8] = ®s->gaddr0;
1075 priv->hash_regs[9] = ®s->gaddr1;
1076 priv->hash_regs[10] = ®s->gaddr2;
1077 priv->hash_regs[11] = ®s->gaddr3;
1078 priv->hash_regs[12] = ®s->gaddr4;
1079 priv->hash_regs[13] = ®s->gaddr5;
1080 priv->hash_regs[14] = ®s->gaddr6;
1081 priv->hash_regs[15] = ®s->gaddr7;
1084 priv->extended_hash = 0;
1085 priv->hash_width = 8;
1087 priv->hash_regs[0] = ®s->gaddr0;
1088 priv->hash_regs[1] = ®s->gaddr1;
1089 priv->hash_regs[2] = ®s->gaddr2;
1090 priv->hash_regs[3] = ®s->gaddr3;
1091 priv->hash_regs[4] = ®s->gaddr4;
1092 priv->hash_regs[5] = ®s->gaddr5;
1093 priv->hash_regs[6] = ®s->gaddr6;
1094 priv->hash_regs[7] = ®s->gaddr7;
1097 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1098 priv->padding = DEFAULT_PADDING;
1102 if (dev->features & NETIF_F_IP_CSUM ||
1103 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1104 dev->needed_headroom = GMAC_FCB_LEN;
1106 /* Program the isrg regs only if number of grps > 1 */
1107 if (priv->num_grps > 1) {
1108 baddr = ®s->isrg0;
1109 for (i = 0; i < priv->num_grps; i++) {
1110 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1111 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1112 gfar_write(baddr, isrg);
1118 /* Need to reverse the bit maps as bit_map's MSB is q0
1119 * but, for_each_set_bit parses from right to left, which
1120 * basically reverses the queue numbers
1122 for (i = 0; i< priv->num_grps; i++) {
1123 priv->gfargrp[i].tx_bit_map =
1124 reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1125 priv->gfargrp[i].rx_bit_map =
1126 reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1129 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1130 * also assign queues to groups
1132 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1133 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1135 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1136 priv->num_rx_queues) {
1137 priv->gfargrp[grp_idx].num_rx_queues++;
1138 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1139 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1140 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1142 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1144 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1145 priv->num_tx_queues) {
1146 priv->gfargrp[grp_idx].num_tx_queues++;
1147 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1148 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1149 tqueue = tqueue | (TQUEUE_EN0 >> i);
1151 priv->gfargrp[grp_idx].rstat = rstat;
1152 priv->gfargrp[grp_idx].tstat = tstat;
1156 gfar_write(®s->rqueue, rqueue);
1157 gfar_write(®s->tqueue, tqueue);
1159 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1161 /* Initializing some of the rx/tx queue level parameters */
1162 for (i = 0; i < priv->num_tx_queues; i++) {
1163 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1164 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1165 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1166 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1169 for (i = 0; i < priv->num_rx_queues; i++) {
1170 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1171 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1172 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1175 /* always enable rx filer */
1176 priv->rx_filer_enable = 1;
1177 /* Enable most messages by default */
1178 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1179 /* use pritority h/w tx queue scheduling for single queue devices */
1180 if (priv->num_tx_queues == 1)
1181 priv->prio_sched_en = 1;
1183 /* Carrier starts down, phylib will bring it up */
1184 netif_carrier_off(dev);
1186 err = register_netdev(dev);
1189 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1193 device_init_wakeup(&dev->dev,
1194 priv->device_flags &
1195 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1197 /* fill out IRQ number and name fields */
1198 for (i = 0; i < priv->num_grps; i++) {
1199 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1200 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1201 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1202 dev->name, "_g", '0' + i, "_tx");
1203 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1204 dev->name, "_g", '0' + i, "_rx");
1205 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1206 dev->name, "_g", '0' + i, "_er");
1208 strcpy(gfar_irq(grp, TX)->name, dev->name);
1211 /* Initialize the filer table */
1212 gfar_init_filer_table(priv);
1214 /* Create all the sysfs files */
1215 gfar_init_sysfs(dev);
1217 /* Print out the device info */
1218 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1220 /* Even more device info helps when determining which kernel
1221 * provided which set of benchmarks.
1223 netdev_info(dev, "Running with NAPI enabled\n");
1224 for (i = 0; i < priv->num_rx_queues; i++)
1225 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1226 i, priv->rx_queue[i]->rx_ring_size);
1227 for (i = 0; i < priv->num_tx_queues; i++)
1228 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1229 i, priv->tx_queue[i]->tx_ring_size);
1234 unmap_group_regs(priv);
1235 free_tx_pointers(priv);
1236 free_rx_pointers(priv);
1238 of_node_put(priv->phy_node);
1240 of_node_put(priv->tbi_node);
1241 free_gfar_dev(priv);
1245 static int gfar_remove(struct platform_device *ofdev)
1247 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1250 of_node_put(priv->phy_node);
1252 of_node_put(priv->tbi_node);
1254 dev_set_drvdata(&ofdev->dev, NULL);
1256 unregister_netdev(priv->ndev);
1257 unmap_group_regs(priv);
1258 free_gfar_dev(priv);
1265 static int gfar_suspend(struct device *dev)
1267 struct gfar_private *priv = dev_get_drvdata(dev);
1268 struct net_device *ndev = priv->ndev;
1269 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1270 unsigned long flags;
1273 int magic_packet = priv->wol_en &&
1274 (priv->device_flags &
1275 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1277 netif_device_detach(ndev);
1279 if (netif_running(ndev)) {
1281 local_irq_save(flags);
1285 gfar_halt_nodisable(ndev);
1287 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1288 tempval = gfar_read(®s->maccfg1);
1290 tempval &= ~MACCFG1_TX_EN;
1293 tempval &= ~MACCFG1_RX_EN;
1295 gfar_write(®s->maccfg1, tempval);
1299 local_irq_restore(flags);
1304 /* Enable interrupt on Magic Packet */
1305 gfar_write(®s->imask, IMASK_MAG);
1307 /* Enable Magic Packet mode */
1308 tempval = gfar_read(®s->maccfg2);
1309 tempval |= MACCFG2_MPEN;
1310 gfar_write(®s->maccfg2, tempval);
1312 phy_stop(priv->phydev);
1319 static int gfar_resume(struct device *dev)
1321 struct gfar_private *priv = dev_get_drvdata(dev);
1322 struct net_device *ndev = priv->ndev;
1323 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1324 unsigned long flags;
1326 int magic_packet = priv->wol_en &&
1327 (priv->device_flags &
1328 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1330 if (!netif_running(ndev)) {
1331 netif_device_attach(ndev);
1335 if (!magic_packet && priv->phydev)
1336 phy_start(priv->phydev);
1338 /* Disable Magic Packet mode, in case something
1341 local_irq_save(flags);
1345 tempval = gfar_read(®s->maccfg2);
1346 tempval &= ~MACCFG2_MPEN;
1347 gfar_write(®s->maccfg2, tempval);
1353 local_irq_restore(flags);
1355 netif_device_attach(ndev);
1362 static int gfar_restore(struct device *dev)
1364 struct gfar_private *priv = dev_get_drvdata(dev);
1365 struct net_device *ndev = priv->ndev;
1367 if (!netif_running(ndev)) {
1368 netif_device_attach(ndev);
1373 if (gfar_init_bds(ndev)) {
1374 free_skb_resources(priv);
1378 init_registers(ndev);
1379 gfar_set_mac_address(ndev);
1380 gfar_init_mac(ndev);
1385 priv->oldduplex = -1;
1388 phy_start(priv->phydev);
1390 netif_device_attach(ndev);
1396 static struct dev_pm_ops gfar_pm_ops = {
1397 .suspend = gfar_suspend,
1398 .resume = gfar_resume,
1399 .freeze = gfar_suspend,
1400 .thaw = gfar_resume,
1401 .restore = gfar_restore,
1404 #define GFAR_PM_OPS (&gfar_pm_ops)
1408 #define GFAR_PM_OPS NULL
1412 /* Reads the controller's registers to determine what interface
1413 * connects it to the PHY.
1415 static phy_interface_t gfar_get_interface(struct net_device *dev)
1417 struct gfar_private *priv = netdev_priv(dev);
1418 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1421 ecntrl = gfar_read(®s->ecntrl);
1423 if (ecntrl & ECNTRL_SGMII_MODE)
1424 return PHY_INTERFACE_MODE_SGMII;
1426 if (ecntrl & ECNTRL_TBI_MODE) {
1427 if (ecntrl & ECNTRL_REDUCED_MODE)
1428 return PHY_INTERFACE_MODE_RTBI;
1430 return PHY_INTERFACE_MODE_TBI;
1433 if (ecntrl & ECNTRL_REDUCED_MODE) {
1434 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1435 return PHY_INTERFACE_MODE_RMII;
1438 phy_interface_t interface = priv->interface;
1440 /* This isn't autodetected right now, so it must
1441 * be set by the device tree or platform code.
1443 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1444 return PHY_INTERFACE_MODE_RGMII_ID;
1446 return PHY_INTERFACE_MODE_RGMII;
1450 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1451 return PHY_INTERFACE_MODE_GMII;
1453 return PHY_INTERFACE_MODE_MII;
1457 /* Initializes driver's PHY state, and attaches to the PHY.
1458 * Returns 0 on success.
1460 static int init_phy(struct net_device *dev)
1462 struct gfar_private *priv = netdev_priv(dev);
1463 uint gigabit_support =
1464 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1465 SUPPORTED_1000baseT_Full : 0;
1466 phy_interface_t interface;
1470 priv->oldduplex = -1;
1472 interface = gfar_get_interface(dev);
1474 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1477 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1479 if (!priv->phydev) {
1480 dev_err(&dev->dev, "could not attach to PHY\n");
1484 if (interface == PHY_INTERFACE_MODE_SGMII)
1485 gfar_configure_serdes(dev);
1487 /* Remove any features not supported by the controller */
1488 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1489 priv->phydev->advertising = priv->phydev->supported;
1494 /* Initialize TBI PHY interface for communicating with the
1495 * SERDES lynx PHY on the chip. We communicate with this PHY
1496 * through the MDIO bus on each controller, treating it as a
1497 * "normal" PHY at the address found in the TBIPA register. We assume
1498 * that the TBIPA register is valid. Either the MDIO bus code will set
1499 * it to a value that doesn't conflict with other PHYs on the bus, or the
1500 * value doesn't matter, as there are no other PHYs on the bus.
1502 static void gfar_configure_serdes(struct net_device *dev)
1504 struct gfar_private *priv = netdev_priv(dev);
1505 struct phy_device *tbiphy;
1507 if (!priv->tbi_node) {
1508 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1509 "device tree specify a tbi-handle\n");
1513 tbiphy = of_phy_find_device(priv->tbi_node);
1515 dev_err(&dev->dev, "error: Could not get TBI device\n");
1519 /* If the link is already up, we must already be ok, and don't need to
1520 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1521 * everything for us? Resetting it takes the link down and requires
1522 * several seconds for it to come back.
1524 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1527 /* Single clk mode, mii mode off(for serdes communication) */
1528 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1530 phy_write(tbiphy, MII_ADVERTISE,
1531 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1532 ADVERTISE_1000XPSE_ASYM);
1534 phy_write(tbiphy, MII_BMCR,
1535 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1539 static void init_registers(struct net_device *dev)
1541 struct gfar_private *priv = netdev_priv(dev);
1542 struct gfar __iomem *regs = NULL;
1545 for (i = 0; i < priv->num_grps; i++) {
1546 regs = priv->gfargrp[i].regs;
1548 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1550 /* Initialize IMASK */
1551 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1554 regs = priv->gfargrp[0].regs;
1555 /* Init hash registers to zero */
1556 gfar_write(®s->igaddr0, 0);
1557 gfar_write(®s->igaddr1, 0);
1558 gfar_write(®s->igaddr2, 0);
1559 gfar_write(®s->igaddr3, 0);
1560 gfar_write(®s->igaddr4, 0);
1561 gfar_write(®s->igaddr5, 0);
1562 gfar_write(®s->igaddr6, 0);
1563 gfar_write(®s->igaddr7, 0);
1565 gfar_write(®s->gaddr0, 0);
1566 gfar_write(®s->gaddr1, 0);
1567 gfar_write(®s->gaddr2, 0);
1568 gfar_write(®s->gaddr3, 0);
1569 gfar_write(®s->gaddr4, 0);
1570 gfar_write(®s->gaddr5, 0);
1571 gfar_write(®s->gaddr6, 0);
1572 gfar_write(®s->gaddr7, 0);
1574 /* Zero out the rmon mib registers if it has them */
1575 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1576 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1578 /* Mask off the CAM interrupts */
1579 gfar_write(®s->rmon.cam1, 0xffffffff);
1580 gfar_write(®s->rmon.cam2, 0xffffffff);
1583 /* Initialize the max receive buffer length */
1584 gfar_write(®s->mrblr, priv->rx_buffer_size);
1586 /* Initialize the Minimum Frame Length Register */
1587 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1590 static int __gfar_is_rx_idle(struct gfar_private *priv)
1594 /* Normaly TSEC should not hang on GRS commands, so we should
1595 * actually wait for IEVENT_GRSC flag.
1597 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1600 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1601 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1602 * and the Rx can be safely reset.
1604 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1606 if ((res & 0xffff) == (res >> 16))
1612 /* Halt the receive and transmit queues */
1613 static void gfar_halt_nodisable(struct net_device *dev)
1615 struct gfar_private *priv = netdev_priv(dev);
1616 struct gfar __iomem *regs = NULL;
1620 for (i = 0; i < priv->num_grps; i++) {
1621 regs = priv->gfargrp[i].regs;
1622 /* Mask all interrupts */
1623 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1625 /* Clear all interrupts */
1626 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1629 regs = priv->gfargrp[0].regs;
1630 /* Stop the DMA, and wait for it to stop */
1631 tempval = gfar_read(®s->dmactrl);
1632 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1633 (DMACTRL_GRS | DMACTRL_GTS)) {
1636 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1637 gfar_write(®s->dmactrl, tempval);
1640 ret = spin_event_timeout(((gfar_read(®s->ievent) &
1641 (IEVENT_GRSC | IEVENT_GTSC)) ==
1642 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1643 if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC))
1644 ret = __gfar_is_rx_idle(priv);
1649 /* Halt the receive and transmit queues */
1650 void gfar_halt(struct net_device *dev)
1652 struct gfar_private *priv = netdev_priv(dev);
1653 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1656 gfar_halt_nodisable(dev);
1658 /* Disable Rx and Tx */
1659 tempval = gfar_read(®s->maccfg1);
1660 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1661 gfar_write(®s->maccfg1, tempval);
1664 static void free_grp_irqs(struct gfar_priv_grp *grp)
1666 free_irq(gfar_irq(grp, TX)->irq, grp);
1667 free_irq(gfar_irq(grp, RX)->irq, grp);
1668 free_irq(gfar_irq(grp, ER)->irq, grp);
1671 void stop_gfar(struct net_device *dev)
1673 struct gfar_private *priv = netdev_priv(dev);
1674 unsigned long flags;
1677 phy_stop(priv->phydev);
1681 local_irq_save(flags);
1689 local_irq_restore(flags);
1692 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1693 for (i = 0; i < priv->num_grps; i++)
1694 free_grp_irqs(&priv->gfargrp[i]);
1696 for (i = 0; i < priv->num_grps; i++)
1697 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
1701 free_skb_resources(priv);
1704 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1706 struct txbd8 *txbdp;
1707 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1710 txbdp = tx_queue->tx_bd_base;
1712 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1713 if (!tx_queue->tx_skbuff[i])
1716 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1717 txbdp->length, DMA_TO_DEVICE);
1719 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1722 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1723 txbdp->length, DMA_TO_DEVICE);
1726 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1727 tx_queue->tx_skbuff[i] = NULL;
1729 kfree(tx_queue->tx_skbuff);
1730 tx_queue->tx_skbuff = NULL;
1733 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1735 struct rxbd8 *rxbdp;
1736 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1739 rxbdp = rx_queue->rx_bd_base;
1741 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1742 if (rx_queue->rx_skbuff[i]) {
1743 dma_unmap_single(&priv->ofdev->dev,
1744 rxbdp->bufPtr, priv->rx_buffer_size,
1746 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1747 rx_queue->rx_skbuff[i] = NULL;
1753 kfree(rx_queue->rx_skbuff);
1754 rx_queue->rx_skbuff = NULL;
1757 /* If there are any tx skbs or rx skbs still around, free them.
1758 * Then free tx_skbuff and rx_skbuff
1760 static void free_skb_resources(struct gfar_private *priv)
1762 struct gfar_priv_tx_q *tx_queue = NULL;
1763 struct gfar_priv_rx_q *rx_queue = NULL;
1766 /* Go through all the buffer descriptors and free their data buffers */
1767 for (i = 0; i < priv->num_tx_queues; i++) {
1768 struct netdev_queue *txq;
1770 tx_queue = priv->tx_queue[i];
1771 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1772 if (tx_queue->tx_skbuff)
1773 free_skb_tx_queue(tx_queue);
1774 netdev_tx_reset_queue(txq);
1777 for (i = 0; i < priv->num_rx_queues; i++) {
1778 rx_queue = priv->rx_queue[i];
1779 if (rx_queue->rx_skbuff)
1780 free_skb_rx_queue(rx_queue);
1783 dma_free_coherent(&priv->ofdev->dev,
1784 sizeof(struct txbd8) * priv->total_tx_ring_size +
1785 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1786 priv->tx_queue[0]->tx_bd_base,
1787 priv->tx_queue[0]->tx_bd_dma_base);
1790 void gfar_start(struct net_device *dev)
1792 struct gfar_private *priv = netdev_priv(dev);
1793 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1797 /* Enable Rx and Tx in MACCFG1 */
1798 tempval = gfar_read(®s->maccfg1);
1799 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1800 gfar_write(®s->maccfg1, tempval);
1802 /* Initialize DMACTRL to have WWR and WOP */
1803 tempval = gfar_read(®s->dmactrl);
1804 tempval |= DMACTRL_INIT_SETTINGS;
1805 gfar_write(®s->dmactrl, tempval);
1807 /* Make sure we aren't stopped */
1808 tempval = gfar_read(®s->dmactrl);
1809 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1810 gfar_write(®s->dmactrl, tempval);
1812 for (i = 0; i < priv->num_grps; i++) {
1813 regs = priv->gfargrp[i].regs;
1814 /* Clear THLT/RHLT, so that the DMA starts polling now */
1815 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1816 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1817 /* Unmask the interrupts we look for */
1818 gfar_write(®s->imask, IMASK_DEFAULT);
1821 dev->trans_start = jiffies; /* prevent tx timeout */
1824 void gfar_configure_coalescing(struct gfar_private *priv,
1825 unsigned long tx_mask, unsigned long rx_mask)
1827 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1831 /* Backward compatible case ---- even if we enable
1832 * multiple queues, there's only single reg to program
1834 gfar_write(®s->txic, 0);
1835 if (likely(priv->tx_queue[0]->txcoalescing))
1836 gfar_write(®s->txic, priv->tx_queue[0]->txic);
1838 gfar_write(®s->rxic, 0);
1839 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1840 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
1842 if (priv->mode == MQ_MG_MODE) {
1843 baddr = ®s->txic0;
1844 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1845 gfar_write(baddr + i, 0);
1846 if (likely(priv->tx_queue[i]->txcoalescing))
1847 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1850 baddr = ®s->rxic0;
1851 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1852 gfar_write(baddr + i, 0);
1853 if (likely(priv->rx_queue[i]->rxcoalescing))
1854 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1859 static int register_grp_irqs(struct gfar_priv_grp *grp)
1861 struct gfar_private *priv = grp->priv;
1862 struct net_device *dev = priv->ndev;
1865 /* If the device has multiple interrupts, register for
1866 * them. Otherwise, only register for the one
1868 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1869 /* Install our interrupt handlers for Error,
1870 * Transmit, and Receive
1872 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1873 gfar_irq(grp, ER)->name, grp);
1875 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1876 gfar_irq(grp, ER)->irq);
1880 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1881 gfar_irq(grp, TX)->name, grp);
1883 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1884 gfar_irq(grp, TX)->irq);
1887 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1888 gfar_irq(grp, RX)->name, grp);
1890 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1891 gfar_irq(grp, RX)->irq);
1895 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1896 gfar_irq(grp, TX)->name, grp);
1898 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1899 gfar_irq(grp, TX)->irq);
1907 free_irq(gfar_irq(grp, TX)->irq, grp);
1909 free_irq(gfar_irq(grp, ER)->irq, grp);
1915 /* Bring the controller up and running */
1916 int startup_gfar(struct net_device *ndev)
1918 struct gfar_private *priv = netdev_priv(ndev);
1919 struct gfar __iomem *regs = NULL;
1922 for (i = 0; i < priv->num_grps; i++) {
1923 regs= priv->gfargrp[i].regs;
1924 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1927 regs= priv->gfargrp[0].regs;
1928 err = gfar_alloc_skb_resources(ndev);
1932 gfar_init_mac(ndev);
1934 for (i = 0; i < priv->num_grps; i++) {
1935 err = register_grp_irqs(&priv->gfargrp[i]);
1937 for (j = 0; j < i; j++)
1938 free_grp_irqs(&priv->gfargrp[j]);
1943 /* Start the controller */
1946 phy_start(priv->phydev);
1948 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1953 free_skb_resources(priv);
1957 /* Called when something needs to use the ethernet device
1958 * Returns 0 for success.
1960 static int gfar_enet_open(struct net_device *dev)
1962 struct gfar_private *priv = netdev_priv(dev);
1967 /* Initialize a bunch of registers */
1968 init_registers(dev);
1970 gfar_set_mac_address(dev);
1972 err = init_phy(dev);
1979 err = startup_gfar(dev);
1985 netif_tx_start_all_queues(dev);
1987 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1992 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1994 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1996 memset(fcb, 0, GMAC_FCB_LEN);
2001 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2004 /* If we're here, it's a IP packet with a TCP or UDP
2005 * payload. We set it to checksum, using a pseudo-header
2008 u8 flags = TXFCB_DEFAULT;
2010 /* Tell the controller what the protocol is
2011 * And provide the already calculated phcs
2013 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2015 fcb->phcs = udp_hdr(skb)->check;
2017 fcb->phcs = tcp_hdr(skb)->check;
2019 /* l3os is the distance between the start of the
2020 * frame (skb->data) and the start of the IP hdr.
2021 * l4os is the distance between the start of the
2022 * l3 hdr and the l4 hdr
2024 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2025 fcb->l4os = skb_network_header_len(skb);
2030 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2032 fcb->flags |= TXFCB_VLN;
2033 fcb->vlctl = vlan_tx_tag_get(skb);
2036 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2037 struct txbd8 *base, int ring_size)
2039 struct txbd8 *new_bd = bdp + stride;
2041 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2044 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2047 return skip_txbd(bdp, 1, base, ring_size);
2050 /* This is called by the kernel when a frame is ready for transmission.
2051 * It is pointed to by the dev->hard_start_xmit function pointer
2053 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2055 struct gfar_private *priv = netdev_priv(dev);
2056 struct gfar_priv_tx_q *tx_queue = NULL;
2057 struct netdev_queue *txq;
2058 struct gfar __iomem *regs = NULL;
2059 struct txfcb *fcb = NULL;
2060 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2062 int i, rq = 0, do_tstamp = 0;
2064 unsigned long flags;
2065 unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2067 /* TOE=1 frames larger than 2500 bytes may see excess delays
2068 * before start of transmission.
2070 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2071 skb->ip_summed == CHECKSUM_PARTIAL &&
2075 ret = skb_checksum_help(skb);
2080 rq = skb->queue_mapping;
2081 tx_queue = priv->tx_queue[rq];
2082 txq = netdev_get_tx_queue(dev, rq);
2083 base = tx_queue->tx_bd_base;
2084 regs = tx_queue->grp->regs;
2086 /* check if time stamp should be generated */
2087 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2088 priv->hwts_tx_en)) {
2090 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2093 /* make space for additional header when fcb is needed */
2094 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2095 vlan_tx_tag_present(skb) ||
2096 unlikely(do_tstamp)) &&
2097 (skb_headroom(skb) < fcb_length)) {
2098 struct sk_buff *skb_new;
2100 skb_new = skb_realloc_headroom(skb, fcb_length);
2102 dev->stats.tx_errors++;
2104 return NETDEV_TX_OK;
2108 skb_set_owner_w(skb_new, skb->sk);
2113 /* total number of fragments in the SKB */
2114 nr_frags = skb_shinfo(skb)->nr_frags;
2116 /* calculate the required number of TxBDs for this skb */
2117 if (unlikely(do_tstamp))
2118 nr_txbds = nr_frags + 2;
2120 nr_txbds = nr_frags + 1;
2122 /* check if there is space to queue this packet */
2123 if (nr_txbds > tx_queue->num_txbdfree) {
2124 /* no space, stop the queue */
2125 netif_tx_stop_queue(txq);
2126 dev->stats.tx_fifo_errors++;
2127 return NETDEV_TX_BUSY;
2130 /* Update transmit stats */
2131 tx_queue->stats.tx_bytes += skb->len;
2132 tx_queue->stats.tx_packets++;
2134 txbdp = txbdp_start = tx_queue->cur_tx;
2135 lstatus = txbdp->lstatus;
2137 /* Time stamp insertion requires one additional TxBD */
2138 if (unlikely(do_tstamp))
2139 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2140 tx_queue->tx_ring_size);
2142 if (nr_frags == 0) {
2143 if (unlikely(do_tstamp))
2144 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2147 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2149 /* Place the fragment addresses and lengths into the TxBDs */
2150 for (i = 0; i < nr_frags; i++) {
2151 /* Point at the next BD, wrapping as needed */
2152 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2154 length = skb_shinfo(skb)->frags[i].size;
2156 lstatus = txbdp->lstatus | length |
2157 BD_LFLAG(TXBD_READY);
2159 /* Handle the last BD specially */
2160 if (i == nr_frags - 1)
2161 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2163 bufaddr = skb_frag_dma_map(&priv->ofdev->dev,
2164 &skb_shinfo(skb)->frags[i],
2169 /* set the TxBD length and buffer pointer */
2170 txbdp->bufPtr = bufaddr;
2171 txbdp->lstatus = lstatus;
2174 lstatus = txbdp_start->lstatus;
2177 /* Add TxPAL between FCB and frame if required */
2178 if (unlikely(do_tstamp)) {
2179 skb_push(skb, GMAC_TXPAL_LEN);
2180 memset(skb->data, 0, GMAC_TXPAL_LEN);
2183 /* Set up checksumming */
2184 if (CHECKSUM_PARTIAL == skb->ip_summed) {
2185 fcb = gfar_add_fcb(skb);
2186 /* as specified by errata */
2187 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2188 ((unsigned long)fcb % 0x20) > 0x18)) {
2189 __skb_pull(skb, GMAC_FCB_LEN);
2190 skb_checksum_help(skb);
2192 lstatus |= BD_LFLAG(TXBD_TOE);
2193 gfar_tx_checksum(skb, fcb, fcb_length);
2197 if (vlan_tx_tag_present(skb)) {
2198 if (unlikely(NULL == fcb)) {
2199 fcb = gfar_add_fcb(skb);
2200 lstatus |= BD_LFLAG(TXBD_TOE);
2203 gfar_tx_vlan(skb, fcb);
2206 /* Setup tx hardware time stamping if requested */
2207 if (unlikely(do_tstamp)) {
2208 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2210 fcb = gfar_add_fcb(skb);
2212 lstatus |= BD_LFLAG(TXBD_TOE);
2215 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2216 skb_headlen(skb), DMA_TO_DEVICE);
2218 /* If time stamping is requested one additional TxBD must be set up. The
2219 * first TxBD points to the FCB and must have a data length of
2220 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2221 * the full frame length.
2223 if (unlikely(do_tstamp)) {
2224 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2225 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2226 (skb_headlen(skb) - fcb_length);
2227 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2229 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2232 netdev_tx_sent_queue(txq, skb->len);
2234 /* We can work in parallel with gfar_clean_tx_ring(), except
2235 * when modifying num_txbdfree. Note that we didn't grab the lock
2236 * when we were reading the num_txbdfree and checking for available
2237 * space, that's because outside of this function it can only grow,
2238 * and once we've got needed space, it cannot suddenly disappear.
2240 * The lock also protects us from gfar_error(), which can modify
2241 * regs->tstat and thus retrigger the transfers, which is why we
2242 * also must grab the lock before setting ready bit for the first
2243 * to be transmitted BD.
2245 spin_lock_irqsave(&tx_queue->txlock, flags);
2247 /* The powerpc-specific eieio() is used, as wmb() has too strong
2248 * semantics (it requires synchronization between cacheable and
2249 * uncacheable mappings, which eieio doesn't provide and which we
2250 * don't need), thus requiring a more expensive sync instruction. At
2251 * some point, the set of architecture-independent barrier functions
2252 * should be expanded to include weaker barriers.
2256 txbdp_start->lstatus = lstatus;
2258 eieio(); /* force lstatus write before tx_skbuff */
2260 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2262 /* Update the current skb pointer to the next entry we will use
2263 * (wrapping if necessary)
2265 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2266 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2268 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2270 /* reduce TxBD free count */
2271 tx_queue->num_txbdfree -= (nr_txbds);
2273 /* If the next BD still needs to be cleaned up, then the bds
2274 * are full. We need to tell the kernel to stop sending us stuff.
2276 if (!tx_queue->num_txbdfree) {
2277 netif_tx_stop_queue(txq);
2279 dev->stats.tx_fifo_errors++;
2282 /* Tell the DMA to go go go */
2283 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2286 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2288 return NETDEV_TX_OK;
2291 /* Stops the kernel queue, and halts the controller */
2292 static int gfar_close(struct net_device *dev)
2294 struct gfar_private *priv = netdev_priv(dev);
2298 cancel_work_sync(&priv->reset_task);
2301 /* Disconnect from the PHY */
2302 phy_disconnect(priv->phydev);
2303 priv->phydev = NULL;
2305 netif_tx_stop_all_queues(dev);
2310 /* Changes the mac address if the controller is not running. */
2311 static int gfar_set_mac_address(struct net_device *dev)
2313 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2318 /* Check if rx parser should be activated */
2319 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2321 struct gfar __iomem *regs;
2324 regs = priv->gfargrp[0].regs;
2326 tempval = gfar_read(®s->rctrl);
2327 /* If parse is no longer required, then disable parser */
2328 if (tempval & RCTRL_REQ_PARSER)
2329 tempval |= RCTRL_PRSDEP_INIT;
2331 tempval &= ~RCTRL_PRSDEP_INIT;
2332 gfar_write(®s->rctrl, tempval);
2335 /* Enables and disables VLAN insertion/extraction */
2336 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2338 struct gfar_private *priv = netdev_priv(dev);
2339 struct gfar __iomem *regs = NULL;
2340 unsigned long flags;
2343 regs = priv->gfargrp[0].regs;
2344 local_irq_save(flags);
2347 if (features & NETIF_F_HW_VLAN_TX) {
2348 /* Enable VLAN tag insertion */
2349 tempval = gfar_read(®s->tctrl);
2350 tempval |= TCTRL_VLINS;
2351 gfar_write(®s->tctrl, tempval);
2353 /* Disable VLAN tag insertion */
2354 tempval = gfar_read(®s->tctrl);
2355 tempval &= ~TCTRL_VLINS;
2356 gfar_write(®s->tctrl, tempval);
2359 if (features & NETIF_F_HW_VLAN_RX) {
2360 /* Enable VLAN tag extraction */
2361 tempval = gfar_read(®s->rctrl);
2362 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2363 gfar_write(®s->rctrl, tempval);
2365 /* Disable VLAN tag extraction */
2366 tempval = gfar_read(®s->rctrl);
2367 tempval &= ~RCTRL_VLEX;
2368 gfar_write(®s->rctrl, tempval);
2370 gfar_check_rx_parser_mode(priv);
2373 gfar_change_mtu(dev, dev->mtu);
2376 local_irq_restore(flags);
2379 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2381 int tempsize, tempval;
2382 struct gfar_private *priv = netdev_priv(dev);
2383 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2384 int oldsize = priv->rx_buffer_size;
2385 int frame_size = new_mtu + ETH_HLEN;
2387 if (gfar_is_vlan_on(priv))
2388 frame_size += VLAN_HLEN;
2390 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2391 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2395 if (gfar_uses_fcb(priv))
2396 frame_size += GMAC_FCB_LEN;
2398 frame_size += priv->padding;
2400 tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2401 INCREMENTAL_BUFFER_SIZE;
2403 /* Only stop and start the controller if it isn't already
2404 * stopped, and we changed something
2406 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2409 priv->rx_buffer_size = tempsize;
2413 gfar_write(®s->mrblr, priv->rx_buffer_size);
2414 gfar_write(®s->maxfrm, priv->rx_buffer_size);
2416 /* If the mtu is larger than the max size for standard
2417 * ethernet frames (ie, a jumbo frame), then set maccfg2
2418 * to allow huge frames, and to check the length
2420 tempval = gfar_read(®s->maccfg2);
2422 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2423 gfar_has_errata(priv, GFAR_ERRATA_74))
2424 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2426 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2428 gfar_write(®s->maccfg2, tempval);
2430 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2436 /* gfar_reset_task gets scheduled when a packet has not been
2437 * transmitted after a set amount of time.
2438 * For now, assume that clearing out all the structures, and
2439 * starting over will fix the problem.
2441 static void gfar_reset_task(struct work_struct *work)
2443 struct gfar_private *priv = container_of(work, struct gfar_private,
2445 struct net_device *dev = priv->ndev;
2447 if (dev->flags & IFF_UP) {
2448 netif_tx_stop_all_queues(dev);
2451 netif_tx_start_all_queues(dev);
2454 netif_tx_schedule_all(dev);
2457 static void gfar_timeout(struct net_device *dev)
2459 struct gfar_private *priv = netdev_priv(dev);
2461 dev->stats.tx_errors++;
2462 schedule_work(&priv->reset_task);
2465 static void gfar_align_skb(struct sk_buff *skb)
2467 /* We need the data buffer to be aligned properly. We will reserve
2468 * as many bytes as needed to align the data properly
2470 skb_reserve(skb, RXBUF_ALIGNMENT -
2471 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2474 /* Interrupt Handler for Transmit complete */
2475 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2477 struct net_device *dev = tx_queue->dev;
2478 struct netdev_queue *txq;
2479 struct gfar_private *priv = netdev_priv(dev);
2480 struct gfar_priv_rx_q *rx_queue = NULL;
2481 struct txbd8 *bdp, *next = NULL;
2482 struct txbd8 *lbdp = NULL;
2483 struct txbd8 *base = tx_queue->tx_bd_base;
2484 struct sk_buff *skb;
2486 int tx_ring_size = tx_queue->tx_ring_size;
2487 int frags = 0, nr_txbds = 0;
2490 int tqi = tx_queue->qindex;
2491 unsigned int bytes_sent = 0;
2495 rx_queue = priv->rx_queue[tqi];
2496 txq = netdev_get_tx_queue(dev, tqi);
2497 bdp = tx_queue->dirty_tx;
2498 skb_dirtytx = tx_queue->skb_dirtytx;
2500 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2501 unsigned long flags;
2503 frags = skb_shinfo(skb)->nr_frags;
2505 /* When time stamping, one additional TxBD must be freed.
2506 * Also, we need to dma_unmap_single() the TxPAL.
2508 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2509 nr_txbds = frags + 2;
2511 nr_txbds = frags + 1;
2513 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2515 lstatus = lbdp->lstatus;
2517 /* Only clean completed frames */
2518 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2519 (lstatus & BD_LENGTH_MASK))
2522 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2523 next = next_txbd(bdp, base, tx_ring_size);
2524 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2526 buflen = bdp->length;
2528 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2529 buflen, DMA_TO_DEVICE);
2531 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2532 struct skb_shared_hwtstamps shhwtstamps;
2533 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2535 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2536 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2537 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2538 skb_tstamp_tx(skb, &shhwtstamps);
2539 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2543 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2544 bdp = next_txbd(bdp, base, tx_ring_size);
2546 for (i = 0; i < frags; i++) {
2547 dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr,
2548 bdp->length, DMA_TO_DEVICE);
2549 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2550 bdp = next_txbd(bdp, base, tx_ring_size);
2553 bytes_sent += skb->len;
2555 dev_kfree_skb_any(skb);
2557 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2559 skb_dirtytx = (skb_dirtytx + 1) &
2560 TX_RING_MOD_MASK(tx_ring_size);
2563 spin_lock_irqsave(&tx_queue->txlock, flags);
2564 tx_queue->num_txbdfree += nr_txbds;
2565 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2568 /* If we freed a buffer, we can restart transmission, if necessary */
2569 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2570 netif_wake_subqueue(dev, tqi);
2572 /* Update dirty indicators */
2573 tx_queue->skb_dirtytx = skb_dirtytx;
2574 tx_queue->dirty_tx = bdp;
2576 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2581 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2583 unsigned long flags;
2585 spin_lock_irqsave(&gfargrp->grplock, flags);
2586 if (napi_schedule_prep(&gfargrp->napi)) {
2587 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2588 __napi_schedule(&gfargrp->napi);
2590 /* Clear IEVENT, so interrupts aren't called again
2591 * because of the packets that have already arrived.
2593 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2595 spin_unlock_irqrestore(&gfargrp->grplock, flags);
2599 /* Interrupt Handler for Transmit complete */
2600 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2602 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2606 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2607 struct sk_buff *skb)
2609 struct net_device *dev = rx_queue->dev;
2610 struct gfar_private *priv = netdev_priv(dev);
2613 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2614 priv->rx_buffer_size, DMA_FROM_DEVICE);
2615 gfar_init_rxbdp(rx_queue, bdp, buf);
2618 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2620 struct gfar_private *priv = netdev_priv(dev);
2621 struct sk_buff *skb;
2623 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2627 gfar_align_skb(skb);
2632 struct sk_buff *gfar_new_skb(struct net_device *dev)
2634 return gfar_alloc_skb(dev);
2637 static inline void count_errors(unsigned short status, struct net_device *dev)
2639 struct gfar_private *priv = netdev_priv(dev);
2640 struct net_device_stats *stats = &dev->stats;
2641 struct gfar_extra_stats *estats = &priv->extra_stats;
2643 /* If the packet was truncated, none of the other errors matter */
2644 if (status & RXBD_TRUNCATED) {
2645 stats->rx_length_errors++;
2647 atomic64_inc(&estats->rx_trunc);
2651 /* Count the errors, if there were any */
2652 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2653 stats->rx_length_errors++;
2655 if (status & RXBD_LARGE)
2656 atomic64_inc(&estats->rx_large);
2658 atomic64_inc(&estats->rx_short);
2660 if (status & RXBD_NONOCTET) {
2661 stats->rx_frame_errors++;
2662 atomic64_inc(&estats->rx_nonoctet);
2664 if (status & RXBD_CRCERR) {
2665 atomic64_inc(&estats->rx_crcerr);
2666 stats->rx_crc_errors++;
2668 if (status & RXBD_OVERRUN) {
2669 atomic64_inc(&estats->rx_overrun);
2670 stats->rx_crc_errors++;
2674 irqreturn_t gfar_receive(int irq, void *grp_id)
2676 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2680 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2682 /* If valid headers were found, and valid sums
2683 * were verified, then we tell the kernel that no
2684 * checksumming is necessary. Otherwise, it is [FIXME]
2686 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2687 skb->ip_summed = CHECKSUM_UNNECESSARY;
2689 skb_checksum_none_assert(skb);
2693 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2694 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2695 int amount_pull, struct napi_struct *napi)
2697 struct gfar_private *priv = netdev_priv(dev);
2698 struct rxfcb *fcb = NULL;
2702 /* fcb is at the beginning if exists */
2703 fcb = (struct rxfcb *)skb->data;
2705 /* Remove the FCB from the skb
2706 * Remove the padded bytes, if there are any
2709 skb_record_rx_queue(skb, fcb->rq);
2710 skb_pull(skb, amount_pull);
2713 /* Get receive timestamp from the skb */
2714 if (priv->hwts_rx_en) {
2715 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2716 u64 *ns = (u64 *) skb->data;
2718 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2719 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2723 skb_pull(skb, priv->padding);
2725 if (dev->features & NETIF_F_RXCSUM)
2726 gfar_rx_checksum(skb, fcb);
2728 /* Tell the skb what kind of packet this is */
2729 skb->protocol = eth_type_trans(skb, dev);
2731 /* There's need to check for NETIF_F_HW_VLAN_RX here.
2732 * Even if vlan rx accel is disabled, on some chips
2733 * RXFCB_VLN is pseudo randomly set.
2735 if (dev->features & NETIF_F_HW_VLAN_RX &&
2736 fcb->flags & RXFCB_VLN)
2737 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2739 /* Send the packet up the stack */
2740 ret = napi_gro_receive(napi, skb);
2742 if (GRO_DROP == ret)
2743 atomic64_inc(&priv->extra_stats.kernel_dropped);
2748 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2749 * until the budget/quota has been reached. Returns the number
2752 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2754 struct net_device *dev = rx_queue->dev;
2755 struct rxbd8 *bdp, *base;
2756 struct sk_buff *skb;
2760 struct gfar_private *priv = netdev_priv(dev);
2762 /* Get the first full descriptor */
2763 bdp = rx_queue->cur_rx;
2764 base = rx_queue->rx_bd_base;
2766 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2768 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2769 struct sk_buff *newskb;
2773 /* Add another skb for the future */
2774 newskb = gfar_new_skb(dev);
2776 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2778 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2779 priv->rx_buffer_size, DMA_FROM_DEVICE);
2781 if (unlikely(!(bdp->status & RXBD_ERR) &&
2782 bdp->length > priv->rx_buffer_size))
2783 bdp->status = RXBD_LARGE;
2785 /* We drop the frame if we failed to allocate a new buffer */
2786 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2787 bdp->status & RXBD_ERR)) {
2788 count_errors(bdp->status, dev);
2790 if (unlikely(!newskb))
2795 /* Increment the number of packets */
2796 rx_queue->stats.rx_packets++;
2800 pkt_len = bdp->length - ETH_FCS_LEN;
2801 /* Remove the FCS from the packet length */
2802 skb_put(skb, pkt_len);
2803 rx_queue->stats.rx_bytes += pkt_len;
2804 skb_record_rx_queue(skb, rx_queue->qindex);
2805 gfar_process_frame(dev, skb, amount_pull,
2806 &rx_queue->grp->napi);
2809 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2810 rx_queue->stats.rx_dropped++;
2811 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2816 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2818 /* Setup the new bdp */
2819 gfar_new_rxbdp(rx_queue, bdp, newskb);
2821 /* Update to the next pointer */
2822 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2824 /* update to point at the next skb */
2825 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2826 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2829 /* Update the current rxbd pointer to be the next one */
2830 rx_queue->cur_rx = bdp;
2835 static int gfar_poll(struct napi_struct *napi, int budget)
2837 struct gfar_priv_grp *gfargrp =
2838 container_of(napi, struct gfar_priv_grp, napi);
2839 struct gfar_private *priv = gfargrp->priv;
2840 struct gfar __iomem *regs = gfargrp->regs;
2841 struct gfar_priv_tx_q *tx_queue = NULL;
2842 struct gfar_priv_rx_q *rx_queue = NULL;
2843 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2844 int tx_cleaned = 0, i, left_over_budget = budget;
2845 unsigned long serviced_queues = 0;
2848 num_queues = gfargrp->num_rx_queues;
2849 budget_per_queue = budget/num_queues;
2851 /* Clear IEVENT, so interrupts aren't called again
2852 * because of the packets that have already arrived
2854 gfar_write(®s->ievent, IEVENT_RTX_MASK);
2856 while (num_queues && left_over_budget) {
2857 budget_per_queue = left_over_budget/num_queues;
2858 left_over_budget = 0;
2860 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2861 if (test_bit(i, &serviced_queues))
2863 rx_queue = priv->rx_queue[i];
2864 tx_queue = priv->tx_queue[rx_queue->qindex];
2866 tx_cleaned += gfar_clean_tx_ring(tx_queue);
2867 rx_cleaned_per_queue =
2868 gfar_clean_rx_ring(rx_queue, budget_per_queue);
2869 rx_cleaned += rx_cleaned_per_queue;
2870 if (rx_cleaned_per_queue < budget_per_queue) {
2871 left_over_budget = left_over_budget +
2873 rx_cleaned_per_queue);
2874 set_bit(i, &serviced_queues);
2883 if (rx_cleaned < budget) {
2884 napi_complete(napi);
2886 /* Clear the halt bit in RSTAT */
2887 gfar_write(®s->rstat, gfargrp->rstat);
2889 gfar_write(®s->imask, IMASK_DEFAULT);
2891 /* If we are coalescing interrupts, update the timer
2892 * Otherwise, clear it
2894 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2895 gfargrp->tx_bit_map);
2901 #ifdef CONFIG_NET_POLL_CONTROLLER
2902 /* Polling 'interrupt' - used by things like netconsole to send skbs
2903 * without having to re-enable interrupts. It's not called while
2904 * the interrupt routine is executing.
2906 static void gfar_netpoll(struct net_device *dev)
2908 struct gfar_private *priv = netdev_priv(dev);
2911 /* If the device has multiple interrupts, run tx/rx */
2912 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2913 for (i = 0; i < priv->num_grps; i++) {
2914 disable_irq(priv->gfargrp[i].interruptTransmit);
2915 disable_irq(priv->gfargrp[i].interruptReceive);
2916 disable_irq(priv->gfargrp[i].interruptError);
2917 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2919 enable_irq(priv->gfargrp[i].interruptError);
2920 enable_irq(priv->gfargrp[i].interruptReceive);
2921 enable_irq(priv->gfargrp[i].interruptTransmit);
2924 for (i = 0; i < priv->num_grps; i++) {
2925 disable_irq(priv->gfargrp[i].interruptTransmit);
2926 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2928 enable_irq(priv->gfargrp[i].interruptTransmit);
2934 /* The interrupt handler for devices with one interrupt */
2935 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2937 struct gfar_priv_grp *gfargrp = grp_id;
2939 /* Save ievent for future reference */
2940 u32 events = gfar_read(&gfargrp->regs->ievent);
2942 /* Check for reception */
2943 if (events & IEVENT_RX_MASK)
2944 gfar_receive(irq, grp_id);
2946 /* Check for transmit completion */
2947 if (events & IEVENT_TX_MASK)
2948 gfar_transmit(irq, grp_id);
2950 /* Check for errors */
2951 if (events & IEVENT_ERR_MASK)
2952 gfar_error(irq, grp_id);
2957 /* Called every time the controller might need to be made
2958 * aware of new link state. The PHY code conveys this
2959 * information through variables in the phydev structure, and this
2960 * function converts those variables into the appropriate
2961 * register values, and can bring down the device if needed.
2963 static void adjust_link(struct net_device *dev)
2965 struct gfar_private *priv = netdev_priv(dev);
2966 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2967 unsigned long flags;
2968 struct phy_device *phydev = priv->phydev;
2971 local_irq_save(flags);
2975 u32 tempval = gfar_read(®s->maccfg2);
2976 u32 ecntrl = gfar_read(®s->ecntrl);
2978 /* Now we make sure that we can be in full duplex mode.
2979 * If not, we operate in half-duplex mode.
2981 if (phydev->duplex != priv->oldduplex) {
2983 if (!(phydev->duplex))
2984 tempval &= ~(MACCFG2_FULL_DUPLEX);
2986 tempval |= MACCFG2_FULL_DUPLEX;
2988 priv->oldduplex = phydev->duplex;
2991 if (phydev->speed != priv->oldspeed) {
2993 switch (phydev->speed) {
2996 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2998 ecntrl &= ~(ECNTRL_R100);
3003 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3005 /* Reduced mode distinguishes
3006 * between 10 and 100
3008 if (phydev->speed == SPEED_100)
3009 ecntrl |= ECNTRL_R100;
3011 ecntrl &= ~(ECNTRL_R100);
3014 netif_warn(priv, link, dev,
3015 "Ack! Speed (%d) is not 10/100/1000!\n",
3020 priv->oldspeed = phydev->speed;
3023 gfar_write(®s->maccfg2, tempval);
3024 gfar_write(®s->ecntrl, ecntrl);
3026 if (!priv->oldlink) {
3030 } else if (priv->oldlink) {
3034 priv->oldduplex = -1;
3037 if (new_state && netif_msg_link(priv))
3038 phy_print_status(phydev);
3040 local_irq_restore(flags);
3043 /* Update the hash table based on the current list of multicast
3044 * addresses we subscribe to. Also, change the promiscuity of
3045 * the device based on the flags (this function is called
3046 * whenever dev->flags is changed
3048 static void gfar_set_multi(struct net_device *dev)
3050 struct netdev_hw_addr *ha;
3051 struct gfar_private *priv = netdev_priv(dev);
3052 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3055 if (dev->flags & IFF_PROMISC) {
3056 /* Set RCTRL to PROM */
3057 tempval = gfar_read(®s->rctrl);
3058 tempval |= RCTRL_PROM;
3059 gfar_write(®s->rctrl, tempval);
3061 /* Set RCTRL to not PROM */
3062 tempval = gfar_read(®s->rctrl);
3063 tempval &= ~(RCTRL_PROM);
3064 gfar_write(®s->rctrl, tempval);
3067 if (dev->flags & IFF_ALLMULTI) {
3068 /* Set the hash to rx all multicast frames */
3069 gfar_write(®s->igaddr0, 0xffffffff);
3070 gfar_write(®s->igaddr1, 0xffffffff);
3071 gfar_write(®s->igaddr2, 0xffffffff);
3072 gfar_write(®s->igaddr3, 0xffffffff);
3073 gfar_write(®s->igaddr4, 0xffffffff);
3074 gfar_write(®s->igaddr5, 0xffffffff);
3075 gfar_write(®s->igaddr6, 0xffffffff);
3076 gfar_write(®s->igaddr7, 0xffffffff);
3077 gfar_write(®s->gaddr0, 0xffffffff);
3078 gfar_write(®s->gaddr1, 0xffffffff);
3079 gfar_write(®s->gaddr2, 0xffffffff);
3080 gfar_write(®s->gaddr3, 0xffffffff);
3081 gfar_write(®s->gaddr4, 0xffffffff);
3082 gfar_write(®s->gaddr5, 0xffffffff);
3083 gfar_write(®s->gaddr6, 0xffffffff);
3084 gfar_write(®s->gaddr7, 0xffffffff);
3089 /* zero out the hash */
3090 gfar_write(®s->igaddr0, 0x0);
3091 gfar_write(®s->igaddr1, 0x0);
3092 gfar_write(®s->igaddr2, 0x0);
3093 gfar_write(®s->igaddr3, 0x0);
3094 gfar_write(®s->igaddr4, 0x0);
3095 gfar_write(®s->igaddr5, 0x0);
3096 gfar_write(®s->igaddr6, 0x0);
3097 gfar_write(®s->igaddr7, 0x0);
3098 gfar_write(®s->gaddr0, 0x0);
3099 gfar_write(®s->gaddr1, 0x0);
3100 gfar_write(®s->gaddr2, 0x0);
3101 gfar_write(®s->gaddr3, 0x0);
3102 gfar_write(®s->gaddr4, 0x0);
3103 gfar_write(®s->gaddr5, 0x0);
3104 gfar_write(®s->gaddr6, 0x0);
3105 gfar_write(®s->gaddr7, 0x0);
3107 /* If we have extended hash tables, we need to
3108 * clear the exact match registers to prepare for
3111 if (priv->extended_hash) {
3112 em_num = GFAR_EM_NUM + 1;
3113 gfar_clear_exact_match(dev);
3120 if (netdev_mc_empty(dev))
3123 /* Parse the list, and set the appropriate bits */
3124 netdev_for_each_mc_addr(ha, dev) {
3126 gfar_set_mac_for_addr(dev, idx, ha->addr);
3129 gfar_set_hash_for_addr(dev, ha->addr);
3135 /* Clears each of the exact match registers to zero, so they
3136 * don't interfere with normal reception
3138 static void gfar_clear_exact_match(struct net_device *dev)
3141 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3143 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3144 gfar_set_mac_for_addr(dev, idx, zero_arr);
3147 /* Set the appropriate hash bit for the given addr */
3148 /* The algorithm works like so:
3149 * 1) Take the Destination Address (ie the multicast address), and
3150 * do a CRC on it (little endian), and reverse the bits of the
3152 * 2) Use the 8 most significant bits as a hash into a 256-entry
3153 * table. The table is controlled through 8 32-bit registers:
3154 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3155 * gaddr7. This means that the 3 most significant bits in the
3156 * hash index which gaddr register to use, and the 5 other bits
3157 * indicate which bit (assuming an IBM numbering scheme, which
3158 * for PowerPC (tm) is usually the case) in the register holds
3161 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3164 struct gfar_private *priv = netdev_priv(dev);
3165 u32 result = ether_crc(ETH_ALEN, addr);
3166 int width = priv->hash_width;
3167 u8 whichbit = (result >> (32 - width)) & 0x1f;
3168 u8 whichreg = result >> (32 - width + 5);
3169 u32 value = (1 << (31-whichbit));
3171 tempval = gfar_read(priv->hash_regs[whichreg]);
3173 gfar_write(priv->hash_regs[whichreg], tempval);
3177 /* There are multiple MAC Address register pairs on some controllers
3178 * This function sets the numth pair to a given address
3180 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3183 struct gfar_private *priv = netdev_priv(dev);
3184 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3186 char tmpbuf[ETH_ALEN];
3188 u32 __iomem *macptr = ®s->macstnaddr1;
3192 /* Now copy it into the mac registers backwards, cuz
3193 * little endian is silly
3195 for (idx = 0; idx < ETH_ALEN; idx++)
3196 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3198 gfar_write(macptr, *((u32 *) (tmpbuf)));
3200 tempval = *((u32 *) (tmpbuf + 4));
3202 gfar_write(macptr+1, tempval);
3205 /* GFAR error interrupt handler */
3206 static irqreturn_t gfar_error(int irq, void *grp_id)
3208 struct gfar_priv_grp *gfargrp = grp_id;
3209 struct gfar __iomem *regs = gfargrp->regs;
3210 struct gfar_private *priv= gfargrp->priv;
3211 struct net_device *dev = priv->ndev;
3213 /* Save ievent for future reference */
3214 u32 events = gfar_read(®s->ievent);
3217 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3219 /* Magic Packet is not an error. */
3220 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3221 (events & IEVENT_MAG))
3222 events &= ~IEVENT_MAG;
3225 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3227 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3228 events, gfar_read(®s->imask));
3230 /* Update the error counters */
3231 if (events & IEVENT_TXE) {
3232 dev->stats.tx_errors++;
3234 if (events & IEVENT_LC)
3235 dev->stats.tx_window_errors++;
3236 if (events & IEVENT_CRL)
3237 dev->stats.tx_aborted_errors++;
3238 if (events & IEVENT_XFUN) {
3239 unsigned long flags;
3241 netif_dbg(priv, tx_err, dev,
3242 "TX FIFO underrun, packet dropped\n");
3243 dev->stats.tx_dropped++;
3244 atomic64_inc(&priv->extra_stats.tx_underrun);
3246 local_irq_save(flags);
3249 /* Reactivate the Tx Queues */
3250 gfar_write(®s->tstat, gfargrp->tstat);
3253 local_irq_restore(flags);
3255 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3257 if (events & IEVENT_BSY) {
3258 dev->stats.rx_errors++;
3259 atomic64_inc(&priv->extra_stats.rx_bsy);
3261 gfar_receive(irq, grp_id);
3263 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3264 gfar_read(®s->rstat));
3266 if (events & IEVENT_BABR) {
3267 dev->stats.rx_errors++;
3268 atomic64_inc(&priv->extra_stats.rx_babr);
3270 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3272 if (events & IEVENT_EBERR) {
3273 atomic64_inc(&priv->extra_stats.eberr);
3274 netif_dbg(priv, rx_err, dev, "bus error\n");
3276 if (events & IEVENT_RXC)
3277 netif_dbg(priv, rx_status, dev, "control frame\n");
3279 if (events & IEVENT_BABT) {
3280 atomic64_inc(&priv->extra_stats.tx_babt);
3281 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3286 static struct of_device_id gfar_match[] =
3290 .compatible = "gianfar",
3293 .compatible = "fsl,etsec2",
3297 MODULE_DEVICE_TABLE(of, gfar_match);
3299 /* Structure for a device driver */
3300 static struct platform_driver gfar_driver = {
3302 .name = "fsl-gianfar",
3303 .owner = THIS_MODULE,
3305 .of_match_table = gfar_match,
3307 .probe = gfar_probe,
3308 .remove = gfar_remove,
3311 module_platform_driver(gfar_driver);