2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2012 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
48 #include <net/checksum.h>
52 #include <asm/byteorder.h>
53 #include <linux/uaccess.h>
56 #include <asm/idprom.h>
65 /* Functions & macros to verify TG3_FLAGS types */
67 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
69 return test_bit(flag, bits);
72 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
77 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
79 clear_bit(flag, bits);
82 #define tg3_flag(tp, flag) \
83 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
84 #define tg3_flag_set(tp, flag) \
85 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
86 #define tg3_flag_clear(tp, flag) \
87 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
89 #define DRV_MODULE_NAME "tg3"
91 #define TG3_MIN_NUM 123
92 #define DRV_MODULE_VERSION \
93 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
94 #define DRV_MODULE_RELDATE "March 21, 2012"
96 #define RESET_KIND_SHUTDOWN 0
97 #define RESET_KIND_INIT 1
98 #define RESET_KIND_SUSPEND 2
100 #define TG3_DEF_RX_MODE 0
101 #define TG3_DEF_TX_MODE 0
102 #define TG3_DEF_MSG_ENABLE \
112 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
114 /* length of time before we decide the hardware is borked,
115 * and dev->tx_timeout() should be called to fix the problem
118 #define TG3_TX_TIMEOUT (5 * HZ)
120 /* hardware minimum and maximum for a single frame's data payload */
121 #define TG3_MIN_MTU 60
122 #define TG3_MAX_MTU(tp) \
123 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
125 /* These numbers seem to be hard coded in the NIC firmware somehow.
126 * You can't change the ring sizes, but you can change where you place
127 * them in the NIC onboard memory.
129 #define TG3_RX_STD_RING_SIZE(tp) \
130 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
131 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
132 #define TG3_DEF_RX_RING_PENDING 200
133 #define TG3_RX_JMB_RING_SIZE(tp) \
134 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
135 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
136 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
138 /* Do not place this n-ring entries value into the tp struct itself,
139 * we really want to expose these constants to GCC so that modulo et
140 * al. operations are done with shifts and masks instead of with
141 * hw multiply/modulo instructions. Another solution would be to
142 * replace things like '% foo' with '& (foo - 1)'.
145 #define TG3_TX_RING_SIZE 512
146 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
148 #define TG3_RX_STD_RING_BYTES(tp) \
149 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
150 #define TG3_RX_JMB_RING_BYTES(tp) \
151 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
152 #define TG3_RX_RCB_RING_BYTES(tp) \
153 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
154 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
156 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
158 #define TG3_DMA_BYTE_ENAB 64
160 #define TG3_RX_STD_DMA_SZ 1536
161 #define TG3_RX_JMB_DMA_SZ 9046
163 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
165 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
166 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
168 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
169 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
171 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
172 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
174 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
175 * that are at least dword aligned when used in PCIX mode. The driver
176 * works around this bug by double copying the packet. This workaround
177 * is built into the normal double copy length check for efficiency.
179 * However, the double copy is only necessary on those architectures
180 * where unaligned memory accesses are inefficient. For those architectures
181 * where unaligned memory accesses incur little penalty, we can reintegrate
182 * the 5701 in the normal rx path. Doing so saves a device structure
183 * dereference by hardcoding the double copy threshold in place.
185 #define TG3_RX_COPY_THRESHOLD 256
186 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
187 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
189 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
192 #if (NET_IP_ALIGN != 0)
193 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
195 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
198 /* minimum number of free TX descriptors required to wake up TX process */
199 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
200 #define TG3_TX_BD_DMA_MAX_2K 2048
201 #define TG3_TX_BD_DMA_MAX_4K 4096
203 #define TG3_RAW_IP_ALIGN 2
205 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
206 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
208 #define FIRMWARE_TG3 "tigon/tg3.bin"
209 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
210 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
212 static char version[] __devinitdata =
213 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
215 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
216 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
217 MODULE_LICENSE("GPL");
218 MODULE_VERSION(DRV_MODULE_VERSION);
219 MODULE_FIRMWARE(FIRMWARE_TG3);
220 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
221 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
223 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
224 module_param(tg3_debug, int, 0);
225 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
227 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
301 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
302 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
303 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
304 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
305 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
306 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
307 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
308 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
312 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
314 static const struct {
315 const char string[ETH_GSTRING_LEN];
316 } ethtool_stats_keys[] = {
319 { "rx_ucast_packets" },
320 { "rx_mcast_packets" },
321 { "rx_bcast_packets" },
323 { "rx_align_errors" },
324 { "rx_xon_pause_rcvd" },
325 { "rx_xoff_pause_rcvd" },
326 { "rx_mac_ctrl_rcvd" },
327 { "rx_xoff_entered" },
328 { "rx_frame_too_long_errors" },
330 { "rx_undersize_packets" },
331 { "rx_in_length_errors" },
332 { "rx_out_length_errors" },
333 { "rx_64_or_less_octet_packets" },
334 { "rx_65_to_127_octet_packets" },
335 { "rx_128_to_255_octet_packets" },
336 { "rx_256_to_511_octet_packets" },
337 { "rx_512_to_1023_octet_packets" },
338 { "rx_1024_to_1522_octet_packets" },
339 { "rx_1523_to_2047_octet_packets" },
340 { "rx_2048_to_4095_octet_packets" },
341 { "rx_4096_to_8191_octet_packets" },
342 { "rx_8192_to_9022_octet_packets" },
349 { "tx_flow_control" },
351 { "tx_single_collisions" },
352 { "tx_mult_collisions" },
354 { "tx_excessive_collisions" },
355 { "tx_late_collisions" },
356 { "tx_collide_2times" },
357 { "tx_collide_3times" },
358 { "tx_collide_4times" },
359 { "tx_collide_5times" },
360 { "tx_collide_6times" },
361 { "tx_collide_7times" },
362 { "tx_collide_8times" },
363 { "tx_collide_9times" },
364 { "tx_collide_10times" },
365 { "tx_collide_11times" },
366 { "tx_collide_12times" },
367 { "tx_collide_13times" },
368 { "tx_collide_14times" },
369 { "tx_collide_15times" },
370 { "tx_ucast_packets" },
371 { "tx_mcast_packets" },
372 { "tx_bcast_packets" },
373 { "tx_carrier_sense_errors" },
377 { "dma_writeq_full" },
378 { "dma_write_prioq_full" },
382 { "rx_threshold_hit" },
384 { "dma_readq_full" },
385 { "dma_read_prioq_full" },
386 { "tx_comp_queue_full" },
388 { "ring_set_send_prod_index" },
389 { "ring_status_update" },
391 { "nic_avoided_irqs" },
392 { "nic_tx_threshold_hit" },
394 { "mbuf_lwm_thresh_hit" },
397 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
400 static const struct {
401 const char string[ETH_GSTRING_LEN];
402 } ethtool_test_keys[] = {
403 { "nvram test (online) " },
404 { "link test (online) " },
405 { "register test (offline)" },
406 { "memory test (offline)" },
407 { "mac loopback test (offline)" },
408 { "phy loopback test (offline)" },
409 { "ext loopback test (offline)" },
410 { "interrupt test (offline)" },
413 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
416 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
418 writel(val, tp->regs + off);
421 static u32 tg3_read32(struct tg3 *tp, u32 off)
423 return readl(tp->regs + off);
426 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
428 writel(val, tp->aperegs + off);
431 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
433 return readl(tp->aperegs + off);
436 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
440 spin_lock_irqsave(&tp->indirect_lock, flags);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
442 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
443 spin_unlock_irqrestore(&tp->indirect_lock, flags);
446 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
448 writel(val, tp->regs + off);
449 readl(tp->regs + off);
452 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
459 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
460 spin_unlock_irqrestore(&tp->indirect_lock, flags);
464 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
468 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
469 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
470 TG3_64BIT_REG_LOW, val);
473 if (off == TG3_RX_STD_PROD_IDX_REG) {
474 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
475 TG3_64BIT_REG_LOW, val);
479 spin_lock_irqsave(&tp->indirect_lock, flags);
480 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
481 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
482 spin_unlock_irqrestore(&tp->indirect_lock, flags);
484 /* In indirect mode when disabling interrupts, we also need
485 * to clear the interrupt bit in the GRC local ctrl register.
487 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
489 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
490 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
494 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
501 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
502 spin_unlock_irqrestore(&tp->indirect_lock, flags);
506 /* usec_wait specifies the wait time in usec when writing to certain registers
507 * where it is unsafe to read back the register without some delay.
508 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
509 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
511 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
513 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
514 /* Non-posted methods */
515 tp->write32(tp, off, val);
518 tg3_write32(tp, off, val);
523 /* Wait again after the read for the posted method to guarantee that
524 * the wait time is met.
530 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
532 tp->write32_mbox(tp, off, val);
533 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
534 tp->read32_mbox(tp, off);
537 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
539 void __iomem *mbox = tp->regs + off;
541 if (tg3_flag(tp, TXD_MBOX_HWBUG))
543 if (tg3_flag(tp, MBOX_WRITE_REORDER))
547 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
549 return readl(tp->regs + off + GRCMBOX_BASE);
552 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
554 writel(val, tp->regs + off + GRCMBOX_BASE);
557 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
558 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
559 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
560 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
561 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
563 #define tw32(reg, val) tp->write32(tp, reg, val)
564 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
565 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
566 #define tr32(reg) tp->read32(tp, reg)
568 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
572 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
573 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
576 spin_lock_irqsave(&tp->indirect_lock, flags);
577 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
578 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
579 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
581 /* Always leave this as zero. */
582 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
584 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
585 tw32_f(TG3PCI_MEM_WIN_DATA, val);
587 /* Always leave this as zero. */
588 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
590 spin_unlock_irqrestore(&tp->indirect_lock, flags);
593 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
598 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
603 spin_lock_irqsave(&tp->indirect_lock, flags);
604 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
605 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
606 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
608 /* Always leave this as zero. */
609 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
611 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
612 *val = tr32(TG3PCI_MEM_WIN_DATA);
614 /* Always leave this as zero. */
615 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
617 spin_unlock_irqrestore(&tp->indirect_lock, flags);
620 static void tg3_ape_lock_init(struct tg3 *tp)
625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
626 regbase = TG3_APE_LOCK_GRANT;
628 regbase = TG3_APE_PER_LOCK_GRANT;
630 /* Make sure the driver hasn't any stale locks. */
631 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
633 case TG3_APE_LOCK_PHY0:
634 case TG3_APE_LOCK_PHY1:
635 case TG3_APE_LOCK_PHY2:
636 case TG3_APE_LOCK_PHY3:
637 bit = APE_LOCK_GRANT_DRIVER;
641 bit = APE_LOCK_GRANT_DRIVER;
643 bit = 1 << tp->pci_fn;
645 tg3_ape_write32(tp, regbase + 4 * i, bit);
650 static int tg3_ape_lock(struct tg3 *tp, int locknum)
654 u32 status, req, gnt, bit;
656 if (!tg3_flag(tp, ENABLE_APE))
660 case TG3_APE_LOCK_GPIO:
661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
663 case TG3_APE_LOCK_GRC:
664 case TG3_APE_LOCK_MEM:
666 bit = APE_LOCK_REQ_DRIVER;
668 bit = 1 << tp->pci_fn;
674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
675 req = TG3_APE_LOCK_REQ;
676 gnt = TG3_APE_LOCK_GRANT;
678 req = TG3_APE_PER_LOCK_REQ;
679 gnt = TG3_APE_PER_LOCK_GRANT;
684 tg3_ape_write32(tp, req + off, bit);
686 /* Wait for up to 1 millisecond to acquire lock. */
687 for (i = 0; i < 100; i++) {
688 status = tg3_ape_read32(tp, gnt + off);
695 /* Revoke the lock request. */
696 tg3_ape_write32(tp, gnt + off, bit);
703 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
707 if (!tg3_flag(tp, ENABLE_APE))
711 case TG3_APE_LOCK_GPIO:
712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
714 case TG3_APE_LOCK_GRC:
715 case TG3_APE_LOCK_MEM:
717 bit = APE_LOCK_GRANT_DRIVER;
719 bit = 1 << tp->pci_fn;
725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
726 gnt = TG3_APE_LOCK_GRANT;
728 gnt = TG3_APE_PER_LOCK_GRANT;
730 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
733 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
738 /* NCSI does not support APE events */
739 if (tg3_flag(tp, APE_HAS_NCSI))
742 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
743 if (apedata != APE_SEG_SIG_MAGIC)
746 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
747 if (!(apedata & APE_FW_STATUS_READY))
750 /* Wait for up to 1 millisecond for APE to service previous event. */
751 for (i = 0; i < 10; i++) {
752 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
755 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
757 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
758 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
759 event | APE_EVENT_STATUS_EVENT_PENDING);
761 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
763 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
769 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
770 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
773 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
778 if (!tg3_flag(tp, ENABLE_APE))
782 case RESET_KIND_INIT:
783 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
784 APE_HOST_SEG_SIG_MAGIC);
785 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
786 APE_HOST_SEG_LEN_MAGIC);
787 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
788 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
789 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
790 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
791 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
792 APE_HOST_BEHAV_NO_PHYLOCK);
793 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
794 TG3_APE_HOST_DRVR_STATE_START);
796 event = APE_EVENT_STATUS_STATE_START;
798 case RESET_KIND_SHUTDOWN:
799 /* With the interface we are currently using,
800 * APE does not track driver state. Wiping
801 * out the HOST SEGMENT SIGNATURE forces
802 * the APE to assume OS absent status.
804 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
806 if (device_may_wakeup(&tp->pdev->dev) &&
807 tg3_flag(tp, WOL_ENABLE)) {
808 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
809 TG3_APE_HOST_WOL_SPEED_AUTO);
810 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
812 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
814 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
816 event = APE_EVENT_STATUS_STATE_UNLOAD;
818 case RESET_KIND_SUSPEND:
819 event = APE_EVENT_STATUS_STATE_SUSPEND;
825 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
827 tg3_ape_send_event(tp, event);
830 static void tg3_disable_ints(struct tg3 *tp)
834 tw32(TG3PCI_MISC_HOST_CTRL,
835 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
836 for (i = 0; i < tp->irq_max; i++)
837 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
840 static void tg3_enable_ints(struct tg3 *tp)
847 tw32(TG3PCI_MISC_HOST_CTRL,
848 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
850 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
851 for (i = 0; i < tp->irq_cnt; i++) {
852 struct tg3_napi *tnapi = &tp->napi[i];
854 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
855 if (tg3_flag(tp, 1SHOT_MSI))
856 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
858 tp->coal_now |= tnapi->coal_now;
861 /* Force an initial interrupt */
862 if (!tg3_flag(tp, TAGGED_STATUS) &&
863 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
864 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
866 tw32(HOSTCC_MODE, tp->coal_now);
868 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
871 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
873 struct tg3 *tp = tnapi->tp;
874 struct tg3_hw_status *sblk = tnapi->hw_status;
875 unsigned int work_exists = 0;
877 /* check for phy events */
878 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
879 if (sblk->status & SD_STATUS_LINK_CHG)
882 /* check for RX/TX work to do */
883 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
884 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
891 * similar to tg3_enable_ints, but it accurately determines whether there
892 * is new work pending and can return without flushing the PIO write
893 * which reenables interrupts
895 static void tg3_int_reenable(struct tg3_napi *tnapi)
897 struct tg3 *tp = tnapi->tp;
899 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
902 /* When doing tagged status, this work check is unnecessary.
903 * The last_tag we write above tells the chip which piece of
904 * work we've completed.
906 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
907 tw32(HOSTCC_MODE, tp->coalesce_mode |
908 HOSTCC_MODE_ENABLE | tnapi->coal_now);
911 static void tg3_switch_clocks(struct tg3 *tp)
916 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
919 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
921 orig_clock_ctrl = clock_ctrl;
922 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
923 CLOCK_CTRL_CLKRUN_OENABLE |
925 tp->pci_clock_ctrl = clock_ctrl;
927 if (tg3_flag(tp, 5705_PLUS)) {
928 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
929 tw32_wait_f(TG3PCI_CLOCK_CTRL,
930 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
932 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
933 tw32_wait_f(TG3PCI_CLOCK_CTRL,
935 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
937 tw32_wait_f(TG3PCI_CLOCK_CTRL,
938 clock_ctrl | (CLOCK_CTRL_ALTCLK),
941 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
944 #define PHY_BUSY_LOOPS 5000
946 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
952 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
954 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
960 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
961 MI_COM_PHY_ADDR_MASK);
962 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
963 MI_COM_REG_ADDR_MASK);
964 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
966 tw32_f(MAC_MI_COM, frame_val);
968 loops = PHY_BUSY_LOOPS;
971 frame_val = tr32(MAC_MI_COM);
973 if ((frame_val & MI_COM_BUSY) == 0) {
975 frame_val = tr32(MAC_MI_COM);
983 *val = frame_val & MI_COM_DATA_MASK;
987 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
988 tw32_f(MAC_MI_MODE, tp->mi_mode);
995 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1001 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1002 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1005 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1007 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1011 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1012 MI_COM_PHY_ADDR_MASK);
1013 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1014 MI_COM_REG_ADDR_MASK);
1015 frame_val |= (val & MI_COM_DATA_MASK);
1016 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1018 tw32_f(MAC_MI_COM, frame_val);
1020 loops = PHY_BUSY_LOOPS;
1021 while (loops != 0) {
1023 frame_val = tr32(MAC_MI_COM);
1024 if ((frame_val & MI_COM_BUSY) == 0) {
1026 frame_val = tr32(MAC_MI_COM);
1036 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1037 tw32_f(MAC_MI_MODE, tp->mi_mode);
1044 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1048 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1052 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1056 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1057 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1061 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1067 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1071 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1075 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1079 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1080 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1084 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1090 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1094 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1096 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1101 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1105 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1107 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1112 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1116 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1117 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1118 MII_TG3_AUXCTL_SHDWSEL_MISC);
1120 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1125 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1127 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1128 set |= MII_TG3_AUXCTL_MISC_WREN;
1130 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1133 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1134 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1135 MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1136 MII_TG3_AUXCTL_ACTL_TX_6DB)
1138 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1139 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1140 MII_TG3_AUXCTL_ACTL_TX_6DB);
1142 static int tg3_bmcr_reset(struct tg3 *tp)
1147 /* OK, reset it, and poll the BMCR_RESET bit until it
1148 * clears or we time out.
1150 phy_control = BMCR_RESET;
1151 err = tg3_writephy(tp, MII_BMCR, phy_control);
1157 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1161 if ((phy_control & BMCR_RESET) == 0) {
1173 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1175 struct tg3 *tp = bp->priv;
1178 spin_lock_bh(&tp->lock);
1180 if (tg3_readphy(tp, reg, &val))
1183 spin_unlock_bh(&tp->lock);
1188 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1190 struct tg3 *tp = bp->priv;
1193 spin_lock_bh(&tp->lock);
1195 if (tg3_writephy(tp, reg, val))
1198 spin_unlock_bh(&tp->lock);
1203 static int tg3_mdio_reset(struct mii_bus *bp)
1208 static void tg3_mdio_config_5785(struct tg3 *tp)
1211 struct phy_device *phydev;
1213 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1214 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1215 case PHY_ID_BCM50610:
1216 case PHY_ID_BCM50610M:
1217 val = MAC_PHYCFG2_50610_LED_MODES;
1219 case PHY_ID_BCMAC131:
1220 val = MAC_PHYCFG2_AC131_LED_MODES;
1222 case PHY_ID_RTL8211C:
1223 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1225 case PHY_ID_RTL8201E:
1226 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1232 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1233 tw32(MAC_PHYCFG2, val);
1235 val = tr32(MAC_PHYCFG1);
1236 val &= ~(MAC_PHYCFG1_RGMII_INT |
1237 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1238 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1239 tw32(MAC_PHYCFG1, val);
1244 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1245 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1246 MAC_PHYCFG2_FMODE_MASK_MASK |
1247 MAC_PHYCFG2_GMODE_MASK_MASK |
1248 MAC_PHYCFG2_ACT_MASK_MASK |
1249 MAC_PHYCFG2_QUAL_MASK_MASK |
1250 MAC_PHYCFG2_INBAND_ENABLE;
1252 tw32(MAC_PHYCFG2, val);
1254 val = tr32(MAC_PHYCFG1);
1255 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1256 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1257 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1258 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1259 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1260 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1261 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1263 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1264 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1265 tw32(MAC_PHYCFG1, val);
1267 val = tr32(MAC_EXT_RGMII_MODE);
1268 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1269 MAC_RGMII_MODE_RX_QUALITY |
1270 MAC_RGMII_MODE_RX_ACTIVITY |
1271 MAC_RGMII_MODE_RX_ENG_DET |
1272 MAC_RGMII_MODE_TX_ENABLE |
1273 MAC_RGMII_MODE_TX_LOWPWR |
1274 MAC_RGMII_MODE_TX_RESET);
1275 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1276 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1277 val |= MAC_RGMII_MODE_RX_INT_B |
1278 MAC_RGMII_MODE_RX_QUALITY |
1279 MAC_RGMII_MODE_RX_ACTIVITY |
1280 MAC_RGMII_MODE_RX_ENG_DET;
1281 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1282 val |= MAC_RGMII_MODE_TX_ENABLE |
1283 MAC_RGMII_MODE_TX_LOWPWR |
1284 MAC_RGMII_MODE_TX_RESET;
1286 tw32(MAC_EXT_RGMII_MODE, val);
1289 static void tg3_mdio_start(struct tg3 *tp)
1291 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1292 tw32_f(MAC_MI_MODE, tp->mi_mode);
1295 if (tg3_flag(tp, MDIOBUS_INITED) &&
1296 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1297 tg3_mdio_config_5785(tp);
1300 static int tg3_mdio_init(struct tg3 *tp)
1304 struct phy_device *phydev;
1306 if (tg3_flag(tp, 5717_PLUS)) {
1309 tp->phy_addr = tp->pci_fn + 1;
1311 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1312 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1314 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1315 TG3_CPMU_PHY_STRAP_IS_SERDES;
1319 tp->phy_addr = TG3_PHY_MII_ADDR;
1323 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1326 tp->mdio_bus = mdiobus_alloc();
1327 if (tp->mdio_bus == NULL)
1330 tp->mdio_bus->name = "tg3 mdio bus";
1331 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1332 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1333 tp->mdio_bus->priv = tp;
1334 tp->mdio_bus->parent = &tp->pdev->dev;
1335 tp->mdio_bus->read = &tg3_mdio_read;
1336 tp->mdio_bus->write = &tg3_mdio_write;
1337 tp->mdio_bus->reset = &tg3_mdio_reset;
1338 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1339 tp->mdio_bus->irq = &tp->mdio_irq[0];
1341 for (i = 0; i < PHY_MAX_ADDR; i++)
1342 tp->mdio_bus->irq[i] = PHY_POLL;
1344 /* The bus registration will look for all the PHYs on the mdio bus.
1345 * Unfortunately, it does not ensure the PHY is powered up before
1346 * accessing the PHY ID registers. A chip reset is the
1347 * quickest way to bring the device back to an operational state..
1349 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1352 i = mdiobus_register(tp->mdio_bus);
1354 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1355 mdiobus_free(tp->mdio_bus);
1359 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1361 if (!phydev || !phydev->drv) {
1362 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1363 mdiobus_unregister(tp->mdio_bus);
1364 mdiobus_free(tp->mdio_bus);
1368 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1369 case PHY_ID_BCM57780:
1370 phydev->interface = PHY_INTERFACE_MODE_GMII;
1371 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1373 case PHY_ID_BCM50610:
1374 case PHY_ID_BCM50610M:
1375 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1376 PHY_BRCM_RX_REFCLK_UNUSED |
1377 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1378 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1379 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1380 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1381 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1382 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1383 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1384 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1386 case PHY_ID_RTL8211C:
1387 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1389 case PHY_ID_RTL8201E:
1390 case PHY_ID_BCMAC131:
1391 phydev->interface = PHY_INTERFACE_MODE_MII;
1392 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1393 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1397 tg3_flag_set(tp, MDIOBUS_INITED);
1399 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1400 tg3_mdio_config_5785(tp);
1405 static void tg3_mdio_fini(struct tg3 *tp)
1407 if (tg3_flag(tp, MDIOBUS_INITED)) {
1408 tg3_flag_clear(tp, MDIOBUS_INITED);
1409 mdiobus_unregister(tp->mdio_bus);
1410 mdiobus_free(tp->mdio_bus);
1414 /* tp->lock is held. */
1415 static inline void tg3_generate_fw_event(struct tg3 *tp)
1419 val = tr32(GRC_RX_CPU_EVENT);
1420 val |= GRC_RX_CPU_DRIVER_EVENT;
1421 tw32_f(GRC_RX_CPU_EVENT, val);
1423 tp->last_event_jiffies = jiffies;
1426 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1428 /* tp->lock is held. */
1429 static void tg3_wait_for_event_ack(struct tg3 *tp)
1432 unsigned int delay_cnt;
1435 /* If enough time has passed, no wait is necessary. */
1436 time_remain = (long)(tp->last_event_jiffies + 1 +
1437 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1439 if (time_remain < 0)
1442 /* Check if we can shorten the wait time. */
1443 delay_cnt = jiffies_to_usecs(time_remain);
1444 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1445 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1446 delay_cnt = (delay_cnt >> 3) + 1;
1448 for (i = 0; i < delay_cnt; i++) {
1449 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1455 /* tp->lock is held. */
1456 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1461 if (!tg3_readphy(tp, MII_BMCR, ®))
1463 if (!tg3_readphy(tp, MII_BMSR, ®))
1464 val |= (reg & 0xffff);
1468 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1470 if (!tg3_readphy(tp, MII_LPA, ®))
1471 val |= (reg & 0xffff);
1475 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1476 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1478 if (!tg3_readphy(tp, MII_STAT1000, ®))
1479 val |= (reg & 0xffff);
1483 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1490 /* tp->lock is held. */
1491 static void tg3_ump_link_report(struct tg3 *tp)
1495 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1498 tg3_phy_gather_ump_data(tp, data);
1500 tg3_wait_for_event_ack(tp);
1502 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1503 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1504 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1505 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1506 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1507 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1509 tg3_generate_fw_event(tp);
1512 /* tp->lock is held. */
1513 static void tg3_stop_fw(struct tg3 *tp)
1515 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1516 /* Wait for RX cpu to ACK the previous event. */
1517 tg3_wait_for_event_ack(tp);
1519 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1521 tg3_generate_fw_event(tp);
1523 /* Wait for RX cpu to ACK this event. */
1524 tg3_wait_for_event_ack(tp);
1528 /* tp->lock is held. */
1529 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1531 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1532 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1534 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1536 case RESET_KIND_INIT:
1537 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1541 case RESET_KIND_SHUTDOWN:
1542 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1546 case RESET_KIND_SUSPEND:
1547 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1556 if (kind == RESET_KIND_INIT ||
1557 kind == RESET_KIND_SUSPEND)
1558 tg3_ape_driver_state_change(tp, kind);
1561 /* tp->lock is held. */
1562 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1564 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1566 case RESET_KIND_INIT:
1567 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1568 DRV_STATE_START_DONE);
1571 case RESET_KIND_SHUTDOWN:
1572 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1573 DRV_STATE_UNLOAD_DONE);
1581 if (kind == RESET_KIND_SHUTDOWN)
1582 tg3_ape_driver_state_change(tp, kind);
1585 /* tp->lock is held. */
1586 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1588 if (tg3_flag(tp, ENABLE_ASF)) {
1590 case RESET_KIND_INIT:
1591 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1595 case RESET_KIND_SHUTDOWN:
1596 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1600 case RESET_KIND_SUSPEND:
1601 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1611 static int tg3_poll_fw(struct tg3 *tp)
1616 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1617 /* Wait up to 20ms for init done. */
1618 for (i = 0; i < 200; i++) {
1619 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1626 /* Wait for firmware initialization to complete. */
1627 for (i = 0; i < 100000; i++) {
1628 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1629 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1634 /* Chip might not be fitted with firmware. Some Sun onboard
1635 * parts are configured like that. So don't signal the timeout
1636 * of the above loop as an error, but do report the lack of
1637 * running firmware once.
1639 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1640 tg3_flag_set(tp, NO_FWARE_REPORTED);
1642 netdev_info(tp->dev, "No firmware running\n");
1645 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1646 /* The 57765 A0 needs a little more
1647 * time to do some important work.
1655 static void tg3_link_report(struct tg3 *tp)
1657 if (!netif_carrier_ok(tp->dev)) {
1658 netif_info(tp, link, tp->dev, "Link is down\n");
1659 tg3_ump_link_report(tp);
1660 } else if (netif_msg_link(tp)) {
1661 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1662 (tp->link_config.active_speed == SPEED_1000 ?
1664 (tp->link_config.active_speed == SPEED_100 ?
1666 (tp->link_config.active_duplex == DUPLEX_FULL ?
1669 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1670 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1672 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1675 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1676 netdev_info(tp->dev, "EEE is %s\n",
1677 tp->setlpicnt ? "enabled" : "disabled");
1679 tg3_ump_link_report(tp);
1683 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1687 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1688 miireg = ADVERTISE_1000XPAUSE;
1689 else if (flow_ctrl & FLOW_CTRL_TX)
1690 miireg = ADVERTISE_1000XPSE_ASYM;
1691 else if (flow_ctrl & FLOW_CTRL_RX)
1692 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1699 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1703 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1704 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1705 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1706 if (lcladv & ADVERTISE_1000XPAUSE)
1708 if (rmtadv & ADVERTISE_1000XPAUSE)
1715 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1719 u32 old_rx_mode = tp->rx_mode;
1720 u32 old_tx_mode = tp->tx_mode;
1722 if (tg3_flag(tp, USE_PHYLIB))
1723 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1725 autoneg = tp->link_config.autoneg;
1727 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1728 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1729 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1731 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1733 flowctrl = tp->link_config.flowctrl;
1735 tp->link_config.active_flowctrl = flowctrl;
1737 if (flowctrl & FLOW_CTRL_RX)
1738 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1740 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1742 if (old_rx_mode != tp->rx_mode)
1743 tw32_f(MAC_RX_MODE, tp->rx_mode);
1745 if (flowctrl & FLOW_CTRL_TX)
1746 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1748 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1750 if (old_tx_mode != tp->tx_mode)
1751 tw32_f(MAC_TX_MODE, tp->tx_mode);
1754 static void tg3_adjust_link(struct net_device *dev)
1756 u8 oldflowctrl, linkmesg = 0;
1757 u32 mac_mode, lcl_adv, rmt_adv;
1758 struct tg3 *tp = netdev_priv(dev);
1759 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1761 spin_lock_bh(&tp->lock);
1763 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1764 MAC_MODE_HALF_DUPLEX);
1766 oldflowctrl = tp->link_config.active_flowctrl;
1772 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1773 mac_mode |= MAC_MODE_PORT_MODE_MII;
1774 else if (phydev->speed == SPEED_1000 ||
1775 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1776 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1778 mac_mode |= MAC_MODE_PORT_MODE_MII;
1780 if (phydev->duplex == DUPLEX_HALF)
1781 mac_mode |= MAC_MODE_HALF_DUPLEX;
1783 lcl_adv = mii_advertise_flowctrl(
1784 tp->link_config.flowctrl);
1787 rmt_adv = LPA_PAUSE_CAP;
1788 if (phydev->asym_pause)
1789 rmt_adv |= LPA_PAUSE_ASYM;
1792 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1794 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1796 if (mac_mode != tp->mac_mode) {
1797 tp->mac_mode = mac_mode;
1798 tw32_f(MAC_MODE, tp->mac_mode);
1802 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1803 if (phydev->speed == SPEED_10)
1805 MAC_MI_STAT_10MBPS_MODE |
1806 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1808 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1811 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1812 tw32(MAC_TX_LENGTHS,
1813 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1814 (6 << TX_LENGTHS_IPG_SHIFT) |
1815 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1817 tw32(MAC_TX_LENGTHS,
1818 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1819 (6 << TX_LENGTHS_IPG_SHIFT) |
1820 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1822 if (phydev->link != tp->old_link ||
1823 phydev->speed != tp->link_config.active_speed ||
1824 phydev->duplex != tp->link_config.active_duplex ||
1825 oldflowctrl != tp->link_config.active_flowctrl)
1828 tp->old_link = phydev->link;
1829 tp->link_config.active_speed = phydev->speed;
1830 tp->link_config.active_duplex = phydev->duplex;
1832 spin_unlock_bh(&tp->lock);
1835 tg3_link_report(tp);
1838 static int tg3_phy_init(struct tg3 *tp)
1840 struct phy_device *phydev;
1842 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1845 /* Bring the PHY back to a known state. */
1848 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1850 /* Attach the MAC to the PHY. */
1851 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1852 phydev->dev_flags, phydev->interface);
1853 if (IS_ERR(phydev)) {
1854 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1855 return PTR_ERR(phydev);
1858 /* Mask with MAC supported features. */
1859 switch (phydev->interface) {
1860 case PHY_INTERFACE_MODE_GMII:
1861 case PHY_INTERFACE_MODE_RGMII:
1862 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1863 phydev->supported &= (PHY_GBIT_FEATURES |
1865 SUPPORTED_Asym_Pause);
1869 case PHY_INTERFACE_MODE_MII:
1870 phydev->supported &= (PHY_BASIC_FEATURES |
1872 SUPPORTED_Asym_Pause);
1875 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1879 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1881 phydev->advertising = phydev->supported;
1886 static void tg3_phy_start(struct tg3 *tp)
1888 struct phy_device *phydev;
1890 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1893 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1895 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1896 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1897 phydev->speed = tp->link_config.speed;
1898 phydev->duplex = tp->link_config.duplex;
1899 phydev->autoneg = tp->link_config.autoneg;
1900 phydev->advertising = tp->link_config.advertising;
1905 phy_start_aneg(phydev);
1908 static void tg3_phy_stop(struct tg3 *tp)
1910 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1913 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1916 static void tg3_phy_fini(struct tg3 *tp)
1918 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1919 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1920 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1924 static int tg3_phy_set_extloopbk(struct tg3 *tp)
1929 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
1932 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1933 /* Cannot do read-modify-write on 5401 */
1934 err = tg3_phy_auxctl_write(tp,
1935 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1936 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
1941 err = tg3_phy_auxctl_read(tp,
1942 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1946 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
1947 err = tg3_phy_auxctl_write(tp,
1948 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
1954 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1958 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1961 tg3_writephy(tp, MII_TG3_FET_TEST,
1962 phytest | MII_TG3_FET_SHADOW_EN);
1963 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1965 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1967 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1968 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1970 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1974 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1978 if (!tg3_flag(tp, 5705_PLUS) ||
1979 (tg3_flag(tp, 5717_PLUS) &&
1980 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1983 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1984 tg3_phy_fet_toggle_apd(tp, enable);
1988 reg = MII_TG3_MISC_SHDW_WREN |
1989 MII_TG3_MISC_SHDW_SCR5_SEL |
1990 MII_TG3_MISC_SHDW_SCR5_LPED |
1991 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1992 MII_TG3_MISC_SHDW_SCR5_SDTL |
1993 MII_TG3_MISC_SHDW_SCR5_C125OE;
1994 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1995 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1997 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2000 reg = MII_TG3_MISC_SHDW_WREN |
2001 MII_TG3_MISC_SHDW_APD_SEL |
2002 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2004 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2006 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2009 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2013 if (!tg3_flag(tp, 5705_PLUS) ||
2014 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2017 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2020 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2021 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2023 tg3_writephy(tp, MII_TG3_FET_TEST,
2024 ephy | MII_TG3_FET_SHADOW_EN);
2025 if (!tg3_readphy(tp, reg, &phy)) {
2027 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2029 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2030 tg3_writephy(tp, reg, phy);
2032 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2037 ret = tg3_phy_auxctl_read(tp,
2038 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2041 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2043 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2044 tg3_phy_auxctl_write(tp,
2045 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2050 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2055 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2058 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2060 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2061 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2064 static void tg3_phy_apply_otp(struct tg3 *tp)
2073 if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
2076 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2077 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2078 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2080 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2081 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2082 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2084 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2085 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2086 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2088 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2089 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2091 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2092 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2094 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2095 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2096 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2098 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2101 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2105 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2110 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2111 current_link_up == 1 &&
2112 tp->link_config.active_duplex == DUPLEX_FULL &&
2113 (tp->link_config.active_speed == SPEED_100 ||
2114 tp->link_config.active_speed == SPEED_1000)) {
2117 if (tp->link_config.active_speed == SPEED_1000)
2118 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2120 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2122 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2124 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2125 TG3_CL45_D7_EEERES_STAT, &val);
2127 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2128 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2132 if (!tp->setlpicnt) {
2133 if (current_link_up == 1 &&
2134 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2135 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2136 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2139 val = tr32(TG3_CPMU_EEE_MODE);
2140 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2144 static void tg3_phy_eee_enable(struct tg3 *tp)
2148 if (tp->link_config.active_speed == SPEED_1000 &&
2149 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2150 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2151 tg3_flag(tp, 57765_CLASS)) &&
2152 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2153 val = MII_TG3_DSP_TAP26_ALNOKO |
2154 MII_TG3_DSP_TAP26_RMRXSTO;
2155 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2156 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2159 val = tr32(TG3_CPMU_EEE_MODE);
2160 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2163 static int tg3_wait_macro_done(struct tg3 *tp)
2170 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2171 if ((tmp32 & 0x1000) == 0)
2181 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2183 static const u32 test_pat[4][6] = {
2184 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2185 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2186 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2187 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2191 for (chan = 0; chan < 4; chan++) {
2194 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2195 (chan * 0x2000) | 0x0200);
2196 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2198 for (i = 0; i < 6; i++)
2199 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2202 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2203 if (tg3_wait_macro_done(tp)) {
2208 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2209 (chan * 0x2000) | 0x0200);
2210 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2211 if (tg3_wait_macro_done(tp)) {
2216 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2217 if (tg3_wait_macro_done(tp)) {
2222 for (i = 0; i < 6; i += 2) {
2225 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2226 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2227 tg3_wait_macro_done(tp)) {
2233 if (low != test_pat[chan][i] ||
2234 high != test_pat[chan][i+1]) {
2235 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2236 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2237 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2247 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2251 for (chan = 0; chan < 4; chan++) {
2254 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2255 (chan * 0x2000) | 0x0200);
2256 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2257 for (i = 0; i < 6; i++)
2258 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2259 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2260 if (tg3_wait_macro_done(tp))
2267 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2269 u32 reg32, phy9_orig;
2270 int retries, do_phy_reset, err;
2276 err = tg3_bmcr_reset(tp);
2282 /* Disable transmitter and interrupt. */
2283 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2287 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2289 /* Set full-duplex, 1000 mbps. */
2290 tg3_writephy(tp, MII_BMCR,
2291 BMCR_FULLDPLX | BMCR_SPEED1000);
2293 /* Set to master mode. */
2294 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2297 tg3_writephy(tp, MII_CTRL1000,
2298 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2300 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2304 /* Block the PHY control access. */
2305 tg3_phydsp_write(tp, 0x8005, 0x0800);
2307 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2310 } while (--retries);
2312 err = tg3_phy_reset_chanpat(tp);
2316 tg3_phydsp_write(tp, 0x8005, 0x0000);
2318 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2319 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2321 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2323 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2325 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2327 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2334 /* This will reset the tigon3 PHY if there is no valid
2335 * link unless the FORCE argument is non-zero.
2337 static int tg3_phy_reset(struct tg3 *tp)
2342 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2343 val = tr32(GRC_MISC_CFG);
2344 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2347 err = tg3_readphy(tp, MII_BMSR, &val);
2348 err |= tg3_readphy(tp, MII_BMSR, &val);
2352 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2353 netif_carrier_off(tp->dev);
2354 tg3_link_report(tp);
2357 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2358 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2359 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2360 err = tg3_phy_reset_5703_4_5(tp);
2367 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2368 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2369 cpmuctrl = tr32(TG3_CPMU_CTRL);
2370 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2372 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2375 err = tg3_bmcr_reset(tp);
2379 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2380 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2381 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2383 tw32(TG3_CPMU_CTRL, cpmuctrl);
2386 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2387 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2388 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2389 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2390 CPMU_LSPD_1000MB_MACCLK_12_5) {
2391 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2393 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2397 if (tg3_flag(tp, 5717_PLUS) &&
2398 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2401 tg3_phy_apply_otp(tp);
2403 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2404 tg3_phy_toggle_apd(tp, true);
2406 tg3_phy_toggle_apd(tp, false);
2409 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2410 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2411 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2412 tg3_phydsp_write(tp, 0x000a, 0x0323);
2413 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2416 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2417 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2418 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2421 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2422 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2423 tg3_phydsp_write(tp, 0x000a, 0x310b);
2424 tg3_phydsp_write(tp, 0x201f, 0x9506);
2425 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2426 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2428 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2429 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2430 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2431 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2432 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2433 tg3_writephy(tp, MII_TG3_TEST1,
2434 MII_TG3_TEST1_TRIM_EN | 0x4);
2436 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2438 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2442 /* Set Extended packet length bit (bit 14) on all chips that */
2443 /* support jumbo frames */
2444 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2445 /* Cannot do read-modify-write on 5401 */
2446 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2447 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2448 /* Set bit 14 with read-modify-write to preserve other bits */
2449 err = tg3_phy_auxctl_read(tp,
2450 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2452 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2453 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2456 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2457 * jumbo frames transmission.
2459 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2460 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2461 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2462 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2465 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2466 /* adjust output voltage */
2467 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2470 tg3_phy_toggle_automdix(tp, 1);
2471 tg3_phy_set_wirespeed(tp);
2475 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2476 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2477 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2478 TG3_GPIO_MSG_NEED_VAUX)
2479 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2480 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2481 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2482 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2483 (TG3_GPIO_MSG_DRVR_PRES << 12))
2485 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2486 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2487 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2488 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2489 (TG3_GPIO_MSG_NEED_VAUX << 12))
2491 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2495 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2496 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2497 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2499 status = tr32(TG3_CPMU_DRV_STATUS);
2501 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2502 status &= ~(TG3_GPIO_MSG_MASK << shift);
2503 status |= (newstat << shift);
2505 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2506 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2507 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2509 tw32(TG3_CPMU_DRV_STATUS, status);
2511 return status >> TG3_APE_GPIO_MSG_SHIFT;
2514 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2516 if (!tg3_flag(tp, IS_NIC))
2519 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2520 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2521 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2522 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2525 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2527 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2528 TG3_GRC_LCLCTL_PWRSW_DELAY);
2530 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2532 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2533 TG3_GRC_LCLCTL_PWRSW_DELAY);
2539 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2543 if (!tg3_flag(tp, IS_NIC) ||
2544 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2545 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2548 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2550 tw32_wait_f(GRC_LOCAL_CTRL,
2551 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2552 TG3_GRC_LCLCTL_PWRSW_DELAY);
2554 tw32_wait_f(GRC_LOCAL_CTRL,
2556 TG3_GRC_LCLCTL_PWRSW_DELAY);
2558 tw32_wait_f(GRC_LOCAL_CTRL,
2559 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2560 TG3_GRC_LCLCTL_PWRSW_DELAY);
2563 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2565 if (!tg3_flag(tp, IS_NIC))
2568 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2569 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2570 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2571 (GRC_LCLCTRL_GPIO_OE0 |
2572 GRC_LCLCTRL_GPIO_OE1 |
2573 GRC_LCLCTRL_GPIO_OE2 |
2574 GRC_LCLCTRL_GPIO_OUTPUT0 |
2575 GRC_LCLCTRL_GPIO_OUTPUT1),
2576 TG3_GRC_LCLCTL_PWRSW_DELAY);
2577 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2578 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2579 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2580 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2581 GRC_LCLCTRL_GPIO_OE1 |
2582 GRC_LCLCTRL_GPIO_OE2 |
2583 GRC_LCLCTRL_GPIO_OUTPUT0 |
2584 GRC_LCLCTRL_GPIO_OUTPUT1 |
2586 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2587 TG3_GRC_LCLCTL_PWRSW_DELAY);
2589 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2590 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2591 TG3_GRC_LCLCTL_PWRSW_DELAY);
2593 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2594 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2595 TG3_GRC_LCLCTL_PWRSW_DELAY);
2598 u32 grc_local_ctrl = 0;
2600 /* Workaround to prevent overdrawing Amps. */
2601 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2602 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2603 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2605 TG3_GRC_LCLCTL_PWRSW_DELAY);
2608 /* On 5753 and variants, GPIO2 cannot be used. */
2609 no_gpio2 = tp->nic_sram_data_cfg &
2610 NIC_SRAM_DATA_CFG_NO_GPIO2;
2612 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2613 GRC_LCLCTRL_GPIO_OE1 |
2614 GRC_LCLCTRL_GPIO_OE2 |
2615 GRC_LCLCTRL_GPIO_OUTPUT1 |
2616 GRC_LCLCTRL_GPIO_OUTPUT2;
2618 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2619 GRC_LCLCTRL_GPIO_OUTPUT2);
2621 tw32_wait_f(GRC_LOCAL_CTRL,
2622 tp->grc_local_ctrl | grc_local_ctrl,
2623 TG3_GRC_LCLCTL_PWRSW_DELAY);
2625 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2627 tw32_wait_f(GRC_LOCAL_CTRL,
2628 tp->grc_local_ctrl | grc_local_ctrl,
2629 TG3_GRC_LCLCTL_PWRSW_DELAY);
2632 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2633 tw32_wait_f(GRC_LOCAL_CTRL,
2634 tp->grc_local_ctrl | grc_local_ctrl,
2635 TG3_GRC_LCLCTL_PWRSW_DELAY);
2640 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2644 /* Serialize power state transitions */
2645 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2648 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2649 msg = TG3_GPIO_MSG_NEED_VAUX;
2651 msg = tg3_set_function_status(tp, msg);
2653 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2656 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2657 tg3_pwrsrc_switch_to_vaux(tp);
2659 tg3_pwrsrc_die_with_vmain(tp);
2662 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2665 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2667 bool need_vaux = false;
2669 /* The GPIOs do something completely different on 57765. */
2670 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2673 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2674 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2675 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2676 tg3_frob_aux_power_5717(tp, include_wol ?
2677 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2681 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2682 struct net_device *dev_peer;
2684 dev_peer = pci_get_drvdata(tp->pdev_peer);
2686 /* remove_one() may have been run on the peer. */
2688 struct tg3 *tp_peer = netdev_priv(dev_peer);
2690 if (tg3_flag(tp_peer, INIT_COMPLETE))
2693 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2694 tg3_flag(tp_peer, ENABLE_ASF))
2699 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2700 tg3_flag(tp, ENABLE_ASF))
2704 tg3_pwrsrc_switch_to_vaux(tp);
2706 tg3_pwrsrc_die_with_vmain(tp);
2709 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2711 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2713 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2714 if (speed != SPEED_10)
2716 } else if (speed == SPEED_10)
2722 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2726 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2727 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2728 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2729 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2732 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2733 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2734 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2739 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2741 val = tr32(GRC_MISC_CFG);
2742 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2745 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2747 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2750 tg3_writephy(tp, MII_ADVERTISE, 0);
2751 tg3_writephy(tp, MII_BMCR,
2752 BMCR_ANENABLE | BMCR_ANRESTART);
2754 tg3_writephy(tp, MII_TG3_FET_TEST,
2755 phytest | MII_TG3_FET_SHADOW_EN);
2756 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2757 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2759 MII_TG3_FET_SHDW_AUXMODE4,
2762 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2765 } else if (do_low_power) {
2766 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2767 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2769 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2770 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2771 MII_TG3_AUXCTL_PCTL_VREG_11V;
2772 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2775 /* The PHY should not be powered down on some chips because
2778 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2779 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2780 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2781 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
2782 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
2786 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2787 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2788 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2789 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2790 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2791 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2794 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2797 /* tp->lock is held. */
2798 static int tg3_nvram_lock(struct tg3 *tp)
2800 if (tg3_flag(tp, NVRAM)) {
2803 if (tp->nvram_lock_cnt == 0) {
2804 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2805 for (i = 0; i < 8000; i++) {
2806 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2811 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2815 tp->nvram_lock_cnt++;
2820 /* tp->lock is held. */
2821 static void tg3_nvram_unlock(struct tg3 *tp)
2823 if (tg3_flag(tp, NVRAM)) {
2824 if (tp->nvram_lock_cnt > 0)
2825 tp->nvram_lock_cnt--;
2826 if (tp->nvram_lock_cnt == 0)
2827 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2831 /* tp->lock is held. */
2832 static void tg3_enable_nvram_access(struct tg3 *tp)
2834 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2835 u32 nvaccess = tr32(NVRAM_ACCESS);
2837 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2841 /* tp->lock is held. */
2842 static void tg3_disable_nvram_access(struct tg3 *tp)
2844 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2845 u32 nvaccess = tr32(NVRAM_ACCESS);
2847 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2851 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2852 u32 offset, u32 *val)
2857 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2860 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2861 EEPROM_ADDR_DEVID_MASK |
2863 tw32(GRC_EEPROM_ADDR,
2865 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2866 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2867 EEPROM_ADDR_ADDR_MASK) |
2868 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2870 for (i = 0; i < 1000; i++) {
2871 tmp = tr32(GRC_EEPROM_ADDR);
2873 if (tmp & EEPROM_ADDR_COMPLETE)
2877 if (!(tmp & EEPROM_ADDR_COMPLETE))
2880 tmp = tr32(GRC_EEPROM_DATA);
2883 * The data will always be opposite the native endian
2884 * format. Perform a blind byteswap to compensate.
2891 #define NVRAM_CMD_TIMEOUT 10000
2893 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2897 tw32(NVRAM_CMD, nvram_cmd);
2898 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2900 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2906 if (i == NVRAM_CMD_TIMEOUT)
2912 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2914 if (tg3_flag(tp, NVRAM) &&
2915 tg3_flag(tp, NVRAM_BUFFERED) &&
2916 tg3_flag(tp, FLASH) &&
2917 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2918 (tp->nvram_jedecnum == JEDEC_ATMEL))
2920 addr = ((addr / tp->nvram_pagesize) <<
2921 ATMEL_AT45DB0X1B_PAGE_POS) +
2922 (addr % tp->nvram_pagesize);
2927 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2929 if (tg3_flag(tp, NVRAM) &&
2930 tg3_flag(tp, NVRAM_BUFFERED) &&
2931 tg3_flag(tp, FLASH) &&
2932 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2933 (tp->nvram_jedecnum == JEDEC_ATMEL))
2935 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2936 tp->nvram_pagesize) +
2937 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2942 /* NOTE: Data read in from NVRAM is byteswapped according to
2943 * the byteswapping settings for all other register accesses.
2944 * tg3 devices are BE devices, so on a BE machine, the data
2945 * returned will be exactly as it is seen in NVRAM. On a LE
2946 * machine, the 32-bit value will be byteswapped.
2948 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2952 if (!tg3_flag(tp, NVRAM))
2953 return tg3_nvram_read_using_eeprom(tp, offset, val);
2955 offset = tg3_nvram_phys_addr(tp, offset);
2957 if (offset > NVRAM_ADDR_MSK)
2960 ret = tg3_nvram_lock(tp);
2964 tg3_enable_nvram_access(tp);
2966 tw32(NVRAM_ADDR, offset);
2967 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2968 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2971 *val = tr32(NVRAM_RDDATA);
2973 tg3_disable_nvram_access(tp);
2975 tg3_nvram_unlock(tp);
2980 /* Ensures NVRAM data is in bytestream format. */
2981 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2984 int res = tg3_nvram_read(tp, offset, &v);
2986 *val = cpu_to_be32(v);
2990 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
2991 u32 offset, u32 len, u8 *buf)
2996 for (i = 0; i < len; i += 4) {
3002 memcpy(&data, buf + i, 4);
3005 * The SEEPROM interface expects the data to always be opposite
3006 * the native endian format. We accomplish this by reversing
3007 * all the operations that would have been performed on the
3008 * data from a call to tg3_nvram_read_be32().
3010 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3012 val = tr32(GRC_EEPROM_ADDR);
3013 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3015 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3017 tw32(GRC_EEPROM_ADDR, val |
3018 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3019 (addr & EEPROM_ADDR_ADDR_MASK) |
3023 for (j = 0; j < 1000; j++) {
3024 val = tr32(GRC_EEPROM_ADDR);
3026 if (val & EEPROM_ADDR_COMPLETE)
3030 if (!(val & EEPROM_ADDR_COMPLETE)) {
3039 /* offset and length are dword aligned */
3040 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3044 u32 pagesize = tp->nvram_pagesize;
3045 u32 pagemask = pagesize - 1;
3049 tmp = kmalloc(pagesize, GFP_KERNEL);
3055 u32 phy_addr, page_off, size;
3057 phy_addr = offset & ~pagemask;
3059 for (j = 0; j < pagesize; j += 4) {
3060 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3061 (__be32 *) (tmp + j));
3068 page_off = offset & pagemask;
3075 memcpy(tmp + page_off, buf, size);
3077 offset = offset + (pagesize - page_off);
3079 tg3_enable_nvram_access(tp);
3082 * Before we can erase the flash page, we need
3083 * to issue a special "write enable" command.
3085 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3087 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3090 /* Erase the target page */
3091 tw32(NVRAM_ADDR, phy_addr);
3093 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3094 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3096 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3099 /* Issue another write enable to start the write. */
3100 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3102 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3105 for (j = 0; j < pagesize; j += 4) {
3108 data = *((__be32 *) (tmp + j));
3110 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3112 tw32(NVRAM_ADDR, phy_addr + j);
3114 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3118 nvram_cmd |= NVRAM_CMD_FIRST;
3119 else if (j == (pagesize - 4))
3120 nvram_cmd |= NVRAM_CMD_LAST;
3122 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3130 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3131 tg3_nvram_exec_cmd(tp, nvram_cmd);
3138 /* offset and length are dword aligned */
3139 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3144 for (i = 0; i < len; i += 4, offset += 4) {
3145 u32 page_off, phy_addr, nvram_cmd;
3148 memcpy(&data, buf + i, 4);
3149 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3151 page_off = offset % tp->nvram_pagesize;
3153 phy_addr = tg3_nvram_phys_addr(tp, offset);
3155 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3157 if (page_off == 0 || i == 0)
3158 nvram_cmd |= NVRAM_CMD_FIRST;
3159 if (page_off == (tp->nvram_pagesize - 4))
3160 nvram_cmd |= NVRAM_CMD_LAST;
3163 nvram_cmd |= NVRAM_CMD_LAST;
3165 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3166 !tg3_flag(tp, FLASH) ||
3167 !tg3_flag(tp, 57765_PLUS))
3168 tw32(NVRAM_ADDR, phy_addr);
3170 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
3171 !tg3_flag(tp, 5755_PLUS) &&
3172 (tp->nvram_jedecnum == JEDEC_ST) &&
3173 (nvram_cmd & NVRAM_CMD_FIRST)) {
3176 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3177 ret = tg3_nvram_exec_cmd(tp, cmd);
3181 if (!tg3_flag(tp, FLASH)) {
3182 /* We always do complete word writes to eeprom. */
3183 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3186 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3193 /* offset and length are dword aligned */
3194 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3198 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3199 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3200 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3204 if (!tg3_flag(tp, NVRAM)) {
3205 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3209 ret = tg3_nvram_lock(tp);
3213 tg3_enable_nvram_access(tp);
3214 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3215 tw32(NVRAM_WRITE1, 0x406);
3217 grc_mode = tr32(GRC_MODE);
3218 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3220 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3221 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3224 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3228 grc_mode = tr32(GRC_MODE);
3229 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3231 tg3_disable_nvram_access(tp);
3232 tg3_nvram_unlock(tp);
3235 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3236 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3243 #define RX_CPU_SCRATCH_BASE 0x30000
3244 #define RX_CPU_SCRATCH_SIZE 0x04000
3245 #define TX_CPU_SCRATCH_BASE 0x34000
3246 #define TX_CPU_SCRATCH_SIZE 0x04000
3248 /* tp->lock is held. */
3249 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
3253 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3256 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3258 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3261 if (offset == RX_CPU_BASE) {
3262 for (i = 0; i < 10000; i++) {
3263 tw32(offset + CPU_STATE, 0xffffffff);
3264 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3265 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3269 tw32(offset + CPU_STATE, 0xffffffff);
3270 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
3273 for (i = 0; i < 10000; i++) {
3274 tw32(offset + CPU_STATE, 0xffffffff);
3275 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3276 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3282 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3283 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3287 /* Clear firmware's nvram arbitration. */
3288 if (tg3_flag(tp, NVRAM))
3289 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3294 unsigned int fw_base;
3295 unsigned int fw_len;
3296 const __be32 *fw_data;
3299 /* tp->lock is held. */
3300 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3301 u32 cpu_scratch_base, int cpu_scratch_size,
3302 struct fw_info *info)
3304 int err, lock_err, i;
3305 void (*write_op)(struct tg3 *, u32, u32);
3307 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3309 "%s: Trying to load TX cpu firmware which is 5705\n",
3314 if (tg3_flag(tp, 5705_PLUS))
3315 write_op = tg3_write_mem;
3317 write_op = tg3_write_indirect_reg32;
3319 /* It is possible that bootcode is still loading at this point.
3320 * Get the nvram lock first before halting the cpu.
3322 lock_err = tg3_nvram_lock(tp);
3323 err = tg3_halt_cpu(tp, cpu_base);
3325 tg3_nvram_unlock(tp);
3329 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3330 write_op(tp, cpu_scratch_base + i, 0);
3331 tw32(cpu_base + CPU_STATE, 0xffffffff);
3332 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3333 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3334 write_op(tp, (cpu_scratch_base +
3335 (info->fw_base & 0xffff) +
3337 be32_to_cpu(info->fw_data[i]));
3345 /* tp->lock is held. */
3346 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3348 struct fw_info info;
3349 const __be32 *fw_data;
3352 fw_data = (void *)tp->fw->data;
3354 /* Firmware blob starts with version numbers, followed by
3355 start address and length. We are setting complete length.
3356 length = end_address_of_bss - start_address_of_text.
3357 Remainder is the blob to be loaded contiguously
3358 from start address. */
3360 info.fw_base = be32_to_cpu(fw_data[1]);
3361 info.fw_len = tp->fw->size - 12;
3362 info.fw_data = &fw_data[3];
3364 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3365 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3370 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3371 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3376 /* Now startup only the RX cpu. */
3377 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3378 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3380 for (i = 0; i < 5; i++) {
3381 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3383 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3384 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3385 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3389 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3390 "should be %08x\n", __func__,
3391 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3394 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3395 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
3400 /* tp->lock is held. */
3401 static int tg3_load_tso_firmware(struct tg3 *tp)
3403 struct fw_info info;
3404 const __be32 *fw_data;
3405 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3408 if (tg3_flag(tp, HW_TSO_1) ||
3409 tg3_flag(tp, HW_TSO_2) ||
3410 tg3_flag(tp, HW_TSO_3))
3413 fw_data = (void *)tp->fw->data;
3415 /* Firmware blob starts with version numbers, followed by
3416 start address and length. We are setting complete length.
3417 length = end_address_of_bss - start_address_of_text.
3418 Remainder is the blob to be loaded contiguously
3419 from start address. */
3421 info.fw_base = be32_to_cpu(fw_data[1]);
3422 cpu_scratch_size = tp->fw_len;
3423 info.fw_len = tp->fw->size - 12;
3424 info.fw_data = &fw_data[3];
3426 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3427 cpu_base = RX_CPU_BASE;
3428 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3430 cpu_base = TX_CPU_BASE;
3431 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3432 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3435 err = tg3_load_firmware_cpu(tp, cpu_base,
3436 cpu_scratch_base, cpu_scratch_size,
3441 /* Now startup the cpu. */
3442 tw32(cpu_base + CPU_STATE, 0xffffffff);
3443 tw32_f(cpu_base + CPU_PC, info.fw_base);
3445 for (i = 0; i < 5; i++) {
3446 if (tr32(cpu_base + CPU_PC) == info.fw_base)
3448 tw32(cpu_base + CPU_STATE, 0xffffffff);
3449 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3450 tw32_f(cpu_base + CPU_PC, info.fw_base);
3455 "%s fails to set CPU PC, is %08x should be %08x\n",
3456 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3459 tw32(cpu_base + CPU_STATE, 0xffffffff);
3460 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3465 /* tp->lock is held. */
3466 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3468 u32 addr_high, addr_low;
3471 addr_high = ((tp->dev->dev_addr[0] << 8) |
3472 tp->dev->dev_addr[1]);
3473 addr_low = ((tp->dev->dev_addr[2] << 24) |
3474 (tp->dev->dev_addr[3] << 16) |
3475 (tp->dev->dev_addr[4] << 8) |
3476 (tp->dev->dev_addr[5] << 0));
3477 for (i = 0; i < 4; i++) {
3478 if (i == 1 && skip_mac_1)
3480 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3481 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3485 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
3486 for (i = 0; i < 12; i++) {
3487 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3488 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3492 addr_high = (tp->dev->dev_addr[0] +
3493 tp->dev->dev_addr[1] +
3494 tp->dev->dev_addr[2] +
3495 tp->dev->dev_addr[3] +
3496 tp->dev->dev_addr[4] +
3497 tp->dev->dev_addr[5]) &
3498 TX_BACKOFF_SEED_MASK;
3499 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3502 static void tg3_enable_register_access(struct tg3 *tp)
3505 * Make sure register accesses (indirect or otherwise) will function
3508 pci_write_config_dword(tp->pdev,
3509 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3512 static int tg3_power_up(struct tg3 *tp)
3516 tg3_enable_register_access(tp);
3518 err = pci_set_power_state(tp->pdev, PCI_D0);
3520 /* Switch out of Vaux if it is a NIC */
3521 tg3_pwrsrc_switch_to_vmain(tp);
3523 netdev_err(tp->dev, "Transition to D0 failed\n");
3529 static int tg3_setup_phy(struct tg3 *, int);
3531 static int tg3_power_down_prepare(struct tg3 *tp)
3534 bool device_should_wake, do_low_power;
3536 tg3_enable_register_access(tp);
3538 /* Restore the CLKREQ setting. */
3539 if (tg3_flag(tp, CLKREQ_BUG)) {
3542 pci_read_config_word(tp->pdev,
3543 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3545 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3546 pci_write_config_word(tp->pdev,
3547 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3551 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3552 tw32(TG3PCI_MISC_HOST_CTRL,
3553 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3555 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
3556 tg3_flag(tp, WOL_ENABLE);
3558 if (tg3_flag(tp, USE_PHYLIB)) {
3559 do_low_power = false;
3560 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
3561 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3562 struct phy_device *phydev;
3563 u32 phyid, advertising;
3565 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
3567 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3569 tp->link_config.speed = phydev->speed;
3570 tp->link_config.duplex = phydev->duplex;
3571 tp->link_config.autoneg = phydev->autoneg;
3572 tp->link_config.advertising = phydev->advertising;
3574 advertising = ADVERTISED_TP |
3576 ADVERTISED_Autoneg |
3577 ADVERTISED_10baseT_Half;
3579 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3580 if (tg3_flag(tp, WOL_SPEED_100MB))
3582 ADVERTISED_100baseT_Half |
3583 ADVERTISED_100baseT_Full |
3584 ADVERTISED_10baseT_Full;
3586 advertising |= ADVERTISED_10baseT_Full;
3589 phydev->advertising = advertising;
3591 phy_start_aneg(phydev);
3593 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
3594 if (phyid != PHY_ID_BCMAC131) {
3595 phyid &= PHY_BCM_OUI_MASK;
3596 if (phyid == PHY_BCM_OUI_1 ||
3597 phyid == PHY_BCM_OUI_2 ||
3598 phyid == PHY_BCM_OUI_3)
3599 do_low_power = true;
3603 do_low_power = true;
3605 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
3606 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3608 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
3609 tg3_setup_phy(tp, 0);
3612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3615 val = tr32(GRC_VCPU_EXT_CTRL);
3616 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
3617 } else if (!tg3_flag(tp, ENABLE_ASF)) {
3621 for (i = 0; i < 200; i++) {
3622 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3623 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3628 if (tg3_flag(tp, WOL_CAP))
3629 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3630 WOL_DRV_STATE_SHUTDOWN |
3634 if (device_should_wake) {
3637 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
3639 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3640 tg3_phy_auxctl_write(tp,
3641 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
3642 MII_TG3_AUXCTL_PCTL_WOL_EN |
3643 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3644 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
3648 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3649 mac_mode = MAC_MODE_PORT_MODE_GMII;
3651 mac_mode = MAC_MODE_PORT_MODE_MII;
3653 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3654 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3656 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
3657 SPEED_100 : SPEED_10;
3658 if (tg3_5700_link_polarity(tp, speed))
3659 mac_mode |= MAC_MODE_LINK_POLARITY;
3661 mac_mode &= ~MAC_MODE_LINK_POLARITY;
3664 mac_mode = MAC_MODE_PORT_MODE_TBI;
3667 if (!tg3_flag(tp, 5750_PLUS))
3668 tw32(MAC_LED_CTRL, tp->led_ctrl);
3670 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
3671 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3672 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
3673 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
3675 if (tg3_flag(tp, ENABLE_APE))
3676 mac_mode |= MAC_MODE_APE_TX_EN |
3677 MAC_MODE_APE_RX_EN |
3678 MAC_MODE_TDE_ENABLE;
3680 tw32_f(MAC_MODE, mac_mode);
3683 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3687 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
3688 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3689 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
3692 base_val = tp->pci_clock_ctrl;
3693 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3694 CLOCK_CTRL_TXCLK_DISABLE);
3696 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
3697 CLOCK_CTRL_PWRDOWN_PLL133, 40);
3698 } else if (tg3_flag(tp, 5780_CLASS) ||
3699 tg3_flag(tp, CPMU_PRESENT) ||
3700 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3702 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
3703 u32 newbits1, newbits2;
3705 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3706 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3707 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3708 CLOCK_CTRL_TXCLK_DISABLE |
3710 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3711 } else if (tg3_flag(tp, 5705_PLUS)) {
3712 newbits1 = CLOCK_CTRL_625_CORE;
3713 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3715 newbits1 = CLOCK_CTRL_ALTCLK;
3716 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3719 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
3722 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
3725 if (!tg3_flag(tp, 5705_PLUS)) {
3728 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3729 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3730 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3731 CLOCK_CTRL_TXCLK_DISABLE |
3732 CLOCK_CTRL_44MHZ_CORE);
3734 newbits3 = CLOCK_CTRL_44MHZ_CORE;
3737 tw32_wait_f(TG3PCI_CLOCK_CTRL,
3738 tp->pci_clock_ctrl | newbits3, 40);
3742 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
3743 tg3_power_down_phy(tp, do_low_power);
3745 tg3_frob_aux_power(tp, true);
3747 /* Workaround for unstable PLL clock */
3748 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3749 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3750 u32 val = tr32(0x7d00);
3752 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3754 if (!tg3_flag(tp, ENABLE_ASF)) {
3757 err = tg3_nvram_lock(tp);
3758 tg3_halt_cpu(tp, RX_CPU_BASE);
3760 tg3_nvram_unlock(tp);
3764 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3769 static void tg3_power_down(struct tg3 *tp)
3771 tg3_power_down_prepare(tp);
3773 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
3774 pci_set_power_state(tp->pdev, PCI_D3hot);
3777 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3779 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3780 case MII_TG3_AUX_STAT_10HALF:
3782 *duplex = DUPLEX_HALF;
3785 case MII_TG3_AUX_STAT_10FULL:
3787 *duplex = DUPLEX_FULL;
3790 case MII_TG3_AUX_STAT_100HALF:
3792 *duplex = DUPLEX_HALF;
3795 case MII_TG3_AUX_STAT_100FULL:
3797 *duplex = DUPLEX_FULL;
3800 case MII_TG3_AUX_STAT_1000HALF:
3801 *speed = SPEED_1000;
3802 *duplex = DUPLEX_HALF;
3805 case MII_TG3_AUX_STAT_1000FULL:
3806 *speed = SPEED_1000;
3807 *duplex = DUPLEX_FULL;
3811 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3812 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3814 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3818 *speed = SPEED_UNKNOWN;
3819 *duplex = DUPLEX_UNKNOWN;
3824 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3829 new_adv = ADVERTISE_CSMA;
3830 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
3831 new_adv |= mii_advertise_flowctrl(flowctrl);
3833 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3837 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3838 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
3840 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3841 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
3842 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
3844 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3849 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3852 tw32(TG3_CPMU_EEE_MODE,
3853 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3855 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3860 /* Advertise 100-BaseTX EEE ability */
3861 if (advertise & ADVERTISED_100baseT_Full)
3862 val |= MDIO_AN_EEE_ADV_100TX;
3863 /* Advertise 1000-BaseT EEE ability */
3864 if (advertise & ADVERTISED_1000baseT_Full)
3865 val |= MDIO_AN_EEE_ADV_1000T;
3866 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3870 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3872 case ASIC_REV_57765:
3873 case ASIC_REV_57766:
3875 /* If we advertised any eee advertisements above... */
3877 val = MII_TG3_DSP_TAP26_ALNOKO |
3878 MII_TG3_DSP_TAP26_RMRXSTO |
3879 MII_TG3_DSP_TAP26_OPCSINPT;
3880 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3883 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3884 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3885 MII_TG3_DSP_CH34TP2_HIBW01);
3888 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3897 static void tg3_phy_copper_begin(struct tg3 *tp)
3899 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
3900 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3903 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
3904 adv = ADVERTISED_10baseT_Half |
3905 ADVERTISED_10baseT_Full;
3906 if (tg3_flag(tp, WOL_SPEED_100MB))
3907 adv |= ADVERTISED_100baseT_Half |
3908 ADVERTISED_100baseT_Full;
3910 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
3912 adv = tp->link_config.advertising;
3913 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3914 adv &= ~(ADVERTISED_1000baseT_Half |
3915 ADVERTISED_1000baseT_Full);
3917 fc = tp->link_config.flowctrl;
3920 tg3_phy_autoneg_cfg(tp, adv, fc);
3922 tg3_writephy(tp, MII_BMCR,
3923 BMCR_ANENABLE | BMCR_ANRESTART);
3926 u32 bmcr, orig_bmcr;
3928 tp->link_config.active_speed = tp->link_config.speed;
3929 tp->link_config.active_duplex = tp->link_config.duplex;
3932 switch (tp->link_config.speed) {
3938 bmcr |= BMCR_SPEED100;
3942 bmcr |= BMCR_SPEED1000;
3946 if (tp->link_config.duplex == DUPLEX_FULL)
3947 bmcr |= BMCR_FULLDPLX;
3949 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3950 (bmcr != orig_bmcr)) {
3951 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3952 for (i = 0; i < 1500; i++) {
3956 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3957 tg3_readphy(tp, MII_BMSR, &tmp))
3959 if (!(tmp & BMSR_LSTATUS)) {
3964 tg3_writephy(tp, MII_BMCR, bmcr);
3970 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3974 /* Turn off tap power management. */
3975 /* Set Extended packet length bit */
3976 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3978 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3979 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3980 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3981 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3982 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3989 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
3991 u32 advmsk, tgtadv, advertising;
3993 advertising = tp->link_config.advertising;
3994 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
3996 advmsk = ADVERTISE_ALL;
3997 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3998 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
3999 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4002 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4005 if ((*lcladv & advmsk) != tgtadv)
4008 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4011 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4013 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4017 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4018 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
4019 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4020 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4021 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4023 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4026 if (tg3_ctrl != tgtadv)
4033 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4037 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4040 if (tg3_readphy(tp, MII_STAT1000, &val))
4043 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4046 if (tg3_readphy(tp, MII_LPA, rmtadv))
4049 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4050 tp->link_config.rmt_adv = lpeth;
4055 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
4057 int current_link_up;
4059 u32 lcl_adv, rmt_adv;
4067 (MAC_STATUS_SYNC_CHANGED |
4068 MAC_STATUS_CFG_CHANGED |
4069 MAC_STATUS_MI_COMPLETION |
4070 MAC_STATUS_LNKSTATE_CHANGED));
4073 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4075 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4079 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4081 /* Some third-party PHYs need to be reset on link going
4084 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
4085 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
4086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
4087 netif_carrier_ok(tp->dev)) {
4088 tg3_readphy(tp, MII_BMSR, &bmsr);
4089 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4090 !(bmsr & BMSR_LSTATUS))
4096 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4097 tg3_readphy(tp, MII_BMSR, &bmsr);
4098 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4099 !tg3_flag(tp, INIT_COMPLETE))
4102 if (!(bmsr & BMSR_LSTATUS)) {
4103 err = tg3_init_5401phy_dsp(tp);
4107 tg3_readphy(tp, MII_BMSR, &bmsr);
4108 for (i = 0; i < 1000; i++) {
4110 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4111 (bmsr & BMSR_LSTATUS)) {
4117 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4118 TG3_PHY_REV_BCM5401_B0 &&
4119 !(bmsr & BMSR_LSTATUS) &&
4120 tp->link_config.active_speed == SPEED_1000) {
4121 err = tg3_phy_reset(tp);
4123 err = tg3_init_5401phy_dsp(tp);
4128 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4129 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
4130 /* 5701 {A0,B0} CRC bug workaround */
4131 tg3_writephy(tp, 0x15, 0x0a75);
4132 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4133 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4134 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4137 /* Clear pending interrupts... */
4138 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4139 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4141 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4142 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4143 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4144 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
4147 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
4148 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4149 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4150 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4152 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4155 current_link_up = 0;
4156 current_speed = SPEED_UNKNOWN;
4157 current_duplex = DUPLEX_UNKNOWN;
4158 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4159 tp->link_config.rmt_adv = 0;
4161 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4162 err = tg3_phy_auxctl_read(tp,
4163 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4165 if (!err && !(val & (1 << 10))) {
4166 tg3_phy_auxctl_write(tp,
4167 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4174 for (i = 0; i < 100; i++) {
4175 tg3_readphy(tp, MII_BMSR, &bmsr);
4176 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4177 (bmsr & BMSR_LSTATUS))
4182 if (bmsr & BMSR_LSTATUS) {
4185 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4186 for (i = 0; i < 2000; i++) {
4188 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4193 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4198 for (i = 0; i < 200; i++) {
4199 tg3_readphy(tp, MII_BMCR, &bmcr);
4200 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4202 if (bmcr && bmcr != 0x7fff)
4210 tp->link_config.active_speed = current_speed;
4211 tp->link_config.active_duplex = current_duplex;
4213 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4214 if ((bmcr & BMCR_ANENABLE) &&
4215 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4216 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4217 current_link_up = 1;
4219 if (!(bmcr & BMCR_ANENABLE) &&
4220 tp->link_config.speed == current_speed &&
4221 tp->link_config.duplex == current_duplex &&
4222 tp->link_config.flowctrl ==
4223 tp->link_config.active_flowctrl) {
4224 current_link_up = 1;
4228 if (current_link_up == 1 &&
4229 tp->link_config.active_duplex == DUPLEX_FULL) {
4232 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4233 reg = MII_TG3_FET_GEN_STAT;
4234 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4236 reg = MII_TG3_EXT_STAT;
4237 bit = MII_TG3_EXT_STAT_MDIX;
4240 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4241 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4243 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4248 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4249 tg3_phy_copper_begin(tp);
4251 tg3_readphy(tp, MII_BMSR, &bmsr);
4252 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4253 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4254 current_link_up = 1;
4257 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4258 if (current_link_up == 1) {
4259 if (tp->link_config.active_speed == SPEED_100 ||
4260 tp->link_config.active_speed == SPEED_10)
4261 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4263 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4264 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4265 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4267 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4269 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4270 if (tp->link_config.active_duplex == DUPLEX_HALF)
4271 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4273 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
4274 if (current_link_up == 1 &&
4275 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
4276 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
4278 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
4281 /* ??? Without this setting Netgear GA302T PHY does not
4282 * ??? send/receive packets...
4284 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4285 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
4286 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4287 tw32_f(MAC_MI_MODE, tp->mi_mode);
4291 tw32_f(MAC_MODE, tp->mac_mode);
4294 tg3_phy_eee_adjust(tp, current_link_up);
4296 if (tg3_flag(tp, USE_LINKCHG_REG)) {
4297 /* Polled via timer. */
4298 tw32_f(MAC_EVENT, 0);
4300 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4304 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
4305 current_link_up == 1 &&
4306 tp->link_config.active_speed == SPEED_1000 &&
4307 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
4310 (MAC_STATUS_SYNC_CHANGED |
4311 MAC_STATUS_CFG_CHANGED));
4314 NIC_SRAM_FIRMWARE_MBOX,
4315 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4318 /* Prevent send BD corruption. */
4319 if (tg3_flag(tp, CLKREQ_BUG)) {
4320 u16 oldlnkctl, newlnkctl;
4322 pci_read_config_word(tp->pdev,
4323 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
4325 if (tp->link_config.active_speed == SPEED_100 ||
4326 tp->link_config.active_speed == SPEED_10)
4327 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
4329 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
4330 if (newlnkctl != oldlnkctl)
4331 pci_write_config_word(tp->pdev,
4332 pci_pcie_cap(tp->pdev) +
4333 PCI_EXP_LNKCTL, newlnkctl);
4336 if (current_link_up != netif_carrier_ok(tp->dev)) {
4337 if (current_link_up)
4338 netif_carrier_on(tp->dev);
4340 netif_carrier_off(tp->dev);
4341 tg3_link_report(tp);
4347 struct tg3_fiber_aneginfo {
4349 #define ANEG_STATE_UNKNOWN 0
4350 #define ANEG_STATE_AN_ENABLE 1
4351 #define ANEG_STATE_RESTART_INIT 2
4352 #define ANEG_STATE_RESTART 3
4353 #define ANEG_STATE_DISABLE_LINK_OK 4
4354 #define ANEG_STATE_ABILITY_DETECT_INIT 5
4355 #define ANEG_STATE_ABILITY_DETECT 6
4356 #define ANEG_STATE_ACK_DETECT_INIT 7
4357 #define ANEG_STATE_ACK_DETECT 8
4358 #define ANEG_STATE_COMPLETE_ACK_INIT 9
4359 #define ANEG_STATE_COMPLETE_ACK 10
4360 #define ANEG_STATE_IDLE_DETECT_INIT 11
4361 #define ANEG_STATE_IDLE_DETECT 12
4362 #define ANEG_STATE_LINK_OK 13
4363 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4364 #define ANEG_STATE_NEXT_PAGE_WAIT 15
4367 #define MR_AN_ENABLE 0x00000001
4368 #define MR_RESTART_AN 0x00000002
4369 #define MR_AN_COMPLETE 0x00000004
4370 #define MR_PAGE_RX 0x00000008
4371 #define MR_NP_LOADED 0x00000010
4372 #define MR_TOGGLE_TX 0x00000020
4373 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
4374 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
4375 #define MR_LP_ADV_SYM_PAUSE 0x00000100
4376 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
4377 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4378 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4379 #define MR_LP_ADV_NEXT_PAGE 0x00001000
4380 #define MR_TOGGLE_RX 0x00002000
4381 #define MR_NP_RX 0x00004000
4383 #define MR_LINK_OK 0x80000000
4385 unsigned long link_time, cur_time;
4387 u32 ability_match_cfg;
4388 int ability_match_count;
4390 char ability_match, idle_match, ack_match;
4392 u32 txconfig, rxconfig;
4393 #define ANEG_CFG_NP 0x00000080
4394 #define ANEG_CFG_ACK 0x00000040
4395 #define ANEG_CFG_RF2 0x00000020
4396 #define ANEG_CFG_RF1 0x00000010
4397 #define ANEG_CFG_PS2 0x00000001
4398 #define ANEG_CFG_PS1 0x00008000
4399 #define ANEG_CFG_HD 0x00004000
4400 #define ANEG_CFG_FD 0x00002000
4401 #define ANEG_CFG_INVAL 0x00001f06
4406 #define ANEG_TIMER_ENAB 2
4407 #define ANEG_FAILED -1
4409 #define ANEG_STATE_SETTLE_TIME 10000
4411 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4412 struct tg3_fiber_aneginfo *ap)
4415 unsigned long delta;
4419 if (ap->state == ANEG_STATE_UNKNOWN) {
4423 ap->ability_match_cfg = 0;
4424 ap->ability_match_count = 0;
4425 ap->ability_match = 0;
4431 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
4432 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4434 if (rx_cfg_reg != ap->ability_match_cfg) {
4435 ap->ability_match_cfg = rx_cfg_reg;
4436 ap->ability_match = 0;
4437 ap->ability_match_count = 0;
4439 if (++ap->ability_match_count > 1) {
4440 ap->ability_match = 1;
4441 ap->ability_match_cfg = rx_cfg_reg;
4444 if (rx_cfg_reg & ANEG_CFG_ACK)
4452 ap->ability_match_cfg = 0;
4453 ap->ability_match_count = 0;
4454 ap->ability_match = 0;
4460 ap->rxconfig = rx_cfg_reg;
4463 switch (ap->state) {
4464 case ANEG_STATE_UNKNOWN:
4465 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4466 ap->state = ANEG_STATE_AN_ENABLE;
4469 case ANEG_STATE_AN_ENABLE:
4470 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4471 if (ap->flags & MR_AN_ENABLE) {
4474 ap->ability_match_cfg = 0;
4475 ap->ability_match_count = 0;
4476 ap->ability_match = 0;
4480 ap->state = ANEG_STATE_RESTART_INIT;
4482 ap->state = ANEG_STATE_DISABLE_LINK_OK;
4486 case ANEG_STATE_RESTART_INIT:
4487 ap->link_time = ap->cur_time;
4488 ap->flags &= ~(MR_NP_LOADED);
4490 tw32(MAC_TX_AUTO_NEG, 0);
4491 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4492 tw32_f(MAC_MODE, tp->mac_mode);
4495 ret = ANEG_TIMER_ENAB;
4496 ap->state = ANEG_STATE_RESTART;
4499 case ANEG_STATE_RESTART:
4500 delta = ap->cur_time - ap->link_time;
4501 if (delta > ANEG_STATE_SETTLE_TIME)
4502 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
4504 ret = ANEG_TIMER_ENAB;
4507 case ANEG_STATE_DISABLE_LINK_OK:
4511 case ANEG_STATE_ABILITY_DETECT_INIT:
4512 ap->flags &= ~(MR_TOGGLE_TX);
4513 ap->txconfig = ANEG_CFG_FD;
4514 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4515 if (flowctrl & ADVERTISE_1000XPAUSE)
4516 ap->txconfig |= ANEG_CFG_PS1;
4517 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4518 ap->txconfig |= ANEG_CFG_PS2;
4519 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4520 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4521 tw32_f(MAC_MODE, tp->mac_mode);
4524 ap->state = ANEG_STATE_ABILITY_DETECT;
4527 case ANEG_STATE_ABILITY_DETECT:
4528 if (ap->ability_match != 0 && ap->rxconfig != 0)
4529 ap->state = ANEG_STATE_ACK_DETECT_INIT;
4532 case ANEG_STATE_ACK_DETECT_INIT:
4533 ap->txconfig |= ANEG_CFG_ACK;
4534 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4535 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4536 tw32_f(MAC_MODE, tp->mac_mode);
4539 ap->state = ANEG_STATE_ACK_DETECT;
4542 case ANEG_STATE_ACK_DETECT:
4543 if (ap->ack_match != 0) {
4544 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4545 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4546 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
4548 ap->state = ANEG_STATE_AN_ENABLE;
4550 } else if (ap->ability_match != 0 &&
4551 ap->rxconfig == 0) {
4552 ap->state = ANEG_STATE_AN_ENABLE;
4556 case ANEG_STATE_COMPLETE_ACK_INIT:
4557 if (ap->rxconfig & ANEG_CFG_INVAL) {
4561 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4562 MR_LP_ADV_HALF_DUPLEX |
4563 MR_LP_ADV_SYM_PAUSE |
4564 MR_LP_ADV_ASYM_PAUSE |
4565 MR_LP_ADV_REMOTE_FAULT1 |
4566 MR_LP_ADV_REMOTE_FAULT2 |
4567 MR_LP_ADV_NEXT_PAGE |
4570 if (ap->rxconfig & ANEG_CFG_FD)
4571 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
4572 if (ap->rxconfig & ANEG_CFG_HD)
4573 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
4574 if (ap->rxconfig & ANEG_CFG_PS1)
4575 ap->flags |= MR_LP_ADV_SYM_PAUSE;
4576 if (ap->rxconfig & ANEG_CFG_PS2)
4577 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4578 if (ap->rxconfig & ANEG_CFG_RF1)
4579 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
4580 if (ap->rxconfig & ANEG_CFG_RF2)
4581 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
4582 if (ap->rxconfig & ANEG_CFG_NP)
4583 ap->flags |= MR_LP_ADV_NEXT_PAGE;
4585 ap->link_time = ap->cur_time;
4587 ap->flags ^= (MR_TOGGLE_TX);
4588 if (ap->rxconfig & 0x0008)
4589 ap->flags |= MR_TOGGLE_RX;
4590 if (ap->rxconfig & ANEG_CFG_NP)
4591 ap->flags |= MR_NP_RX;
4592 ap->flags |= MR_PAGE_RX;
4594 ap->state = ANEG_STATE_COMPLETE_ACK;
4595 ret = ANEG_TIMER_ENAB;
4598 case ANEG_STATE_COMPLETE_ACK:
4599 if (ap->ability_match != 0 &&
4600 ap->rxconfig == 0) {
4601 ap->state = ANEG_STATE_AN_ENABLE;
4604 delta = ap->cur_time - ap->link_time;
4605 if (delta > ANEG_STATE_SETTLE_TIME) {
4606 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4607 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4609 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4610 !(ap->flags & MR_NP_RX)) {
4611 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4619 case ANEG_STATE_IDLE_DETECT_INIT:
4620 ap->link_time = ap->cur_time;
4621 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4622 tw32_f(MAC_MODE, tp->mac_mode);
4625 ap->state = ANEG_STATE_IDLE_DETECT;
4626 ret = ANEG_TIMER_ENAB;
4629 case ANEG_STATE_IDLE_DETECT:
4630 if (ap->ability_match != 0 &&
4631 ap->rxconfig == 0) {
4632 ap->state = ANEG_STATE_AN_ENABLE;
4635 delta = ap->cur_time - ap->link_time;
4636 if (delta > ANEG_STATE_SETTLE_TIME) {
4637 /* XXX another gem from the Broadcom driver :( */
4638 ap->state = ANEG_STATE_LINK_OK;
4642 case ANEG_STATE_LINK_OK:
4643 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4647 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
4648 /* ??? unimplemented */
4651 case ANEG_STATE_NEXT_PAGE_WAIT:
4652 /* ??? unimplemented */
4663 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
4666 struct tg3_fiber_aneginfo aninfo;
4667 int status = ANEG_FAILED;
4671 tw32_f(MAC_TX_AUTO_NEG, 0);
4673 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4674 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
4677 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
4680 memset(&aninfo, 0, sizeof(aninfo));
4681 aninfo.flags |= MR_AN_ENABLE;
4682 aninfo.state = ANEG_STATE_UNKNOWN;
4683 aninfo.cur_time = 0;
4685 while (++tick < 195000) {
4686 status = tg3_fiber_aneg_smachine(tp, &aninfo);
4687 if (status == ANEG_DONE || status == ANEG_FAILED)
4693 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4694 tw32_f(MAC_MODE, tp->mac_mode);
4697 *txflags = aninfo.txconfig;
4698 *rxflags = aninfo.flags;
4700 if (status == ANEG_DONE &&
4701 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4702 MR_LP_ADV_FULL_DUPLEX)))
4708 static void tg3_init_bcm8002(struct tg3 *tp)
4710 u32 mac_status = tr32(MAC_STATUS);
4713 /* Reset when initting first time or we have a link. */
4714 if (tg3_flag(tp, INIT_COMPLETE) &&
4715 !(mac_status & MAC_STATUS_PCS_SYNCED))
4718 /* Set PLL lock range. */
4719 tg3_writephy(tp, 0x16, 0x8007);
4722 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4724 /* Wait for reset to complete. */
4725 /* XXX schedule_timeout() ... */
4726 for (i = 0; i < 500; i++)
4729 /* Config mode; select PMA/Ch 1 regs. */
4730 tg3_writephy(tp, 0x10, 0x8411);
4732 /* Enable auto-lock and comdet, select txclk for tx. */
4733 tg3_writephy(tp, 0x11, 0x0a10);
4735 tg3_writephy(tp, 0x18, 0x00a0);
4736 tg3_writephy(tp, 0x16, 0x41ff);
4738 /* Assert and deassert POR. */
4739 tg3_writephy(tp, 0x13, 0x0400);
4741 tg3_writephy(tp, 0x13, 0x0000);
4743 tg3_writephy(tp, 0x11, 0x0a50);
4745 tg3_writephy(tp, 0x11, 0x0a10);
4747 /* Wait for signal to stabilize */
4748 /* XXX schedule_timeout() ... */
4749 for (i = 0; i < 15000; i++)
4752 /* Deselect the channel register so we can read the PHYID
4755 tg3_writephy(tp, 0x10, 0x8011);
4758 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4761 u32 sg_dig_ctrl, sg_dig_status;
4762 u32 serdes_cfg, expected_sg_dig_ctrl;
4763 int workaround, port_a;
4764 int current_link_up;
4767 expected_sg_dig_ctrl = 0;
4770 current_link_up = 0;
4772 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4773 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4775 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4778 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4779 /* preserve bits 20-23 for voltage regulator */
4780 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4783 sg_dig_ctrl = tr32(SG_DIG_CTRL);
4785 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
4786 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
4788 u32 val = serdes_cfg;
4794 tw32_f(MAC_SERDES_CFG, val);
4797 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4799 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4800 tg3_setup_flow_control(tp, 0, 0);
4801 current_link_up = 1;
4806 /* Want auto-negotiation. */
4807 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
4809 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4810 if (flowctrl & ADVERTISE_1000XPAUSE)
4811 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4812 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4813 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
4815 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
4816 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
4817 tp->serdes_counter &&
4818 ((mac_status & (MAC_STATUS_PCS_SYNCED |
4819 MAC_STATUS_RCVD_CFG)) ==
4820 MAC_STATUS_PCS_SYNCED)) {
4821 tp->serdes_counter--;
4822 current_link_up = 1;
4827 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
4828 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
4830 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4832 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4833 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4834 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4835 MAC_STATUS_SIGNAL_DET)) {
4836 sg_dig_status = tr32(SG_DIG_STATUS);
4837 mac_status = tr32(MAC_STATUS);
4839 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
4840 (mac_status & MAC_STATUS_PCS_SYNCED)) {
4841 u32 local_adv = 0, remote_adv = 0;
4843 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4844 local_adv |= ADVERTISE_1000XPAUSE;
4845 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4846 local_adv |= ADVERTISE_1000XPSE_ASYM;
4848 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
4849 remote_adv |= LPA_1000XPAUSE;
4850 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
4851 remote_adv |= LPA_1000XPAUSE_ASYM;
4853 tp->link_config.rmt_adv =
4854 mii_adv_to_ethtool_adv_x(remote_adv);
4856 tg3_setup_flow_control(tp, local_adv, remote_adv);
4857 current_link_up = 1;
4858 tp->serdes_counter = 0;
4859 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4860 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
4861 if (tp->serdes_counter)
4862 tp->serdes_counter--;
4865 u32 val = serdes_cfg;
4872 tw32_f(MAC_SERDES_CFG, val);
4875 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4878 /* Link parallel detection - link is up */
4879 /* only if we have PCS_SYNC and not */
4880 /* receiving config code words */
4881 mac_status = tr32(MAC_STATUS);
4882 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4883 !(mac_status & MAC_STATUS_RCVD_CFG)) {
4884 tg3_setup_flow_control(tp, 0, 0);
4885 current_link_up = 1;
4887 TG3_PHYFLG_PARALLEL_DETECT;
4888 tp->serdes_counter =
4889 SERDES_PARALLEL_DET_TIMEOUT;
4891 goto restart_autoneg;
4895 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4896 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4900 return current_link_up;
4903 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4905 int current_link_up = 0;
4907 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4910 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4911 u32 txflags, rxflags;
4914 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4915 u32 local_adv = 0, remote_adv = 0;
4917 if (txflags & ANEG_CFG_PS1)
4918 local_adv |= ADVERTISE_1000XPAUSE;
4919 if (txflags & ANEG_CFG_PS2)
4920 local_adv |= ADVERTISE_1000XPSE_ASYM;
4922 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4923 remote_adv |= LPA_1000XPAUSE;
4924 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4925 remote_adv |= LPA_1000XPAUSE_ASYM;
4927 tp->link_config.rmt_adv =
4928 mii_adv_to_ethtool_adv_x(remote_adv);
4930 tg3_setup_flow_control(tp, local_adv, remote_adv);
4932 current_link_up = 1;
4934 for (i = 0; i < 30; i++) {
4937 (MAC_STATUS_SYNC_CHANGED |
4938 MAC_STATUS_CFG_CHANGED));
4940 if ((tr32(MAC_STATUS) &
4941 (MAC_STATUS_SYNC_CHANGED |
4942 MAC_STATUS_CFG_CHANGED)) == 0)
4946 mac_status = tr32(MAC_STATUS);
4947 if (current_link_up == 0 &&
4948 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4949 !(mac_status & MAC_STATUS_RCVD_CFG))
4950 current_link_up = 1;
4952 tg3_setup_flow_control(tp, 0, 0);
4954 /* Forcing 1000FD link up. */
4955 current_link_up = 1;
4957 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4960 tw32_f(MAC_MODE, tp->mac_mode);
4965 return current_link_up;
4968 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4971 u16 orig_active_speed;
4972 u8 orig_active_duplex;
4974 int current_link_up;
4977 orig_pause_cfg = tp->link_config.active_flowctrl;
4978 orig_active_speed = tp->link_config.active_speed;
4979 orig_active_duplex = tp->link_config.active_duplex;
4981 if (!tg3_flag(tp, HW_AUTONEG) &&
4982 netif_carrier_ok(tp->dev) &&
4983 tg3_flag(tp, INIT_COMPLETE)) {
4984 mac_status = tr32(MAC_STATUS);
4985 mac_status &= (MAC_STATUS_PCS_SYNCED |
4986 MAC_STATUS_SIGNAL_DET |
4987 MAC_STATUS_CFG_CHANGED |
4988 MAC_STATUS_RCVD_CFG);
4989 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4990 MAC_STATUS_SIGNAL_DET)) {
4991 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4992 MAC_STATUS_CFG_CHANGED));
4997 tw32_f(MAC_TX_AUTO_NEG, 0);
4999 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5000 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5001 tw32_f(MAC_MODE, tp->mac_mode);
5004 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5005 tg3_init_bcm8002(tp);
5007 /* Enable link change event even when serdes polling. */
5008 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5011 current_link_up = 0;
5012 tp->link_config.rmt_adv = 0;
5013 mac_status = tr32(MAC_STATUS);
5015 if (tg3_flag(tp, HW_AUTONEG))
5016 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5018 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5020 tp->napi[0].hw_status->status =
5021 (SD_STATUS_UPDATED |
5022 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5024 for (i = 0; i < 100; i++) {
5025 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5026 MAC_STATUS_CFG_CHANGED));
5028 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5029 MAC_STATUS_CFG_CHANGED |
5030 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5034 mac_status = tr32(MAC_STATUS);
5035 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5036 current_link_up = 0;
5037 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5038 tp->serdes_counter == 0) {
5039 tw32_f(MAC_MODE, (tp->mac_mode |
5040 MAC_MODE_SEND_CONFIGS));
5042 tw32_f(MAC_MODE, tp->mac_mode);
5046 if (current_link_up == 1) {
5047 tp->link_config.active_speed = SPEED_1000;
5048 tp->link_config.active_duplex = DUPLEX_FULL;
5049 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5050 LED_CTRL_LNKLED_OVERRIDE |
5051 LED_CTRL_1000MBPS_ON));
5053 tp->link_config.active_speed = SPEED_UNKNOWN;
5054 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5055 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5056 LED_CTRL_LNKLED_OVERRIDE |
5057 LED_CTRL_TRAFFIC_OVERRIDE));
5060 if (current_link_up != netif_carrier_ok(tp->dev)) {
5061 if (current_link_up)
5062 netif_carrier_on(tp->dev);
5064 netif_carrier_off(tp->dev);
5065 tg3_link_report(tp);
5067 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5068 if (orig_pause_cfg != now_pause_cfg ||
5069 orig_active_speed != tp->link_config.active_speed ||
5070 orig_active_duplex != tp->link_config.active_duplex)
5071 tg3_link_report(tp);
5077 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
5079 int current_link_up, err = 0;
5083 u32 local_adv, remote_adv;
5085 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5086 tw32_f(MAC_MODE, tp->mac_mode);
5092 (MAC_STATUS_SYNC_CHANGED |
5093 MAC_STATUS_CFG_CHANGED |
5094 MAC_STATUS_MI_COMPLETION |
5095 MAC_STATUS_LNKSTATE_CHANGED));
5101 current_link_up = 0;
5102 current_speed = SPEED_UNKNOWN;
5103 current_duplex = DUPLEX_UNKNOWN;
5104 tp->link_config.rmt_adv = 0;
5106 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5107 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5108 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
5109 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5110 bmsr |= BMSR_LSTATUS;
5112 bmsr &= ~BMSR_LSTATUS;
5115 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5117 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5118 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5119 /* do nothing, just check for link up at the end */
5120 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5123 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5124 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5125 ADVERTISE_1000XPAUSE |
5126 ADVERTISE_1000XPSE_ASYM |
5129 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5130 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5132 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5133 tg3_writephy(tp, MII_ADVERTISE, newadv);
5134 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5135 tg3_writephy(tp, MII_BMCR, bmcr);
5137 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5138 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5139 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5146 bmcr &= ~BMCR_SPEED1000;
5147 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5149 if (tp->link_config.duplex == DUPLEX_FULL)
5150 new_bmcr |= BMCR_FULLDPLX;
5152 if (new_bmcr != bmcr) {
5153 /* BMCR_SPEED1000 is a reserved bit that needs
5154 * to be set on write.
5156 new_bmcr |= BMCR_SPEED1000;
5158 /* Force a linkdown */
5159 if (netif_carrier_ok(tp->dev)) {
5162 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5163 adv &= ~(ADVERTISE_1000XFULL |
5164 ADVERTISE_1000XHALF |
5166 tg3_writephy(tp, MII_ADVERTISE, adv);
5167 tg3_writephy(tp, MII_BMCR, bmcr |
5171 netif_carrier_off(tp->dev);
5173 tg3_writephy(tp, MII_BMCR, new_bmcr);
5175 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5176 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5177 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
5179 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5180 bmsr |= BMSR_LSTATUS;
5182 bmsr &= ~BMSR_LSTATUS;
5184 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5188 if (bmsr & BMSR_LSTATUS) {
5189 current_speed = SPEED_1000;
5190 current_link_up = 1;
5191 if (bmcr & BMCR_FULLDPLX)
5192 current_duplex = DUPLEX_FULL;
5194 current_duplex = DUPLEX_HALF;
5199 if (bmcr & BMCR_ANENABLE) {
5202 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5203 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5204 common = local_adv & remote_adv;
5205 if (common & (ADVERTISE_1000XHALF |
5206 ADVERTISE_1000XFULL)) {
5207 if (common & ADVERTISE_1000XFULL)
5208 current_duplex = DUPLEX_FULL;
5210 current_duplex = DUPLEX_HALF;
5212 tp->link_config.rmt_adv =
5213 mii_adv_to_ethtool_adv_x(remote_adv);
5214 } else if (!tg3_flag(tp, 5780_CLASS)) {
5215 /* Link is up via parallel detect */
5217 current_link_up = 0;
5222 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
5223 tg3_setup_flow_control(tp, local_adv, remote_adv);
5225 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5226 if (tp->link_config.active_duplex == DUPLEX_HALF)
5227 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5229 tw32_f(MAC_MODE, tp->mac_mode);
5232 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5234 tp->link_config.active_speed = current_speed;
5235 tp->link_config.active_duplex = current_duplex;
5237 if (current_link_up != netif_carrier_ok(tp->dev)) {
5238 if (current_link_up)
5239 netif_carrier_on(tp->dev);
5241 netif_carrier_off(tp->dev);
5242 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5244 tg3_link_report(tp);
5249 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5251 if (tp->serdes_counter) {
5252 /* Give autoneg time to complete. */
5253 tp->serdes_counter--;
5257 if (!netif_carrier_ok(tp->dev) &&
5258 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5261 tg3_readphy(tp, MII_BMCR, &bmcr);
5262 if (bmcr & BMCR_ANENABLE) {
5265 /* Select shadow register 0x1f */
5266 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5267 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
5269 /* Select expansion interrupt status register */
5270 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5271 MII_TG3_DSP_EXP1_INT_STAT);
5272 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5273 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5275 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5276 /* We have signal detect and not receiving
5277 * config code words, link is up by parallel
5281 bmcr &= ~BMCR_ANENABLE;
5282 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5283 tg3_writephy(tp, MII_BMCR, bmcr);
5284 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
5287 } else if (netif_carrier_ok(tp->dev) &&
5288 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
5289 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5292 /* Select expansion interrupt status register */
5293 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5294 MII_TG3_DSP_EXP1_INT_STAT);
5295 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5299 /* Config code words received, turn on autoneg. */
5300 tg3_readphy(tp, MII_BMCR, &bmcr);
5301 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5303 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5309 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5314 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5315 err = tg3_setup_fiber_phy(tp, force_reset);
5316 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
5317 err = tg3_setup_fiber_mii_phy(tp, force_reset);
5319 err = tg3_setup_copper_phy(tp, force_reset);
5321 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
5324 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5325 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5327 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5332 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5333 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5334 tw32(GRC_MISC_CFG, val);
5337 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5338 (6 << TX_LENGTHS_IPG_SHIFT);
5339 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
5340 val |= tr32(MAC_TX_LENGTHS) &
5341 (TX_LENGTHS_JMB_FRM_LEN_MSK |
5342 TX_LENGTHS_CNT_DWN_VAL_MSK);
5344 if (tp->link_config.active_speed == SPEED_1000 &&
5345 tp->link_config.active_duplex == DUPLEX_HALF)
5346 tw32(MAC_TX_LENGTHS, val |
5347 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
5349 tw32(MAC_TX_LENGTHS, val |
5350 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5352 if (!tg3_flag(tp, 5705_PLUS)) {
5353 if (netif_carrier_ok(tp->dev)) {
5354 tw32(HOSTCC_STAT_COAL_TICKS,
5355 tp->coal.stats_block_coalesce_usecs);
5357 tw32(HOSTCC_STAT_COAL_TICKS, 0);
5361 if (tg3_flag(tp, ASPM_WORKAROUND)) {
5362 val = tr32(PCIE_PWR_MGMT_THRESH);
5363 if (!netif_carrier_ok(tp->dev))
5364 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5367 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5368 tw32(PCIE_PWR_MGMT_THRESH, val);
5374 static inline int tg3_irq_sync(struct tg3 *tp)
5376 return tp->irq_sync;
5379 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5383 dst = (u32 *)((u8 *)dst + off);
5384 for (i = 0; i < len; i += sizeof(u32))
5385 *dst++ = tr32(off + i);
5388 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5390 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5391 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5392 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5393 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5394 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5395 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5396 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5397 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5398 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5399 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5400 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5401 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5402 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5403 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5404 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5405 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5406 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5407 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5408 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5410 if (tg3_flag(tp, SUPPORT_MSIX))
5411 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5413 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5414 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5415 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5416 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5417 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5418 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5419 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5420 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5422 if (!tg3_flag(tp, 5705_PLUS)) {
5423 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5424 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5425 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5428 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5429 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5430 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5431 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5432 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5434 if (tg3_flag(tp, NVRAM))
5435 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5438 static void tg3_dump_state(struct tg3 *tp)
5443 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
5445 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
5449 if (tg3_flag(tp, PCI_EXPRESS)) {
5450 /* Read up to but not including private PCI registers */
5451 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5452 regs[i / sizeof(u32)] = tr32(i);
5454 tg3_dump_legacy_regs(tp, regs);
5456 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5457 if (!regs[i + 0] && !regs[i + 1] &&
5458 !regs[i + 2] && !regs[i + 3])
5461 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5463 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5468 for (i = 0; i < tp->irq_cnt; i++) {
5469 struct tg3_napi *tnapi = &tp->napi[i];
5471 /* SW status block */
5473 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5475 tnapi->hw_status->status,
5476 tnapi->hw_status->status_tag,
5477 tnapi->hw_status->rx_jumbo_consumer,
5478 tnapi->hw_status->rx_consumer,
5479 tnapi->hw_status->rx_mini_consumer,
5480 tnapi->hw_status->idx[0].rx_producer,
5481 tnapi->hw_status->idx[0].tx_consumer);
5484 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
5486 tnapi->last_tag, tnapi->last_irq_tag,
5487 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
5489 tnapi->prodring.rx_std_prod_idx,
5490 tnapi->prodring.rx_std_cons_idx,
5491 tnapi->prodring.rx_jmb_prod_idx,
5492 tnapi->prodring.rx_jmb_cons_idx);
5496 /* This is called whenever we suspect that the system chipset is re-
5497 * ordering the sequence of MMIO to the tx send mailbox. The symptom
5498 * is bogus tx completions. We try to recover by setting the
5499 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
5502 static void tg3_tx_recover(struct tg3 *tp)
5504 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
5505 tp->write32_tx_mbox == tg3_write_indirect_mbox);
5507 netdev_warn(tp->dev,
5508 "The system may be re-ordering memory-mapped I/O "
5509 "cycles to the network device, attempting to recover. "
5510 "Please report the problem to the driver maintainer "
5511 "and include system chipset information.\n");
5513 spin_lock(&tp->lock);
5514 tg3_flag_set(tp, TX_RECOVERY_PENDING);
5515 spin_unlock(&tp->lock);
5518 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
5520 /* Tell compiler to fetch tx indices from memory. */
5522 return tnapi->tx_pending -
5523 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
5526 /* Tigon3 never reports partial packet sends. So we do not
5527 * need special logic to handle SKBs that have not had all
5528 * of their frags sent yet, like SunGEM does.
5530 static void tg3_tx(struct tg3_napi *tnapi)
5532 struct tg3 *tp = tnapi->tp;
5533 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
5534 u32 sw_idx = tnapi->tx_cons;
5535 struct netdev_queue *txq;
5536 int index = tnapi - tp->napi;
5537 unsigned int pkts_compl = 0, bytes_compl = 0;
5539 if (tg3_flag(tp, ENABLE_TSS))
5542 txq = netdev_get_tx_queue(tp->dev, index);
5544 while (sw_idx != hw_idx) {
5545 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
5546 struct sk_buff *skb = ri->skb;
5549 if (unlikely(skb == NULL)) {
5554 pci_unmap_single(tp->pdev,
5555 dma_unmap_addr(ri, mapping),
5561 while (ri->fragmented) {
5562 ri->fragmented = false;
5563 sw_idx = NEXT_TX(sw_idx);
5564 ri = &tnapi->tx_buffers[sw_idx];
5567 sw_idx = NEXT_TX(sw_idx);
5569 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5570 ri = &tnapi->tx_buffers[sw_idx];
5571 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
5574 pci_unmap_page(tp->pdev,
5575 dma_unmap_addr(ri, mapping),
5576 skb_frag_size(&skb_shinfo(skb)->frags[i]),
5579 while (ri->fragmented) {
5580 ri->fragmented = false;
5581 sw_idx = NEXT_TX(sw_idx);
5582 ri = &tnapi->tx_buffers[sw_idx];
5585 sw_idx = NEXT_TX(sw_idx);
5589 bytes_compl += skb->len;
5593 if (unlikely(tx_bug)) {
5599 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
5601 tnapi->tx_cons = sw_idx;
5603 /* Need to make the tx_cons update visible to tg3_start_xmit()
5604 * before checking for netif_queue_stopped(). Without the
5605 * memory barrier, there is a small possibility that tg3_start_xmit()
5606 * will miss it and cause the queue to be stopped forever.
5610 if (unlikely(netif_tx_queue_stopped(txq) &&
5611 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
5612 __netif_tx_lock(txq, smp_processor_id());
5613 if (netif_tx_queue_stopped(txq) &&
5614 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
5615 netif_tx_wake_queue(txq);
5616 __netif_tx_unlock(txq);
5620 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
5625 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
5626 map_sz, PCI_DMA_FROMDEVICE);
5631 /* Returns size of skb allocated or < 0 on error.
5633 * We only need to fill in the address because the other members
5634 * of the RX descriptor are invariant, see tg3_init_rings.
5636 * Note the purposeful assymetry of cpu vs. chip accesses. For
5637 * posting buffers we only dirty the first cache line of the RX
5638 * descriptor (containing the address). Whereas for the RX status
5639 * buffers the cpu only reads the last cacheline of the RX descriptor
5640 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
5642 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
5643 u32 opaque_key, u32 dest_idx_unmasked)
5645 struct tg3_rx_buffer_desc *desc;
5646 struct ring_info *map;
5649 int skb_size, data_size, dest_idx;
5651 switch (opaque_key) {
5652 case RXD_OPAQUE_RING_STD:
5653 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5654 desc = &tpr->rx_std[dest_idx];
5655 map = &tpr->rx_std_buffers[dest_idx];
5656 data_size = tp->rx_pkt_map_sz;
5659 case RXD_OPAQUE_RING_JUMBO:
5660 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5661 desc = &tpr->rx_jmb[dest_idx].std;
5662 map = &tpr->rx_jmb_buffers[dest_idx];
5663 data_size = TG3_RX_JMB_MAP_SZ;
5670 /* Do not overwrite any of the map or rp information
5671 * until we are sure we can commit to a new buffer.
5673 * Callers depend upon this behavior and assume that
5674 * we leave everything unchanged if we fail.
5676 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
5677 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5678 data = kmalloc(skb_size, GFP_ATOMIC);
5682 mapping = pci_map_single(tp->pdev,
5683 data + TG3_RX_OFFSET(tp),
5685 PCI_DMA_FROMDEVICE);
5686 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5692 dma_unmap_addr_set(map, mapping, mapping);
5694 desc->addr_hi = ((u64)mapping >> 32);
5695 desc->addr_lo = ((u64)mapping & 0xffffffff);
5700 /* We only need to move over in the address because the other
5701 * members of the RX descriptor are invariant. See notes above
5702 * tg3_alloc_rx_data for full details.
5704 static void tg3_recycle_rx(struct tg3_napi *tnapi,
5705 struct tg3_rx_prodring_set *dpr,
5706 u32 opaque_key, int src_idx,
5707 u32 dest_idx_unmasked)
5709 struct tg3 *tp = tnapi->tp;
5710 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
5711 struct ring_info *src_map, *dest_map;
5712 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
5715 switch (opaque_key) {
5716 case RXD_OPAQUE_RING_STD:
5717 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5718 dest_desc = &dpr->rx_std[dest_idx];
5719 dest_map = &dpr->rx_std_buffers[dest_idx];
5720 src_desc = &spr->rx_std[src_idx];
5721 src_map = &spr->rx_std_buffers[src_idx];
5724 case RXD_OPAQUE_RING_JUMBO:
5725 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5726 dest_desc = &dpr->rx_jmb[dest_idx].std;
5727 dest_map = &dpr->rx_jmb_buffers[dest_idx];
5728 src_desc = &spr->rx_jmb[src_idx].std;
5729 src_map = &spr->rx_jmb_buffers[src_idx];
5736 dest_map->data = src_map->data;
5737 dma_unmap_addr_set(dest_map, mapping,
5738 dma_unmap_addr(src_map, mapping));
5739 dest_desc->addr_hi = src_desc->addr_hi;
5740 dest_desc->addr_lo = src_desc->addr_lo;
5742 /* Ensure that the update to the skb happens after the physical
5743 * addresses have been transferred to the new BD location.
5747 src_map->data = NULL;
5750 /* The RX ring scheme is composed of multiple rings which post fresh
5751 * buffers to the chip, and one special ring the chip uses to report
5752 * status back to the host.
5754 * The special ring reports the status of received packets to the
5755 * host. The chip does not write into the original descriptor the
5756 * RX buffer was obtained from. The chip simply takes the original
5757 * descriptor as provided by the host, updates the status and length
5758 * field, then writes this into the next status ring entry.
5760 * Each ring the host uses to post buffers to the chip is described
5761 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
5762 * it is first placed into the on-chip ram. When the packet's length
5763 * is known, it walks down the TG3_BDINFO entries to select the ring.
5764 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5765 * which is within the range of the new packet's length is chosen.
5767 * The "separate ring for rx status" scheme may sound queer, but it makes
5768 * sense from a cache coherency perspective. If only the host writes
5769 * to the buffer post rings, and only the chip writes to the rx status
5770 * rings, then cache lines never move beyond shared-modified state.
5771 * If both the host and chip were to write into the same ring, cache line
5772 * eviction could occur since both entities want it in an exclusive state.
5774 static int tg3_rx(struct tg3_napi *tnapi, int budget)
5776 struct tg3 *tp = tnapi->tp;
5777 u32 work_mask, rx_std_posted = 0;
5778 u32 std_prod_idx, jmb_prod_idx;
5779 u32 sw_idx = tnapi->rx_rcb_ptr;
5782 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
5784 hw_idx = *(tnapi->rx_rcb_prod_idx);
5786 * We need to order the read of hw_idx and the read of
5787 * the opaque cookie.
5792 std_prod_idx = tpr->rx_std_prod_idx;
5793 jmb_prod_idx = tpr->rx_jmb_prod_idx;
5794 while (sw_idx != hw_idx && budget > 0) {
5795 struct ring_info *ri;
5796 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
5798 struct sk_buff *skb;
5799 dma_addr_t dma_addr;
5800 u32 opaque_key, desc_idx, *post_ptr;
5803 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5804 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5805 if (opaque_key == RXD_OPAQUE_RING_STD) {
5806 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
5807 dma_addr = dma_unmap_addr(ri, mapping);
5809 post_ptr = &std_prod_idx;
5811 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
5812 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
5813 dma_addr = dma_unmap_addr(ri, mapping);
5815 post_ptr = &jmb_prod_idx;
5817 goto next_pkt_nopost;
5819 work_mask |= opaque_key;
5821 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5822 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5824 tg3_recycle_rx(tnapi, tpr, opaque_key,
5825 desc_idx, *post_ptr);
5827 /* Other statistics kept track of by card. */
5832 prefetch(data + TG3_RX_OFFSET(tp));
5833 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5836 if (len > TG3_RX_COPY_THRESH(tp)) {
5839 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
5844 pci_unmap_single(tp->pdev, dma_addr, skb_size,
5845 PCI_DMA_FROMDEVICE);
5847 skb = build_skb(data, 0);
5850 goto drop_it_no_recycle;
5852 skb_reserve(skb, TG3_RX_OFFSET(tp));
5853 /* Ensure that the update to the data happens
5854 * after the usage of the old DMA mapping.
5861 tg3_recycle_rx(tnapi, tpr, opaque_key,
5862 desc_idx, *post_ptr);
5864 skb = netdev_alloc_skb(tp->dev,
5865 len + TG3_RAW_IP_ALIGN);
5867 goto drop_it_no_recycle;
5869 skb_reserve(skb, TG3_RAW_IP_ALIGN);
5870 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5872 data + TG3_RX_OFFSET(tp),
5874 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5878 if ((tp->dev->features & NETIF_F_RXCSUM) &&
5879 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
5880 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
5881 >> RXD_TCPCSUM_SHIFT) == 0xffff))
5882 skb->ip_summed = CHECKSUM_UNNECESSARY;
5884 skb_checksum_none_assert(skb);
5886 skb->protocol = eth_type_trans(skb, tp->dev);
5888 if (len > (tp->dev->mtu + ETH_HLEN) &&
5889 skb->protocol != htons(ETH_P_8021Q)) {
5891 goto drop_it_no_recycle;
5894 if (desc->type_flags & RXD_FLAG_VLAN &&
5895 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
5896 __vlan_hwaccel_put_tag(skb,
5897 desc->err_vlan & RXD_VLAN_MASK);
5899 napi_gro_receive(&tnapi->napi, skb);
5907 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
5908 tpr->rx_std_prod_idx = std_prod_idx &
5909 tp->rx_std_ring_mask;
5910 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5911 tpr->rx_std_prod_idx);
5912 work_mask &= ~RXD_OPAQUE_RING_STD;
5917 sw_idx &= tp->rx_ret_ring_mask;
5919 /* Refresh hw_idx to see if there is new work */
5920 if (sw_idx == hw_idx) {
5921 hw_idx = *(tnapi->rx_rcb_prod_idx);
5926 /* ACK the status ring. */
5927 tnapi->rx_rcb_ptr = sw_idx;
5928 tw32_rx_mbox(tnapi->consmbox, sw_idx);
5930 /* Refill RX ring(s). */
5931 if (!tg3_flag(tp, ENABLE_RSS)) {
5932 /* Sync BD data before updating mailbox */
5935 if (work_mask & RXD_OPAQUE_RING_STD) {
5936 tpr->rx_std_prod_idx = std_prod_idx &
5937 tp->rx_std_ring_mask;
5938 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5939 tpr->rx_std_prod_idx);
5941 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
5942 tpr->rx_jmb_prod_idx = jmb_prod_idx &
5943 tp->rx_jmb_ring_mask;
5944 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5945 tpr->rx_jmb_prod_idx);
5948 } else if (work_mask) {
5949 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5950 * updated before the producer indices can be updated.
5954 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5955 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5957 if (tnapi != &tp->napi[1]) {
5958 tp->rx_refill = true;
5959 napi_schedule(&tp->napi[1].napi);
5966 static void tg3_poll_link(struct tg3 *tp)
5968 /* handle link change and other phy events */
5969 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
5970 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5972 if (sblk->status & SD_STATUS_LINK_CHG) {
5973 sblk->status = SD_STATUS_UPDATED |
5974 (sblk->status & ~SD_STATUS_LINK_CHG);
5975 spin_lock(&tp->lock);
5976 if (tg3_flag(tp, USE_PHYLIB)) {
5978 (MAC_STATUS_SYNC_CHANGED |
5979 MAC_STATUS_CFG_CHANGED |
5980 MAC_STATUS_MI_COMPLETION |
5981 MAC_STATUS_LNKSTATE_CHANGED));
5984 tg3_setup_phy(tp, 0);
5985 spin_unlock(&tp->lock);
5990 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5991 struct tg3_rx_prodring_set *dpr,
5992 struct tg3_rx_prodring_set *spr)
5994 u32 si, di, cpycnt, src_prod_idx;
5998 src_prod_idx = spr->rx_std_prod_idx;
6000 /* Make sure updates to the rx_std_buffers[] entries and the
6001 * standard producer index are seen in the correct order.
6005 if (spr->rx_std_cons_idx == src_prod_idx)
6008 if (spr->rx_std_cons_idx < src_prod_idx)
6009 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
6011 cpycnt = tp->rx_std_ring_mask + 1 -
6012 spr->rx_std_cons_idx;
6014 cpycnt = min(cpycnt,
6015 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
6017 si = spr->rx_std_cons_idx;
6018 di = dpr->rx_std_prod_idx;
6020 for (i = di; i < di + cpycnt; i++) {
6021 if (dpr->rx_std_buffers[i].data) {
6031 /* Ensure that updates to the rx_std_buffers ring and the
6032 * shadowed hardware producer ring from tg3_recycle_skb() are
6033 * ordered correctly WRT the skb check above.
6037 memcpy(&dpr->rx_std_buffers[di],
6038 &spr->rx_std_buffers[si],
6039 cpycnt * sizeof(struct ring_info));
6041 for (i = 0; i < cpycnt; i++, di++, si++) {
6042 struct tg3_rx_buffer_desc *sbd, *dbd;
6043 sbd = &spr->rx_std[si];
6044 dbd = &dpr->rx_std[di];
6045 dbd->addr_hi = sbd->addr_hi;
6046 dbd->addr_lo = sbd->addr_lo;
6049 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
6050 tp->rx_std_ring_mask;
6051 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
6052 tp->rx_std_ring_mask;
6056 src_prod_idx = spr->rx_jmb_prod_idx;
6058 /* Make sure updates to the rx_jmb_buffers[] entries and
6059 * the jumbo producer index are seen in the correct order.
6063 if (spr->rx_jmb_cons_idx == src_prod_idx)
6066 if (spr->rx_jmb_cons_idx < src_prod_idx)
6067 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
6069 cpycnt = tp->rx_jmb_ring_mask + 1 -
6070 spr->rx_jmb_cons_idx;
6072 cpycnt = min(cpycnt,
6073 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
6075 si = spr->rx_jmb_cons_idx;
6076 di = dpr->rx_jmb_prod_idx;
6078 for (i = di; i < di + cpycnt; i++) {
6079 if (dpr->rx_jmb_buffers[i].data) {
6089 /* Ensure that updates to the rx_jmb_buffers ring and the
6090 * shadowed hardware producer ring from tg3_recycle_skb() are
6091 * ordered correctly WRT the skb check above.
6095 memcpy(&dpr->rx_jmb_buffers[di],
6096 &spr->rx_jmb_buffers[si],
6097 cpycnt * sizeof(struct ring_info));
6099 for (i = 0; i < cpycnt; i++, di++, si++) {
6100 struct tg3_rx_buffer_desc *sbd, *dbd;
6101 sbd = &spr->rx_jmb[si].std;
6102 dbd = &dpr->rx_jmb[di].std;
6103 dbd->addr_hi = sbd->addr_hi;
6104 dbd->addr_lo = sbd->addr_lo;
6107 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
6108 tp->rx_jmb_ring_mask;
6109 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
6110 tp->rx_jmb_ring_mask;
6116 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
6118 struct tg3 *tp = tnapi->tp;
6120 /* run TX completion thread */
6121 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
6123 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6127 /* run RX thread, within the bounds set by NAPI.
6128 * All RX "locking" is done by ensuring outside
6129 * code synchronizes with tg3->napi.poll()
6131 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
6132 work_done += tg3_rx(tnapi, budget - work_done);
6134 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
6135 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
6137 u32 std_prod_idx = dpr->rx_std_prod_idx;
6138 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
6140 tp->rx_refill = false;
6141 for (i = 1; i < tp->irq_cnt; i++)
6142 err |= tg3_rx_prodring_xfer(tp, dpr,
6143 &tp->napi[i].prodring);
6147 if (std_prod_idx != dpr->rx_std_prod_idx)
6148 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6149 dpr->rx_std_prod_idx);
6151 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
6152 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6153 dpr->rx_jmb_prod_idx);
6158 tw32_f(HOSTCC_MODE, tp->coal_now);
6164 static inline void tg3_reset_task_schedule(struct tg3 *tp)
6166 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
6167 schedule_work(&tp->reset_task);
6170 static inline void tg3_reset_task_cancel(struct tg3 *tp)
6172 cancel_work_sync(&tp->reset_task);
6173 tg3_flag_clear(tp, RESET_TASK_PENDING);
6174 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
6177 static int tg3_poll_msix(struct napi_struct *napi, int budget)
6179 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6180 struct tg3 *tp = tnapi->tp;
6182 struct tg3_hw_status *sblk = tnapi->hw_status;
6185 work_done = tg3_poll_work(tnapi, work_done, budget);
6187 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6190 if (unlikely(work_done >= budget))
6193 /* tp->last_tag is used in tg3_int_reenable() below
6194 * to tell the hw how much work has been processed,
6195 * so we must read it before checking for more work.
6197 tnapi->last_tag = sblk->status_tag;
6198 tnapi->last_irq_tag = tnapi->last_tag;
6201 /* check for RX/TX work to do */
6202 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
6203 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
6205 /* This test here is not race free, but will reduce
6206 * the number of interrupts by looping again.
6208 if (tnapi == &tp->napi[1] && tp->rx_refill)
6211 napi_complete(napi);
6212 /* Reenable interrupts. */
6213 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
6215 /* This test here is synchronized by napi_schedule()
6216 * and napi_complete() to close the race condition.
6218 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
6219 tw32(HOSTCC_MODE, tp->coalesce_mode |
6220 HOSTCC_MODE_ENABLE |
6231 /* work_done is guaranteed to be less than budget. */
6232 napi_complete(napi);
6233 tg3_reset_task_schedule(tp);
6237 static void tg3_process_error(struct tg3 *tp)
6240 bool real_error = false;
6242 if (tg3_flag(tp, ERROR_PROCESSED))
6245 /* Check Flow Attention register */
6246 val = tr32(HOSTCC_FLOW_ATTN);
6247 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
6248 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
6252 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
6253 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
6257 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
6258 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
6267 tg3_flag_set(tp, ERROR_PROCESSED);
6268 tg3_reset_task_schedule(tp);
6271 static int tg3_poll(struct napi_struct *napi, int budget)
6273 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6274 struct tg3 *tp = tnapi->tp;
6276 struct tg3_hw_status *sblk = tnapi->hw_status;
6279 if (sblk->status & SD_STATUS_ERROR)
6280 tg3_process_error(tp);
6284 work_done = tg3_poll_work(tnapi, work_done, budget);
6286 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6289 if (unlikely(work_done >= budget))
6292 if (tg3_flag(tp, TAGGED_STATUS)) {
6293 /* tp->last_tag is used in tg3_int_reenable() below
6294 * to tell the hw how much work has been processed,
6295 * so we must read it before checking for more work.
6297 tnapi->last_tag = sblk->status_tag;
6298 tnapi->last_irq_tag = tnapi->last_tag;
6301 sblk->status &= ~SD_STATUS_UPDATED;
6303 if (likely(!tg3_has_work(tnapi))) {
6304 napi_complete(napi);
6305 tg3_int_reenable(tnapi);
6313 /* work_done is guaranteed to be less than budget. */
6314 napi_complete(napi);
6315 tg3_reset_task_schedule(tp);
6319 static void tg3_napi_disable(struct tg3 *tp)
6323 for (i = tp->irq_cnt - 1; i >= 0; i--)
6324 napi_disable(&tp->napi[i].napi);
6327 static void tg3_napi_enable(struct tg3 *tp)
6331 for (i = 0; i < tp->irq_cnt; i++)
6332 napi_enable(&tp->napi[i].napi);
6335 static void tg3_napi_init(struct tg3 *tp)
6339 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
6340 for (i = 1; i < tp->irq_cnt; i++)
6341 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
6344 static void tg3_napi_fini(struct tg3 *tp)
6348 for (i = 0; i < tp->irq_cnt; i++)
6349 netif_napi_del(&tp->napi[i].napi);
6352 static inline void tg3_netif_stop(struct tg3 *tp)
6354 tp->dev->trans_start = jiffies; /* prevent tx timeout */
6355 tg3_napi_disable(tp);
6356 netif_tx_disable(tp->dev);
6359 static inline void tg3_netif_start(struct tg3 *tp)
6361 /* NOTE: unconditional netif_tx_wake_all_queues is only
6362 * appropriate so long as all callers are assured to
6363 * have free tx slots (such as after tg3_init_hw)
6365 netif_tx_wake_all_queues(tp->dev);
6367 tg3_napi_enable(tp);
6368 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
6369 tg3_enable_ints(tp);
6372 static void tg3_irq_quiesce(struct tg3 *tp)
6376 BUG_ON(tp->irq_sync);
6381 for (i = 0; i < tp->irq_cnt; i++)
6382 synchronize_irq(tp->napi[i].irq_vec);
6385 /* Fully shutdown all tg3 driver activity elsewhere in the system.
6386 * If irq_sync is non-zero, then the IRQ handler must be synchronized
6387 * with as well. Most of the time, this is not necessary except when
6388 * shutting down the device.
6390 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
6392 spin_lock_bh(&tp->lock);
6394 tg3_irq_quiesce(tp);
6397 static inline void tg3_full_unlock(struct tg3 *tp)
6399 spin_unlock_bh(&tp->lock);
6402 /* One-shot MSI handler - Chip automatically disables interrupt
6403 * after sending MSI so driver doesn't have to do it.
6405 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
6407 struct tg3_napi *tnapi = dev_id;
6408 struct tg3 *tp = tnapi->tp;
6410 prefetch(tnapi->hw_status);
6412 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6414 if (likely(!tg3_irq_sync(tp)))
6415 napi_schedule(&tnapi->napi);
6420 /* MSI ISR - No need to check for interrupt sharing and no need to
6421 * flush status block and interrupt mailbox. PCI ordering rules
6422 * guarantee that MSI will arrive after the status block.
6424 static irqreturn_t tg3_msi(int irq, void *dev_id)
6426 struct tg3_napi *tnapi = dev_id;
6427 struct tg3 *tp = tnapi->tp;
6429 prefetch(tnapi->hw_status);
6431 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6433 * Writing any value to intr-mbox-0 clears PCI INTA# and
6434 * chip-internal interrupt pending events.
6435 * Writing non-zero to intr-mbox-0 additional tells the
6436 * NIC to stop sending us irqs, engaging "in-intr-handler"
6439 tw32_mailbox(tnapi->int_mbox, 0x00000001);
6440 if (likely(!tg3_irq_sync(tp)))
6441 napi_schedule(&tnapi->napi);
6443 return IRQ_RETVAL(1);
6446 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
6448 struct tg3_napi *tnapi = dev_id;
6449 struct tg3 *tp = tnapi->tp;
6450 struct tg3_hw_status *sblk = tnapi->hw_status;
6451 unsigned int handled = 1;
6453 /* In INTx mode, it is possible for the interrupt to arrive at
6454 * the CPU before the status block posted prior to the interrupt.
6455 * Reading the PCI State register will confirm whether the
6456 * interrupt is ours and will flush the status block.
6458 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
6459 if (tg3_flag(tp, CHIP_RESETTING) ||
6460 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6467 * Writing any value to intr-mbox-0 clears PCI INTA# and
6468 * chip-internal interrupt pending events.
6469 * Writing non-zero to intr-mbox-0 additional tells the
6470 * NIC to stop sending us irqs, engaging "in-intr-handler"
6473 * Flush the mailbox to de-assert the IRQ immediately to prevent
6474 * spurious interrupts. The flush impacts performance but
6475 * excessive spurious interrupts can be worse in some cases.
6477 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6478 if (tg3_irq_sync(tp))
6480 sblk->status &= ~SD_STATUS_UPDATED;
6481 if (likely(tg3_has_work(tnapi))) {
6482 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6483 napi_schedule(&tnapi->napi);
6485 /* No work, shared interrupt perhaps? re-enable
6486 * interrupts, and flush that PCI write
6488 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
6492 return IRQ_RETVAL(handled);
6495 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
6497 struct tg3_napi *tnapi = dev_id;
6498 struct tg3 *tp = tnapi->tp;
6499 struct tg3_hw_status *sblk = tnapi->hw_status;
6500 unsigned int handled = 1;
6502 /* In INTx mode, it is possible for the interrupt to arrive at
6503 * the CPU before the status block posted prior to the interrupt.
6504 * Reading the PCI State register will confirm whether the
6505 * interrupt is ours and will flush the status block.
6507 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
6508 if (tg3_flag(tp, CHIP_RESETTING) ||
6509 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6516 * writing any value to intr-mbox-0 clears PCI INTA# and
6517 * chip-internal interrupt pending events.
6518 * writing non-zero to intr-mbox-0 additional tells the
6519 * NIC to stop sending us irqs, engaging "in-intr-handler"
6522 * Flush the mailbox to de-assert the IRQ immediately to prevent
6523 * spurious interrupts. The flush impacts performance but
6524 * excessive spurious interrupts can be worse in some cases.
6526 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6529 * In a shared interrupt configuration, sometimes other devices'
6530 * interrupts will scream. We record the current status tag here
6531 * so that the above check can report that the screaming interrupts
6532 * are unhandled. Eventually they will be silenced.
6534 tnapi->last_irq_tag = sblk->status_tag;
6536 if (tg3_irq_sync(tp))
6539 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6541 napi_schedule(&tnapi->napi);
6544 return IRQ_RETVAL(handled);
6547 /* ISR for interrupt test */
6548 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
6550 struct tg3_napi *tnapi = dev_id;
6551 struct tg3 *tp = tnapi->tp;
6552 struct tg3_hw_status *sblk = tnapi->hw_status;
6554 if ((sblk->status & SD_STATUS_UPDATED) ||
6555 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6556 tg3_disable_ints(tp);
6557 return IRQ_RETVAL(1);
6559 return IRQ_RETVAL(0);
6562 #ifdef CONFIG_NET_POLL_CONTROLLER
6563 static void tg3_poll_controller(struct net_device *dev)
6566 struct tg3 *tp = netdev_priv(dev);
6568 for (i = 0; i < tp->irq_cnt; i++)
6569 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
6573 static void tg3_tx_timeout(struct net_device *dev)
6575 struct tg3 *tp = netdev_priv(dev);
6577 if (netif_msg_tx_err(tp)) {
6578 netdev_err(dev, "transmit timed out, resetting\n");
6582 tg3_reset_task_schedule(tp);
6585 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
6586 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
6588 u32 base = (u32) mapping & 0xffffffff;
6590 return (base > 0xffffdcc0) && (base + len + 8 < base);
6593 /* Test for DMA addresses > 40-bit */
6594 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
6597 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6598 if (tg3_flag(tp, 40BIT_DMA_BUG))
6599 return ((u64) mapping + len) > DMA_BIT_MASK(40);
6606 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
6607 dma_addr_t mapping, u32 len, u32 flags,
6610 txbd->addr_hi = ((u64) mapping >> 32);
6611 txbd->addr_lo = ((u64) mapping & 0xffffffff);
6612 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
6613 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
6616 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
6617 dma_addr_t map, u32 len, u32 flags,
6620 struct tg3 *tp = tnapi->tp;
6623 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6626 if (tg3_4g_overflow_test(map, len))
6629 if (tg3_40bit_overflow_test(tp, map, len))
6632 if (tp->dma_limit) {
6633 u32 prvidx = *entry;
6634 u32 tmp_flag = flags & ~TXD_FLAG_END;
6635 while (len > tp->dma_limit && *budget) {
6636 u32 frag_len = tp->dma_limit;
6637 len -= tp->dma_limit;
6639 /* Avoid the 8byte DMA problem */
6641 len += tp->dma_limit / 2;
6642 frag_len = tp->dma_limit / 2;
6645 tnapi->tx_buffers[*entry].fragmented = true;
6647 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6648 frag_len, tmp_flag, mss, vlan);
6651 *entry = NEXT_TX(*entry);
6658 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6659 len, flags, mss, vlan);
6661 *entry = NEXT_TX(*entry);
6664 tnapi->tx_buffers[prvidx].fragmented = false;
6668 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6669 len, flags, mss, vlan);
6670 *entry = NEXT_TX(*entry);
6676 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
6679 struct sk_buff *skb;
6680 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
6685 pci_unmap_single(tnapi->tp->pdev,
6686 dma_unmap_addr(txb, mapping),
6690 while (txb->fragmented) {
6691 txb->fragmented = false;
6692 entry = NEXT_TX(entry);
6693 txb = &tnapi->tx_buffers[entry];
6696 for (i = 0; i <= last; i++) {
6697 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6699 entry = NEXT_TX(entry);
6700 txb = &tnapi->tx_buffers[entry];
6702 pci_unmap_page(tnapi->tp->pdev,
6703 dma_unmap_addr(txb, mapping),
6704 skb_frag_size(frag), PCI_DMA_TODEVICE);
6706 while (txb->fragmented) {
6707 txb->fragmented = false;
6708 entry = NEXT_TX(entry);
6709 txb = &tnapi->tx_buffers[entry];
6714 /* Workaround 4GB and 40-bit hardware DMA bugs. */
6715 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
6716 struct sk_buff **pskb,
6717 u32 *entry, u32 *budget,
6718 u32 base_flags, u32 mss, u32 vlan)
6720 struct tg3 *tp = tnapi->tp;
6721 struct sk_buff *new_skb, *skb = *pskb;
6722 dma_addr_t new_addr = 0;
6725 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
6726 new_skb = skb_copy(skb, GFP_ATOMIC);
6728 int more_headroom = 4 - ((unsigned long)skb->data & 3);
6730 new_skb = skb_copy_expand(skb,
6731 skb_headroom(skb) + more_headroom,
6732 skb_tailroom(skb), GFP_ATOMIC);
6738 /* New SKB is guaranteed to be linear. */
6739 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
6741 /* Make sure the mapping succeeded */
6742 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
6743 dev_kfree_skb(new_skb);
6746 u32 save_entry = *entry;
6748 base_flags |= TXD_FLAG_END;
6750 tnapi->tx_buffers[*entry].skb = new_skb;
6751 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
6754 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
6755 new_skb->len, base_flags,
6757 tg3_tx_skb_unmap(tnapi, save_entry, -1);
6758 dev_kfree_skb(new_skb);
6769 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
6771 /* Use GSO to workaround a rare TSO bug that may be triggered when the
6772 * TSO header is greater than 80 bytes.
6774 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
6776 struct sk_buff *segs, *nskb;
6777 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
6779 /* Estimate the number of fragments in the worst case */
6780 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
6781 netif_stop_queue(tp->dev);
6783 /* netif_tx_stop_queue() must be done before checking
6784 * checking tx index in tg3_tx_avail() below, because in
6785 * tg3_tx(), we update tx index before checking for
6786 * netif_tx_queue_stopped().
6789 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
6790 return NETDEV_TX_BUSY;
6792 netif_wake_queue(tp->dev);
6795 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
6797 goto tg3_tso_bug_end;
6803 tg3_start_xmit(nskb, tp->dev);
6809 return NETDEV_TX_OK;
6812 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6813 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
6815 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
6817 struct tg3 *tp = netdev_priv(dev);
6818 u32 len, entry, base_flags, mss, vlan = 0;
6820 int i = -1, would_hit_hwbug;
6822 struct tg3_napi *tnapi;
6823 struct netdev_queue *txq;
6826 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6827 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6828 if (tg3_flag(tp, ENABLE_TSS))
6831 budget = tg3_tx_avail(tnapi);
6833 /* We are running in BH disabled context with netif_tx_lock
6834 * and TX reclaim runs via tp->napi.poll inside of a software
6835 * interrupt. Furthermore, IRQ processing runs lockless so we have
6836 * no IRQ context deadlocks to worry about either. Rejoice!
6838 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
6839 if (!netif_tx_queue_stopped(txq)) {
6840 netif_tx_stop_queue(txq);
6842 /* This is a hard error, log it. */
6844 "BUG! Tx Ring full when queue awake!\n");
6846 return NETDEV_TX_BUSY;
6849 entry = tnapi->tx_prod;
6851 if (skb->ip_summed == CHECKSUM_PARTIAL)
6852 base_flags |= TXD_FLAG_TCPUDP_CSUM;
6854 mss = skb_shinfo(skb)->gso_size;
6857 u32 tcp_opt_len, hdr_len;
6859 if (skb_header_cloned(skb) &&
6860 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6864 tcp_opt_len = tcp_optlen(skb);
6866 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
6868 if (!skb_is_gso_v6(skb)) {
6870 iph->tot_len = htons(mss + hdr_len);
6873 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
6874 tg3_flag(tp, TSO_BUG))
6875 return tg3_tso_bug(tp, skb);
6877 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6878 TXD_FLAG_CPU_POST_DMA);
6880 if (tg3_flag(tp, HW_TSO_1) ||
6881 tg3_flag(tp, HW_TSO_2) ||
6882 tg3_flag(tp, HW_TSO_3)) {
6883 tcp_hdr(skb)->check = 0;
6884 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
6886 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6891 if (tg3_flag(tp, HW_TSO_3)) {
6892 mss |= (hdr_len & 0xc) << 12;
6894 base_flags |= 0x00000010;
6895 base_flags |= (hdr_len & 0x3e0) << 5;
6896 } else if (tg3_flag(tp, HW_TSO_2))
6897 mss |= hdr_len << 9;
6898 else if (tg3_flag(tp, HW_TSO_1) ||
6899 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6900 if (tcp_opt_len || iph->ihl > 5) {
6903 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6904 mss |= (tsflags << 11);
6907 if (tcp_opt_len || iph->ihl > 5) {
6910 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6911 base_flags |= tsflags << 12;
6916 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
6917 !mss && skb->len > VLAN_ETH_FRAME_LEN)
6918 base_flags |= TXD_FLAG_JMB_PKT;
6920 if (vlan_tx_tag_present(skb)) {
6921 base_flags |= TXD_FLAG_VLAN;
6922 vlan = vlan_tx_tag_get(skb);
6925 len = skb_headlen(skb);
6927 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6928 if (pci_dma_mapping_error(tp->pdev, mapping))
6932 tnapi->tx_buffers[entry].skb = skb;
6933 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6935 would_hit_hwbug = 0;
6937 if (tg3_flag(tp, 5701_DMA_BUG))
6938 would_hit_hwbug = 1;
6940 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
6941 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
6943 would_hit_hwbug = 1;
6944 } else if (skb_shinfo(skb)->nr_frags > 0) {
6947 if (!tg3_flag(tp, HW_TSO_1) &&
6948 !tg3_flag(tp, HW_TSO_2) &&
6949 !tg3_flag(tp, HW_TSO_3))
6952 /* Now loop through additional data
6953 * fragments, and queue them.
6955 last = skb_shinfo(skb)->nr_frags - 1;
6956 for (i = 0; i <= last; i++) {
6957 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6959 len = skb_frag_size(frag);
6960 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
6961 len, DMA_TO_DEVICE);
6963 tnapi->tx_buffers[entry].skb = NULL;
6964 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6966 if (dma_mapping_error(&tp->pdev->dev, mapping))
6970 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
6972 ((i == last) ? TXD_FLAG_END : 0),
6974 would_hit_hwbug = 1;
6980 if (would_hit_hwbug) {
6981 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
6983 /* If the workaround fails due to memory/mapping
6984 * failure, silently drop this packet.
6986 entry = tnapi->tx_prod;
6987 budget = tg3_tx_avail(tnapi);
6988 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
6989 base_flags, mss, vlan))
6993 skb_tx_timestamp(skb);
6994 netdev_tx_sent_queue(txq, skb->len);
6996 /* Sync BD data before updating mailbox */
6999 /* Packets are ready, update Tx producer idx local and on card. */
7000 tw32_tx_mbox(tnapi->prodmbox, entry);
7002 tnapi->tx_prod = entry;
7003 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
7004 netif_tx_stop_queue(txq);
7006 /* netif_tx_stop_queue() must be done before checking
7007 * checking tx index in tg3_tx_avail() below, because in
7008 * tg3_tx(), we update tx index before checking for
7009 * netif_tx_queue_stopped().
7012 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
7013 netif_tx_wake_queue(txq);
7017 return NETDEV_TX_OK;
7020 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
7021 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
7026 return NETDEV_TX_OK;
7029 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
7032 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
7033 MAC_MODE_PORT_MODE_MASK);
7035 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
7037 if (!tg3_flag(tp, 5705_PLUS))
7038 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7040 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
7041 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
7043 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7045 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
7047 if (tg3_flag(tp, 5705_PLUS) ||
7048 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
7049 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
7050 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
7053 tw32(MAC_MODE, tp->mac_mode);
7057 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
7059 u32 val, bmcr, mac_mode, ptest = 0;
7061 tg3_phy_toggle_apd(tp, false);
7062 tg3_phy_toggle_automdix(tp, 0);
7064 if (extlpbk && tg3_phy_set_extloopbk(tp))
7067 bmcr = BMCR_FULLDPLX;
7072 bmcr |= BMCR_SPEED100;
7076 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7078 bmcr |= BMCR_SPEED100;
7081 bmcr |= BMCR_SPEED1000;
7086 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
7087 tg3_readphy(tp, MII_CTRL1000, &val);
7088 val |= CTL1000_AS_MASTER |
7089 CTL1000_ENABLE_MASTER;
7090 tg3_writephy(tp, MII_CTRL1000, val);
7092 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
7093 MII_TG3_FET_PTEST_TRIM_2;
7094 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
7097 bmcr |= BMCR_LOOPBACK;
7099 tg3_writephy(tp, MII_BMCR, bmcr);
7101 /* The write needs to be flushed for the FETs */
7102 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7103 tg3_readphy(tp, MII_BMCR, &bmcr);
7107 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
7108 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
7109 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
7110 MII_TG3_FET_PTEST_FRC_TX_LINK |
7111 MII_TG3_FET_PTEST_FRC_TX_LOCK);
7113 /* The write needs to be flushed for the AC131 */
7114 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
7117 /* Reset to prevent losing 1st rx packet intermittently */
7118 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
7119 tg3_flag(tp, 5780_CLASS)) {
7120 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7122 tw32_f(MAC_RX_MODE, tp->rx_mode);
7125 mac_mode = tp->mac_mode &
7126 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
7127 if (speed == SPEED_1000)
7128 mac_mode |= MAC_MODE_PORT_MODE_GMII;
7130 mac_mode |= MAC_MODE_PORT_MODE_MII;
7132 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
7133 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
7135 if (masked_phy_id == TG3_PHY_ID_BCM5401)
7136 mac_mode &= ~MAC_MODE_LINK_POLARITY;
7137 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
7138 mac_mode |= MAC_MODE_LINK_POLARITY;
7140 tg3_writephy(tp, MII_TG3_EXT_CTRL,
7141 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
7144 tw32(MAC_MODE, mac_mode);
7150 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
7152 struct tg3 *tp = netdev_priv(dev);
7154 if (features & NETIF_F_LOOPBACK) {
7155 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
7158 spin_lock_bh(&tp->lock);
7159 tg3_mac_loopback(tp, true);
7160 netif_carrier_on(tp->dev);
7161 spin_unlock_bh(&tp->lock);
7162 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
7164 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
7167 spin_lock_bh(&tp->lock);
7168 tg3_mac_loopback(tp, false);
7169 /* Force link status check */
7170 tg3_setup_phy(tp, 1);
7171 spin_unlock_bh(&tp->lock);
7172 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
7176 static netdev_features_t tg3_fix_features(struct net_device *dev,
7177 netdev_features_t features)
7179 struct tg3 *tp = netdev_priv(dev);
7181 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
7182 features &= ~NETIF_F_ALL_TSO;
7187 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
7189 netdev_features_t changed = dev->features ^ features;
7191 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
7192 tg3_set_loopback(dev, features);
7197 static void tg3_rx_prodring_free(struct tg3 *tp,
7198 struct tg3_rx_prodring_set *tpr)
7202 if (tpr != &tp->napi[0].prodring) {
7203 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
7204 i = (i + 1) & tp->rx_std_ring_mask)
7205 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
7208 if (tg3_flag(tp, JUMBO_CAPABLE)) {
7209 for (i = tpr->rx_jmb_cons_idx;
7210 i != tpr->rx_jmb_prod_idx;
7211 i = (i + 1) & tp->rx_jmb_ring_mask) {
7212 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
7220 for (i = 0; i <= tp->rx_std_ring_mask; i++)
7221 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
7224 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7225 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
7226 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
7231 /* Initialize rx rings for packet processing.
7233 * The chip has been shut down and the driver detached from
7234 * the networking, so no interrupts or new tx packets will
7235 * end up in the driver. tp->{tx,}lock are held and thus
7238 static int tg3_rx_prodring_alloc(struct tg3 *tp,
7239 struct tg3_rx_prodring_set *tpr)
7241 u32 i, rx_pkt_dma_sz;
7243 tpr->rx_std_cons_idx = 0;
7244 tpr->rx_std_prod_idx = 0;
7245 tpr->rx_jmb_cons_idx = 0;
7246 tpr->rx_jmb_prod_idx = 0;
7248 if (tpr != &tp->napi[0].prodring) {
7249 memset(&tpr->rx_std_buffers[0], 0,
7250 TG3_RX_STD_BUFF_RING_SIZE(tp));
7251 if (tpr->rx_jmb_buffers)
7252 memset(&tpr->rx_jmb_buffers[0], 0,
7253 TG3_RX_JMB_BUFF_RING_SIZE(tp));
7257 /* Zero out all descriptors. */
7258 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
7260 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
7261 if (tg3_flag(tp, 5780_CLASS) &&
7262 tp->dev->mtu > ETH_DATA_LEN)
7263 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
7264 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7266 /* Initialize invariants of the rings, we only set this
7267 * stuff once. This works because the card does not
7268 * write into the rx buffer posting rings.
7270 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
7271 struct tg3_rx_buffer_desc *rxd;
7273 rxd = &tpr->rx_std[i];
7274 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
7275 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
7276 rxd->opaque = (RXD_OPAQUE_RING_STD |
7277 (i << RXD_OPAQUE_INDEX_SHIFT));
7280 /* Now allocate fresh SKBs for each rx ring. */
7281 for (i = 0; i < tp->rx_pending; i++) {
7282 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
7283 netdev_warn(tp->dev,
7284 "Using a smaller RX standard ring. Only "
7285 "%d out of %d buffers were allocated "
7286 "successfully\n", i, tp->rx_pending);
7294 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
7297 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
7299 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
7302 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
7303 struct tg3_rx_buffer_desc *rxd;
7305 rxd = &tpr->rx_jmb[i].std;
7306 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
7307 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
7309 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
7310 (i << RXD_OPAQUE_INDEX_SHIFT));
7313 for (i = 0; i < tp->rx_jumbo_pending; i++) {
7314 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
7315 netdev_warn(tp->dev,
7316 "Using a smaller RX jumbo ring. Only %d "
7317 "out of %d buffers were allocated "
7318 "successfully\n", i, tp->rx_jumbo_pending);
7321 tp->rx_jumbo_pending = i;
7330 tg3_rx_prodring_free(tp, tpr);
7334 static void tg3_rx_prodring_fini(struct tg3 *tp,
7335 struct tg3_rx_prodring_set *tpr)
7337 kfree(tpr->rx_std_buffers);
7338 tpr->rx_std_buffers = NULL;
7339 kfree(tpr->rx_jmb_buffers);
7340 tpr->rx_jmb_buffers = NULL;
7342 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
7343 tpr->rx_std, tpr->rx_std_mapping);
7347 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
7348 tpr->rx_jmb, tpr->rx_jmb_mapping);
7353 static int tg3_rx_prodring_init(struct tg3 *tp,
7354 struct tg3_rx_prodring_set *tpr)
7356 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
7358 if (!tpr->rx_std_buffers)
7361 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
7362 TG3_RX_STD_RING_BYTES(tp),
7363 &tpr->rx_std_mapping,
7368 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7369 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
7371 if (!tpr->rx_jmb_buffers)
7374 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
7375 TG3_RX_JMB_RING_BYTES(tp),
7376 &tpr->rx_jmb_mapping,
7385 tg3_rx_prodring_fini(tp, tpr);
7389 /* Free up pending packets in all rx/tx rings.
7391 * The chip has been shut down and the driver detached from
7392 * the networking, so no interrupts or new tx packets will
7393 * end up in the driver. tp->{tx,}lock is not held and we are not
7394 * in an interrupt context and thus may sleep.
7396 static void tg3_free_rings(struct tg3 *tp)
7400 for (j = 0; j < tp->irq_cnt; j++) {
7401 struct tg3_napi *tnapi = &tp->napi[j];
7403 tg3_rx_prodring_free(tp, &tnapi->prodring);
7405 if (!tnapi->tx_buffers)
7408 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
7409 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
7414 tg3_tx_skb_unmap(tnapi, i,
7415 skb_shinfo(skb)->nr_frags - 1);
7417 dev_kfree_skb_any(skb);
7419 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
7423 /* Initialize tx/rx rings for packet processing.
7425 * The chip has been shut down and the driver detached from
7426 * the networking, so no interrupts or new tx packets will
7427 * end up in the driver. tp->{tx,}lock are held and thus
7430 static int tg3_init_rings(struct tg3 *tp)
7434 /* Free up all the SKBs. */
7437 for (i = 0; i < tp->irq_cnt; i++) {
7438 struct tg3_napi *tnapi = &tp->napi[i];
7440 tnapi->last_tag = 0;
7441 tnapi->last_irq_tag = 0;
7442 tnapi->hw_status->status = 0;
7443 tnapi->hw_status->status_tag = 0;
7444 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7449 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
7451 tnapi->rx_rcb_ptr = 0;
7453 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7455 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
7465 * Must not be invoked with interrupt sources disabled and
7466 * the hardware shutdown down.
7468 static void tg3_free_consistent(struct tg3 *tp)
7472 for (i = 0; i < tp->irq_cnt; i++) {
7473 struct tg3_napi *tnapi = &tp->napi[i];
7475 if (tnapi->tx_ring) {
7476 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
7477 tnapi->tx_ring, tnapi->tx_desc_mapping);
7478 tnapi->tx_ring = NULL;
7481 kfree(tnapi->tx_buffers);
7482 tnapi->tx_buffers = NULL;
7484 if (tnapi->rx_rcb) {
7485 dma_free_coherent(&tp->pdev->dev,
7486 TG3_RX_RCB_RING_BYTES(tp),
7488 tnapi->rx_rcb_mapping);
7489 tnapi->rx_rcb = NULL;
7492 tg3_rx_prodring_fini(tp, &tnapi->prodring);
7494 if (tnapi->hw_status) {
7495 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
7497 tnapi->status_mapping);
7498 tnapi->hw_status = NULL;
7503 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
7504 tp->hw_stats, tp->stats_mapping);
7505 tp->hw_stats = NULL;
7510 * Must not be invoked with interrupt sources disabled and
7511 * the hardware shutdown down. Can sleep.
7513 static int tg3_alloc_consistent(struct tg3 *tp)
7517 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
7518 sizeof(struct tg3_hw_stats),
7524 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7526 for (i = 0; i < tp->irq_cnt; i++) {
7527 struct tg3_napi *tnapi = &tp->napi[i];
7528 struct tg3_hw_status *sblk;
7530 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
7532 &tnapi->status_mapping,
7534 if (!tnapi->hw_status)
7537 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7538 sblk = tnapi->hw_status;
7540 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
7543 /* If multivector TSS is enabled, vector 0 does not handle
7544 * tx interrupts. Don't allocate any resources for it.
7546 if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
7547 (i && tg3_flag(tp, ENABLE_TSS))) {
7548 tnapi->tx_buffers = kzalloc(
7549 sizeof(struct tg3_tx_ring_info) *
7550 TG3_TX_RING_SIZE, GFP_KERNEL);
7551 if (!tnapi->tx_buffers)
7554 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
7556 &tnapi->tx_desc_mapping,
7558 if (!tnapi->tx_ring)
7563 * When RSS is enabled, the status block format changes
7564 * slightly. The "rx_jumbo_consumer", "reserved",
7565 * and "rx_mini_consumer" members get mapped to the
7566 * other three rx return ring producer indexes.
7570 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
7573 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
7576 tnapi->rx_rcb_prod_idx = &sblk->reserved;
7579 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
7584 * If multivector RSS is enabled, vector 0 does not handle
7585 * rx or tx interrupts. Don't allocate any resources for it.
7587 if (!i && tg3_flag(tp, ENABLE_RSS))
7590 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
7591 TG3_RX_RCB_RING_BYTES(tp),
7592 &tnapi->rx_rcb_mapping,
7597 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7603 tg3_free_consistent(tp);
7607 #define MAX_WAIT_CNT 1000
7609 /* To stop a block, clear the enable bit and poll till it
7610 * clears. tp->lock is held.
7612 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
7617 if (tg3_flag(tp, 5705_PLUS)) {
7624 /* We can't enable/disable these bits of the
7625 * 5705/5750, just say success.
7638 for (i = 0; i < MAX_WAIT_CNT; i++) {
7641 if ((val & enable_bit) == 0)
7645 if (i == MAX_WAIT_CNT && !silent) {
7646 dev_err(&tp->pdev->dev,
7647 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
7655 /* tp->lock is held. */
7656 static int tg3_abort_hw(struct tg3 *tp, int silent)
7660 tg3_disable_ints(tp);
7662 tp->rx_mode &= ~RX_MODE_ENABLE;
7663 tw32_f(MAC_RX_MODE, tp->rx_mode);
7666 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
7667 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
7668 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
7669 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
7670 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
7671 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
7673 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
7674 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
7675 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
7676 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
7677 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
7678 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
7679 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
7681 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
7682 tw32_f(MAC_MODE, tp->mac_mode);
7685 tp->tx_mode &= ~TX_MODE_ENABLE;
7686 tw32_f(MAC_TX_MODE, tp->tx_mode);
7688 for (i = 0; i < MAX_WAIT_CNT; i++) {
7690 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
7693 if (i >= MAX_WAIT_CNT) {
7694 dev_err(&tp->pdev->dev,
7695 "%s timed out, TX_MODE_ENABLE will not clear "
7696 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
7700 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
7701 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
7702 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
7704 tw32(FTQ_RESET, 0xffffffff);
7705 tw32(FTQ_RESET, 0x00000000);
7707 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
7708 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
7710 for (i = 0; i < tp->irq_cnt; i++) {
7711 struct tg3_napi *tnapi = &tp->napi[i];
7712 if (tnapi->hw_status)
7713 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7719 /* Save PCI command register before chip reset */
7720 static void tg3_save_pci_state(struct tg3 *tp)
7722 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7725 /* Restore PCI state after chip reset */
7726 static void tg3_restore_pci_state(struct tg3 *tp)
7730 /* Re-enable indirect register accesses. */
7731 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7732 tp->misc_host_ctrl);
7734 /* Set MAX PCI retry to zero. */
7735 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7736 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7737 tg3_flag(tp, PCIX_MODE))
7738 val |= PCISTATE_RETRY_SAME_DMA;
7739 /* Allow reads and writes to the APE register and memory space. */
7740 if (tg3_flag(tp, ENABLE_APE))
7741 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7742 PCISTATE_ALLOW_APE_SHMEM_WR |
7743 PCISTATE_ALLOW_APE_PSPACE_WR;
7744 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7746 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7748 if (!tg3_flag(tp, PCI_EXPRESS)) {
7749 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7750 tp->pci_cacheline_sz);
7751 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7755 /* Make sure PCI-X relaxed ordering bit is clear. */
7756 if (tg3_flag(tp, PCIX_MODE)) {
7759 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7761 pcix_cmd &= ~PCI_X_CMD_ERO;
7762 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7766 if (tg3_flag(tp, 5780_CLASS)) {
7768 /* Chip reset on 5780 will reset MSI enable bit,
7769 * so need to restore it.
7771 if (tg3_flag(tp, USING_MSI)) {
7774 pci_read_config_word(tp->pdev,
7775 tp->msi_cap + PCI_MSI_FLAGS,
7777 pci_write_config_word(tp->pdev,
7778 tp->msi_cap + PCI_MSI_FLAGS,
7779 ctrl | PCI_MSI_FLAGS_ENABLE);
7780 val = tr32(MSGINT_MODE);
7781 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7786 /* tp->lock is held. */
7787 static int tg3_chip_reset(struct tg3 *tp)
7790 void (*write_op)(struct tg3 *, u32, u32);
7795 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7797 /* No matching tg3_nvram_unlock() after this because
7798 * chip reset below will undo the nvram lock.
7800 tp->nvram_lock_cnt = 0;
7802 /* GRC_MISC_CFG core clock reset will clear the memory
7803 * enable bit in PCI register 4 and the MSI enable bit
7804 * on some chips, so we save relevant registers here.
7806 tg3_save_pci_state(tp);
7808 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7809 tg3_flag(tp, 5755_PLUS))
7810 tw32(GRC_FASTBOOT_PC, 0);
7813 * We must avoid the readl() that normally takes place.
7814 * It locks machines, causes machine checks, and other
7815 * fun things. So, temporarily disable the 5701
7816 * hardware workaround, while we do the reset.
7818 write_op = tp->write32;
7819 if (write_op == tg3_write_flush_reg32)
7820 tp->write32 = tg3_write32;
7822 /* Prevent the irq handler from reading or writing PCI registers
7823 * during chip reset when the memory enable bit in the PCI command
7824 * register may be cleared. The chip does not generate interrupt
7825 * at this time, but the irq handler may still be called due to irq
7826 * sharing or irqpoll.
7828 tg3_flag_set(tp, CHIP_RESETTING);
7829 for (i = 0; i < tp->irq_cnt; i++) {
7830 struct tg3_napi *tnapi = &tp->napi[i];
7831 if (tnapi->hw_status) {
7832 tnapi->hw_status->status = 0;
7833 tnapi->hw_status->status_tag = 0;
7835 tnapi->last_tag = 0;
7836 tnapi->last_irq_tag = 0;
7840 for (i = 0; i < tp->irq_cnt; i++)
7841 synchronize_irq(tp->napi[i].irq_vec);
7843 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7844 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7845 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7849 val = GRC_MISC_CFG_CORECLK_RESET;
7851 if (tg3_flag(tp, PCI_EXPRESS)) {
7852 /* Force PCIe 1.0a mode */
7853 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7854 !tg3_flag(tp, 57765_PLUS) &&
7855 tr32(TG3_PCIE_PHY_TSTCTL) ==
7856 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7857 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7859 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7860 tw32(GRC_MISC_CFG, (1 << 29));
7865 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7866 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7867 tw32(GRC_VCPU_EXT_CTRL,
7868 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7871 /* Manage gphy power for all CPMU absent PCIe devices. */
7872 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
7873 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7875 tw32(GRC_MISC_CFG, val);
7877 /* restore 5701 hardware bug workaround write method */
7878 tp->write32 = write_op;
7880 /* Unfortunately, we have to delay before the PCI read back.
7881 * Some 575X chips even will not respond to a PCI cfg access
7882 * when the reset command is given to the chip.
7884 * How do these hardware designers expect things to work
7885 * properly if the PCI write is posted for a long period
7886 * of time? It is always necessary to have some method by
7887 * which a register read back can occur to push the write
7888 * out which does the reset.
7890 * For most tg3 variants the trick below was working.
7895 /* Flush PCI posted writes. The normal MMIO registers
7896 * are inaccessible at this time so this is the only
7897 * way to make this reliably (actually, this is no longer
7898 * the case, see above). I tried to use indirect
7899 * register read/write but this upset some 5701 variants.
7901 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7905 if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
7908 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7912 /* Wait for link training to complete. */
7913 for (i = 0; i < 5000; i++)
7916 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7917 pci_write_config_dword(tp->pdev, 0xc4,
7918 cfg_val | (1 << 15));
7921 /* Clear the "no snoop" and "relaxed ordering" bits. */
7922 pci_read_config_word(tp->pdev,
7923 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7925 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7926 PCI_EXP_DEVCTL_NOSNOOP_EN);
7928 * Older PCIe devices only support the 128 byte
7929 * MPS setting. Enforce the restriction.
7931 if (!tg3_flag(tp, CPMU_PRESENT))
7932 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7933 pci_write_config_word(tp->pdev,
7934 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7937 /* Clear error status */
7938 pci_write_config_word(tp->pdev,
7939 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
7940 PCI_EXP_DEVSTA_CED |
7941 PCI_EXP_DEVSTA_NFED |
7942 PCI_EXP_DEVSTA_FED |
7943 PCI_EXP_DEVSTA_URD);
7946 tg3_restore_pci_state(tp);
7948 tg3_flag_clear(tp, CHIP_RESETTING);
7949 tg3_flag_clear(tp, ERROR_PROCESSED);
7952 if (tg3_flag(tp, 5780_CLASS))
7953 val = tr32(MEMARB_MODE);
7954 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7956 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7958 tw32(0x5000, 0x400);
7961 tw32(GRC_MODE, tp->grc_mode);
7963 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7966 tw32(0xc4, val | (1 << 15));
7969 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7970 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7971 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7972 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7973 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7974 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7977 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7978 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7980 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7981 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7986 tw32_f(MAC_MODE, val);
7989 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7991 err = tg3_poll_fw(tp);
7997 if (tg3_flag(tp, PCI_EXPRESS) &&
7998 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7999 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
8000 !tg3_flag(tp, 57765_PLUS)) {
8003 tw32(0x7c00, val | (1 << 25));
8006 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8007 val = tr32(TG3_CPMU_CLCK_ORIDE);
8008 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8011 /* Reprobe ASF enable state. */
8012 tg3_flag_clear(tp, ENABLE_ASF);
8013 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
8014 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8015 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8018 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8019 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
8020 tg3_flag_set(tp, ENABLE_ASF);
8021 tp->last_event_jiffies = jiffies;
8022 if (tg3_flag(tp, 5750_PLUS))
8023 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
8030 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
8031 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
8033 /* tp->lock is held. */
8034 static int tg3_halt(struct tg3 *tp, int kind, int silent)
8040 tg3_write_sig_pre_reset(tp, kind);
8042 tg3_abort_hw(tp, silent);
8043 err = tg3_chip_reset(tp);
8045 __tg3_set_mac_addr(tp, 0);
8047 tg3_write_sig_legacy(tp, kind);
8048 tg3_write_sig_post_reset(tp, kind);
8051 /* Save the stats across chip resets... */
8052 tg3_get_nstats(tp, &tp->net_stats_prev);
8053 tg3_get_estats(tp, &tp->estats_prev);
8055 /* And make sure the next sample is new data */
8056 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
8065 static int tg3_set_mac_addr(struct net_device *dev, void *p)
8067 struct tg3 *tp = netdev_priv(dev);
8068 struct sockaddr *addr = p;
8069 int err = 0, skip_mac_1 = 0;
8071 if (!is_valid_ether_addr(addr->sa_data))
8072 return -EADDRNOTAVAIL;
8074 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
8076 if (!netif_running(dev))
8079 if (tg3_flag(tp, ENABLE_ASF)) {
8080 u32 addr0_high, addr0_low, addr1_high, addr1_low;
8082 addr0_high = tr32(MAC_ADDR_0_HIGH);
8083 addr0_low = tr32(MAC_ADDR_0_LOW);
8084 addr1_high = tr32(MAC_ADDR_1_HIGH);
8085 addr1_low = tr32(MAC_ADDR_1_LOW);
8087 /* Skip MAC addr 1 if ASF is using it. */
8088 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
8089 !(addr1_high == 0 && addr1_low == 0))
8092 spin_lock_bh(&tp->lock);
8093 __tg3_set_mac_addr(tp, skip_mac_1);
8094 spin_unlock_bh(&tp->lock);
8099 /* tp->lock is held. */
8100 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
8101 dma_addr_t mapping, u32 maxlen_flags,
8105 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
8106 ((u64) mapping >> 32));
8108 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
8109 ((u64) mapping & 0xffffffff));
8111 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
8114 if (!tg3_flag(tp, 5705_PLUS))
8116 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
8120 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
8124 if (!tg3_flag(tp, ENABLE_TSS)) {
8125 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
8126 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
8127 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
8129 tw32(HOSTCC_TXCOL_TICKS, 0);
8130 tw32(HOSTCC_TXMAX_FRAMES, 0);
8131 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
8134 if (!tg3_flag(tp, ENABLE_RSS)) {
8135 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
8136 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
8137 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
8139 tw32(HOSTCC_RXCOL_TICKS, 0);
8140 tw32(HOSTCC_RXMAX_FRAMES, 0);
8141 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
8144 if (!tg3_flag(tp, 5705_PLUS)) {
8145 u32 val = ec->stats_block_coalesce_usecs;
8147 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
8148 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
8150 if (!netif_carrier_ok(tp->dev))
8153 tw32(HOSTCC_STAT_COAL_TICKS, val);
8156 for (i = 0; i < tp->irq_cnt - 1; i++) {
8159 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
8160 tw32(reg, ec->rx_coalesce_usecs);
8161 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
8162 tw32(reg, ec->rx_max_coalesced_frames);
8163 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
8164 tw32(reg, ec->rx_max_coalesced_frames_irq);
8166 if (tg3_flag(tp, ENABLE_TSS)) {
8167 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
8168 tw32(reg, ec->tx_coalesce_usecs);
8169 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
8170 tw32(reg, ec->tx_max_coalesced_frames);
8171 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
8172 tw32(reg, ec->tx_max_coalesced_frames_irq);
8176 for (; i < tp->irq_max - 1; i++) {
8177 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
8178 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
8179 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8181 if (tg3_flag(tp, ENABLE_TSS)) {
8182 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
8183 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
8184 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8189 /* tp->lock is held. */
8190 static void tg3_rings_reset(struct tg3 *tp)
8193 u32 stblk, txrcb, rxrcb, limit;
8194 struct tg3_napi *tnapi = &tp->napi[0];
8196 /* Disable all transmit rings but the first. */
8197 if (!tg3_flag(tp, 5705_PLUS))
8198 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
8199 else if (tg3_flag(tp, 5717_PLUS))
8200 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
8201 else if (tg3_flag(tp, 57765_CLASS))
8202 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
8204 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8206 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8207 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
8208 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
8209 BDINFO_FLAGS_DISABLED);
8212 /* Disable all receive return rings but the first. */
8213 if (tg3_flag(tp, 5717_PLUS))
8214 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
8215 else if (!tg3_flag(tp, 5705_PLUS))
8216 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
8217 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8218 tg3_flag(tp, 57765_CLASS))
8219 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
8221 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8223 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8224 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
8225 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
8226 BDINFO_FLAGS_DISABLED);
8228 /* Disable interrupts */
8229 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
8230 tp->napi[0].chk_msi_cnt = 0;
8231 tp->napi[0].last_rx_cons = 0;
8232 tp->napi[0].last_tx_cons = 0;
8234 /* Zero mailbox registers. */
8235 if (tg3_flag(tp, SUPPORT_MSIX)) {
8236 for (i = 1; i < tp->irq_max; i++) {
8237 tp->napi[i].tx_prod = 0;
8238 tp->napi[i].tx_cons = 0;
8239 if (tg3_flag(tp, ENABLE_TSS))
8240 tw32_mailbox(tp->napi[i].prodmbox, 0);
8241 tw32_rx_mbox(tp->napi[i].consmbox, 0);
8242 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
8243 tp->napi[i].chk_msi_cnt = 0;
8244 tp->napi[i].last_rx_cons = 0;
8245 tp->napi[i].last_tx_cons = 0;
8247 if (!tg3_flag(tp, ENABLE_TSS))
8248 tw32_mailbox(tp->napi[0].prodmbox, 0);
8250 tp->napi[0].tx_prod = 0;
8251 tp->napi[0].tx_cons = 0;
8252 tw32_mailbox(tp->napi[0].prodmbox, 0);
8253 tw32_rx_mbox(tp->napi[0].consmbox, 0);
8256 /* Make sure the NIC-based send BD rings are disabled. */
8257 if (!tg3_flag(tp, 5705_PLUS)) {
8258 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
8259 for (i = 0; i < 16; i++)
8260 tw32_tx_mbox(mbox + i * 8, 0);
8263 txrcb = NIC_SRAM_SEND_RCB;
8264 rxrcb = NIC_SRAM_RCV_RET_RCB;
8266 /* Clear status block in ram. */
8267 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8269 /* Set status block DMA address */
8270 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8271 ((u64) tnapi->status_mapping >> 32));
8272 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8273 ((u64) tnapi->status_mapping & 0xffffffff));
8275 if (tnapi->tx_ring) {
8276 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8277 (TG3_TX_RING_SIZE <<
8278 BDINFO_FLAGS_MAXLEN_SHIFT),
8279 NIC_SRAM_TX_BUFFER_DESC);
8280 txrcb += TG3_BDINFO_SIZE;
8283 if (tnapi->rx_rcb) {
8284 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8285 (tp->rx_ret_ring_mask + 1) <<
8286 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
8287 rxrcb += TG3_BDINFO_SIZE;
8290 stblk = HOSTCC_STATBLCK_RING1;
8292 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
8293 u64 mapping = (u64)tnapi->status_mapping;
8294 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
8295 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
8297 /* Clear status block in ram. */
8298 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8300 if (tnapi->tx_ring) {
8301 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8302 (TG3_TX_RING_SIZE <<
8303 BDINFO_FLAGS_MAXLEN_SHIFT),
8304 NIC_SRAM_TX_BUFFER_DESC);
8305 txrcb += TG3_BDINFO_SIZE;
8308 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8309 ((tp->rx_ret_ring_mask + 1) <<
8310 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
8313 rxrcb += TG3_BDINFO_SIZE;
8317 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
8319 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
8321 if (!tg3_flag(tp, 5750_PLUS) ||
8322 tg3_flag(tp, 5780_CLASS) ||
8323 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8324 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
8325 tg3_flag(tp, 57765_PLUS))
8326 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
8327 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8328 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8329 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
8331 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
8333 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
8334 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
8336 val = min(nic_rep_thresh, host_rep_thresh);
8337 tw32(RCVBDI_STD_THRESH, val);
8339 if (tg3_flag(tp, 57765_PLUS))
8340 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8342 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8345 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
8347 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8349 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8350 tw32(RCVBDI_JUMBO_THRESH, val);
8352 if (tg3_flag(tp, 57765_PLUS))
8353 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8356 static inline u32 calc_crc(unsigned char *buf, int len)
8364 for (j = 0; j < len; j++) {
8367 for (k = 0; k < 8; k++) {
8380 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8382 /* accept or reject all multicast frames */
8383 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8384 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8385 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8386 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8389 static void __tg3_set_rx_mode(struct net_device *dev)
8391 struct tg3 *tp = netdev_priv(dev);
8394 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8395 RX_MODE_KEEP_VLAN_TAG);
8397 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
8398 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8401 if (!tg3_flag(tp, ENABLE_ASF))
8402 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8405 if (dev->flags & IFF_PROMISC) {
8406 /* Promiscuous mode. */
8407 rx_mode |= RX_MODE_PROMISC;
8408 } else if (dev->flags & IFF_ALLMULTI) {
8409 /* Accept all multicast. */
8410 tg3_set_multi(tp, 1);
8411 } else if (netdev_mc_empty(dev)) {
8412 /* Reject all multicast. */
8413 tg3_set_multi(tp, 0);
8415 /* Accept one or more multicast(s). */
8416 struct netdev_hw_addr *ha;
8417 u32 mc_filter[4] = { 0, };
8422 netdev_for_each_mc_addr(ha, dev) {
8423 crc = calc_crc(ha->addr, ETH_ALEN);
8425 regidx = (bit & 0x60) >> 5;
8427 mc_filter[regidx] |= (1 << bit);
8430 tw32(MAC_HASH_REG_0, mc_filter[0]);
8431 tw32(MAC_HASH_REG_1, mc_filter[1]);
8432 tw32(MAC_HASH_REG_2, mc_filter[2]);
8433 tw32(MAC_HASH_REG_3, mc_filter[3]);
8436 if (rx_mode != tp->rx_mode) {
8437 tp->rx_mode = rx_mode;
8438 tw32_f(MAC_RX_MODE, rx_mode);
8443 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp)
8447 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
8448 tp->rss_ind_tbl[i] =
8449 ethtool_rxfh_indir_default(i, tp->irq_cnt - 1);
8452 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
8456 if (!tg3_flag(tp, SUPPORT_MSIX))
8459 if (tp->irq_cnt <= 2) {
8460 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
8464 /* Validate table against current IRQ count */
8465 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8466 if (tp->rss_ind_tbl[i] >= tp->irq_cnt - 1)
8470 if (i != TG3_RSS_INDIR_TBL_SIZE)
8471 tg3_rss_init_dflt_indir_tbl(tp);
8474 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
8477 u32 reg = MAC_RSS_INDIR_TBL_0;
8479 while (i < TG3_RSS_INDIR_TBL_SIZE) {
8480 u32 val = tp->rss_ind_tbl[i];
8482 for (; i % 8; i++) {
8484 val |= tp->rss_ind_tbl[i];
8491 /* tp->lock is held. */
8492 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8494 u32 val, rdmac_mode;
8496 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
8498 tg3_disable_ints(tp);
8502 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8504 if (tg3_flag(tp, INIT_COMPLETE))
8505 tg3_abort_hw(tp, 1);
8507 /* Enable MAC control of LPI */
8508 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
8509 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
8510 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
8511 TG3_CPMU_EEE_LNKIDL_UART_IDL);
8513 tw32_f(TG3_CPMU_EEE_CTRL,
8514 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
8516 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
8517 TG3_CPMU_EEEMD_LPI_IN_TX |
8518 TG3_CPMU_EEEMD_LPI_IN_RX |
8519 TG3_CPMU_EEEMD_EEE_ENABLE;
8521 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8522 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8524 if (tg3_flag(tp, ENABLE_APE))
8525 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8527 tw32_f(TG3_CPMU_EEE_MODE, val);
8529 tw32_f(TG3_CPMU_EEE_DBTMR1,
8530 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
8531 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
8533 tw32_f(TG3_CPMU_EEE_DBTMR2,
8534 TG3_CPMU_DBTMR2_APE_TX_2047US |
8535 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
8541 err = tg3_chip_reset(tp);
8545 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8547 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
8548 val = tr32(TG3_CPMU_CTRL);
8549 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8550 tw32(TG3_CPMU_CTRL, val);
8552 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8553 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8554 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8555 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8557 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8558 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8559 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8560 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8562 val = tr32(TG3_CPMU_HST_ACC);
8563 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8564 val |= CPMU_HST_ACC_MACCLK_6_25;
8565 tw32(TG3_CPMU_HST_ACC, val);
8568 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8569 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8570 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8571 PCIE_PWR_MGMT_L1_THRESH_4MS;
8572 tw32(PCIE_PWR_MGMT_THRESH, val);
8574 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8575 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8577 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
8579 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8580 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8583 if (tg3_flag(tp, L1PLLPD_EN)) {
8584 u32 grc_mode = tr32(GRC_MODE);
8586 /* Access the lower 1K of PL PCIE block registers. */
8587 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8588 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8590 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8591 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8592 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8594 tw32(GRC_MODE, grc_mode);
8597 if (tg3_flag(tp, 57765_CLASS)) {
8598 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8599 u32 grc_mode = tr32(GRC_MODE);
8601 /* Access the lower 1K of PL PCIE block registers. */
8602 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8603 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8605 val = tr32(TG3_PCIE_TLDLPL_PORT +
8606 TG3_PCIE_PL_LO_PHYCTL5);
8607 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8608 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
8610 tw32(GRC_MODE, grc_mode);
8613 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
8614 u32 grc_mode = tr32(GRC_MODE);
8616 /* Access the lower 1K of DL PCIE block registers. */
8617 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8618 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8620 val = tr32(TG3_PCIE_TLDLPL_PORT +
8621 TG3_PCIE_DL_LO_FTSMAX);
8622 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8623 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8624 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8626 tw32(GRC_MODE, grc_mode);
8629 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8630 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8631 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8632 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8635 /* This works around an issue with Athlon chipsets on
8636 * B3 tigon3 silicon. This bit has no effect on any
8637 * other revision. But do not set this on PCI Express
8638 * chips and don't even touch the clocks if the CPMU is present.
8640 if (!tg3_flag(tp, CPMU_PRESENT)) {
8641 if (!tg3_flag(tp, PCI_EXPRESS))
8642 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8643 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8646 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8647 tg3_flag(tp, PCIX_MODE)) {
8648 val = tr32(TG3PCI_PCISTATE);
8649 val |= PCISTATE_RETRY_SAME_DMA;
8650 tw32(TG3PCI_PCISTATE, val);
8653 if (tg3_flag(tp, ENABLE_APE)) {
8654 /* Allow reads and writes to the
8655 * APE register and memory space.
8657 val = tr32(TG3PCI_PCISTATE);
8658 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8659 PCISTATE_ALLOW_APE_SHMEM_WR |
8660 PCISTATE_ALLOW_APE_PSPACE_WR;
8661 tw32(TG3PCI_PCISTATE, val);
8664 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8665 /* Enable some hw fixes. */
8666 val = tr32(TG3PCI_MSI_DATA);
8667 val |= (1 << 26) | (1 << 28) | (1 << 29);
8668 tw32(TG3PCI_MSI_DATA, val);
8671 /* Descriptor ring init may make accesses to the
8672 * NIC SRAM area to setup the TX descriptors, so we
8673 * can only do this after the hardware has been
8674 * successfully reset.
8676 err = tg3_init_rings(tp);
8680 if (tg3_flag(tp, 57765_PLUS)) {
8681 val = tr32(TG3PCI_DMA_RW_CTRL) &
8682 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8683 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8684 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8685 if (!tg3_flag(tp, 57765_CLASS) &&
8686 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8687 val |= DMA_RWCTRL_TAGGED_STAT_WA;
8688 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8689 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8690 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8691 /* This value is determined during the probe time DMA
8692 * engine test, tg3_test_dma.
8694 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8697 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8698 GRC_MODE_4X_NIC_SEND_RINGS |
8699 GRC_MODE_NO_TX_PHDR_CSUM |
8700 GRC_MODE_NO_RX_PHDR_CSUM);
8701 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8703 /* Pseudo-header checksum is done by hardware logic and not
8704 * the offload processers, so make the chip do the pseudo-
8705 * header checksums on receive. For transmit it is more
8706 * convenient to do the pseudo-header checksum in software
8707 * as Linux does that on transmit for us in all cases.
8709 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8713 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8715 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8716 val = tr32(GRC_MISC_CFG);
8718 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8719 tw32(GRC_MISC_CFG, val);
8721 /* Initialize MBUF/DESC pool. */
8722 if (tg3_flag(tp, 5750_PLUS)) {
8724 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8725 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8726 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8727 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8729 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8730 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8731 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8732 } else if (tg3_flag(tp, TSO_CAPABLE)) {
8735 fw_len = tp->fw_len;
8736 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8737 tw32(BUFMGR_MB_POOL_ADDR,
8738 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8739 tw32(BUFMGR_MB_POOL_SIZE,
8740 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8743 if (tp->dev->mtu <= ETH_DATA_LEN) {
8744 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8745 tp->bufmgr_config.mbuf_read_dma_low_water);
8746 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8747 tp->bufmgr_config.mbuf_mac_rx_low_water);
8748 tw32(BUFMGR_MB_HIGH_WATER,
8749 tp->bufmgr_config.mbuf_high_water);
8751 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8752 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8753 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8754 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8755 tw32(BUFMGR_MB_HIGH_WATER,
8756 tp->bufmgr_config.mbuf_high_water_jumbo);
8758 tw32(BUFMGR_DMA_LOW_WATER,
8759 tp->bufmgr_config.dma_low_water);
8760 tw32(BUFMGR_DMA_HIGH_WATER,
8761 tp->bufmgr_config.dma_high_water);
8763 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8764 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8765 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8766 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8767 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8768 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8769 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
8770 tw32(BUFMGR_MODE, val);
8771 for (i = 0; i < 2000; i++) {
8772 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8777 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8781 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8782 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8784 tg3_setup_rxbd_thresholds(tp);
8786 /* Initialize TG3_BDINFO's at:
8787 * RCVDBDI_STD_BD: standard eth size rx ring
8788 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8789 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8792 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8793 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8794 * ring attribute flags
8795 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8797 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8798 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8800 * The size of each ring is fixed in the firmware, but the location is
8803 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8804 ((u64) tpr->rx_std_mapping >> 32));
8805 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8806 ((u64) tpr->rx_std_mapping & 0xffffffff));
8807 if (!tg3_flag(tp, 5717_PLUS))
8808 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8809 NIC_SRAM_RX_BUFFER_DESC);
8811 /* Disable the mini ring */
8812 if (!tg3_flag(tp, 5705_PLUS))
8813 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8814 BDINFO_FLAGS_DISABLED);
8816 /* Program the jumbo buffer descriptor ring control
8817 * blocks on those devices that have them.
8819 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8820 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
8822 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
8823 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8824 ((u64) tpr->rx_jmb_mapping >> 32));
8825 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8826 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8827 val = TG3_RX_JMB_RING_SIZE(tp) <<
8828 BDINFO_FLAGS_MAXLEN_SHIFT;
8829 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8830 val | BDINFO_FLAGS_USE_EXT_RECV);
8831 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
8832 tg3_flag(tp, 57765_CLASS))
8833 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8834 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8836 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8837 BDINFO_FLAGS_DISABLED);
8840 if (tg3_flag(tp, 57765_PLUS)) {
8841 val = TG3_RX_STD_RING_SIZE(tp);
8842 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8843 val |= (TG3_RX_STD_DMA_SZ << 2);
8845 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8847 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8849 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8851 tpr->rx_std_prod_idx = tp->rx_pending;
8852 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8854 tpr->rx_jmb_prod_idx =
8855 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
8856 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8858 tg3_rings_reset(tp);
8860 /* Initialize MAC address and backoff seed. */
8861 __tg3_set_mac_addr(tp, 0);
8863 /* MTU + ethernet header + FCS + optional VLAN tag */
8864 tw32(MAC_RX_MTU_SIZE,
8865 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8867 /* The slot time is changed by tg3_setup_phy if we
8868 * run at gigabit with half duplex.
8870 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8871 (6 << TX_LENGTHS_IPG_SHIFT) |
8872 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8875 val |= tr32(MAC_TX_LENGTHS) &
8876 (TX_LENGTHS_JMB_FRM_LEN_MSK |
8877 TX_LENGTHS_CNT_DWN_VAL_MSK);
8879 tw32(MAC_TX_LENGTHS, val);
8881 /* Receive rules. */
8882 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8883 tw32(RCVLPC_CONFIG, 0x0181);
8885 /* Calculate RDMAC_MODE setting early, we need it to determine
8886 * the RCVLPC_STATE_ENABLE mask.
8888 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8889 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8890 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8891 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8892 RDMAC_MODE_LNGREAD_ENAB);
8894 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8895 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8897 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8898 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8899 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8900 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8901 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8902 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8905 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8906 if (tg3_flag(tp, TSO_CAPABLE) &&
8907 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8908 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8909 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8910 !tg3_flag(tp, IS_5788)) {
8911 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8915 if (tg3_flag(tp, PCI_EXPRESS))
8916 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8918 if (tg3_flag(tp, HW_TSO_1) ||
8919 tg3_flag(tp, HW_TSO_2) ||
8920 tg3_flag(tp, HW_TSO_3))
8921 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8923 if (tg3_flag(tp, 57765_PLUS) ||
8924 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8925 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8926 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8928 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8929 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8931 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8932 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8933 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8934 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8935 tg3_flag(tp, 57765_PLUS)) {
8936 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8937 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8939 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8940 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8941 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8942 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8943 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8944 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8946 tw32(TG3_RDMA_RSRVCTRL_REG,
8947 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8951 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8952 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8953 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8954 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8955 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8958 /* Receive/send statistics. */
8959 if (tg3_flag(tp, 5750_PLUS)) {
8960 val = tr32(RCVLPC_STATS_ENABLE);
8961 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8962 tw32(RCVLPC_STATS_ENABLE, val);
8963 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8964 tg3_flag(tp, TSO_CAPABLE)) {
8965 val = tr32(RCVLPC_STATS_ENABLE);
8966 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8967 tw32(RCVLPC_STATS_ENABLE, val);
8969 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8971 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8972 tw32(SNDDATAI_STATSENAB, 0xffffff);
8973 tw32(SNDDATAI_STATSCTRL,
8974 (SNDDATAI_SCTRL_ENABLE |
8975 SNDDATAI_SCTRL_FASTUPD));
8977 /* Setup host coalescing engine. */
8978 tw32(HOSTCC_MODE, 0);
8979 for (i = 0; i < 2000; i++) {
8980 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8985 __tg3_set_coalesce(tp, &tp->coal);
8987 if (!tg3_flag(tp, 5705_PLUS)) {
8988 /* Status/statistics block address. See tg3_timer,
8989 * the tg3_periodic_fetch_stats call there, and
8990 * tg3_get_stats to see how this works for 5705/5750 chips.
8992 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8993 ((u64) tp->stats_mapping >> 32));
8994 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8995 ((u64) tp->stats_mapping & 0xffffffff));
8996 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8998 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
9000 /* Clear statistics and status block memory areas */
9001 for (i = NIC_SRAM_STATS_BLK;
9002 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
9004 tg3_write_mem(tp, i, 0);
9009 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
9011 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
9012 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
9013 if (!tg3_flag(tp, 5705_PLUS))
9014 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
9016 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9017 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
9018 /* reset to prevent losing 1st rx packet intermittently */
9019 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9023 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9024 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
9025 MAC_MODE_FHDE_ENABLE;
9026 if (tg3_flag(tp, ENABLE_APE))
9027 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
9028 if (!tg3_flag(tp, 5705_PLUS) &&
9029 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9030 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
9031 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
9032 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
9035 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9036 * If TG3_FLAG_IS_NIC is zero, we should read the
9037 * register to preserve the GPIO settings for LOMs. The GPIOs,
9038 * whether used as inputs or outputs, are set by boot code after
9041 if (!tg3_flag(tp, IS_NIC)) {
9044 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
9045 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
9046 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
9048 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9049 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
9050 GRC_LCLCTRL_GPIO_OUTPUT3;
9052 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9053 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
9055 tp->grc_local_ctrl &= ~gpio_mask;
9056 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
9058 /* GPIO1 must be driven high for eeprom write protect */
9059 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9060 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9061 GRC_LCLCTRL_GPIO_OUTPUT1);
9063 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9066 if (tg3_flag(tp, USING_MSIX)) {
9067 val = tr32(MSGINT_MODE);
9068 val |= MSGINT_MODE_ENABLE;
9069 if (tp->irq_cnt > 1)
9070 val |= MSGINT_MODE_MULTIVEC_EN;
9071 if (!tg3_flag(tp, 1SHOT_MSI))
9072 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
9073 tw32(MSGINT_MODE, val);
9076 if (!tg3_flag(tp, 5705_PLUS)) {
9077 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
9081 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
9082 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
9083 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
9084 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
9085 WDMAC_MODE_LNGREAD_ENAB);
9087 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9088 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
9089 if (tg3_flag(tp, TSO_CAPABLE) &&
9090 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
9091 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
9093 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
9094 !tg3_flag(tp, IS_5788)) {
9095 val |= WDMAC_MODE_RX_ACCEL;
9099 /* Enable host coalescing bug fix */
9100 if (tg3_flag(tp, 5755_PLUS))
9101 val |= WDMAC_MODE_STATUS_TAG_FIX;
9103 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9104 val |= WDMAC_MODE_BURST_ALL_DATA;
9106 tw32_f(WDMAC_MODE, val);
9109 if (tg3_flag(tp, PCIX_MODE)) {
9112 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9114 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9115 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
9116 pcix_cmd |= PCI_X_CMD_READ_2K;
9117 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9118 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
9119 pcix_cmd |= PCI_X_CMD_READ_2K;
9121 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9125 tw32_f(RDMAC_MODE, rdmac_mode);
9128 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
9129 if (!tg3_flag(tp, 5705_PLUS))
9130 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9132 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9134 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
9136 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
9138 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
9139 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
9140 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
9141 if (tg3_flag(tp, LRG_PROD_RING_CAP))
9142 val |= RCVDBDI_MODE_LRG_RING_SZ;
9143 tw32(RCVDBDI_MODE, val);
9144 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
9145 if (tg3_flag(tp, HW_TSO_1) ||
9146 tg3_flag(tp, HW_TSO_2) ||
9147 tg3_flag(tp, HW_TSO_3))
9148 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
9149 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
9150 if (tg3_flag(tp, ENABLE_TSS))
9151 val |= SNDBDI_MODE_MULTI_TXQ_EN;
9152 tw32(SNDBDI_MODE, val);
9153 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
9155 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9156 err = tg3_load_5701_a0_firmware_fix(tp);
9161 if (tg3_flag(tp, TSO_CAPABLE)) {
9162 err = tg3_load_tso_firmware(tp);
9167 tp->tx_mode = TX_MODE_ENABLE;
9169 if (tg3_flag(tp, 5755_PLUS) ||
9170 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9171 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
9173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9174 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
9175 tp->tx_mode &= ~val;
9176 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
9179 tw32_f(MAC_TX_MODE, tp->tx_mode);
9182 if (tg3_flag(tp, ENABLE_RSS)) {
9183 tg3_rss_write_indir_tbl(tp);
9185 /* Setup the "secret" hash key. */
9186 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
9187 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
9188 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
9189 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
9190 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
9191 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
9192 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
9193 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
9194 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
9195 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
9198 tp->rx_mode = RX_MODE_ENABLE;
9199 if (tg3_flag(tp, 5755_PLUS))
9200 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
9202 if (tg3_flag(tp, ENABLE_RSS))
9203 tp->rx_mode |= RX_MODE_RSS_ENABLE |
9204 RX_MODE_RSS_ITBL_HASH_BITS_7 |
9205 RX_MODE_RSS_IPV6_HASH_EN |
9206 RX_MODE_RSS_TCP_IPV6_HASH_EN |
9207 RX_MODE_RSS_IPV4_HASH_EN |
9208 RX_MODE_RSS_TCP_IPV4_HASH_EN;
9210 tw32_f(MAC_RX_MODE, tp->rx_mode);
9213 tw32(MAC_LED_CTRL, tp->led_ctrl);
9215 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
9216 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9217 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9220 tw32_f(MAC_RX_MODE, tp->rx_mode);
9223 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9224 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
9225 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
9226 /* Set drive transmission level to 1.2V */
9227 /* only if the signal pre-emphasis bit is not set */
9228 val = tr32(MAC_SERDES_CFG);
9231 tw32(MAC_SERDES_CFG, val);
9233 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
9234 tw32(MAC_SERDES_CFG, 0x616000);
9237 /* Prevent chip from dropping frames when flow control
9240 if (tg3_flag(tp, 57765_CLASS))
9244 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
9246 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9247 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
9248 /* Use hardware link auto-negotiation */
9249 tg3_flag_set(tp, HW_AUTONEG);
9252 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9253 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9256 tmp = tr32(SERDES_RX_CTRL);
9257 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
9258 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
9259 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
9260 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9263 if (!tg3_flag(tp, USE_PHYLIB)) {
9264 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9265 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
9267 err = tg3_setup_phy(tp, 0);
9271 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9272 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
9275 /* Clear CRC stats. */
9276 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
9277 tg3_writephy(tp, MII_TG3_TEST1,
9278 tmp | MII_TG3_TEST1_CRC_EN);
9279 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
9284 __tg3_set_rx_mode(tp->dev);
9286 /* Initialize receive rules. */
9287 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
9288 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
9289 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
9290 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
9292 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
9296 if (tg3_flag(tp, ENABLE_ASF))
9300 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
9302 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
9304 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
9306 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
9308 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
9310 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
9312 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
9314 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
9316 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
9318 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
9320 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
9322 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
9324 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
9326 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
9334 if (tg3_flag(tp, ENABLE_APE))
9335 /* Write our heartbeat update interval to APE. */
9336 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
9337 APE_HOST_HEARTBEAT_INT_DISABLE);
9339 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
9344 /* Called at device open time to get the chip ready for
9345 * packet processing. Invoked with tp->lock held.
9347 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
9349 tg3_switch_clocks(tp);
9351 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9353 return tg3_reset_hw(tp, reset_phy);
9356 #define TG3_STAT_ADD32(PSTAT, REG) \
9357 do { u32 __val = tr32(REG); \
9358 (PSTAT)->low += __val; \
9359 if ((PSTAT)->low < __val) \
9360 (PSTAT)->high += 1; \
9363 static void tg3_periodic_fetch_stats(struct tg3 *tp)
9365 struct tg3_hw_stats *sp = tp->hw_stats;
9367 if (!netif_carrier_ok(tp->dev))
9370 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
9371 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
9372 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
9373 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
9374 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
9375 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
9376 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
9377 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
9378 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
9379 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
9380 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
9381 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
9382 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9384 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
9385 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
9386 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
9387 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
9388 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
9389 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
9390 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
9391 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
9392 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
9393 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
9394 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
9395 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
9396 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
9397 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
9399 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
9400 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9401 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
9402 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
9403 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
9405 u32 val = tr32(HOSTCC_FLOW_ATTN);
9406 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
9408 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
9409 sp->rx_discards.low += val;
9410 if (sp->rx_discards.low < val)
9411 sp->rx_discards.high += 1;
9413 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
9415 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
9418 static void tg3_chk_missed_msi(struct tg3 *tp)
9422 for (i = 0; i < tp->irq_cnt; i++) {
9423 struct tg3_napi *tnapi = &tp->napi[i];
9425 if (tg3_has_work(tnapi)) {
9426 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
9427 tnapi->last_tx_cons == tnapi->tx_cons) {
9428 if (tnapi->chk_msi_cnt < 1) {
9429 tnapi->chk_msi_cnt++;
9435 tnapi->chk_msi_cnt = 0;
9436 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
9437 tnapi->last_tx_cons = tnapi->tx_cons;
9441 static void tg3_timer(unsigned long __opaque)
9443 struct tg3 *tp = (struct tg3 *) __opaque;
9445 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
9448 spin_lock(&tp->lock);
9450 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
9451 tg3_flag(tp, 57765_CLASS))
9452 tg3_chk_missed_msi(tp);
9454 if (!tg3_flag(tp, TAGGED_STATUS)) {
9455 /* All of this garbage is because when using non-tagged
9456 * IRQ status the mailbox/status_block protocol the chip
9457 * uses with the cpu is race prone.
9459 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
9460 tw32(GRC_LOCAL_CTRL,
9461 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
9463 tw32(HOSTCC_MODE, tp->coalesce_mode |
9464 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
9467 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9468 spin_unlock(&tp->lock);
9469 tg3_reset_task_schedule(tp);
9474 /* This part only runs once per second. */
9475 if (!--tp->timer_counter) {
9476 if (tg3_flag(tp, 5705_PLUS))
9477 tg3_periodic_fetch_stats(tp);
9479 if (tp->setlpicnt && !--tp->setlpicnt)
9480 tg3_phy_eee_enable(tp);
9482 if (tg3_flag(tp, USE_LINKCHG_REG)) {
9486 mac_stat = tr32(MAC_STATUS);
9489 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
9490 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
9492 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
9496 tg3_setup_phy(tp, 0);
9497 } else if (tg3_flag(tp, POLL_SERDES)) {
9498 u32 mac_stat = tr32(MAC_STATUS);
9501 if (netif_carrier_ok(tp->dev) &&
9502 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
9505 if (!netif_carrier_ok(tp->dev) &&
9506 (mac_stat & (MAC_STATUS_PCS_SYNCED |
9507 MAC_STATUS_SIGNAL_DET))) {
9511 if (!tp->serdes_counter) {
9514 ~MAC_MODE_PORT_MODE_MASK));
9516 tw32_f(MAC_MODE, tp->mac_mode);
9519 tg3_setup_phy(tp, 0);
9521 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9522 tg3_flag(tp, 5780_CLASS)) {
9523 tg3_serdes_parallel_detect(tp);
9526 tp->timer_counter = tp->timer_multiplier;
9529 /* Heartbeat is only sent once every 2 seconds.
9531 * The heartbeat is to tell the ASF firmware that the host
9532 * driver is still alive. In the event that the OS crashes,
9533 * ASF needs to reset the hardware to free up the FIFO space
9534 * that may be filled with rx packets destined for the host.
9535 * If the FIFO is full, ASF will no longer function properly.
9537 * Unintended resets have been reported on real time kernels
9538 * where the timer doesn't run on time. Netpoll will also have
9541 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9542 * to check the ring condition when the heartbeat is expiring
9543 * before doing the reset. This will prevent most unintended
9546 if (!--tp->asf_counter) {
9547 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
9548 tg3_wait_for_event_ack(tp);
9550 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
9551 FWCMD_NICDRV_ALIVE3);
9552 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
9553 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
9554 TG3_FW_UPDATE_TIMEOUT_SEC);
9556 tg3_generate_fw_event(tp);
9558 tp->asf_counter = tp->asf_multiplier;
9561 spin_unlock(&tp->lock);
9564 tp->timer.expires = jiffies + tp->timer_offset;
9565 add_timer(&tp->timer);
9568 static void __devinit tg3_timer_init(struct tg3 *tp)
9570 if (tg3_flag(tp, TAGGED_STATUS) &&
9571 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9572 !tg3_flag(tp, 57765_CLASS))
9573 tp->timer_offset = HZ;
9575 tp->timer_offset = HZ / 10;
9577 BUG_ON(tp->timer_offset > HZ);
9579 tp->timer_multiplier = (HZ / tp->timer_offset);
9580 tp->asf_multiplier = (HZ / tp->timer_offset) *
9581 TG3_FW_UPDATE_FREQ_SEC;
9583 init_timer(&tp->timer);
9584 tp->timer.data = (unsigned long) tp;
9585 tp->timer.function = tg3_timer;
9588 static void tg3_timer_start(struct tg3 *tp)
9590 tp->asf_counter = tp->asf_multiplier;
9591 tp->timer_counter = tp->timer_multiplier;
9593 tp->timer.expires = jiffies + tp->timer_offset;
9594 add_timer(&tp->timer);
9597 static void tg3_timer_stop(struct tg3 *tp)
9599 del_timer_sync(&tp->timer);
9602 /* Restart hardware after configuration changes, self-test, etc.
9603 * Invoked with tp->lock held.
9605 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
9606 __releases(tp->lock)
9607 __acquires(tp->lock)
9611 err = tg3_init_hw(tp, reset_phy);
9614 "Failed to re-initialize device, aborting\n");
9615 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9616 tg3_full_unlock(tp);
9619 tg3_napi_enable(tp);
9621 tg3_full_lock(tp, 0);
9626 static void tg3_reset_task(struct work_struct *work)
9628 struct tg3 *tp = container_of(work, struct tg3, reset_task);
9631 tg3_full_lock(tp, 0);
9633 if (!netif_running(tp->dev)) {
9634 tg3_flag_clear(tp, RESET_TASK_PENDING);
9635 tg3_full_unlock(tp);
9639 tg3_full_unlock(tp);
9645 tg3_full_lock(tp, 1);
9647 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
9648 tp->write32_tx_mbox = tg3_write32_tx_mbox;
9649 tp->write32_rx_mbox = tg3_write_flush_reg32;
9650 tg3_flag_set(tp, MBOX_WRITE_REORDER);
9651 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
9654 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
9655 err = tg3_init_hw(tp, 1);
9659 tg3_netif_start(tp);
9662 tg3_full_unlock(tp);
9667 tg3_flag_clear(tp, RESET_TASK_PENDING);
9670 static int tg3_request_irq(struct tg3 *tp, int irq_num)
9673 unsigned long flags;
9675 struct tg3_napi *tnapi = &tp->napi[irq_num];
9677 if (tp->irq_cnt == 1)
9678 name = tp->dev->name;
9680 name = &tnapi->irq_lbl[0];
9681 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
9682 name[IFNAMSIZ-1] = 0;
9685 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9687 if (tg3_flag(tp, 1SHOT_MSI))
9692 if (tg3_flag(tp, TAGGED_STATUS))
9693 fn = tg3_interrupt_tagged;
9694 flags = IRQF_SHARED;
9697 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
9700 static int tg3_test_interrupt(struct tg3 *tp)
9702 struct tg3_napi *tnapi = &tp->napi[0];
9703 struct net_device *dev = tp->dev;
9704 int err, i, intr_ok = 0;
9707 if (!netif_running(dev))
9710 tg3_disable_ints(tp);
9712 free_irq(tnapi->irq_vec, tnapi);
9715 * Turn off MSI one shot mode. Otherwise this test has no
9716 * observable way to know whether the interrupt was delivered.
9718 if (tg3_flag(tp, 57765_PLUS)) {
9719 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9720 tw32(MSGINT_MODE, val);
9723 err = request_irq(tnapi->irq_vec, tg3_test_isr,
9724 IRQF_SHARED, dev->name, tnapi);
9728 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
9729 tg3_enable_ints(tp);
9731 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9734 for (i = 0; i < 5; i++) {
9735 u32 int_mbox, misc_host_ctrl;
9737 int_mbox = tr32_mailbox(tnapi->int_mbox);
9738 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9740 if ((int_mbox != 0) ||
9741 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9746 if (tg3_flag(tp, 57765_PLUS) &&
9747 tnapi->hw_status->status_tag != tnapi->last_tag)
9748 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
9753 tg3_disable_ints(tp);
9755 free_irq(tnapi->irq_vec, tnapi);
9757 err = tg3_request_irq(tp, 0);
9763 /* Reenable MSI one shot mode. */
9764 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
9765 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9766 tw32(MSGINT_MODE, val);
9774 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9775 * successfully restored
9777 static int tg3_test_msi(struct tg3 *tp)
9782 if (!tg3_flag(tp, USING_MSI))
9785 /* Turn off SERR reporting in case MSI terminates with Master
9788 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9789 pci_write_config_word(tp->pdev, PCI_COMMAND,
9790 pci_cmd & ~PCI_COMMAND_SERR);
9792 err = tg3_test_interrupt(tp);
9794 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9799 /* other failures */
9803 /* MSI test failed, go back to INTx mode */
9804 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9805 "to INTx mode. Please report this failure to the PCI "
9806 "maintainer and include system chipset information\n");
9808 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9810 pci_disable_msi(tp->pdev);
9812 tg3_flag_clear(tp, USING_MSI);
9813 tp->napi[0].irq_vec = tp->pdev->irq;
9815 err = tg3_request_irq(tp, 0);
9819 /* Need to reset the chip because the MSI cycle may have terminated
9820 * with Master Abort.
9822 tg3_full_lock(tp, 1);
9824 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9825 err = tg3_init_hw(tp, 1);
9827 tg3_full_unlock(tp);
9830 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9835 static int tg3_request_firmware(struct tg3 *tp)
9837 const __be32 *fw_data;
9839 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9840 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9845 fw_data = (void *)tp->fw->data;
9847 /* Firmware blob starts with version numbers, followed by
9848 * start address and _full_ length including BSS sections
9849 * (which must be longer than the actual data, of course
9852 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9853 if (tp->fw_len < (tp->fw->size - 12)) {
9854 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9855 tp->fw_len, tp->fw_needed);
9856 release_firmware(tp->fw);
9861 /* We no longer need firmware; we have it. */
9862 tp->fw_needed = NULL;
9866 static bool tg3_enable_msix(struct tg3 *tp)
9869 struct msix_entry msix_ent[tp->irq_max];
9871 tp->irq_cnt = num_online_cpus();
9872 if (tp->irq_cnt > 1) {
9873 /* We want as many rx rings enabled as there are cpus.
9874 * In multiqueue MSI-X mode, the first MSI-X vector
9875 * only deals with link interrupts, etc, so we add
9876 * one to the number of vectors we are requesting.
9878 tp->irq_cnt = min_t(unsigned, tp->irq_cnt + 1, tp->irq_max);
9881 for (i = 0; i < tp->irq_max; i++) {
9882 msix_ent[i].entry = i;
9883 msix_ent[i].vector = 0;
9886 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9889 } else if (rc != 0) {
9890 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9892 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9897 for (i = 0; i < tp->irq_max; i++)
9898 tp->napi[i].irq_vec = msix_ent[i].vector;
9900 netif_set_real_num_tx_queues(tp->dev, 1);
9901 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9902 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9903 pci_disable_msix(tp->pdev);
9907 if (tp->irq_cnt > 1) {
9908 tg3_flag_set(tp, ENABLE_RSS);
9910 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9911 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9912 tg3_flag_set(tp, ENABLE_TSS);
9913 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9920 static void tg3_ints_init(struct tg3 *tp)
9922 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
9923 !tg3_flag(tp, TAGGED_STATUS)) {
9924 /* All MSI supporting chips should support tagged
9925 * status. Assert that this is the case.
9927 netdev_warn(tp->dev,
9928 "MSI without TAGGED_STATUS? Not using MSI\n");
9932 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
9933 tg3_flag_set(tp, USING_MSIX);
9934 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
9935 tg3_flag_set(tp, USING_MSI);
9937 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9938 u32 msi_mode = tr32(MSGINT_MODE);
9939 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
9940 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9941 if (!tg3_flag(tp, 1SHOT_MSI))
9942 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
9943 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9946 if (!tg3_flag(tp, USING_MSIX)) {
9948 tp->napi[0].irq_vec = tp->pdev->irq;
9949 netif_set_real_num_tx_queues(tp->dev, 1);
9950 netif_set_real_num_rx_queues(tp->dev, 1);
9954 static void tg3_ints_fini(struct tg3 *tp)
9956 if (tg3_flag(tp, USING_MSIX))
9957 pci_disable_msix(tp->pdev);
9958 else if (tg3_flag(tp, USING_MSI))
9959 pci_disable_msi(tp->pdev);
9960 tg3_flag_clear(tp, USING_MSI);
9961 tg3_flag_clear(tp, USING_MSIX);
9962 tg3_flag_clear(tp, ENABLE_RSS);
9963 tg3_flag_clear(tp, ENABLE_TSS);
9966 static int tg3_open(struct net_device *dev)
9968 struct tg3 *tp = netdev_priv(dev);
9971 if (tp->fw_needed) {
9972 err = tg3_request_firmware(tp);
9973 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9977 netdev_warn(tp->dev, "TSO capability disabled\n");
9978 tg3_flag_clear(tp, TSO_CAPABLE);
9979 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
9980 netdev_notice(tp->dev, "TSO capability restored\n");
9981 tg3_flag_set(tp, TSO_CAPABLE);
9985 netif_carrier_off(tp->dev);
9987 err = tg3_power_up(tp);
9991 tg3_full_lock(tp, 0);
9993 tg3_disable_ints(tp);
9994 tg3_flag_clear(tp, INIT_COMPLETE);
9996 tg3_full_unlock(tp);
9999 * Setup interrupts first so we know how
10000 * many NAPI resources to allocate
10004 tg3_rss_check_indir_tbl(tp);
10006 /* The placement of this call is tied
10007 * to the setup and use of Host TX descriptors.
10009 err = tg3_alloc_consistent(tp);
10015 tg3_napi_enable(tp);
10017 for (i = 0; i < tp->irq_cnt; i++) {
10018 struct tg3_napi *tnapi = &tp->napi[i];
10019 err = tg3_request_irq(tp, i);
10021 for (i--; i >= 0; i--) {
10022 tnapi = &tp->napi[i];
10023 free_irq(tnapi->irq_vec, tnapi);
10029 tg3_full_lock(tp, 0);
10031 err = tg3_init_hw(tp, 1);
10033 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10034 tg3_free_rings(tp);
10037 tg3_full_unlock(tp);
10042 if (tg3_flag(tp, USING_MSI)) {
10043 err = tg3_test_msi(tp);
10046 tg3_full_lock(tp, 0);
10047 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10048 tg3_free_rings(tp);
10049 tg3_full_unlock(tp);
10054 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
10055 u32 val = tr32(PCIE_TRANSACTION_CFG);
10057 tw32(PCIE_TRANSACTION_CFG,
10058 val | PCIE_TRANS_CFG_1SHOT_MSI);
10064 tg3_full_lock(tp, 0);
10066 tg3_timer_start(tp);
10067 tg3_flag_set(tp, INIT_COMPLETE);
10068 tg3_enable_ints(tp);
10070 tg3_full_unlock(tp);
10072 netif_tx_start_all_queues(dev);
10075 * Reset loopback feature if it was turned on while the device was down
10076 * make sure that it's installed properly now.
10078 if (dev->features & NETIF_F_LOOPBACK)
10079 tg3_set_loopback(dev, dev->features);
10084 for (i = tp->irq_cnt - 1; i >= 0; i--) {
10085 struct tg3_napi *tnapi = &tp->napi[i];
10086 free_irq(tnapi->irq_vec, tnapi);
10090 tg3_napi_disable(tp);
10092 tg3_free_consistent(tp);
10096 tg3_frob_aux_power(tp, false);
10097 pci_set_power_state(tp->pdev, PCI_D3hot);
10101 static int tg3_close(struct net_device *dev)
10104 struct tg3 *tp = netdev_priv(dev);
10106 tg3_napi_disable(tp);
10107 tg3_reset_task_cancel(tp);
10109 netif_tx_stop_all_queues(dev);
10111 tg3_timer_stop(tp);
10115 tg3_full_lock(tp, 1);
10117 tg3_disable_ints(tp);
10119 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10120 tg3_free_rings(tp);
10121 tg3_flag_clear(tp, INIT_COMPLETE);
10123 tg3_full_unlock(tp);
10125 for (i = tp->irq_cnt - 1; i >= 0; i--) {
10126 struct tg3_napi *tnapi = &tp->napi[i];
10127 free_irq(tnapi->irq_vec, tnapi);
10132 /* Clear stats across close / open calls */
10133 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
10134 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
10138 tg3_free_consistent(tp);
10140 tg3_power_down(tp);
10142 netif_carrier_off(tp->dev);
10147 static inline u64 get_stat64(tg3_stat64_t *val)
10149 return ((u64)val->high << 32) | ((u64)val->low);
10152 static u64 tg3_calc_crc_errors(struct tg3 *tp)
10154 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10156 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10157 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10158 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
10161 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
10162 tg3_writephy(tp, MII_TG3_TEST1,
10163 val | MII_TG3_TEST1_CRC_EN);
10164 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
10168 tp->phy_crc_errors += val;
10170 return tp->phy_crc_errors;
10173 return get_stat64(&hw_stats->rx_fcs_errors);
10176 #define ESTAT_ADD(member) \
10177 estats->member = old_estats->member + \
10178 get_stat64(&hw_stats->member)
10180 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
10182 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
10183 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10185 ESTAT_ADD(rx_octets);
10186 ESTAT_ADD(rx_fragments);
10187 ESTAT_ADD(rx_ucast_packets);
10188 ESTAT_ADD(rx_mcast_packets);
10189 ESTAT_ADD(rx_bcast_packets);
10190 ESTAT_ADD(rx_fcs_errors);
10191 ESTAT_ADD(rx_align_errors);
10192 ESTAT_ADD(rx_xon_pause_rcvd);
10193 ESTAT_ADD(rx_xoff_pause_rcvd);
10194 ESTAT_ADD(rx_mac_ctrl_rcvd);
10195 ESTAT_ADD(rx_xoff_entered);
10196 ESTAT_ADD(rx_frame_too_long_errors);
10197 ESTAT_ADD(rx_jabbers);
10198 ESTAT_ADD(rx_undersize_packets);
10199 ESTAT_ADD(rx_in_length_errors);
10200 ESTAT_ADD(rx_out_length_errors);
10201 ESTAT_ADD(rx_64_or_less_octet_packets);
10202 ESTAT_ADD(rx_65_to_127_octet_packets);
10203 ESTAT_ADD(rx_128_to_255_octet_packets);
10204 ESTAT_ADD(rx_256_to_511_octet_packets);
10205 ESTAT_ADD(rx_512_to_1023_octet_packets);
10206 ESTAT_ADD(rx_1024_to_1522_octet_packets);
10207 ESTAT_ADD(rx_1523_to_2047_octet_packets);
10208 ESTAT_ADD(rx_2048_to_4095_octet_packets);
10209 ESTAT_ADD(rx_4096_to_8191_octet_packets);
10210 ESTAT_ADD(rx_8192_to_9022_octet_packets);
10212 ESTAT_ADD(tx_octets);
10213 ESTAT_ADD(tx_collisions);
10214 ESTAT_ADD(tx_xon_sent);
10215 ESTAT_ADD(tx_xoff_sent);
10216 ESTAT_ADD(tx_flow_control);
10217 ESTAT_ADD(tx_mac_errors);
10218 ESTAT_ADD(tx_single_collisions);
10219 ESTAT_ADD(tx_mult_collisions);
10220 ESTAT_ADD(tx_deferred);
10221 ESTAT_ADD(tx_excessive_collisions);
10222 ESTAT_ADD(tx_late_collisions);
10223 ESTAT_ADD(tx_collide_2times);
10224 ESTAT_ADD(tx_collide_3times);
10225 ESTAT_ADD(tx_collide_4times);
10226 ESTAT_ADD(tx_collide_5times);
10227 ESTAT_ADD(tx_collide_6times);
10228 ESTAT_ADD(tx_collide_7times);
10229 ESTAT_ADD(tx_collide_8times);
10230 ESTAT_ADD(tx_collide_9times);
10231 ESTAT_ADD(tx_collide_10times);
10232 ESTAT_ADD(tx_collide_11times);
10233 ESTAT_ADD(tx_collide_12times);
10234 ESTAT_ADD(tx_collide_13times);
10235 ESTAT_ADD(tx_collide_14times);
10236 ESTAT_ADD(tx_collide_15times);
10237 ESTAT_ADD(tx_ucast_packets);
10238 ESTAT_ADD(tx_mcast_packets);
10239 ESTAT_ADD(tx_bcast_packets);
10240 ESTAT_ADD(tx_carrier_sense_errors);
10241 ESTAT_ADD(tx_discards);
10242 ESTAT_ADD(tx_errors);
10244 ESTAT_ADD(dma_writeq_full);
10245 ESTAT_ADD(dma_write_prioq_full);
10246 ESTAT_ADD(rxbds_empty);
10247 ESTAT_ADD(rx_discards);
10248 ESTAT_ADD(rx_errors);
10249 ESTAT_ADD(rx_threshold_hit);
10251 ESTAT_ADD(dma_readq_full);
10252 ESTAT_ADD(dma_read_prioq_full);
10253 ESTAT_ADD(tx_comp_queue_full);
10255 ESTAT_ADD(ring_set_send_prod_index);
10256 ESTAT_ADD(ring_status_update);
10257 ESTAT_ADD(nic_irqs);
10258 ESTAT_ADD(nic_avoided_irqs);
10259 ESTAT_ADD(nic_tx_threshold_hit);
10261 ESTAT_ADD(mbuf_lwm_thresh_hit);
10264 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
10266 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
10267 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10269 stats->rx_packets = old_stats->rx_packets +
10270 get_stat64(&hw_stats->rx_ucast_packets) +
10271 get_stat64(&hw_stats->rx_mcast_packets) +
10272 get_stat64(&hw_stats->rx_bcast_packets);
10274 stats->tx_packets = old_stats->tx_packets +
10275 get_stat64(&hw_stats->tx_ucast_packets) +
10276 get_stat64(&hw_stats->tx_mcast_packets) +
10277 get_stat64(&hw_stats->tx_bcast_packets);
10279 stats->rx_bytes = old_stats->rx_bytes +
10280 get_stat64(&hw_stats->rx_octets);
10281 stats->tx_bytes = old_stats->tx_bytes +
10282 get_stat64(&hw_stats->tx_octets);
10284 stats->rx_errors = old_stats->rx_errors +
10285 get_stat64(&hw_stats->rx_errors);
10286 stats->tx_errors = old_stats->tx_errors +
10287 get_stat64(&hw_stats->tx_errors) +
10288 get_stat64(&hw_stats->tx_mac_errors) +
10289 get_stat64(&hw_stats->tx_carrier_sense_errors) +
10290 get_stat64(&hw_stats->tx_discards);
10292 stats->multicast = old_stats->multicast +
10293 get_stat64(&hw_stats->rx_mcast_packets);
10294 stats->collisions = old_stats->collisions +
10295 get_stat64(&hw_stats->tx_collisions);
10297 stats->rx_length_errors = old_stats->rx_length_errors +
10298 get_stat64(&hw_stats->rx_frame_too_long_errors) +
10299 get_stat64(&hw_stats->rx_undersize_packets);
10301 stats->rx_over_errors = old_stats->rx_over_errors +
10302 get_stat64(&hw_stats->rxbds_empty);
10303 stats->rx_frame_errors = old_stats->rx_frame_errors +
10304 get_stat64(&hw_stats->rx_align_errors);
10305 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
10306 get_stat64(&hw_stats->tx_discards);
10307 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
10308 get_stat64(&hw_stats->tx_carrier_sense_errors);
10310 stats->rx_crc_errors = old_stats->rx_crc_errors +
10311 tg3_calc_crc_errors(tp);
10313 stats->rx_missed_errors = old_stats->rx_missed_errors +
10314 get_stat64(&hw_stats->rx_discards);
10316 stats->rx_dropped = tp->rx_dropped;
10317 stats->tx_dropped = tp->tx_dropped;
10320 static int tg3_get_regs_len(struct net_device *dev)
10322 return TG3_REG_BLK_SIZE;
10325 static void tg3_get_regs(struct net_device *dev,
10326 struct ethtool_regs *regs, void *_p)
10328 struct tg3 *tp = netdev_priv(dev);
10332 memset(_p, 0, TG3_REG_BLK_SIZE);
10334 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10337 tg3_full_lock(tp, 0);
10339 tg3_dump_legacy_regs(tp, (u32 *)_p);
10341 tg3_full_unlock(tp);
10344 static int tg3_get_eeprom_len(struct net_device *dev)
10346 struct tg3 *tp = netdev_priv(dev);
10348 return tp->nvram_size;
10351 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10353 struct tg3 *tp = netdev_priv(dev);
10356 u32 i, offset, len, b_offset, b_count;
10359 if (tg3_flag(tp, NO_NVRAM))
10362 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10365 offset = eeprom->offset;
10369 eeprom->magic = TG3_EEPROM_MAGIC;
10372 /* adjustments to start on required 4 byte boundary */
10373 b_offset = offset & 3;
10374 b_count = 4 - b_offset;
10375 if (b_count > len) {
10376 /* i.e. offset=1 len=2 */
10379 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
10382 memcpy(data, ((char *)&val) + b_offset, b_count);
10385 eeprom->len += b_count;
10388 /* read bytes up to the last 4 byte boundary */
10389 pd = &data[eeprom->len];
10390 for (i = 0; i < (len - (len & 3)); i += 4) {
10391 ret = tg3_nvram_read_be32(tp, offset + i, &val);
10396 memcpy(pd + i, &val, 4);
10401 /* read last bytes not ending on 4 byte boundary */
10402 pd = &data[eeprom->len];
10404 b_offset = offset + len - b_count;
10405 ret = tg3_nvram_read_be32(tp, b_offset, &val);
10408 memcpy(pd, &val, b_count);
10409 eeprom->len += b_count;
10414 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10416 struct tg3 *tp = netdev_priv(dev);
10418 u32 offset, len, b_offset, odd_len;
10422 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10425 if (tg3_flag(tp, NO_NVRAM) ||
10426 eeprom->magic != TG3_EEPROM_MAGIC)
10429 offset = eeprom->offset;
10432 if ((b_offset = (offset & 3))) {
10433 /* adjustments to start on required 4 byte boundary */
10434 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
10445 /* adjustments to end on required 4 byte boundary */
10447 len = (len + 3) & ~3;
10448 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
10454 if (b_offset || odd_len) {
10455 buf = kmalloc(len, GFP_KERNEL);
10459 memcpy(buf, &start, 4);
10461 memcpy(buf+len-4, &end, 4);
10462 memcpy(buf + b_offset, data, eeprom->len);
10465 ret = tg3_nvram_write_block(tp, offset, len, buf);
10473 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10475 struct tg3 *tp = netdev_priv(dev);
10477 if (tg3_flag(tp, USE_PHYLIB)) {
10478 struct phy_device *phydev;
10479 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10481 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10482 return phy_ethtool_gset(phydev, cmd);
10485 cmd->supported = (SUPPORTED_Autoneg);
10487 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10488 cmd->supported |= (SUPPORTED_1000baseT_Half |
10489 SUPPORTED_1000baseT_Full);
10491 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10492 cmd->supported |= (SUPPORTED_100baseT_Half |
10493 SUPPORTED_100baseT_Full |
10494 SUPPORTED_10baseT_Half |
10495 SUPPORTED_10baseT_Full |
10497 cmd->port = PORT_TP;
10499 cmd->supported |= SUPPORTED_FIBRE;
10500 cmd->port = PORT_FIBRE;
10503 cmd->advertising = tp->link_config.advertising;
10504 if (tg3_flag(tp, PAUSE_AUTONEG)) {
10505 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
10506 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10507 cmd->advertising |= ADVERTISED_Pause;
10509 cmd->advertising |= ADVERTISED_Pause |
10510 ADVERTISED_Asym_Pause;
10512 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10513 cmd->advertising |= ADVERTISED_Asym_Pause;
10516 if (netif_running(dev) && netif_carrier_ok(dev)) {
10517 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
10518 cmd->duplex = tp->link_config.active_duplex;
10519 cmd->lp_advertising = tp->link_config.rmt_adv;
10520 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10521 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
10522 cmd->eth_tp_mdix = ETH_TP_MDI_X;
10524 cmd->eth_tp_mdix = ETH_TP_MDI;
10527 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
10528 cmd->duplex = DUPLEX_UNKNOWN;
10529 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
10531 cmd->phy_address = tp->phy_addr;
10532 cmd->transceiver = XCVR_INTERNAL;
10533 cmd->autoneg = tp->link_config.autoneg;
10539 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10541 struct tg3 *tp = netdev_priv(dev);
10542 u32 speed = ethtool_cmd_speed(cmd);
10544 if (tg3_flag(tp, USE_PHYLIB)) {
10545 struct phy_device *phydev;
10546 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10548 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10549 return phy_ethtool_sset(phydev, cmd);
10552 if (cmd->autoneg != AUTONEG_ENABLE &&
10553 cmd->autoneg != AUTONEG_DISABLE)
10556 if (cmd->autoneg == AUTONEG_DISABLE &&
10557 cmd->duplex != DUPLEX_FULL &&
10558 cmd->duplex != DUPLEX_HALF)
10561 if (cmd->autoneg == AUTONEG_ENABLE) {
10562 u32 mask = ADVERTISED_Autoneg |
10564 ADVERTISED_Asym_Pause;
10566 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10567 mask |= ADVERTISED_1000baseT_Half |
10568 ADVERTISED_1000baseT_Full;
10570 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
10571 mask |= ADVERTISED_100baseT_Half |
10572 ADVERTISED_100baseT_Full |
10573 ADVERTISED_10baseT_Half |
10574 ADVERTISED_10baseT_Full |
10577 mask |= ADVERTISED_FIBRE;
10579 if (cmd->advertising & ~mask)
10582 mask &= (ADVERTISED_1000baseT_Half |
10583 ADVERTISED_1000baseT_Full |
10584 ADVERTISED_100baseT_Half |
10585 ADVERTISED_100baseT_Full |
10586 ADVERTISED_10baseT_Half |
10587 ADVERTISED_10baseT_Full);
10589 cmd->advertising &= mask;
10591 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
10592 if (speed != SPEED_1000)
10595 if (cmd->duplex != DUPLEX_FULL)
10598 if (speed != SPEED_100 &&
10604 tg3_full_lock(tp, 0);
10606 tp->link_config.autoneg = cmd->autoneg;
10607 if (cmd->autoneg == AUTONEG_ENABLE) {
10608 tp->link_config.advertising = (cmd->advertising |
10609 ADVERTISED_Autoneg);
10610 tp->link_config.speed = SPEED_UNKNOWN;
10611 tp->link_config.duplex = DUPLEX_UNKNOWN;
10613 tp->link_config.advertising = 0;
10614 tp->link_config.speed = speed;
10615 tp->link_config.duplex = cmd->duplex;
10618 if (netif_running(dev))
10619 tg3_setup_phy(tp, 1);
10621 tg3_full_unlock(tp);
10626 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10628 struct tg3 *tp = netdev_priv(dev);
10630 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
10631 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
10632 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
10633 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
10636 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10638 struct tg3 *tp = netdev_priv(dev);
10640 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
10641 wol->supported = WAKE_MAGIC;
10643 wol->supported = 0;
10645 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
10646 wol->wolopts = WAKE_MAGIC;
10647 memset(&wol->sopass, 0, sizeof(wol->sopass));
10650 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10652 struct tg3 *tp = netdev_priv(dev);
10653 struct device *dp = &tp->pdev->dev;
10655 if (wol->wolopts & ~WAKE_MAGIC)
10657 if ((wol->wolopts & WAKE_MAGIC) &&
10658 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
10661 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10663 spin_lock_bh(&tp->lock);
10664 if (device_may_wakeup(dp))
10665 tg3_flag_set(tp, WOL_ENABLE);
10667 tg3_flag_clear(tp, WOL_ENABLE);
10668 spin_unlock_bh(&tp->lock);
10673 static u32 tg3_get_msglevel(struct net_device *dev)
10675 struct tg3 *tp = netdev_priv(dev);
10676 return tp->msg_enable;
10679 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10681 struct tg3 *tp = netdev_priv(dev);
10682 tp->msg_enable = value;
10685 static int tg3_nway_reset(struct net_device *dev)
10687 struct tg3 *tp = netdev_priv(dev);
10690 if (!netif_running(dev))
10693 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10696 if (tg3_flag(tp, USE_PHYLIB)) {
10697 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10699 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10703 spin_lock_bh(&tp->lock);
10705 tg3_readphy(tp, MII_BMCR, &bmcr);
10706 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10707 ((bmcr & BMCR_ANENABLE) ||
10708 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10709 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10713 spin_unlock_bh(&tp->lock);
10719 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10721 struct tg3 *tp = netdev_priv(dev);
10723 ering->rx_max_pending = tp->rx_std_ring_mask;
10724 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10725 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10727 ering->rx_jumbo_max_pending = 0;
10729 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10731 ering->rx_pending = tp->rx_pending;
10732 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10733 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10735 ering->rx_jumbo_pending = 0;
10737 ering->tx_pending = tp->napi[0].tx_pending;
10740 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10742 struct tg3 *tp = netdev_priv(dev);
10743 int i, irq_sync = 0, err = 0;
10745 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10746 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10747 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10748 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10749 (tg3_flag(tp, TSO_BUG) &&
10750 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10753 if (netif_running(dev)) {
10755 tg3_netif_stop(tp);
10759 tg3_full_lock(tp, irq_sync);
10761 tp->rx_pending = ering->rx_pending;
10763 if (tg3_flag(tp, MAX_RXPEND_64) &&
10764 tp->rx_pending > 63)
10765 tp->rx_pending = 63;
10766 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10768 for (i = 0; i < tp->irq_max; i++)
10769 tp->napi[i].tx_pending = ering->tx_pending;
10771 if (netif_running(dev)) {
10772 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10773 err = tg3_restart_hw(tp, 1);
10775 tg3_netif_start(tp);
10778 tg3_full_unlock(tp);
10780 if (irq_sync && !err)
10786 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10788 struct tg3 *tp = netdev_priv(dev);
10790 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
10792 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
10793 epause->rx_pause = 1;
10795 epause->rx_pause = 0;
10797 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
10798 epause->tx_pause = 1;
10800 epause->tx_pause = 0;
10803 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10805 struct tg3 *tp = netdev_priv(dev);
10808 if (tg3_flag(tp, USE_PHYLIB)) {
10810 struct phy_device *phydev;
10812 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10814 if (!(phydev->supported & SUPPORTED_Pause) ||
10815 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10816 (epause->rx_pause != epause->tx_pause)))
10819 tp->link_config.flowctrl = 0;
10820 if (epause->rx_pause) {
10821 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10823 if (epause->tx_pause) {
10824 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10825 newadv = ADVERTISED_Pause;
10827 newadv = ADVERTISED_Pause |
10828 ADVERTISED_Asym_Pause;
10829 } else if (epause->tx_pause) {
10830 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10831 newadv = ADVERTISED_Asym_Pause;
10835 if (epause->autoneg)
10836 tg3_flag_set(tp, PAUSE_AUTONEG);
10838 tg3_flag_clear(tp, PAUSE_AUTONEG);
10840 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10841 u32 oldadv = phydev->advertising &
10842 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10843 if (oldadv != newadv) {
10844 phydev->advertising &=
10845 ~(ADVERTISED_Pause |
10846 ADVERTISED_Asym_Pause);
10847 phydev->advertising |= newadv;
10848 if (phydev->autoneg) {
10850 * Always renegotiate the link to
10851 * inform our link partner of our
10852 * flow control settings, even if the
10853 * flow control is forced. Let
10854 * tg3_adjust_link() do the final
10855 * flow control setup.
10857 return phy_start_aneg(phydev);
10861 if (!epause->autoneg)
10862 tg3_setup_flow_control(tp, 0, 0);
10864 tp->link_config.advertising &=
10865 ~(ADVERTISED_Pause |
10866 ADVERTISED_Asym_Pause);
10867 tp->link_config.advertising |= newadv;
10872 if (netif_running(dev)) {
10873 tg3_netif_stop(tp);
10877 tg3_full_lock(tp, irq_sync);
10879 if (epause->autoneg)
10880 tg3_flag_set(tp, PAUSE_AUTONEG);
10882 tg3_flag_clear(tp, PAUSE_AUTONEG);
10883 if (epause->rx_pause)
10884 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10886 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10887 if (epause->tx_pause)
10888 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10890 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10892 if (netif_running(dev)) {
10893 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10894 err = tg3_restart_hw(tp, 1);
10896 tg3_netif_start(tp);
10899 tg3_full_unlock(tp);
10905 static int tg3_get_sset_count(struct net_device *dev, int sset)
10909 return TG3_NUM_TEST;
10911 return TG3_NUM_STATS;
10913 return -EOPNOTSUPP;
10917 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
10918 u32 *rules __always_unused)
10920 struct tg3 *tp = netdev_priv(dev);
10922 if (!tg3_flag(tp, SUPPORT_MSIX))
10923 return -EOPNOTSUPP;
10925 switch (info->cmd) {
10926 case ETHTOOL_GRXRINGS:
10927 if (netif_running(tp->dev))
10928 info->data = tp->irq_cnt;
10930 info->data = num_online_cpus();
10931 if (info->data > TG3_IRQ_MAX_VECS_RSS)
10932 info->data = TG3_IRQ_MAX_VECS_RSS;
10935 /* The first interrupt vector only
10936 * handles link interrupts.
10942 return -EOPNOTSUPP;
10946 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
10949 struct tg3 *tp = netdev_priv(dev);
10951 if (tg3_flag(tp, SUPPORT_MSIX))
10952 size = TG3_RSS_INDIR_TBL_SIZE;
10957 static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
10959 struct tg3 *tp = netdev_priv(dev);
10962 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
10963 indir[i] = tp->rss_ind_tbl[i];
10968 static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
10970 struct tg3 *tp = netdev_priv(dev);
10973 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
10974 tp->rss_ind_tbl[i] = indir[i];
10976 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
10979 /* It is legal to write the indirection
10980 * table while the device is running.
10982 tg3_full_lock(tp, 0);
10983 tg3_rss_write_indir_tbl(tp);
10984 tg3_full_unlock(tp);
10989 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10991 switch (stringset) {
10993 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10996 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10999 WARN_ON(1); /* we need a WARN() */
11004 static int tg3_set_phys_id(struct net_device *dev,
11005 enum ethtool_phys_id_state state)
11007 struct tg3 *tp = netdev_priv(dev);
11009 if (!netif_running(tp->dev))
11013 case ETHTOOL_ID_ACTIVE:
11014 return 1; /* cycle on/off once per second */
11016 case ETHTOOL_ID_ON:
11017 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
11018 LED_CTRL_1000MBPS_ON |
11019 LED_CTRL_100MBPS_ON |
11020 LED_CTRL_10MBPS_ON |
11021 LED_CTRL_TRAFFIC_OVERRIDE |
11022 LED_CTRL_TRAFFIC_BLINK |
11023 LED_CTRL_TRAFFIC_LED);
11026 case ETHTOOL_ID_OFF:
11027 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
11028 LED_CTRL_TRAFFIC_OVERRIDE);
11031 case ETHTOOL_ID_INACTIVE:
11032 tw32(MAC_LED_CTRL, tp->led_ctrl);
11039 static void tg3_get_ethtool_stats(struct net_device *dev,
11040 struct ethtool_stats *estats, u64 *tmp_stats)
11042 struct tg3 *tp = netdev_priv(dev);
11045 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
11047 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
11050 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
11054 u32 offset = 0, len = 0;
11057 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
11060 if (magic == TG3_EEPROM_MAGIC) {
11061 for (offset = TG3_NVM_DIR_START;
11062 offset < TG3_NVM_DIR_END;
11063 offset += TG3_NVM_DIRENT_SIZE) {
11064 if (tg3_nvram_read(tp, offset, &val))
11067 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
11068 TG3_NVM_DIRTYPE_EXTVPD)
11072 if (offset != TG3_NVM_DIR_END) {
11073 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
11074 if (tg3_nvram_read(tp, offset + 4, &offset))
11077 offset = tg3_nvram_logical_addr(tp, offset);
11081 if (!offset || !len) {
11082 offset = TG3_NVM_VPD_OFF;
11083 len = TG3_NVM_VPD_LEN;
11086 buf = kmalloc(len, GFP_KERNEL);
11090 if (magic == TG3_EEPROM_MAGIC) {
11091 for (i = 0; i < len; i += 4) {
11092 /* The data is in little-endian format in NVRAM.
11093 * Use the big-endian read routines to preserve
11094 * the byte order as it exists in NVRAM.
11096 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
11102 unsigned int pos = 0;
11104 ptr = (u8 *)&buf[0];
11105 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
11106 cnt = pci_read_vpd(tp->pdev, pos,
11108 if (cnt == -ETIMEDOUT || cnt == -EINTR)
11126 #define NVRAM_TEST_SIZE 0x100
11127 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
11128 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
11129 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
11130 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
11131 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
11132 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
11133 #define NVRAM_SELFBOOT_HW_SIZE 0x20
11134 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
11136 static int tg3_test_nvram(struct tg3 *tp)
11138 u32 csum, magic, len;
11140 int i, j, k, err = 0, size;
11142 if (tg3_flag(tp, NO_NVRAM))
11145 if (tg3_nvram_read(tp, 0, &magic) != 0)
11148 if (magic == TG3_EEPROM_MAGIC)
11149 size = NVRAM_TEST_SIZE;
11150 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
11151 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
11152 TG3_EEPROM_SB_FORMAT_1) {
11153 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
11154 case TG3_EEPROM_SB_REVISION_0:
11155 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
11157 case TG3_EEPROM_SB_REVISION_2:
11158 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
11160 case TG3_EEPROM_SB_REVISION_3:
11161 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
11163 case TG3_EEPROM_SB_REVISION_4:
11164 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
11166 case TG3_EEPROM_SB_REVISION_5:
11167 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
11169 case TG3_EEPROM_SB_REVISION_6:
11170 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
11177 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11178 size = NVRAM_SELFBOOT_HW_SIZE;
11182 buf = kmalloc(size, GFP_KERNEL);
11187 for (i = 0, j = 0; i < size; i += 4, j++) {
11188 err = tg3_nvram_read_be32(tp, i, &buf[j]);
11195 /* Selfboot format */
11196 magic = be32_to_cpu(buf[0]);
11197 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
11198 TG3_EEPROM_MAGIC_FW) {
11199 u8 *buf8 = (u8 *) buf, csum8 = 0;
11201 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
11202 TG3_EEPROM_SB_REVISION_2) {
11203 /* For rev 2, the csum doesn't include the MBA. */
11204 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
11206 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
11209 for (i = 0; i < size; i++)
11222 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
11223 TG3_EEPROM_MAGIC_HW) {
11224 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
11225 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
11226 u8 *buf8 = (u8 *) buf;
11228 /* Separate the parity bits and the data bytes. */
11229 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
11230 if ((i == 0) || (i == 8)) {
11234 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
11235 parity[k++] = buf8[i] & msk;
11237 } else if (i == 16) {
11241 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
11242 parity[k++] = buf8[i] & msk;
11245 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
11246 parity[k++] = buf8[i] & msk;
11249 data[j++] = buf8[i];
11253 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
11254 u8 hw8 = hweight8(data[i]);
11256 if ((hw8 & 0x1) && parity[i])
11258 else if (!(hw8 & 0x1) && !parity[i])
11267 /* Bootstrap checksum at offset 0x10 */
11268 csum = calc_crc((unsigned char *) buf, 0x10);
11269 if (csum != le32_to_cpu(buf[0x10/4]))
11272 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
11273 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
11274 if (csum != le32_to_cpu(buf[0xfc/4]))
11279 buf = tg3_vpd_readblock(tp, &len);
11283 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
11285 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
11289 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
11292 i += PCI_VPD_LRDT_TAG_SIZE;
11293 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
11294 PCI_VPD_RO_KEYWORD_CHKSUM);
11298 j += PCI_VPD_INFO_FLD_HDR_SIZE;
11300 for (i = 0; i <= j; i++)
11301 csum8 += ((u8 *)buf)[i];
11315 #define TG3_SERDES_TIMEOUT_SEC 2
11316 #define TG3_COPPER_TIMEOUT_SEC 6
11318 static int tg3_test_link(struct tg3 *tp)
11322 if (!netif_running(tp->dev))
11325 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
11326 max = TG3_SERDES_TIMEOUT_SEC;
11328 max = TG3_COPPER_TIMEOUT_SEC;
11330 for (i = 0; i < max; i++) {
11331 if (netif_carrier_ok(tp->dev))
11334 if (msleep_interruptible(1000))
11341 /* Only test the commonly used registers */
11342 static int tg3_test_registers(struct tg3 *tp)
11344 int i, is_5705, is_5750;
11345 u32 offset, read_mask, write_mask, val, save_val, read_val;
11349 #define TG3_FL_5705 0x1
11350 #define TG3_FL_NOT_5705 0x2
11351 #define TG3_FL_NOT_5788 0x4
11352 #define TG3_FL_NOT_5750 0x8
11356 /* MAC Control Registers */
11357 { MAC_MODE, TG3_FL_NOT_5705,
11358 0x00000000, 0x00ef6f8c },
11359 { MAC_MODE, TG3_FL_5705,
11360 0x00000000, 0x01ef6b8c },
11361 { MAC_STATUS, TG3_FL_NOT_5705,
11362 0x03800107, 0x00000000 },
11363 { MAC_STATUS, TG3_FL_5705,
11364 0x03800100, 0x00000000 },
11365 { MAC_ADDR_0_HIGH, 0x0000,
11366 0x00000000, 0x0000ffff },
11367 { MAC_ADDR_0_LOW, 0x0000,
11368 0x00000000, 0xffffffff },
11369 { MAC_RX_MTU_SIZE, 0x0000,
11370 0x00000000, 0x0000ffff },
11371 { MAC_TX_MODE, 0x0000,
11372 0x00000000, 0x00000070 },
11373 { MAC_TX_LENGTHS, 0x0000,
11374 0x00000000, 0x00003fff },
11375 { MAC_RX_MODE, TG3_FL_NOT_5705,
11376 0x00000000, 0x000007fc },
11377 { MAC_RX_MODE, TG3_FL_5705,
11378 0x00000000, 0x000007dc },
11379 { MAC_HASH_REG_0, 0x0000,
11380 0x00000000, 0xffffffff },
11381 { MAC_HASH_REG_1, 0x0000,
11382 0x00000000, 0xffffffff },
11383 { MAC_HASH_REG_2, 0x0000,
11384 0x00000000, 0xffffffff },
11385 { MAC_HASH_REG_3, 0x0000,
11386 0x00000000, 0xffffffff },
11388 /* Receive Data and Receive BD Initiator Control Registers. */
11389 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
11390 0x00000000, 0xffffffff },
11391 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
11392 0x00000000, 0xffffffff },
11393 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
11394 0x00000000, 0x00000003 },
11395 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
11396 0x00000000, 0xffffffff },
11397 { RCVDBDI_STD_BD+0, 0x0000,
11398 0x00000000, 0xffffffff },
11399 { RCVDBDI_STD_BD+4, 0x0000,
11400 0x00000000, 0xffffffff },
11401 { RCVDBDI_STD_BD+8, 0x0000,
11402 0x00000000, 0xffff0002 },
11403 { RCVDBDI_STD_BD+0xc, 0x0000,
11404 0x00000000, 0xffffffff },
11406 /* Receive BD Initiator Control Registers. */
11407 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
11408 0x00000000, 0xffffffff },
11409 { RCVBDI_STD_THRESH, TG3_FL_5705,
11410 0x00000000, 0x000003ff },
11411 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
11412 0x00000000, 0xffffffff },
11414 /* Host Coalescing Control Registers. */
11415 { HOSTCC_MODE, TG3_FL_NOT_5705,
11416 0x00000000, 0x00000004 },
11417 { HOSTCC_MODE, TG3_FL_5705,
11418 0x00000000, 0x000000f6 },
11419 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
11420 0x00000000, 0xffffffff },
11421 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
11422 0x00000000, 0x000003ff },
11423 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
11424 0x00000000, 0xffffffff },
11425 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
11426 0x00000000, 0x000003ff },
11427 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
11428 0x00000000, 0xffffffff },
11429 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11430 0x00000000, 0x000000ff },
11431 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
11432 0x00000000, 0xffffffff },
11433 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11434 0x00000000, 0x000000ff },
11435 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
11436 0x00000000, 0xffffffff },
11437 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
11438 0x00000000, 0xffffffff },
11439 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11440 0x00000000, 0xffffffff },
11441 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11442 0x00000000, 0x000000ff },
11443 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11444 0x00000000, 0xffffffff },
11445 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11446 0x00000000, 0x000000ff },
11447 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
11448 0x00000000, 0xffffffff },
11449 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
11450 0x00000000, 0xffffffff },
11451 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
11452 0x00000000, 0xffffffff },
11453 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
11454 0x00000000, 0xffffffff },
11455 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
11456 0x00000000, 0xffffffff },
11457 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
11458 0xffffffff, 0x00000000 },
11459 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
11460 0xffffffff, 0x00000000 },
11462 /* Buffer Manager Control Registers. */
11463 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
11464 0x00000000, 0x007fff80 },
11465 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
11466 0x00000000, 0x007fffff },
11467 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
11468 0x00000000, 0x0000003f },
11469 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
11470 0x00000000, 0x000001ff },
11471 { BUFMGR_MB_HIGH_WATER, 0x0000,
11472 0x00000000, 0x000001ff },
11473 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
11474 0xffffffff, 0x00000000 },
11475 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
11476 0xffffffff, 0x00000000 },
11478 /* Mailbox Registers */
11479 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
11480 0x00000000, 0x000001ff },
11481 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
11482 0x00000000, 0x000001ff },
11483 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
11484 0x00000000, 0x000007ff },
11485 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
11486 0x00000000, 0x000001ff },
11488 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
11491 is_5705 = is_5750 = 0;
11492 if (tg3_flag(tp, 5705_PLUS)) {
11494 if (tg3_flag(tp, 5750_PLUS))
11498 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
11499 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
11502 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
11505 if (tg3_flag(tp, IS_5788) &&
11506 (reg_tbl[i].flags & TG3_FL_NOT_5788))
11509 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
11512 offset = (u32) reg_tbl[i].offset;
11513 read_mask = reg_tbl[i].read_mask;
11514 write_mask = reg_tbl[i].write_mask;
11516 /* Save the original register content */
11517 save_val = tr32(offset);
11519 /* Determine the read-only value. */
11520 read_val = save_val & read_mask;
11522 /* Write zero to the register, then make sure the read-only bits
11523 * are not changed and the read/write bits are all zeros.
11527 val = tr32(offset);
11529 /* Test the read-only and read/write bits. */
11530 if (((val & read_mask) != read_val) || (val & write_mask))
11533 /* Write ones to all the bits defined by RdMask and WrMask, then
11534 * make sure the read-only bits are not changed and the
11535 * read/write bits are all ones.
11537 tw32(offset, read_mask | write_mask);
11539 val = tr32(offset);
11541 /* Test the read-only bits. */
11542 if ((val & read_mask) != read_val)
11545 /* Test the read/write bits. */
11546 if ((val & write_mask) != write_mask)
11549 tw32(offset, save_val);
11555 if (netif_msg_hw(tp))
11556 netdev_err(tp->dev,
11557 "Register test failed at offset %x\n", offset);
11558 tw32(offset, save_val);
11562 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
11564 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
11568 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
11569 for (j = 0; j < len; j += 4) {
11572 tg3_write_mem(tp, offset + j, test_pattern[i]);
11573 tg3_read_mem(tp, offset + j, &val);
11574 if (val != test_pattern[i])
11581 static int tg3_test_memory(struct tg3 *tp)
11583 static struct mem_entry {
11586 } mem_tbl_570x[] = {
11587 { 0x00000000, 0x00b50},
11588 { 0x00002000, 0x1c000},
11589 { 0xffffffff, 0x00000}
11590 }, mem_tbl_5705[] = {
11591 { 0x00000100, 0x0000c},
11592 { 0x00000200, 0x00008},
11593 { 0x00004000, 0x00800},
11594 { 0x00006000, 0x01000},
11595 { 0x00008000, 0x02000},
11596 { 0x00010000, 0x0e000},
11597 { 0xffffffff, 0x00000}
11598 }, mem_tbl_5755[] = {
11599 { 0x00000200, 0x00008},
11600 { 0x00004000, 0x00800},
11601 { 0x00006000, 0x00800},
11602 { 0x00008000, 0x02000},
11603 { 0x00010000, 0x0c000},
11604 { 0xffffffff, 0x00000}
11605 }, mem_tbl_5906[] = {
11606 { 0x00000200, 0x00008},
11607 { 0x00004000, 0x00400},
11608 { 0x00006000, 0x00400},
11609 { 0x00008000, 0x01000},
11610 { 0x00010000, 0x01000},
11611 { 0xffffffff, 0x00000}
11612 }, mem_tbl_5717[] = {
11613 { 0x00000200, 0x00008},
11614 { 0x00010000, 0x0a000},
11615 { 0x00020000, 0x13c00},
11616 { 0xffffffff, 0x00000}
11617 }, mem_tbl_57765[] = {
11618 { 0x00000200, 0x00008},
11619 { 0x00004000, 0x00800},
11620 { 0x00006000, 0x09800},
11621 { 0x00010000, 0x0a000},
11622 { 0xffffffff, 0x00000}
11624 struct mem_entry *mem_tbl;
11628 if (tg3_flag(tp, 5717_PLUS))
11629 mem_tbl = mem_tbl_5717;
11630 else if (tg3_flag(tp, 57765_CLASS))
11631 mem_tbl = mem_tbl_57765;
11632 else if (tg3_flag(tp, 5755_PLUS))
11633 mem_tbl = mem_tbl_5755;
11634 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11635 mem_tbl = mem_tbl_5906;
11636 else if (tg3_flag(tp, 5705_PLUS))
11637 mem_tbl = mem_tbl_5705;
11639 mem_tbl = mem_tbl_570x;
11641 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
11642 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
11650 #define TG3_TSO_MSS 500
11652 #define TG3_TSO_IP_HDR_LEN 20
11653 #define TG3_TSO_TCP_HDR_LEN 20
11654 #define TG3_TSO_TCP_OPT_LEN 12
11656 static const u8 tg3_tso_header[] = {
11658 0x45, 0x00, 0x00, 0x00,
11659 0x00, 0x00, 0x40, 0x00,
11660 0x40, 0x06, 0x00, 0x00,
11661 0x0a, 0x00, 0x00, 0x01,
11662 0x0a, 0x00, 0x00, 0x02,
11663 0x0d, 0x00, 0xe0, 0x00,
11664 0x00, 0x00, 0x01, 0x00,
11665 0x00, 0x00, 0x02, 0x00,
11666 0x80, 0x10, 0x10, 0x00,
11667 0x14, 0x09, 0x00, 0x00,
11668 0x01, 0x01, 0x08, 0x0a,
11669 0x11, 0x11, 0x11, 0x11,
11670 0x11, 0x11, 0x11, 0x11,
11673 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
11675 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
11676 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
11678 struct sk_buff *skb;
11679 u8 *tx_data, *rx_data;
11681 int num_pkts, tx_len, rx_len, i, err;
11682 struct tg3_rx_buffer_desc *desc;
11683 struct tg3_napi *tnapi, *rnapi;
11684 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
11686 tnapi = &tp->napi[0];
11687 rnapi = &tp->napi[0];
11688 if (tp->irq_cnt > 1) {
11689 if (tg3_flag(tp, ENABLE_RSS))
11690 rnapi = &tp->napi[1];
11691 if (tg3_flag(tp, ENABLE_TSS))
11692 tnapi = &tp->napi[1];
11694 coal_now = tnapi->coal_now | rnapi->coal_now;
11699 skb = netdev_alloc_skb(tp->dev, tx_len);
11703 tx_data = skb_put(skb, tx_len);
11704 memcpy(tx_data, tp->dev->dev_addr, 6);
11705 memset(tx_data + 6, 0x0, 8);
11707 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
11709 if (tso_loopback) {
11710 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
11712 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
11713 TG3_TSO_TCP_OPT_LEN;
11715 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
11716 sizeof(tg3_tso_header));
11719 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
11720 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
11722 /* Set the total length field in the IP header */
11723 iph->tot_len = htons((u16)(mss + hdr_len));
11725 base_flags = (TXD_FLAG_CPU_PRE_DMA |
11726 TXD_FLAG_CPU_POST_DMA);
11728 if (tg3_flag(tp, HW_TSO_1) ||
11729 tg3_flag(tp, HW_TSO_2) ||
11730 tg3_flag(tp, HW_TSO_3)) {
11732 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
11733 th = (struct tcphdr *)&tx_data[val];
11736 base_flags |= TXD_FLAG_TCPUDP_CSUM;
11738 if (tg3_flag(tp, HW_TSO_3)) {
11739 mss |= (hdr_len & 0xc) << 12;
11740 if (hdr_len & 0x10)
11741 base_flags |= 0x00000010;
11742 base_flags |= (hdr_len & 0x3e0) << 5;
11743 } else if (tg3_flag(tp, HW_TSO_2))
11744 mss |= hdr_len << 9;
11745 else if (tg3_flag(tp, HW_TSO_1) ||
11746 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
11747 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
11749 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
11752 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
11755 data_off = ETH_HLEN;
11757 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
11758 tx_len > VLAN_ETH_FRAME_LEN)
11759 base_flags |= TXD_FLAG_JMB_PKT;
11762 for (i = data_off; i < tx_len; i++)
11763 tx_data[i] = (u8) (i & 0xff);
11765 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11766 if (pci_dma_mapping_error(tp->pdev, map)) {
11767 dev_kfree_skb(skb);
11771 val = tnapi->tx_prod;
11772 tnapi->tx_buffers[val].skb = skb;
11773 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
11775 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11780 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11782 budget = tg3_tx_avail(tnapi);
11783 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
11784 base_flags | TXD_FLAG_END, mss, 0)) {
11785 tnapi->tx_buffers[val].skb = NULL;
11786 dev_kfree_skb(skb);
11792 /* Sync BD data before updating mailbox */
11795 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11796 tr32_mailbox(tnapi->prodmbox);
11800 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11801 for (i = 0; i < 35; i++) {
11802 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11807 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11808 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11809 if ((tx_idx == tnapi->tx_prod) &&
11810 (rx_idx == (rx_start_idx + num_pkts)))
11814 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
11815 dev_kfree_skb(skb);
11817 if (tx_idx != tnapi->tx_prod)
11820 if (rx_idx != rx_start_idx + num_pkts)
11824 while (rx_idx != rx_start_idx) {
11825 desc = &rnapi->rx_rcb[rx_start_idx++];
11826 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11827 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11829 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11830 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11833 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
11836 if (!tso_loopback) {
11837 if (rx_len != tx_len)
11840 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
11841 if (opaque_key != RXD_OPAQUE_RING_STD)
11844 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
11847 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
11848 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
11849 >> RXD_TCPCSUM_SHIFT != 0xffff) {
11853 if (opaque_key == RXD_OPAQUE_RING_STD) {
11854 rx_data = tpr->rx_std_buffers[desc_idx].data;
11855 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
11857 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
11858 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
11859 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
11864 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
11865 PCI_DMA_FROMDEVICE);
11867 rx_data += TG3_RX_OFFSET(tp);
11868 for (i = data_off; i < rx_len; i++, val++) {
11869 if (*(rx_data + i) != (u8) (val & 0xff))
11876 /* tg3_free_rings will unmap and free the rx_data */
11881 #define TG3_STD_LOOPBACK_FAILED 1
11882 #define TG3_JMB_LOOPBACK_FAILED 2
11883 #define TG3_TSO_LOOPBACK_FAILED 4
11884 #define TG3_LOOPBACK_FAILED \
11885 (TG3_STD_LOOPBACK_FAILED | \
11886 TG3_JMB_LOOPBACK_FAILED | \
11887 TG3_TSO_LOOPBACK_FAILED)
11889 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
11893 u32 jmb_pkt_sz = 9000;
11896 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
11898 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11899 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11901 if (!netif_running(tp->dev)) {
11902 data[0] = TG3_LOOPBACK_FAILED;
11903 data[1] = TG3_LOOPBACK_FAILED;
11905 data[2] = TG3_LOOPBACK_FAILED;
11909 err = tg3_reset_hw(tp, 1);
11911 data[0] = TG3_LOOPBACK_FAILED;
11912 data[1] = TG3_LOOPBACK_FAILED;
11914 data[2] = TG3_LOOPBACK_FAILED;
11918 if (tg3_flag(tp, ENABLE_RSS)) {
11921 /* Reroute all rx packets to the 1st queue */
11922 for (i = MAC_RSS_INDIR_TBL_0;
11923 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
11927 /* HW errata - mac loopback fails in some cases on 5780.
11928 * Normal traffic and PHY loopback are not affected by
11929 * errata. Also, the MAC loopback test is deprecated for
11930 * all newer ASIC revisions.
11932 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
11933 !tg3_flag(tp, CPMU_PRESENT)) {
11934 tg3_mac_loopback(tp, true);
11936 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11937 data[0] |= TG3_STD_LOOPBACK_FAILED;
11939 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11940 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
11941 data[0] |= TG3_JMB_LOOPBACK_FAILED;
11943 tg3_mac_loopback(tp, false);
11946 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11947 !tg3_flag(tp, USE_PHYLIB)) {
11950 tg3_phy_lpbk_set(tp, 0, false);
11952 /* Wait for link */
11953 for (i = 0; i < 100; i++) {
11954 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11959 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11960 data[1] |= TG3_STD_LOOPBACK_FAILED;
11961 if (tg3_flag(tp, TSO_CAPABLE) &&
11962 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11963 data[1] |= TG3_TSO_LOOPBACK_FAILED;
11964 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11965 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
11966 data[1] |= TG3_JMB_LOOPBACK_FAILED;
11969 tg3_phy_lpbk_set(tp, 0, true);
11971 /* All link indications report up, but the hardware
11972 * isn't really ready for about 20 msec. Double it
11977 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11978 data[2] |= TG3_STD_LOOPBACK_FAILED;
11979 if (tg3_flag(tp, TSO_CAPABLE) &&
11980 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11981 data[2] |= TG3_TSO_LOOPBACK_FAILED;
11982 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11983 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
11984 data[2] |= TG3_JMB_LOOPBACK_FAILED;
11987 /* Re-enable gphy autopowerdown. */
11988 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11989 tg3_phy_toggle_apd(tp, true);
11992 err = (data[0] | data[1] | data[2]) ? -EIO : 0;
11995 tp->phy_flags |= eee_cap;
12000 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
12003 struct tg3 *tp = netdev_priv(dev);
12004 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
12006 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
12007 tg3_power_up(tp)) {
12008 etest->flags |= ETH_TEST_FL_FAILED;
12009 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
12013 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
12015 if (tg3_test_nvram(tp) != 0) {
12016 etest->flags |= ETH_TEST_FL_FAILED;
12019 if (!doextlpbk && tg3_test_link(tp)) {
12020 etest->flags |= ETH_TEST_FL_FAILED;
12023 if (etest->flags & ETH_TEST_FL_OFFLINE) {
12024 int err, err2 = 0, irq_sync = 0;
12026 if (netif_running(dev)) {
12028 tg3_netif_stop(tp);
12032 tg3_full_lock(tp, irq_sync);
12034 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
12035 err = tg3_nvram_lock(tp);
12036 tg3_halt_cpu(tp, RX_CPU_BASE);
12037 if (!tg3_flag(tp, 5705_PLUS))
12038 tg3_halt_cpu(tp, TX_CPU_BASE);
12040 tg3_nvram_unlock(tp);
12042 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
12045 if (tg3_test_registers(tp) != 0) {
12046 etest->flags |= ETH_TEST_FL_FAILED;
12050 if (tg3_test_memory(tp) != 0) {
12051 etest->flags |= ETH_TEST_FL_FAILED;
12056 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
12058 if (tg3_test_loopback(tp, &data[4], doextlpbk))
12059 etest->flags |= ETH_TEST_FL_FAILED;
12061 tg3_full_unlock(tp);
12063 if (tg3_test_interrupt(tp) != 0) {
12064 etest->flags |= ETH_TEST_FL_FAILED;
12068 tg3_full_lock(tp, 0);
12070 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12071 if (netif_running(dev)) {
12072 tg3_flag_set(tp, INIT_COMPLETE);
12073 err2 = tg3_restart_hw(tp, 1);
12075 tg3_netif_start(tp);
12078 tg3_full_unlock(tp);
12080 if (irq_sync && !err2)
12083 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
12084 tg3_power_down(tp);
12088 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12090 struct mii_ioctl_data *data = if_mii(ifr);
12091 struct tg3 *tp = netdev_priv(dev);
12094 if (tg3_flag(tp, USE_PHYLIB)) {
12095 struct phy_device *phydev;
12096 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12098 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
12099 return phy_mii_ioctl(phydev, ifr, cmd);
12104 data->phy_id = tp->phy_addr;
12107 case SIOCGMIIREG: {
12110 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12111 break; /* We have no PHY */
12113 if (!netif_running(dev))
12116 spin_lock_bh(&tp->lock);
12117 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
12118 spin_unlock_bh(&tp->lock);
12120 data->val_out = mii_regval;
12126 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12127 break; /* We have no PHY */
12129 if (!netif_running(dev))
12132 spin_lock_bh(&tp->lock);
12133 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
12134 spin_unlock_bh(&tp->lock);
12142 return -EOPNOTSUPP;
12145 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
12147 struct tg3 *tp = netdev_priv(dev);
12149 memcpy(ec, &tp->coal, sizeof(*ec));
12153 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
12155 struct tg3 *tp = netdev_priv(dev);
12156 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
12157 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
12159 if (!tg3_flag(tp, 5705_PLUS)) {
12160 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
12161 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
12162 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
12163 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
12166 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
12167 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
12168 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
12169 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
12170 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
12171 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
12172 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
12173 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
12174 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
12175 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
12178 /* No rx interrupts will be generated if both are zero */
12179 if ((ec->rx_coalesce_usecs == 0) &&
12180 (ec->rx_max_coalesced_frames == 0))
12183 /* No tx interrupts will be generated if both are zero */
12184 if ((ec->tx_coalesce_usecs == 0) &&
12185 (ec->tx_max_coalesced_frames == 0))
12188 /* Only copy relevant parameters, ignore all others. */
12189 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
12190 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
12191 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
12192 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
12193 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
12194 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
12195 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
12196 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
12197 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
12199 if (netif_running(dev)) {
12200 tg3_full_lock(tp, 0);
12201 __tg3_set_coalesce(tp, &tp->coal);
12202 tg3_full_unlock(tp);
12207 static const struct ethtool_ops tg3_ethtool_ops = {
12208 .get_settings = tg3_get_settings,
12209 .set_settings = tg3_set_settings,
12210 .get_drvinfo = tg3_get_drvinfo,
12211 .get_regs_len = tg3_get_regs_len,
12212 .get_regs = tg3_get_regs,
12213 .get_wol = tg3_get_wol,
12214 .set_wol = tg3_set_wol,
12215 .get_msglevel = tg3_get_msglevel,
12216 .set_msglevel = tg3_set_msglevel,
12217 .nway_reset = tg3_nway_reset,
12218 .get_link = ethtool_op_get_link,
12219 .get_eeprom_len = tg3_get_eeprom_len,
12220 .get_eeprom = tg3_get_eeprom,
12221 .set_eeprom = tg3_set_eeprom,
12222 .get_ringparam = tg3_get_ringparam,
12223 .set_ringparam = tg3_set_ringparam,
12224 .get_pauseparam = tg3_get_pauseparam,
12225 .set_pauseparam = tg3_set_pauseparam,
12226 .self_test = tg3_self_test,
12227 .get_strings = tg3_get_strings,
12228 .set_phys_id = tg3_set_phys_id,
12229 .get_ethtool_stats = tg3_get_ethtool_stats,
12230 .get_coalesce = tg3_get_coalesce,
12231 .set_coalesce = tg3_set_coalesce,
12232 .get_sset_count = tg3_get_sset_count,
12233 .get_rxnfc = tg3_get_rxnfc,
12234 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
12235 .get_rxfh_indir = tg3_get_rxfh_indir,
12236 .set_rxfh_indir = tg3_set_rxfh_indir,
12237 .get_ts_info = ethtool_op_get_ts_info,
12240 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
12241 struct rtnl_link_stats64 *stats)
12243 struct tg3 *tp = netdev_priv(dev);
12246 return &tp->net_stats_prev;
12248 spin_lock_bh(&tp->lock);
12249 tg3_get_nstats(tp, stats);
12250 spin_unlock_bh(&tp->lock);
12255 static void tg3_set_rx_mode(struct net_device *dev)
12257 struct tg3 *tp = netdev_priv(dev);
12259 if (!netif_running(dev))
12262 tg3_full_lock(tp, 0);
12263 __tg3_set_rx_mode(dev);
12264 tg3_full_unlock(tp);
12267 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
12270 dev->mtu = new_mtu;
12272 if (new_mtu > ETH_DATA_LEN) {
12273 if (tg3_flag(tp, 5780_CLASS)) {
12274 netdev_update_features(dev);
12275 tg3_flag_clear(tp, TSO_CAPABLE);
12277 tg3_flag_set(tp, JUMBO_RING_ENABLE);
12280 if (tg3_flag(tp, 5780_CLASS)) {
12281 tg3_flag_set(tp, TSO_CAPABLE);
12282 netdev_update_features(dev);
12284 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
12288 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
12290 struct tg3 *tp = netdev_priv(dev);
12291 int err, reset_phy = 0;
12293 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
12296 if (!netif_running(dev)) {
12297 /* We'll just catch it later when the
12300 tg3_set_mtu(dev, tp, new_mtu);
12306 tg3_netif_stop(tp);
12308 tg3_full_lock(tp, 1);
12310 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12312 tg3_set_mtu(dev, tp, new_mtu);
12314 /* Reset PHY, otherwise the read DMA engine will be in a mode that
12315 * breaks all requests to 256 bytes.
12317 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
12320 err = tg3_restart_hw(tp, reset_phy);
12323 tg3_netif_start(tp);
12325 tg3_full_unlock(tp);
12333 static const struct net_device_ops tg3_netdev_ops = {
12334 .ndo_open = tg3_open,
12335 .ndo_stop = tg3_close,
12336 .ndo_start_xmit = tg3_start_xmit,
12337 .ndo_get_stats64 = tg3_get_stats64,
12338 .ndo_validate_addr = eth_validate_addr,
12339 .ndo_set_rx_mode = tg3_set_rx_mode,
12340 .ndo_set_mac_address = tg3_set_mac_addr,
12341 .ndo_do_ioctl = tg3_ioctl,
12342 .ndo_tx_timeout = tg3_tx_timeout,
12343 .ndo_change_mtu = tg3_change_mtu,
12344 .ndo_fix_features = tg3_fix_features,
12345 .ndo_set_features = tg3_set_features,
12346 #ifdef CONFIG_NET_POLL_CONTROLLER
12347 .ndo_poll_controller = tg3_poll_controller,
12351 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
12353 u32 cursize, val, magic;
12355 tp->nvram_size = EEPROM_CHIP_SIZE;
12357 if (tg3_nvram_read(tp, 0, &magic) != 0)
12360 if ((magic != TG3_EEPROM_MAGIC) &&
12361 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
12362 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
12366 * Size the chip by reading offsets at increasing powers of two.
12367 * When we encounter our validation signature, we know the addressing
12368 * has wrapped around, and thus have our chip size.
12372 while (cursize < tp->nvram_size) {
12373 if (tg3_nvram_read(tp, cursize, &val) != 0)
12382 tp->nvram_size = cursize;
12385 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
12389 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
12392 /* Selfboot format */
12393 if (val != TG3_EEPROM_MAGIC) {
12394 tg3_get_eeprom_size(tp);
12398 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
12400 /* This is confusing. We want to operate on the
12401 * 16-bit value at offset 0xf2. The tg3_nvram_read()
12402 * call will read from NVRAM and byteswap the data
12403 * according to the byteswapping settings for all
12404 * other register accesses. This ensures the data we
12405 * want will always reside in the lower 16-bits.
12406 * However, the data in NVRAM is in LE format, which
12407 * means the data from the NVRAM read will always be
12408 * opposite the endianness of the CPU. The 16-bit
12409 * byteswap then brings the data to CPU endianness.
12411 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
12415 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12418 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
12422 nvcfg1 = tr32(NVRAM_CFG1);
12423 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
12424 tg3_flag_set(tp, FLASH);
12426 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12427 tw32(NVRAM_CFG1, nvcfg1);
12430 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12431 tg3_flag(tp, 5780_CLASS)) {
12432 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
12433 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
12434 tp->nvram_jedecnum = JEDEC_ATMEL;
12435 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12436 tg3_flag_set(tp, NVRAM_BUFFERED);
12438 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
12439 tp->nvram_jedecnum = JEDEC_ATMEL;
12440 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
12442 case FLASH_VENDOR_ATMEL_EEPROM:
12443 tp->nvram_jedecnum = JEDEC_ATMEL;
12444 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12445 tg3_flag_set(tp, NVRAM_BUFFERED);
12447 case FLASH_VENDOR_ST:
12448 tp->nvram_jedecnum = JEDEC_ST;
12449 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
12450 tg3_flag_set(tp, NVRAM_BUFFERED);
12452 case FLASH_VENDOR_SAIFUN:
12453 tp->nvram_jedecnum = JEDEC_SAIFUN;
12454 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
12456 case FLASH_VENDOR_SST_SMALL:
12457 case FLASH_VENDOR_SST_LARGE:
12458 tp->nvram_jedecnum = JEDEC_SST;
12459 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
12463 tp->nvram_jedecnum = JEDEC_ATMEL;
12464 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12465 tg3_flag_set(tp, NVRAM_BUFFERED);
12469 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
12471 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
12472 case FLASH_5752PAGE_SIZE_256:
12473 tp->nvram_pagesize = 256;
12475 case FLASH_5752PAGE_SIZE_512:
12476 tp->nvram_pagesize = 512;
12478 case FLASH_5752PAGE_SIZE_1K:
12479 tp->nvram_pagesize = 1024;
12481 case FLASH_5752PAGE_SIZE_2K:
12482 tp->nvram_pagesize = 2048;
12484 case FLASH_5752PAGE_SIZE_4K:
12485 tp->nvram_pagesize = 4096;
12487 case FLASH_5752PAGE_SIZE_264:
12488 tp->nvram_pagesize = 264;
12490 case FLASH_5752PAGE_SIZE_528:
12491 tp->nvram_pagesize = 528;
12496 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
12500 nvcfg1 = tr32(NVRAM_CFG1);
12502 /* NVRAM protection for TPM */
12503 if (nvcfg1 & (1 << 27))
12504 tg3_flag_set(tp, PROTECTED_NVRAM);
12506 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12507 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
12508 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
12509 tp->nvram_jedecnum = JEDEC_ATMEL;
12510 tg3_flag_set(tp, NVRAM_BUFFERED);
12512 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12513 tp->nvram_jedecnum = JEDEC_ATMEL;
12514 tg3_flag_set(tp, NVRAM_BUFFERED);
12515 tg3_flag_set(tp, FLASH);
12517 case FLASH_5752VENDOR_ST_M45PE10:
12518 case FLASH_5752VENDOR_ST_M45PE20:
12519 case FLASH_5752VENDOR_ST_M45PE40:
12520 tp->nvram_jedecnum = JEDEC_ST;
12521 tg3_flag_set(tp, NVRAM_BUFFERED);
12522 tg3_flag_set(tp, FLASH);
12526 if (tg3_flag(tp, FLASH)) {
12527 tg3_nvram_get_pagesize(tp, nvcfg1);
12529 /* For eeprom, set pagesize to maximum eeprom size */
12530 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12532 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12533 tw32(NVRAM_CFG1, nvcfg1);
12537 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
12539 u32 nvcfg1, protect = 0;
12541 nvcfg1 = tr32(NVRAM_CFG1);
12543 /* NVRAM protection for TPM */
12544 if (nvcfg1 & (1 << 27)) {
12545 tg3_flag_set(tp, PROTECTED_NVRAM);
12549 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12551 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12552 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12553 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12554 case FLASH_5755VENDOR_ATMEL_FLASH_5:
12555 tp->nvram_jedecnum = JEDEC_ATMEL;
12556 tg3_flag_set(tp, NVRAM_BUFFERED);
12557 tg3_flag_set(tp, FLASH);
12558 tp->nvram_pagesize = 264;
12559 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
12560 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
12561 tp->nvram_size = (protect ? 0x3e200 :
12562 TG3_NVRAM_SIZE_512KB);
12563 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
12564 tp->nvram_size = (protect ? 0x1f200 :
12565 TG3_NVRAM_SIZE_256KB);
12567 tp->nvram_size = (protect ? 0x1f200 :
12568 TG3_NVRAM_SIZE_128KB);
12570 case FLASH_5752VENDOR_ST_M45PE10:
12571 case FLASH_5752VENDOR_ST_M45PE20:
12572 case FLASH_5752VENDOR_ST_M45PE40:
12573 tp->nvram_jedecnum = JEDEC_ST;
12574 tg3_flag_set(tp, NVRAM_BUFFERED);
12575 tg3_flag_set(tp, FLASH);
12576 tp->nvram_pagesize = 256;
12577 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
12578 tp->nvram_size = (protect ?
12579 TG3_NVRAM_SIZE_64KB :
12580 TG3_NVRAM_SIZE_128KB);
12581 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
12582 tp->nvram_size = (protect ?
12583 TG3_NVRAM_SIZE_64KB :
12584 TG3_NVRAM_SIZE_256KB);
12586 tp->nvram_size = (protect ?
12587 TG3_NVRAM_SIZE_128KB :
12588 TG3_NVRAM_SIZE_512KB);
12593 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
12597 nvcfg1 = tr32(NVRAM_CFG1);
12599 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12600 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
12601 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12602 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
12603 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12604 tp->nvram_jedecnum = JEDEC_ATMEL;
12605 tg3_flag_set(tp, NVRAM_BUFFERED);
12606 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12608 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12609 tw32(NVRAM_CFG1, nvcfg1);
12611 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12612 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12613 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12614 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12615 tp->nvram_jedecnum = JEDEC_ATMEL;
12616 tg3_flag_set(tp, NVRAM_BUFFERED);
12617 tg3_flag_set(tp, FLASH);
12618 tp->nvram_pagesize = 264;
12620 case FLASH_5752VENDOR_ST_M45PE10:
12621 case FLASH_5752VENDOR_ST_M45PE20:
12622 case FLASH_5752VENDOR_ST_M45PE40:
12623 tp->nvram_jedecnum = JEDEC_ST;
12624 tg3_flag_set(tp, NVRAM_BUFFERED);
12625 tg3_flag_set(tp, FLASH);
12626 tp->nvram_pagesize = 256;
12631 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
12633 u32 nvcfg1, protect = 0;
12635 nvcfg1 = tr32(NVRAM_CFG1);
12637 /* NVRAM protection for TPM */
12638 if (nvcfg1 & (1 << 27)) {
12639 tg3_flag_set(tp, PROTECTED_NVRAM);
12643 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12645 case FLASH_5761VENDOR_ATMEL_ADB021D:
12646 case FLASH_5761VENDOR_ATMEL_ADB041D:
12647 case FLASH_5761VENDOR_ATMEL_ADB081D:
12648 case FLASH_5761VENDOR_ATMEL_ADB161D:
12649 case FLASH_5761VENDOR_ATMEL_MDB021D:
12650 case FLASH_5761VENDOR_ATMEL_MDB041D:
12651 case FLASH_5761VENDOR_ATMEL_MDB081D:
12652 case FLASH_5761VENDOR_ATMEL_MDB161D:
12653 tp->nvram_jedecnum = JEDEC_ATMEL;
12654 tg3_flag_set(tp, NVRAM_BUFFERED);
12655 tg3_flag_set(tp, FLASH);
12656 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12657 tp->nvram_pagesize = 256;
12659 case FLASH_5761VENDOR_ST_A_M45PE20:
12660 case FLASH_5761VENDOR_ST_A_M45PE40:
12661 case FLASH_5761VENDOR_ST_A_M45PE80:
12662 case FLASH_5761VENDOR_ST_A_M45PE16:
12663 case FLASH_5761VENDOR_ST_M_M45PE20:
12664 case FLASH_5761VENDOR_ST_M_M45PE40:
12665 case FLASH_5761VENDOR_ST_M_M45PE80:
12666 case FLASH_5761VENDOR_ST_M_M45PE16:
12667 tp->nvram_jedecnum = JEDEC_ST;
12668 tg3_flag_set(tp, NVRAM_BUFFERED);
12669 tg3_flag_set(tp, FLASH);
12670 tp->nvram_pagesize = 256;
12675 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
12678 case FLASH_5761VENDOR_ATMEL_ADB161D:
12679 case FLASH_5761VENDOR_ATMEL_MDB161D:
12680 case FLASH_5761VENDOR_ST_A_M45PE16:
12681 case FLASH_5761VENDOR_ST_M_M45PE16:
12682 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
12684 case FLASH_5761VENDOR_ATMEL_ADB081D:
12685 case FLASH_5761VENDOR_ATMEL_MDB081D:
12686 case FLASH_5761VENDOR_ST_A_M45PE80:
12687 case FLASH_5761VENDOR_ST_M_M45PE80:
12688 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12690 case FLASH_5761VENDOR_ATMEL_ADB041D:
12691 case FLASH_5761VENDOR_ATMEL_MDB041D:
12692 case FLASH_5761VENDOR_ST_A_M45PE40:
12693 case FLASH_5761VENDOR_ST_M_M45PE40:
12694 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12696 case FLASH_5761VENDOR_ATMEL_ADB021D:
12697 case FLASH_5761VENDOR_ATMEL_MDB021D:
12698 case FLASH_5761VENDOR_ST_A_M45PE20:
12699 case FLASH_5761VENDOR_ST_M_M45PE20:
12700 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12706 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
12708 tp->nvram_jedecnum = JEDEC_ATMEL;
12709 tg3_flag_set(tp, NVRAM_BUFFERED);
12710 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12713 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12717 nvcfg1 = tr32(NVRAM_CFG1);
12719 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12720 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12721 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12722 tp->nvram_jedecnum = JEDEC_ATMEL;
12723 tg3_flag_set(tp, NVRAM_BUFFERED);
12724 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12726 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12727 tw32(NVRAM_CFG1, nvcfg1);
12729 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12730 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12731 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12732 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12733 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12734 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12735 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12736 tp->nvram_jedecnum = JEDEC_ATMEL;
12737 tg3_flag_set(tp, NVRAM_BUFFERED);
12738 tg3_flag_set(tp, FLASH);
12740 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12741 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12742 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12743 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12744 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12746 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12747 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12748 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12750 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12751 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12752 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12756 case FLASH_5752VENDOR_ST_M45PE10:
12757 case FLASH_5752VENDOR_ST_M45PE20:
12758 case FLASH_5752VENDOR_ST_M45PE40:
12759 tp->nvram_jedecnum = JEDEC_ST;
12760 tg3_flag_set(tp, NVRAM_BUFFERED);
12761 tg3_flag_set(tp, FLASH);
12763 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12764 case FLASH_5752VENDOR_ST_M45PE10:
12765 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12767 case FLASH_5752VENDOR_ST_M45PE20:
12768 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12770 case FLASH_5752VENDOR_ST_M45PE40:
12771 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12776 tg3_flag_set(tp, NO_NVRAM);
12780 tg3_nvram_get_pagesize(tp, nvcfg1);
12781 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12782 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12786 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12790 nvcfg1 = tr32(NVRAM_CFG1);
12792 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12793 case FLASH_5717VENDOR_ATMEL_EEPROM:
12794 case FLASH_5717VENDOR_MICRO_EEPROM:
12795 tp->nvram_jedecnum = JEDEC_ATMEL;
12796 tg3_flag_set(tp, NVRAM_BUFFERED);
12797 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12799 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12800 tw32(NVRAM_CFG1, nvcfg1);
12802 case FLASH_5717VENDOR_ATMEL_MDB011D:
12803 case FLASH_5717VENDOR_ATMEL_ADB011B:
12804 case FLASH_5717VENDOR_ATMEL_ADB011D:
12805 case FLASH_5717VENDOR_ATMEL_MDB021D:
12806 case FLASH_5717VENDOR_ATMEL_ADB021B:
12807 case FLASH_5717VENDOR_ATMEL_ADB021D:
12808 case FLASH_5717VENDOR_ATMEL_45USPT:
12809 tp->nvram_jedecnum = JEDEC_ATMEL;
12810 tg3_flag_set(tp, NVRAM_BUFFERED);
12811 tg3_flag_set(tp, FLASH);
12813 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12814 case FLASH_5717VENDOR_ATMEL_MDB021D:
12815 /* Detect size with tg3_nvram_get_size() */
12817 case FLASH_5717VENDOR_ATMEL_ADB021B:
12818 case FLASH_5717VENDOR_ATMEL_ADB021D:
12819 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12822 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12826 case FLASH_5717VENDOR_ST_M_M25PE10:
12827 case FLASH_5717VENDOR_ST_A_M25PE10:
12828 case FLASH_5717VENDOR_ST_M_M45PE10:
12829 case FLASH_5717VENDOR_ST_A_M45PE10:
12830 case FLASH_5717VENDOR_ST_M_M25PE20:
12831 case FLASH_5717VENDOR_ST_A_M25PE20:
12832 case FLASH_5717VENDOR_ST_M_M45PE20:
12833 case FLASH_5717VENDOR_ST_A_M45PE20:
12834 case FLASH_5717VENDOR_ST_25USPT:
12835 case FLASH_5717VENDOR_ST_45USPT:
12836 tp->nvram_jedecnum = JEDEC_ST;
12837 tg3_flag_set(tp, NVRAM_BUFFERED);
12838 tg3_flag_set(tp, FLASH);
12840 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12841 case FLASH_5717VENDOR_ST_M_M25PE20:
12842 case FLASH_5717VENDOR_ST_M_M45PE20:
12843 /* Detect size with tg3_nvram_get_size() */
12845 case FLASH_5717VENDOR_ST_A_M25PE20:
12846 case FLASH_5717VENDOR_ST_A_M45PE20:
12847 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12850 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12855 tg3_flag_set(tp, NO_NVRAM);
12859 tg3_nvram_get_pagesize(tp, nvcfg1);
12860 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12861 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12864 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12866 u32 nvcfg1, nvmpinstrp;
12868 nvcfg1 = tr32(NVRAM_CFG1);
12869 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
12871 switch (nvmpinstrp) {
12872 case FLASH_5720_EEPROM_HD:
12873 case FLASH_5720_EEPROM_LD:
12874 tp->nvram_jedecnum = JEDEC_ATMEL;
12875 tg3_flag_set(tp, NVRAM_BUFFERED);
12877 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12878 tw32(NVRAM_CFG1, nvcfg1);
12879 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
12880 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12882 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
12884 case FLASH_5720VENDOR_M_ATMEL_DB011D:
12885 case FLASH_5720VENDOR_A_ATMEL_DB011B:
12886 case FLASH_5720VENDOR_A_ATMEL_DB011D:
12887 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12888 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12889 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12890 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12891 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12892 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12893 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12894 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12895 case FLASH_5720VENDOR_ATMEL_45USPT:
12896 tp->nvram_jedecnum = JEDEC_ATMEL;
12897 tg3_flag_set(tp, NVRAM_BUFFERED);
12898 tg3_flag_set(tp, FLASH);
12900 switch (nvmpinstrp) {
12901 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12902 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12903 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12904 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12906 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12907 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12908 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12909 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12911 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12912 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12913 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12916 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12920 case FLASH_5720VENDOR_M_ST_M25PE10:
12921 case FLASH_5720VENDOR_M_ST_M45PE10:
12922 case FLASH_5720VENDOR_A_ST_M25PE10:
12923 case FLASH_5720VENDOR_A_ST_M45PE10:
12924 case FLASH_5720VENDOR_M_ST_M25PE20:
12925 case FLASH_5720VENDOR_M_ST_M45PE20:
12926 case FLASH_5720VENDOR_A_ST_M25PE20:
12927 case FLASH_5720VENDOR_A_ST_M45PE20:
12928 case FLASH_5720VENDOR_M_ST_M25PE40:
12929 case FLASH_5720VENDOR_M_ST_M45PE40:
12930 case FLASH_5720VENDOR_A_ST_M25PE40:
12931 case FLASH_5720VENDOR_A_ST_M45PE40:
12932 case FLASH_5720VENDOR_M_ST_M25PE80:
12933 case FLASH_5720VENDOR_M_ST_M45PE80:
12934 case FLASH_5720VENDOR_A_ST_M25PE80:
12935 case FLASH_5720VENDOR_A_ST_M45PE80:
12936 case FLASH_5720VENDOR_ST_25USPT:
12937 case FLASH_5720VENDOR_ST_45USPT:
12938 tp->nvram_jedecnum = JEDEC_ST;
12939 tg3_flag_set(tp, NVRAM_BUFFERED);
12940 tg3_flag_set(tp, FLASH);
12942 switch (nvmpinstrp) {
12943 case FLASH_5720VENDOR_M_ST_M25PE20:
12944 case FLASH_5720VENDOR_M_ST_M45PE20:
12945 case FLASH_5720VENDOR_A_ST_M25PE20:
12946 case FLASH_5720VENDOR_A_ST_M45PE20:
12947 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12949 case FLASH_5720VENDOR_M_ST_M25PE40:
12950 case FLASH_5720VENDOR_M_ST_M45PE40:
12951 case FLASH_5720VENDOR_A_ST_M25PE40:
12952 case FLASH_5720VENDOR_A_ST_M45PE40:
12953 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12955 case FLASH_5720VENDOR_M_ST_M25PE80:
12956 case FLASH_5720VENDOR_M_ST_M45PE80:
12957 case FLASH_5720VENDOR_A_ST_M25PE80:
12958 case FLASH_5720VENDOR_A_ST_M45PE80:
12959 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12962 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12967 tg3_flag_set(tp, NO_NVRAM);
12971 tg3_nvram_get_pagesize(tp, nvcfg1);
12972 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12973 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12976 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12977 static void __devinit tg3_nvram_init(struct tg3 *tp)
12979 tw32_f(GRC_EEPROM_ADDR,
12980 (EEPROM_ADDR_FSM_RESET |
12981 (EEPROM_DEFAULT_CLOCK_PERIOD <<
12982 EEPROM_ADDR_CLKPERD_SHIFT)));
12986 /* Enable seeprom accesses. */
12987 tw32_f(GRC_LOCAL_CTRL,
12988 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12991 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12992 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12993 tg3_flag_set(tp, NVRAM);
12995 if (tg3_nvram_lock(tp)) {
12996 netdev_warn(tp->dev,
12997 "Cannot get nvram lock, %s failed\n",
13001 tg3_enable_nvram_access(tp);
13003 tp->nvram_size = 0;
13005 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13006 tg3_get_5752_nvram_info(tp);
13007 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13008 tg3_get_5755_nvram_info(tp);
13009 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13011 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13012 tg3_get_5787_nvram_info(tp);
13013 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
13014 tg3_get_5761_nvram_info(tp);
13015 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13016 tg3_get_5906_nvram_info(tp);
13017 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13018 tg3_flag(tp, 57765_CLASS))
13019 tg3_get_57780_nvram_info(tp);
13020 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13021 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13022 tg3_get_5717_nvram_info(tp);
13023 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13024 tg3_get_5720_nvram_info(tp);
13026 tg3_get_nvram_info(tp);
13028 if (tp->nvram_size == 0)
13029 tg3_get_nvram_size(tp);
13031 tg3_disable_nvram_access(tp);
13032 tg3_nvram_unlock(tp);
13035 tg3_flag_clear(tp, NVRAM);
13036 tg3_flag_clear(tp, NVRAM_BUFFERED);
13038 tg3_get_eeprom_size(tp);
13042 struct subsys_tbl_ent {
13043 u16 subsys_vendor, subsys_devid;
13047 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
13048 /* Broadcom boards. */
13049 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13050 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
13051 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13052 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
13053 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13054 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
13055 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13056 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
13057 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13058 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
13059 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13060 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
13061 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13062 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
13063 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13064 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
13065 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13066 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
13067 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13068 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
13069 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13070 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
13073 { TG3PCI_SUBVENDOR_ID_3COM,
13074 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
13075 { TG3PCI_SUBVENDOR_ID_3COM,
13076 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
13077 { TG3PCI_SUBVENDOR_ID_3COM,
13078 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
13079 { TG3PCI_SUBVENDOR_ID_3COM,
13080 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
13081 { TG3PCI_SUBVENDOR_ID_3COM,
13082 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
13085 { TG3PCI_SUBVENDOR_ID_DELL,
13086 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
13087 { TG3PCI_SUBVENDOR_ID_DELL,
13088 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
13089 { TG3PCI_SUBVENDOR_ID_DELL,
13090 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
13091 { TG3PCI_SUBVENDOR_ID_DELL,
13092 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
13094 /* Compaq boards. */
13095 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13096 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
13097 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13098 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
13099 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13100 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
13101 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13102 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
13103 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13104 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
13107 { TG3PCI_SUBVENDOR_ID_IBM,
13108 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
13111 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
13115 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
13116 if ((subsys_id_to_phy_id[i].subsys_vendor ==
13117 tp->pdev->subsystem_vendor) &&
13118 (subsys_id_to_phy_id[i].subsys_devid ==
13119 tp->pdev->subsystem_device))
13120 return &subsys_id_to_phy_id[i];
13125 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
13129 tp->phy_id = TG3_PHY_ID_INVALID;
13130 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13132 /* Assume an onboard device and WOL capable by default. */
13133 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13134 tg3_flag_set(tp, WOL_CAP);
13136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13137 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
13138 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13139 tg3_flag_set(tp, IS_NIC);
13141 val = tr32(VCPU_CFGSHDW);
13142 if (val & VCPU_CFGSHDW_ASPM_DBNC)
13143 tg3_flag_set(tp, ASPM_WORKAROUND);
13144 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
13145 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
13146 tg3_flag_set(tp, WOL_ENABLE);
13147 device_set_wakeup_enable(&tp->pdev->dev, true);
13152 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
13153 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
13154 u32 nic_cfg, led_cfg;
13155 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
13156 int eeprom_phy_serdes = 0;
13158 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
13159 tp->nic_sram_data_cfg = nic_cfg;
13161 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
13162 ver >>= NIC_SRAM_DATA_VER_SHIFT;
13163 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13164 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13165 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
13166 (ver > 0) && (ver < 0x100))
13167 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
13169 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13170 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
13172 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
13173 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
13174 eeprom_phy_serdes = 1;
13176 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
13177 if (nic_phy_id != 0) {
13178 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
13179 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
13181 eeprom_phy_id = (id1 >> 16) << 10;
13182 eeprom_phy_id |= (id2 & 0xfc00) << 16;
13183 eeprom_phy_id |= (id2 & 0x03ff) << 0;
13187 tp->phy_id = eeprom_phy_id;
13188 if (eeprom_phy_serdes) {
13189 if (!tg3_flag(tp, 5705_PLUS))
13190 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13192 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
13195 if (tg3_flag(tp, 5750_PLUS))
13196 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
13197 SHASTA_EXT_LED_MODE_MASK);
13199 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
13203 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
13204 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13207 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
13208 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13211 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
13212 tp->led_ctrl = LED_CTRL_MODE_MAC;
13214 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
13215 * read on some older 5700/5701 bootcode.
13217 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
13219 GET_ASIC_REV(tp->pci_chip_rev_id) ==
13221 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13225 case SHASTA_EXT_LED_SHARED:
13226 tp->led_ctrl = LED_CTRL_MODE_SHARED;
13227 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
13228 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
13229 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13230 LED_CTRL_MODE_PHY_2);
13233 case SHASTA_EXT_LED_MAC:
13234 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
13237 case SHASTA_EXT_LED_COMBO:
13238 tp->led_ctrl = LED_CTRL_MODE_COMBO;
13239 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
13240 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13241 LED_CTRL_MODE_PHY_2);
13246 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13247 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
13248 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
13249 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13251 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
13252 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13254 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
13255 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13256 if ((tp->pdev->subsystem_vendor ==
13257 PCI_VENDOR_ID_ARIMA) &&
13258 (tp->pdev->subsystem_device == 0x205a ||
13259 tp->pdev->subsystem_device == 0x2063))
13260 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13262 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13263 tg3_flag_set(tp, IS_NIC);
13266 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
13267 tg3_flag_set(tp, ENABLE_ASF);
13268 if (tg3_flag(tp, 5750_PLUS))
13269 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
13272 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
13273 tg3_flag(tp, 5750_PLUS))
13274 tg3_flag_set(tp, ENABLE_APE);
13276 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
13277 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
13278 tg3_flag_clear(tp, WOL_CAP);
13280 if (tg3_flag(tp, WOL_CAP) &&
13281 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
13282 tg3_flag_set(tp, WOL_ENABLE);
13283 device_set_wakeup_enable(&tp->pdev->dev, true);
13286 if (cfg2 & (1 << 17))
13287 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
13289 /* serdes signal pre-emphasis in register 0x590 set by */
13290 /* bootcode if bit 18 is set */
13291 if (cfg2 & (1 << 18))
13292 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
13294 if ((tg3_flag(tp, 57765_PLUS) ||
13295 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13296 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
13297 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
13298 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
13300 if (tg3_flag(tp, PCI_EXPRESS) &&
13301 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13302 !tg3_flag(tp, 57765_PLUS)) {
13305 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
13306 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
13307 tg3_flag_set(tp, ASPM_WORKAROUND);
13310 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
13311 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
13312 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
13313 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
13314 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
13315 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
13318 if (tg3_flag(tp, WOL_CAP))
13319 device_set_wakeup_enable(&tp->pdev->dev,
13320 tg3_flag(tp, WOL_ENABLE));
13322 device_set_wakeup_capable(&tp->pdev->dev, false);
13325 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
13330 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
13331 tw32(OTP_CTRL, cmd);
13333 /* Wait for up to 1 ms for command to execute. */
13334 for (i = 0; i < 100; i++) {
13335 val = tr32(OTP_STATUS);
13336 if (val & OTP_STATUS_CMD_DONE)
13341 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
13344 /* Read the gphy configuration from the OTP region of the chip. The gphy
13345 * configuration is a 32-bit value that straddles the alignment boundary.
13346 * We do two 32-bit reads and then shift and merge the results.
13348 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
13350 u32 bhalf_otp, thalf_otp;
13352 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
13354 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
13357 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
13359 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13362 thalf_otp = tr32(OTP_READ_DATA);
13364 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
13366 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13369 bhalf_otp = tr32(OTP_READ_DATA);
13371 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
13374 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
13376 u32 adv = ADVERTISED_Autoneg;
13378 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
13379 adv |= ADVERTISED_1000baseT_Half |
13380 ADVERTISED_1000baseT_Full;
13382 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13383 adv |= ADVERTISED_100baseT_Half |
13384 ADVERTISED_100baseT_Full |
13385 ADVERTISED_10baseT_Half |
13386 ADVERTISED_10baseT_Full |
13389 adv |= ADVERTISED_FIBRE;
13391 tp->link_config.advertising = adv;
13392 tp->link_config.speed = SPEED_UNKNOWN;
13393 tp->link_config.duplex = DUPLEX_UNKNOWN;
13394 tp->link_config.autoneg = AUTONEG_ENABLE;
13395 tp->link_config.active_speed = SPEED_UNKNOWN;
13396 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
13401 static int __devinit tg3_phy_probe(struct tg3 *tp)
13403 u32 hw_phy_id_1, hw_phy_id_2;
13404 u32 hw_phy_id, hw_phy_id_masked;
13407 /* flow control autonegotiation is default behavior */
13408 tg3_flag_set(tp, PAUSE_AUTONEG);
13409 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13411 if (tg3_flag(tp, USE_PHYLIB))
13412 return tg3_phy_init(tp);
13414 /* Reading the PHY ID register can conflict with ASF
13415 * firmware access to the PHY hardware.
13418 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
13419 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
13421 /* Now read the physical PHY_ID from the chip and verify
13422 * that it is sane. If it doesn't look good, we fall back
13423 * to either the hard-coded table based PHY_ID and failing
13424 * that the value found in the eeprom area.
13426 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
13427 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
13429 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
13430 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
13431 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
13433 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
13436 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
13437 tp->phy_id = hw_phy_id;
13438 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
13439 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13441 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
13443 if (tp->phy_id != TG3_PHY_ID_INVALID) {
13444 /* Do nothing, phy ID already set up in
13445 * tg3_get_eeprom_hw_cfg().
13448 struct subsys_tbl_ent *p;
13450 /* No eeprom signature? Try the hardcoded
13451 * subsys device table.
13453 p = tg3_lookup_by_subsys(tp);
13457 tp->phy_id = p->phy_id;
13459 tp->phy_id == TG3_PHY_ID_BCM8002)
13460 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13464 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13465 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13466 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
13467 (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
13468 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
13469 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
13470 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
13471 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
13473 tg3_phy_init_link_config(tp);
13475 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13476 !tg3_flag(tp, ENABLE_APE) &&
13477 !tg3_flag(tp, ENABLE_ASF)) {
13480 tg3_readphy(tp, MII_BMSR, &bmsr);
13481 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
13482 (bmsr & BMSR_LSTATUS))
13483 goto skip_phy_reset;
13485 err = tg3_phy_reset(tp);
13489 tg3_phy_set_wirespeed(tp);
13491 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
13492 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
13493 tp->link_config.flowctrl);
13495 tg3_writephy(tp, MII_BMCR,
13496 BMCR_ANENABLE | BMCR_ANRESTART);
13501 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
13502 err = tg3_init_5401phy_dsp(tp);
13506 err = tg3_init_5401phy_dsp(tp);
13512 static void __devinit tg3_read_vpd(struct tg3 *tp)
13515 unsigned int block_end, rosize, len;
13519 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
13523 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
13525 goto out_not_found;
13527 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13528 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13529 i += PCI_VPD_LRDT_TAG_SIZE;
13531 if (block_end > vpdlen)
13532 goto out_not_found;
13534 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13535 PCI_VPD_RO_KEYWORD_MFR_ID);
13537 len = pci_vpd_info_field_size(&vpd_data[j]);
13539 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13540 if (j + len > block_end || len != 4 ||
13541 memcmp(&vpd_data[j], "1028", 4))
13544 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13545 PCI_VPD_RO_KEYWORD_VENDOR0);
13549 len = pci_vpd_info_field_size(&vpd_data[j]);
13551 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13552 if (j + len > block_end)
13555 memcpy(tp->fw_ver, &vpd_data[j], len);
13556 strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
13560 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13561 PCI_VPD_RO_KEYWORD_PARTNO);
13563 goto out_not_found;
13565 len = pci_vpd_info_field_size(&vpd_data[i]);
13567 i += PCI_VPD_INFO_FLD_HDR_SIZE;
13568 if (len > TG3_BPN_SIZE ||
13569 (len + i) > vpdlen)
13570 goto out_not_found;
13572 memcpy(tp->board_part_number, &vpd_data[i], len);
13576 if (tp->board_part_number[0])
13580 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13581 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13582 strcpy(tp->board_part_number, "BCM5717");
13583 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13584 strcpy(tp->board_part_number, "BCM5718");
13587 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13588 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13589 strcpy(tp->board_part_number, "BCM57780");
13590 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13591 strcpy(tp->board_part_number, "BCM57760");
13592 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13593 strcpy(tp->board_part_number, "BCM57790");
13594 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13595 strcpy(tp->board_part_number, "BCM57788");
13598 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13599 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13600 strcpy(tp->board_part_number, "BCM57761");
13601 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13602 strcpy(tp->board_part_number, "BCM57765");
13603 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13604 strcpy(tp->board_part_number, "BCM57781");
13605 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13606 strcpy(tp->board_part_number, "BCM57785");
13607 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13608 strcpy(tp->board_part_number, "BCM57791");
13609 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13610 strcpy(tp->board_part_number, "BCM57795");
13613 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) {
13614 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
13615 strcpy(tp->board_part_number, "BCM57762");
13616 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
13617 strcpy(tp->board_part_number, "BCM57766");
13618 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
13619 strcpy(tp->board_part_number, "BCM57782");
13620 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
13621 strcpy(tp->board_part_number, "BCM57786");
13624 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13625 strcpy(tp->board_part_number, "BCM95906");
13628 strcpy(tp->board_part_number, "none");
13632 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13636 if (tg3_nvram_read(tp, offset, &val) ||
13637 (val & 0xfc000000) != 0x0c000000 ||
13638 tg3_nvram_read(tp, offset + 4, &val) ||
13645 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13647 u32 val, offset, start, ver_offset;
13649 bool newver = false;
13651 if (tg3_nvram_read(tp, 0xc, &offset) ||
13652 tg3_nvram_read(tp, 0x4, &start))
13655 offset = tg3_nvram_logical_addr(tp, offset);
13657 if (tg3_nvram_read(tp, offset, &val))
13660 if ((val & 0xfc000000) == 0x0c000000) {
13661 if (tg3_nvram_read(tp, offset + 4, &val))
13668 dst_off = strlen(tp->fw_ver);
13671 if (TG3_VER_SIZE - dst_off < 16 ||
13672 tg3_nvram_read(tp, offset + 8, &ver_offset))
13675 offset = offset + ver_offset - start;
13676 for (i = 0; i < 16; i += 4) {
13678 if (tg3_nvram_read_be32(tp, offset + i, &v))
13681 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13686 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13689 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13690 TG3_NVM_BCVER_MAJSFT;
13691 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13692 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13693 "v%d.%02d", major, minor);
13697 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13699 u32 val, major, minor;
13701 /* Use native endian representation */
13702 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13705 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13706 TG3_NVM_HWSB_CFG1_MAJSFT;
13707 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13708 TG3_NVM_HWSB_CFG1_MINSFT;
13710 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13713 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13715 u32 offset, major, minor, build;
13717 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13719 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13722 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13723 case TG3_EEPROM_SB_REVISION_0:
13724 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13726 case TG3_EEPROM_SB_REVISION_2:
13727 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13729 case TG3_EEPROM_SB_REVISION_3:
13730 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13732 case TG3_EEPROM_SB_REVISION_4:
13733 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13735 case TG3_EEPROM_SB_REVISION_5:
13736 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13738 case TG3_EEPROM_SB_REVISION_6:
13739 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13745 if (tg3_nvram_read(tp, offset, &val))
13748 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13749 TG3_EEPROM_SB_EDH_BLD_SHFT;
13750 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13751 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13752 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
13754 if (minor > 99 || build > 26)
13757 offset = strlen(tp->fw_ver);
13758 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13759 " v%d.%02d", major, minor);
13762 offset = strlen(tp->fw_ver);
13763 if (offset < TG3_VER_SIZE - 1)
13764 tp->fw_ver[offset] = 'a' + build - 1;
13768 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13770 u32 val, offset, start;
13773 for (offset = TG3_NVM_DIR_START;
13774 offset < TG3_NVM_DIR_END;
13775 offset += TG3_NVM_DIRENT_SIZE) {
13776 if (tg3_nvram_read(tp, offset, &val))
13779 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13783 if (offset == TG3_NVM_DIR_END)
13786 if (!tg3_flag(tp, 5705_PLUS))
13787 start = 0x08000000;
13788 else if (tg3_nvram_read(tp, offset - 4, &start))
13791 if (tg3_nvram_read(tp, offset + 4, &offset) ||
13792 !tg3_fw_img_is_valid(tp, offset) ||
13793 tg3_nvram_read(tp, offset + 8, &val))
13796 offset += val - start;
13798 vlen = strlen(tp->fw_ver);
13800 tp->fw_ver[vlen++] = ',';
13801 tp->fw_ver[vlen++] = ' ';
13803 for (i = 0; i < 4; i++) {
13805 if (tg3_nvram_read_be32(tp, offset, &v))
13808 offset += sizeof(v);
13810 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13811 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13815 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13820 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13826 if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
13829 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13830 if (apedata != APE_SEG_SIG_MAGIC)
13833 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13834 if (!(apedata & APE_FW_STATUS_READY))
13837 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13839 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13840 tg3_flag_set(tp, APE_HAS_NCSI);
13846 vlen = strlen(tp->fw_ver);
13848 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13850 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13851 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13852 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13853 (apedata & APE_FW_VERSION_BLDMSK));
13856 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13859 bool vpd_vers = false;
13861 if (tp->fw_ver[0] != 0)
13864 if (tg3_flag(tp, NO_NVRAM)) {
13865 strcat(tp->fw_ver, "sb");
13869 if (tg3_nvram_read(tp, 0, &val))
13872 if (val == TG3_EEPROM_MAGIC)
13873 tg3_read_bc_ver(tp);
13874 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13875 tg3_read_sb_ver(tp, val);
13876 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13877 tg3_read_hwsb_ver(tp);
13884 if (tg3_flag(tp, ENABLE_APE)) {
13885 if (tg3_flag(tp, ENABLE_ASF))
13886 tg3_read_dash_ver(tp);
13887 } else if (tg3_flag(tp, ENABLE_ASF)) {
13888 tg3_read_mgmtfw_ver(tp);
13892 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13895 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13897 if (tg3_flag(tp, LRG_PROD_RING_CAP))
13898 return TG3_RX_RET_MAX_SIZE_5717;
13899 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
13900 return TG3_RX_RET_MAX_SIZE_5700;
13902 return TG3_RX_RET_MAX_SIZE_5705;
13905 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13906 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13907 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13908 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13912 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13914 struct pci_dev *peer;
13915 unsigned int func, devnr = tp->pdev->devfn & ~7;
13917 for (func = 0; func < 8; func++) {
13918 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13919 if (peer && peer != tp->pdev)
13923 /* 5704 can be configured in single-port mode, set peer to
13924 * tp->pdev in that case.
13932 * We don't need to keep the refcount elevated; there's no way
13933 * to remove one half of this device without removing the other
13940 static void __devinit tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
13942 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
13943 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13946 /* All devices that use the alternate
13947 * ASIC REV location have a CPMU.
13949 tg3_flag_set(tp, CPMU_PRESENT);
13951 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13952 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13953 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13954 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13955 reg = TG3PCI_GEN2_PRODID_ASICREV;
13956 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13957 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13958 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13959 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13960 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13961 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13962 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
13963 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
13964 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
13965 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
13966 reg = TG3PCI_GEN15_PRODID_ASICREV;
13968 reg = TG3PCI_PRODID_ASICREV;
13970 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
13973 /* Wrong chip ID in 5752 A0. This code can be removed later
13974 * as A0 is not in production.
13976 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13977 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13979 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13980 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13982 tg3_flag_set(tp, 5717_PLUS);
13984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13985 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
13986 tg3_flag_set(tp, 57765_CLASS);
13988 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS))
13989 tg3_flag_set(tp, 57765_PLUS);
13991 /* Intentionally exclude ASIC_REV_5906 */
13992 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13993 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13996 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13997 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13998 tg3_flag(tp, 57765_PLUS))
13999 tg3_flag_set(tp, 5755_PLUS);
14001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
14002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
14003 tg3_flag_set(tp, 5780_CLASS);
14005 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14006 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14007 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14008 tg3_flag(tp, 5755_PLUS) ||
14009 tg3_flag(tp, 5780_CLASS))
14010 tg3_flag_set(tp, 5750_PLUS);
14012 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14013 tg3_flag(tp, 5750_PLUS))
14014 tg3_flag_set(tp, 5705_PLUS);
14017 static int __devinit tg3_get_invariants(struct tg3 *tp)
14020 u32 pci_state_reg, grc_misc_cfg;
14025 /* Force memory write invalidate off. If we leave it on,
14026 * then on 5700_BX chips we have to enable a workaround.
14027 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
14028 * to match the cacheline size. The Broadcom driver have this
14029 * workaround but turns MWI off all the times so never uses
14030 * it. This seems to suggest that the workaround is insufficient.
14032 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14033 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
14034 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14036 /* Important! -- Make sure register accesses are byteswapped
14037 * correctly. Also, for those chips that require it, make
14038 * sure that indirect register accesses are enabled before
14039 * the first operation.
14041 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14043 tp->misc_host_ctrl |= (misc_ctrl_reg &
14044 MISC_HOST_CTRL_CHIPREV);
14045 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14046 tp->misc_host_ctrl);
14048 tg3_detect_asic_rev(tp, misc_ctrl_reg);
14050 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
14051 * we need to disable memory and use config. cycles
14052 * only to access all registers. The 5702/03 chips
14053 * can mistakenly decode the special cycles from the
14054 * ICH chipsets as memory write cycles, causing corruption
14055 * of register and memory space. Only certain ICH bridges
14056 * will drive special cycles with non-zero data during the
14057 * address phase which can fall within the 5703's address
14058 * range. This is not an ICH bug as the PCI spec allows
14059 * non-zero address during special cycles. However, only
14060 * these ICH bridges are known to drive non-zero addresses
14061 * during special cycles.
14063 * Since special cycles do not cross PCI bridges, we only
14064 * enable this workaround if the 5703 is on the secondary
14065 * bus of these ICH bridges.
14067 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
14068 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
14069 static struct tg3_dev_id {
14073 } ich_chipsets[] = {
14074 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
14076 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
14078 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
14080 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
14084 struct tg3_dev_id *pci_id = &ich_chipsets[0];
14085 struct pci_dev *bridge = NULL;
14087 while (pci_id->vendor != 0) {
14088 bridge = pci_get_device(pci_id->vendor, pci_id->device,
14094 if (pci_id->rev != PCI_ANY_ID) {
14095 if (bridge->revision > pci_id->rev)
14098 if (bridge->subordinate &&
14099 (bridge->subordinate->number ==
14100 tp->pdev->bus->number)) {
14101 tg3_flag_set(tp, ICH_WORKAROUND);
14102 pci_dev_put(bridge);
14108 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14109 static struct tg3_dev_id {
14112 } bridge_chipsets[] = {
14113 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
14114 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
14117 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
14118 struct pci_dev *bridge = NULL;
14120 while (pci_id->vendor != 0) {
14121 bridge = pci_get_device(pci_id->vendor,
14128 if (bridge->subordinate &&
14129 (bridge->subordinate->number <=
14130 tp->pdev->bus->number) &&
14131 (bridge->subordinate->subordinate >=
14132 tp->pdev->bus->number)) {
14133 tg3_flag_set(tp, 5701_DMA_BUG);
14134 pci_dev_put(bridge);
14140 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
14141 * DMA addresses > 40-bit. This bridge may have other additional
14142 * 57xx devices behind it in some 4-port NIC designs for example.
14143 * Any tg3 device found behind the bridge will also need the 40-bit
14146 if (tg3_flag(tp, 5780_CLASS)) {
14147 tg3_flag_set(tp, 40BIT_DMA_BUG);
14148 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
14150 struct pci_dev *bridge = NULL;
14153 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
14154 PCI_DEVICE_ID_SERVERWORKS_EPB,
14156 if (bridge && bridge->subordinate &&
14157 (bridge->subordinate->number <=
14158 tp->pdev->bus->number) &&
14159 (bridge->subordinate->subordinate >=
14160 tp->pdev->bus->number)) {
14161 tg3_flag_set(tp, 40BIT_DMA_BUG);
14162 pci_dev_put(bridge);
14168 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14169 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
14170 tp->pdev_peer = tg3_find_peer(tp);
14172 /* Determine TSO capabilities */
14173 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
14174 ; /* Do nothing. HW bug. */
14175 else if (tg3_flag(tp, 57765_PLUS))
14176 tg3_flag_set(tp, HW_TSO_3);
14177 else if (tg3_flag(tp, 5755_PLUS) ||
14178 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14179 tg3_flag_set(tp, HW_TSO_2);
14180 else if (tg3_flag(tp, 5750_PLUS)) {
14181 tg3_flag_set(tp, HW_TSO_1);
14182 tg3_flag_set(tp, TSO_BUG);
14183 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
14184 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
14185 tg3_flag_clear(tp, TSO_BUG);
14186 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14187 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14188 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
14189 tg3_flag_set(tp, TSO_BUG);
14190 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14191 tp->fw_needed = FIRMWARE_TG3TSO5;
14193 tp->fw_needed = FIRMWARE_TG3TSO;
14196 /* Selectively allow TSO based on operating conditions */
14197 if (tg3_flag(tp, HW_TSO_1) ||
14198 tg3_flag(tp, HW_TSO_2) ||
14199 tg3_flag(tp, HW_TSO_3) ||
14201 /* For firmware TSO, assume ASF is disabled.
14202 * We'll disable TSO later if we discover ASF
14203 * is enabled in tg3_get_eeprom_hw_cfg().
14205 tg3_flag_set(tp, TSO_CAPABLE);
14207 tg3_flag_clear(tp, TSO_CAPABLE);
14208 tg3_flag_clear(tp, TSO_BUG);
14209 tp->fw_needed = NULL;
14212 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14213 tp->fw_needed = FIRMWARE_TG3;
14217 if (tg3_flag(tp, 5750_PLUS)) {
14218 tg3_flag_set(tp, SUPPORT_MSI);
14219 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
14220 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
14221 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
14222 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
14223 tp->pdev_peer == tp->pdev))
14224 tg3_flag_clear(tp, SUPPORT_MSI);
14226 if (tg3_flag(tp, 5755_PLUS) ||
14227 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14228 tg3_flag_set(tp, 1SHOT_MSI);
14231 if (tg3_flag(tp, 57765_PLUS)) {
14232 tg3_flag_set(tp, SUPPORT_MSIX);
14233 tp->irq_max = TG3_IRQ_MAX_VECS;
14234 tg3_rss_init_dflt_indir_tbl(tp);
14238 if (tg3_flag(tp, 5755_PLUS))
14239 tg3_flag_set(tp, SHORT_DMA_BUG);
14241 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
14242 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
14244 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14245 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14246 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14247 tg3_flag_set(tp, LRG_PROD_RING_CAP);
14249 if (tg3_flag(tp, 57765_PLUS) &&
14250 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
14251 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
14253 if (!tg3_flag(tp, 5705_PLUS) ||
14254 tg3_flag(tp, 5780_CLASS) ||
14255 tg3_flag(tp, USE_JUMBO_BDFLAG))
14256 tg3_flag_set(tp, JUMBO_CAPABLE);
14258 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14261 if (pci_is_pcie(tp->pdev)) {
14264 tg3_flag_set(tp, PCI_EXPRESS);
14266 pci_read_config_word(tp->pdev,
14267 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
14269 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
14270 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
14272 tg3_flag_clear(tp, HW_TSO_2);
14273 tg3_flag_clear(tp, TSO_CAPABLE);
14275 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14276 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14277 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
14278 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
14279 tg3_flag_set(tp, CLKREQ_BUG);
14280 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
14281 tg3_flag_set(tp, L1PLLPD_EN);
14283 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
14284 /* BCM5785 devices are effectively PCIe devices, and should
14285 * follow PCIe codepaths, but do not have a PCIe capabilities
14288 tg3_flag_set(tp, PCI_EXPRESS);
14289 } else if (!tg3_flag(tp, 5705_PLUS) ||
14290 tg3_flag(tp, 5780_CLASS)) {
14291 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
14292 if (!tp->pcix_cap) {
14293 dev_err(&tp->pdev->dev,
14294 "Cannot find PCI-X capability, aborting\n");
14298 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
14299 tg3_flag_set(tp, PCIX_MODE);
14302 /* If we have an AMD 762 or VIA K8T800 chipset, write
14303 * reordering to the mailbox registers done by the host
14304 * controller can cause major troubles. We read back from
14305 * every mailbox register write to force the writes to be
14306 * posted to the chip in order.
14308 if (pci_dev_present(tg3_write_reorder_chipsets) &&
14309 !tg3_flag(tp, PCI_EXPRESS))
14310 tg3_flag_set(tp, MBOX_WRITE_REORDER);
14312 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
14313 &tp->pci_cacheline_sz);
14314 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14315 &tp->pci_lat_timer);
14316 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14317 tp->pci_lat_timer < 64) {
14318 tp->pci_lat_timer = 64;
14319 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14320 tp->pci_lat_timer);
14323 /* Important! -- It is critical that the PCI-X hw workaround
14324 * situation is decided before the first MMIO register access.
14326 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
14327 /* 5700 BX chips need to have their TX producer index
14328 * mailboxes written twice to workaround a bug.
14330 tg3_flag_set(tp, TXD_MBOX_HWBUG);
14332 /* If we are in PCI-X mode, enable register write workaround.
14334 * The workaround is to use indirect register accesses
14335 * for all chip writes not to mailbox registers.
14337 if (tg3_flag(tp, PCIX_MODE)) {
14340 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14342 /* The chip can have it's power management PCI config
14343 * space registers clobbered due to this bug.
14344 * So explicitly force the chip into D0 here.
14346 pci_read_config_dword(tp->pdev,
14347 tp->pm_cap + PCI_PM_CTRL,
14349 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
14350 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
14351 pci_write_config_dword(tp->pdev,
14352 tp->pm_cap + PCI_PM_CTRL,
14355 /* Also, force SERR#/PERR# in PCI command. */
14356 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14357 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
14358 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14362 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
14363 tg3_flag_set(tp, PCI_HIGH_SPEED);
14364 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
14365 tg3_flag_set(tp, PCI_32BIT);
14367 /* Chip-specific fixup from Broadcom driver */
14368 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
14369 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
14370 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
14371 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
14374 /* Default fast path register access methods */
14375 tp->read32 = tg3_read32;
14376 tp->write32 = tg3_write32;
14377 tp->read32_mbox = tg3_read32;
14378 tp->write32_mbox = tg3_write32;
14379 tp->write32_tx_mbox = tg3_write32;
14380 tp->write32_rx_mbox = tg3_write32;
14382 /* Various workaround register access methods */
14383 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
14384 tp->write32 = tg3_write_indirect_reg32;
14385 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14386 (tg3_flag(tp, PCI_EXPRESS) &&
14387 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
14389 * Back to back register writes can cause problems on these
14390 * chips, the workaround is to read back all reg writes
14391 * except those to mailbox regs.
14393 * See tg3_write_indirect_reg32().
14395 tp->write32 = tg3_write_flush_reg32;
14398 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
14399 tp->write32_tx_mbox = tg3_write32_tx_mbox;
14400 if (tg3_flag(tp, MBOX_WRITE_REORDER))
14401 tp->write32_rx_mbox = tg3_write_flush_reg32;
14404 if (tg3_flag(tp, ICH_WORKAROUND)) {
14405 tp->read32 = tg3_read_indirect_reg32;
14406 tp->write32 = tg3_write_indirect_reg32;
14407 tp->read32_mbox = tg3_read_indirect_mbox;
14408 tp->write32_mbox = tg3_write_indirect_mbox;
14409 tp->write32_tx_mbox = tg3_write_indirect_mbox;
14410 tp->write32_rx_mbox = tg3_write_indirect_mbox;
14415 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14416 pci_cmd &= ~PCI_COMMAND_MEMORY;
14417 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14419 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14420 tp->read32_mbox = tg3_read32_mbox_5906;
14421 tp->write32_mbox = tg3_write32_mbox_5906;
14422 tp->write32_tx_mbox = tg3_write32_mbox_5906;
14423 tp->write32_rx_mbox = tg3_write32_mbox_5906;
14426 if (tp->write32 == tg3_write_indirect_reg32 ||
14427 (tg3_flag(tp, PCIX_MODE) &&
14428 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14429 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
14430 tg3_flag_set(tp, SRAM_USE_CONFIG);
14432 /* The memory arbiter has to be enabled in order for SRAM accesses
14433 * to succeed. Normally on powerup the tg3 chip firmware will make
14434 * sure it is enabled, but other entities such as system netboot
14435 * code might disable it.
14437 val = tr32(MEMARB_MODE);
14438 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
14440 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
14441 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14442 tg3_flag(tp, 5780_CLASS)) {
14443 if (tg3_flag(tp, PCIX_MODE)) {
14444 pci_read_config_dword(tp->pdev,
14445 tp->pcix_cap + PCI_X_STATUS,
14447 tp->pci_fn = val & 0x7;
14449 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
14450 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14451 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14452 NIC_SRAM_CPMUSTAT_SIG) {
14453 tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
14454 tp->pci_fn = tp->pci_fn ? 1 : 0;
14456 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14457 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
14458 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14459 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14460 NIC_SRAM_CPMUSTAT_SIG) {
14461 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
14462 TG3_CPMU_STATUS_FSHFT_5719;
14466 /* Get eeprom hw config before calling tg3_set_power_state().
14467 * In particular, the TG3_FLAG_IS_NIC flag must be
14468 * determined before calling tg3_set_power_state() so that
14469 * we know whether or not to switch out of Vaux power.
14470 * When the flag is set, it means that GPIO1 is used for eeprom
14471 * write protect and also implies that it is a LOM where GPIOs
14472 * are not used to switch power.
14474 tg3_get_eeprom_hw_cfg(tp);
14476 if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) {
14477 tg3_flag_clear(tp, TSO_CAPABLE);
14478 tg3_flag_clear(tp, TSO_BUG);
14479 tp->fw_needed = NULL;
14482 if (tg3_flag(tp, ENABLE_APE)) {
14483 /* Allow reads and writes to the
14484 * APE register and memory space.
14486 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
14487 PCISTATE_ALLOW_APE_SHMEM_WR |
14488 PCISTATE_ALLOW_APE_PSPACE_WR;
14489 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
14492 tg3_ape_lock_init(tp);
14495 /* Set up tp->grc_local_ctrl before calling
14496 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
14497 * will bring 5700's external PHY out of reset.
14498 * It is also used as eeprom write protect on LOMs.
14500 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
14501 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14502 tg3_flag(tp, EEPROM_WRITE_PROT))
14503 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
14504 GRC_LCLCTRL_GPIO_OUTPUT1);
14505 /* Unused GPIO3 must be driven as output on 5752 because there
14506 * are no pull-up resistors on unused GPIO pins.
14508 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
14509 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
14511 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14512 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14513 tg3_flag(tp, 57765_CLASS))
14514 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14516 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
14517 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
14518 /* Turn off the debug UART. */
14519 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14520 if (tg3_flag(tp, IS_NIC))
14521 /* Keep VMain power. */
14522 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
14523 GRC_LCLCTRL_GPIO_OUTPUT0;
14526 /* Switch out of Vaux if it is a NIC */
14527 tg3_pwrsrc_switch_to_vmain(tp);
14529 /* Derive initial jumbo mode from MTU assigned in
14530 * ether_setup() via the alloc_etherdev() call
14532 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
14533 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14535 /* Determine WakeOnLan speed to use. */
14536 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14537 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
14538 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
14539 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
14540 tg3_flag_clear(tp, WOL_SPEED_100MB);
14542 tg3_flag_set(tp, WOL_SPEED_100MB);
14545 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14546 tp->phy_flags |= TG3_PHYFLG_IS_FET;
14548 /* A few boards don't want Ethernet@WireSpeed phy feature */
14549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14550 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14551 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
14552 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
14553 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
14554 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14555 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
14557 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
14558 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
14559 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
14560 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
14561 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
14563 if (tg3_flag(tp, 5705_PLUS) &&
14564 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
14565 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
14566 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
14567 !tg3_flag(tp, 57765_PLUS)) {
14568 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14569 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14570 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14571 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
14572 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
14573 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
14574 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
14575 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
14576 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
14578 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
14581 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14582 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
14583 tp->phy_otp = tg3_read_otp_phycfg(tp);
14584 if (tp->phy_otp == 0)
14585 tp->phy_otp = TG3_OTP_DEFAULT;
14588 if (tg3_flag(tp, CPMU_PRESENT))
14589 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
14591 tp->mi_mode = MAC_MI_MODE_BASE;
14593 tp->coalesce_mode = 0;
14594 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
14595 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
14596 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
14598 /* Set these bits to enable statistics workaround. */
14599 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14600 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
14601 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
14602 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
14603 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
14606 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14607 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14608 tg3_flag_set(tp, USE_PHYLIB);
14610 err = tg3_mdio_init(tp);
14614 /* Initialize data/descriptor byte/word swapping. */
14615 val = tr32(GRC_MODE);
14616 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14617 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
14618 GRC_MODE_WORD_SWAP_B2HRX_DATA |
14619 GRC_MODE_B2HRX_ENABLE |
14620 GRC_MODE_HTX2B_ENABLE |
14621 GRC_MODE_HOST_STACKUP);
14623 val &= GRC_MODE_HOST_STACKUP;
14625 tw32(GRC_MODE, val | tp->grc_mode);
14627 tg3_switch_clocks(tp);
14629 /* Clear this out for sanity. */
14630 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14632 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14634 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14635 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
14636 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14638 if (chiprevid == CHIPREV_ID_5701_A0 ||
14639 chiprevid == CHIPREV_ID_5701_B0 ||
14640 chiprevid == CHIPREV_ID_5701_B2 ||
14641 chiprevid == CHIPREV_ID_5701_B5) {
14642 void __iomem *sram_base;
14644 /* Write some dummy words into the SRAM status block
14645 * area, see if it reads back correctly. If the return
14646 * value is bad, force enable the PCIX workaround.
14648 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14650 writel(0x00000000, sram_base);
14651 writel(0x00000000, sram_base + 4);
14652 writel(0xffffffff, sram_base + 4);
14653 if (readl(sram_base) != 0x00000000)
14654 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14659 tg3_nvram_init(tp);
14661 grc_misc_cfg = tr32(GRC_MISC_CFG);
14662 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14664 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14665 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14666 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14667 tg3_flag_set(tp, IS_5788);
14669 if (!tg3_flag(tp, IS_5788) &&
14670 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
14671 tg3_flag_set(tp, TAGGED_STATUS);
14672 if (tg3_flag(tp, TAGGED_STATUS)) {
14673 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14674 HOSTCC_MODE_CLRTICK_TXBD);
14676 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14677 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14678 tp->misc_host_ctrl);
14681 /* Preserve the APE MAC_MODE bits */
14682 if (tg3_flag(tp, ENABLE_APE))
14683 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14687 /* these are limited to 10/100 only */
14688 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14689 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14690 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14691 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14692 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14693 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14694 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14695 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14696 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
14697 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14698 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
14699 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
14700 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14701 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14702 (tp->phy_flags & TG3_PHYFLG_IS_FET))
14703 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
14705 err = tg3_phy_probe(tp);
14707 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
14708 /* ... but do not return immediately ... */
14713 tg3_read_fw_ver(tp);
14715 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14716 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14718 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14719 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14721 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14724 /* 5700 {AX,BX} chips have a broken status block link
14725 * change bit implementation, so we must use the
14726 * status register in those cases.
14728 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14729 tg3_flag_set(tp, USE_LINKCHG_REG);
14731 tg3_flag_clear(tp, USE_LINKCHG_REG);
14733 /* The led_ctrl is set during tg3_phy_probe, here we might
14734 * have to force the link status polling mechanism based
14735 * upon subsystem IDs.
14737 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14738 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14739 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14740 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14741 tg3_flag_set(tp, USE_LINKCHG_REG);
14744 /* For all SERDES we poll the MAC status register. */
14745 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14746 tg3_flag_set(tp, POLL_SERDES);
14748 tg3_flag_clear(tp, POLL_SERDES);
14750 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
14751 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14752 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14753 tg3_flag(tp, PCIX_MODE)) {
14754 tp->rx_offset = NET_SKB_PAD;
14755 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14756 tp->rx_copy_thresh = ~(u16)0;
14760 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14761 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14762 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14764 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14766 /* Increment the rx prod index on the rx std ring by at most
14767 * 8 for these chips to workaround hw errata.
14769 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14770 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14771 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14772 tp->rx_std_max_post = 8;
14774 if (tg3_flag(tp, ASPM_WORKAROUND))
14775 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14776 PCIE_PWR_MGMT_L1_THRESH_MSK;
14781 #ifdef CONFIG_SPARC
14782 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14784 struct net_device *dev = tp->dev;
14785 struct pci_dev *pdev = tp->pdev;
14786 struct device_node *dp = pci_device_to_OF_node(pdev);
14787 const unsigned char *addr;
14790 addr = of_get_property(dp, "local-mac-address", &len);
14791 if (addr && len == 6) {
14792 memcpy(dev->dev_addr, addr, 6);
14793 memcpy(dev->perm_addr, dev->dev_addr, 6);
14799 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14801 struct net_device *dev = tp->dev;
14803 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14804 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14809 static int __devinit tg3_get_device_address(struct tg3 *tp)
14811 struct net_device *dev = tp->dev;
14812 u32 hi, lo, mac_offset;
14815 #ifdef CONFIG_SPARC
14816 if (!tg3_get_macaddr_sparc(tp))
14821 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14822 tg3_flag(tp, 5780_CLASS)) {
14823 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14825 if (tg3_nvram_lock(tp))
14826 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14828 tg3_nvram_unlock(tp);
14829 } else if (tg3_flag(tp, 5717_PLUS)) {
14830 if (tp->pci_fn & 1)
14832 if (tp->pci_fn > 1)
14833 mac_offset += 0x18c;
14834 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14837 /* First try to get it from MAC address mailbox. */
14838 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14839 if ((hi >> 16) == 0x484b) {
14840 dev->dev_addr[0] = (hi >> 8) & 0xff;
14841 dev->dev_addr[1] = (hi >> 0) & 0xff;
14843 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14844 dev->dev_addr[2] = (lo >> 24) & 0xff;
14845 dev->dev_addr[3] = (lo >> 16) & 0xff;
14846 dev->dev_addr[4] = (lo >> 8) & 0xff;
14847 dev->dev_addr[5] = (lo >> 0) & 0xff;
14849 /* Some old bootcode may report a 0 MAC address in SRAM */
14850 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14853 /* Next, try NVRAM. */
14854 if (!tg3_flag(tp, NO_NVRAM) &&
14855 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14856 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14857 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14858 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14860 /* Finally just fetch it out of the MAC control regs. */
14862 hi = tr32(MAC_ADDR_0_HIGH);
14863 lo = tr32(MAC_ADDR_0_LOW);
14865 dev->dev_addr[5] = lo & 0xff;
14866 dev->dev_addr[4] = (lo >> 8) & 0xff;
14867 dev->dev_addr[3] = (lo >> 16) & 0xff;
14868 dev->dev_addr[2] = (lo >> 24) & 0xff;
14869 dev->dev_addr[1] = hi & 0xff;
14870 dev->dev_addr[0] = (hi >> 8) & 0xff;
14874 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14875 #ifdef CONFIG_SPARC
14876 if (!tg3_get_default_macaddr_sparc(tp))
14881 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14885 #define BOUNDARY_SINGLE_CACHELINE 1
14886 #define BOUNDARY_MULTI_CACHELINE 2
14888 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14890 int cacheline_size;
14894 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14896 cacheline_size = 1024;
14898 cacheline_size = (int) byte * 4;
14900 /* On 5703 and later chips, the boundary bits have no
14903 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14904 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14905 !tg3_flag(tp, PCI_EXPRESS))
14908 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14909 goal = BOUNDARY_MULTI_CACHELINE;
14911 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14912 goal = BOUNDARY_SINGLE_CACHELINE;
14918 if (tg3_flag(tp, 57765_PLUS)) {
14919 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14926 /* PCI controllers on most RISC systems tend to disconnect
14927 * when a device tries to burst across a cache-line boundary.
14928 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14930 * Unfortunately, for PCI-E there are only limited
14931 * write-side controls for this, and thus for reads
14932 * we will still get the disconnects. We'll also waste
14933 * these PCI cycles for both read and write for chips
14934 * other than 5700 and 5701 which do not implement the
14937 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
14938 switch (cacheline_size) {
14943 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14944 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14945 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14947 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14948 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14953 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14954 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14958 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14959 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14962 } else if (tg3_flag(tp, PCI_EXPRESS)) {
14963 switch (cacheline_size) {
14967 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14968 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14969 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14975 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14976 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14980 switch (cacheline_size) {
14982 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14983 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14984 DMA_RWCTRL_WRITE_BNDRY_16);
14989 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14990 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14991 DMA_RWCTRL_WRITE_BNDRY_32);
14996 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14997 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14998 DMA_RWCTRL_WRITE_BNDRY_64);
15003 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15004 val |= (DMA_RWCTRL_READ_BNDRY_128 |
15005 DMA_RWCTRL_WRITE_BNDRY_128);
15010 val |= (DMA_RWCTRL_READ_BNDRY_256 |
15011 DMA_RWCTRL_WRITE_BNDRY_256);
15014 val |= (DMA_RWCTRL_READ_BNDRY_512 |
15015 DMA_RWCTRL_WRITE_BNDRY_512);
15019 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
15020 DMA_RWCTRL_WRITE_BNDRY_1024);
15029 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
15031 struct tg3_internal_buffer_desc test_desc;
15032 u32 sram_dma_descs;
15035 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
15037 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
15038 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
15039 tw32(RDMAC_STATUS, 0);
15040 tw32(WDMAC_STATUS, 0);
15042 tw32(BUFMGR_MODE, 0);
15043 tw32(FTQ_RESET, 0);
15045 test_desc.addr_hi = ((u64) buf_dma) >> 32;
15046 test_desc.addr_lo = buf_dma & 0xffffffff;
15047 test_desc.nic_mbuf = 0x00002100;
15048 test_desc.len = size;
15051 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
15052 * the *second* time the tg3 driver was getting loaded after an
15055 * Broadcom tells me:
15056 * ...the DMA engine is connected to the GRC block and a DMA
15057 * reset may affect the GRC block in some unpredictable way...
15058 * The behavior of resets to individual blocks has not been tested.
15060 * Broadcom noted the GRC reset will also reset all sub-components.
15063 test_desc.cqid_sqid = (13 << 8) | 2;
15065 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
15068 test_desc.cqid_sqid = (16 << 8) | 7;
15070 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
15073 test_desc.flags = 0x00000005;
15075 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
15078 val = *(((u32 *)&test_desc) + i);
15079 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
15080 sram_dma_descs + (i * sizeof(u32)));
15081 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
15083 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
15086 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
15088 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
15091 for (i = 0; i < 40; i++) {
15095 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
15097 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
15098 if ((val & 0xffff) == sram_dma_descs) {
15109 #define TEST_BUFFER_SIZE 0x2000
15111 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
15112 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
15116 static int __devinit tg3_test_dma(struct tg3 *tp)
15118 dma_addr_t buf_dma;
15119 u32 *buf, saved_dma_rwctrl;
15122 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
15123 &buf_dma, GFP_KERNEL);
15129 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
15130 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
15132 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
15134 if (tg3_flag(tp, 57765_PLUS))
15137 if (tg3_flag(tp, PCI_EXPRESS)) {
15138 /* DMA read watermark not used on PCIE */
15139 tp->dma_rwctrl |= 0x00180000;
15140 } else if (!tg3_flag(tp, PCIX_MODE)) {
15141 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
15142 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
15143 tp->dma_rwctrl |= 0x003f0000;
15145 tp->dma_rwctrl |= 0x003f000f;
15147 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15148 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
15149 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
15150 u32 read_water = 0x7;
15152 /* If the 5704 is behind the EPB bridge, we can
15153 * do the less restrictive ONE_DMA workaround for
15154 * better performance.
15156 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
15157 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15158 tp->dma_rwctrl |= 0x8000;
15159 else if (ccval == 0x6 || ccval == 0x7)
15160 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
15162 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
15164 /* Set bit 23 to enable PCIX hw bug fix */
15166 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
15167 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
15169 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
15170 /* 5780 always in PCIX mode */
15171 tp->dma_rwctrl |= 0x00144000;
15172 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
15173 /* 5714 always in PCIX mode */
15174 tp->dma_rwctrl |= 0x00148000;
15176 tp->dma_rwctrl |= 0x001b000f;
15180 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15181 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15182 tp->dma_rwctrl &= 0xfffffff0;
15184 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
15185 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
15186 /* Remove this if it causes problems for some boards. */
15187 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
15189 /* On 5700/5701 chips, we need to set this bit.
15190 * Otherwise the chip will issue cacheline transactions
15191 * to streamable DMA memory with not all the byte
15192 * enables turned on. This is an error on several
15193 * RISC PCI controllers, in particular sparc64.
15195 * On 5703/5704 chips, this bit has been reassigned
15196 * a different meaning. In particular, it is used
15197 * on those chips to enable a PCI-X workaround.
15199 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
15202 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15205 /* Unneeded, already done by tg3_get_invariants. */
15206 tg3_switch_clocks(tp);
15209 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15210 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
15213 /* It is best to perform DMA test with maximum write burst size
15214 * to expose the 5700/5701 write DMA bug.
15216 saved_dma_rwctrl = tp->dma_rwctrl;
15217 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15218 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15223 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
15226 /* Send the buffer to the chip. */
15227 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
15229 dev_err(&tp->pdev->dev,
15230 "%s: Buffer write failed. err = %d\n",
15236 /* validate data reached card RAM correctly. */
15237 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15239 tg3_read_mem(tp, 0x2100 + (i*4), &val);
15240 if (le32_to_cpu(val) != p[i]) {
15241 dev_err(&tp->pdev->dev,
15242 "%s: Buffer corrupted on device! "
15243 "(%d != %d)\n", __func__, val, i);
15244 /* ret = -ENODEV here? */
15249 /* Now read it back. */
15250 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
15252 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
15253 "err = %d\n", __func__, ret);
15258 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15262 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15263 DMA_RWCTRL_WRITE_BNDRY_16) {
15264 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15265 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15266 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15269 dev_err(&tp->pdev->dev,
15270 "%s: Buffer corrupted on read back! "
15271 "(%d != %d)\n", __func__, p[i], i);
15277 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
15283 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15284 DMA_RWCTRL_WRITE_BNDRY_16) {
15285 /* DMA test passed without adjusting DMA boundary,
15286 * now look for chipsets that are known to expose the
15287 * DMA bug without failing the test.
15289 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
15290 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15291 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15293 /* Safe to use the calculated DMA boundary. */
15294 tp->dma_rwctrl = saved_dma_rwctrl;
15297 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15301 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
15306 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
15308 if (tg3_flag(tp, 57765_PLUS)) {
15309 tp->bufmgr_config.mbuf_read_dma_low_water =
15310 DEFAULT_MB_RDMA_LOW_WATER_5705;
15311 tp->bufmgr_config.mbuf_mac_rx_low_water =
15312 DEFAULT_MB_MACRX_LOW_WATER_57765;
15313 tp->bufmgr_config.mbuf_high_water =
15314 DEFAULT_MB_HIGH_WATER_57765;
15316 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15317 DEFAULT_MB_RDMA_LOW_WATER_5705;
15318 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15319 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
15320 tp->bufmgr_config.mbuf_high_water_jumbo =
15321 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
15322 } else if (tg3_flag(tp, 5705_PLUS)) {
15323 tp->bufmgr_config.mbuf_read_dma_low_water =
15324 DEFAULT_MB_RDMA_LOW_WATER_5705;
15325 tp->bufmgr_config.mbuf_mac_rx_low_water =
15326 DEFAULT_MB_MACRX_LOW_WATER_5705;
15327 tp->bufmgr_config.mbuf_high_water =
15328 DEFAULT_MB_HIGH_WATER_5705;
15329 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
15330 tp->bufmgr_config.mbuf_mac_rx_low_water =
15331 DEFAULT_MB_MACRX_LOW_WATER_5906;
15332 tp->bufmgr_config.mbuf_high_water =
15333 DEFAULT_MB_HIGH_WATER_5906;
15336 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15337 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
15338 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15339 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
15340 tp->bufmgr_config.mbuf_high_water_jumbo =
15341 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
15343 tp->bufmgr_config.mbuf_read_dma_low_water =
15344 DEFAULT_MB_RDMA_LOW_WATER;
15345 tp->bufmgr_config.mbuf_mac_rx_low_water =
15346 DEFAULT_MB_MACRX_LOW_WATER;
15347 tp->bufmgr_config.mbuf_high_water =
15348 DEFAULT_MB_HIGH_WATER;
15350 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15351 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
15352 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15353 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
15354 tp->bufmgr_config.mbuf_high_water_jumbo =
15355 DEFAULT_MB_HIGH_WATER_JUMBO;
15358 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
15359 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
15362 static char * __devinit tg3_phy_string(struct tg3 *tp)
15364 switch (tp->phy_id & TG3_PHY_ID_MASK) {
15365 case TG3_PHY_ID_BCM5400: return "5400";
15366 case TG3_PHY_ID_BCM5401: return "5401";
15367 case TG3_PHY_ID_BCM5411: return "5411";
15368 case TG3_PHY_ID_BCM5701: return "5701";
15369 case TG3_PHY_ID_BCM5703: return "5703";
15370 case TG3_PHY_ID_BCM5704: return "5704";
15371 case TG3_PHY_ID_BCM5705: return "5705";
15372 case TG3_PHY_ID_BCM5750: return "5750";
15373 case TG3_PHY_ID_BCM5752: return "5752";
15374 case TG3_PHY_ID_BCM5714: return "5714";
15375 case TG3_PHY_ID_BCM5780: return "5780";
15376 case TG3_PHY_ID_BCM5755: return "5755";
15377 case TG3_PHY_ID_BCM5787: return "5787";
15378 case TG3_PHY_ID_BCM5784: return "5784";
15379 case TG3_PHY_ID_BCM5756: return "5722/5756";
15380 case TG3_PHY_ID_BCM5906: return "5906";
15381 case TG3_PHY_ID_BCM5761: return "5761";
15382 case TG3_PHY_ID_BCM5718C: return "5718C";
15383 case TG3_PHY_ID_BCM5718S: return "5718S";
15384 case TG3_PHY_ID_BCM57765: return "57765";
15385 case TG3_PHY_ID_BCM5719C: return "5719C";
15386 case TG3_PHY_ID_BCM5720C: return "5720C";
15387 case TG3_PHY_ID_BCM8002: return "8002/serdes";
15388 case 0: return "serdes";
15389 default: return "unknown";
15393 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
15395 if (tg3_flag(tp, PCI_EXPRESS)) {
15396 strcpy(str, "PCI Express");
15398 } else if (tg3_flag(tp, PCIX_MODE)) {
15399 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
15401 strcpy(str, "PCIX:");
15403 if ((clock_ctrl == 7) ||
15404 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
15405 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
15406 strcat(str, "133MHz");
15407 else if (clock_ctrl == 0)
15408 strcat(str, "33MHz");
15409 else if (clock_ctrl == 2)
15410 strcat(str, "50MHz");
15411 else if (clock_ctrl == 4)
15412 strcat(str, "66MHz");
15413 else if (clock_ctrl == 6)
15414 strcat(str, "100MHz");
15416 strcpy(str, "PCI:");
15417 if (tg3_flag(tp, PCI_HIGH_SPEED))
15418 strcat(str, "66MHz");
15420 strcat(str, "33MHz");
15422 if (tg3_flag(tp, PCI_32BIT))
15423 strcat(str, ":32-bit");
15425 strcat(str, ":64-bit");
15429 static void __devinit tg3_init_coal(struct tg3 *tp)
15431 struct ethtool_coalesce *ec = &tp->coal;
15433 memset(ec, 0, sizeof(*ec));
15434 ec->cmd = ETHTOOL_GCOALESCE;
15435 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
15436 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
15437 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
15438 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
15439 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
15440 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
15441 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
15442 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
15443 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
15445 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
15446 HOSTCC_MODE_CLRTICK_TXBD)) {
15447 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
15448 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
15449 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
15450 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
15453 if (tg3_flag(tp, 5705_PLUS)) {
15454 ec->rx_coalesce_usecs_irq = 0;
15455 ec->tx_coalesce_usecs_irq = 0;
15456 ec->stats_block_coalesce_usecs = 0;
15460 static int __devinit tg3_init_one(struct pci_dev *pdev,
15461 const struct pci_device_id *ent)
15463 struct net_device *dev;
15465 int i, err, pm_cap;
15466 u32 sndmbx, rcvmbx, intmbx;
15468 u64 dma_mask, persist_dma_mask;
15469 netdev_features_t features = 0;
15471 printk_once(KERN_INFO "%s\n", version);
15473 err = pci_enable_device(pdev);
15475 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
15479 err = pci_request_regions(pdev, DRV_MODULE_NAME);
15481 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
15482 goto err_out_disable_pdev;
15485 pci_set_master(pdev);
15487 /* Find power-management capability. */
15488 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
15490 dev_err(&pdev->dev,
15491 "Cannot find Power Management capability, aborting\n");
15493 goto err_out_free_res;
15496 err = pci_set_power_state(pdev, PCI_D0);
15498 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
15499 goto err_out_free_res;
15502 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
15505 goto err_out_power_down;
15508 SET_NETDEV_DEV(dev, &pdev->dev);
15510 tp = netdev_priv(dev);
15513 tp->pm_cap = pm_cap;
15514 tp->rx_mode = TG3_DEF_RX_MODE;
15515 tp->tx_mode = TG3_DEF_TX_MODE;
15518 tp->msg_enable = tg3_debug;
15520 tp->msg_enable = TG3_DEF_MSG_ENABLE;
15522 /* The word/byte swap controls here control register access byte
15523 * swapping. DMA data byte swapping is controlled in the GRC_MODE
15526 tp->misc_host_ctrl =
15527 MISC_HOST_CTRL_MASK_PCI_INT |
15528 MISC_HOST_CTRL_WORD_SWAP |
15529 MISC_HOST_CTRL_INDIR_ACCESS |
15530 MISC_HOST_CTRL_PCISTATE_RW;
15532 /* The NONFRM (non-frame) byte/word swap controls take effect
15533 * on descriptor entries, anything which isn't packet data.
15535 * The StrongARM chips on the board (one for tx, one for rx)
15536 * are running in big-endian mode.
15538 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
15539 GRC_MODE_WSWAP_NONFRM_DATA);
15540 #ifdef __BIG_ENDIAN
15541 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
15543 spin_lock_init(&tp->lock);
15544 spin_lock_init(&tp->indirect_lock);
15545 INIT_WORK(&tp->reset_task, tg3_reset_task);
15547 tp->regs = pci_ioremap_bar(pdev, BAR_0);
15549 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
15551 goto err_out_free_dev;
15554 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
15555 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
15556 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
15557 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
15558 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15559 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15560 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15561 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) {
15562 tg3_flag_set(tp, ENABLE_APE);
15563 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15564 if (!tp->aperegs) {
15565 dev_err(&pdev->dev,
15566 "Cannot map APE registers, aborting\n");
15568 goto err_out_iounmap;
15572 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
15573 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
15575 dev->ethtool_ops = &tg3_ethtool_ops;
15576 dev->watchdog_timeo = TG3_TX_TIMEOUT;
15577 dev->netdev_ops = &tg3_netdev_ops;
15578 dev->irq = pdev->irq;
15580 err = tg3_get_invariants(tp);
15582 dev_err(&pdev->dev,
15583 "Problem fetching invariants of chip, aborting\n");
15584 goto err_out_apeunmap;
15587 /* The EPB bridge inside 5714, 5715, and 5780 and any
15588 * device behind the EPB cannot support DMA addresses > 40-bit.
15589 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15590 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15591 * do DMA address check in tg3_start_xmit().
15593 if (tg3_flag(tp, IS_5788))
15594 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15595 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
15596 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15597 #ifdef CONFIG_HIGHMEM
15598 dma_mask = DMA_BIT_MASK(64);
15601 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
15603 /* Configure DMA attributes. */
15604 if (dma_mask > DMA_BIT_MASK(32)) {
15605 err = pci_set_dma_mask(pdev, dma_mask);
15607 features |= NETIF_F_HIGHDMA;
15608 err = pci_set_consistent_dma_mask(pdev,
15611 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15612 "DMA for consistent allocations\n");
15613 goto err_out_apeunmap;
15617 if (err || dma_mask == DMA_BIT_MASK(32)) {
15618 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
15620 dev_err(&pdev->dev,
15621 "No usable DMA configuration, aborting\n");
15622 goto err_out_apeunmap;
15626 tg3_init_bufmgr_config(tp);
15628 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
15630 /* 5700 B0 chips do not support checksumming correctly due
15631 * to hardware bugs.
15633 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
15634 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
15636 if (tg3_flag(tp, 5755_PLUS))
15637 features |= NETIF_F_IPV6_CSUM;
15640 /* TSO is on by default on chips that support hardware TSO.
15641 * Firmware TSO on older chips gives lower performance, so it
15642 * is off by default, but can be enabled using ethtool.
15644 if ((tg3_flag(tp, HW_TSO_1) ||
15645 tg3_flag(tp, HW_TSO_2) ||
15646 tg3_flag(tp, HW_TSO_3)) &&
15647 (features & NETIF_F_IP_CSUM))
15648 features |= NETIF_F_TSO;
15649 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
15650 if (features & NETIF_F_IPV6_CSUM)
15651 features |= NETIF_F_TSO6;
15652 if (tg3_flag(tp, HW_TSO_3) ||
15653 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15654 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15655 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15656 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15657 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15658 features |= NETIF_F_TSO_ECN;
15661 dev->features |= features;
15662 dev->vlan_features |= features;
15665 * Add loopback capability only for a subset of devices that support
15666 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
15667 * loopback for the remaining devices.
15669 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
15670 !tg3_flag(tp, CPMU_PRESENT))
15671 /* Add the loopback capability */
15672 features |= NETIF_F_LOOPBACK;
15674 dev->hw_features |= features;
15676 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15677 !tg3_flag(tp, TSO_CAPABLE) &&
15678 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15679 tg3_flag_set(tp, MAX_RXPEND_64);
15680 tp->rx_pending = 63;
15683 err = tg3_get_device_address(tp);
15685 dev_err(&pdev->dev,
15686 "Could not obtain valid ethernet address, aborting\n");
15687 goto err_out_apeunmap;
15691 * Reset chip in case UNDI or EFI driver did not shutdown
15692 * DMA self test will enable WDMAC and we'll see (spurious)
15693 * pending DMA on the PCI bus at that point.
15695 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15696 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15697 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15698 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15701 err = tg3_test_dma(tp);
15703 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15704 goto err_out_apeunmap;
15707 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15708 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15709 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15710 for (i = 0; i < tp->irq_max; i++) {
15711 struct tg3_napi *tnapi = &tp->napi[i];
15714 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15716 tnapi->int_mbox = intmbx;
15722 tnapi->consmbox = rcvmbx;
15723 tnapi->prodmbox = sndmbx;
15726 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15728 tnapi->coal_now = HOSTCC_MODE_NOW;
15730 if (!tg3_flag(tp, SUPPORT_MSIX))
15734 * If we support MSIX, we'll be using RSS. If we're using
15735 * RSS, the first vector only handles link interrupts and the
15736 * remaining vectors handle rx and tx interrupts. Reuse the
15737 * mailbox values for the next iteration. The values we setup
15738 * above are still useful for the single vectored mode.
15753 pci_set_drvdata(pdev, dev);
15755 if (tg3_flag(tp, 5717_PLUS)) {
15756 /* Resume a low-power mode */
15757 tg3_frob_aux_power(tp, false);
15760 tg3_timer_init(tp);
15762 err = register_netdev(dev);
15764 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15765 goto err_out_apeunmap;
15768 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15769 tp->board_part_number,
15770 tp->pci_chip_rev_id,
15771 tg3_bus_string(tp, str),
15774 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15775 struct phy_device *phydev;
15776 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15778 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15779 phydev->drv->name, dev_name(&phydev->dev));
15783 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15784 ethtype = "10/100Base-TX";
15785 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15786 ethtype = "1000Base-SX";
15788 ethtype = "10/100/1000Base-T";
15790 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15791 "(WireSpeed[%d], EEE[%d])\n",
15792 tg3_phy_string(tp), ethtype,
15793 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
15794 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
15797 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15798 (dev->features & NETIF_F_RXCSUM) != 0,
15799 tg3_flag(tp, USE_LINKCHG_REG) != 0,
15800 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15801 tg3_flag(tp, ENABLE_ASF) != 0,
15802 tg3_flag(tp, TSO_CAPABLE) != 0);
15803 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15805 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15806 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15808 pci_save_state(pdev);
15814 iounmap(tp->aperegs);
15815 tp->aperegs = NULL;
15827 err_out_power_down:
15828 pci_set_power_state(pdev, PCI_D3hot);
15831 pci_release_regions(pdev);
15833 err_out_disable_pdev:
15834 pci_disable_device(pdev);
15835 pci_set_drvdata(pdev, NULL);
15839 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15841 struct net_device *dev = pci_get_drvdata(pdev);
15844 struct tg3 *tp = netdev_priv(dev);
15847 release_firmware(tp->fw);
15849 tg3_reset_task_cancel(tp);
15851 if (tg3_flag(tp, USE_PHYLIB)) {
15856 unregister_netdev(dev);
15858 iounmap(tp->aperegs);
15859 tp->aperegs = NULL;
15866 pci_release_regions(pdev);
15867 pci_disable_device(pdev);
15868 pci_set_drvdata(pdev, NULL);
15872 #ifdef CONFIG_PM_SLEEP
15873 static int tg3_suspend(struct device *device)
15875 struct pci_dev *pdev = to_pci_dev(device);
15876 struct net_device *dev = pci_get_drvdata(pdev);
15877 struct tg3 *tp = netdev_priv(dev);
15880 if (!netif_running(dev))
15883 tg3_reset_task_cancel(tp);
15885 tg3_netif_stop(tp);
15887 tg3_timer_stop(tp);
15889 tg3_full_lock(tp, 1);
15890 tg3_disable_ints(tp);
15891 tg3_full_unlock(tp);
15893 netif_device_detach(dev);
15895 tg3_full_lock(tp, 0);
15896 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15897 tg3_flag_clear(tp, INIT_COMPLETE);
15898 tg3_full_unlock(tp);
15900 err = tg3_power_down_prepare(tp);
15904 tg3_full_lock(tp, 0);
15906 tg3_flag_set(tp, INIT_COMPLETE);
15907 err2 = tg3_restart_hw(tp, 1);
15911 tg3_timer_start(tp);
15913 netif_device_attach(dev);
15914 tg3_netif_start(tp);
15917 tg3_full_unlock(tp);
15926 static int tg3_resume(struct device *device)
15928 struct pci_dev *pdev = to_pci_dev(device);
15929 struct net_device *dev = pci_get_drvdata(pdev);
15930 struct tg3 *tp = netdev_priv(dev);
15933 if (!netif_running(dev))
15936 netif_device_attach(dev);
15938 tg3_full_lock(tp, 0);
15940 tg3_flag_set(tp, INIT_COMPLETE);
15941 err = tg3_restart_hw(tp, 1);
15945 tg3_timer_start(tp);
15947 tg3_netif_start(tp);
15950 tg3_full_unlock(tp);
15958 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15959 #define TG3_PM_OPS (&tg3_pm_ops)
15963 #define TG3_PM_OPS NULL
15965 #endif /* CONFIG_PM_SLEEP */
15968 * tg3_io_error_detected - called when PCI error is detected
15969 * @pdev: Pointer to PCI device
15970 * @state: The current pci connection state
15972 * This function is called after a PCI bus error affecting
15973 * this device has been detected.
15975 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
15976 pci_channel_state_t state)
15978 struct net_device *netdev = pci_get_drvdata(pdev);
15979 struct tg3 *tp = netdev_priv(netdev);
15980 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
15982 netdev_info(netdev, "PCI I/O error detected\n");
15986 if (!netif_running(netdev))
15991 tg3_netif_stop(tp);
15993 tg3_timer_stop(tp);
15995 /* Want to make sure that the reset task doesn't run */
15996 tg3_reset_task_cancel(tp);
15998 netif_device_detach(netdev);
16000 /* Clean up software state, even if MMIO is blocked */
16001 tg3_full_lock(tp, 0);
16002 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
16003 tg3_full_unlock(tp);
16006 if (state == pci_channel_io_perm_failure)
16007 err = PCI_ERS_RESULT_DISCONNECT;
16009 pci_disable_device(pdev);
16017 * tg3_io_slot_reset - called after the pci bus has been reset.
16018 * @pdev: Pointer to PCI device
16020 * Restart the card from scratch, as if from a cold-boot.
16021 * At this point, the card has exprienced a hard reset,
16022 * followed by fixups by BIOS, and has its config space
16023 * set up identically to what it was at cold boot.
16025 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
16027 struct net_device *netdev = pci_get_drvdata(pdev);
16028 struct tg3 *tp = netdev_priv(netdev);
16029 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
16034 if (pci_enable_device(pdev)) {
16035 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
16039 pci_set_master(pdev);
16040 pci_restore_state(pdev);
16041 pci_save_state(pdev);
16043 if (!netif_running(netdev)) {
16044 rc = PCI_ERS_RESULT_RECOVERED;
16048 err = tg3_power_up(tp);
16052 rc = PCI_ERS_RESULT_RECOVERED;
16061 * tg3_io_resume - called when traffic can start flowing again.
16062 * @pdev: Pointer to PCI device
16064 * This callback is called when the error recovery driver tells
16065 * us that its OK to resume normal operation.
16067 static void tg3_io_resume(struct pci_dev *pdev)
16069 struct net_device *netdev = pci_get_drvdata(pdev);
16070 struct tg3 *tp = netdev_priv(netdev);
16075 if (!netif_running(netdev))
16078 tg3_full_lock(tp, 0);
16079 tg3_flag_set(tp, INIT_COMPLETE);
16080 err = tg3_restart_hw(tp, 1);
16081 tg3_full_unlock(tp);
16083 netdev_err(netdev, "Cannot restart hardware after reset.\n");
16087 netif_device_attach(netdev);
16089 tg3_timer_start(tp);
16091 tg3_netif_start(tp);
16099 static struct pci_error_handlers tg3_err_handler = {
16100 .error_detected = tg3_io_error_detected,
16101 .slot_reset = tg3_io_slot_reset,
16102 .resume = tg3_io_resume
16105 static struct pci_driver tg3_driver = {
16106 .name = DRV_MODULE_NAME,
16107 .id_table = tg3_pci_tbl,
16108 .probe = tg3_init_one,
16109 .remove = __devexit_p(tg3_remove_one),
16110 .err_handler = &tg3_err_handler,
16111 .driver.pm = TG3_PM_OPS,
16114 static int __init tg3_init(void)
16116 return pci_register_driver(&tg3_driver);
16119 static void __exit tg3_cleanup(void)
16121 pci_unregister_driver(&tg3_driver);
16124 module_init(tg3_init);
16125 module_exit(tg3_cleanup);