drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  */
  56
  57 #include "e1000.h"
  58
  59 #define ICH_FLASH_GFPREG                0x0000
  60 #define ICH_FLASH_HSFSTS                0x0004
  61 #define ICH_FLASH_HSFCTL                0x0006
  62 #define ICH_FLASH_FADDR                 0x0008
  63 #define ICH_FLASH_FDATA0                0x0010
  64 #define ICH_FLASH_PR0                   0x0074
  65
  66 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  67 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  68 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  69 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  70 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  71
  72 #define ICH_CYCLE_READ                  0
  73 #define ICH_CYCLE_WRITE                 2
  74 #define ICH_CYCLE_ERASE                 3
  75
  76 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  77 #define FLASH_SECTOR_ADDR_SHIFT         12
  78
  79 #define ICH_FLASH_SEG_SIZE_256          256
  80 #define ICH_FLASH_SEG_SIZE_4K           4096
  81 #define ICH_FLASH_SEG_SIZE_8K           8192
  82 #define ICH_FLASH_SEG_SIZE_64K          65536
  83
  84
  85 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  86
  87 #define E1000_ICH_MNG_IAMT_MODE         0x2
  88
  89 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  90                                  (ID_LED_DEF1_OFF2 <<  8) | \
  91                                  (ID_LED_DEF1_ON2  <<  4) | \
  92                                  (ID_LED_DEF1_DEF2))
  93
  94 #define E1000_ICH_NVM_SIG_WORD          0x13
  95 #define E1000_ICH_NVM_SIG_MASK          0xC000
  96 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
  97 #define E1000_ICH_NVM_SIG_VALUE         0x80
  98
  99 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 100
 101 #define E1000_FEXTNVM_SW_CONFIG         1
 102 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 103
 104 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 105
 106 #define E1000_ICH_RAR_ENTRIES           7
 107
 108 #define PHY_PAGE_SHIFT 5
 109 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 110                            ((reg) & MAX_PHY_REG_ADDRESS))
 111 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 112 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 113
 114 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 115 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 116 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 117
 118 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 119
 120 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 121
 122 /* SMBus Address Phy Register */
 123 #define HV_SMB_ADDR            PHY_REG(768, 26)
 124 #define HV_SMB_ADDR_PEC_EN     0x0200
 125 #define HV_SMB_ADDR_VALID      0x0080
 126
 127 /* Strapping Option Register - RO */
 128 #define E1000_STRAP                     0x0000C
 129 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 130 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 131
 132 /* OEM Bits Phy Register */
 133 #define HV_OEM_BITS            PHY_REG(768, 25)
 134 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 135 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 136 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 137
 138 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 139 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 140
 141 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 142 /* Offset 04h HSFSTS */
 143 union ich8_hws_flash_status {
 144         struct ich8_hsfsts {
 145                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 146                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 147                 u16 dael       :1; /* bit 2 Direct Access error Log */
 148                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 149                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 150                 u16 reserved1  :2; /* bit 13:6 Reserved */
 151                 u16 reserved2  :6; /* bit 13:6 Reserved */
 152                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 153                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 154         } hsf_status;
 155         u16 regval;
 156 };
 157
 158 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 159 /* Offset 06h FLCTL */
 160 union ich8_hws_flash_ctrl {
 161         struct ich8_hsflctl {
 162                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 163                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 164                 u16 reserved   :5;   /* 7:3 Reserved  */
 165                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 166                 u16 flockdn    :6;   /* 15:10 Reserved */
 167         } hsf_ctrl;
 168         u16 regval;
 169 };
 170
 171 /* ICH Flash Region Access Permissions */
 172 union ich8_hws_flash_regacc {
 173         struct ich8_flracc {
 174                 u32 grra      :8; /* 0:7 GbE region Read Access */
 175                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 176                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 177                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 178         } hsf_flregacc;
 179         u16 regval;
 180 };
 181
 182 /* ICH Flash Protected Region */
 183 union ich8_flash_protected_range {
 184         struct ich8_pr {
 185                 u32 base:13;     /* 0:12 Protected Range Base */
 186                 u32 reserved1:2; /* 13:14 Reserved */
 187                 u32 rpe:1;       /* 15 Read Protection Enable */
 188                 u32 limit:13;    /* 16:28 Protected Range Limit */
 189                 u32 reserved2:2; /* 29:30 Reserved */
 190                 u32 wpe:1;       /* 31 Write Protection Enable */
 191         } range;
 192         u32 regval;
 193 };
 194
 195 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 196 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 197 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 198 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 199 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 200                                                 u32 offset, u8 byte);
 201 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 202                                          u8 *data);
 203 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 204                                          u16 *data);
 205 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 206                                          u8 size, u16 *data);
 207 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 208 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 209 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 210 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 211 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 212 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 213 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 214 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 215 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 216 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 217 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 218 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 219 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 220 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 221 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 222
 223 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 224 {
 225         return readw(hw->flash_address + reg);
 226 }
 227
 228 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 229 {
 230         return readl(hw->flash_address + reg);
 231 }
 232
 233 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 234 {
 235         writew(val, hw->flash_address + reg);
 236 }
 237
 238 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 239 {
 240         writel(val, hw->flash_address + reg);
 241 }
 242
 243 #define er16flash(reg)          __er16flash(hw, (reg))
 244 #define er32flash(reg)          __er32flash(hw, (reg))
 245 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 246 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 247
 248 /**
 249  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 250  *  @hw: pointer to the HW structure
 251  *
 252  *  Initialize family-specific PHY parameters and function pointers.
 253  **/
 254 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 255 {
 256         struct e1000_phy_info *phy = &hw->phy;
 257         s32 ret_val = 0;
 258
 259         phy->addr                     = 1;
 260         phy->reset_delay_us           = 100;
 261
 262         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 263         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 264         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 265         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 266         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 267         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 268         phy->ops.power_up             = e1000_power_up_phy_copper;
 269         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 270         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 271
 272         phy->id = e1000_phy_unknown;
 273         e1000e_get_phy_id(hw);
 274         phy->type = e1000e_get_phy_type_from_id(phy->id);
 275
 276         switch (phy->type) {
 277         case e1000_phy_82577:
 278                 phy->ops.check_polarity = e1000_check_polarity_82577;
 279                 phy->ops.force_speed_duplex =
 280                         e1000_phy_force_speed_duplex_82577;
 281                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 282                 phy->ops.get_info = e1000_get_phy_info_82577;
 283                 phy->ops.commit = e1000e_phy_sw_reset;
 284         case e1000_phy_82578:
 285                 phy->ops.check_polarity = e1000_check_polarity_m88;
 286                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 287                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 288                 phy->ops.get_info = e1000e_get_phy_info_m88;
 289                 break;
 290         default:
 291                 ret_val = -E1000_ERR_PHY;
 292                 break;
 293         }
 294
 295         return ret_val;
 296 }
 297
 298 /**
 299  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 300  *  @hw: pointer to the HW structure
 301  *
 302  *  Initialize family-specific PHY parameters and function pointers.
 303  **/
 304 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 305 {
 306         struct e1000_phy_info *phy = &hw->phy;
 307         s32 ret_val;
 308         u16 i = 0;
 309
 310         phy->addr                       = 1;
 311         phy->reset_delay_us             = 100;
 312
 313         phy->ops.power_up               = e1000_power_up_phy_copper;
 314         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 315
 316         /*
 317          * We may need to do this twice - once for IGP and if that fails,
 318          * we'll set BM func pointers and try again
 319          */
 320         ret_val = e1000e_determine_phy_address(hw);
 321         if (ret_val) {
 322                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 323                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 324                 ret_val = e1000e_determine_phy_address(hw);
 325                 if (ret_val) {
 326                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 327                         return ret_val;
 328                 }
 329         }
 330
 331         phy->id = 0;
 332         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 333                (i++ < 100)) {
 334                 msleep(1);
 335                 ret_val = e1000e_get_phy_id(hw);
 336                 if (ret_val)
 337                         return ret_val;
 338         }
 339
 340         /* Verify phy id */
 341         switch (phy->id) {
 342         case IGP03E1000_E_PHY_ID:
 343                 phy->type = e1000_phy_igp_3;
 344                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 345                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 346                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 347                 phy->ops.get_info = e1000e_get_phy_info_igp;
 348                 phy->ops.check_polarity = e1000_check_polarity_igp;
 349                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 350                 break;
 351         case IFE_E_PHY_ID:
 352         case IFE_PLUS_E_PHY_ID:
 353         case IFE_C_E_PHY_ID:
 354                 phy->type = e1000_phy_ife;
 355                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 356                 phy->ops.get_info = e1000_get_phy_info_ife;
 357                 phy->ops.check_polarity = e1000_check_polarity_ife;
 358                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 359                 break;
 360         case BME1000_E_PHY_ID:
 361                 phy->type = e1000_phy_bm;
 362                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 363                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 364                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 365                 phy->ops.commit = e1000e_phy_sw_reset;
 366                 phy->ops.get_info = e1000e_get_phy_info_m88;
 367                 phy->ops.check_polarity = e1000_check_polarity_m88;
 368                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 369                 break;
 370         default:
 371                 return -E1000_ERR_PHY;
 372                 break;
 373         }
 374
 375         return 0;
 376 }
 377
 378 /**
 379  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 380  *  @hw: pointer to the HW structure
 381  *
 382  *  Initialize family-specific NVM parameters and function
 383  *  pointers.
 384  **/
 385 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 386 {
 387         struct e1000_nvm_info *nvm = &hw->nvm;
 388         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 389         u32 gfpreg, sector_base_addr, sector_end_addr;
 390         u16 i;
 391
 392         /* Can't read flash registers if the register set isn't mapped. */
 393         if (!hw->flash_address) {
 394                 e_dbg("ERROR: Flash registers not mapped\n");
 395                 return -E1000_ERR_CONFIG;
 396         }
 397
 398         nvm->type = e1000_nvm_flash_sw;
 399
 400         gfpreg = er32flash(ICH_FLASH_GFPREG);
 401
 402         /*
 403          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 404          * Add 1 to sector_end_addr since this sector is included in
 405          * the overall size.
 406          */
 407         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 408         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 409
 410         /* flash_base_addr is byte-aligned */
 411         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 412
 413         /*
 414          * find total size of the NVM, then cut in half since the total
 415          * size represents two separate NVM banks.
 416          */
 417         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 418                                 << FLASH_SECTOR_ADDR_SHIFT;
 419         nvm->flash_bank_size /= 2;
 420         /* Adjust to word count */
 421         nvm->flash_bank_size /= sizeof(u16);
 422
 423         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 424
 425         /* Clear shadow ram */
 426         for (i = 0; i < nvm->word_size; i++) {
 427                 dev_spec->shadow_ram[i].modified = false;
 428                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 429         }
 430
 431         return 0;
 432 }
 433
 434 /**
 435  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 436  *  @hw: pointer to the HW structure
 437  *
 438  *  Initialize family-specific MAC parameters and function
 439  *  pointers.
 440  **/
 441 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 442 {
 443         struct e1000_hw *hw = &adapter->hw;
 444         struct e1000_mac_info *mac = &hw->mac;
 445
 446         /* Set media type function pointer */
 447         hw->phy.media_type = e1000_media_type_copper;
 448
 449         /* Set mta register count */
 450         mac->mta_reg_count = 32;
 451         /* Set rar entry count */
 452         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 453         if (mac->type == e1000_ich8lan)
 454                 mac->rar_entry_count--;
 455         /* Set if manageability features are enabled. */
 456         mac->arc_subsystem_valid = true;
 457
 458         /* LED operations */
 459         switch (mac->type) {
 460         case e1000_ich8lan:
 461         case e1000_ich9lan:
 462         case e1000_ich10lan:
 463                 /* ID LED init */
 464                 mac->ops.id_led_init = e1000e_id_led_init;
 465                 /* setup LED */
 466                 mac->ops.setup_led = e1000e_setup_led_generic;
 467                 /* cleanup LED */
 468                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 469                 /* turn on/off LED */
 470                 mac->ops.led_on = e1000_led_on_ich8lan;
 471                 mac->ops.led_off = e1000_led_off_ich8lan;
 472                 break;
 473         case e1000_pchlan:
 474                 /* ID LED init */
 475                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 476                 /* setup LED */
 477                 mac->ops.setup_led = e1000_setup_led_pchlan;
 478                 /* cleanup LED */
 479                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 480                 /* turn on/off LED */
 481                 mac->ops.led_on = e1000_led_on_pchlan;
 482                 mac->ops.led_off = e1000_led_off_pchlan;
 483                 break;
 484         default:
 485                 break;
 486         }
 487
 488         /* Enable PCS Lock-loss workaround for ICH8 */
 489         if (mac->type == e1000_ich8lan)
 490                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 491
 492         return 0;
 493 }
 494
 495 /**
 496  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 497  *  @hw: pointer to the HW structure
 498  *
 499  *  Checks to see of the link status of the hardware has changed.  If a
 500  *  change in link status has been detected, then we read the PHY registers
 501  *  to get the current speed/duplex if link exists.
 502  **/
 503 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 504 {
 505         struct e1000_mac_info *mac = &hw->mac;
 506         s32 ret_val;
 507         bool link;
 508
 509         /*
 510          * We only want to go out to the PHY registers to see if Auto-Neg
 511          * has completed and/or if our link status has changed.  The
 512          * get_link_status flag is set upon receiving a Link Status
 513          * Change or Rx Sequence Error interrupt.
 514          */
 515         if (!mac->get_link_status) {
 516                 ret_val = 0;
 517                 goto out;
 518         }
 519
 520         /*
 521          * First we want to see if the MII Status Register reports
 522          * link.  If so, then we want to get the current speed/duplex
 523          * of the PHY.
 524          */
 525         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 526         if (ret_val)
 527                 goto out;
 528
 529         if (hw->mac.type == e1000_pchlan) {
 530                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 531                 if (ret_val)
 532                         goto out;
 533         }
 534
 535         if (!link)
 536                 goto out; /* No link detected */
 537
 538         mac->get_link_status = false;
 539
 540         if (hw->phy.type == e1000_phy_82578) {
 541                 ret_val = e1000_link_stall_workaround_hv(hw);
 542                 if (ret_val)
 543                         goto out;
 544         }
 545
 546         /*
 547          * Check if there was DownShift, must be checked
 548          * immediately after link-up
 549          */
 550         e1000e_check_downshift(hw);
 551
 552         /*
 553          * If we are forcing speed/duplex, then we simply return since
 554          * we have already determined whether we have link or not.
 555          */
 556         if (!mac->autoneg) {
 557                 ret_val = -E1000_ERR_CONFIG;
 558                 goto out;
 559         }
 560
 561         /*
 562          * Auto-Neg is enabled.  Auto Speed Detection takes care
 563          * of MAC speed/duplex configuration.  So we only need to
 564          * configure Collision Distance in the MAC.
 565          */
 566         e1000e_config_collision_dist(hw);
 567
 568         /*
 569          * Configure Flow Control now that Auto-Neg has completed.
 570          * First, we need to restore the desired flow control
 571          * settings because we may have had to re-autoneg with a
 572          * different link partner.
 573          */
 574         ret_val = e1000e_config_fc_after_link_up(hw);
 575         if (ret_val)
 576                 e_dbg("Error configuring flow control\n");
 577
 578 out:
 579         return ret_val;
 580 }
 581
 582 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 583 {
 584         struct e1000_hw *hw = &adapter->hw;
 585         s32 rc;
 586
 587         rc = e1000_init_mac_params_ich8lan(adapter);
 588         if (rc)
 589                 return rc;
 590
 591         rc = e1000_init_nvm_params_ich8lan(hw);
 592         if (rc)
 593                 return rc;
 594
 595         if (hw->mac.type == e1000_pchlan)
 596                 rc = e1000_init_phy_params_pchlan(hw);
 597         else
 598                 rc = e1000_init_phy_params_ich8lan(hw);
 599         if (rc)
 600                 return rc;
 601
 602         if (adapter->hw.phy.type == e1000_phy_ife) {
 603                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 604                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 605         }
 606
 607         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 608             (adapter->hw.phy.type == e1000_phy_igp_3))
 609                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 610
 611         return 0;
 612 }
 613
 614 static DEFINE_MUTEX(nvm_mutex);
 615
 616 /**
 617  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 618  *  @hw: pointer to the HW structure
 619  *
 620  *  Acquires the mutex for performing NVM operations.
 621  **/
 622 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 623 {
 624         mutex_lock(&nvm_mutex);
 625
 626         return 0;
 627 }
 628
 629 /**
 630  *  e1000_release_nvm_ich8lan - Release NVM mutex
 631  *  @hw: pointer to the HW structure
 632  *
 633  *  Releases the mutex used while performing NVM operations.
 634  **/
 635 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 636 {
 637         mutex_unlock(&nvm_mutex);
 638
 639         return;
 640 }
 641
 642 static DEFINE_MUTEX(swflag_mutex);
 643
 644 /**
 645  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 646  *  @hw: pointer to the HW structure
 647  *
 648  *  Acquires the software control flag for performing PHY and select
 649  *  MAC CSR accesses.
 650  **/
 651 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 652 {
 653         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 654         s32 ret_val = 0;
 655
 656         mutex_lock(&swflag_mutex);
 657
 658         while (timeout) {
 659                 extcnf_ctrl = er32(EXTCNF_CTRL);
 660                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 661                         break;
 662
 663                 mdelay(1);
 664                 timeout--;
 665         }
 666
 667         if (!timeout) {
 668                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
 669                 ret_val = -E1000_ERR_CONFIG;
 670                 goto out;
 671         }
 672
 673         timeout = SW_FLAG_TIMEOUT;
 674
 675         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 676         ew32(EXTCNF_CTRL, extcnf_ctrl);
 677
 678         while (timeout) {
 679                 extcnf_ctrl = er32(EXTCNF_CTRL);
 680                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 681                         break;
 682
 683                 mdelay(1);
 684                 timeout--;
 685         }
 686
 687         if (!timeout) {
 688                 e_dbg("Failed to acquire the semaphore.\n");
 689                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 690                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 691                 ret_val = -E1000_ERR_CONFIG;
 692                 goto out;
 693         }
 694
 695 out:
 696         if (ret_val)
 697                 mutex_unlock(&swflag_mutex);
 698
 699         return ret_val;
 700 }
 701
 702 /**
 703  *  e1000_release_swflag_ich8lan - Release software control flag
 704  *  @hw: pointer to the HW structure
 705  *
 706  *  Releases the software control flag for performing PHY and select
 707  *  MAC CSR accesses.
 708  **/
 709 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 710 {
 711         u32 extcnf_ctrl;
 712
 713         extcnf_ctrl = er32(EXTCNF_CTRL);
 714         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 715         ew32(EXTCNF_CTRL, extcnf_ctrl);
 716
 717         mutex_unlock(&swflag_mutex);
 718
 719         return;
 720 }
 721
 722 /**
 723  *  e1000_check_mng_mode_ich8lan - Checks management mode
 724  *  @hw: pointer to the HW structure
 725  *
 726  *  This checks if the adapter has manageability enabled.
 727  *  This is a function pointer entry point only called by read/write
 728  *  routines for the PHY and NVM parts.
 729  **/
 730 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 731 {
 732         u32 fwsm;
 733
 734         fwsm = er32(FWSM);
 735
 736         return (fwsm & E1000_FWSM_MODE_MASK) ==
 737                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 738 }
 739
 740 /**
 741  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 742  *  @hw: pointer to the HW structure
 743  *
 744  *  Checks if firmware is blocking the reset of the PHY.
 745  *  This is a function pointer entry point only called by
 746  *  reset routines.
 747  **/
 748 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 749 {
 750         u32 fwsm;
 751
 752         fwsm = er32(FWSM);
 753
 754         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 755 }
 756
 757 /**
 758  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 759  *  @hw:   pointer to the HW structure
 760  *
 761  *  SW should configure the LCD from the NVM extended configuration region
 762  *  as a workaround for certain parts.
 763  **/
 764 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 765 {
 766         struct e1000_phy_info *phy = &hw->phy;
 767         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 768         s32 ret_val;
 769         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 770
 771         ret_val = hw->phy.ops.acquire(hw);
 772         if (ret_val)
 773                 return ret_val;
 774
 775         /*
 776          * Initialize the PHY from the NVM on ICH platforms.  This
 777          * is needed due to an issue where the NVM configuration is
 778          * not properly autoloaded after power transitions.
 779          * Therefore, after each PHY reset, we will load the
 780          * configuration data out of the NVM manually.
 781          */
 782         if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
 783                 (hw->mac.type == e1000_pchlan)) {
 784                 struct e1000_adapter *adapter = hw->adapter;
 785
 786                 /* Check if SW needs to configure the PHY */
 787                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 788                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
 789                     (hw->mac.type == e1000_pchlan))
 790                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 791                 else
 792                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 793
 794                 data = er32(FEXTNVM);
 795                 if (!(data & sw_cfg_mask))
 796                         goto out;
 797
 798                 /* Wait for basic configuration completes before proceeding */
 799                 e1000_lan_init_done_ich8lan(hw);
 800
 801                 /*
 802                  * Make sure HW does not configure LCD from PHY
 803                  * extended configuration before SW configuration
 804                  */
 805                 data = er32(EXTCNF_CTRL);
 806                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 807                         goto out;
 808
 809                 cnf_size = er32(EXTCNF_SIZE);
 810                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 811                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 812                 if (!cnf_size)
 813                         goto out;
 814
 815                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 816                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 817
 818                 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
 819                     (hw->mac.type == e1000_pchlan)) {
 820                         /*
 821                          * HW configures the SMBus address and LEDs when the
 822                          * OEM and LCD Write Enable bits are set in the NVM.
 823                          * When both NVM bits are cleared, SW will configure
 824                          * them instead.
 825                          */
 826                         data = er32(STRAP);
 827                         data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 828                         reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
 829                         reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 830                         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
 831                                                                 reg_data);
 832                         if (ret_val)
 833                                 goto out;
 834
 835                         data = er32(LEDCTL);
 836                         ret_val = e1000_write_phy_reg_hv_locked(hw,
 837                                                                 HV_LED_CONFIG,
 838                                                                 (u16)data);
 839                         if (ret_val)
 840                                 goto out;
 841                 }
 842                 /* Configure LCD from extended configuration region. */
 843
 844                 /* cnf_base_addr is in DWORD */
 845                 word_addr = (u16)(cnf_base_addr << 1);
 846
 847                 for (i = 0; i < cnf_size; i++) {
 848                         ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
 849                                                    &reg_data);
 850                         if (ret_val)
 851                                 goto out;
 852
 853                         ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
 854                                                    1, &reg_addr);
 855                         if (ret_val)
 856                                 goto out;
 857
 858                         /* Save off the PHY page for future writes. */
 859                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 860                                 phy_page = reg_data;
 861                                 continue;
 862                         }
 863
 864                         reg_addr &= PHY_REG_MASK;
 865                         reg_addr |= phy_page;
 866
 867                         ret_val = phy->ops.write_reg_locked(hw,
 868                                                             (u32)reg_addr,
 869                                                             reg_data);
 870                         if (ret_val)
 871                                 goto out;
 872                 }
 873         }
 874
 875 out:
 876         hw->phy.ops.release(hw);
 877         return ret_val;
 878 }
 879
 880 /**
 881  *  e1000_k1_gig_workaround_hv - K1 Si workaround
 882  *  @hw:   pointer to the HW structure
 883  *  @link: link up bool flag
 884  *
 885  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
 886  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
 887  *  If link is down, the function will restore the default K1 setting located
 888  *  in the NVM.
 889  **/
 890 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
 891 {
 892         s32 ret_val = 0;
 893         u16 status_reg = 0;
 894         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
 895
 896         if (hw->mac.type != e1000_pchlan)
 897                 goto out;
 898
 899         /* Wrap the whole flow with the sw flag */
 900         ret_val = hw->phy.ops.acquire(hw);
 901         if (ret_val)
 902                 goto out;
 903
 904         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
 905         if (link) {
 906                 if (hw->phy.type == e1000_phy_82578) {
 907                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
 908                                                                   &status_reg);
 909                         if (ret_val)
 910                                 goto release;
 911
 912                         status_reg &= BM_CS_STATUS_LINK_UP |
 913                                       BM_CS_STATUS_RESOLVED |
 914                                       BM_CS_STATUS_SPEED_MASK;
 915
 916                         if (status_reg == (BM_CS_STATUS_LINK_UP |
 917                                            BM_CS_STATUS_RESOLVED |
 918                                            BM_CS_STATUS_SPEED_1000))
 919                                 k1_enable = false;
 920                 }
 921
 922                 if (hw->phy.type == e1000_phy_82577) {
 923                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
 924                                                                   &status_reg);
 925                         if (ret_val)
 926                                 goto release;
 927
 928                         status_reg &= HV_M_STATUS_LINK_UP |
 929                                       HV_M_STATUS_AUTONEG_COMPLETE |
 930                                       HV_M_STATUS_SPEED_MASK;
 931
 932                         if (status_reg == (HV_M_STATUS_LINK_UP |
 933                                            HV_M_STATUS_AUTONEG_COMPLETE |
 934                                            HV_M_STATUS_SPEED_1000))
 935                                 k1_enable = false;
 936                 }
 937
 938                 /* Link stall fix for link up */
 939                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
 940                                                            0x0100);
 941                 if (ret_val)
 942                         goto release;
 943
 944         } else {
 945                 /* Link stall fix for link down */
 946                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
 947                                                            0x4100);
 948                 if (ret_val)
 949                         goto release;
 950         }
 951
 952         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
 953
 954 release:
 955         hw->phy.ops.release(hw);
 956 out:
 957         return ret_val;
 958 }
 959
 960 /**
 961  *  e1000_configure_k1_ich8lan - Configure K1 power state
 962  *  @hw: pointer to the HW structure
 963  *  @enable: K1 state to configure
 964  *
 965  *  Configure the K1 power state based on the provided parameter.
 966  *  Assumes semaphore already acquired.
 967  *
 968  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
 969  **/
 970 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
 971 {
 972         s32 ret_val = 0;
 973         u32 ctrl_reg = 0;
 974         u32 ctrl_ext = 0;
 975         u32 reg = 0;
 976         u16 kmrn_reg = 0;
 977
 978         ret_val = e1000e_read_kmrn_reg_locked(hw,
 979                                              E1000_KMRNCTRLSTA_K1_CONFIG,
 980                                              &kmrn_reg);
 981         if (ret_val)
 982                 goto out;
 983
 984         if (k1_enable)
 985                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
 986         else
 987                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
 988
 989         ret_val = e1000e_write_kmrn_reg_locked(hw,
 990                                               E1000_KMRNCTRLSTA_K1_CONFIG,
 991                                               kmrn_reg);
 992         if (ret_val)
 993                 goto out;
 994
 995         udelay(20);
 996         ctrl_ext = er32(CTRL_EXT);
 997         ctrl_reg = er32(CTRL);
 998
 999         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1000         reg |= E1000_CTRL_FRCSPD;
1001         ew32(CTRL, reg);
1002
1003         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1004         udelay(20);
1005         ew32(CTRL, ctrl_reg);
1006         ew32(CTRL_EXT, ctrl_ext);
1007         udelay(20);
1008
1009 out:
1010         return ret_val;
1011 }
1012
1013 /**
1014  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1015  *  @hw:       pointer to the HW structure
1016  *  @d0_state: boolean if entering d0 or d3 device state
1017  *
1018  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1019  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1020  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1021  **/
1022 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1023 {
1024         s32 ret_val = 0;
1025         u32 mac_reg;
1026         u16 oem_reg;
1027
1028         if (hw->mac.type != e1000_pchlan)
1029                 return ret_val;
1030
1031         ret_val = hw->phy.ops.acquire(hw);
1032         if (ret_val)
1033                 return ret_val;
1034
1035         mac_reg = er32(EXTCNF_CTRL);
1036         if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1037                 goto out;
1038
1039         mac_reg = er32(FEXTNVM);
1040         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1041                 goto out;
1042
1043         mac_reg = er32(PHY_CTRL);
1044
1045         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1046         if (ret_val)
1047                 goto out;
1048
1049         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1050
1051         if (d0_state) {
1052                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1053                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1054
1055                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1056                         oem_reg |= HV_OEM_BITS_LPLU;
1057         } else {
1058                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1059                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1060
1061                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1062                         oem_reg |= HV_OEM_BITS_LPLU;
1063         }
1064         /* Restart auto-neg to activate the bits */
1065         if (!e1000_check_reset_block(hw))
1066                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1067         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1068
1069 out:
1070         hw->phy.ops.release(hw);
1071
1072         return ret_val;
1073 }
1074
1075
1076 /**
1077  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1078  *  done after every PHY reset.
1079  **/
1080 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1081 {
1082         s32 ret_val = 0;
1083
1084         if (hw->mac.type != e1000_pchlan)
1085                 return ret_val;
1086
1087         if (((hw->phy.type == e1000_phy_82577) &&
1088              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1089             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1090                 /* Disable generation of early preamble */
1091                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1092                 if (ret_val)
1093                         return ret_val;
1094
1095                 /* Preamble tuning for SSC */
1096                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1097                 if (ret_val)
1098                         return ret_val;
1099         }
1100
1101         if (hw->phy.type == e1000_phy_82578) {
1102                 /*
1103                  * Return registers to default by doing a soft reset then
1104                  * writing 0x3140 to the control register.
1105                  */
1106                 if (hw->phy.revision < 2) {
1107                         e1000e_phy_sw_reset(hw);
1108                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1109                 }
1110         }
1111
1112         /* Select page 0 */
1113         ret_val = hw->phy.ops.acquire(hw);
1114         if (ret_val)
1115                 return ret_val;
1116
1117         hw->phy.addr = 1;
1118         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1119         if (ret_val)
1120                 goto out;
1121         hw->phy.ops.release(hw);
1122
1123         /*
1124          * Configure the K1 Si workaround during phy reset assuming there is
1125          * link so that it disables K1 if link is in 1Gbps.
1126          */
1127         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1128
1129 out:
1130         return ret_val;
1131 }
1132
1133 /**
1134  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1135  *  @hw: pointer to the HW structure
1136  *
1137  *  Check the appropriate indication the MAC has finished configuring the
1138  *  PHY after a software reset.
1139  **/
1140 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1141 {
1142         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1143
1144         /* Wait for basic configuration completes before proceeding */
1145         do {
1146                 data = er32(STATUS);
1147                 data &= E1000_STATUS_LAN_INIT_DONE;
1148                 udelay(100);
1149         } while ((!data) && --loop);
1150
1151         /*
1152          * If basic configuration is incomplete before the above loop
1153          * count reaches 0, loading the configuration from NVM will
1154          * leave the PHY in a bad state possibly resulting in no link.
1155          */
1156         if (loop == 0)
1157                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1158
1159         /* Clear the Init Done bit for the next init event */
1160         data = er32(STATUS);
1161         data &= ~E1000_STATUS_LAN_INIT_DONE;
1162         ew32(STATUS, data);
1163 }
1164
1165 /**
1166  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1167  *  @hw: pointer to the HW structure
1168  *
1169  *  Resets the PHY
1170  *  This is a function pointer entry point called by drivers
1171  *  or other shared routines.
1172  **/
1173 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1174 {
1175         s32 ret_val = 0;
1176         u16 reg;
1177
1178         ret_val = e1000e_phy_hw_reset_generic(hw);
1179         if (ret_val)
1180                 return ret_val;
1181
1182         /* Allow time for h/w to get to a quiescent state after reset */
1183         mdelay(10);
1184
1185         if (hw->mac.type == e1000_pchlan) {
1186                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1187                 if (ret_val)
1188                         return ret_val;
1189         }
1190
1191         /* Dummy read to clear the phy wakeup bit after lcd reset */
1192         if (hw->mac.type == e1000_pchlan)
1193                 e1e_rphy(hw, BM_WUC, &reg);
1194
1195         /* Configure the LCD with the extended configuration region in NVM */
1196         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1197         if (ret_val)
1198                 goto out;
1199
1200         /* Configure the LCD with the OEM bits in NVM */
1201         if (hw->mac.type == e1000_pchlan)
1202                 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1203
1204 out:
1205         return 0;
1206 }
1207
1208 /**
1209  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1210  *  @hw: pointer to the HW structure
1211  *  @active: true to enable LPLU, false to disable
1212  *
1213  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1214  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1215  *  the phy speed. This function will manually set the LPLU bit and restart
1216  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1217  *  since it configures the same bit.
1218  **/
1219 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1220 {
1221         s32 ret_val = 0;
1222         u16 oem_reg;
1223
1224         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1225         if (ret_val)
1226                 goto out;
1227
1228         if (active)
1229                 oem_reg |= HV_OEM_BITS_LPLU;
1230         else
1231                 oem_reg &= ~HV_OEM_BITS_LPLU;
1232
1233         oem_reg |= HV_OEM_BITS_RESTART_AN;
1234         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1235
1236 out:
1237         return ret_val;
1238 }
1239
1240 /**
1241  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1242  *  @hw: pointer to the HW structure
1243  *  @active: true to enable LPLU, false to disable
1244  *
1245  *  Sets the LPLU D0 state according to the active flag.  When
1246  *  activating LPLU this function also disables smart speed
1247  *  and vice versa.  LPLU will not be activated unless the
1248  *  device autonegotiation advertisement meets standards of
1249  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1250  *  This is a function pointer entry point only called by
1251  *  PHY setup routines.
1252  **/
1253 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1254 {
1255         struct e1000_phy_info *phy = &hw->phy;
1256         u32 phy_ctrl;
1257         s32 ret_val = 0;
1258         u16 data;
1259
1260         if (phy->type == e1000_phy_ife)
1261                 return ret_val;
1262
1263         phy_ctrl = er32(PHY_CTRL);
1264
1265         if (active) {
1266                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1267                 ew32(PHY_CTRL, phy_ctrl);
1268
1269                 if (phy->type != e1000_phy_igp_3)
1270                         return 0;
1271
1272                 /*
1273                  * Call gig speed drop workaround on LPLU before accessing
1274                  * any PHY registers
1275                  */
1276                 if (hw->mac.type == e1000_ich8lan)
1277                         e1000e_gig_downshift_workaround_ich8lan(hw);
1278
1279                 /* When LPLU is enabled, we should disable SmartSpeed */
1280                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1281                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1282                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1283                 if (ret_val)
1284                         return ret_val;
1285         } else {
1286                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1287                 ew32(PHY_CTRL, phy_ctrl);
1288
1289                 if (phy->type != e1000_phy_igp_3)
1290                         return 0;
1291
1292                 /*
1293                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1294                  * during Dx states where the power conservation is most
1295                  * important.  During driver activity we should enable
1296                  * SmartSpeed, so performance is maintained.
1297                  */
1298                 if (phy->smart_speed == e1000_smart_speed_on) {
1299                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1300                                            &data);
1301                         if (ret_val)
1302                                 return ret_val;
1303
1304                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1305                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1306                                            data);
1307                         if (ret_val)
1308                                 return ret_val;
1309                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1310                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1311                                            &data);
1312                         if (ret_val)
1313                                 return ret_val;
1314
1315                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1316                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1317                                            data);
1318                         if (ret_val)
1319                                 return ret_val;
1320                 }
1321         }
1322
1323         return 0;
1324 }
1325
1326 /**
1327  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1328  *  @hw: pointer to the HW structure
1329  *  @active: true to enable LPLU, false to disable
1330  *
1331  *  Sets the LPLU D3 state according to the active flag.  When
1332  *  activating LPLU this function also disables smart speed
1333  *  and vice versa.  LPLU will not be activated unless the
1334  *  device autonegotiation advertisement meets standards of
1335  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1336  *  This is a function pointer entry point only called by
1337  *  PHY setup routines.
1338  **/
1339 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1340 {
1341         struct e1000_phy_info *phy = &hw->phy;
1342         u32 phy_ctrl;
1343         s32 ret_val;
1344         u16 data;
1345
1346         phy_ctrl = er32(PHY_CTRL);
1347
1348         if (!active) {
1349                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1350                 ew32(PHY_CTRL, phy_ctrl);
1351
1352                 if (phy->type != e1000_phy_igp_3)
1353                         return 0;
1354
1355                 /*
1356                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1357                  * during Dx states where the power conservation is most
1358                  * important.  During driver activity we should enable
1359                  * SmartSpeed, so performance is maintained.
1360                  */
1361                 if (phy->smart_speed == e1000_smart_speed_on) {
1362                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1363                                            &data);
1364                         if (ret_val)
1365                                 return ret_val;
1366
1367                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1368                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1369                                            data);
1370                         if (ret_val)
1371                                 return ret_val;
1372                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1373                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1374                                            &data);
1375                         if (ret_val)
1376                                 return ret_val;
1377
1378                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1379                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1380                                            data);
1381                         if (ret_val)
1382                                 return ret_val;
1383                 }
1384         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1385                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1386                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1387                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1388                 ew32(PHY_CTRL, phy_ctrl);
1389
1390                 if (phy->type != e1000_phy_igp_3)
1391                         return 0;
1392
1393                 /*
1394                  * Call gig speed drop workaround on LPLU before accessing
1395                  * any PHY registers
1396                  */
1397                 if (hw->mac.type == e1000_ich8lan)
1398                         e1000e_gig_downshift_workaround_ich8lan(hw);
1399
1400                 /* When LPLU is enabled, we should disable SmartSpeed */
1401                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1402                 if (ret_val)
1403                         return ret_val;
1404
1405                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1406                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1407         }
1408
1409         return 0;
1410 }
1411
1412 /**
1413  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1414  *  @hw: pointer to the HW structure
1415  *  @bank:  pointer to the variable that returns the active bank
1416  *
1417  *  Reads signature byte from the NVM using the flash access registers.
1418  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1419  **/
1420 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1421 {
1422         u32 eecd;
1423         struct e1000_nvm_info *nvm = &hw->nvm;
1424         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1425         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1426         u8 sig_byte = 0;
1427         s32 ret_val = 0;
1428
1429         switch (hw->mac.type) {
1430         case e1000_ich8lan:
1431         case e1000_ich9lan:
1432                 eecd = er32(EECD);
1433                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1434                     E1000_EECD_SEC1VAL_VALID_MASK) {
1435                         if (eecd & E1000_EECD_SEC1VAL)
1436                                 *bank = 1;
1437                         else
1438                                 *bank = 0;
1439
1440                         return 0;
1441                 }
1442                 e_dbg("Unable to determine valid NVM bank via EEC - "
1443                        "reading flash signature\n");
1444                 /* fall-thru */
1445         default:
1446                 /* set bank to 0 in case flash read fails */
1447                 *bank = 0;
1448
1449                 /* Check bank 0 */
1450                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1451                                                         &sig_byte);
1452                 if (ret_val)
1453                         return ret_val;
1454                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1455                     E1000_ICH_NVM_SIG_VALUE) {
1456                         *bank = 0;
1457                         return 0;
1458                 }
1459
1460                 /* Check bank 1 */
1461                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1462                                                         bank1_offset,
1463                                                         &sig_byte);
1464                 if (ret_val)
1465                         return ret_val;
1466                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1467                     E1000_ICH_NVM_SIG_VALUE) {
1468                         *bank = 1;
1469                         return 0;
1470                 }
1471
1472                 e_dbg("ERROR: No valid NVM bank present\n");
1473                 return -E1000_ERR_NVM;
1474         }
1475
1476         return 0;
1477 }
1478
1479 /**
1480  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1481  *  @hw: pointer to the HW structure
1482  *  @offset: The offset (in bytes) of the word(s) to read.
1483  *  @words: Size of data to read in words
1484  *  @data: Pointer to the word(s) to read at offset.
1485  *
1486  *  Reads a word(s) from the NVM using the flash access registers.
1487  **/
1488 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1489                                   u16 *data)
1490 {
1491         struct e1000_nvm_info *nvm = &hw->nvm;
1492         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1493         u32 act_offset;
1494         s32 ret_val = 0;
1495         u32 bank = 0;
1496         u16 i, word;
1497
1498         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1499             (words == 0)) {
1500                 e_dbg("nvm parameter(s) out of bounds\n");
1501                 ret_val = -E1000_ERR_NVM;
1502                 goto out;
1503         }
1504
1505         nvm->ops.acquire(hw);
1506
1507         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1508         if (ret_val) {
1509                 e_dbg("Could not detect valid bank, assuming bank 0\n");
1510                 bank = 0;
1511         }
1512
1513         act_offset = (bank) ? nvm->flash_bank_size : 0;
1514         act_offset += offset;
1515
1516         ret_val = 0;
1517         for (i = 0; i < words; i++) {
1518                 if ((dev_spec->shadow_ram) &&
1519                     (dev_spec->shadow_ram[offset+i].modified)) {
1520                         data[i] = dev_spec->shadow_ram[offset+i].value;
1521                 } else {
1522                         ret_val = e1000_read_flash_word_ich8lan(hw,
1523                                                                 act_offset + i,
1524                                                                 &word);
1525                         if (ret_val)
1526                                 break;
1527                         data[i] = word;
1528                 }
1529         }
1530
1531         nvm->ops.release(hw);
1532
1533 out:
1534         if (ret_val)
1535                 e_dbg("NVM read error: %d\n", ret_val);
1536
1537         return ret_val;
1538 }
1539
1540 /**
1541  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1542  *  @hw: pointer to the HW structure
1543  *
1544  *  This function does initial flash setup so that a new read/write/erase cycle
1545  *  can be started.
1546  **/
1547 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1548 {
1549         union ich8_hws_flash_status hsfsts;
1550         s32 ret_val = -E1000_ERR_NVM;
1551         s32 i = 0;
1552
1553         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1554
1555         /* Check if the flash descriptor is valid */
1556         if (hsfsts.hsf_status.fldesvalid == 0) {
1557                 e_dbg("Flash descriptor invalid.  "
1558                          "SW Sequencing must be used.");
1559                 return -E1000_ERR_NVM;
1560         }
1561
1562         /* Clear FCERR and DAEL in hw status by writing 1 */
1563         hsfsts.hsf_status.flcerr = 1;
1564         hsfsts.hsf_status.dael = 1;
1565
1566         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1567
1568         /*
1569          * Either we should have a hardware SPI cycle in progress
1570          * bit to check against, in order to start a new cycle or
1571          * FDONE bit should be changed in the hardware so that it
1572          * is 1 after hardware reset, which can then be used as an
1573          * indication whether a cycle is in progress or has been
1574          * completed.
1575          */
1576
1577         if (hsfsts.hsf_status.flcinprog == 0) {
1578                 /*
1579                  * There is no cycle running at present,
1580                  * so we can start a cycle.
1581                  * Begin by setting Flash Cycle Done.
1582                  */
1583                 hsfsts.hsf_status.flcdone = 1;
1584                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1585                 ret_val = 0;
1586         } else {
1587                 /*
1588                  * Otherwise poll for sometime so the current
1589                  * cycle has a chance to end before giving up.
1590                  */
1591                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1592                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1593                         if (hsfsts.hsf_status.flcinprog == 0) {
1594                                 ret_val = 0;
1595                                 break;
1596                         }
1597                         udelay(1);
1598                 }
1599                 if (ret_val == 0) {
1600                         /*
1601                          * Successful in waiting for previous cycle to timeout,
1602                          * now set the Flash Cycle Done.
1603                          */
1604                         hsfsts.hsf_status.flcdone = 1;
1605                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1606                 } else {
1607                         e_dbg("Flash controller busy, cannot get access");
1608                 }
1609         }
1610
1611         return ret_val;
1612 }
1613
1614 /**
1615  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1616  *  @hw: pointer to the HW structure
1617  *  @timeout: maximum time to wait for completion
1618  *
1619  *  This function starts a flash cycle and waits for its completion.
1620  **/
1621 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1622 {
1623         union ich8_hws_flash_ctrl hsflctl;
1624         union ich8_hws_flash_status hsfsts;
1625         s32 ret_val = -E1000_ERR_NVM;
1626         u32 i = 0;
1627
1628         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1629         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1630         hsflctl.hsf_ctrl.flcgo = 1;
1631         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1632
1633         /* wait till FDONE bit is set to 1 */
1634         do {
1635                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1636                 if (hsfsts.hsf_status.flcdone == 1)
1637                         break;
1638                 udelay(1);
1639         } while (i++ < timeout);
1640
1641         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1642                 return 0;
1643
1644         return ret_val;
1645 }
1646
1647 /**
1648  *  e1000_read_flash_word_ich8lan - Read word from flash
1649  *  @hw: pointer to the HW structure
1650  *  @offset: offset to data location
1651  *  @data: pointer to the location for storing the data
1652  *
1653  *  Reads the flash word at offset into data.  Offset is converted
1654  *  to bytes before read.
1655  **/
1656 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1657                                          u16 *data)
1658 {
1659         /* Must convert offset into bytes. */
1660         offset <<= 1;
1661
1662         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1663 }
1664
1665 /**
1666  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1667  *  @hw: pointer to the HW structure
1668  *  @offset: The offset of the byte to read.
1669  *  @data: Pointer to a byte to store the value read.
1670  *
1671  *  Reads a single byte from the NVM using the flash access registers.
1672  **/
1673 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1674                                          u8 *data)
1675 {
1676         s32 ret_val;
1677         u16 word = 0;
1678
1679         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1680         if (ret_val)
1681                 return ret_val;
1682
1683         *data = (u8)word;
1684
1685         return 0;
1686 }
1687
1688 /**
1689  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1690  *  @hw: pointer to the HW structure
1691  *  @offset: The offset (in bytes) of the byte or word to read.
1692  *  @size: Size of data to read, 1=byte 2=word
1693  *  @data: Pointer to the word to store the value read.
1694  *
1695  *  Reads a byte or word from the NVM using the flash access registers.
1696  **/
1697 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1698                                          u8 size, u16 *data)
1699 {
1700         union ich8_hws_flash_status hsfsts;
1701         union ich8_hws_flash_ctrl hsflctl;
1702         u32 flash_linear_addr;
1703         u32 flash_data = 0;
1704         s32 ret_val = -E1000_ERR_NVM;
1705         u8 count = 0;
1706
1707         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1708                 return -E1000_ERR_NVM;
1709
1710         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1711                             hw->nvm.flash_base_addr;
1712
1713         do {
1714                 udelay(1);
1715                 /* Steps */
1716                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1717                 if (ret_val != 0)
1718                         break;
1719
1720                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1721                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1722                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1723                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1724                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1725
1726                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1727
1728                 ret_val = e1000_flash_cycle_ich8lan(hw,
1729                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1730
1731                 /*
1732                  * Check if FCERR is set to 1, if set to 1, clear it
1733                  * and try the whole sequence a few more times, else
1734                  * read in (shift in) the Flash Data0, the order is
1735                  * least significant byte first msb to lsb
1736                  */
1737                 if (ret_val == 0) {
1738                         flash_data = er32flash(ICH_FLASH_FDATA0);
1739                         if (size == 1) {
1740                                 *data = (u8)(flash_data & 0x000000FF);
1741                         } else if (size == 2) {
1742                                 *data = (u16)(flash_data & 0x0000FFFF);
1743                         }
1744                         break;
1745                 } else {
1746                         /*
1747                          * If we've gotten here, then things are probably
1748                          * completely hosed, but if the error condition is
1749                          * detected, it won't hurt to give it another try...
1750                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1751                          */
1752                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1753                         if (hsfsts.hsf_status.flcerr == 1) {
1754                                 /* Repeat for some time before giving up. */
1755                                 continue;
1756                         } else if (hsfsts.hsf_status.flcdone == 0) {
1757                                 e_dbg("Timeout error - flash cycle "
1758                                          "did not complete.");
1759                                 break;
1760                         }
1761                 }
1762         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1763
1764         return ret_val;
1765 }
1766
1767 /**
1768  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1769  *  @hw: pointer to the HW structure
1770  *  @offset: The offset (in bytes) of the word(s) to write.
1771  *  @words: Size of data to write in words
1772  *  @data: Pointer to the word(s) to write at offset.
1773  *
1774  *  Writes a byte or word to the NVM using the flash access registers.
1775  **/
1776 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1777                                    u16 *data)
1778 {
1779         struct e1000_nvm_info *nvm = &hw->nvm;
1780         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1781         u16 i;
1782
1783         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1784             (words == 0)) {
1785                 e_dbg("nvm parameter(s) out of bounds\n");
1786                 return -E1000_ERR_NVM;
1787         }
1788
1789         nvm->ops.acquire(hw);
1790
1791         for (i = 0; i < words; i++) {
1792                 dev_spec->shadow_ram[offset+i].modified = true;
1793                 dev_spec->shadow_ram[offset+i].value = data[i];
1794         }
1795
1796         nvm->ops.release(hw);
1797
1798         return 0;
1799 }
1800
1801 /**
1802  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1803  *  @hw: pointer to the HW structure
1804  *
1805  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1806  *  which writes the checksum to the shadow ram.  The changes in the shadow
1807  *  ram are then committed to the EEPROM by processing each bank at a time
1808  *  checking for the modified bit and writing only the pending changes.
1809  *  After a successful commit, the shadow ram is cleared and is ready for
1810  *  future writes.
1811  **/
1812 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1813 {
1814         struct e1000_nvm_info *nvm = &hw->nvm;
1815         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1816         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1817         s32 ret_val;
1818         u16 data;
1819
1820         ret_val = e1000e_update_nvm_checksum_generic(hw);
1821         if (ret_val)
1822                 goto out;
1823
1824         if (nvm->type != e1000_nvm_flash_sw)
1825                 goto out;
1826
1827         nvm->ops.acquire(hw);
1828
1829         /*
1830          * We're writing to the opposite bank so if we're on bank 1,
1831          * write to bank 0 etc.  We also need to erase the segment that
1832          * is going to be written
1833          */
1834         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1835         if (ret_val) {
1836                 e_dbg("Could not detect valid bank, assuming bank 0\n");
1837                 bank = 0;
1838         }
1839
1840         if (bank == 0) {
1841                 new_bank_offset = nvm->flash_bank_size;
1842                 old_bank_offset = 0;
1843                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1844                 if (ret_val) {
1845                         nvm->ops.release(hw);
1846                         goto out;
1847                 }
1848         } else {
1849                 old_bank_offset = nvm->flash_bank_size;
1850                 new_bank_offset = 0;
1851                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1852                 if (ret_val) {
1853                         nvm->ops.release(hw);
1854                         goto out;
1855                 }
1856         }
1857
1858         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1859                 /*
1860                  * Determine whether to write the value stored
1861                  * in the other NVM bank or a modified value stored
1862                  * in the shadow RAM
1863                  */
1864                 if (dev_spec->shadow_ram[i].modified) {
1865                         data = dev_spec->shadow_ram[i].value;
1866                 } else {
1867                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
1868                                                                 old_bank_offset,
1869                                                                 &data);
1870                         if (ret_val)
1871                                 break;
1872                 }
1873
1874                 /*
1875                  * If the word is 0x13, then make sure the signature bits
1876                  * (15:14) are 11b until the commit has completed.
1877                  * This will allow us to write 10b which indicates the
1878                  * signature is valid.  We want to do this after the write
1879                  * has completed so that we don't mark the segment valid
1880                  * while the write is still in progress
1881                  */
1882                 if (i == E1000_ICH_NVM_SIG_WORD)
1883                         data |= E1000_ICH_NVM_SIG_MASK;
1884
1885                 /* Convert offset to bytes. */
1886                 act_offset = (i + new_bank_offset) << 1;
1887
1888                 udelay(100);
1889                 /* Write the bytes to the new bank. */
1890                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1891                                                                act_offset,
1892                                                                (u8)data);
1893                 if (ret_val)
1894                         break;
1895
1896                 udelay(100);
1897                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1898                                                           act_offset + 1,
1899                                                           (u8)(data >> 8));
1900                 if (ret_val)
1901                         break;
1902         }
1903
1904         /*
1905          * Don't bother writing the segment valid bits if sector
1906          * programming failed.
1907          */
1908         if (ret_val) {
1909                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1910                 e_dbg("Flash commit failed.\n");
1911                 nvm->ops.release(hw);
1912                 goto out;
1913         }
1914
1915         /*
1916          * Finally validate the new segment by setting bit 15:14
1917          * to 10b in word 0x13 , this can be done without an
1918          * erase as well since these bits are 11 to start with
1919          * and we need to change bit 14 to 0b
1920          */
1921         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1922         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1923         if (ret_val) {
1924                 nvm->ops.release(hw);
1925                 goto out;
1926         }
1927         data &= 0xBFFF;
1928         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1929                                                        act_offset * 2 + 1,
1930                                                        (u8)(data >> 8));
1931         if (ret_val) {
1932                 nvm->ops.release(hw);
1933                 goto out;
1934         }
1935
1936         /*
1937          * And invalidate the previously valid segment by setting
1938          * its signature word (0x13) high_byte to 0b. This can be
1939          * done without an erase because flash erase sets all bits
1940          * to 1's. We can write 1's to 0's without an erase
1941          */
1942         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1943         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1944         if (ret_val) {
1945                 nvm->ops.release(hw);
1946                 goto out;
1947         }
1948
1949         /* Great!  Everything worked, we can now clear the cached entries. */
1950         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1951                 dev_spec->shadow_ram[i].modified = false;
1952                 dev_spec->shadow_ram[i].value = 0xFFFF;
1953         }
1954
1955         nvm->ops.release(hw);
1956
1957         /*
1958          * Reload the EEPROM, or else modifications will not appear
1959          * until after the next adapter reset.
1960          */
1961         e1000e_reload_nvm(hw);
1962         msleep(10);
1963
1964 out:
1965         if (ret_val)
1966                 e_dbg("NVM update error: %d\n", ret_val);
1967
1968         return ret_val;
1969 }
1970
1971 /**
1972  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1973  *  @hw: pointer to the HW structure
1974  *
1975  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1976  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1977  *  calculated, in which case we need to calculate the checksum and set bit 6.
1978  **/
1979 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1980 {
1981         s32 ret_val;
1982         u16 data;
1983
1984         /*
1985          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1986          * needs to be fixed.  This bit is an indication that the NVM
1987          * was prepared by OEM software and did not calculate the
1988          * checksum...a likely scenario.
1989          */
1990         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1991         if (ret_val)
1992                 return ret_val;
1993
1994         if ((data & 0x40) == 0) {
1995                 data |= 0x40;
1996                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1997                 if (ret_val)
1998                         return ret_val;
1999                 ret_val = e1000e_update_nvm_checksum(hw);
2000                 if (ret_val)
2001                         return ret_val;
2002         }
2003
2004         return e1000e_validate_nvm_checksum_generic(hw);
2005 }
2006
2007 /**
2008  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2009  *  @hw: pointer to the HW structure
2010  *
2011  *  To prevent malicious write/erase of the NVM, set it to be read-only
2012  *  so that the hardware ignores all write/erase cycles of the NVM via
2013  *  the flash control registers.  The shadow-ram copy of the NVM will
2014  *  still be updated, however any updates to this copy will not stick
2015  *  across driver reloads.
2016  **/
2017 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2018 {
2019         struct e1000_nvm_info *nvm = &hw->nvm;
2020         union ich8_flash_protected_range pr0;
2021         union ich8_hws_flash_status hsfsts;
2022         u32 gfpreg;
2023
2024         nvm->ops.acquire(hw);
2025
2026         gfpreg = er32flash(ICH_FLASH_GFPREG);
2027
2028         /* Write-protect GbE Sector of NVM */
2029         pr0.regval = er32flash(ICH_FLASH_PR0);
2030         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2031         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2032         pr0.range.wpe = true;
2033         ew32flash(ICH_FLASH_PR0, pr0.regval);
2034
2035         /*
2036          * Lock down a subset of GbE Flash Control Registers, e.g.
2037          * PR0 to prevent the write-protection from being lifted.
2038          * Once FLOCKDN is set, the registers protected by it cannot
2039          * be written until FLOCKDN is cleared by a hardware reset.
2040          */
2041         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2042         hsfsts.hsf_status.flockdn = true;
2043         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2044
2045         nvm->ops.release(hw);
2046 }
2047
2048 /**
2049  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2050  *  @hw: pointer to the HW structure
2051  *  @offset: The offset (in bytes) of the byte/word to read.
2052  *  @size: Size of data to read, 1=byte 2=word
2053  *  @data: The byte(s) to write to the NVM.
2054  *
2055  *  Writes one/two bytes to the NVM using the flash access registers.
2056  **/
2057 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2058                                           u8 size, u16 data)
2059 {
2060         union ich8_hws_flash_status hsfsts;
2061         union ich8_hws_flash_ctrl hsflctl;
2062         u32 flash_linear_addr;
2063         u32 flash_data = 0;
2064         s32 ret_val;
2065         u8 count = 0;
2066
2067         if (size < 1 || size > 2 || data > size * 0xff ||
2068             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2069                 return -E1000_ERR_NVM;
2070
2071         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2072                             hw->nvm.flash_base_addr;
2073
2074         do {
2075                 udelay(1);
2076                 /* Steps */
2077                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2078                 if (ret_val)
2079                         break;
2080
2081                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2082                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2083                 hsflctl.hsf_ctrl.fldbcount = size -1;
2084                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2085                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2086
2087                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2088
2089                 if (size == 1)
2090                         flash_data = (u32)data & 0x00FF;
2091                 else
2092                         flash_data = (u32)data;
2093
2094                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2095
2096                 /*
2097                  * check if FCERR is set to 1 , if set to 1, clear it
2098                  * and try the whole sequence a few more times else done
2099                  */
2100                 ret_val = e1000_flash_cycle_ich8lan(hw,
2101                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2102                 if (!ret_val)
2103                         break;
2104
2105                 /*
2106                  * If we're here, then things are most likely
2107                  * completely hosed, but if the error condition
2108                  * is detected, it won't hurt to give it another
2109                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2110                  */
2111                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2112                 if (hsfsts.hsf_status.flcerr == 1)
2113                         /* Repeat for some time before giving up. */
2114                         continue;
2115                 if (hsfsts.hsf_status.flcdone == 0) {
2116                         e_dbg("Timeout error - flash cycle "
2117                                  "did not complete.");
2118                         break;
2119                 }
2120         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2121
2122         return ret_val;
2123 }
2124
2125 /**
2126  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2127  *  @hw: pointer to the HW structure
2128  *  @offset: The index of the byte to read.
2129  *  @data: The byte to write to the NVM.
2130  *
2131  *  Writes a single byte to the NVM using the flash access registers.
2132  **/
2133 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2134                                           u8 data)
2135 {
2136         u16 word = (u16)data;
2137
2138         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2139 }
2140
2141 /**
2142  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2143  *  @hw: pointer to the HW structure
2144  *  @offset: The offset of the byte to write.
2145  *  @byte: The byte to write to the NVM.
2146  *
2147  *  Writes a single byte to the NVM using the flash access registers.
2148  *  Goes through a retry algorithm before giving up.
2149  **/
2150 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2151                                                 u32 offset, u8 byte)
2152 {
2153         s32 ret_val;
2154         u16 program_retries;
2155
2156         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2157         if (!ret_val)
2158                 return ret_val;
2159
2160         for (program_retries = 0; program_retries < 100; program_retries++) {
2161                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2162                 udelay(100);
2163                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2164                 if (!ret_val)
2165                         break;
2166         }
2167         if (program_retries == 100)
2168                 return -E1000_ERR_NVM;
2169
2170         return 0;
2171 }
2172
2173 /**
2174  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2175  *  @hw: pointer to the HW structure
2176  *  @bank: 0 for first bank, 1 for second bank, etc.
2177  *
2178  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2179  *  bank N is 4096 * N + flash_reg_addr.
2180  **/
2181 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2182 {
2183         struct e1000_nvm_info *nvm = &hw->nvm;
2184         union ich8_hws_flash_status hsfsts;
2185         union ich8_hws_flash_ctrl hsflctl;
2186         u32 flash_linear_addr;
2187         /* bank size is in 16bit words - adjust to bytes */
2188         u32 flash_bank_size = nvm->flash_bank_size * 2;
2189         s32 ret_val;
2190         s32 count = 0;
2191         s32 j, iteration, sector_size;
2192
2193         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2194
2195         /*
2196          * Determine HW Sector size: Read BERASE bits of hw flash status
2197          * register
2198          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2199          *     consecutive sectors.  The start index for the nth Hw sector
2200          *     can be calculated as = bank * 4096 + n * 256
2201          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2202          *     The start index for the nth Hw sector can be calculated
2203          *     as = bank * 4096
2204          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2205          *     (ich9 only, otherwise error condition)
2206          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2207          */
2208         switch (hsfsts.hsf_status.berasesz) {
2209         case 0:
2210                 /* Hw sector size 256 */
2211                 sector_size = ICH_FLASH_SEG_SIZE_256;
2212                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2213                 break;
2214         case 1:
2215                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2216                 iteration = 1;
2217                 break;
2218         case 2:
2219                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2220                 iteration = 1;
2221                 break;
2222         case 3:
2223                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2224                 iteration = 1;
2225                 break;
2226         default:
2227                 return -E1000_ERR_NVM;
2228         }
2229
2230         /* Start with the base address, then add the sector offset. */
2231         flash_linear_addr = hw->nvm.flash_base_addr;
2232         flash_linear_addr += (bank) ? flash_bank_size : 0;
2233
2234         for (j = 0; j < iteration ; j++) {
2235                 do {
2236                         /* Steps */
2237                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2238                         if (ret_val)
2239                                 return ret_val;
2240
2241                         /*
2242                          * Write a value 11 (block Erase) in Flash
2243                          * Cycle field in hw flash control
2244                          */
2245                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2246                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2247                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2248
2249                         /*
2250                          * Write the last 24 bits of an index within the
2251                          * block into Flash Linear address field in Flash
2252                          * Address.
2253                          */
2254                         flash_linear_addr += (j * sector_size);
2255                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2256
2257                         ret_val = e1000_flash_cycle_ich8lan(hw,
2258                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2259                         if (ret_val == 0)
2260                                 break;
2261
2262                         /*
2263                          * Check if FCERR is set to 1.  If 1,
2264                          * clear it and try the whole sequence
2265                          * a few more times else Done
2266                          */
2267                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2268                         if (hsfsts.hsf_status.flcerr == 1)
2269                                 /* repeat for some time before giving up */
2270                                 continue;
2271                         else if (hsfsts.hsf_status.flcdone == 0)
2272                                 return ret_val;
2273                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2274         }
2275
2276         return 0;
2277 }
2278
2279 /**
2280  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2281  *  @hw: pointer to the HW structure
2282  *  @data: Pointer to the LED settings
2283  *
2284  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2285  *  settings is all 0's or F's, set the LED default to a valid LED default
2286  *  setting.
2287  **/
2288 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2289 {
2290         s32 ret_val;
2291
2292         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2293         if (ret_val) {
2294                 e_dbg("NVM Read Error\n");
2295                 return ret_val;
2296         }
2297
2298         if (*data == ID_LED_RESERVED_0000 ||
2299             *data == ID_LED_RESERVED_FFFF)
2300                 *data = ID_LED_DEFAULT_ICH8LAN;
2301
2302         return 0;
2303 }
2304
2305 /**
2306  *  e1000_id_led_init_pchlan - store LED configurations
2307  *  @hw: pointer to the HW structure
2308  *
2309  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2310  *  the PHY LED configuration register.
2311  *
2312  *  PCH also does not have an "always on" or "always off" mode which
2313  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2314  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2315  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2316  *  link based on logic in e1000_led_[on|off]_pchlan().
2317  **/
2318 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2319 {
2320         struct e1000_mac_info *mac = &hw->mac;
2321         s32 ret_val;
2322         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2323         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2324         u16 data, i, temp, shift;
2325
2326         /* Get default ID LED modes */
2327         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2328         if (ret_val)
2329                 goto out;
2330
2331         mac->ledctl_default = er32(LEDCTL);
2332         mac->ledctl_mode1 = mac->ledctl_default;
2333         mac->ledctl_mode2 = mac->ledctl_default;
2334
2335         for (i = 0; i < 4; i++) {
2336                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2337                 shift = (i * 5);
2338                 switch (temp) {
2339                 case ID_LED_ON1_DEF2:
2340                 case ID_LED_ON1_ON2:
2341                 case ID_LED_ON1_OFF2:
2342                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2343                         mac->ledctl_mode1 |= (ledctl_on << shift);
2344                         break;
2345                 case ID_LED_OFF1_DEF2:
2346                 case ID_LED_OFF1_ON2:
2347                 case ID_LED_OFF1_OFF2:
2348                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2349                         mac->ledctl_mode1 |= (ledctl_off << shift);
2350                         break;
2351                 default:
2352                         /* Do nothing */
2353                         break;
2354                 }
2355                 switch (temp) {
2356                 case ID_LED_DEF1_ON2:
2357                 case ID_LED_ON1_ON2:
2358                 case ID_LED_OFF1_ON2:
2359                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2360                         mac->ledctl_mode2 |= (ledctl_on << shift);
2361                         break;
2362                 case ID_LED_DEF1_OFF2:
2363                 case ID_LED_ON1_OFF2:
2364                 case ID_LED_OFF1_OFF2:
2365                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2366                         mac->ledctl_mode2 |= (ledctl_off << shift);
2367                         break;
2368                 default:
2369                         /* Do nothing */
2370                         break;
2371                 }
2372         }
2373
2374 out:
2375         return ret_val;
2376 }
2377
2378 /**
2379  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2380  *  @hw: pointer to the HW structure
2381  *
2382  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2383  *  register, so the the bus width is hard coded.
2384  **/
2385 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2386 {
2387         struct e1000_bus_info *bus = &hw->bus;
2388         s32 ret_val;
2389
2390         ret_val = e1000e_get_bus_info_pcie(hw);
2391
2392         /*
2393          * ICH devices are "PCI Express"-ish.  They have
2394          * a configuration space, but do not contain
2395          * PCI Express Capability registers, so bus width
2396          * must be hardcoded.
2397          */
2398         if (bus->width == e1000_bus_width_unknown)
2399                 bus->width = e1000_bus_width_pcie_x1;
2400
2401         return ret_val;
2402 }
2403
2404 /**
2405  *  e1000_reset_hw_ich8lan - Reset the hardware
2406  *  @hw: pointer to the HW structure
2407  *
2408  *  Does a full reset of the hardware which includes a reset of the PHY and
2409  *  MAC.
2410  **/
2411 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2412 {
2413         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2414         u16 reg;
2415         u32 ctrl, icr, kab;
2416         s32 ret_val;
2417
2418         /*
2419          * Prevent the PCI-E bus from sticking if there is no TLP connection
2420          * on the last TLP read/write transaction when MAC is reset.
2421          */
2422         ret_val = e1000e_disable_pcie_master(hw);
2423         if (ret_val) {
2424                 e_dbg("PCI-E Master disable polling has failed.\n");
2425         }
2426
2427         e_dbg("Masking off all interrupts\n");
2428         ew32(IMC, 0xffffffff);
2429
2430         /*
2431          * Disable the Transmit and Receive units.  Then delay to allow
2432          * any pending transactions to complete before we hit the MAC
2433          * with the global reset.
2434          */
2435         ew32(RCTL, 0);
2436         ew32(TCTL, E1000_TCTL_PSP);
2437         e1e_flush();
2438
2439         msleep(10);
2440
2441         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2442         if (hw->mac.type == e1000_ich8lan) {
2443                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2444                 ew32(PBA, E1000_PBA_8K);
2445                 /* Set Packet Buffer Size to 16k. */
2446                 ew32(PBS, E1000_PBS_16K);
2447         }
2448
2449         if (hw->mac.type == e1000_pchlan) {
2450                 /* Save the NVM K1 bit setting*/
2451                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2452                 if (ret_val)
2453                         return ret_val;
2454
2455                 if (reg & E1000_NVM_K1_ENABLE)
2456                         dev_spec->nvm_k1_enabled = true;
2457                 else
2458                         dev_spec->nvm_k1_enabled = false;
2459         }
2460
2461         ctrl = er32(CTRL);
2462
2463         if (!e1000_check_reset_block(hw)) {
2464                 /* Clear PHY Reset Asserted bit */
2465                 if (hw->mac.type >= e1000_pchlan) {
2466                         u32 status = er32(STATUS);
2467                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2468                 }
2469
2470                 /*
2471                  * PHY HW reset requires MAC CORE reset at the same
2472                  * time to make sure the interface between MAC and the
2473                  * external PHY is reset.
2474                  */
2475                 ctrl |= E1000_CTRL_PHY_RST;
2476         }
2477         ret_val = e1000_acquire_swflag_ich8lan(hw);
2478         e_dbg("Issuing a global reset to ich8lan\n");
2479         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2480         msleep(20);
2481
2482         if (!ret_val)
2483                 e1000_release_swflag_ich8lan(hw);
2484
2485         if (ctrl & E1000_CTRL_PHY_RST)
2486                 ret_val = hw->phy.ops.get_cfg_done(hw);
2487
2488         if (hw->mac.type >= e1000_ich10lan) {
2489                 e1000_lan_init_done_ich8lan(hw);
2490         } else {
2491                 ret_val = e1000e_get_auto_rd_done(hw);
2492                 if (ret_val) {
2493                         /*
2494                          * When auto config read does not complete, do not
2495                          * return with an error. This can happen in situations
2496                          * where there is no eeprom and prevents getting link.
2497                          */
2498                         e_dbg("Auto Read Done did not complete\n");
2499                 }
2500         }
2501         /* Dummy read to clear the phy wakeup bit after lcd reset */
2502         if (hw->mac.type == e1000_pchlan)
2503                 e1e_rphy(hw, BM_WUC, &reg);
2504
2505         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2506         if (ret_val)
2507                 goto out;
2508
2509         if (hw->mac.type == e1000_pchlan) {
2510                 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2511                 if (ret_val)
2512                         goto out;
2513         }
2514         /*
2515          * For PCH, this write will make sure that any noise
2516          * will be detected as a CRC error and be dropped rather than show up
2517          * as a bad packet to the DMA engine.
2518          */
2519         if (hw->mac.type == e1000_pchlan)
2520                 ew32(CRC_OFFSET, 0x65656565);
2521
2522         ew32(IMC, 0xffffffff);
2523         icr = er32(ICR);
2524
2525         kab = er32(KABGTXD);
2526         kab |= E1000_KABGTXD_BGSQLBIAS;
2527         ew32(KABGTXD, kab);
2528
2529         if (hw->mac.type == e1000_pchlan)
2530                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2531
2532 out:
2533         return ret_val;
2534 }
2535
2536 /**
2537  *  e1000_init_hw_ich8lan - Initialize the hardware
2538  *  @hw: pointer to the HW structure
2539  *
2540  *  Prepares the hardware for transmit and receive by doing the following:
2541  *   - initialize hardware bits
2542  *   - initialize LED identification
2543  *   - setup receive address registers
2544  *   - setup flow control
2545  *   - setup transmit descriptors
2546  *   - clear statistics
2547  **/
2548 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2549 {
2550         struct e1000_mac_info *mac = &hw->mac;
2551         u32 ctrl_ext, txdctl, snoop;
2552         s32 ret_val;
2553         u16 i;
2554
2555         e1000_initialize_hw_bits_ich8lan(hw);
2556
2557         /* Initialize identification LED */
2558         ret_val = mac->ops.id_led_init(hw);
2559         if (ret_val)
2560                 e_dbg("Error initializing identification LED\n");
2561                 /* This is not fatal and we should not stop init due to this */
2562
2563         /* Setup the receive address. */
2564         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2565
2566         /* Zero out the Multicast HASH table */
2567         e_dbg("Zeroing the MTA\n");
2568         for (i = 0; i < mac->mta_reg_count; i++)
2569                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2570
2571         /*
2572          * The 82578 Rx buffer will stall if wakeup is enabled in host and
2573          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
2574          * Reset the phy after disabling host wakeup to reset the Rx buffer.
2575          */
2576         if (hw->phy.type == e1000_phy_82578) {
2577                 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2578                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2579                 if (ret_val)
2580                         return ret_val;
2581         }
2582
2583         /* Setup link and flow control */
2584         ret_val = e1000_setup_link_ich8lan(hw);
2585
2586         /* Set the transmit descriptor write-back policy for both queues */
2587         txdctl = er32(TXDCTL(0));
2588         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2589                  E1000_TXDCTL_FULL_TX_DESC_WB;
2590         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2591                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2592         ew32(TXDCTL(0), txdctl);
2593         txdctl = er32(TXDCTL(1));
2594         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2595                  E1000_TXDCTL_FULL_TX_DESC_WB;
2596         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2597                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2598         ew32(TXDCTL(1), txdctl);
2599
2600         /*
2601          * ICH8 has opposite polarity of no_snoop bits.
2602          * By default, we should use snoop behavior.
2603          */
2604         if (mac->type == e1000_ich8lan)
2605                 snoop = PCIE_ICH8_SNOOP_ALL;
2606         else
2607                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2608         e1000e_set_pcie_no_snoop(hw, snoop);
2609
2610         ctrl_ext = er32(CTRL_EXT);
2611         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2612         ew32(CTRL_EXT, ctrl_ext);
2613
2614         /*
2615          * Clear all of the statistics registers (clear on read).  It is
2616          * important that we do this after we have tried to establish link
2617          * because the symbol error count will increment wildly if there
2618          * is no link.
2619          */
2620         e1000_clear_hw_cntrs_ich8lan(hw);
2621
2622         return 0;
2623 }
2624 /**
2625  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2626  *  @hw: pointer to the HW structure
2627  *
2628  *  Sets/Clears required hardware bits necessary for correctly setting up the
2629  *  hardware for transmit and receive.
2630  **/
2631 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2632 {
2633         u32 reg;
2634
2635         /* Extended Device Control */
2636         reg = er32(CTRL_EXT);
2637         reg |= (1 << 22);
2638         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2639         if (hw->mac.type >= e1000_pchlan)
2640                 reg |= E1000_CTRL_EXT_PHYPDEN;
2641         ew32(CTRL_EXT, reg);
2642
2643         /* Transmit Descriptor Control 0 */
2644         reg = er32(TXDCTL(0));
2645         reg |= (1 << 22);
2646         ew32(TXDCTL(0), reg);
2647
2648         /* Transmit Descriptor Control 1 */
2649         reg = er32(TXDCTL(1));
2650         reg |= (1 << 22);
2651         ew32(TXDCTL(1), reg);
2652
2653         /* Transmit Arbitration Control 0 */
2654         reg = er32(TARC(0));
2655         if (hw->mac.type == e1000_ich8lan)
2656                 reg |= (1 << 28) | (1 << 29);
2657         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2658         ew32(TARC(0), reg);
2659
2660         /* Transmit Arbitration Control 1 */
2661         reg = er32(TARC(1));
2662         if (er32(TCTL) & E1000_TCTL_MULR)
2663                 reg &= ~(1 << 28);
2664         else
2665                 reg |= (1 << 28);
2666         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2667         ew32(TARC(1), reg);
2668
2669         /* Device Status */
2670         if (hw->mac.type == e1000_ich8lan) {
2671                 reg = er32(STATUS);
2672                 reg &= ~(1 << 31);
2673                 ew32(STATUS, reg);
2674         }
2675 }
2676
2677 /**
2678  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2679  *  @hw: pointer to the HW structure
2680  *
2681  *  Determines which flow control settings to use, then configures flow
2682  *  control.  Calls the appropriate media-specific link configuration
2683  *  function.  Assuming the adapter has a valid link partner, a valid link
2684  *  should be established.  Assumes the hardware has previously been reset
2685  *  and the transmitter and receiver are not enabled.
2686  **/
2687 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2688 {
2689         s32 ret_val;
2690
2691         if (e1000_check_reset_block(hw))
2692                 return 0;
2693
2694         /*
2695          * ICH parts do not have a word in the NVM to determine
2696          * the default flow control setting, so we explicitly
2697          * set it to full.
2698          */
2699         if (hw->fc.requested_mode == e1000_fc_default) {
2700                 /* Workaround h/w hang when Tx flow control enabled */
2701                 if (hw->mac.type == e1000_pchlan)
2702                         hw->fc.requested_mode = e1000_fc_rx_pause;
2703                 else
2704                         hw->fc.requested_mode = e1000_fc_full;
2705         }
2706
2707         /*
2708          * Save off the requested flow control mode for use later.  Depending
2709          * on the link partner's capabilities, we may or may not use this mode.
2710          */
2711         hw->fc.current_mode = hw->fc.requested_mode;
2712
2713         e_dbg("After fix-ups FlowControl is now = %x\n",
2714                 hw->fc.current_mode);
2715
2716         /* Continue to configure the copper link. */
2717         ret_val = e1000_setup_copper_link_ich8lan(hw);
2718         if (ret_val)
2719                 return ret_val;
2720
2721         ew32(FCTTV, hw->fc.pause_time);
2722         if ((hw->phy.type == e1000_phy_82578) ||
2723             (hw->phy.type == e1000_phy_82577)) {
2724                 ret_val = hw->phy.ops.write_reg(hw,
2725                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
2726                                              hw->fc.pause_time);
2727                 if (ret_val)
2728                         return ret_val;
2729         }
2730
2731         return e1000e_set_fc_watermarks(hw);
2732 }
2733
2734 /**
2735  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2736  *  @hw: pointer to the HW structure
2737  *
2738  *  Configures the kumeran interface to the PHY to wait the appropriate time
2739  *  when polling the PHY, then call the generic setup_copper_link to finish
2740  *  configuring the copper link.
2741  **/
2742 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2743 {
2744         u32 ctrl;
2745         s32 ret_val;
2746         u16 reg_data;
2747
2748         ctrl = er32(CTRL);
2749         ctrl |= E1000_CTRL_SLU;
2750         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2751         ew32(CTRL, ctrl);
2752
2753         /*
2754          * Set the mac to wait the maximum time between each iteration
2755          * and increase the max iterations when polling the phy;
2756          * this fixes erroneous timeouts at 10Mbps.
2757          */
2758         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2759         if (ret_val)
2760                 return ret_val;
2761         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2762         if (ret_val)
2763                 return ret_val;
2764         reg_data |= 0x3F;
2765         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2766         if (ret_val)
2767                 return ret_val;
2768
2769         switch (hw->phy.type) {
2770         case e1000_phy_igp_3:
2771                 ret_val = e1000e_copper_link_setup_igp(hw);
2772                 if (ret_val)
2773                         return ret_val;
2774                 break;
2775         case e1000_phy_bm:
2776         case e1000_phy_82578:
2777                 ret_val = e1000e_copper_link_setup_m88(hw);
2778                 if (ret_val)
2779                         return ret_val;
2780                 break;
2781         case e1000_phy_82577:
2782                 ret_val = e1000_copper_link_setup_82577(hw);
2783                 if (ret_val)
2784                         return ret_val;
2785                 break;
2786         case e1000_phy_ife:
2787                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2788                                                &reg_data);
2789                 if (ret_val)
2790                         return ret_val;
2791
2792                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2793
2794                 switch (hw->phy.mdix) {
2795                 case 1:
2796                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2797                         break;
2798                 case 2:
2799                         reg_data |= IFE_PMC_FORCE_MDIX;
2800                         break;
2801                 case 0:
2802                 default:
2803                         reg_data |= IFE_PMC_AUTO_MDIX;
2804                         break;
2805                 }
2806                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2807                                                 reg_data);
2808                 if (ret_val)
2809                         return ret_val;
2810                 break;
2811         default:
2812                 break;
2813         }
2814         return e1000e_setup_copper_link(hw);
2815 }
2816
2817 /**
2818  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2819  *  @hw: pointer to the HW structure
2820  *  @speed: pointer to store current link speed
2821  *  @duplex: pointer to store the current link duplex
2822  *
2823  *  Calls the generic get_speed_and_duplex to retrieve the current link
2824  *  information and then calls the Kumeran lock loss workaround for links at
2825  *  gigabit speeds.
2826  **/
2827 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2828                                           u16 *duplex)
2829 {
2830         s32 ret_val;
2831
2832         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2833         if (ret_val)
2834                 return ret_val;
2835
2836         if ((hw->mac.type == e1000_ich8lan) &&
2837             (hw->phy.type == e1000_phy_igp_3) &&
2838             (*speed == SPEED_1000)) {
2839                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2840         }
2841
2842         return ret_val;
2843 }
2844
2845 /**
2846  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2847  *  @hw: pointer to the HW structure
2848  *
2849  *  Work-around for 82566 Kumeran PCS lock loss:
2850  *  On link status change (i.e. PCI reset, speed change) and link is up and
2851  *  speed is gigabit-
2852  *    0) if workaround is optionally disabled do nothing
2853  *    1) wait 1ms for Kumeran link to come up
2854  *    2) check Kumeran Diagnostic register PCS lock loss bit
2855  *    3) if not set the link is locked (all is good), otherwise...
2856  *    4) reset the PHY
2857  *    5) repeat up to 10 times
2858  *  Note: this is only called for IGP3 copper when speed is 1gb.
2859  **/
2860 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2861 {
2862         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2863         u32 phy_ctrl;
2864         s32 ret_val;
2865         u16 i, data;
2866         bool link;
2867
2868         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2869                 return 0;
2870
2871         /*
2872          * Make sure link is up before proceeding.  If not just return.
2873          * Attempting this while link is negotiating fouled up link
2874          * stability
2875          */
2876         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2877         if (!link)
2878                 return 0;
2879
2880         for (i = 0; i < 10; i++) {
2881                 /* read once to clear */
2882                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2883                 if (ret_val)
2884                         return ret_val;
2885                 /* and again to get new status */
2886                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2887                 if (ret_val)
2888                         return ret_val;
2889
2890                 /* check for PCS lock */
2891                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2892                         return 0;
2893
2894                 /* Issue PHY reset */
2895                 e1000_phy_hw_reset(hw);
2896                 mdelay(5);
2897         }
2898         /* Disable GigE link negotiation */
2899         phy_ctrl = er32(PHY_CTRL);
2900         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2901                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2902         ew32(PHY_CTRL, phy_ctrl);
2903
2904         /*
2905          * Call gig speed drop workaround on Gig disable before accessing
2906          * any PHY registers
2907          */
2908         e1000e_gig_downshift_workaround_ich8lan(hw);
2909
2910         /* unable to acquire PCS lock */
2911         return -E1000_ERR_PHY;
2912 }
2913
2914 /**
2915  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2916  *  @hw: pointer to the HW structure
2917  *  @state: boolean value used to set the current Kumeran workaround state
2918  *
2919  *  If ICH8, set the current Kumeran workaround state (enabled - true
2920  *  /disabled - false).
2921  **/
2922 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2923                                                  bool state)
2924 {
2925         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2926
2927         if (hw->mac.type != e1000_ich8lan) {
2928                 e_dbg("Workaround applies to ICH8 only.\n");
2929                 return;
2930         }
2931
2932         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2933 }
2934
2935 /**
2936  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2937  *  @hw: pointer to the HW structure
2938  *
2939  *  Workaround for 82566 power-down on D3 entry:
2940  *    1) disable gigabit link
2941  *    2) write VR power-down enable
2942  *    3) read it back
2943  *  Continue if successful, else issue LCD reset and repeat
2944  **/
2945 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2946 {
2947         u32 reg;
2948         u16 data;
2949         u8  retry = 0;
2950
2951         if (hw->phy.type != e1000_phy_igp_3)
2952                 return;
2953
2954         /* Try the workaround twice (if needed) */
2955         do {
2956                 /* Disable link */
2957                 reg = er32(PHY_CTRL);
2958                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2959                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2960                 ew32(PHY_CTRL, reg);
2961
2962                 /*
2963                  * Call gig speed drop workaround on Gig disable before
2964                  * accessing any PHY registers
2965                  */
2966                 if (hw->mac.type == e1000_ich8lan)
2967                         e1000e_gig_downshift_workaround_ich8lan(hw);
2968
2969                 /* Write VR power-down enable */
2970                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2971                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2972                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2973
2974                 /* Read it back and test */
2975                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2976                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2977                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2978                         break;
2979
2980                 /* Issue PHY reset and repeat at most one more time */
2981                 reg = er32(CTRL);
2982                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2983                 retry++;
2984         } while (retry);
2985 }
2986
2987 /**
2988  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2989  *  @hw: pointer to the HW structure
2990  *
2991  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2992  *  LPLU, Gig disable, MDIC PHY reset):
2993  *    1) Set Kumeran Near-end loopback
2994  *    2) Clear Kumeran Near-end loopback
2995  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2996  **/
2997 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2998 {
2999         s32 ret_val;
3000         u16 reg_data;
3001
3002         if ((hw->mac.type != e1000_ich8lan) ||
3003             (hw->phy.type != e1000_phy_igp_3))
3004                 return;
3005
3006         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3007                                       &reg_data);
3008         if (ret_val)
3009                 return;
3010         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3011         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3012                                        reg_data);
3013         if (ret_val)
3014                 return;
3015         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3016         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3017                                        reg_data);
3018 }
3019
3020 /**
3021  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3022  *  @hw: pointer to the HW structure
3023  *
3024  *  During S0 to Sx transition, it is possible the link remains at gig
3025  *  instead of negotiating to a lower speed.  Before going to Sx, set
3026  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3027  *  to a lower speed.
3028  *
3029  *  Should only be called for applicable parts.
3030  **/
3031 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3032 {
3033         u32 phy_ctrl;
3034
3035         switch (hw->mac.type) {
3036         case e1000_ich8lan:
3037         case e1000_ich9lan:
3038         case e1000_ich10lan:
3039         case e1000_pchlan:
3040                 phy_ctrl = er32(PHY_CTRL);
3041                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3042                             E1000_PHY_CTRL_GBE_DISABLE;
3043                 ew32(PHY_CTRL, phy_ctrl);
3044
3045                 if (hw->mac.type == e1000_pchlan)
3046                         e1000_phy_hw_reset_ich8lan(hw);
3047         default:
3048                 break;
3049         }
3050
3051         return;
3052 }
3053
3054 /**
3055  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3056  *  @hw: pointer to the HW structure
3057  *
3058  *  Return the LED back to the default configuration.
3059  **/
3060 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3061 {
3062         if (hw->phy.type == e1000_phy_ife)
3063                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3064
3065         ew32(LEDCTL, hw->mac.ledctl_default);
3066         return 0;
3067 }
3068
3069 /**
3070  *  e1000_led_on_ich8lan - Turn LEDs on
3071  *  @hw: pointer to the HW structure
3072  *
3073  *  Turn on the LEDs.
3074  **/
3075 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3076 {
3077         if (hw->phy.type == e1000_phy_ife)
3078                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3079                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3080
3081         ew32(LEDCTL, hw->mac.ledctl_mode2);
3082         return 0;
3083 }
3084
3085 /**
3086  *  e1000_led_off_ich8lan - Turn LEDs off
3087  *  @hw: pointer to the HW structure
3088  *
3089  *  Turn off the LEDs.
3090  **/
3091 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3092 {
3093         if (hw->phy.type == e1000_phy_ife)
3094                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3095                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3096
3097         ew32(LEDCTL, hw->mac.ledctl_mode1);
3098         return 0;
3099 }
3100
3101 /**
3102  *  e1000_setup_led_pchlan - Configures SW controllable LED
3103  *  @hw: pointer to the HW structure
3104  *
3105  *  This prepares the SW controllable LED for use.
3106  **/
3107 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3108 {
3109         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3110                                         (u16)hw->mac.ledctl_mode1);
3111 }
3112
3113 /**
3114  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3115  *  @hw: pointer to the HW structure
3116  *
3117  *  Return the LED back to the default configuration.
3118  **/
3119 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3120 {
3121         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3122                                         (u16)hw->mac.ledctl_default);
3123 }
3124
3125 /**
3126  *  e1000_led_on_pchlan - Turn LEDs on
3127  *  @hw: pointer to the HW structure
3128  *
3129  *  Turn on the LEDs.
3130  **/
3131 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3132 {
3133         u16 data = (u16)hw->mac.ledctl_mode2;
3134         u32 i, led;
3135
3136         /*
3137          * If no link, then turn LED on by setting the invert bit
3138          * for each LED that's mode is "link_up" in ledctl_mode2.
3139          */
3140         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3141                 for (i = 0; i < 3; i++) {
3142                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3143                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3144                             E1000_LEDCTL_MODE_LINK_UP)
3145                                 continue;
3146                         if (led & E1000_PHY_LED0_IVRT)
3147                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3148                         else
3149                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3150                 }
3151         }
3152
3153         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3154 }
3155
3156 /**
3157  *  e1000_led_off_pchlan - Turn LEDs off
3158  *  @hw: pointer to the HW structure
3159  *
3160  *  Turn off the LEDs.
3161  **/
3162 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3163 {
3164         u16 data = (u16)hw->mac.ledctl_mode1;
3165         u32 i, led;
3166
3167         /*
3168          * If no link, then turn LED off by clearing the invert bit
3169          * for each LED that's mode is "link_up" in ledctl_mode1.
3170          */
3171         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3172                 for (i = 0; i < 3; i++) {
3173                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3174                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3175                             E1000_LEDCTL_MODE_LINK_UP)
3176                                 continue;
3177                         if (led & E1000_PHY_LED0_IVRT)
3178                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3179                         else
3180                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3181                 }
3182         }
3183
3184         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3185 }
3186
3187 /**
3188  *  e1000_get_cfg_done_ich8lan - Read config done bit
3189  *  @hw: pointer to the HW structure
3190  *
3191  *  Read the management control register for the config done bit for
3192  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
3193  *  to read the config done bit, so an error is *ONLY* logged and returns
3194  *  0.  If we were to return with error, EEPROM-less silicon
3195  *  would not be able to be reset or change link.
3196  **/
3197 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3198 {
3199         u32 bank = 0;
3200
3201         if (hw->mac.type >= e1000_pchlan) {
3202                 u32 status = er32(STATUS);
3203
3204                 if (status & E1000_STATUS_PHYRA)
3205                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3206                 else
3207                         e_dbg("PHY Reset Asserted not set - needs delay\n");
3208         }
3209
3210         e1000e_get_cfg_done(hw);
3211
3212         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3213         if ((hw->mac.type != e1000_ich10lan) &&
3214             (hw->mac.type != e1000_pchlan)) {
3215                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3216                     (hw->phy.type == e1000_phy_igp_3)) {
3217                         e1000e_phy_init_script_igp3(hw);
3218                 }
3219         } else {
3220                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3221                         /* Maybe we should do a basic PHY config */
3222                         e_dbg("EEPROM not present\n");
3223                         return -E1000_ERR_CONFIG;
3224                 }
3225         }
3226
3227         return 0;
3228 }
3229
3230 /**
3231  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3232  * @hw: pointer to the HW structure
3233  *
3234  * In the case of a PHY power down to save power, or to turn off link during a
3235  * driver unload, or wake on lan is not enabled, remove the link.
3236  **/
3237 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3238 {
3239         /* If the management interface is not enabled, then power down */
3240         if (!(hw->mac.ops.check_mng_mode(hw) ||
3241               hw->phy.ops.check_reset_block(hw)))
3242                 e1000_power_down_phy_copper(hw);
3243
3244         return;
3245 }
3246
3247 /**
3248  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3249  *  @hw: pointer to the HW structure
3250  *
3251  *  Clears hardware counters specific to the silicon family and calls
3252  *  clear_hw_cntrs_generic to clear all general purpose counters.
3253  **/
3254 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3255 {
3256         u16 phy_data;
3257
3258         e1000e_clear_hw_cntrs_base(hw);
3259
3260         er32(ALGNERRC);
3261         er32(RXERRC);
3262         er32(TNCRS);
3263         er32(CEXTERR);
3264         er32(TSCTC);
3265         er32(TSCTFC);
3266
3267         er32(MGTPRC);
3268         er32(MGTPDC);
3269         er32(MGTPTC);
3270
3271         er32(IAC);
3272         er32(ICRXOC);
3273
3274         /* Clear PHY statistics registers */
3275         if ((hw->phy.type == e1000_phy_82578) ||
3276             (hw->phy.type == e1000_phy_82577)) {
3277                 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3278                 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3279                 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3280                 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3281                 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3282                 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3283                 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3284                 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3285                 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3286                 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3287                 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3288                 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3289                 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3290                 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3291         }
3292 }
3293
3294 static struct e1000_mac_operations ich8_mac_ops = {
3295         .id_led_init            = e1000e_id_led_init,
3296         .check_mng_mode         = e1000_check_mng_mode_ich8lan,
3297         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3298         /* cleanup_led dependent on mac type */
3299         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3300         .get_bus_info           = e1000_get_bus_info_ich8lan,
3301         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3302         /* led_on dependent on mac type */
3303         /* led_off dependent on mac type */
3304         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3305         .reset_hw               = e1000_reset_hw_ich8lan,
3306         .init_hw                = e1000_init_hw_ich8lan,
3307         .setup_link             = e1000_setup_link_ich8lan,
3308         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3309         /* id_led_init dependent on mac type */
3310 };
3311
3312 static struct e1000_phy_operations ich8_phy_ops = {
3313         .acquire                = e1000_acquire_swflag_ich8lan,
3314         .check_reset_block      = e1000_check_reset_block_ich8lan,
3315         .commit                 = NULL,
3316         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3317         .get_cable_length       = e1000e_get_cable_length_igp_2,
3318         .read_reg               = e1000e_read_phy_reg_igp,
3319         .release                = e1000_release_swflag_ich8lan,
3320         .reset                  = e1000_phy_hw_reset_ich8lan,
3321         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3322         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3323         .write_reg              = e1000e_write_phy_reg_igp,
3324 };
3325
3326 static struct e1000_nvm_operations ich8_nvm_ops = {
3327         .acquire                = e1000_acquire_nvm_ich8lan,
3328         .read                   = e1000_read_nvm_ich8lan,
3329         .release                = e1000_release_nvm_ich8lan,
3330         .update                 = e1000_update_nvm_checksum_ich8lan,
3331         .valid_led_default      = e1000_valid_led_default_ich8lan,
3332         .validate               = e1000_validate_nvm_checksum_ich8lan,
3333         .write                  = e1000_write_nvm_ich8lan,
3334 };
3335
3336 struct e1000_info e1000_ich8_info = {
3337         .mac                    = e1000_ich8lan,
3338         .flags                  = FLAG_HAS_WOL
3339                                   | FLAG_IS_ICH
3340                                   | FLAG_RX_CSUM_ENABLED
3341                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3342                                   | FLAG_HAS_AMT
3343                                   | FLAG_HAS_FLASH
3344                                   | FLAG_APME_IN_WUC,
3345         .pba                    = 8,
3346         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3347         .get_variants           = e1000_get_variants_ich8lan,
3348         .mac_ops                = &ich8_mac_ops,
3349         .phy_ops                = &ich8_phy_ops,
3350         .nvm_ops                = &ich8_nvm_ops,
3351 };
3352
3353 struct e1000_info e1000_ich9_info = {
3354         .mac                    = e1000_ich9lan,
3355         .flags                  = FLAG_HAS_JUMBO_FRAMES
3356                                   | FLAG_IS_ICH
3357                                   | FLAG_HAS_WOL
3358                                   | FLAG_RX_CSUM_ENABLED
3359                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3360                                   | FLAG_HAS_AMT
3361                                   | FLAG_HAS_ERT
3362                                   | FLAG_HAS_FLASH
3363                                   | FLAG_APME_IN_WUC,
3364         .pba                    = 10,
3365         .max_hw_frame_size      = DEFAULT_JUMBO,
3366         .get_variants           = e1000_get_variants_ich8lan,
3367         .mac_ops                = &ich8_mac_ops,
3368         .phy_ops                = &ich8_phy_ops,
3369         .nvm_ops                = &ich8_nvm_ops,
3370 };
3371
3372 struct e1000_info e1000_ich10_info = {
3373         .mac                    = e1000_ich10lan,
3374         .flags                  = FLAG_HAS_JUMBO_FRAMES
3375                                   | FLAG_IS_ICH
3376                                   | FLAG_HAS_WOL
3377                                   | FLAG_RX_CSUM_ENABLED
3378                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3379                                   | FLAG_HAS_AMT
3380                                   | FLAG_HAS_ERT
3381                                   | FLAG_HAS_FLASH
3382                                   | FLAG_APME_IN_WUC,
3383         .pba                    = 10,
3384         .max_hw_frame_size      = DEFAULT_JUMBO,
3385         .get_variants           = e1000_get_variants_ich8lan,
3386         .mac_ops                = &ich8_mac_ops,
3387         .phy_ops                = &ich8_phy_ops,
3388         .nvm_ops                = &ich8_nvm_ops,
3389 };
3390
3391 struct e1000_info e1000_pch_info = {
3392         .mac                    = e1000_pchlan,
3393         .flags                  = FLAG_IS_ICH
3394                                   | FLAG_HAS_WOL
3395                                   | FLAG_RX_CSUM_ENABLED
3396                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3397                                   | FLAG_HAS_AMT
3398                                   | FLAG_HAS_FLASH
3399                                   | FLAG_HAS_JUMBO_FRAMES
3400                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3401                                   | FLAG_APME_IN_WUC,
3402         .pba                    = 26,
3403         .max_hw_frame_size      = 4096,
3404         .get_variants           = e1000_get_variants_ich8lan,
3405         .mac_ops                = &ich8_mac_ops,
3406         .phy_ops                = &ich8_phy_ops,
3407         .nvm_ops                = &ich8_nvm_ops,
3408 };