drivers/net/e1000e/es2lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
  31  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  32  */
  33
  34 #include <linux/netdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/delay.h>
  37 #include <linux/pci.h>
  38
  39 #include "e1000.h"
  40
  41 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
  42 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
  43 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
  44
  45 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
  46 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
  47 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
  48
  49 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
  50 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
  51
  52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
  53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
  54
  55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
  56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
  57
  58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
  59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE   0x0002 /* 1=Reversal Disab. */
  60 #define GG82563_PSCR_CROSSOVER_MODE_MASK         0x0060
  61 #define GG82563_PSCR_CROSSOVER_MODE_MDI          0x0000 /* 00=Manual MDI */
  62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX         0x0020 /* 01=Manual MDIX */
  63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO         0x0060 /* 11=Auto crossover */
  64
  65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
  66 #define GG82563_PSCR2_REVERSE_AUTO_NEG           0x2000
  67                                                 /* 1=Reverse Auto-Negotiation */
  68
  69 /* MAC Specific Control Register (Page 2, Register 21) */
  70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
  71 #define GG82563_MSCR_TX_CLK_MASK                 0x0007
  72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5           0x0004
  73 #define GG82563_MSCR_TX_CLK_100MBPS_25           0x0005
  74 #define GG82563_MSCR_TX_CLK_1000MBPS_25          0x0007
  75
  76 #define GG82563_MSCR_ASSERT_CRS_ON_TX            0x0010 /* 1=Assert */
  77
  78 /* DSP Distance Register (Page 5, Register 26) */
  79 #define GG82563_DSPD_CABLE_LENGTH                0x0007 /* 0 = <50M
  80                                                            1 = 50-80M
  81                                                            2 = 80-110M
  82                                                            3 = 110-140M
  83                                                            4 = >140M */
  84
  85 /* Kumeran Mode Control Register (Page 193, Register 16) */
  86 #define GG82563_KMCR_PASS_FALSE_CARRIER          0x0800
  87
  88 /* Power Management Control Register (Page 193, Register 20) */
  89 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE      0x0001
  90                                            /* 1=Enable SERDES Electrical Idle */
  91
  92 /* In-Band Control Register (Page 194, Register 18) */
  93 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
  94
  95 /*
  96  * A table for the GG82563 cable length where the range is defined
  97  * with a lower bound at "index" and the upper bound at
  98  * "index + 5".
  99  */
 100 static const u16 e1000_gg82563_cable_length_table[] =
 101          { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
 102
 103 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
 104 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 105 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 106 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
 107 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
 108 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
 109 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
 110
 111 /**
 112  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
 113  *  @hw: pointer to the HW structure
 114  *
 115  *  This is a function pointer entry point called by the api module.
 116  **/
 117 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
 118 {
 119         struct e1000_phy_info *phy = &hw->phy;
 120         s32 ret_val;
 121
 122         if (hw->phy.media_type != e1000_media_type_copper) {
 123                 phy->type       = e1000_phy_none;
 124                 return 0;
 125         }
 126
 127         phy->addr               = 1;
 128         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 129         phy->reset_delay_us      = 100;
 130         phy->type               = e1000_phy_gg82563;
 131
 132         /* This can only be done after all function pointers are setup. */
 133         ret_val = e1000e_get_phy_id(hw);
 134
 135         /* Verify phy id */
 136         if (phy->id != GG82563_E_PHY_ID)
 137                 return -E1000_ERR_PHY;
 138
 139         return ret_val;
 140 }
 141
 142 /**
 143  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
 144  *  @hw: pointer to the HW structure
 145  *
 146  *  This is a function pointer entry point called by the api module.
 147  **/
 148 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 149 {
 150         struct e1000_nvm_info *nvm = &hw->nvm;
 151         u32 eecd = er32(EECD);
 152         u16 size;
 153
 154         nvm->opcode_bits        = 8;
 155         nvm->delay_usec  = 1;
 156         switch (nvm->override) {
 157         case e1000_nvm_override_spi_large:
 158                 nvm->page_size    = 32;
 159                 nvm->address_bits = 16;
 160                 break;
 161         case e1000_nvm_override_spi_small:
 162                 nvm->page_size    = 8;
 163                 nvm->address_bits = 8;
 164                 break;
 165         default:
 166                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 167                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 168                 break;
 169         }
 170
 171         nvm->type = e1000_nvm_eeprom_spi;
 172
 173         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 174                           E1000_EECD_SIZE_EX_SHIFT);
 175
 176         /*
 177          * Added to a constant, "size" becomes the left-shift value
 178          * for setting word_size.
 179          */
 180         size += NVM_WORD_SIZE_BASE_SHIFT;
 181
 182         /* EEPROM access above 16k is unsupported */
 183         if (size > 14)
 184                 size = 14;
 185         nvm->word_size  = 1 << size;
 186
 187         return 0;
 188 }
 189
 190 /**
 191  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 192  *  @hw: pointer to the HW structure
 193  *
 194  *  This is a function pointer entry point called by the api module.
 195  **/
 196 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
 197 {
 198         struct e1000_hw *hw = &adapter->hw;
 199         struct e1000_mac_info *mac = &hw->mac;
 200         struct e1000_mac_operations *func = &mac->ops;
 201
 202         /* Set media type */
 203         switch (adapter->pdev->device) {
 204         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 205                 hw->phy.media_type = e1000_media_type_internal_serdes;
 206                 break;
 207         default:
 208                 hw->phy.media_type = e1000_media_type_copper;
 209                 break;
 210         }
 211
 212         /* Set mta register count */
 213         mac->mta_reg_count = 128;
 214         /* Set rar entry count */
 215         mac->rar_entry_count = E1000_RAR_ENTRIES;
 216         /* Set if manageability features are enabled. */
 217         mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
 218
 219         /* check for link */
 220         switch (hw->phy.media_type) {
 221         case e1000_media_type_copper:
 222                 func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
 223                 func->check_for_link = e1000e_check_for_copper_link;
 224                 break;
 225         case e1000_media_type_fiber:
 226                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
 227                 func->check_for_link = e1000e_check_for_fiber_link;
 228                 break;
 229         case e1000_media_type_internal_serdes:
 230                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
 231                 func->check_for_link = e1000e_check_for_serdes_link;
 232                 break;
 233         default:
 234                 return -E1000_ERR_CONFIG;
 235                 break;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static s32 e1000_get_invariants_80003es2lan(struct e1000_adapter *adapter)
 242 {
 243         struct e1000_hw *hw = &adapter->hw;
 244         s32 rc;
 245
 246         rc = e1000_init_mac_params_80003es2lan(adapter);
 247         if (rc)
 248                 return rc;
 249
 250         rc = e1000_init_nvm_params_80003es2lan(hw);
 251         if (rc)
 252                 return rc;
 253
 254         rc = e1000_init_phy_params_80003es2lan(hw);
 255         if (rc)
 256                 return rc;
 257
 258         return 0;
 259 }
 260
 261 /**
 262  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 263  *  @hw: pointer to the HW structure
 264  *
 265  *  A wrapper to acquire access rights to the correct PHY.  This is a
 266  *  function pointer entry point called by the api module.
 267  **/
 268 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 269 {
 270         u16 mask;
 271
 272         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 273
 274         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 275 }
 276
 277 /**
 278  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 279  *  @hw: pointer to the HW structure
 280  *
 281  *  A wrapper to release access rights to the correct PHY.  This is a
 282  *  function pointer entry point called by the api module.
 283  **/
 284 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 285 {
 286         u16 mask;
 287
 288         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 289         e1000_release_swfw_sync_80003es2lan(hw, mask);
 290 }
 291
 292 /**
 293  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 294  *  @hw: pointer to the HW structure
 295  *
 296  *  Acquire the semaphore to access the EEPROM.  This is a function
 297  *  pointer entry point called by the api module.
 298  **/
 299 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 300 {
 301         s32 ret_val;
 302
 303         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 304         if (ret_val)
 305                 return ret_val;
 306
 307         ret_val = e1000e_acquire_nvm(hw);
 308
 309         if (ret_val)
 310                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 311
 312         return ret_val;
 313 }
 314
 315 /**
 316  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 317  *  @hw: pointer to the HW structure
 318  *
 319  *  Release the semaphore used to access the EEPROM.  This is a
 320  *  function pointer entry point called by the api module.
 321  **/
 322 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 323 {
 324         e1000e_release_nvm(hw);
 325         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 326 }
 327
 328 /**
 329  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 330  *  @hw: pointer to the HW structure
 331  *  @mask: specifies which semaphore to acquire
 332  *
 333  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 334  *  will also specify which port we're acquiring the lock for.
 335  **/
 336 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 337 {
 338         u32 swfw_sync;
 339         u32 swmask = mask;
 340         u32 fwmask = mask << 16;
 341         s32 i = 0;
 342         s32 timeout = 200;
 343
 344         while (i < timeout) {
 345                 if (e1000e_get_hw_semaphore(hw))
 346                         return -E1000_ERR_SWFW_SYNC;
 347
 348                 swfw_sync = er32(SW_FW_SYNC);
 349                 if (!(swfw_sync & (fwmask | swmask)))
 350                         break;
 351
 352                 /*
 353                  * Firmware currently using resource (fwmask)
 354                  * or other software thread using resource (swmask)
 355                  */
 356                 e1000e_put_hw_semaphore(hw);
 357                 mdelay(5);
 358                 i++;
 359         }
 360
 361         if (i == timeout) {
 362                 hw_dbg(hw,
 363                        "Driver can't access resource, SW_FW_SYNC timeout.\n");
 364                 return -E1000_ERR_SWFW_SYNC;
 365         }
 366
 367         swfw_sync |= swmask;
 368         ew32(SW_FW_SYNC, swfw_sync);
 369
 370         e1000e_put_hw_semaphore(hw);
 371
 372         return 0;
 373 }
 374
 375 /**
 376  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 377  *  @hw: pointer to the HW structure
 378  *  @mask: specifies which semaphore to acquire
 379  *
 380  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 381  *  will also specify which port we're releasing the lock for.
 382  **/
 383 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 384 {
 385         u32 swfw_sync;
 386
 387         while (e1000e_get_hw_semaphore(hw) != 0);
 388         /* Empty */
 389
 390         swfw_sync = er32(SW_FW_SYNC);
 391         swfw_sync &= ~mask;
 392         ew32(SW_FW_SYNC, swfw_sync);
 393
 394         e1000e_put_hw_semaphore(hw);
 395 }
 396
 397 /**
 398  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 399  *  @hw: pointer to the HW structure
 400  *  @offset: offset of the register to read
 401  *  @data: pointer to the data returned from the operation
 402  *
 403  *  Read the GG82563 PHY register.  This is a function pointer entry
 404  *  point called by the api module.
 405  **/
 406 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 407                                                   u32 offset, u16 *data)
 408 {
 409         s32 ret_val;
 410         u32 page_select;
 411         u16 temp;
 412
 413         /* Select Configuration Page */
 414         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
 415                 page_select = GG82563_PHY_PAGE_SELECT;
 416         else
 417                 /*
 418                  * Use Alternative Page Select register to access
 419                  * registers 30 and 31
 420                  */
 421                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 422
 423         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 424         ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp);
 425         if (ret_val)
 426                 return ret_val;
 427
 428         /*
 429          * The "ready" bit in the MDIC register may be incorrectly set
 430          * before the device has completed the "Page Select" MDI
 431          * transaction.  So we wait 200us after each MDI command...
 432          */
 433         udelay(200);
 434
 435         /* ...and verify the command was successful. */
 436         ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp);
 437
 438         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 439                 ret_val = -E1000_ERR_PHY;
 440                 return ret_val;
 441         }
 442
 443         udelay(200);
 444
 445         ret_val = e1000e_read_phy_reg_m88(hw,
 446                                          MAX_PHY_REG_ADDRESS & offset,
 447                                          data);
 448
 449         udelay(200);
 450
 451         return ret_val;
 452 }
 453
 454 /**
 455  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 456  *  @hw: pointer to the HW structure
 457  *  @offset: offset of the register to read
 458  *  @data: value to write to the register
 459  *
 460  *  Write to the GG82563 PHY register.  This is a function pointer entry
 461  *  point called by the api module.
 462  **/
 463 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 464                                                    u32 offset, u16 data)
 465 {
 466         s32 ret_val;
 467         u32 page_select;
 468         u16 temp;
 469
 470         /* Select Configuration Page */
 471         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
 472                 page_select = GG82563_PHY_PAGE_SELECT;
 473         else
 474                 /*
 475                  * Use Alternative Page Select register to access
 476                  * registers 30 and 31
 477                  */
 478                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 479
 480         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 481         ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp);
 482         if (ret_val)
 483                 return ret_val;
 484
 485
 486         /*
 487          * The "ready" bit in the MDIC register may be incorrectly set
 488          * before the device has completed the "Page Select" MDI
 489          * transaction.  So we wait 200us after each MDI command...
 490          */
 491         udelay(200);
 492
 493         /* ...and verify the command was successful. */
 494         ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp);
 495
 496         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp)
 497                 return -E1000_ERR_PHY;
 498
 499         udelay(200);
 500
 501         ret_val = e1000e_write_phy_reg_m88(hw,
 502                                           MAX_PHY_REG_ADDRESS & offset,
 503                                           data);
 504
 505         udelay(200);
 506
 507         return ret_val;
 508 }
 509
 510 /**
 511  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 512  *  @hw: pointer to the HW structure
 513  *  @offset: offset of the register to read
 514  *  @words: number of words to write
 515  *  @data: buffer of data to write to the NVM
 516  *
 517  *  Write "words" of data to the ESB2 NVM.  This is a function
 518  *  pointer entry point called by the api module.
 519  **/
 520 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 521                                        u16 words, u16 *data)
 522 {
 523         return e1000e_write_nvm_spi(hw, offset, words, data);
 524 }
 525
 526 /**
 527  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 528  *  @hw: pointer to the HW structure
 529  *
 530  *  Wait a specific amount of time for manageability processes to complete.
 531  *  This is a function pointer entry point called by the phy module.
 532  **/
 533 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 534 {
 535         s32 timeout = PHY_CFG_TIMEOUT;
 536         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 537
 538         if (hw->bus.func == 1)
 539                 mask = E1000_NVM_CFG_DONE_PORT_1;
 540
 541         while (timeout) {
 542                 if (er32(EEMNGCTL) & mask)
 543                         break;
 544                 msleep(1);
 545                 timeout--;
 546         }
 547         if (!timeout) {
 548                 hw_dbg(hw, "MNG configuration cycle has not completed.\n");
 549                 return -E1000_ERR_RESET;
 550         }
 551
 552         return 0;
 553 }
 554
 555 /**
 556  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 557  *  @hw: pointer to the HW structure
 558  *
 559  *  Force the speed and duplex settings onto the PHY.  This is a
 560  *  function pointer entry point called by the phy module.
 561  **/
 562 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 563 {
 564         s32 ret_val;
 565         u16 phy_data;
 566         bool link;
 567
 568         /*
 569          * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 570          * forced whenever speed and duplex are forced.
 571          */
 572         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 573         if (ret_val)
 574                 return ret_val;
 575
 576         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 577         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 578         if (ret_val)
 579                 return ret_val;
 580
 581         hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data);
 582
 583         ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
 584         if (ret_val)
 585                 return ret_val;
 586
 587         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 588
 589         /* Reset the phy to commit changes. */
 590         phy_data |= MII_CR_RESET;
 591
 592         ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
 593         if (ret_val)
 594                 return ret_val;
 595
 596         udelay(1);
 597
 598         if (hw->phy.autoneg_wait_to_complete) {
 599                 hw_dbg(hw, "Waiting for forced speed/duplex link "
 600                          "on GG82563 phy.\n");
 601
 602                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 603                                                      100000, &link);
 604                 if (ret_val)
 605                         return ret_val;
 606
 607                 if (!link) {
 608                         /*
 609                          * We didn't get link.
 610                          * Reset the DSP and cross our fingers.
 611                          */
 612                         ret_val = e1000e_phy_reset_dsp(hw);
 613                         if (ret_val)
 614                                 return ret_val;
 615                 }
 616
 617                 /* Try once more */
 618                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 619                                                      100000, &link);
 620                 if (ret_val)
 621                         return ret_val;
 622         }
 623
 624         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 625         if (ret_val)
 626                 return ret_val;
 627
 628         /*
 629          * Resetting the phy means we need to verify the TX_CLK corresponds
 630          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 631          */
 632         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 633         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 634                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 635         else
 636                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 637
 638         /*
 639          * In addition, we must re-enable CRS on Tx for both half and full
 640          * duplex.
 641          */
 642         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 643         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 644
 645         return ret_val;
 646 }
 647
 648 /**
 649  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 650  *  @hw: pointer to the HW structure
 651  *
 652  *  Find the approximate cable length as measured by the GG82563 PHY.
 653  *  This is a function pointer entry point called by the phy module.
 654  **/
 655 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 656 {
 657         struct e1000_phy_info *phy = &hw->phy;
 658         s32 ret_val;
 659         u16 phy_data;
 660         u16 index;
 661
 662         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 663         if (ret_val)
 664                 return ret_val;
 665
 666         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 667         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 668         phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
 669
 670         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 671
 672         return 0;
 673 }
 674
 675 /**
 676  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 677  *  @hw: pointer to the HW structure
 678  *  @speed: pointer to speed buffer
 679  *  @duplex: pointer to duplex buffer
 680  *
 681  *  Retrieve the current speed and duplex configuration.
 682  *  This is a function pointer entry point called by the api module.
 683  **/
 684 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 685                                               u16 *duplex)
 686 {
 687         s32 ret_val;
 688
 689         if (hw->phy.media_type == e1000_media_type_copper) {
 690                 ret_val = e1000e_get_speed_and_duplex_copper(hw,
 691                                                                     speed,
 692                                                                     duplex);
 693                 if (ret_val)
 694                         return ret_val;
 695                 if (*speed == SPEED_1000)
 696                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
 697                 else
 698                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw,
 699                                                               *duplex);
 700         } else {
 701                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 702                                                                   speed,
 703                                                                   duplex);
 704         }
 705
 706         return ret_val;
 707 }
 708
 709 /**
 710  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 711  *  @hw: pointer to the HW structure
 712  *
 713  *  Perform a global reset to the ESB2 controller.
 714  *  This is a function pointer entry point called by the api module.
 715  **/
 716 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 717 {
 718         u32 ctrl;
 719         u32 icr;
 720         s32 ret_val;
 721
 722         /*
 723          * Prevent the PCI-E bus from sticking if there is no TLP connection
 724          * on the last TLP read/write transaction when MAC is reset.
 725          */
 726         ret_val = e1000e_disable_pcie_master(hw);
 727         if (ret_val)
 728                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 729
 730         hw_dbg(hw, "Masking off all interrupts\n");
 731         ew32(IMC, 0xffffffff);
 732
 733         ew32(RCTL, 0);
 734         ew32(TCTL, E1000_TCTL_PSP);
 735         e1e_flush();
 736
 737         msleep(10);
 738
 739         ctrl = er32(CTRL);
 740
 741         hw_dbg(hw, "Issuing a global reset to MAC\n");
 742         ew32(CTRL, ctrl | E1000_CTRL_RST);
 743
 744         ret_val = e1000e_get_auto_rd_done(hw);
 745         if (ret_val)
 746                 /* We don't want to continue accessing MAC registers. */
 747                 return ret_val;
 748
 749         /* Clear any pending interrupt events. */
 750         ew32(IMC, 0xffffffff);
 751         icr = er32(ICR);
 752
 753         return 0;
 754 }
 755
 756 /**
 757  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 758  *  @hw: pointer to the HW structure
 759  *
 760  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 761  *  This is a function pointer entry point called by the api module.
 762  **/
 763 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 764 {
 765         struct e1000_mac_info *mac = &hw->mac;
 766         u32 reg_data;
 767         s32 ret_val;
 768         u16 i;
 769
 770         e1000_initialize_hw_bits_80003es2lan(hw);
 771
 772         /* Initialize identification LED */
 773         ret_val = e1000e_id_led_init(hw);
 774         if (ret_val) {
 775                 hw_dbg(hw, "Error initializing identification LED\n");
 776                 return ret_val;
 777         }
 778
 779         /* Disabling VLAN filtering */
 780         hw_dbg(hw, "Initializing the IEEE VLAN\n");
 781         e1000e_clear_vfta(hw);
 782
 783         /* Setup the receive address. */
 784         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 785
 786         /* Zero out the Multicast HASH table */
 787         hw_dbg(hw, "Zeroing the MTA\n");
 788         for (i = 0; i < mac->mta_reg_count; i++)
 789                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 790
 791         /* Setup link and flow control */
 792         ret_val = e1000e_setup_link(hw);
 793
 794         /* Set the transmit descriptor write-back policy */
 795         reg_data = er32(TXDCTL(0));
 796         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 797                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 798         ew32(TXDCTL(0), reg_data);
 799
 800         /* ...for both queues. */
 801         reg_data = er32(TXDCTL(1));
 802         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 803                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 804         ew32(TXDCTL(1), reg_data);
 805
 806         /* Enable retransmit on late collisions */
 807         reg_data = er32(TCTL);
 808         reg_data |= E1000_TCTL_RTLC;
 809         ew32(TCTL, reg_data);
 810
 811         /* Configure Gigabit Carry Extend Padding */
 812         reg_data = er32(TCTL_EXT);
 813         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 814         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 815         ew32(TCTL_EXT, reg_data);
 816
 817         /* Configure Transmit Inter-Packet Gap */
 818         reg_data = er32(TIPG);
 819         reg_data &= ~E1000_TIPG_IPGT_MASK;
 820         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 821         ew32(TIPG, reg_data);
 822
 823         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 824         reg_data &= ~0x00100000;
 825         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 826
 827         /*
 828          * Clear all of the statistics registers (clear on read).  It is
 829          * important that we do this after we have tried to establish link
 830          * because the symbol error count will increment wildly if there
 831          * is no link.
 832          */
 833         e1000_clear_hw_cntrs_80003es2lan(hw);
 834
 835         return ret_val;
 836 }
 837
 838 /**
 839  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 840  *  @hw: pointer to the HW structure
 841  *
 842  *  Initializes required hardware-dependent bits needed for normal operation.
 843  **/
 844 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 845 {
 846         u32 reg;
 847
 848         /* Transmit Descriptor Control 0 */
 849         reg = er32(TXDCTL(0));
 850         reg |= (1 << 22);
 851         ew32(TXDCTL(0), reg);
 852
 853         /* Transmit Descriptor Control 1 */
 854         reg = er32(TXDCTL(1));
 855         reg |= (1 << 22);
 856         ew32(TXDCTL(1), reg);
 857
 858         /* Transmit Arbitration Control 0 */
 859         reg = er32(TARC(0));
 860         reg &= ~(0xF << 27); /* 30:27 */
 861         if (hw->phy.media_type != e1000_media_type_copper)
 862                 reg &= ~(1 << 20);
 863         ew32(TARC(0), reg);
 864
 865         /* Transmit Arbitration Control 1 */
 866         reg = er32(TARC(1));
 867         if (er32(TCTL) & E1000_TCTL_MULR)
 868                 reg &= ~(1 << 28);
 869         else
 870                 reg |= (1 << 28);
 871         ew32(TARC(1), reg);
 872 }
 873
 874 /**
 875  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 876  *  @hw: pointer to the HW structure
 877  *
 878  *  Setup some GG82563 PHY registers for obtaining link
 879  **/
 880 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 881 {
 882         struct e1000_phy_info *phy = &hw->phy;
 883         s32 ret_val;
 884         u32 ctrl_ext;
 885         u16 data;
 886
 887         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
 888                                      &data);
 889         if (ret_val)
 890                 return ret_val;
 891
 892         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 893         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 894         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 895
 896         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
 897                                       data);
 898         if (ret_val)
 899                 return ret_val;
 900
 901         /*
 902          * Options:
 903          *   MDI/MDI-X = 0 (default)
 904          *   0 - Auto for all speeds
 905          *   1 - MDI mode
 906          *   2 - MDI-X mode
 907          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 908          */
 909         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 910         if (ret_val)
 911                 return ret_val;
 912
 913         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 914
 915         switch (phy->mdix) {
 916         case 1:
 917                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 918                 break;
 919         case 2:
 920                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 921                 break;
 922         case 0:
 923         default:
 924                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 925                 break;
 926         }
 927
 928         /*
 929          * Options:
 930          *   disable_polarity_correction = 0 (default)
 931          *       Automatic Correction for Reversed Cable Polarity
 932          *   0 - Disabled
 933          *   1 - Enabled
 934          */
 935         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 936         if (phy->disable_polarity_correction)
 937                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 938
 939         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
 940         if (ret_val)
 941                 return ret_val;
 942
 943         /* SW Reset the PHY so all changes take effect */
 944         ret_val = e1000e_commit_phy(hw);
 945         if (ret_val) {
 946                 hw_dbg(hw, "Error Resetting the PHY\n");
 947                 return ret_val;
 948         }
 949
 950         /* Bypass Rx and Tx FIFO's */
 951         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
 952                                         E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
 953                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
 954         if (ret_val)
 955                 return ret_val;
 956
 957         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
 958         if (ret_val)
 959                 return ret_val;
 960
 961         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
 962         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
 963         if (ret_val)
 964                 return ret_val;
 965
 966         ctrl_ext = er32(CTRL_EXT);
 967         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
 968         ew32(CTRL_EXT, ctrl_ext);
 969
 970         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
 971         if (ret_val)
 972                 return ret_val;
 973
 974         /*
 975          * Do not init these registers when the HW is in IAMT mode, since the
 976          * firmware will have already initialized them.  We only initialize
 977          * them if the HW is not in IAMT mode.
 978          */
 979         if (!e1000e_check_mng_mode(hw)) {
 980                 /* Enable Electrical Idle on the PHY */
 981                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
 982                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
 983                 if (ret_val)
 984                         return ret_val;
 985
 986                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
 987                 if (ret_val)
 988                         return ret_val;
 989
 990                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
 991                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
 992                 if (ret_val)
 993                         return ret_val;
 994         }
 995
 996         /*
 997          * Workaround: Disable padding in Kumeran interface in the MAC
 998          * and in the PHY to avoid CRC errors.
 999          */
1000         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1001         if (ret_val)
1002                 return ret_val;
1003
1004         data |= GG82563_ICR_DIS_PADDING;
1005         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1006         if (ret_val)
1007                 return ret_val;
1008
1009         return 0;
1010 }
1011
1012 /**
1013  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1014  *  @hw: pointer to the HW structure
1015  *
1016  *  Essentially a wrapper for setting up all things "copper" related.
1017  *  This is a function pointer entry point called by the mac module.
1018  **/
1019 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1020 {
1021         u32 ctrl;
1022         s32 ret_val;
1023         u16 reg_data;
1024
1025         ctrl = er32(CTRL);
1026         ctrl |= E1000_CTRL_SLU;
1027         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1028         ew32(CTRL, ctrl);
1029
1030         /*
1031          * Set the mac to wait the maximum time between each
1032          * iteration and increase the max iterations when
1033          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1034          */
1035         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1036         if (ret_val)
1037                 return ret_val;
1038         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1039         if (ret_val)
1040                 return ret_val;
1041         reg_data |= 0x3F;
1042         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1043         if (ret_val)
1044                 return ret_val;
1045         ret_val = e1000e_read_kmrn_reg(hw,
1046                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1047                                       &reg_data);
1048         if (ret_val)
1049                 return ret_val;
1050         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1051         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1052                                         reg_data);
1053         if (ret_val)
1054                 return ret_val;
1055
1056         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1057         if (ret_val)
1058                 return ret_val;
1059
1060         ret_val = e1000e_setup_copper_link(hw);
1061
1062         return 0;
1063 }
1064
1065 /**
1066  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1067  *  @hw: pointer to the HW structure
1068  *  @duplex: current duplex setting
1069  *
1070  *  Configure the KMRN interface by applying last minute quirks for
1071  *  10/100 operation.
1072  **/
1073 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1074 {
1075         s32 ret_val;
1076         u32 tipg;
1077         u16 reg_data;
1078
1079         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1080         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1081                                         reg_data);
1082         if (ret_val)
1083                 return ret_val;
1084
1085         /* Configure Transmit Inter-Packet Gap */
1086         tipg = er32(TIPG);
1087         tipg &= ~E1000_TIPG_IPGT_MASK;
1088         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1089         ew32(TIPG, tipg);
1090
1091         ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1092         if (ret_val)
1093                 return ret_val;
1094
1095         if (duplex == HALF_DUPLEX)
1096                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1097         else
1098                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1099
1100         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1101
1102         return 0;
1103 }
1104
1105 /**
1106  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1107  *  @hw: pointer to the HW structure
1108  *
1109  *  Configure the KMRN interface by applying last minute quirks for
1110  *  gigabit operation.
1111  **/
1112 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1113 {
1114         s32 ret_val;
1115         u16 reg_data;
1116         u32 tipg;
1117
1118         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1119         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1120                                         reg_data);
1121         if (ret_val)
1122                 return ret_val;
1123
1124         /* Configure Transmit Inter-Packet Gap */
1125         tipg = er32(TIPG);
1126         tipg &= ~E1000_TIPG_IPGT_MASK;
1127         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1128         ew32(TIPG, tipg);
1129
1130         ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1131         if (ret_val)
1132                 return ret_val;
1133
1134         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1135         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1136
1137         return ret_val;
1138 }
1139
1140 /**
1141  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1142  *  @hw: pointer to the HW structure
1143  *
1144  *  Clears the hardware counters by reading the counter registers.
1145  **/
1146 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1147 {
1148         u32 temp;
1149
1150         e1000e_clear_hw_cntrs_base(hw);
1151
1152         temp = er32(PRC64);
1153         temp = er32(PRC127);
1154         temp = er32(PRC255);
1155         temp = er32(PRC511);
1156         temp = er32(PRC1023);
1157         temp = er32(PRC1522);
1158         temp = er32(PTC64);
1159         temp = er32(PTC127);
1160         temp = er32(PTC255);
1161         temp = er32(PTC511);
1162         temp = er32(PTC1023);
1163         temp = er32(PTC1522);
1164
1165         temp = er32(ALGNERRC);
1166         temp = er32(RXERRC);
1167         temp = er32(TNCRS);
1168         temp = er32(CEXTERR);
1169         temp = er32(TSCTC);
1170         temp = er32(TSCTFC);
1171
1172         temp = er32(MGTPRC);
1173         temp = er32(MGTPDC);
1174         temp = er32(MGTPTC);
1175
1176         temp = er32(IAC);
1177         temp = er32(ICRXOC);
1178
1179         temp = er32(ICRXPTC);
1180         temp = er32(ICRXATC);
1181         temp = er32(ICTXPTC);
1182         temp = er32(ICTXATC);
1183         temp = er32(ICTXQEC);
1184         temp = er32(ICTXQMTC);
1185         temp = er32(ICRXDMTC);
1186 }
1187
1188 static struct e1000_mac_operations es2_mac_ops = {
1189         .mng_mode_enab          = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT,
1190         /* check_for_link dependent on media type */
1191         .cleanup_led            = e1000e_cleanup_led_generic,
1192         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1193         .get_bus_info           = e1000e_get_bus_info_pcie,
1194         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1195         .led_on                 = e1000e_led_on_generic,
1196         .led_off                = e1000e_led_off_generic,
1197         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1198         .reset_hw               = e1000_reset_hw_80003es2lan,
1199         .init_hw                = e1000_init_hw_80003es2lan,
1200         .setup_link             = e1000e_setup_link,
1201         /* setup_physical_interface dependent on media type */
1202 };
1203
1204 static struct e1000_phy_operations es2_phy_ops = {
1205         .acquire_phy            = e1000_acquire_phy_80003es2lan,
1206         .check_reset_block      = e1000e_check_reset_block_generic,
1207         .commit_phy             = e1000e_phy_sw_reset,
1208         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1209         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1210         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1211         .get_phy_info           = e1000e_get_phy_info_m88,
1212         .read_phy_reg           = e1000_read_phy_reg_gg82563_80003es2lan,
1213         .release_phy            = e1000_release_phy_80003es2lan,
1214         .reset_phy              = e1000e_phy_hw_reset_generic,
1215         .set_d0_lplu_state      = NULL,
1216         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1217         .write_phy_reg          = e1000_write_phy_reg_gg82563_80003es2lan,
1218 };
1219
1220 static struct e1000_nvm_operations es2_nvm_ops = {
1221         .acquire_nvm            = e1000_acquire_nvm_80003es2lan,
1222         .read_nvm               = e1000e_read_nvm_eerd,
1223         .release_nvm            = e1000_release_nvm_80003es2lan,
1224         .update_nvm             = e1000e_update_nvm_checksum_generic,
1225         .valid_led_default      = e1000e_valid_led_default,
1226         .validate_nvm           = e1000e_validate_nvm_checksum_generic,
1227         .write_nvm              = e1000_write_nvm_80003es2lan,
1228 };
1229
1230 struct e1000_info e1000_es2_info = {
1231         .mac                    = e1000_80003es2lan,
1232         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1233                                   | FLAG_HAS_JUMBO_FRAMES
1234                                   | FLAG_HAS_STATS_PTC_PRC
1235                                   | FLAG_HAS_WOL
1236                                   | FLAG_APME_IN_CTRL3
1237                                   | FLAG_RX_CSUM_ENABLED
1238                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1239                                   | FLAG_HAS_STATS_ICR_ICT
1240                                   | FLAG_RX_NEEDS_RESTART /* errata */
1241                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1242                                   | FLAG_APME_CHECK_PORT_B
1243                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1244                                   | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1245         .pba                    = 38,
1246         .get_invariants         = e1000_get_invariants_80003es2lan,
1247         .mac_ops                = &es2_mac_ops,
1248         .phy_ops                = &es2_phy_ops,
1249         .nvm_ops                = &es2_nvm_ops,
1250 };
1251