drivers/mtd/nand/mxc_nand.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA 02110-1301, USA.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/nand.h>
  26 #include <linux/mtd/partitions.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/clk.h>
  31 #include <linux/err.h>
  32 #include <linux/io.h>
  33
  34 #include <asm/mach/flash.h>
  35 #include <mach/mxc_nand.h>
  36
  37 #define DRIVER_NAME "mxc_nand"
  38
  39 /* Addresses for NFC registers */
  40 #define NFC_BUF_SIZE            0xE00
  41 #define NFC_BUF_ADDR            0xE04
  42 #define NFC_FLASH_ADDR          0xE06
  43 #define NFC_FLASH_CMD           0xE08
  44 #define NFC_CONFIG              0xE0A
  45 #define NFC_ECC_STATUS_RESULT   0xE0C
  46 #define NFC_RSLTMAIN_AREA       0xE0E
  47 #define NFC_RSLTSPARE_AREA      0xE10
  48 #define NFC_WRPROT              0xE12
  49 #define NFC_UNLOCKSTART_BLKADDR 0xE14
  50 #define NFC_UNLOCKEND_BLKADDR   0xE16
  51 #define NFC_NF_WRPRST           0xE18
  52 #define NFC_CONFIG1             0xE1A
  53 #define NFC_CONFIG2             0xE1C
  54
  55 /* Addresses for NFC RAM BUFFER Main area 0 */
  56 #define MAIN_AREA0              0x000
  57 #define MAIN_AREA1              0x200
  58 #define MAIN_AREA2              0x400
  59 #define MAIN_AREA3              0x600
  60
  61 /* Addresses for NFC SPARE BUFFER Spare area 0 */
  62 #define SPARE_AREA0             0x800
  63 #define SPARE_AREA1             0x810
  64 #define SPARE_AREA2             0x820
  65 #define SPARE_AREA3             0x830
  66
  67 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
  68  * for Command operation */
  69 #define NFC_CMD            0x1
  70
  71 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
  72  * for Address operation */
  73 #define NFC_ADDR           0x2
  74
  75 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
  76  * for Input operation */
  77 #define NFC_INPUT          0x4
  78
  79 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
  80  * for Data Output operation */
  81 #define NFC_OUTPUT         0x8
  82
  83 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
  84  * for Read ID operation */
  85 #define NFC_ID             0x10
  86
  87 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
  88  * for Read Status operation */
  89 #define NFC_STATUS         0x20
  90
  91 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
  92  * Status operation */
  93 #define NFC_INT            0x8000
  94
  95 #define NFC_SP_EN           (1 << 2)
  96 #define NFC_ECC_EN          (1 << 3)
  97 #define NFC_INT_MSK         (1 << 4)
  98 #define NFC_BIG             (1 << 5)
  99 #define NFC_RST             (1 << 6)
 100 #define NFC_CE              (1 << 7)
 101 #define NFC_ONE_CYCLE       (1 << 8)
 102
 103 struct mxc_nand_host {
 104         struct mtd_info         mtd;
 105         struct nand_chip        nand;
 106         struct mtd_partition    *parts;
 107         struct device           *dev;
 108
 109         void __iomem            *regs;
 110         int                     spare_only;
 111         int                     status_request;
 112         int                     pagesize_2k;
 113         uint16_t                col_addr;
 114         struct clk              *clk;
 115         int                     clk_act;
 116         int                     irq;
 117
 118         wait_queue_head_t       irq_waitq;
 119 };
 120
 121 /* Define delays in microsec for NAND device operations */
 122 #define TROP_US_DELAY   2000
 123 /* Macros to get byte and bit positions of ECC */
 124 #define COLPOS(x)  ((x) >> 3)
 125 #define BITPOS(x) ((x) & 0xf)
 126
 127 /* Define single bit Error positions in Main & Spare area */
 128 #define MAIN_SINGLEBIT_ERROR 0x4
 129 #define SPARE_SINGLEBIT_ERROR 0x1
 130
 131 /* OOB placement block for use with hardware ecc generation */
 132 static struct nand_ecclayout nand_hw_eccoob_8 = {
 133         .eccbytes = 5,
 134         .eccpos = {6, 7, 8, 9, 10},
 135         .oobfree = {{0, 5}, {11, 5}, }
 136 };
 137
 138 static struct nand_ecclayout nand_hw_eccoob_16 = {
 139         .eccbytes = 5,
 140         .eccpos = {6, 7, 8, 9, 10},
 141         .oobfree = {{0, 5}, {11, 5}, }
 142 };
 143
 144 static struct nand_ecclayout nand_hw_eccoob_64 = {
 145         .eccbytes = 20,
 146         .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
 147                    38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
 148         .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
 149 };
 150
 151 #ifdef CONFIG_MTD_PARTITIONS
 152 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
 153 #endif
 154
 155 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 156 {
 157         struct mxc_nand_host *host = dev_id;
 158
 159         uint16_t tmp;
 160
 161         tmp = readw(host->regs + NFC_CONFIG1);
 162         tmp |= NFC_INT_MSK; /* Disable interrupt */
 163         writew(tmp, host->regs + NFC_CONFIG1);
 164
 165         wake_up(&host->irq_waitq);
 166
 167         return IRQ_HANDLED;
 168 }
 169
 170 /* This function polls the NANDFC to wait for the basic operation to
 171  * complete by checking the INT bit of config2 register.
 172  */
 173 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
 174                                 uint16_t param, int useirq)
 175 {
 176         uint32_t tmp;
 177
 178         if (useirq) {
 179                 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
 180
 181                         tmp = readw(host->regs + NFC_CONFIG1);
 182                         tmp  &= ~NFC_INT_MSK;   /* Enable interrupt */
 183                         writew(tmp, host->regs + NFC_CONFIG1);
 184
 185                         wait_event(host->irq_waitq,
 186                                 readw(host->regs + NFC_CONFIG2) & NFC_INT);
 187
 188                         tmp = readw(host->regs + NFC_CONFIG2);
 189                         tmp  &= ~NFC_INT;
 190                         writew(tmp, host->regs + NFC_CONFIG2);
 191                 }
 192         } else {
 193                 while (max_retries-- > 0) {
 194                         if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
 195                                 tmp = readw(host->regs + NFC_CONFIG2);
 196                                 tmp  &= ~NFC_INT;
 197                                 writew(tmp, host->regs + NFC_CONFIG2);
 198                                 break;
 199                         }
 200                         udelay(1);
 201                 }
 202                 if (max_retries < 0)
 203                         DEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
 204                               __func__, param);
 205         }
 206 }
 207
 208 /* This function issues the specified command to the NAND device and
 209  * waits for completion. */
 210 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 211 {
 212         DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
 213
 214         writew(cmd, host->regs + NFC_FLASH_CMD);
 215         writew(NFC_CMD, host->regs + NFC_CONFIG2);
 216
 217         /* Wait for operation to complete */
 218         wait_op_done(host, TROP_US_DELAY, cmd, useirq);
 219 }
 220
 221 /* This function sends an address (or partial address) to the
 222  * NAND device. The address is used to select the source/destination for
 223  * a NAND command. */
 224 static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
 225 {
 226         DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
 227
 228         writew(addr, host->regs + NFC_FLASH_ADDR);
 229         writew(NFC_ADDR, host->regs + NFC_CONFIG2);
 230
 231         /* Wait for operation to complete */
 232         wait_op_done(host, TROP_US_DELAY, addr, islast);
 233 }
 234
 235 /* This function requests the NANDFC to initate the transfer
 236  * of data currently in the NANDFC RAM buffer to the NAND device. */
 237 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
 238                         int spare_only)
 239 {
 240         DEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
 241
 242         /* NANDFC buffer 0 is used for page read/write */
 243         writew(buf_id, host->regs + NFC_BUF_ADDR);
 244
 245         /* Configure spare or page+spare access */
 246         if (!host->pagesize_2k) {
 247                 uint16_t config1 = readw(host->regs + NFC_CONFIG1);
 248                 if (spare_only)
 249                         config1 |= NFC_SP_EN;
 250                 else
 251                         config1 &= ~(NFC_SP_EN);
 252                 writew(config1, host->regs + NFC_CONFIG1);
 253         }
 254
 255         writew(NFC_INPUT, host->regs + NFC_CONFIG2);
 256
 257         /* Wait for operation to complete */
 258         wait_op_done(host, TROP_US_DELAY, spare_only, true);
 259 }
 260
 261 /* Requests NANDFC to initated the transfer of data from the
 262  * NAND device into in the NANDFC ram buffer. */
 263 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
 264                 int spare_only)
 265 {
 266         DEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
 267
 268         /* NANDFC buffer 0 is used for page read/write */
 269         writew(buf_id, host->regs + NFC_BUF_ADDR);
 270
 271         /* Configure spare or page+spare access */
 272         if (!host->pagesize_2k) {
 273                 uint32_t config1 = readw(host->regs + NFC_CONFIG1);
 274                 if (spare_only)
 275                         config1 |= NFC_SP_EN;
 276                 else
 277                         config1 &= ~NFC_SP_EN;
 278                 writew(config1, host->regs + NFC_CONFIG1);
 279         }
 280
 281         writew(NFC_OUTPUT, host->regs + NFC_CONFIG2);
 282
 283         /* Wait for operation to complete */
 284         wait_op_done(host, TROP_US_DELAY, spare_only, true);
 285 }
 286
 287 /* Request the NANDFC to perform a read of the NAND device ID. */
 288 static void send_read_id(struct mxc_nand_host *host)
 289 {
 290         struct nand_chip *this = &host->nand;
 291         uint16_t tmp;
 292
 293         /* NANDFC buffer 0 is used for device ID output */
 294         writew(0x0, host->regs + NFC_BUF_ADDR);
 295
 296         /* Read ID into main buffer */
 297         tmp = readw(host->regs + NFC_CONFIG1);
 298         tmp &= ~NFC_SP_EN;
 299         writew(tmp, host->regs + NFC_CONFIG1);
 300
 301         writew(NFC_ID, host->regs + NFC_CONFIG2);
 302
 303         /* Wait for operation to complete */
 304         wait_op_done(host, TROP_US_DELAY, 0, true);
 305
 306         if (this->options & NAND_BUSWIDTH_16) {
 307                 void __iomem *main_buf = host->regs + MAIN_AREA0;
 308                 /* compress the ID info */
 309                 writeb(readb(main_buf + 2), main_buf + 1);
 310                 writeb(readb(main_buf + 4), main_buf + 2);
 311                 writeb(readb(main_buf + 6), main_buf + 3);
 312                 writeb(readb(main_buf + 8), main_buf + 4);
 313                 writeb(readb(main_buf + 10), main_buf + 5);
 314         }
 315 }
 316
 317 /* This function requests the NANDFC to perform a read of the
 318  * NAND device status and returns the current status. */
 319 static uint16_t get_dev_status(struct mxc_nand_host *host)
 320 {
 321         void __iomem *main_buf = host->regs + MAIN_AREA1;
 322         uint32_t store;
 323         uint16_t ret, tmp;
 324         /* Issue status request to NAND device */
 325
 326         /* store the main area1 first word, later do recovery */
 327         store = readl(main_buf);
 328         /* NANDFC buffer 1 is used for device status to prevent
 329          * corruption of read/write buffer on status requests. */
 330         writew(1, host->regs + NFC_BUF_ADDR);
 331
 332         /* Read status into main buffer */
 333         tmp = readw(host->regs + NFC_CONFIG1);
 334         tmp &= ~NFC_SP_EN;
 335         writew(tmp, host->regs + NFC_CONFIG1);
 336
 337         writew(NFC_STATUS, host->regs + NFC_CONFIG2);
 338
 339         /* Wait for operation to complete */
 340         wait_op_done(host, TROP_US_DELAY, 0, true);
 341
 342         /* Status is placed in first word of main buffer */
 343         /* get status, then recovery area 1 data */
 344         ret = readw(main_buf);
 345         writel(store, main_buf);
 346
 347         return ret;
 348 }
 349
 350 /* This functions is used by upper layer to checks if device is ready */
 351 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 352 {
 353         /*
 354          * NFC handles R/B internally. Therefore, this function
 355          * always returns status as ready.
 356          */
 357         return 1;
 358 }
 359
 360 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 361 {
 362         /*
 363          * If HW ECC is enabled, we turn it on during init. There is
 364          * no need to enable again here.
 365          */
 366 }
 367
 368 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 369                                  u_char *read_ecc, u_char *calc_ecc)
 370 {
 371         struct nand_chip *nand_chip = mtd->priv;
 372         struct mxc_nand_host *host = nand_chip->priv;
 373
 374         /*
 375          * 1-Bit errors are automatically corrected in HW.  No need for
 376          * additional correction.  2-Bit errors cannot be corrected by
 377          * HW ECC, so we need to return failure
 378          */
 379         uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
 380
 381         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 382                 DEBUG(MTD_DEBUG_LEVEL0,
 383                       "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 384                 return -1;
 385         }
 386
 387         return 0;
 388 }
 389
 390 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 391                                   u_char *ecc_code)
 392 {
 393         return 0;
 394 }
 395
 396 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 397 {
 398         struct nand_chip *nand_chip = mtd->priv;
 399         struct mxc_nand_host *host = nand_chip->priv;
 400         uint8_t ret = 0;
 401         uint16_t col, rd_word;
 402         uint16_t __iomem *main_buf = host->regs + MAIN_AREA0;
 403         uint16_t __iomem *spare_buf = host->regs + SPARE_AREA0;
 404
 405         /* Check for status request */
 406         if (host->status_request)
 407                 return get_dev_status(host) & 0xFF;
 408
 409         /* Get column for 16-bit access */
 410         col = host->col_addr >> 1;
 411
 412         /* If we are accessing the spare region */
 413         if (host->spare_only)
 414                 rd_word = readw(&spare_buf[col]);
 415         else
 416                 rd_word = readw(&main_buf[col]);
 417
 418         /* Pick upper/lower byte of word from RAM buffer */
 419         if (host->col_addr & 0x1)
 420                 ret = (rd_word >> 8) & 0xFF;
 421         else
 422                 ret = rd_word & 0xFF;
 423
 424         /* Update saved column address */
 425         host->col_addr++;
 426
 427         return ret;
 428 }
 429
 430 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 431 {
 432         struct nand_chip *nand_chip = mtd->priv;
 433         struct mxc_nand_host *host = nand_chip->priv;
 434         uint16_t col, rd_word, ret;
 435         uint16_t __iomem *p;
 436
 437         DEBUG(MTD_DEBUG_LEVEL3,
 438               "mxc_nand_read_word(col = %d)\n", host->col_addr);
 439
 440         col = host->col_addr;
 441         /* Adjust saved column address */
 442         if (col < mtd->writesize && host->spare_only)
 443                 col += mtd->writesize;
 444
 445         if (col < mtd->writesize)
 446                 p = (host->regs + MAIN_AREA0) + (col >> 1);
 447         else
 448                 p = (host->regs + SPARE_AREA0) + ((col - mtd->writesize) >> 1);
 449
 450         if (col & 1) {
 451                 rd_word = readw(p);
 452                 ret = (rd_word >> 8) & 0xff;
 453                 rd_word = readw(&p[1]);
 454                 ret |= (rd_word << 8) & 0xff00;
 455
 456         } else
 457                 ret = readw(p);
 458
 459         /* Update saved column address */
 460         host->col_addr = col + 2;
 461
 462         return ret;
 463 }
 464
 465 /* Write data of length len to buffer buf. The data to be
 466  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 467  * Operation by the NFC, the data is written to NAND Flash */
 468 static void mxc_nand_write_buf(struct mtd_info *mtd,
 469                                 const u_char *buf, int len)
 470 {
 471         struct nand_chip *nand_chip = mtd->priv;
 472         struct mxc_nand_host *host = nand_chip->priv;
 473         int n, col, i = 0;
 474
 475         DEBUG(MTD_DEBUG_LEVEL3,
 476               "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
 477               len);
 478
 479         col = host->col_addr;
 480
 481         /* Adjust saved column address */
 482         if (col < mtd->writesize && host->spare_only)
 483                 col += mtd->writesize;
 484
 485         n = mtd->writesize + mtd->oobsize - col;
 486         n = min(len, n);
 487
 488         DEBUG(MTD_DEBUG_LEVEL3,
 489               "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
 490
 491         while (n) {
 492                 void __iomem *p;
 493
 494                 if (col < mtd->writesize)
 495                         p = host->regs + MAIN_AREA0 + (col & ~3);
 496                 else
 497                         p = host->regs + SPARE_AREA0 -
 498                                                 mtd->writesize + (col & ~3);
 499
 500                 DEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
 501                       __LINE__, p);
 502
 503                 if (((col | (int)&buf[i]) & 3) || n < 16) {
 504                         uint32_t data = 0;
 505
 506                         if (col & 3 || n < 4)
 507                                 data = readl(p);
 508
 509                         switch (col & 3) {
 510                         case 0:
 511                                 if (n) {
 512                                         data = (data & 0xffffff00) |
 513                                             (buf[i++] << 0);
 514                                         n--;
 515                                         col++;
 516                                 }
 517                         case 1:
 518                                 if (n) {
 519                                         data = (data & 0xffff00ff) |
 520                                             (buf[i++] << 8);
 521                                         n--;
 522                                         col++;
 523                                 }
 524                         case 2:
 525                                 if (n) {
 526                                         data = (data & 0xff00ffff) |
 527                                             (buf[i++] << 16);
 528                                         n--;
 529                                         col++;
 530                                 }
 531                         case 3:
 532                                 if (n) {
 533                                         data = (data & 0x00ffffff) |
 534                                             (buf[i++] << 24);
 535                                         n--;
 536                                         col++;
 537                                 }
 538                         }
 539
 540                         writel(data, p);
 541                 } else {
 542                         int m = mtd->writesize - col;
 543
 544                         if (col >= mtd->writesize)
 545                                 m += mtd->oobsize;
 546
 547                         m = min(n, m) & ~3;
 548
 549                         DEBUG(MTD_DEBUG_LEVEL3,
 550                               "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
 551                               __func__,  __LINE__, n, m, i, col);
 552
 553                         memcpy(p, &buf[i], m);
 554                         col += m;
 555                         i += m;
 556                         n -= m;
 557                 }
 558         }
 559         /* Update saved column address */
 560         host->col_addr = col;
 561 }
 562
 563 /* Read the data buffer from the NAND Flash. To read the data from NAND
 564  * Flash first the data output cycle is initiated by the NFC, which copies
 565  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 566  */
 567 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 568 {
 569         struct nand_chip *nand_chip = mtd->priv;
 570         struct mxc_nand_host *host = nand_chip->priv;
 571         int n, col, i = 0;
 572
 573         DEBUG(MTD_DEBUG_LEVEL3,
 574               "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
 575
 576         col = host->col_addr;
 577
 578         /* Adjust saved column address */
 579         if (col < mtd->writesize && host->spare_only)
 580                 col += mtd->writesize;
 581
 582         n = mtd->writesize + mtd->oobsize - col;
 583         n = min(len, n);
 584
 585         while (n) {
 586                 void __iomem *p;
 587
 588                 if (col < mtd->writesize)
 589                         p = host->regs + MAIN_AREA0 + (col & ~3);
 590                 else
 591                         p = host->regs + SPARE_AREA0 -
 592                                         mtd->writesize + (col & ~3);
 593
 594                 if (((col | (int)&buf[i]) & 3) || n < 16) {
 595                         uint32_t data;
 596
 597                         data = readl(p);
 598                         switch (col & 3) {
 599                         case 0:
 600                                 if (n) {
 601                                         buf[i++] = (uint8_t) (data);
 602                                         n--;
 603                                         col++;
 604                                 }
 605                         case 1:
 606                                 if (n) {
 607                                         buf[i++] = (uint8_t) (data >> 8);
 608                                         n--;
 609                                         col++;
 610                                 }
 611                         case 2:
 612                                 if (n) {
 613                                         buf[i++] = (uint8_t) (data >> 16);
 614                                         n--;
 615                                         col++;
 616                                 }
 617                         case 3:
 618                                 if (n) {
 619                                         buf[i++] = (uint8_t) (data >> 24);
 620                                         n--;
 621                                         col++;
 622                                 }
 623                         }
 624                 } else {
 625                         int m = mtd->writesize - col;
 626
 627                         if (col >= mtd->writesize)
 628                                 m += mtd->oobsize;
 629
 630                         m = min(n, m) & ~3;
 631                         memcpy(&buf[i], p, m);
 632                         col += m;
 633                         i += m;
 634                         n -= m;
 635                 }
 636         }
 637         /* Update saved column address */
 638         host->col_addr = col;
 639
 640 }
 641
 642 /* Used by the upper layer to verify the data in NAND Flash
 643  * with the data in the buf. */
 644 static int mxc_nand_verify_buf(struct mtd_info *mtd,
 645                                 const u_char *buf, int len)
 646 {
 647         return -EFAULT;
 648 }
 649
 650 /* This function is used by upper layer for select and
 651  * deselect of the NAND chip */
 652 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 653 {
 654         struct nand_chip *nand_chip = mtd->priv;
 655         struct mxc_nand_host *host = nand_chip->priv;
 656
 657 #ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
 658         if (chip > 0) {
 659                 DEBUG(MTD_DEBUG_LEVEL0,
 660                       "ERROR:  Illegal chip select (chip = %d)\n", chip);
 661                 return;
 662         }
 663
 664         if (chip == -1) {
 665                 writew(readw(host->regs + NFC_CONFIG1) & ~NFC_CE,
 666                                 host->regs + NFC_CONFIG1);
 667                 return;
 668         }
 669
 670         writew(readw(host->regs + NFC_CONFIG1) | NFC_CE,
 671                         host->regs + NFC_CONFIG1);
 672 #endif
 673
 674         switch (chip) {
 675         case -1:
 676                 /* Disable the NFC clock */
 677                 if (host->clk_act) {
 678                         clk_disable(host->clk);
 679                         host->clk_act = 0;
 680                 }
 681                 break;
 682         case 0:
 683                 /* Enable the NFC clock */
 684                 if (!host->clk_act) {
 685                         clk_enable(host->clk);
 686                         host->clk_act = 1;
 687                 }
 688                 break;
 689
 690         default:
 691                 break;
 692         }
 693 }
 694
 695 /* Used by the upper layer to write command to NAND Flash for
 696  * different operations to be carried out on NAND Flash */
 697 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 698                                 int column, int page_addr)
 699 {
 700         struct nand_chip *nand_chip = mtd->priv;
 701         struct mxc_nand_host *host = nand_chip->priv;
 702         int useirq = true;
 703
 704         DEBUG(MTD_DEBUG_LEVEL3,
 705               "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
 706               command, column, page_addr);
 707
 708         /* Reset command state information */
 709         host->status_request = false;
 710
 711         /* Command pre-processing step */
 712         switch (command) {
 713
 714         case NAND_CMD_STATUS:
 715                 host->col_addr = 0;
 716                 host->status_request = true;
 717                 break;
 718
 719         case NAND_CMD_READ0:
 720                 host->col_addr = column;
 721                 host->spare_only = false;
 722                 useirq = false;
 723                 break;
 724
 725         case NAND_CMD_READOOB:
 726                 host->col_addr = column;
 727                 host->spare_only = true;
 728                 useirq = false;
 729                 if (host->pagesize_2k)
 730                         command = NAND_CMD_READ0; /* only READ0 is valid */
 731                 break;
 732
 733         case NAND_CMD_SEQIN:
 734                 if (column >= mtd->writesize) {
 735                         /*
 736                          * FIXME: before send SEQIN command for write OOB,
 737                          * We must read one page out.
 738                          * For K9F1GXX has no READ1 command to set current HW
 739                          * pointer to spare area, we must write the whole page
 740                          * including OOB together.
 741                          */
 742                         if (host->pagesize_2k)
 743                                 /* call ourself to read a page */
 744                                 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
 745                                                 page_addr);
 746
 747                         host->col_addr = column - mtd->writesize;
 748                         host->spare_only = true;
 749
 750                         /* Set program pointer to spare region */
 751                         if (!host->pagesize_2k)
 752                                 send_cmd(host, NAND_CMD_READOOB, false);
 753                 } else {
 754                         host->spare_only = false;
 755                         host->col_addr = column;
 756
 757                         /* Set program pointer to page start */
 758                         if (!host->pagesize_2k)
 759                                 send_cmd(host, NAND_CMD_READ0, false);
 760                 }
 761                 useirq = false;
 762                 break;
 763
 764         case NAND_CMD_PAGEPROG:
 765                 send_prog_page(host, 0, host->spare_only);
 766
 767                 if (host->pagesize_2k) {
 768                         /* data in 4 areas datas */
 769                         send_prog_page(host, 1, host->spare_only);
 770                         send_prog_page(host, 2, host->spare_only);
 771                         send_prog_page(host, 3, host->spare_only);
 772                 }
 773
 774                 break;
 775
 776         case NAND_CMD_ERASE1:
 777                 useirq = false;
 778                 break;
 779         }
 780
 781         /* Write out the command to the device. */
 782         send_cmd(host, command, useirq);
 783
 784         /* Write out column address, if necessary */
 785         if (column != -1) {
 786                 /*
 787                  * MXC NANDFC can only perform full page+spare or
 788                  * spare-only read/write.  When the upper layers
 789                  * layers perform a read/write buf operation,
 790                  * we will used the saved column adress to index into
 791                  * the full page.
 792                  */
 793                 send_addr(host, 0, page_addr == -1);
 794                 if (host->pagesize_2k)
 795                         /* another col addr cycle for 2k page */
 796                         send_addr(host, 0, false);
 797         }
 798
 799         /* Write out page address, if necessary */
 800         if (page_addr != -1) {
 801                 /* paddr_0 - p_addr_7 */
 802                 send_addr(host, (page_addr & 0xff), false);
 803
 804                 if (host->pagesize_2k) {
 805                         if (mtd->size >= 0x10000000) {
 806                                 /* paddr_8 - paddr_15 */
 807                                 send_addr(host, (page_addr >> 8) & 0xff, false);
 808                                 send_addr(host, (page_addr >> 16) & 0xff, true);
 809                         } else
 810                                 /* paddr_8 - paddr_15 */
 811                                 send_addr(host, (page_addr >> 8) & 0xff, true);
 812                 } else {
 813                         /* One more address cycle for higher density devices */
 814                         if (mtd->size >= 0x4000000) {
 815                                 /* paddr_8 - paddr_15 */
 816                                 send_addr(host, (page_addr >> 8) & 0xff, false);
 817                                 send_addr(host, (page_addr >> 16) & 0xff, true);
 818                         } else
 819                                 /* paddr_8 - paddr_15 */
 820                                 send_addr(host, (page_addr >> 8) & 0xff, true);
 821                 }
 822         }
 823
 824         /* Command post-processing step */
 825         switch (command) {
 826
 827         case NAND_CMD_RESET:
 828                 break;
 829
 830         case NAND_CMD_READOOB:
 831         case NAND_CMD_READ0:
 832                 if (host->pagesize_2k) {
 833                         /* send read confirm command */
 834                         send_cmd(host, NAND_CMD_READSTART, true);
 835                         /* read for each AREA */
 836                         send_read_page(host, 0, host->spare_only);
 837                         send_read_page(host, 1, host->spare_only);
 838                         send_read_page(host, 2, host->spare_only);
 839                         send_read_page(host, 3, host->spare_only);
 840                 } else
 841                         send_read_page(host, 0, host->spare_only);
 842                 break;
 843
 844         case NAND_CMD_READID:
 845                 host->col_addr = 0;
 846                 send_read_id(host);
 847                 break;
 848
 849         case NAND_CMD_PAGEPROG:
 850                 break;
 851
 852         case NAND_CMD_STATUS:
 853                 break;
 854
 855         case NAND_CMD_ERASE2:
 856                 break;
 857         }
 858 }
 859
 860 /* Define some generic bad / good block scan pattern which are used
 861  * while scanning a device for factory marked good / bad blocks. */
 862 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
 863
 864 static struct nand_bbt_descr smallpage_memorybased = {
 865         .options = NAND_BBT_SCAN2NDPAGE,
 866         .offs = 5,
 867         .len = 1,
 868         .pattern = scan_ff_pattern
 869 };
 870
 871 static int __init mxcnd_probe(struct platform_device *pdev)
 872 {
 873         struct nand_chip *this;
 874         struct mtd_info *mtd;
 875         struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
 876         struct mxc_nand_host *host;
 877         struct resource *res;
 878         uint16_t tmp;
 879         int err = 0, nr_parts = 0;
 880
 881         /* Allocate memory for MTD device structure and private data */
 882         host = kzalloc(sizeof(struct mxc_nand_host), GFP_KERNEL);
 883         if (!host)
 884                 return -ENOMEM;
 885
 886         host->dev = &pdev->dev;
 887         /* structures must be linked */
 888         this = &host->nand;
 889         mtd = &host->mtd;
 890         mtd->priv = this;
 891         mtd->owner = THIS_MODULE;
 892         mtd->dev.parent = &pdev->dev;
 893         mtd->name = "mxc_nand";
 894
 895         /* 50 us command delay time */
 896         this->chip_delay = 5;
 897
 898         this->priv = host;
 899         this->dev_ready = mxc_nand_dev_ready;
 900         this->cmdfunc = mxc_nand_command;
 901         this->select_chip = mxc_nand_select_chip;
 902         this->read_byte = mxc_nand_read_byte;
 903         this->read_word = mxc_nand_read_word;
 904         this->write_buf = mxc_nand_write_buf;
 905         this->read_buf = mxc_nand_read_buf;
 906         this->verify_buf = mxc_nand_verify_buf;
 907
 908         host->clk = clk_get(&pdev->dev, "nfc");
 909         if (IS_ERR(host->clk)) {
 910                 err = PTR_ERR(host->clk);
 911                 goto eclk;
 912         }
 913
 914         clk_enable(host->clk);
 915         host->clk_act = 1;
 916
 917         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 918         if (!res) {
 919                 err = -ENODEV;
 920                 goto eres;
 921         }
 922
 923         host->regs = ioremap(res->start, res->end - res->start + 1);
 924         if (!host->regs) {
 925                 err = -ENOMEM;
 926                 goto eres;
 927         }
 928
 929         tmp = readw(host->regs + NFC_CONFIG1);
 930         tmp |= NFC_INT_MSK;
 931         writew(tmp, host->regs + NFC_CONFIG1);
 932
 933         init_waitqueue_head(&host->irq_waitq);
 934
 935         host->irq = platform_get_irq(pdev, 0);
 936
 937         err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host);
 938         if (err)
 939                 goto eirq;
 940
 941         if (pdata->hw_ecc) {
 942                 this->ecc.calculate = mxc_nand_calculate_ecc;
 943                 this->ecc.hwctl = mxc_nand_enable_hwecc;
 944                 this->ecc.correct = mxc_nand_correct_data;
 945                 this->ecc.mode = NAND_ECC_HW;
 946                 this->ecc.size = 512;
 947                 this->ecc.bytes = 3;
 948                 tmp = readw(host->regs + NFC_CONFIG1);
 949                 tmp |= NFC_ECC_EN;
 950                 writew(tmp, host->regs + NFC_CONFIG1);
 951         } else {
 952                 this->ecc.size = 512;
 953                 this->ecc.bytes = 3;
 954                 this->ecc.layout = &nand_hw_eccoob_8;
 955                 this->ecc.mode = NAND_ECC_SOFT;
 956                 tmp = readw(host->regs + NFC_CONFIG1);
 957                 tmp &= ~NFC_ECC_EN;
 958                 writew(tmp, host->regs + NFC_CONFIG1);
 959         }
 960
 961         /* Reset NAND */
 962         this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
 963
 964         /* preset operation */
 965         /* Unlock the internal RAM Buffer */
 966         writew(0x2, host->regs + NFC_CONFIG);
 967
 968         /* Blocks to be unlocked */
 969         writew(0x0, host->regs + NFC_UNLOCKSTART_BLKADDR);
 970         writew(0x4000, host->regs + NFC_UNLOCKEND_BLKADDR);
 971
 972         /* Unlock Block Command for given address range */
 973         writew(0x4, host->regs + NFC_WRPROT);
 974
 975         /* NAND bus width determines access funtions used by upper layer */
 976         if (pdata->width == 2) {
 977                 this->options |= NAND_BUSWIDTH_16;
 978                 this->ecc.layout = &nand_hw_eccoob_16;
 979         }
 980
 981         /* first scan to find the device and get the page size */
 982         if (nand_scan_ident(mtd, 1)) {
 983                 err = -ENXIO;
 984                 goto escan;
 985         }
 986
 987         if (mtd->writesize == 2048) {
 988                 host->pagesize_2k = 1;
 989                 this->badblock_pattern = &smallpage_memorybased;
 990         }
 991
 992         if (this->ecc.mode == NAND_ECC_HW) {
 993                 switch (mtd->oobsize) {
 994                 case 8:
 995                         this->ecc.layout = &nand_hw_eccoob_8;
 996                         break;
 997                 case 16:
 998                         this->ecc.layout = &nand_hw_eccoob_16;
 999                         break;
1000                 case 64:
1001                         this->ecc.layout = &nand_hw_eccoob_64;
1002                         break;
1003                 default:
1004                         /* page size not handled by HW ECC */
1005                         /* switching back to soft ECC */
1006                         this->ecc.size = 512;
1007                         this->ecc.bytes = 3;
1008                         this->ecc.layout = &nand_hw_eccoob_8;
1009                         this->ecc.mode = NAND_ECC_SOFT;
1010                         this->ecc.calculate = NULL;
1011                         this->ecc.correct = NULL;
1012                         this->ecc.hwctl = NULL;
1013                         tmp = readw(host->regs + NFC_CONFIG1);
1014                         tmp &= ~NFC_ECC_EN;
1015                         writew(tmp, host->regs + NFC_CONFIG1);
1016                         break;
1017                 }
1018         }
1019
1020         /* second phase scan */
1021         if (nand_scan_tail(mtd)) {
1022                 err = -ENXIO;
1023                 goto escan;
1024         }
1025
1026         /* Register the partitions */
1027 #ifdef CONFIG_MTD_PARTITIONS
1028         nr_parts =
1029             parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
1030         if (nr_parts > 0)
1031                 add_mtd_partitions(mtd, host->parts, nr_parts);
1032         else
1033 #endif
1034         {
1035                 pr_info("Registering %s as whole device\n", mtd->name);
1036                 add_mtd_device(mtd);
1037         }
1038
1039         platform_set_drvdata(pdev, host);
1040
1041         return 0;
1042
1043 escan:
1044         free_irq(host->irq, host);
1045 eirq:
1046         iounmap(host->regs);
1047 eres:
1048         clk_put(host->clk);
1049 eclk:
1050         kfree(host);
1051
1052         return err;
1053 }
1054
1055 static int __devexit mxcnd_remove(struct platform_device *pdev)
1056 {
1057         struct mxc_nand_host *host = platform_get_drvdata(pdev);
1058
1059         clk_put(host->clk);
1060
1061         platform_set_drvdata(pdev, NULL);
1062
1063         nand_release(&host->mtd);
1064         free_irq(host->irq, host);
1065         iounmap(host->regs);
1066         kfree(host);
1067
1068         return 0;
1069 }
1070
1071 #ifdef CONFIG_PM
1072 static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
1073 {
1074         struct mtd_info *mtd = platform_get_drvdata(pdev);
1075         struct nand_chip *nand_chip = mtd->priv;
1076         struct mxc_nand_host *host = nand_chip->priv;
1077         int ret = 0;
1078
1079         DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
1080         if (mtd) {
1081                 ret = mtd->suspend(mtd);
1082                 /* Disable the NFC clock */
1083                 clk_disable(host->clk);
1084         }
1085
1086         return ret;
1087 }
1088
1089 static int mxcnd_resume(struct platform_device *pdev)
1090 {
1091         struct mtd_info *mtd = platform_get_drvdata(pdev);
1092         struct nand_chip *nand_chip = mtd->priv;
1093         struct mxc_nand_host *host = nand_chip->priv;
1094         int ret = 0;
1095
1096         DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
1097
1098         if (mtd) {
1099                 /* Enable the NFC clock */
1100                 clk_enable(host->clk);
1101                 mtd->resume(mtd);
1102         }
1103
1104         return ret;
1105 }
1106
1107 #else
1108 # define mxcnd_suspend   NULL
1109 # define mxcnd_resume    NULL
1110 #endif                          /* CONFIG_PM */
1111
1112 static struct platform_driver mxcnd_driver = {
1113         .driver = {
1114                    .name = DRIVER_NAME,
1115                    },
1116         .remove = __exit_p(mxcnd_remove),
1117         .suspend = mxcnd_suspend,
1118         .resume = mxcnd_resume,
1119 };
1120
1121 static int __init mxc_nd_init(void)
1122 {
1123         return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
1124 }
1125
1126 static void __exit mxc_nd_cleanup(void)
1127 {
1128         /* Unregister the device structure */
1129         platform_driver_unregister(&mxcnd_driver);
1130 }
1131
1132 module_init(mxc_nd_init);
1133 module_exit(mxc_nd_cleanup);
1134
1135 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1136 MODULE_DESCRIPTION("MXC NAND MTD driver");
1137 MODULE_LICENSE("GPL");