drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/core.h>
  31 #include <linux/io.h>
  32 #include <linux/semaphore.h>
  33 #include <linux/gpio.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <plat/dma.h>
  36 #include <mach/hardware.h>
  37 #include <plat/board.h>
  38 #include <plat/mmc.h>
  39 #include <plat/cpu.h>
  40
  41 /* OMAP HSMMC Host Controller Registers */
  42 #define OMAP_HSMMC_SYSCONFIG    0x0010
  43 #define OMAP_HSMMC_SYSSTATUS    0x0014
  44 #define OMAP_HSMMC_CON          0x002C
  45 #define OMAP_HSMMC_BLK          0x0104
  46 #define OMAP_HSMMC_ARG          0x0108
  47 #define OMAP_HSMMC_CMD          0x010C
  48 #define OMAP_HSMMC_RSP10        0x0110
  49 #define OMAP_HSMMC_RSP32        0x0114
  50 #define OMAP_HSMMC_RSP54        0x0118
  51 #define OMAP_HSMMC_RSP76        0x011C
  52 #define OMAP_HSMMC_DATA         0x0120
  53 #define OMAP_HSMMC_HCTL         0x0128
  54 #define OMAP_HSMMC_SYSCTL       0x012C
  55 #define OMAP_HSMMC_STAT         0x0130
  56 #define OMAP_HSMMC_IE           0x0134
  57 #define OMAP_HSMMC_ISE          0x0138
  58 #define OMAP_HSMMC_CAPA         0x0140
  59
  60 #define VS18                    (1 << 26)
  61 #define VS30                    (1 << 25)
  62 #define SDVS18                  (0x5 << 9)
  63 #define SDVS30                  (0x6 << 9)
  64 #define SDVS33                  (0x7 << 9)
  65 #define SDVS_MASK               0x00000E00
  66 #define SDVSCLR                 0xFFFFF1FF
  67 #define SDVSDET                 0x00000400
  68 #define AUTOIDLE                0x1
  69 #define SDBP                    (1 << 8)
  70 #define DTO                     0xe
  71 #define ICE                     0x1
  72 #define ICS                     0x2
  73 #define CEN                     (1 << 2)
  74 #define CLKD_MASK               0x0000FFC0
  75 #define CLKD_SHIFT              6
  76 #define DTO_MASK                0x000F0000
  77 #define DTO_SHIFT               16
  78 #define INT_EN_MASK             0x307F0033
  79 #define BWR_ENABLE              (1 << 4)
  80 #define BRR_ENABLE              (1 << 5)
  81 #define INIT_STREAM             (1 << 1)
  82 #define DP_SELECT               (1 << 21)
  83 #define DDIR                    (1 << 4)
  84 #define DMA_EN                  0x1
  85 #define MSBS                    (1 << 5)
  86 #define BCE                     (1 << 1)
  87 #define FOUR_BIT                (1 << 1)
  88 #define DW8                     (1 << 5)
  89 #define CC                      0x1
  90 #define TC                      0x02
  91 #define OD                      0x1
  92 #define ERR                     (1 << 15)
  93 #define CMD_TIMEOUT             (1 << 16)
  94 #define DATA_TIMEOUT            (1 << 20)
  95 #define CMD_CRC                 (1 << 17)
  96 #define DATA_CRC                (1 << 21)
  97 #define CARD_ERR                (1 << 28)
  98 #define STAT_CLEAR              0xFFFFFFFF
  99 #define INIT_STREAM_CMD         0x00000000
 100 #define DUAL_VOLT_OCR_BIT       7
 101 #define SRC                     (1 << 25)
 102 #define SRD                     (1 << 26)
 103 #define SOFTRESET               (1 << 1)
 104 #define RESETDONE               (1 << 0)
 105
 106 /*
 107  * FIXME: Most likely all the data using these _DEVID defines should come
 108  * from the platform_data, or implemented in controller and slot specific
 109  * functions.
 110  */
 111 #define OMAP_MMC1_DEVID         0
 112 #define OMAP_MMC2_DEVID         1
 113 #define OMAP_MMC3_DEVID         2
 114 #define OMAP_MMC4_DEVID         3
 115 #define OMAP_MMC5_DEVID         4
 116
 117 #define MMC_TIMEOUT_MS          20
 118 #define OMAP_MMC_MASTER_CLOCK   96000000
 119 #define DRIVER_NAME             "mmci-omap-hs"
 120
 121 /* Timeouts for entering power saving states on inactivity, msec */
 122 #define OMAP_MMC_DISABLED_TIMEOUT       100
 123 #define OMAP_MMC_SLEEP_TIMEOUT          1000
 124 #define OMAP_MMC_OFF_TIMEOUT            8000
 125
 126 /*
 127  * One controller can have multiple slots, like on some omap boards using
 128  * omap.c controller driver. Luckily this is not currently done on any known
 129  * omap_hsmmc.c device.
 130  */
 131 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 132
 133 /*
 134  * MMC Host controller read/write API's
 135  */
 136 #define OMAP_HSMMC_READ(base, reg)      \
 137         __raw_readl((base) + OMAP_HSMMC_##reg)
 138
 139 #define OMAP_HSMMC_WRITE(base, reg, val) \
 140         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 141
 142 struct omap_hsmmc_host {
 143         struct  device          *dev;
 144         struct  mmc_host        *mmc;
 145         struct  mmc_request     *mrq;
 146         struct  mmc_command     *cmd;
 147         struct  mmc_data        *data;
 148         struct  clk             *fclk;
 149         struct  clk             *iclk;
 150         struct  clk             *dbclk;
 151         /*
 152          * vcc == configured supply
 153          * vcc_aux == optional
 154          *   -  MMC1, supply for DAT4..DAT7
 155          *   -  MMC2/MMC2, external level shifter voltage supply, for
 156          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 157          */
 158         struct  regulator       *vcc;
 159         struct  regulator       *vcc_aux;
 160         struct  semaphore       sem;
 161         struct  work_struct     mmc_carddetect_work;
 162         void    __iomem         *base;
 163         resource_size_t         mapbase;
 164         spinlock_t              irq_lock; /* Prevent races with irq handler */
 165         unsigned long           flags;
 166         unsigned int            id;
 167         unsigned int            dma_len;
 168         unsigned int            dma_sg_idx;
 169         unsigned char           bus_mode;
 170         unsigned char           power_mode;
 171         u32                     *buffer;
 172         u32                     bytesleft;
 173         int                     suspended;
 174         int                     irq;
 175         int                     use_dma, dma_ch;
 176         int                     dma_line_tx, dma_line_rx;
 177         int                     slot_id;
 178         int                     got_dbclk;
 179         int                     response_busy;
 180         int                     context_loss;
 181         int                     dpm_state;
 182         int                     vdd;
 183         int                     protect_card;
 184         int                     reqs_blocked;
 185         int                     use_reg;
 186
 187         struct  omap_mmc_platform_data  *pdata;
 188 };
 189
 190 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 191 {
 192         struct omap_mmc_platform_data *mmc = dev->platform_data;
 193
 194         /* NOTE: assumes card detect signal is active-low */
 195         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 196 }
 197
 198 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 199 {
 200         struct omap_mmc_platform_data *mmc = dev->platform_data;
 201
 202         /* NOTE: assumes write protect signal is active-high */
 203         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 204 }
 205
 206 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 207 {
 208         struct omap_mmc_platform_data *mmc = dev->platform_data;
 209
 210         /* NOTE: assumes card detect signal is active-low */
 211         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 212 }
 213
 214 #ifdef CONFIG_PM
 215
 216 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 217 {
 218         struct omap_mmc_platform_data *mmc = dev->platform_data;
 219
 220         disable_irq(mmc->slots[0].card_detect_irq);
 221         return 0;
 222 }
 223
 224 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 225 {
 226         struct omap_mmc_platform_data *mmc = dev->platform_data;
 227
 228         enable_irq(mmc->slots[0].card_detect_irq);
 229         return 0;
 230 }
 231
 232 #else
 233
 234 #define omap_hsmmc_suspend_cdirq        NULL
 235 #define omap_hsmmc_resume_cdirq         NULL
 236
 237 #endif
 238
 239 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
 240                                   int vdd)
 241 {
 242         struct omap_hsmmc_host *host =
 243                 platform_get_drvdata(to_platform_device(dev));
 244         int ret;
 245
 246         if (mmc_slot(host).before_set_reg)
 247                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 248
 249         if (power_on)
 250                 ret = mmc_regulator_set_ocr(host->vcc, vdd);
 251         else
 252                 ret = mmc_regulator_set_ocr(host->vcc, 0);
 253
 254         if (mmc_slot(host).after_set_reg)
 255                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 256
 257         return ret;
 258 }
 259
 260 static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
 261                                    int vdd)
 262 {
 263         struct omap_hsmmc_host *host =
 264                 platform_get_drvdata(to_platform_device(dev));
 265         int ret = 0;
 266
 267         /*
 268          * If we don't see a Vcc regulator, assume it's a fixed
 269          * voltage always-on regulator.
 270          */
 271         if (!host->vcc)
 272                 return 0;
 273
 274         if (mmc_slot(host).before_set_reg)
 275                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 276
 277         /*
 278          * Assume Vcc regulator is used only to power the card ... OMAP
 279          * VDDS is used to power the pins, optionally with a transceiver to
 280          * support cards using voltages other than VDDS (1.8V nominal).  When a
 281          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 282          *
 283          * In some cases this regulator won't support enable/disable;
 284          * e.g. it's a fixed rail for a WLAN chip.
 285          *
 286          * In other cases vcc_aux switches interface power.  Example, for
 287          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 288          * chips/cards need an interface voltage rail too.
 289          */
 290         if (power_on) {
 291                 ret = mmc_regulator_set_ocr(host->vcc, vdd);
 292                 /* Enable interface voltage rail, if needed */
 293                 if (ret == 0 && host->vcc_aux) {
 294                         ret = regulator_enable(host->vcc_aux);
 295                         if (ret < 0)
 296                                 ret = mmc_regulator_set_ocr(host->vcc, 0);
 297                 }
 298         } else {
 299                 if (host->vcc_aux) {
 300                         ret = regulator_is_enabled(host->vcc_aux);
 301                         if (ret > 0)
 302                                 ret = regulator_disable(host->vcc_aux);
 303                 }
 304                 if (ret == 0)
 305                         ret = mmc_regulator_set_ocr(host->vcc, 0);
 306         }
 307
 308         if (mmc_slot(host).after_set_reg)
 309                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 310
 311         return ret;
 312 }
 313
 314 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
 315                                   int vdd, int cardsleep)
 316 {
 317         struct omap_hsmmc_host *host =
 318                 platform_get_drvdata(to_platform_device(dev));
 319         int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
 320
 321         return regulator_set_mode(host->vcc, mode);
 322 }
 323
 324 static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
 325                                    int vdd, int cardsleep)
 326 {
 327         struct omap_hsmmc_host *host =
 328                 platform_get_drvdata(to_platform_device(dev));
 329         int err, mode;
 330
 331         /*
 332          * If we don't see a Vcc regulator, assume it's a fixed
 333          * voltage always-on regulator.
 334          */
 335         if (!host->vcc)
 336                 return 0;
 337
 338         mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
 339
 340         if (!host->vcc_aux)
 341                 return regulator_set_mode(host->vcc, mode);
 342
 343         if (cardsleep) {
 344                 /* VCC can be turned off if card is asleep */
 345                 if (sleep)
 346                         err = mmc_regulator_set_ocr(host->vcc, 0);
 347                 else
 348                         err = mmc_regulator_set_ocr(host->vcc, vdd);
 349         } else
 350                 err = regulator_set_mode(host->vcc, mode);
 351         if (err)
 352                 return err;
 353         return regulator_set_mode(host->vcc_aux, mode);
 354 }
 355
 356 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 357 {
 358         int ret;
 359
 360         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 361                 pdata->suspend = omap_hsmmc_suspend_cdirq;
 362                 pdata->resume = omap_hsmmc_resume_cdirq;
 363                 if (pdata->slots[0].cover)
 364                         pdata->slots[0].get_cover_state =
 365                                         omap_hsmmc_get_cover_state;
 366                 else
 367                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 368                 pdata->slots[0].card_detect_irq =
 369                                 gpio_to_irq(pdata->slots[0].switch_pin);
 370                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 371                 if (ret)
 372                         return ret;
 373                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 374                 if (ret)
 375                         goto err_free_sp;
 376         } else
 377                 pdata->slots[0].switch_pin = -EINVAL;
 378
 379         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 380                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 381                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 382                 if (ret)
 383                         goto err_free_cd;
 384                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 385                 if (ret)
 386                         goto err_free_wp;
 387         } else
 388                 pdata->slots[0].gpio_wp = -EINVAL;
 389
 390         return 0;
 391
 392 err_free_wp:
 393         gpio_free(pdata->slots[0].gpio_wp);
 394 err_free_cd:
 395         if (gpio_is_valid(pdata->slots[0].switch_pin))
 396 err_free_sp:
 397                 gpio_free(pdata->slots[0].switch_pin);
 398         return ret;
 399 }
 400
 401 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 402 {
 403         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 404                 gpio_free(pdata->slots[0].gpio_wp);
 405         if (gpio_is_valid(pdata->slots[0].switch_pin))
 406                 gpio_free(pdata->slots[0].switch_pin);
 407 }
 408
 409 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 410 {
 411         struct regulator *reg;
 412         int ret = 0;
 413
 414         switch (host->id) {
 415         case OMAP_MMC1_DEVID:
 416                 /* On-chip level shifting via PBIAS0/PBIAS1 */
 417                 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
 418                 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
 419                 break;
 420         case OMAP_MMC2_DEVID:
 421         case OMAP_MMC3_DEVID:
 422                 /* Off-chip level shifting, or none */
 423                 mmc_slot(host).set_power = omap_hsmmc_23_set_power;
 424                 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
 425                 break;
 426         default:
 427                 pr_err("MMC%d configuration not supported!\n", host->id);
 428                 return -EINVAL;
 429         }
 430
 431         reg = regulator_get(host->dev, "vmmc");
 432         if (IS_ERR(reg)) {
 433                 dev_dbg(host->dev, "vmmc regulator missing\n");
 434                 /*
 435                 * HACK: until fixed.c regulator is usable,
 436                 * we don't require a main regulator
 437                 * for MMC2 or MMC3
 438                 */
 439                 if (host->id == OMAP_MMC1_DEVID) {
 440                         ret = PTR_ERR(reg);
 441                         goto err;
 442                 }
 443         } else {
 444                 host->vcc = reg;
 445                 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
 446
 447                 /* Allow an aux regulator */
 448                 reg = regulator_get(host->dev, "vmmc_aux");
 449                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 450
 451                 /*
 452                 * UGLY HACK:  workaround regulator framework bugs.
 453                 * When the bootloader leaves a supply active, it's
 454                 * initialized with zero usecount ... and we can't
 455                 * disable it without first enabling it.  Until the
 456                 * framework is fixed, we need a workaround like this
 457                 * (which is safe for MMC, but not in general).
 458                 */
 459                 if (regulator_is_enabled(host->vcc) > 0) {
 460                         regulator_enable(host->vcc);
 461                         regulator_disable(host->vcc);
 462                 }
 463                 if (host->vcc_aux) {
 464                         if (regulator_is_enabled(reg) > 0) {
 465                                 regulator_enable(reg);
 466                                 regulator_disable(reg);
 467                         }
 468                 }
 469         }
 470
 471         return 0;
 472
 473 err:
 474         mmc_slot(host).set_power = NULL;
 475         mmc_slot(host).set_sleep = NULL;
 476         return ret;
 477 }
 478
 479 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 480 {
 481         regulator_put(host->vcc);
 482         regulator_put(host->vcc_aux);
 483         mmc_slot(host).set_power = NULL;
 484         mmc_slot(host).set_sleep = NULL;
 485 }
 486
 487 /*
 488  * Stop clock to the card
 489  */
 490 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 491 {
 492         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 493                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 494         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 495                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 496 }
 497
 498 #ifdef CONFIG_PM
 499
 500 /*
 501  * Restore the MMC host context, if it was lost as result of a
 502  * power state change.
 503  */
 504 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 505 {
 506         struct mmc_ios *ios = &host->mmc->ios;
 507         struct omap_mmc_platform_data *pdata = host->pdata;
 508         int context_loss = 0;
 509         u32 hctl, capa, con;
 510         u16 dsor = 0;
 511         unsigned long timeout;
 512
 513         if (pdata->get_context_loss_count) {
 514                 context_loss = pdata->get_context_loss_count(host->dev);
 515                 if (context_loss < 0)
 516                         return 1;
 517         }
 518
 519         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 520                 context_loss == host->context_loss ? "not " : "");
 521         if (host->context_loss == context_loss)
 522                 return 1;
 523
 524         /* Wait for hardware reset */
 525         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 526         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 527                 && time_before(jiffies, timeout))
 528                 ;
 529
 530         /* Do software reset */
 531         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 532         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 533         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 534                 && time_before(jiffies, timeout))
 535                 ;
 536
 537         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 538                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 539
 540         if (host->id == OMAP_MMC1_DEVID) {
 541                 if (host->power_mode != MMC_POWER_OFF &&
 542                     (1 << ios->vdd) <= MMC_VDD_23_24)
 543                         hctl = SDVS18;
 544                 else
 545                         hctl = SDVS30;
 546                 capa = VS30 | VS18;
 547         } else {
 548                 hctl = SDVS18;
 549                 capa = VS18;
 550         }
 551
 552         OMAP_HSMMC_WRITE(host->base, HCTL,
 553                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 554
 555         OMAP_HSMMC_WRITE(host->base, CAPA,
 556                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 557
 558         OMAP_HSMMC_WRITE(host->base, HCTL,
 559                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 560
 561         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 562         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 563                 && time_before(jiffies, timeout))
 564                 ;
 565
 566         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 567         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 568         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 569
 570         /* Do not initialize card-specific things if the power is off */
 571         if (host->power_mode == MMC_POWER_OFF)
 572                 goto out;
 573
 574         con = OMAP_HSMMC_READ(host->base, CON);
 575         switch (ios->bus_width) {
 576         case MMC_BUS_WIDTH_8:
 577                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 578                 break;
 579         case MMC_BUS_WIDTH_4:
 580                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 581                 OMAP_HSMMC_WRITE(host->base, HCTL,
 582                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 583                 break;
 584         case MMC_BUS_WIDTH_1:
 585                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 586                 OMAP_HSMMC_WRITE(host->base, HCTL,
 587                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 588                 break;
 589         }
 590
 591         if (ios->clock) {
 592                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 593                 if (dsor < 1)
 594                         dsor = 1;
 595
 596                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 597                         dsor++;
 598
 599                 if (dsor > 250)
 600                         dsor = 250;
 601         }
 602
 603         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 604                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 605         OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
 606         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 607                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 608
 609         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 610         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 611                 && time_before(jiffies, timeout))
 612                 ;
 613
 614         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 615                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 616
 617         con = OMAP_HSMMC_READ(host->base, CON);
 618         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 619                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 620         else
 621                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 622 out:
 623         host->context_loss = context_loss;
 624
 625         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 626         return 0;
 627 }
 628
 629 /*
 630  * Save the MMC host context (store the number of power state changes so far).
 631  */
 632 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 633 {
 634         struct omap_mmc_platform_data *pdata = host->pdata;
 635         int context_loss;
 636
 637         if (pdata->get_context_loss_count) {
 638                 context_loss = pdata->get_context_loss_count(host->dev);
 639                 if (context_loss < 0)
 640                         return;
 641                 host->context_loss = context_loss;
 642         }
 643 }
 644
 645 #else
 646
 647 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 648 {
 649         return 0;
 650 }
 651
 652 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 653 {
 654 }
 655
 656 #endif
 657
 658 /*
 659  * Send init stream sequence to card
 660  * before sending IDLE command
 661  */
 662 static void send_init_stream(struct omap_hsmmc_host *host)
 663 {
 664         int reg = 0;
 665         unsigned long timeout;
 666
 667         if (host->protect_card)
 668                 return;
 669
 670         disable_irq(host->irq);
 671         OMAP_HSMMC_WRITE(host->base, CON,
 672                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 673         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 674
 675         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 676         while ((reg != CC) && time_before(jiffies, timeout))
 677                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 678
 679         OMAP_HSMMC_WRITE(host->base, CON,
 680                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 681
 682         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 683         OMAP_HSMMC_READ(host->base, STAT);
 684
 685         enable_irq(host->irq);
 686 }
 687
 688 static inline
 689 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 690 {
 691         int r = 1;
 692
 693         if (mmc_slot(host).get_cover_state)
 694                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 695         return r;
 696 }
 697
 698 static ssize_t
 699 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 700                            char *buf)
 701 {
 702         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 703         struct omap_hsmmc_host *host = mmc_priv(mmc);
 704
 705         return sprintf(buf, "%s\n",
 706                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 707 }
 708
 709 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 710
 711 static ssize_t
 712 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 713                         char *buf)
 714 {
 715         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 716         struct omap_hsmmc_host *host = mmc_priv(mmc);
 717
 718         return sprintf(buf, "%s\n", mmc_slot(host).name);
 719 }
 720
 721 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 722
 723 /*
 724  * Configure the response type and send the cmd.
 725  */
 726 static void
 727 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 728         struct mmc_data *data)
 729 {
 730         int cmdreg = 0, resptype = 0, cmdtype = 0;
 731
 732         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 733                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 734         host->cmd = cmd;
 735
 736         /*
 737          * Clear status bits and enable interrupts
 738          */
 739         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 740         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 741
 742         if (host->use_dma)
 743                 OMAP_HSMMC_WRITE(host->base, IE,
 744                                  INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
 745         else
 746                 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 747
 748         host->response_busy = 0;
 749         if (cmd->flags & MMC_RSP_PRESENT) {
 750                 if (cmd->flags & MMC_RSP_136)
 751                         resptype = 1;
 752                 else if (cmd->flags & MMC_RSP_BUSY) {
 753                         resptype = 3;
 754                         host->response_busy = 1;
 755                 } else
 756                         resptype = 2;
 757         }
 758
 759         /*
 760          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 761          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 762          * a val of 0x3, rest 0x0.
 763          */
 764         if (cmd == host->mrq->stop)
 765                 cmdtype = 0x3;
 766
 767         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 768
 769         if (data) {
 770                 cmdreg |= DP_SELECT | MSBS | BCE;
 771                 if (data->flags & MMC_DATA_READ)
 772                         cmdreg |= DDIR;
 773                 else
 774                         cmdreg &= ~(DDIR);
 775         }
 776
 777         if (host->use_dma)
 778                 cmdreg |= DMA_EN;
 779
 780         /*
 781          * In an interrupt context (i.e. STOP command), the spinlock is unlocked
 782          * by the interrupt handler, otherwise (i.e. for a new request) it is
 783          * unlocked here.
 784          */
 785         if (!in_interrupt())
 786                 spin_unlock_irqrestore(&host->irq_lock, host->flags);
 787
 788         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 789         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 790 }
 791
 792 static int
 793 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 794 {
 795         if (data->flags & MMC_DATA_WRITE)
 796                 return DMA_TO_DEVICE;
 797         else
 798                 return DMA_FROM_DEVICE;
 799 }
 800
 801 /*
 802  * Notify the transfer complete to MMC core
 803  */
 804 static void
 805 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 806 {
 807         if (!data) {
 808                 struct mmc_request *mrq = host->mrq;
 809
 810                 /* TC before CC from CMD6 - don't know why, but it happens */
 811                 if (host->cmd && host->cmd->opcode == 6 &&
 812                     host->response_busy) {
 813                         host->response_busy = 0;
 814                         return;
 815                 }
 816
 817                 host->mrq = NULL;
 818                 mmc_request_done(host->mmc, mrq);
 819                 return;
 820         }
 821
 822         host->data = NULL;
 823
 824         if (host->use_dma && host->dma_ch != -1)
 825                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 826                         omap_hsmmc_get_dma_dir(host, data));
 827
 828         if (!data->error)
 829                 data->bytes_xfered += data->blocks * (data->blksz);
 830         else
 831                 data->bytes_xfered = 0;
 832
 833         if (!data->stop) {
 834                 host->mrq = NULL;
 835                 mmc_request_done(host->mmc, data->mrq);
 836                 return;
 837         }
 838         omap_hsmmc_start_command(host, data->stop, NULL);
 839 }
 840
 841 /*
 842  * Notify the core about command completion
 843  */
 844 static void
 845 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 846 {
 847         host->cmd = NULL;
 848
 849         if (cmd->flags & MMC_RSP_PRESENT) {
 850                 if (cmd->flags & MMC_RSP_136) {
 851                         /* response type 2 */
 852                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 853                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 854                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 855                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 856                 } else {
 857                         /* response types 1, 1b, 3, 4, 5, 6 */
 858                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 859                 }
 860         }
 861         if ((host->data == NULL && !host->response_busy) || cmd->error) {
 862                 host->mrq = NULL;
 863                 mmc_request_done(host->mmc, cmd->mrq);
 864         }
 865 }
 866
 867 /*
 868  * DMA clean up for command errors
 869  */
 870 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 871 {
 872         host->data->error = errno;
 873
 874         if (host->use_dma && host->dma_ch != -1) {
 875                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 876                         omap_hsmmc_get_dma_dir(host, host->data));
 877                 omap_free_dma(host->dma_ch);
 878                 host->dma_ch = -1;
 879                 up(&host->sem);
 880         }
 881         host->data = NULL;
 882 }
 883
 884 /*
 885  * Readable error output
 886  */
 887 #ifdef CONFIG_MMC_DEBUG
 888 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
 889 {
 890         /* --- means reserved bit without definition at documentation */
 891         static const char *omap_hsmmc_status_bits[] = {
 892                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 893                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 894                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 895                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 896         };
 897         char res[256];
 898         char *buf = res;
 899         int len, i;
 900
 901         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 902         buf += len;
 903
 904         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 905                 if (status & (1 << i)) {
 906                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 907                         buf += len;
 908                 }
 909
 910         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 911 }
 912 #endif  /* CONFIG_MMC_DEBUG */
 913
 914 /*
 915  * MMC controller internal state machines reset
 916  *
 917  * Used to reset command or data internal state machines, using respectively
 918  *  SRC or SRD bit of SYSCTL register
 919  * Can be called from interrupt context
 920  */
 921 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 922                                                    unsigned long bit)
 923 {
 924         unsigned long i = 0;
 925         unsigned long limit = (loops_per_jiffy *
 926                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 927
 928         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 929                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 930
 931         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 932                 (i++ < limit))
 933                 cpu_relax();
 934
 935         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 936                 dev_err(mmc_dev(host->mmc),
 937                         "Timeout waiting on controller reset in %s\n",
 938                         __func__);
 939 }
 940
 941 /*
 942  * MMC controller IRQ handler
 943  */
 944 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
 945 {
 946         struct omap_hsmmc_host *host = dev_id;
 947         struct mmc_data *data;
 948         int end_cmd = 0, end_trans = 0, status;
 949
 950         spin_lock(&host->irq_lock);
 951
 952         if (host->mrq == NULL) {
 953                 OMAP_HSMMC_WRITE(host->base, STAT,
 954                         OMAP_HSMMC_READ(host->base, STAT));
 955                 /* Flush posted write */
 956                 OMAP_HSMMC_READ(host->base, STAT);
 957                 spin_unlock(&host->irq_lock);
 958                 return IRQ_HANDLED;
 959         }
 960
 961         data = host->data;
 962         status = OMAP_HSMMC_READ(host->base, STAT);
 963         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 964
 965         if (status & ERR) {
 966 #ifdef CONFIG_MMC_DEBUG
 967                 omap_hsmmc_report_irq(host, status);
 968 #endif
 969                 if ((status & CMD_TIMEOUT) ||
 970                         (status & CMD_CRC)) {
 971                         if (host->cmd) {
 972                                 if (status & CMD_TIMEOUT) {
 973                                         omap_hsmmc_reset_controller_fsm(host,
 974                                                                         SRC);
 975                                         host->cmd->error = -ETIMEDOUT;
 976                                 } else {
 977                                         host->cmd->error = -EILSEQ;
 978                                 }
 979                                 end_cmd = 1;
 980                         }
 981                         if (host->data || host->response_busy) {
 982                                 if (host->data)
 983                                         omap_hsmmc_dma_cleanup(host,
 984                                                                 -ETIMEDOUT);
 985                                 host->response_busy = 0;
 986                                 omap_hsmmc_reset_controller_fsm(host, SRD);
 987                         }
 988                 }
 989                 if ((status & DATA_TIMEOUT) ||
 990                         (status & DATA_CRC)) {
 991                         if (host->data || host->response_busy) {
 992                                 int err = (status & DATA_TIMEOUT) ?
 993                                                 -ETIMEDOUT : -EILSEQ;
 994
 995                                 if (host->data)
 996                                         omap_hsmmc_dma_cleanup(host, err);
 997                                 else
 998                                         host->mrq->cmd->error = err;
 999                                 host->response_busy = 0;
1000                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1001                                 end_trans = 1;
1002                         }
1003                 }
1004                 if (status & CARD_ERR) {
1005                         dev_dbg(mmc_dev(host->mmc),
1006                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1007                         if (host->cmd)
1008                                 end_cmd = 1;
1009                         if (host->data)
1010                                 end_trans = 1;
1011                 }
1012         }
1013
1014         OMAP_HSMMC_WRITE(host->base, STAT, status);
1015         /* Flush posted write */
1016         OMAP_HSMMC_READ(host->base, STAT);
1017
1018         if (end_cmd || ((status & CC) && host->cmd))
1019                 omap_hsmmc_cmd_done(host, host->cmd);
1020         if ((end_trans || (status & TC)) && host->mrq)
1021                 omap_hsmmc_xfer_done(host, data);
1022
1023         spin_unlock(&host->irq_lock);
1024
1025         return IRQ_HANDLED;
1026 }
1027
1028 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1029 {
1030         unsigned long i;
1031
1032         OMAP_HSMMC_WRITE(host->base, HCTL,
1033                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1034         for (i = 0; i < loops_per_jiffy; i++) {
1035                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1036                         break;
1037                 cpu_relax();
1038         }
1039 }
1040
1041 /*
1042  * Switch MMC interface voltage ... only relevant for MMC1.
1043  *
1044  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1045  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1046  * Some chips, like eMMC ones, use internal transceivers.
1047  */
1048 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1049 {
1050         u32 reg_val = 0;
1051         int ret;
1052
1053         /* Disable the clocks */
1054         clk_disable(host->fclk);
1055         clk_disable(host->iclk);
1056         if (host->got_dbclk)
1057                 clk_disable(host->dbclk);
1058
1059         /* Turn the power off */
1060         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1061
1062         /* Turn the power ON with given VDD 1.8 or 3.0v */
1063         if (!ret)
1064                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1065                                                vdd);
1066         clk_enable(host->iclk);
1067         clk_enable(host->fclk);
1068         if (host->got_dbclk)
1069                 clk_enable(host->dbclk);
1070
1071         if (ret != 0)
1072                 goto err;
1073
1074         OMAP_HSMMC_WRITE(host->base, HCTL,
1075                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1076         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1077
1078         /*
1079          * If a MMC dual voltage card is detected, the set_ios fn calls
1080          * this fn with VDD bit set for 1.8V. Upon card removal from the
1081          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1082          *
1083          * Cope with a bit of slop in the range ... per data sheets:
1084          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1085          *    but recommended values are 1.71V to 1.89V
1086          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1087          *    but recommended values are 2.7V to 3.3V
1088          *
1089          * Board setup code shouldn't permit anything very out-of-range.
1090          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1091          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1092          */
1093         if ((1 << vdd) <= MMC_VDD_23_24)
1094                 reg_val |= SDVS18;
1095         else
1096                 reg_val |= SDVS30;
1097
1098         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1099         set_sd_bus_power(host);
1100
1101         return 0;
1102 err:
1103         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1104         return ret;
1105 }
1106
1107 /* Protect the card while the cover is open */
1108 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1109 {
1110         if (!mmc_slot(host).get_cover_state)
1111                 return;
1112
1113         host->reqs_blocked = 0;
1114         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1115                 if (host->protect_card) {
1116                         printk(KERN_INFO "%s: cover is closed, "
1117                                          "card is now accessible\n",
1118                                          mmc_hostname(host->mmc));
1119                         host->protect_card = 0;
1120                 }
1121         } else {
1122                 if (!host->protect_card) {
1123                         printk(KERN_INFO "%s: cover is open, "
1124                                          "card is now inaccessible\n",
1125                                          mmc_hostname(host->mmc));
1126                         host->protect_card = 1;
1127                 }
1128         }
1129 }
1130
1131 /*
1132  * Work Item to notify the core about card insertion/removal
1133  */
1134 static void omap_hsmmc_detect(struct work_struct *work)
1135 {
1136         struct omap_hsmmc_host *host =
1137                 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1138         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1139         int carddetect;
1140
1141         if (host->suspended)
1142                 return;
1143
1144         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1145
1146         if (slot->card_detect)
1147                 carddetect = slot->card_detect(host->dev, host->slot_id);
1148         else {
1149                 omap_hsmmc_protect_card(host);
1150                 carddetect = -ENOSYS;
1151         }
1152
1153         if (carddetect) {
1154                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1155         } else {
1156                 mmc_host_enable(host->mmc);
1157                 omap_hsmmc_reset_controller_fsm(host, SRD);
1158                 mmc_host_lazy_disable(host->mmc);
1159
1160                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1161         }
1162 }
1163
1164 /*
1165  * ISR for handling card insertion and removal
1166  */
1167 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1168 {
1169         struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1170
1171         if (host->suspended)
1172                 return IRQ_HANDLED;
1173         schedule_work(&host->mmc_carddetect_work);
1174
1175         return IRQ_HANDLED;
1176 }
1177
1178 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1179                                      struct mmc_data *data)
1180 {
1181         int sync_dev;
1182
1183         if (data->flags & MMC_DATA_WRITE)
1184                 sync_dev = host->dma_line_tx;
1185         else
1186                 sync_dev = host->dma_line_rx;
1187         return sync_dev;
1188 }
1189
1190 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1191                                        struct mmc_data *data,
1192                                        struct scatterlist *sgl)
1193 {
1194         int blksz, nblk, dma_ch;
1195
1196         dma_ch = host->dma_ch;
1197         if (data->flags & MMC_DATA_WRITE) {
1198                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1199                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1200                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1201                         sg_dma_address(sgl), 0, 0);
1202         } else {
1203                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1204                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1205                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1206                         sg_dma_address(sgl), 0, 0);
1207         }
1208
1209         blksz = host->data->blksz;
1210         nblk = sg_dma_len(sgl) / blksz;
1211
1212         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1213                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1214                         omap_hsmmc_get_dma_sync_dev(host, data),
1215                         !(data->flags & MMC_DATA_WRITE));
1216
1217         omap_start_dma(dma_ch);
1218 }
1219
1220 /*
1221  * DMA call back function
1222  */
1223 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data)
1224 {
1225         struct omap_hsmmc_host *host = data;
1226
1227         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
1228                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
1229
1230         if (host->dma_ch < 0)
1231                 return;
1232
1233         host->dma_sg_idx++;
1234         if (host->dma_sg_idx < host->dma_len) {
1235                 /* Fire up the next transfer. */
1236                 omap_hsmmc_config_dma_params(host, host->data,
1237                                            host->data->sg + host->dma_sg_idx);
1238                 return;
1239         }
1240
1241         omap_free_dma(host->dma_ch);
1242         host->dma_ch = -1;
1243         /*
1244          * DMA Callback: run in interrupt context.
1245          * mutex_unlock will throw a kernel warning if used.
1246          */
1247         up(&host->sem);
1248 }
1249
1250 /*
1251  * Routine to configure and start DMA for the MMC card
1252  */
1253 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1254                                         struct mmc_request *req)
1255 {
1256         int dma_ch = 0, ret = 0, err = 1, i;
1257         struct mmc_data *data = req->data;
1258
1259         /* Sanity check: all the SG entries must be aligned by block size. */
1260         for (i = 0; i < data->sg_len; i++) {
1261                 struct scatterlist *sgl;
1262
1263                 sgl = data->sg + i;
1264                 if (sgl->length % data->blksz)
1265                         return -EINVAL;
1266         }
1267         if ((data->blksz % 4) != 0)
1268                 /* REVISIT: The MMC buffer increments only when MSB is written.
1269                  * Return error for blksz which is non multiple of four.
1270                  */
1271                 return -EINVAL;
1272
1273         /*
1274          * If for some reason the DMA transfer is still active,
1275          * we wait for timeout period and free the dma
1276          */
1277         if (host->dma_ch != -1) {
1278                 set_current_state(TASK_UNINTERRUPTIBLE);
1279                 schedule_timeout(100);
1280                 if (down_trylock(&host->sem)) {
1281                         omap_free_dma(host->dma_ch);
1282                         host->dma_ch = -1;
1283                         up(&host->sem);
1284                         return err;
1285                 }
1286         } else {
1287                 if (down_trylock(&host->sem))
1288                         return err;
1289         }
1290
1291         ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1292                                "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1293         if (ret != 0) {
1294                 dev_err(mmc_dev(host->mmc),
1295                         "%s: omap_request_dma() failed with %d\n",
1296                         mmc_hostname(host->mmc), ret);
1297                 return ret;
1298         }
1299
1300         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1301                         data->sg_len, omap_hsmmc_get_dma_dir(host, data));
1302         host->dma_ch = dma_ch;
1303         host->dma_sg_idx = 0;
1304
1305         omap_hsmmc_config_dma_params(host, data, data->sg);
1306
1307         return 0;
1308 }
1309
1310 static void set_data_timeout(struct omap_hsmmc_host *host,
1311                              unsigned int timeout_ns,
1312                              unsigned int timeout_clks)
1313 {
1314         unsigned int timeout, cycle_ns;
1315         uint32_t reg, clkd, dto = 0;
1316
1317         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1318         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1319         if (clkd == 0)
1320                 clkd = 1;
1321
1322         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1323         timeout = timeout_ns / cycle_ns;
1324         timeout += timeout_clks;
1325         if (timeout) {
1326                 while ((timeout & 0x80000000) == 0) {
1327                         dto += 1;
1328                         timeout <<= 1;
1329                 }
1330                 dto = 31 - dto;
1331                 timeout <<= 1;
1332                 if (timeout && dto)
1333                         dto += 1;
1334                 if (dto >= 13)
1335                         dto -= 13;
1336                 else
1337                         dto = 0;
1338                 if (dto > 14)
1339                         dto = 14;
1340         }
1341
1342         reg &= ~DTO_MASK;
1343         reg |= dto << DTO_SHIFT;
1344         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1345 }
1346
1347 /*
1348  * Configure block length for MMC/SD cards and initiate the transfer.
1349  */
1350 static int
1351 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1352 {
1353         int ret;
1354         host->data = req->data;
1355
1356         if (req->data == NULL) {
1357                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1358                 /*
1359                  * Set an arbitrary 100ms data timeout for commands with
1360                  * busy signal.
1361                  */
1362                 if (req->cmd->flags & MMC_RSP_BUSY)
1363                         set_data_timeout(host, 100000000U, 0);
1364                 return 0;
1365         }
1366
1367         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1368                                         | (req->data->blocks << 16));
1369         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1370
1371         if (host->use_dma) {
1372                 ret = omap_hsmmc_start_dma_transfer(host, req);
1373                 if (ret != 0) {
1374                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1375                         return ret;
1376                 }
1377         }
1378         return 0;
1379 }
1380
1381 /*
1382  * Request function. for read/write operation
1383  */
1384 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1385 {
1386         struct omap_hsmmc_host *host = mmc_priv(mmc);
1387         int err;
1388
1389         /*
1390          * Prevent races with the interrupt handler because of unexpected
1391          * interrupts, but not if we are already in interrupt context i.e.
1392          * retries.
1393          */
1394         if (!in_interrupt()) {
1395                 spin_lock_irqsave(&host->irq_lock, host->flags);
1396                 /*
1397                  * Protect the card from I/O if there is a possibility
1398                  * it can be removed.
1399                  */
1400                 if (host->protect_card) {
1401                         if (host->reqs_blocked < 3) {
1402                                 /*
1403                                  * Ensure the controller is left in a consistent
1404                                  * state by resetting the command and data state
1405                                  * machines.
1406                                  */
1407                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1408                                 omap_hsmmc_reset_controller_fsm(host, SRC);
1409                                 host->reqs_blocked += 1;
1410                         }
1411                         req->cmd->error = -EBADF;
1412                         if (req->data)
1413                                 req->data->error = -EBADF;
1414                         spin_unlock_irqrestore(&host->irq_lock, host->flags);
1415                         mmc_request_done(mmc, req);
1416                         return;
1417                 } else if (host->reqs_blocked)
1418                         host->reqs_blocked = 0;
1419         }
1420         WARN_ON(host->mrq != NULL);
1421         host->mrq = req;
1422         err = omap_hsmmc_prepare_data(host, req);
1423         if (err) {
1424                 req->cmd->error = err;
1425                 if (req->data)
1426                         req->data->error = err;
1427                 host->mrq = NULL;
1428                 if (!in_interrupt())
1429                         spin_unlock_irqrestore(&host->irq_lock, host->flags);
1430                 mmc_request_done(mmc, req);
1431                 return;
1432         }
1433
1434         omap_hsmmc_start_command(host, req->cmd, req->data);
1435 }
1436
1437 /* Routine to configure clock values. Exposed API to core */
1438 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1439 {
1440         struct omap_hsmmc_host *host = mmc_priv(mmc);
1441         u16 dsor = 0;
1442         unsigned long regval;
1443         unsigned long timeout;
1444         u32 con;
1445         int do_send_init_stream = 0;
1446
1447         mmc_host_enable(host->mmc);
1448
1449         if (ios->power_mode != host->power_mode) {
1450                 switch (ios->power_mode) {
1451                 case MMC_POWER_OFF:
1452                         mmc_slot(host).set_power(host->dev, host->slot_id,
1453                                                  0, 0);
1454                         host->vdd = 0;
1455                         break;
1456                 case MMC_POWER_UP:
1457                         mmc_slot(host).set_power(host->dev, host->slot_id,
1458                                                  1, ios->vdd);
1459                         host->vdd = ios->vdd;
1460                         break;
1461                 case MMC_POWER_ON:
1462                         do_send_init_stream = 1;
1463                         break;
1464                 }
1465                 host->power_mode = ios->power_mode;
1466         }
1467
1468         /* FIXME: set registers based only on changes to ios */
1469
1470         con = OMAP_HSMMC_READ(host->base, CON);
1471         switch (mmc->ios.bus_width) {
1472         case MMC_BUS_WIDTH_8:
1473                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1474                 break;
1475         case MMC_BUS_WIDTH_4:
1476                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1477                 OMAP_HSMMC_WRITE(host->base, HCTL,
1478                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1479                 break;
1480         case MMC_BUS_WIDTH_1:
1481                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1482                 OMAP_HSMMC_WRITE(host->base, HCTL,
1483                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1484                 break;
1485         }
1486
1487         if (host->id == OMAP_MMC1_DEVID) {
1488                 /* Only MMC1 can interface at 3V without some flavor
1489                  * of external transceiver; but they all handle 1.8V.
1490                  */
1491                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1492                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1493                                 /*
1494                                  * The mmc_select_voltage fn of the core does
1495                                  * not seem to set the power_mode to
1496                                  * MMC_POWER_UP upon recalculating the voltage.
1497                                  * vdd 1.8v.
1498                                  */
1499                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1500                                 dev_dbg(mmc_dev(host->mmc),
1501                                                 "Switch operation failed\n");
1502                 }
1503         }
1504
1505         if (ios->clock) {
1506                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1507                 if (dsor < 1)
1508                         dsor = 1;
1509
1510                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1511                         dsor++;
1512
1513                 if (dsor > 250)
1514                         dsor = 250;
1515         }
1516         omap_hsmmc_stop_clock(host);
1517         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1518         regval = regval & ~(CLKD_MASK);
1519         regval = regval | (dsor << 6) | (DTO << 16);
1520         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1521         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1522                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1523
1524         /* Wait till the ICS bit is set */
1525         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1526         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1527                 && time_before(jiffies, timeout))
1528                 msleep(1);
1529
1530         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1531                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1532
1533         if (do_send_init_stream)
1534                 send_init_stream(host);
1535
1536         con = OMAP_HSMMC_READ(host->base, CON);
1537         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1538                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1539         else
1540                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1541
1542         if (host->power_mode == MMC_POWER_OFF)
1543                 mmc_host_disable(host->mmc);
1544         else
1545                 mmc_host_lazy_disable(host->mmc);
1546 }
1547
1548 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1549 {
1550         struct omap_hsmmc_host *host = mmc_priv(mmc);
1551
1552         if (!mmc_slot(host).card_detect)
1553                 return -ENOSYS;
1554         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1555 }
1556
1557 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1558 {
1559         struct omap_hsmmc_host *host = mmc_priv(mmc);
1560
1561         if (!mmc_slot(host).get_ro)
1562                 return -ENOSYS;
1563         return mmc_slot(host).get_ro(host->dev, 0);
1564 }
1565
1566 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1567 {
1568         u32 hctl, capa, value;
1569
1570         /* Only MMC1 supports 3.0V */
1571         if (host->id == OMAP_MMC1_DEVID) {
1572                 hctl = SDVS30;
1573                 capa = VS30 | VS18;
1574         } else {
1575                 hctl = SDVS18;
1576                 capa = VS18;
1577         }
1578
1579         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1580         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1581
1582         value = OMAP_HSMMC_READ(host->base, CAPA);
1583         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1584
1585         /* Set the controller to AUTO IDLE mode */
1586         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1587         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1588
1589         /* Set SD bus power bit */
1590         set_sd_bus_power(host);
1591 }
1592
1593 /*
1594  * Dynamic power saving handling, FSM:
1595  *   ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1596  *     ^___________|          |                      |
1597  *     |______________________|______________________|
1598  *
1599  * ENABLED:   mmc host is fully functional
1600  * DISABLED:  fclk is off
1601  * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1602  * REGSLEEP:  fclk is off, voltage regulator is asleep
1603  * OFF:       fclk is off, voltage regulator is off
1604  *
1605  * Transition handlers return the timeout for the next state transition
1606  * or negative error.
1607  */
1608
1609 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
1610
1611 /* Handler for [ENABLED -> DISABLED] transition */
1612 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
1613 {
1614         omap_hsmmc_context_save(host);
1615         clk_disable(host->fclk);
1616         host->dpm_state = DISABLED;
1617
1618         dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1619
1620         if (host->power_mode == MMC_POWER_OFF)
1621                 return 0;
1622
1623         return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT);
1624 }
1625
1626 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1627 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
1628 {
1629         int err, new_state;
1630
1631         if (!mmc_try_claim_host(host->mmc))
1632                 return 0;
1633
1634         clk_enable(host->fclk);
1635         omap_hsmmc_context_restore(host);
1636         if (mmc_card_can_sleep(host->mmc)) {
1637                 err = mmc_card_sleep(host->mmc);
1638                 if (err < 0) {
1639                         clk_disable(host->fclk);
1640                         mmc_release_host(host->mmc);
1641                         return err;
1642                 }
1643                 new_state = CARDSLEEP;
1644         } else {
1645                 new_state = REGSLEEP;
1646         }
1647         if (mmc_slot(host).set_sleep)
1648                 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1649                                          new_state == CARDSLEEP);
1650         /* FIXME: turn off bus power and perhaps interrupts too */
1651         clk_disable(host->fclk);
1652         host->dpm_state = new_state;
1653
1654         mmc_release_host(host->mmc);
1655
1656         dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1657                 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1658
1659         if (mmc_slot(host).no_off)
1660                 return 0;
1661
1662         if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1663             mmc_slot(host).card_detect ||
1664             (mmc_slot(host).get_cover_state &&
1665              mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1666                 return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT);
1667
1668         return 0;
1669 }
1670
1671 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1672 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
1673 {
1674         if (!mmc_try_claim_host(host->mmc))
1675                 return 0;
1676
1677         if (mmc_slot(host).no_off)
1678                 return 0;
1679
1680         if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1681               mmc_slot(host).card_detect ||
1682               (mmc_slot(host).get_cover_state &&
1683                mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1684                 mmc_release_host(host->mmc);
1685                 return 0;
1686         }
1687
1688         mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1689         host->vdd = 0;
1690         host->power_mode = MMC_POWER_OFF;
1691
1692         dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1693                 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1694
1695         host->dpm_state = OFF;
1696
1697         mmc_release_host(host->mmc);
1698
1699         return 0;
1700 }
1701
1702 /* Handler for [DISABLED -> ENABLED] transition */
1703 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
1704 {
1705         int err;
1706
1707         err = clk_enable(host->fclk);
1708         if (err < 0)
1709                 return err;
1710
1711         omap_hsmmc_context_restore(host);
1712         host->dpm_state = ENABLED;
1713
1714         dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1715
1716         return 0;
1717 }
1718
1719 /* Handler for [SLEEP -> ENABLED] transition */
1720 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
1721 {
1722         if (!mmc_try_claim_host(host->mmc))
1723                 return 0;
1724
1725         clk_enable(host->fclk);
1726         omap_hsmmc_context_restore(host);
1727         if (mmc_slot(host).set_sleep)
1728                 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1729                          host->vdd, host->dpm_state == CARDSLEEP);
1730         if (mmc_card_can_sleep(host->mmc))
1731                 mmc_card_awake(host->mmc);
1732
1733         dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1734                 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1735
1736         host->dpm_state = ENABLED;
1737
1738         mmc_release_host(host->mmc);
1739
1740         return 0;
1741 }
1742
1743 /* Handler for [OFF -> ENABLED] transition */
1744 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
1745 {
1746         clk_enable(host->fclk);
1747
1748         omap_hsmmc_context_restore(host);
1749         omap_hsmmc_conf_bus_power(host);
1750         mmc_power_restore_host(host->mmc);
1751
1752         host->dpm_state = ENABLED;
1753
1754         dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1755
1756         return 0;
1757 }
1758
1759 /*
1760  * Bring MMC host to ENABLED from any other PM state.
1761  */
1762 static int omap_hsmmc_enable(struct mmc_host *mmc)
1763 {
1764         struct omap_hsmmc_host *host = mmc_priv(mmc);
1765
1766         switch (host->dpm_state) {
1767         case DISABLED:
1768                 return omap_hsmmc_disabled_to_enabled(host);
1769         case CARDSLEEP:
1770         case REGSLEEP:
1771                 return omap_hsmmc_sleep_to_enabled(host);
1772         case OFF:
1773                 return omap_hsmmc_off_to_enabled(host);
1774         default:
1775                 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1776                 return -EINVAL;
1777         }
1778 }
1779
1780 /*
1781  * Bring MMC host in PM state (one level deeper).
1782  */
1783 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
1784 {
1785         struct omap_hsmmc_host *host = mmc_priv(mmc);
1786
1787         switch (host->dpm_state) {
1788         case ENABLED: {
1789                 int delay;
1790
1791                 delay = omap_hsmmc_enabled_to_disabled(host);
1792                 if (lazy || delay < 0)
1793                         return delay;
1794                 return 0;
1795         }
1796         case DISABLED:
1797                 return omap_hsmmc_disabled_to_sleep(host);
1798         case CARDSLEEP:
1799         case REGSLEEP:
1800                 return omap_hsmmc_sleep_to_off(host);
1801         default:
1802                 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1803                 return -EINVAL;
1804         }
1805 }
1806
1807 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1808 {
1809         struct omap_hsmmc_host *host = mmc_priv(mmc);
1810         int err;
1811
1812         err = clk_enable(host->fclk);
1813         if (err)
1814                 return err;
1815         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1816         omap_hsmmc_context_restore(host);
1817         return 0;
1818 }
1819
1820 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1821 {
1822         struct omap_hsmmc_host *host = mmc_priv(mmc);
1823
1824         omap_hsmmc_context_save(host);
1825         clk_disable(host->fclk);
1826         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1827         return 0;
1828 }
1829
1830 static const struct mmc_host_ops omap_hsmmc_ops = {
1831         .enable = omap_hsmmc_enable_fclk,
1832         .disable = omap_hsmmc_disable_fclk,
1833         .request = omap_hsmmc_request,
1834         .set_ios = omap_hsmmc_set_ios,
1835         .get_cd = omap_hsmmc_get_cd,
1836         .get_ro = omap_hsmmc_get_ro,
1837         /* NYET -- enable_sdio_irq */
1838 };
1839
1840 static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1841         .enable = omap_hsmmc_enable,
1842         .disable = omap_hsmmc_disable,
1843         .request = omap_hsmmc_request,
1844         .set_ios = omap_hsmmc_set_ios,
1845         .get_cd = omap_hsmmc_get_cd,
1846         .get_ro = omap_hsmmc_get_ro,
1847         /* NYET -- enable_sdio_irq */
1848 };
1849
1850 #ifdef CONFIG_DEBUG_FS
1851
1852 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1853 {
1854         struct mmc_host *mmc = s->private;
1855         struct omap_hsmmc_host *host = mmc_priv(mmc);
1856         int context_loss = 0;
1857
1858         if (host->pdata->get_context_loss_count)
1859                 context_loss = host->pdata->get_context_loss_count(host->dev);
1860
1861         seq_printf(s, "mmc%d:\n"
1862                         " enabled:\t%d\n"
1863                         " dpm_state:\t%d\n"
1864                         " nesting_cnt:\t%d\n"
1865                         " ctx_loss:\t%d:%d\n"
1866                         "\nregs:\n",
1867                         mmc->index, mmc->enabled ? 1 : 0,
1868                         host->dpm_state, mmc->nesting_cnt,
1869                         host->context_loss, context_loss);
1870
1871         if (host->suspended || host->dpm_state == OFF) {
1872                 seq_printf(s, "host suspended, can't read registers\n");
1873                 return 0;
1874         }
1875
1876         if (clk_enable(host->fclk) != 0) {
1877                 seq_printf(s, "can't read the regs\n");
1878                 return 0;
1879         }
1880
1881         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1882                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1883         seq_printf(s, "CON:\t\t0x%08x\n",
1884                         OMAP_HSMMC_READ(host->base, CON));
1885         seq_printf(s, "HCTL:\t\t0x%08x\n",
1886                         OMAP_HSMMC_READ(host->base, HCTL));
1887         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1888                         OMAP_HSMMC_READ(host->base, SYSCTL));
1889         seq_printf(s, "IE:\t\t0x%08x\n",
1890                         OMAP_HSMMC_READ(host->base, IE));
1891         seq_printf(s, "ISE:\t\t0x%08x\n",
1892                         OMAP_HSMMC_READ(host->base, ISE));
1893         seq_printf(s, "CAPA:\t\t0x%08x\n",
1894                         OMAP_HSMMC_READ(host->base, CAPA));
1895
1896         clk_disable(host->fclk);
1897
1898         return 0;
1899 }
1900
1901 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1902 {
1903         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1904 }
1905
1906 static const struct file_operations mmc_regs_fops = {
1907         .open           = omap_hsmmc_regs_open,
1908         .read           = seq_read,
1909         .llseek         = seq_lseek,
1910         .release        = single_release,
1911 };
1912
1913 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1914 {
1915         if (mmc->debugfs_root)
1916                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1917                         mmc, &mmc_regs_fops);
1918 }
1919
1920 #else
1921
1922 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1923 {
1924 }
1925
1926 #endif
1927
1928 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1929 {
1930         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1931         struct mmc_host *mmc;
1932         struct omap_hsmmc_host *host = NULL;
1933         struct resource *res;
1934         int ret, irq;
1935
1936         if (pdata == NULL) {
1937                 dev_err(&pdev->dev, "Platform Data is missing\n");
1938                 return -ENXIO;
1939         }
1940
1941         if (pdata->nr_slots == 0) {
1942                 dev_err(&pdev->dev, "No Slots\n");
1943                 return -ENXIO;
1944         }
1945
1946         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1947         irq = platform_get_irq(pdev, 0);
1948         if (res == NULL || irq < 0)
1949                 return -ENXIO;
1950
1951         res = request_mem_region(res->start, res->end - res->start + 1,
1952                                                         pdev->name);
1953         if (res == NULL)
1954                 return -EBUSY;
1955
1956         ret = omap_hsmmc_gpio_init(pdata);
1957         if (ret)
1958                 goto err;
1959
1960         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1961         if (!mmc) {
1962                 ret = -ENOMEM;
1963                 goto err_alloc;
1964         }
1965
1966         host            = mmc_priv(mmc);
1967         host->mmc       = mmc;
1968         host->pdata     = pdata;
1969         host->dev       = &pdev->dev;
1970         host->use_dma   = 1;
1971         host->dev->dma_mask = &pdata->dma_mask;
1972         host->dma_ch    = -1;
1973         host->irq       = irq;
1974         host->id        = pdev->id;
1975         host->slot_id   = 0;
1976         host->mapbase   = res->start;
1977         host->base      = ioremap(host->mapbase, SZ_4K);
1978         host->power_mode = -1;
1979
1980         platform_set_drvdata(pdev, host);
1981         INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
1982
1983         if (mmc_slot(host).power_saving)
1984                 mmc->ops        = &omap_hsmmc_ps_ops;
1985         else
1986                 mmc->ops        = &omap_hsmmc_ops;
1987
1988         mmc->f_min      = 400000;
1989         mmc->f_max      = 52000000;
1990
1991         sema_init(&host->sem, 1);
1992         spin_lock_init(&host->irq_lock);
1993
1994         host->iclk = clk_get(&pdev->dev, "ick");
1995         if (IS_ERR(host->iclk)) {
1996                 ret = PTR_ERR(host->iclk);
1997                 host->iclk = NULL;
1998                 goto err1;
1999         }
2000         host->fclk = clk_get(&pdev->dev, "fck");
2001         if (IS_ERR(host->fclk)) {
2002                 ret = PTR_ERR(host->fclk);
2003                 host->fclk = NULL;
2004                 clk_put(host->iclk);
2005                 goto err1;
2006         }
2007
2008         omap_hsmmc_context_save(host);
2009
2010         mmc->caps |= MMC_CAP_DISABLE;
2011         mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
2012         /* we start off in DISABLED state */
2013         host->dpm_state = DISABLED;
2014
2015         if (mmc_host_enable(host->mmc) != 0) {
2016                 clk_put(host->iclk);
2017                 clk_put(host->fclk);
2018                 goto err1;
2019         }
2020
2021         if (clk_enable(host->iclk) != 0) {
2022                 mmc_host_disable(host->mmc);
2023                 clk_put(host->iclk);
2024                 clk_put(host->fclk);
2025                 goto err1;
2026         }
2027
2028         if (cpu_is_omap2430()) {
2029                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2030                 /*
2031                  * MMC can still work without debounce clock.
2032                  */
2033                 if (IS_ERR(host->dbclk))
2034                         dev_warn(mmc_dev(host->mmc),
2035                                 "Failed to get debounce clock\n");
2036                 else
2037                         host->got_dbclk = 1;
2038
2039                 if (host->got_dbclk)
2040                         if (clk_enable(host->dbclk) != 0)
2041                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2042                                                         " clk failed\n");
2043         }
2044
2045         /* Since we do only SG emulation, we can have as many segs
2046          * as we want. */
2047         mmc->max_phys_segs = 1024;
2048         mmc->max_hw_segs = 1024;
2049
2050         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2051         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2052         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2053         mmc->max_seg_size = mmc->max_req_size;
2054
2055         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2056                      MMC_CAP_WAIT_WHILE_BUSY;
2057
2058         if (mmc_slot(host).wires >= 8)
2059                 mmc->caps |= MMC_CAP_8_BIT_DATA;
2060         else if (mmc_slot(host).wires >= 4)
2061                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2062
2063         if (mmc_slot(host).nonremovable)
2064                 mmc->caps |= MMC_CAP_NONREMOVABLE;
2065
2066         omap_hsmmc_conf_bus_power(host);
2067
2068         /* Select DMA lines */
2069         switch (host->id) {
2070         case OMAP_MMC1_DEVID:
2071                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2072                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2073                 break;
2074         case OMAP_MMC2_DEVID:
2075                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2076                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2077                 break;
2078         case OMAP_MMC3_DEVID:
2079                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2080                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2081                 break;
2082         case OMAP_MMC4_DEVID:
2083                 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2084                 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2085                 break;
2086         case OMAP_MMC5_DEVID:
2087                 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2088                 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2089                 break;
2090         default:
2091                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2092                 goto err_irq;
2093         }
2094
2095         /* Request IRQ for MMC operations */
2096         ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
2097                         mmc_hostname(mmc), host);
2098         if (ret) {
2099                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2100                 goto err_irq;
2101         }
2102
2103         if (pdata->init != NULL) {
2104                 if (pdata->init(&pdev->dev) != 0) {
2105                         dev_dbg(mmc_dev(host->mmc),
2106                                 "Unable to configure MMC IRQs\n");
2107                         goto err_irq_cd_init;
2108                 }
2109         }
2110
2111         if (!mmc_slot(host).set_power) {
2112                 ret = omap_hsmmc_reg_get(host);
2113                 if (ret)
2114                         goto err_reg;
2115                 host->use_reg = 1;
2116         }
2117
2118         mmc->ocr_avail = mmc_slot(host).ocr_mask;
2119
2120         /* Request IRQ for card detect */
2121         if ((mmc_slot(host).card_detect_irq)) {
2122                 ret = request_irq(mmc_slot(host).card_detect_irq,
2123                                   omap_hsmmc_cd_handler,
2124                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2125                                           | IRQF_DISABLED,
2126                                   mmc_hostname(mmc), host);
2127                 if (ret) {
2128                         dev_dbg(mmc_dev(host->mmc),
2129                                 "Unable to grab MMC CD IRQ\n");
2130                         goto err_irq_cd;
2131                 }
2132         }
2133
2134         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
2135         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
2136
2137         mmc_host_lazy_disable(host->mmc);
2138
2139         omap_hsmmc_protect_card(host);
2140
2141         mmc_add_host(mmc);
2142
2143         if (mmc_slot(host).name != NULL) {
2144                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2145                 if (ret < 0)
2146                         goto err_slot_name;
2147         }
2148         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2149                 ret = device_create_file(&mmc->class_dev,
2150                                         &dev_attr_cover_switch);
2151                 if (ret < 0)
2152                         goto err_slot_name;
2153         }
2154
2155         omap_hsmmc_debugfs(mmc);
2156
2157         return 0;
2158
2159 err_slot_name:
2160         mmc_remove_host(mmc);
2161         free_irq(mmc_slot(host).card_detect_irq, host);
2162 err_irq_cd:
2163         if (host->use_reg)
2164                 omap_hsmmc_reg_put(host);
2165 err_reg:
2166         if (host->pdata->cleanup)
2167                 host->pdata->cleanup(&pdev->dev);
2168 err_irq_cd_init:
2169         free_irq(host->irq, host);
2170 err_irq:
2171         mmc_host_disable(host->mmc);
2172         clk_disable(host->iclk);
2173         clk_put(host->fclk);
2174         clk_put(host->iclk);
2175         if (host->got_dbclk) {
2176                 clk_disable(host->dbclk);
2177                 clk_put(host->dbclk);
2178         }
2179 err1:
2180         iounmap(host->base);
2181         platform_set_drvdata(pdev, NULL);
2182         mmc_free_host(mmc);
2183 err_alloc:
2184         omap_hsmmc_gpio_free(pdata);
2185 err:
2186         release_mem_region(res->start, res->end - res->start + 1);
2187         return ret;
2188 }
2189
2190 static int omap_hsmmc_remove(struct platform_device *pdev)
2191 {
2192         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2193         struct resource *res;
2194
2195         if (host) {
2196                 mmc_host_enable(host->mmc);
2197                 mmc_remove_host(host->mmc);
2198                 if (host->use_reg)
2199                         omap_hsmmc_reg_put(host);
2200                 if (host->pdata->cleanup)
2201                         host->pdata->cleanup(&pdev->dev);
2202                 free_irq(host->irq, host);
2203                 if (mmc_slot(host).card_detect_irq)
2204                         free_irq(mmc_slot(host).card_detect_irq, host);
2205                 flush_scheduled_work();
2206
2207                 mmc_host_disable(host->mmc);
2208                 clk_disable(host->iclk);
2209                 clk_put(host->fclk);
2210                 clk_put(host->iclk);
2211                 if (host->got_dbclk) {
2212                         clk_disable(host->dbclk);
2213                         clk_put(host->dbclk);
2214                 }
2215
2216                 mmc_free_host(host->mmc);
2217                 iounmap(host->base);
2218                 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2219         }
2220
2221         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2222         if (res)
2223                 release_mem_region(res->start, res->end - res->start + 1);
2224         platform_set_drvdata(pdev, NULL);
2225
2226         return 0;
2227 }
2228
2229 #ifdef CONFIG_PM
2230 static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state)
2231 {
2232         int ret = 0;
2233         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2234
2235         if (host && host->suspended)
2236                 return 0;
2237
2238         if (host) {
2239                 host->suspended = 1;
2240                 if (host->pdata->suspend) {
2241                         ret = host->pdata->suspend(&pdev->dev,
2242                                                         host->slot_id);
2243                         if (ret) {
2244                                 dev_dbg(mmc_dev(host->mmc),
2245                                         "Unable to handle MMC board"
2246                                         " level suspend\n");
2247                                 host->suspended = 0;
2248                                 return ret;
2249                         }
2250                 }
2251                 cancel_work_sync(&host->mmc_carddetect_work);
2252                 mmc_host_enable(host->mmc);
2253                 ret = mmc_suspend_host(host->mmc, state);
2254                 if (ret == 0) {
2255                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
2256                         OMAP_HSMMC_WRITE(host->base, IE, 0);
2257
2258
2259                         OMAP_HSMMC_WRITE(host->base, HCTL,
2260                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2261                         mmc_host_disable(host->mmc);
2262                         clk_disable(host->iclk);
2263                         if (host->got_dbclk)
2264                                 clk_disable(host->dbclk);
2265                 } else {
2266                         host->suspended = 0;
2267                         if (host->pdata->resume) {
2268                                 ret = host->pdata->resume(&pdev->dev,
2269                                                           host->slot_id);
2270                                 if (ret)
2271                                         dev_dbg(mmc_dev(host->mmc),
2272                                                 "Unmask interrupt failed\n");
2273                         }
2274                         mmc_host_disable(host->mmc);
2275                 }
2276
2277         }
2278         return ret;
2279 }
2280
2281 /* Routine to resume the MMC device */
2282 static int omap_hsmmc_resume(struct platform_device *pdev)
2283 {
2284         int ret = 0;
2285         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2286
2287         if (host && !host->suspended)
2288                 return 0;
2289
2290         if (host) {
2291                 ret = clk_enable(host->iclk);
2292                 if (ret)
2293                         goto clk_en_err;
2294
2295                 if (mmc_host_enable(host->mmc) != 0) {
2296                         clk_disable(host->iclk);
2297                         goto clk_en_err;
2298                 }
2299
2300                 if (host->got_dbclk)
2301                         clk_enable(host->dbclk);
2302
2303                 omap_hsmmc_conf_bus_power(host);
2304
2305                 if (host->pdata->resume) {
2306                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
2307                         if (ret)
2308                                 dev_dbg(mmc_dev(host->mmc),
2309                                         "Unmask interrupt failed\n");
2310                 }
2311
2312                 omap_hsmmc_protect_card(host);
2313
2314                 /* Notify the core to resume the host */
2315                 ret = mmc_resume_host(host->mmc);
2316                 if (ret == 0)
2317                         host->suspended = 0;
2318
2319                 mmc_host_lazy_disable(host->mmc);
2320         }
2321
2322         return ret;
2323
2324 clk_en_err:
2325         dev_dbg(mmc_dev(host->mmc),
2326                 "Failed to enable MMC clocks during resume\n");
2327         return ret;
2328 }
2329
2330 #else
2331 #define omap_hsmmc_suspend      NULL
2332 #define omap_hsmmc_resume               NULL
2333 #endif
2334
2335 static struct platform_driver omap_hsmmc_driver = {
2336         .remove         = omap_hsmmc_remove,
2337         .suspend        = omap_hsmmc_suspend,
2338         .resume         = omap_hsmmc_resume,
2339         .driver         = {
2340                 .name = DRIVER_NAME,
2341                 .owner = THIS_MODULE,
2342         },
2343 };
2344
2345 static int __init omap_hsmmc_init(void)
2346 {
2347         /* Register the MMC driver */
2348         return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2349 }
2350
2351 static void __exit omap_hsmmc_cleanup(void)
2352 {
2353         /* Unregister MMC driver */
2354         platform_driver_unregister(&omap_hsmmc_driver);
2355 }
2356
2357 module_init(omap_hsmmc_init);
2358 module_exit(omap_hsmmc_cleanup);
2359
2360 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2361 MODULE_LICENSE("GPL");
2362 MODULE_ALIAS("platform:" DRIVER_NAME);
2363 MODULE_AUTHOR("Texas Instruments Inc");