drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/core.h>
  31 #include <linux/mmc/mmc.h>
  32 #include <linux/io.h>
  33 #include <linux/semaphore.h>
  34 #include <linux/gpio.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/pm_runtime.h>
  37 #include <plat/dma.h>
  38 #include <mach/hardware.h>
  39 #include <plat/board.h>
  40 #include <plat/mmc.h>
  41 #include <plat/cpu.h>
  42
  43 /* OMAP HSMMC Host Controller Registers */
  44 #define OMAP_HSMMC_SYSCONFIG    0x0010
  45 #define OMAP_HSMMC_SYSSTATUS    0x0014
  46 #define OMAP_HSMMC_CON          0x002C
  47 #define OMAP_HSMMC_BLK          0x0104
  48 #define OMAP_HSMMC_ARG          0x0108
  49 #define OMAP_HSMMC_CMD          0x010C
  50 #define OMAP_HSMMC_RSP10        0x0110
  51 #define OMAP_HSMMC_RSP32        0x0114
  52 #define OMAP_HSMMC_RSP54        0x0118
  53 #define OMAP_HSMMC_RSP76        0x011C
  54 #define OMAP_HSMMC_DATA         0x0120
  55 #define OMAP_HSMMC_HCTL         0x0128
  56 #define OMAP_HSMMC_SYSCTL       0x012C
  57 #define OMAP_HSMMC_STAT         0x0130
  58 #define OMAP_HSMMC_IE           0x0134
  59 #define OMAP_HSMMC_ISE          0x0138
  60 #define OMAP_HSMMC_CAPA         0x0140
  61
  62 #define VS18                    (1 << 26)
  63 #define VS30                    (1 << 25)
  64 #define SDVS18                  (0x5 << 9)
  65 #define SDVS30                  (0x6 << 9)
  66 #define SDVS33                  (0x7 << 9)
  67 #define SDVS_MASK               0x00000E00
  68 #define SDVSCLR                 0xFFFFF1FF
  69 #define SDVSDET                 0x00000400
  70 #define AUTOIDLE                0x1
  71 #define SDBP                    (1 << 8)
  72 #define DTO                     0xe
  73 #define ICE                     0x1
  74 #define ICS                     0x2
  75 #define CEN                     (1 << 2)
  76 #define CLKD_MASK               0x0000FFC0
  77 #define CLKD_SHIFT              6
  78 #define DTO_MASK                0x000F0000
  79 #define DTO_SHIFT               16
  80 #define INT_EN_MASK             0x307F0033
  81 #define BWR_ENABLE              (1 << 4)
  82 #define BRR_ENABLE              (1 << 5)
  83 #define DTO_ENABLE              (1 << 20)
  84 #define INIT_STREAM             (1 << 1)
  85 #define DP_SELECT               (1 << 21)
  86 #define DDIR                    (1 << 4)
  87 #define DMA_EN                  0x1
  88 #define MSBS                    (1 << 5)
  89 #define BCE                     (1 << 1)
  90 #define FOUR_BIT                (1 << 1)
  91 #define DW8                     (1 << 5)
  92 #define CC                      0x1
  93 #define TC                      0x02
  94 #define OD                      0x1
  95 #define ERR                     (1 << 15)
  96 #define CMD_TIMEOUT             (1 << 16)
  97 #define DATA_TIMEOUT            (1 << 20)
  98 #define CMD_CRC                 (1 << 17)
  99 #define DATA_CRC                (1 << 21)
 100 #define CARD_ERR                (1 << 28)
 101 #define STAT_CLEAR              0xFFFFFFFF
 102 #define INIT_STREAM_CMD         0x00000000
 103 #define DUAL_VOLT_OCR_BIT       7
 104 #define SRC                     (1 << 25)
 105 #define SRD                     (1 << 26)
 106 #define SOFTRESET               (1 << 1)
 107 #define RESETDONE               (1 << 0)
 108
 109 /*
 110  * FIXME: Most likely all the data using these _DEVID defines should come
 111  * from the platform_data, or implemented in controller and slot specific
 112  * functions.
 113  */
 114 #define OMAP_MMC1_DEVID         0
 115 #define OMAP_MMC2_DEVID         1
 116 #define OMAP_MMC3_DEVID         2
 117 #define OMAP_MMC4_DEVID         3
 118 #define OMAP_MMC5_DEVID         4
 119
 120 #define MMC_AUTOSUSPEND_DELAY   100
 121 #define MMC_TIMEOUT_MS          20
 122 #define OMAP_MMC_MASTER_CLOCK   96000000
 123 #define OMAP_MMC_MIN_CLOCK      400000
 124 #define OMAP_MMC_MAX_CLOCK      52000000
 125 #define DRIVER_NAME             "omap_hsmmc"
 126
 127 /*
 128  * One controller can have multiple slots, like on some omap boards using
 129  * omap.c controller driver. Luckily this is not currently done on any known
 130  * omap_hsmmc.c device.
 131  */
 132 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 133
 134 /*
 135  * MMC Host controller read/write API's
 136  */
 137 #define OMAP_HSMMC_READ(base, reg)      \
 138         __raw_readl((base) + OMAP_HSMMC_##reg)
 139
 140 #define OMAP_HSMMC_WRITE(base, reg, val) \
 141         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 142
 143 struct omap_hsmmc_next {
 144         unsigned int    dma_len;
 145         s32             cookie;
 146 };
 147
 148 struct omap_hsmmc_host {
 149         struct  device          *dev;
 150         struct  mmc_host        *mmc;
 151         struct  mmc_request     *mrq;
 152         struct  mmc_command     *cmd;
 153         struct  mmc_data        *data;
 154         struct  clk             *fclk;
 155         struct  clk             *dbclk;
 156         /*
 157          * vcc == configured supply
 158          * vcc_aux == optional
 159          *   -  MMC1, supply for DAT4..DAT7
 160          *   -  MMC2/MMC2, external level shifter voltage supply, for
 161          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 162          */
 163         struct  regulator       *vcc;
 164         struct  regulator       *vcc_aux;
 165         void    __iomem         *base;
 166         resource_size_t         mapbase;
 167         spinlock_t              irq_lock; /* Prevent races with irq handler */
 168         unsigned int            id;
 169         unsigned int            dma_len;
 170         unsigned int            dma_sg_idx;
 171         unsigned char           bus_mode;
 172         unsigned char           power_mode;
 173         u32                     *buffer;
 174         u32                     bytesleft;
 175         int                     suspended;
 176         int                     irq;
 177         int                     use_dma, dma_ch;
 178         int                     dma_ch_tx, dma_ch_rx;
 179         int                     dma_line_tx, dma_line_rx;
 180         int                     slot_id;
 181         int                     got_dbclk;
 182         int                     response_busy;
 183         int                     context_loss;
 184         int                     dpm_state;
 185         int                     vdd;
 186         int                     protect_card;
 187         int                     reqs_blocked;
 188         int                     use_reg;
 189         int                     req_in_progress;
 190         struct omap_hsmmc_next  next_data;
 191
 192         struct  omap_mmc_platform_data  *pdata;
 193 };
 194
 195 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 196 {
 197         struct omap_mmc_platform_data *mmc = dev->platform_data;
 198
 199         /* NOTE: assumes card detect signal is active-low */
 200         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 201 }
 202
 203 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 204 {
 205         struct omap_mmc_platform_data *mmc = dev->platform_data;
 206
 207         /* NOTE: assumes write protect signal is active-high */
 208         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 209 }
 210
 211 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 212 {
 213         struct omap_mmc_platform_data *mmc = dev->platform_data;
 214
 215         /* NOTE: assumes card detect signal is active-low */
 216         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 217 }
 218
 219 #ifdef CONFIG_PM
 220
 221 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 222 {
 223         struct omap_mmc_platform_data *mmc = dev->platform_data;
 224
 225         disable_irq(mmc->slots[0].card_detect_irq);
 226         return 0;
 227 }
 228
 229 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 230 {
 231         struct omap_mmc_platform_data *mmc = dev->platform_data;
 232
 233         enable_irq(mmc->slots[0].card_detect_irq);
 234         return 0;
 235 }
 236
 237 #else
 238
 239 #define omap_hsmmc_suspend_cdirq        NULL
 240 #define omap_hsmmc_resume_cdirq         NULL
 241
 242 #endif
 243
 244 #ifdef CONFIG_REGULATOR
 245
 246 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
 247                                   int vdd)
 248 {
 249         struct omap_hsmmc_host *host =
 250                 platform_get_drvdata(to_platform_device(dev));
 251         int ret;
 252
 253         if (mmc_slot(host).before_set_reg)
 254                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 255
 256         if (power_on)
 257                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 258         else
 259                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
 260
 261         if (mmc_slot(host).after_set_reg)
 262                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 263
 264         return ret;
 265 }
 266
 267 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
 268                                    int vdd)
 269 {
 270         struct omap_hsmmc_host *host =
 271                 platform_get_drvdata(to_platform_device(dev));
 272         int ret = 0;
 273
 274         /*
 275          * If we don't see a Vcc regulator, assume it's a fixed
 276          * voltage always-on regulator.
 277          */
 278         if (!host->vcc)
 279                 return 0;
 280
 281         if (mmc_slot(host).before_set_reg)
 282                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 283
 284         /*
 285          * Assume Vcc regulator is used only to power the card ... OMAP
 286          * VDDS is used to power the pins, optionally with a transceiver to
 287          * support cards using voltages other than VDDS (1.8V nominal).  When a
 288          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 289          *
 290          * In some cases this regulator won't support enable/disable;
 291          * e.g. it's a fixed rail for a WLAN chip.
 292          *
 293          * In other cases vcc_aux switches interface power.  Example, for
 294          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 295          * chips/cards need an interface voltage rail too.
 296          */
 297         if (power_on) {
 298                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 299                 /* Enable interface voltage rail, if needed */
 300                 if (ret == 0 && host->vcc_aux) {
 301                         ret = regulator_enable(host->vcc_aux);
 302                         if (ret < 0)
 303                                 ret = mmc_regulator_set_ocr(host->mmc,
 304                                                         host->vcc, 0);
 305                 }
 306         } else {
 307                 /* Shut down the rail */
 308                 if (host->vcc_aux)
 309                         ret = regulator_disable(host->vcc_aux);
 310                 if (!ret) {
 311                         /* Then proceed to shut down the local regulator */
 312                         ret = mmc_regulator_set_ocr(host->mmc,
 313                                                 host->vcc, 0);
 314                 }
 315         }
 316
 317         if (mmc_slot(host).after_set_reg)
 318                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 319
 320         return ret;
 321 }
 322
 323 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
 324                                         int vdd)
 325 {
 326         return 0;
 327 }
 328
 329 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
 330                                   int vdd, int cardsleep)
 331 {
 332         struct omap_hsmmc_host *host =
 333                 platform_get_drvdata(to_platform_device(dev));
 334         int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
 335
 336         return regulator_set_mode(host->vcc, mode);
 337 }
 338
 339 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
 340                                    int vdd, int cardsleep)
 341 {
 342         struct omap_hsmmc_host *host =
 343                 platform_get_drvdata(to_platform_device(dev));
 344         int err, mode;
 345
 346         /*
 347          * If we don't see a Vcc regulator, assume it's a fixed
 348          * voltage always-on regulator.
 349          */
 350         if (!host->vcc)
 351                 return 0;
 352
 353         mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
 354
 355         if (!host->vcc_aux)
 356                 return regulator_set_mode(host->vcc, mode);
 357
 358         if (cardsleep) {
 359                 /* VCC can be turned off if card is asleep */
 360                 if (sleep)
 361                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
 362                 else
 363                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 364         } else
 365                 err = regulator_set_mode(host->vcc, mode);
 366         if (err)
 367                 return err;
 368
 369         if (!mmc_slot(host).vcc_aux_disable_is_sleep)
 370                 return regulator_set_mode(host->vcc_aux, mode);
 371
 372         if (sleep)
 373                 return regulator_disable(host->vcc_aux);
 374         else
 375                 return regulator_enable(host->vcc_aux);
 376 }
 377
 378 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
 379                                         int vdd, int cardsleep)
 380 {
 381         return 0;
 382 }
 383
 384 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 385 {
 386         struct regulator *reg;
 387         int ret = 0;
 388         int ocr_value = 0;
 389
 390         switch (host->id) {
 391         case OMAP_MMC1_DEVID:
 392                 /* On-chip level shifting via PBIAS0/PBIAS1 */
 393                 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
 394                 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
 395                 break;
 396         case OMAP_MMC2_DEVID:
 397         case OMAP_MMC3_DEVID:
 398         case OMAP_MMC5_DEVID:
 399                 /* Off-chip level shifting, or none */
 400                 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
 401                 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
 402                 break;
 403         case OMAP_MMC4_DEVID:
 404                 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
 405                 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
 406         default:
 407                 pr_err("MMC%d configuration not supported!\n", host->id);
 408                 return -EINVAL;
 409         }
 410
 411         reg = regulator_get(host->dev, "vmmc");
 412         if (IS_ERR(reg)) {
 413                 dev_dbg(host->dev, "vmmc regulator missing\n");
 414                 /*
 415                 * HACK: until fixed.c regulator is usable,
 416                 * we don't require a main regulator
 417                 * for MMC2 or MMC3
 418                 */
 419                 if (host->id == OMAP_MMC1_DEVID) {
 420                         ret = PTR_ERR(reg);
 421                         goto err;
 422                 }
 423         } else {
 424                 host->vcc = reg;
 425                 ocr_value = mmc_regulator_get_ocrmask(reg);
 426                 if (!mmc_slot(host).ocr_mask) {
 427                         mmc_slot(host).ocr_mask = ocr_value;
 428                 } else {
 429                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
 430                                 pr_err("MMC%d ocrmask %x is not supported\n",
 431                                         host->id, mmc_slot(host).ocr_mask);
 432                                 mmc_slot(host).ocr_mask = 0;
 433                                 return -EINVAL;
 434                         }
 435                 }
 436
 437                 /* Allow an aux regulator */
 438                 reg = regulator_get(host->dev, "vmmc_aux");
 439                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 440
 441                 /* For eMMC do not power off when not in sleep state */
 442                 if (mmc_slot(host).no_regulator_off_init)
 443                         return 0;
 444                 /*
 445                 * UGLY HACK:  workaround regulator framework bugs.
 446                 * When the bootloader leaves a supply active, it's
 447                 * initialized with zero usecount ... and we can't
 448                 * disable it without first enabling it.  Until the
 449                 * framework is fixed, we need a workaround like this
 450                 * (which is safe for MMC, but not in general).
 451                 */
 452                 if (regulator_is_enabled(host->vcc) > 0 ||
 453                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 454                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
 455
 456                         mmc_slot(host).set_power(host->dev, host->slot_id,
 457                                                  1, vdd);
 458                         mmc_slot(host).set_power(host->dev, host->slot_id,
 459                                                  0, 0);
 460                 }
 461         }
 462
 463         return 0;
 464
 465 err:
 466         mmc_slot(host).set_power = NULL;
 467         mmc_slot(host).set_sleep = NULL;
 468         return ret;
 469 }
 470
 471 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 472 {
 473         regulator_put(host->vcc);
 474         regulator_put(host->vcc_aux);
 475         mmc_slot(host).set_power = NULL;
 476         mmc_slot(host).set_sleep = NULL;
 477 }
 478
 479 static inline int omap_hsmmc_have_reg(void)
 480 {
 481         return 1;
 482 }
 483
 484 #else
 485
 486 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 487 {
 488         return -EINVAL;
 489 }
 490
 491 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 492 {
 493 }
 494
 495 static inline int omap_hsmmc_have_reg(void)
 496 {
 497         return 0;
 498 }
 499
 500 #endif
 501
 502 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 503 {
 504         int ret;
 505
 506         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 507                 if (pdata->slots[0].cover)
 508                         pdata->slots[0].get_cover_state =
 509                                         omap_hsmmc_get_cover_state;
 510                 else
 511                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 512                 pdata->slots[0].card_detect_irq =
 513                                 gpio_to_irq(pdata->slots[0].switch_pin);
 514                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 515                 if (ret)
 516                         return ret;
 517                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 518                 if (ret)
 519                         goto err_free_sp;
 520         } else
 521                 pdata->slots[0].switch_pin = -EINVAL;
 522
 523         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 524                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 525                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 526                 if (ret)
 527                         goto err_free_cd;
 528                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 529                 if (ret)
 530                         goto err_free_wp;
 531         } else
 532                 pdata->slots[0].gpio_wp = -EINVAL;
 533
 534         return 0;
 535
 536 err_free_wp:
 537         gpio_free(pdata->slots[0].gpio_wp);
 538 err_free_cd:
 539         if (gpio_is_valid(pdata->slots[0].switch_pin))
 540 err_free_sp:
 541                 gpio_free(pdata->slots[0].switch_pin);
 542         return ret;
 543 }
 544
 545 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 546 {
 547         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 548                 gpio_free(pdata->slots[0].gpio_wp);
 549         if (gpio_is_valid(pdata->slots[0].switch_pin))
 550                 gpio_free(pdata->slots[0].switch_pin);
 551 }
 552
 553 /*
 554  * Start clock to the card
 555  */
 556 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 557 {
 558         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 559                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 560 }
 561
 562 /*
 563  * Stop clock to the card
 564  */
 565 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 566 {
 567         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 568                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 569         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 570                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 571 }
 572
 573 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 574                                   struct mmc_command *cmd)
 575 {
 576         unsigned int irq_mask;
 577
 578         if (host->use_dma)
 579                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
 580         else
 581                 irq_mask = INT_EN_MASK;
 582
 583         /* Disable timeout for erases */
 584         if (cmd->opcode == MMC_ERASE)
 585                 irq_mask &= ~DTO_ENABLE;
 586
 587         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 588         OMAP_HSMMC_WRITE(host->base, ISE, host->use_dma ? irq_mask : 0);
 589         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 590 }
 591
 592 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 593 {
 594         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 595         OMAP_HSMMC_WRITE(host->base, IE, 0);
 596         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 597 }
 598
 599 /* Calculate divisor for the given clock frequency */
 600 static u16 calc_divisor(struct mmc_ios *ios)
 601 {
 602         u16 dsor = 0;
 603
 604         if (ios->clock) {
 605                 dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
 606                 if (dsor > 250)
 607                         dsor = 250;
 608         }
 609
 610         return dsor;
 611 }
 612
 613 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 614 {
 615         struct mmc_ios *ios = &host->mmc->ios;
 616         unsigned long regval;
 617         unsigned long timeout;
 618
 619         dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 620
 621         omap_hsmmc_stop_clock(host);
 622
 623         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 624         regval = regval & ~(CLKD_MASK | DTO_MASK);
 625         regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
 626         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 627         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 628                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 629
 630         /* Wait till the ICS bit is set */
 631         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 632         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 633                 && time_before(jiffies, timeout))
 634                 cpu_relax();
 635
 636         omap_hsmmc_start_clock(host);
 637 }
 638
 639 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 640 {
 641         struct mmc_ios *ios = &host->mmc->ios;
 642         u32 con;
 643
 644         con = OMAP_HSMMC_READ(host->base, CON);
 645         switch (ios->bus_width) {
 646         case MMC_BUS_WIDTH_8:
 647                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 648                 break;
 649         case MMC_BUS_WIDTH_4:
 650                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 651                 OMAP_HSMMC_WRITE(host->base, HCTL,
 652                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 653                 break;
 654         case MMC_BUS_WIDTH_1:
 655                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 656                 OMAP_HSMMC_WRITE(host->base, HCTL,
 657                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 658                 break;
 659         }
 660 }
 661
 662 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 663 {
 664         struct mmc_ios *ios = &host->mmc->ios;
 665         u32 con;
 666
 667         con = OMAP_HSMMC_READ(host->base, CON);
 668         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 669                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 670         else
 671                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 672 }
 673
 674 #ifdef CONFIG_PM
 675
 676 /*
 677  * Restore the MMC host context, if it was lost as result of a
 678  * power state change.
 679  */
 680 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 681 {
 682         struct mmc_ios *ios = &host->mmc->ios;
 683         struct omap_mmc_platform_data *pdata = host->pdata;
 684         int context_loss = 0;
 685         u32 hctl, capa;
 686         unsigned long timeout;
 687
 688         if (pdata->get_context_loss_count) {
 689                 context_loss = pdata->get_context_loss_count(host->dev);
 690                 if (context_loss < 0)
 691                         return 1;
 692         }
 693
 694         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 695                 context_loss == host->context_loss ? "not " : "");
 696         if (host->context_loss == context_loss)
 697                 return 1;
 698
 699         /* Wait for hardware reset */
 700         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 701         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 702                 && time_before(jiffies, timeout))
 703                 ;
 704
 705         /* Do software reset */
 706         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 707         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 708         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 709                 && time_before(jiffies, timeout))
 710                 ;
 711
 712         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 713                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 714
 715         if (host->id == OMAP_MMC1_DEVID) {
 716                 if (host->power_mode != MMC_POWER_OFF &&
 717                     (1 << ios->vdd) <= MMC_VDD_23_24)
 718                         hctl = SDVS18;
 719                 else
 720                         hctl = SDVS30;
 721                 capa = VS30 | VS18;
 722         } else {
 723                 hctl = SDVS18;
 724                 capa = VS18;
 725         }
 726
 727         OMAP_HSMMC_WRITE(host->base, HCTL,
 728                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 729
 730         OMAP_HSMMC_WRITE(host->base, CAPA,
 731                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 732
 733         OMAP_HSMMC_WRITE(host->base, HCTL,
 734                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 735
 736         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 737         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 738                 && time_before(jiffies, timeout))
 739                 ;
 740
 741         omap_hsmmc_disable_irq(host);
 742
 743         /* Do not initialize card-specific things if the power is off */
 744         if (host->power_mode == MMC_POWER_OFF)
 745                 goto out;
 746
 747         omap_hsmmc_set_bus_width(host);
 748
 749         omap_hsmmc_set_clock(host);
 750
 751         omap_hsmmc_set_bus_mode(host);
 752
 753 out:
 754         host->context_loss = context_loss;
 755
 756         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 757         return 0;
 758 }
 759
 760 /*
 761  * Save the MMC host context (store the number of power state changes so far).
 762  */
 763 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 764 {
 765         struct omap_mmc_platform_data *pdata = host->pdata;
 766         int context_loss;
 767
 768         if (pdata->get_context_loss_count) {
 769                 context_loss = pdata->get_context_loss_count(host->dev);
 770                 if (context_loss < 0)
 771                         return;
 772                 host->context_loss = context_loss;
 773         }
 774 }
 775
 776 #else
 777
 778 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 779 {
 780         return 0;
 781 }
 782
 783 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 784 {
 785 }
 786
 787 #endif
 788
 789 /*
 790  * Send init stream sequence to card
 791  * before sending IDLE command
 792  */
 793 static void send_init_stream(struct omap_hsmmc_host *host)
 794 {
 795         int reg = 0;
 796         unsigned long timeout;
 797
 798         if (host->protect_card)
 799                 return;
 800
 801         disable_irq(host->irq);
 802
 803         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 804         OMAP_HSMMC_WRITE(host->base, CON,
 805                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 806         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 807
 808         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 809         while ((reg != CC) && time_before(jiffies, timeout))
 810                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 811
 812         OMAP_HSMMC_WRITE(host->base, CON,
 813                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 814
 815         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 816         OMAP_HSMMC_READ(host->base, STAT);
 817
 818         enable_irq(host->irq);
 819 }
 820
 821 static inline
 822 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 823 {
 824         int r = 1;
 825
 826         if (mmc_slot(host).get_cover_state)
 827                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 828         return r;
 829 }
 830
 831 static ssize_t
 832 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 833                            char *buf)
 834 {
 835         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 836         struct omap_hsmmc_host *host = mmc_priv(mmc);
 837
 838         return sprintf(buf, "%s\n",
 839                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 840 }
 841
 842 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 843
 844 static ssize_t
 845 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 846                         char *buf)
 847 {
 848         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 849         struct omap_hsmmc_host *host = mmc_priv(mmc);
 850
 851         return sprintf(buf, "%s\n", mmc_slot(host).name);
 852 }
 853
 854 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 855
 856 /* for hosts with 35xx erratum 2.1.1.128 */
 857 static ssize_t
 858 omap_hsmmc_show_unsafe_read(struct device *dev, struct device_attribute *attr,
 859                         char *buf)
 860 {
 861         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 862         int val = 0;
 863
 864         if (!(mmc->caps2 & MMC_CAP2_NO_MULTI_READ)) {
 865                 val = 1;
 866                 if (mmc->f_max == OMAP_MMC_MAX_CLOCK)
 867                         val = 2;
 868         }
 869
 870         return sprintf(buf, "%d\n", val);
 871 }
 872
 873 static ssize_t
 874 omap_hsmmc_set_unsafe_read(struct device *dev, struct device_attribute *attr,
 875                 const char *buf, size_t count)
 876 {
 877         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 878         unsigned long val;
 879         int ret;
 880
 881         ret = strict_strtoul(buf, 0, &val);
 882         if (ret)
 883                 return -EINVAL;
 884
 885         switch (val) {
 886         case 0:
 887                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
 888                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
 889                 break;
 890         case 1:
 891                 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
 892                 mmc->f_max = 32000000;
 893                 break;
 894         case 2:
 895                 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
 896                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
 897                 break;
 898         }
 899
 900         return count;
 901 }
 902 static DEVICE_ATTR(unsafe_read, S_IWUSR | S_IRUGO,
 903         omap_hsmmc_show_unsafe_read, omap_hsmmc_set_unsafe_read);
 904
 905 /*
 906  * Configure the response type and send the cmd.
 907  */
 908 static void
 909 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 910         struct mmc_data *data)
 911 {
 912         int cmdreg = 0, resptype = 0, cmdtype = 0;
 913
 914         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 915                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 916         host->cmd = cmd;
 917
 918         omap_hsmmc_enable_irq(host, cmd);
 919
 920         host->response_busy = 0;
 921         if (cmd->flags & MMC_RSP_PRESENT) {
 922                 if (cmd->flags & MMC_RSP_136)
 923                         resptype = 1;
 924                 else if (cmd->flags & MMC_RSP_BUSY) {
 925                         resptype = 3;
 926                         host->response_busy = 1;
 927                 } else
 928                         resptype = 2;
 929         }
 930
 931         /*
 932          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 933          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 934          * a val of 0x3, rest 0x0.
 935          */
 936         if (cmd == host->mrq->stop)
 937                 cmdtype = 0x3;
 938
 939         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 940
 941         if (data) {
 942                 cmdreg |= DP_SELECT | MSBS | BCE;
 943                 if (data->flags & MMC_DATA_READ)
 944                         cmdreg |= DDIR;
 945                 else
 946                         cmdreg &= ~(DDIR);
 947         }
 948
 949         if (host->use_dma)
 950                 cmdreg |= DMA_EN;
 951
 952         host->req_in_progress = 1;
 953
 954         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 955         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 956 }
 957
 958 static int
 959 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 960 {
 961         if (data->flags & MMC_DATA_WRITE)
 962                 return DMA_TO_DEVICE;
 963         else
 964                 return DMA_FROM_DEVICE;
 965 }
 966
 967 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 968 {
 969         int dma_ch;
 970
 971         spin_lock(&host->irq_lock);
 972         host->req_in_progress = 0;
 973         dma_ch = host->dma_ch;
 974         spin_unlock(&host->irq_lock);
 975
 976         omap_hsmmc_disable_irq(host);
 977         /* Do not complete the request if DMA is still in progress */
 978         if (mrq->data && host->use_dma && dma_ch != -1)
 979                 return;
 980         host->mrq = NULL;
 981         mmc_request_done(host->mmc, mrq);
 982 }
 983
 984 /*
 985  * Notify the transfer complete to MMC core
 986  */
 987 static void
 988 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 989 {
 990         if (!data) {
 991                 struct mmc_request *mrq = host->mrq;
 992
 993                 /* TC before CC from CMD6 - don't know why, but it happens */
 994                 if (host->cmd && host->cmd->opcode == 6 &&
 995                     host->response_busy) {
 996                         host->response_busy = 0;
 997                         return;
 998                 }
 999
1000                 omap_hsmmc_request_done(host, mrq);
1001                 return;
1002         }
1003
1004         host->data = NULL;
1005
1006         if (!data->error)
1007                 data->bytes_xfered += data->blocks * (data->blksz);
1008         else
1009                 data->bytes_xfered = 0;
1010
1011         if (!data->stop) {
1012                 omap_hsmmc_request_done(host, data->mrq);
1013                 return;
1014         }
1015         omap_hsmmc_start_command(host, data->stop, NULL);
1016 }
1017
1018 /*
1019  * Notify the core about command completion
1020  */
1021 static void
1022 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
1023 {
1024         host->cmd = NULL;
1025
1026         if (cmd->flags & MMC_RSP_PRESENT) {
1027                 if (cmd->flags & MMC_RSP_136) {
1028                         /* response type 2 */
1029                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
1030                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
1031                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
1032                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
1033                 } else {
1034                         /* response types 1, 1b, 3, 4, 5, 6 */
1035                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
1036                 }
1037         }
1038         if ((host->data == NULL && !host->response_busy) || cmd->error)
1039                 omap_hsmmc_request_done(host, cmd->mrq);
1040 }
1041
1042 static void omap_hsmmc_free_dma(struct omap_hsmmc_host *host)
1043 {
1044         int dma_ch;
1045
1046         dma_ch = xchg(&host->dma_ch_tx, -1);
1047         if (dma_ch != -1)
1048                 omap_free_dma(dma_ch);
1049
1050         dma_ch = xchg(&host->dma_ch_rx, -1);
1051         if (dma_ch != -1)
1052                 omap_free_dma(dma_ch);
1053 }
1054
1055 /*
1056  * DMA clean up for command errors
1057  */
1058 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1059 {
1060         int dma_ch;
1061
1062         host->data->error = errno;
1063
1064         spin_lock(&host->irq_lock);
1065         dma_ch = host->dma_ch;
1066         host->dma_ch = -1;
1067         spin_unlock(&host->irq_lock);
1068
1069         if (host->use_dma && dma_ch != -1) {
1070                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
1071                         host->data->sg_len,
1072                         omap_hsmmc_get_dma_dir(host, host->data));
1073                 host->data->host_cookie = 0;
1074         }
1075         omap_hsmmc_free_dma(host);
1076         host->data = NULL;
1077 }
1078
1079 /*
1080  * Readable error output
1081  */
1082 #ifdef CONFIG_MMC_DEBUG
1083 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1084 {
1085         /* --- means reserved bit without definition at documentation */
1086         static const char *omap_hsmmc_status_bits[] = {
1087                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1088                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1089                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1090                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1091         };
1092         char res[256];
1093         char *buf = res;
1094         int len, i;
1095
1096         len = sprintf(buf, "MMC IRQ 0x%x :", status);
1097         buf += len;
1098
1099         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1100                 if (status & (1 << i)) {
1101                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1102                         buf += len;
1103                 }
1104
1105         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1106 }
1107 #else
1108 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1109                                              u32 status)
1110 {
1111 }
1112 #endif  /* CONFIG_MMC_DEBUG */
1113
1114 /*
1115  * MMC controller internal state machines reset
1116  *
1117  * Used to reset command or data internal state machines, using respectively
1118  *  SRC or SRD bit of SYSCTL register
1119  * Can be called from interrupt context
1120  */
1121 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1122                                                    unsigned long bit)
1123 {
1124         unsigned long i = 0;
1125         unsigned long limit = (loops_per_jiffy *
1126                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
1127
1128         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1129                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1130
1131         /*
1132          * OMAP4 ES2 and greater has an updated reset logic.
1133          * Monitor a 0->1 transition first
1134          */
1135         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1136                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1137                                         && (i++ < limit))
1138                         cpu_relax();
1139         }
1140         i = 0;
1141
1142         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1143                 (i++ < limit))
1144                 cpu_relax();
1145
1146         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1147                 dev_err(mmc_dev(host->mmc),
1148                         "Timeout waiting on controller reset in %s\n",
1149                         __func__);
1150 }
1151
1152 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1153 {
1154         struct mmc_data *data;
1155         int end_cmd = 0, end_trans = 0;
1156
1157         if (unlikely(!host->req_in_progress)) {
1158                 OMAP_HSMMC_WRITE(host->base, STAT, status);
1159                 return;
1160         }
1161
1162         data = host->data;
1163         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1164
1165         if (unlikely(status & ERR)) {
1166                 omap_hsmmc_dbg_report_irq(host, status);
1167                 if ((status & CMD_TIMEOUT) ||
1168                         (status & CMD_CRC)) {
1169                         if (host->cmd) {
1170                                 if (status & CMD_TIMEOUT) {
1171                                         omap_hsmmc_reset_controller_fsm(host,
1172                                                                         SRC);
1173                                         host->cmd->error = -ETIMEDOUT;
1174                                 } else {
1175                                         host->cmd->error = -EILSEQ;
1176                                 }
1177                                 end_cmd = 1;
1178                         }
1179                         if (host->data || host->response_busy) {
1180                                 if (host->data)
1181                                         omap_hsmmc_dma_cleanup(host,
1182                                                                 -ETIMEDOUT);
1183                                 host->response_busy = 0;
1184                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1185                         }
1186                 }
1187                 if ((status & DATA_TIMEOUT) ||
1188                         (status & DATA_CRC)) {
1189                         if (host->data || host->response_busy) {
1190                                 int err = (status & DATA_TIMEOUT) ?
1191                                                 -ETIMEDOUT : -EILSEQ;
1192
1193                                 if (host->data)
1194                                         omap_hsmmc_dma_cleanup(host, err);
1195                                 else
1196                                         host->mrq->cmd->error = err;
1197                                 host->response_busy = 0;
1198                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1199                                 end_trans = 1;
1200                         }
1201                 }
1202                 if (status & CARD_ERR) {
1203                         dev_dbg(mmc_dev(host->mmc),
1204                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1205                         if (host->cmd)
1206                                 end_cmd = 1;
1207                         if (host->data)
1208                                 end_trans = 1;
1209                 }
1210         }
1211
1212         OMAP_HSMMC_WRITE(host->base, STAT, status);
1213
1214         if (end_cmd || ((status & CC) && host->cmd))
1215                 omap_hsmmc_cmd_done(host, host->cmd);
1216         if ((end_trans || (status & TC)) && host->mrq)
1217                 omap_hsmmc_xfer_done(host, data);
1218 }
1219
1220 /*
1221  * MMC controller IRQ handler
1222  */
1223 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1224 {
1225         struct omap_hsmmc_host *host = dev_id;
1226         int status;
1227
1228         status = OMAP_HSMMC_READ(host->base, STAT);
1229         do {
1230                 omap_hsmmc_do_irq(host, status);
1231                 /* Flush posted write */
1232                 status = OMAP_HSMMC_READ(host->base, STAT);
1233         } while (status & INT_EN_MASK);
1234
1235         return IRQ_HANDLED;
1236 }
1237
1238 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1239 {
1240         unsigned long i;
1241
1242         OMAP_HSMMC_WRITE(host->base, HCTL,
1243                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1244         for (i = 0; i < loops_per_jiffy; i++) {
1245                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1246                         break;
1247                 cpu_relax();
1248         }
1249 }
1250
1251 /*
1252  * Switch MMC interface voltage ... only relevant for MMC1.
1253  *
1254  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1255  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1256  * Some chips, like eMMC ones, use internal transceivers.
1257  */
1258 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1259 {
1260         u32 reg_val = 0;
1261         int ret;
1262
1263         /* Disable the clocks */
1264         pm_runtime_put_sync(host->dev);
1265         if (host->got_dbclk)
1266                 clk_disable(host->dbclk);
1267
1268         /* Turn the power off */
1269         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1270
1271         /* Turn the power ON with given VDD 1.8 or 3.0v */
1272         if (!ret)
1273                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1274                                                vdd);
1275         pm_runtime_get_sync(host->dev);
1276         if (host->got_dbclk)
1277                 clk_enable(host->dbclk);
1278
1279         if (ret != 0)
1280                 goto err;
1281
1282         OMAP_HSMMC_WRITE(host->base, HCTL,
1283                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1284         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1285
1286         /*
1287          * If a MMC dual voltage card is detected, the set_ios fn calls
1288          * this fn with VDD bit set for 1.8V. Upon card removal from the
1289          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1290          *
1291          * Cope with a bit of slop in the range ... per data sheets:
1292          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1293          *    but recommended values are 1.71V to 1.89V
1294          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1295          *    but recommended values are 2.7V to 3.3V
1296          *
1297          * Board setup code shouldn't permit anything very out-of-range.
1298          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1299          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1300          */
1301         if ((1 << vdd) <= MMC_VDD_23_24)
1302                 reg_val |= SDVS18;
1303         else
1304                 reg_val |= SDVS30;
1305
1306         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1307         set_sd_bus_power(host);
1308
1309         return 0;
1310 err:
1311         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1312         return ret;
1313 }
1314
1315 /* Protect the card while the cover is open */
1316 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1317 {
1318         if (!mmc_slot(host).get_cover_state)
1319                 return;
1320
1321         host->reqs_blocked = 0;
1322         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1323                 if (host->protect_card) {
1324                         pr_info("%s: cover is closed, "
1325                                          "card is now accessible\n",
1326                                          mmc_hostname(host->mmc));
1327                         host->protect_card = 0;
1328                 }
1329         } else {
1330                 if (!host->protect_card) {
1331                         pr_info("%s: cover is open, "
1332                                          "card is now inaccessible\n",
1333                                          mmc_hostname(host->mmc));
1334                         host->protect_card = 1;
1335                 }
1336         }
1337 }
1338
1339 /*
1340  * irq handler to notify the core about card insertion/removal
1341  */
1342 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1343 {
1344         struct omap_hsmmc_host *host = dev_id;
1345         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1346         int carddetect;
1347
1348         if (host->suspended)
1349                 return IRQ_HANDLED;
1350
1351         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1352
1353         if (slot->card_detect)
1354                 carddetect = slot->card_detect(host->dev, host->slot_id);
1355         else {
1356                 omap_hsmmc_protect_card(host);
1357                 carddetect = -ENOSYS;
1358         }
1359
1360         if (carddetect)
1361                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1362         else
1363                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1364         return IRQ_HANDLED;
1365 }
1366
1367 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1368                                      struct mmc_data *data)
1369 {
1370         int sync_dev;
1371
1372         if (data->flags & MMC_DATA_WRITE)
1373                 sync_dev = host->dma_line_tx;
1374         else
1375                 sync_dev = host->dma_line_rx;
1376         return sync_dev;
1377 }
1378
1379 static void omap_hsmmc_config_dma_params_once(struct omap_hsmmc_host *host,
1380                                               struct mmc_data *data,
1381                                               int dma_ch)
1382 {
1383         /* pandora hack: only benefits wifi, so only set there, just in case */
1384         if (host->id != OMAP_MMC3_DEVID)
1385                 return;
1386
1387         if (data->flags & MMC_DATA_WRITE) {
1388                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_16);
1389                 omap_set_dma_src_data_pack(dma_ch, 1);
1390         } else {
1391                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_16);
1392                 omap_set_dma_dest_data_pack(dma_ch, 1);
1393         }
1394 }
1395
1396 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1397                                        struct mmc_data *data,
1398                                        struct scatterlist *sgl)
1399 {
1400         int blksz, nblk, dma_ch, sync;
1401
1402         dma_ch = host->dma_ch;
1403         if (data->flags & MMC_DATA_WRITE) {
1404                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1405                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1406                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1407                         sg_dma_address(sgl), 0, 0);
1408                 sync = OMAP_DMA_DST_SYNC;
1409         } else {
1410                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1411                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1412                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1413                         sg_dma_address(sgl), 0, 0);
1414                 sync = OMAP_DMA_SRC_SYNC;
1415         }
1416
1417         blksz = host->data->blksz;
1418         nblk = sg_dma_len(sgl) / blksz;
1419
1420         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1421                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1422                         omap_hsmmc_get_dma_sync_dev(host, data), sync);
1423
1424         omap_start_dma(dma_ch);
1425 }
1426
1427 /*
1428  * DMA call back function
1429  */
1430 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1431 {
1432         struct omap_hsmmc_host *host = cb_data;
1433         struct mmc_data *data;
1434         int req_in_progress;
1435
1436         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1437                 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1438                         ch_status);
1439                 return;
1440         }
1441
1442         spin_lock(&host->irq_lock);
1443         if (host->dma_ch < 0) {
1444                 spin_unlock(&host->irq_lock);
1445                 return;
1446         }
1447
1448         data = host->mrq->data;
1449         host->dma_sg_idx++;
1450         if (host->dma_sg_idx < host->dma_len) {
1451                 /* Fire up the next transfer. */
1452                 omap_hsmmc_config_dma_params(host, data,
1453                                            data->sg + host->dma_sg_idx);
1454                 spin_unlock(&host->irq_lock);
1455                 return;
1456         }
1457
1458         if (!data->host_cookie)
1459                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1460                              omap_hsmmc_get_dma_dir(host, data));
1461
1462         req_in_progress = host->req_in_progress;
1463         host->dma_ch = -1;
1464         spin_unlock(&host->irq_lock);
1465
1466         /* If DMA has finished after TC, complete the request */
1467         if (!req_in_progress) {
1468                 struct mmc_request *mrq = host->mrq;
1469
1470                 host->mrq = NULL;
1471                 mmc_request_done(host->mmc, mrq);
1472         }
1473 }
1474
1475 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1476                                        struct mmc_data *data,
1477                                        struct omap_hsmmc_next *next)
1478 {
1479         int dma_len;
1480
1481         if (unlikely(!next && data->host_cookie &&
1482             data->host_cookie != host->next_data.cookie)) {
1483                 pr_warning("[%s] invalid cookie: data->host_cookie %d"
1484                        " host->next_data.cookie %d\n",
1485                        __func__, data->host_cookie, host->next_data.cookie);
1486                 data->host_cookie = 0;
1487         }
1488
1489         /* Check if next job is already prepared */
1490         if (next ||
1491             (!next && data->host_cookie != host->next_data.cookie)) {
1492                 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1493                                      data->sg_len,
1494                                      omap_hsmmc_get_dma_dir(host, data));
1495
1496         } else {
1497                 dma_len = host->next_data.dma_len;
1498                 host->next_data.dma_len = 0;
1499         }
1500
1501
1502         if (unlikely(dma_len == 0))
1503                 return -EINVAL;
1504
1505         if (next) {
1506                 next->dma_len = dma_len;
1507                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1508         } else
1509                 host->dma_len = dma_len;
1510
1511         return 0;
1512 }
1513
1514 /*
1515  * Routine to configure and start DMA for the MMC card
1516  */
1517 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1518                                         struct mmc_request *req)
1519 {
1520         int dma_ch = 0, ret = 0, i;
1521         struct mmc_data *data = req->data;
1522
1523         /* Sanity check: all the SG entries must be aligned by block size. */
1524         for (i = 0; i < data->sg_len; i++) {
1525                 struct scatterlist *sgl;
1526
1527                 sgl = data->sg + i;
1528                 if (unlikely(sgl->length % data->blksz))
1529                         return -EINVAL;
1530         }
1531         if (unlikely((data->blksz % 4) != 0))
1532                 /* REVISIT: The MMC buffer increments only when MSB is written.
1533                  * Return error for blksz which is non multiple of four.
1534                  */
1535                 return -EINVAL;
1536
1537         BUG_ON(host->dma_ch != -1);
1538
1539         if (data->flags & MMC_DATA_WRITE)
1540                 dma_ch = host->dma_ch_tx;
1541         else
1542                 dma_ch = host->dma_ch_rx;
1543
1544         if (dma_ch == -1) {
1545                 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1546                                        "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1547                 if (unlikely(ret != 0)) {
1548                         dev_err(mmc_dev(host->mmc),
1549                                 "%s: omap_request_dma() failed with %d\n",
1550                                 mmc_hostname(host->mmc), ret);
1551                         return ret;
1552                 }
1553
1554                 omap_hsmmc_config_dma_params_once(host, data, dma_ch);
1555
1556                 if (data->flags & MMC_DATA_WRITE)
1557                         host->dma_ch_tx = dma_ch;
1558                 else
1559                         host->dma_ch_rx = dma_ch;
1560         }
1561
1562         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1563         if (unlikely(ret))
1564                 return ret;
1565
1566         host->dma_ch = dma_ch;
1567         host->dma_sg_idx = 0;
1568
1569         omap_hsmmc_config_dma_params(host, data, data->sg);
1570
1571         return 0;
1572 }
1573
1574 /* pandora wifi small transfer hack */
1575 static int check_mmc3_dma_hack(struct omap_hsmmc_host *host,
1576                                struct mmc_request *req)
1577 {
1578         if (req->data != NULL && req->data->sg_len == 1
1579             && req->data->sg->length <= 16)
1580                 return 0;
1581         else
1582                 return 1;
1583 }
1584
1585 /*
1586  * Configure block length for MMC/SD cards and initiate the transfer.
1587  */
1588 static int
1589 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1590 {
1591         int ret;
1592         host->data = req->data;
1593
1594         if (req->data == NULL) {
1595                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1596                 return 0;
1597         }
1598
1599         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1600                                         | (req->data->blocks << 16));
1601
1602         if (host->use_dma) {
1603                 ret = omap_hsmmc_start_dma_transfer(host, req);
1604                 if (ret != 0) {
1605                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1606                         return ret;
1607                 }
1608         }
1609         return 0;
1610 }
1611
1612 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1613                                 int err)
1614 {
1615         struct omap_hsmmc_host *host = mmc_priv(mmc);
1616         struct mmc_data *data = mrq->data;
1617
1618         if (host->use_dma) {
1619                 if (data->host_cookie)
1620                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1621                                      data->sg_len,
1622                                      omap_hsmmc_get_dma_dir(host, data));
1623                 data->host_cookie = 0;
1624         }
1625 }
1626
1627 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1628                                bool is_first_req)
1629 {
1630         struct omap_hsmmc_host *host = mmc_priv(mmc);
1631         int use_dma = host->use_dma;
1632
1633         if (mrq->data->host_cookie) {
1634                 mrq->data->host_cookie = 0;
1635                 return ;
1636         }
1637
1638         if (host->id == OMAP_MMC3_DEVID)
1639                 use_dma = check_mmc3_dma_hack(host, mrq);
1640         if (use_dma)
1641                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1642                                                 &host->next_data))
1643                         mrq->data->host_cookie = 0;
1644 }
1645
1646 #define BWR (1 << 4)
1647 #define BRR (1 << 5)
1648
1649 static noinline void omap_hsmmc_request_do_pio(struct mmc_host *mmc,
1650         struct mmc_request *req)
1651 {
1652         struct omap_hsmmc_host *host = mmc_priv(mmc);
1653         u32 *data = sg_virt(req->data->sg);
1654         u32 len = req->data->sg->length;
1655         int stat;
1656         int i;
1657
1658         for (i = 0; i < 10000000; i++) {
1659                 stat = OMAP_HSMMC_READ(host->base, STAT);
1660                 if (stat == 0)
1661                         continue;
1662
1663                 //dev_err(mmc_dev(host->mmc), "stat %x, l %d\n", stat, i);
1664
1665                 if (stat & (DATA_TIMEOUT | DATA_CRC))
1666                         omap_hsmmc_reset_controller_fsm(host, SRD);
1667
1668                 if (stat & ERR) {
1669                         req->cmd->error =
1670                         req->data->error = -EINVAL; // ?
1671                         omap_hsmmc_xfer_done(host, host->data);
1672                         return;
1673                 }
1674
1675                 if (req->data->flags & MMC_DATA_WRITE) {
1676                         while (len > 0 && (stat & BWR)) {
1677                                 OMAP_HSMMC_WRITE(host->base, DATA, *data++);
1678                                 len -= 4;
1679                         }
1680                 } else {
1681                         while (len > 0 && (stat & BRR)) {
1682                                 *data++ = OMAP_HSMMC_READ(host->base, DATA);
1683                                 len -= 4;
1684                         }
1685                 }
1686
1687                 if ((stat & CC) && host->cmd)
1688                         omap_hsmmc_cmd_done(host, host->cmd);
1689                 if ((stat & TC) && host->mrq) {
1690                         omap_hsmmc_xfer_done(host, host->data);
1691                         break;
1692                 }
1693         }
1694
1695         if (len > 0) {
1696                 req->cmd->error =
1697                 req->data->error = -ETIMEDOUT;
1698                 omap_hsmmc_xfer_done(host, req->data);
1699         }
1700 }
1701
1702 /*
1703  * Request function. for read/write operation
1704  */
1705 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1706 {
1707         struct omap_hsmmc_host *host = mmc_priv(mmc);
1708         int err;
1709
1710         BUG_ON(host->req_in_progress);
1711         BUG_ON(host->dma_ch != -1);
1712         if (unlikely(host->protect_card)) {
1713                 if (host->reqs_blocked < 3) {
1714                         /*
1715                          * Ensure the controller is left in a consistent
1716                          * state by resetting the command and data state
1717                          * machines.
1718                          */
1719                         omap_hsmmc_reset_controller_fsm(host, SRD);
1720                         omap_hsmmc_reset_controller_fsm(host, SRC);
1721                         host->reqs_blocked += 1;
1722                 }
1723                 req->cmd->error = -EBADF;
1724                 if (req->data)
1725                         req->data->error = -EBADF;
1726                 req->cmd->retries = 0;
1727                 mmc_request_done(mmc, req);
1728                 return;
1729         } else if (host->reqs_blocked)
1730                 host->reqs_blocked = 0;
1731
1732         /* pandora wifi hack... */
1733         if (host->id == OMAP_MMC3_DEVID)
1734                 host->use_dma = check_mmc3_dma_hack(host, req);
1735
1736         WARN_ON(host->mrq != NULL);
1737         host->mrq = req;
1738         err = omap_hsmmc_prepare_data(host, req);
1739         if (unlikely(err)) {
1740                 req->cmd->error = err;
1741                 if (req->data)
1742                         req->data->error = err;
1743                 host->mrq = NULL;
1744                 mmc_request_done(mmc, req);
1745                 return;
1746         }
1747
1748         omap_hsmmc_start_command(host, req->cmd, req->data);
1749
1750         if (host->use_dma == 0)
1751                 omap_hsmmc_request_do_pio(mmc, req);
1752 }
1753
1754 /* Routine to configure clock values. Exposed API to core */
1755 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1756 {
1757         struct omap_hsmmc_host *host = mmc_priv(mmc);
1758         int do_send_init_stream = 0;
1759
1760         pm_runtime_get_sync(host->dev);
1761
1762         if (ios->power_mode != host->power_mode) {
1763                 switch (ios->power_mode) {
1764                 case MMC_POWER_OFF:
1765                         mmc_slot(host).set_power(host->dev, host->slot_id,
1766                                                  0, 0);
1767                         host->vdd = 0;
1768                         break;
1769                 case MMC_POWER_UP:
1770                         mmc_slot(host).set_power(host->dev, host->slot_id,
1771                                                  1, ios->vdd);
1772                         host->vdd = ios->vdd;
1773                         break;
1774                 case MMC_POWER_ON:
1775                         do_send_init_stream = 1;
1776                         break;
1777                 }
1778                 host->power_mode = ios->power_mode;
1779         }
1780
1781         /* FIXME: set registers based only on changes to ios */
1782
1783         omap_hsmmc_set_bus_width(host);
1784
1785         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1786                 /* Only MMC1 can interface at 3V without some flavor
1787                  * of external transceiver; but they all handle 1.8V.
1788                  */
1789                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1790                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1791                                 /*
1792                                  * The mmc_select_voltage fn of the core does
1793                                  * not seem to set the power_mode to
1794                                  * MMC_POWER_UP upon recalculating the voltage.
1795                                  * vdd 1.8v.
1796                                  */
1797                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1798                                 dev_dbg(mmc_dev(host->mmc),
1799                                                 "Switch operation failed\n");
1800                 }
1801         }
1802
1803         omap_hsmmc_set_clock(host);
1804
1805         if (do_send_init_stream)
1806                 send_init_stream(host);
1807
1808         omap_hsmmc_set_bus_mode(host);
1809
1810         pm_runtime_put_autosuspend(host->dev);
1811 }
1812
1813 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1814 {
1815         struct omap_hsmmc_host *host = mmc_priv(mmc);
1816
1817         if (!mmc_slot(host).card_detect)
1818                 return -ENOSYS;
1819         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1820 }
1821
1822 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1823 {
1824         struct omap_hsmmc_host *host = mmc_priv(mmc);
1825
1826         if (!mmc_slot(host).get_ro)
1827                 return -ENOSYS;
1828         return mmc_slot(host).get_ro(host->dev, 0);
1829 }
1830
1831 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1832 {
1833         struct omap_hsmmc_host *host = mmc_priv(mmc);
1834
1835         if (mmc_slot(host).init_card)
1836                 mmc_slot(host).init_card(card);
1837 }
1838
1839 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1840 {
1841         u32 hctl, capa, value;
1842
1843         /* Only MMC1 supports 3.0V */
1844         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1845                 hctl = SDVS30;
1846                 capa = VS30 | VS18;
1847         } else {
1848                 hctl = SDVS18;
1849                 capa = VS18;
1850         }
1851
1852         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1853         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1854
1855         value = OMAP_HSMMC_READ(host->base, CAPA);
1856         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1857
1858         /* Set the controller to AUTO IDLE mode */
1859         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1860         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1861
1862         /* Set SD bus power bit */
1863         set_sd_bus_power(host);
1864 }
1865
1866 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1867 {
1868         struct omap_hsmmc_host *host = mmc_priv(mmc);
1869
1870         pm_runtime_get_sync(host->dev);
1871
1872         return 0;
1873 }
1874
1875 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1876 {
1877         struct omap_hsmmc_host *host = mmc_priv(mmc);
1878
1879         pm_runtime_mark_last_busy(host->dev);
1880         pm_runtime_put_autosuspend(host->dev);
1881
1882         return 0;
1883 }
1884
1885 static const struct mmc_host_ops omap_hsmmc_ops = {
1886         .enable = omap_hsmmc_enable_fclk,
1887         .disable = omap_hsmmc_disable_fclk,
1888         .post_req = omap_hsmmc_post_req,
1889         .pre_req = omap_hsmmc_pre_req,
1890         .request = omap_hsmmc_request,
1891         .set_ios = omap_hsmmc_set_ios,
1892         .get_cd = omap_hsmmc_get_cd,
1893         .get_ro = omap_hsmmc_get_ro,
1894         .init_card = omap_hsmmc_init_card,
1895         /* NYET -- enable_sdio_irq */
1896 };
1897
1898 #ifdef CONFIG_DEBUG_FS
1899
1900 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1901 {
1902         struct mmc_host *mmc = s->private;
1903         struct omap_hsmmc_host *host = mmc_priv(mmc);
1904         int context_loss = 0;
1905
1906         if (host->pdata->get_context_loss_count)
1907                 context_loss = host->pdata->get_context_loss_count(host->dev);
1908
1909         seq_printf(s, "mmc%d:\n"
1910                         " enabled:\t%d\n"
1911                         " dpm_state:\t%d\n"
1912                         " nesting_cnt:\t%d\n"
1913                         " ctx_loss:\t%d:%d\n"
1914                         "\nregs:\n",
1915                         mmc->index, mmc->enabled ? 1 : 0,
1916                         host->dpm_state, mmc->nesting_cnt,
1917                         host->context_loss, context_loss);
1918
1919         if (host->suspended) {
1920                 seq_printf(s, "host suspended, can't read registers\n");
1921                 return 0;
1922         }
1923
1924         pm_runtime_get_sync(host->dev);
1925
1926         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1927                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1928         seq_printf(s, "CON:\t\t0x%08x\n",
1929                         OMAP_HSMMC_READ(host->base, CON));
1930         seq_printf(s, "HCTL:\t\t0x%08x\n",
1931                         OMAP_HSMMC_READ(host->base, HCTL));
1932         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1933                         OMAP_HSMMC_READ(host->base, SYSCTL));
1934         seq_printf(s, "IE:\t\t0x%08x\n",
1935                         OMAP_HSMMC_READ(host->base, IE));
1936         seq_printf(s, "ISE:\t\t0x%08x\n",
1937                         OMAP_HSMMC_READ(host->base, ISE));
1938         seq_printf(s, "CAPA:\t\t0x%08x\n",
1939                         OMAP_HSMMC_READ(host->base, CAPA));
1940
1941         pm_runtime_mark_last_busy(host->dev);
1942         pm_runtime_put_autosuspend(host->dev);
1943
1944         return 0;
1945 }
1946
1947 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1948 {
1949         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1950 }
1951
1952 static const struct file_operations mmc_regs_fops = {
1953         .open           = omap_hsmmc_regs_open,
1954         .read           = seq_read,
1955         .llseek         = seq_lseek,
1956         .release        = single_release,
1957 };
1958
1959 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1960 {
1961         if (mmc->debugfs_root)
1962                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1963                         mmc, &mmc_regs_fops);
1964 }
1965
1966 #else
1967
1968 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1969 {
1970 }
1971
1972 #endif
1973
1974 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1975 {
1976         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1977         struct mmc_host *mmc;
1978         struct omap_hsmmc_host *host = NULL;
1979         struct resource *res;
1980         int ret, irq;
1981
1982         if (pdata == NULL) {
1983                 dev_err(&pdev->dev, "Platform Data is missing\n");
1984                 return -ENXIO;
1985         }
1986
1987         if (pdata->nr_slots == 0) {
1988                 dev_err(&pdev->dev, "No Slots\n");
1989                 return -ENXIO;
1990         }
1991
1992         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1993         irq = platform_get_irq(pdev, 0);
1994         if (res == NULL || irq < 0)
1995                 return -ENXIO;
1996
1997         res->start += pdata->reg_offset;
1998         res->end += pdata->reg_offset;
1999         res = request_mem_region(res->start, resource_size(res), pdev->name);
2000         if (res == NULL)
2001                 return -EBUSY;
2002
2003         ret = omap_hsmmc_gpio_init(pdata);
2004         if (ret)
2005                 goto err;
2006
2007         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2008         if (!mmc) {
2009                 ret = -ENOMEM;
2010                 goto err_alloc;
2011         }
2012
2013         host            = mmc_priv(mmc);
2014         host->mmc       = mmc;
2015         host->pdata     = pdata;
2016         host->dev       = &pdev->dev;
2017         host->use_dma   = 1;
2018         host->dev->dma_mask = &pdata->dma_mask;
2019         host->dma_ch    = -1;
2020         host->dma_ch_tx = -1;
2021         host->dma_ch_rx = -1;
2022         host->irq       = irq;
2023         host->id        = pdev->id;
2024         host->slot_id   = 0;
2025         host->mapbase   = res->start;
2026         host->base      = ioremap(host->mapbase, SZ_4K);
2027         host->power_mode = MMC_POWER_OFF;
2028         host->next_data.cookie = 1;
2029
2030         platform_set_drvdata(pdev, host);
2031
2032         mmc->ops        = &omap_hsmmc_ops;
2033
2034         /*
2035          * If regulator_disable can only put vcc_aux to sleep then there is
2036          * no off state.
2037          */
2038         if (mmc_slot(host).vcc_aux_disable_is_sleep)
2039                 mmc_slot(host).no_off = 1;
2040
2041         mmc->f_min      = OMAP_MMC_MIN_CLOCK;
2042         mmc->f_max      = OMAP_MMC_MAX_CLOCK;
2043
2044         spin_lock_init(&host->irq_lock);
2045
2046         host->fclk = clk_get(&pdev->dev, "fck");
2047         if (IS_ERR(host->fclk)) {
2048                 ret = PTR_ERR(host->fclk);
2049                 host->fclk = NULL;
2050                 goto err1;
2051         }
2052
2053         omap_hsmmc_context_save(host);
2054
2055         mmc->caps |= MMC_CAP_DISABLE;
2056
2057         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2058                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2059                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
2060         }
2061
2062         pm_runtime_enable(host->dev);
2063         pm_runtime_get_sync(host->dev);
2064         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2065         pm_runtime_use_autosuspend(host->dev);
2066
2067         if (cpu_is_omap2430()) {
2068                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2069                 /*
2070                  * MMC can still work without debounce clock.
2071                  */
2072                 if (IS_ERR(host->dbclk))
2073                         dev_warn(mmc_dev(host->mmc),
2074                                 "Failed to get debounce clock\n");
2075                 else
2076                         host->got_dbclk = 1;
2077
2078                 if (host->got_dbclk)
2079                         if (clk_enable(host->dbclk) != 0)
2080                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2081                                                         " clk failed\n");
2082         }
2083
2084         /* Since we do only SG emulation, we can have as many segs
2085          * as we want. */
2086         mmc->max_segs = 1024;
2087
2088         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2089         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2090         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2091         mmc->max_seg_size = mmc->max_req_size;
2092
2093         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2094                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2095
2096         mmc->caps |= mmc_slot(host).caps;
2097         if (mmc->caps & MMC_CAP_8_BIT_DATA)
2098                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2099
2100         if (mmc_slot(host).nonremovable)
2101                 mmc->caps |= MMC_CAP_NONREMOVABLE;
2102
2103         omap_hsmmc_conf_bus_power(host);
2104
2105         /* Select DMA lines */
2106         switch (host->id) {
2107         case OMAP_MMC1_DEVID:
2108                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2109                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2110                 break;
2111         case OMAP_MMC2_DEVID:
2112                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2113                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2114                 break;
2115         case OMAP_MMC3_DEVID:
2116                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2117                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2118                 break;
2119         case OMAP_MMC4_DEVID:
2120                 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2121                 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2122                 break;
2123         case OMAP_MMC5_DEVID:
2124                 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2125                 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2126                 break;
2127         default:
2128                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2129                 goto err_irq;
2130         }
2131
2132         /* Request IRQ for MMC operations */
2133         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
2134                         mmc_hostname(mmc), host);
2135         if (ret) {
2136                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2137                 goto err_irq;
2138         }
2139
2140         if (pdata->init != NULL) {
2141                 if (pdata->init(&pdev->dev) != 0) {
2142                         dev_dbg(mmc_dev(host->mmc),
2143                                 "Unable to configure MMC IRQs\n");
2144                         goto err_irq_cd_init;
2145                 }
2146         }
2147
2148         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2149                 ret = omap_hsmmc_reg_get(host);
2150                 if (ret)
2151                         goto err_reg;
2152                 host->use_reg = 1;
2153         }
2154
2155         mmc->ocr_avail = mmc_slot(host).ocr_mask;
2156
2157         /* Request IRQ for card detect */
2158         if ((mmc_slot(host).card_detect_irq)) {
2159                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
2160                                            NULL,
2161                                            omap_hsmmc_detect,
2162                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
2163                                            mmc_hostname(mmc), host);
2164                 if (ret) {
2165                         dev_dbg(mmc_dev(host->mmc),
2166                                 "Unable to grab MMC CD IRQ\n");
2167                         goto err_irq_cd;
2168                 }
2169                 pdata->suspend = omap_hsmmc_suspend_cdirq;
2170                 pdata->resume = omap_hsmmc_resume_cdirq;
2171         }
2172
2173         omap_hsmmc_disable_irq(host);
2174
2175         omap_hsmmc_protect_card(host);
2176
2177         mmc_add_host(mmc);
2178
2179         if (mmc_slot(host).name != NULL) {
2180                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2181                 if (ret < 0)
2182                         goto err_slot_name;
2183         }
2184         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2185                 ret = device_create_file(&mmc->class_dev,
2186                                         &dev_attr_cover_switch);
2187                 if (ret < 0)
2188                         goto err_slot_name;
2189         }
2190
2191         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2192                 ret = device_create_file(&mmc->class_dev, &dev_attr_unsafe_read);
2193
2194                 /* MMC_CAP2_NO_MULTI_READ makes it crawl, try a different workaround */
2195                 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
2196                 mmc->max_segs = 1;
2197                 mmc->f_max = 32000000;
2198         }
2199
2200         omap_hsmmc_debugfs(mmc);
2201         pm_runtime_mark_last_busy(host->dev);
2202         pm_runtime_put_autosuspend(host->dev);
2203
2204         return 0;
2205
2206 err_slot_name:
2207         mmc_remove_host(mmc);
2208         free_irq(mmc_slot(host).card_detect_irq, host);
2209 err_irq_cd:
2210         if (host->use_reg)
2211                 omap_hsmmc_reg_put(host);
2212 err_reg:
2213         if (host->pdata->cleanup)
2214                 host->pdata->cleanup(&pdev->dev);
2215 err_irq_cd_init:
2216         free_irq(host->irq, host);
2217 err_irq:
2218         pm_runtime_mark_last_busy(host->dev);
2219         pm_runtime_put_autosuspend(host->dev);
2220         clk_put(host->fclk);
2221         if (host->got_dbclk) {
2222                 clk_disable(host->dbclk);
2223                 clk_put(host->dbclk);
2224         }
2225 err1:
2226         iounmap(host->base);
2227         platform_set_drvdata(pdev, NULL);
2228         mmc_free_host(mmc);
2229 err_alloc:
2230         omap_hsmmc_gpio_free(pdata);
2231 err:
2232         release_mem_region(res->start, resource_size(res));
2233         return ret;
2234 }
2235
2236 static int omap_hsmmc_remove(struct platform_device *pdev)
2237 {
2238         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2239         struct resource *res;
2240
2241         if (host) {
2242                 pm_runtime_get_sync(host->dev);
2243                 mmc_remove_host(host->mmc);
2244                 if (host->use_reg)
2245                         omap_hsmmc_reg_put(host);
2246                 if (host->pdata->cleanup)
2247                         host->pdata->cleanup(&pdev->dev);
2248                 free_irq(host->irq, host);
2249                 if (mmc_slot(host).card_detect_irq)
2250                         free_irq(mmc_slot(host).card_detect_irq, host);
2251
2252                 pm_runtime_put_sync(host->dev);
2253                 pm_runtime_disable(host->dev);
2254                 clk_put(host->fclk);
2255                 if (host->got_dbclk) {
2256                         clk_disable(host->dbclk);
2257                         clk_put(host->dbclk);
2258                 }
2259
2260                 mmc_free_host(host->mmc);
2261                 iounmap(host->base);
2262                 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2263         }
2264
2265         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2266         if (res)
2267                 release_mem_region(res->start, resource_size(res));
2268         platform_set_drvdata(pdev, NULL);
2269
2270         return 0;
2271 }
2272
2273 #ifdef CONFIG_PM
2274 static int omap_hsmmc_suspend(struct device *dev)
2275 {
2276         int ret = 0;
2277         struct platform_device *pdev = to_platform_device(dev);
2278         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2279
2280         if (host && host->suspended)
2281                 return 0;
2282
2283         if (host) {
2284                 pm_runtime_get_sync(host->dev);
2285                 host->suspended = 1;
2286                 if (host->pdata->suspend) {
2287                         ret = host->pdata->suspend(&pdev->dev,
2288                                                         host->slot_id);
2289                         if (ret) {
2290                                 dev_dbg(mmc_dev(host->mmc),
2291                                         "Unable to handle MMC board"
2292                                         " level suspend\n");
2293                                 host->suspended = 0;
2294                                 return ret;
2295                         }
2296                 }
2297                 ret = mmc_suspend_host(host->mmc);
2298
2299                 if (ret == 0) {
2300                         omap_hsmmc_disable_irq(host);
2301                         OMAP_HSMMC_WRITE(host->base, HCTL,
2302                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2303                         if (host->got_dbclk)
2304                                 clk_disable(host->dbclk);
2305                 } else {
2306                         host->suspended = 0;
2307                         if (host->pdata->resume) {
2308                                 if (host->pdata->resume(&pdev->dev, host->slot_id))
2309                                         dev_dbg(mmc_dev(host->mmc),
2310                                                 "Unmask interrupt failed\n");
2311                         }
2312                 }
2313                 pm_runtime_put_sync(host->dev);
2314         }
2315         return ret;
2316 }
2317
2318 /* Routine to resume the MMC device */
2319 static int omap_hsmmc_resume(struct device *dev)
2320 {
2321         int ret = 0;
2322         struct platform_device *pdev = to_platform_device(dev);
2323         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2324
2325         if (host && !host->suspended)
2326                 return 0;
2327
2328         if (host) {
2329                 pm_runtime_get_sync(host->dev);
2330
2331                 if (host->got_dbclk)
2332                         clk_enable(host->dbclk);
2333
2334                 omap_hsmmc_conf_bus_power(host);
2335
2336                 if (host->pdata->resume) {
2337                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
2338                         if (ret)
2339                                 dev_dbg(mmc_dev(host->mmc),
2340                                         "Unmask interrupt failed\n");
2341                 }
2342
2343                 omap_hsmmc_protect_card(host);
2344
2345                 /* Notify the core to resume the host */
2346                 ret = mmc_resume_host(host->mmc);
2347                 if (ret == 0)
2348                         host->suspended = 0;
2349
2350                 pm_runtime_mark_last_busy(host->dev);
2351                 pm_runtime_put_autosuspend(host->dev);
2352         }
2353
2354         return ret;
2355
2356 }
2357
2358 #else
2359 #define omap_hsmmc_suspend      NULL
2360 #define omap_hsmmc_resume               NULL
2361 #endif
2362
2363 static int omap_hsmmc_runtime_suspend(struct device *dev)
2364 {
2365         struct omap_hsmmc_host *host;
2366
2367         host = platform_get_drvdata(to_platform_device(dev));
2368         omap_hsmmc_context_save(host);
2369
2370         omap_hsmmc_free_dma(host);
2371
2372         dev_dbg(mmc_dev(host->mmc), "disabled\n");
2373
2374         return 0;
2375 }
2376
2377 static int omap_hsmmc_runtime_resume(struct device *dev)
2378 {
2379         struct omap_hsmmc_host *host;
2380
2381         host = platform_get_drvdata(to_platform_device(dev));
2382         omap_hsmmc_context_restore(host);
2383         dev_dbg(mmc_dev(host->mmc), "enabled\n");
2384
2385         return 0;
2386 }
2387
2388 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2389         .suspend        = omap_hsmmc_suspend,
2390         .resume         = omap_hsmmc_resume,
2391         .runtime_suspend = omap_hsmmc_runtime_suspend,
2392         .runtime_resume = omap_hsmmc_runtime_resume,
2393 };
2394
2395 static struct platform_driver omap_hsmmc_driver = {
2396         .remove         = omap_hsmmc_remove,
2397         .driver         = {
2398                 .name = DRIVER_NAME,
2399                 .owner = THIS_MODULE,
2400                 .pm = &omap_hsmmc_dev_pm_ops,
2401         },
2402 };
2403
2404 static int __init omap_hsmmc_init(void)
2405 {
2406         /* Register the MMC driver */
2407         return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2408 }
2409
2410 static void __exit omap_hsmmc_cleanup(void)
2411 {
2412         /* Unregister MMC driver */
2413         platform_driver_unregister(&omap_hsmmc_driver);
2414 }
2415
2416 module_init(omap_hsmmc_init);
2417 module_exit(omap_hsmmc_cleanup);
2418
2419 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2420 MODULE_LICENSE("GPL");
2421 MODULE_ALIAS("platform:" DRIVER_NAME);
2422 MODULE_AUTHOR("Texas Instruments Inc");