drivers/media/dvb/frontends/tda1004x.c

   1   /*
   2      Driver for Philips tda1004xh OFDM Demodulator
   3
   4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   5
   6      This program is free software; you can redistribute it and/or modify
   7      it under the terms of the GNU General Public License as published by
   8      the Free Software Foundation; either version 2 of the License, or
   9      (at your option) any later version.
  10
  11      This program is distributed in the hope that it will be useful,
  12      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15      GNU General Public License for more details.
  16
  17      You should have received a copy of the GNU General Public License
  18      along with this program; if not, write to the Free Software
  19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21    */
  22 /*
  23  * This driver needs external firmware. Please use the commands
  24  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
  25  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
  26  * download/extract them, and then copy them to /usr/lib/hotplug/firmware
  27  * or /lib/firmware (depending on configuration of firmware hotplug).
  28  */
  29 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
  30 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
  31
  32 #include <linux/init.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/device.h>
  36 #include <linux/jiffies.h>
  37 #include <linux/string.h>
  38 #include <linux/slab.h>
  39
  40 #include "dvb_frontend.h"
  41 #include "tda1004x.h"
  42
  43 enum tda1004x_demod {
  44         TDA1004X_DEMOD_TDA10045,
  45         TDA1004X_DEMOD_TDA10046,
  46 };
  47
  48 struct tda1004x_state {
  49         struct i2c_adapter* i2c;
  50         const struct tda1004x_config* config;
  51         struct dvb_frontend frontend;
  52
  53         /* private demod data */
  54         enum tda1004x_demod demod_type;
  55 };
  56
  57 static int debug;
  58 #define dprintk(args...) \
  59         do { \
  60                 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
  61         } while (0)
  62
  63 #define TDA1004X_CHIPID          0x00
  64 #define TDA1004X_AUTO            0x01
  65 #define TDA1004X_IN_CONF1        0x02
  66 #define TDA1004X_IN_CONF2        0x03
  67 #define TDA1004X_OUT_CONF1       0x04
  68 #define TDA1004X_OUT_CONF2       0x05
  69 #define TDA1004X_STATUS_CD       0x06
  70 #define TDA1004X_CONFC4          0x07
  71 #define TDA1004X_DSSPARE2        0x0C
  72 #define TDA10045H_CODE_IN        0x0D
  73 #define TDA10045H_FWPAGE         0x0E
  74 #define TDA1004X_SCAN_CPT        0x10
  75 #define TDA1004X_DSP_CMD         0x11
  76 #define TDA1004X_DSP_ARG         0x12
  77 #define TDA1004X_DSP_DATA1       0x13
  78 #define TDA1004X_DSP_DATA2       0x14
  79 #define TDA1004X_CONFADC1        0x15
  80 #define TDA1004X_CONFC1          0x16
  81 #define TDA10045H_S_AGC          0x1a
  82 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  83 #define TDA1004X_SNR             0x1c
  84 #define TDA1004X_CONF_TS1        0x1e
  85 #define TDA1004X_CONF_TS2        0x1f
  86 #define TDA1004X_CBER_RESET      0x20
  87 #define TDA1004X_CBER_MSB        0x21
  88 #define TDA1004X_CBER_LSB        0x22
  89 #define TDA1004X_CVBER_LUT       0x23
  90 #define TDA1004X_VBER_MSB        0x24
  91 #define TDA1004X_VBER_MID        0x25
  92 #define TDA1004X_VBER_LSB        0x26
  93 #define TDA1004X_UNCOR           0x27
  94
  95 #define TDA10045H_CONFPLL_P      0x2D
  96 #define TDA10045H_CONFPLL_M_MSB  0x2E
  97 #define TDA10045H_CONFPLL_M_LSB  0x2F
  98 #define TDA10045H_CONFPLL_N      0x30
  99
 100 #define TDA10046H_CONFPLL1       0x2D
 101 #define TDA10046H_CONFPLL2       0x2F
 102 #define TDA10046H_CONFPLL3       0x30
 103 #define TDA10046H_TIME_WREF1     0x31
 104 #define TDA10046H_TIME_WREF2     0x32
 105 #define TDA10046H_TIME_WREF3     0x33
 106 #define TDA10046H_TIME_WREF4     0x34
 107 #define TDA10046H_TIME_WREF5     0x35
 108
 109 #define TDA10045H_UNSURW_MSB     0x31
 110 #define TDA10045H_UNSURW_LSB     0x32
 111 #define TDA10045H_WREF_MSB       0x33
 112 #define TDA10045H_WREF_MID       0x34
 113 #define TDA10045H_WREF_LSB       0x35
 114 #define TDA10045H_MUXOUT         0x36
 115 #define TDA1004X_CONFADC2        0x37
 116
 117 #define TDA10045H_IOFFSET        0x38
 118
 119 #define TDA10046H_CONF_TRISTATE1 0x3B
 120 #define TDA10046H_CONF_TRISTATE2 0x3C
 121 #define TDA10046H_CONF_POLARITY  0x3D
 122 #define TDA10046H_FREQ_OFFSET    0x3E
 123 #define TDA10046H_GPIO_OUT_SEL   0x41
 124 #define TDA10046H_GPIO_SELECT    0x42
 125 #define TDA10046H_AGC_CONF       0x43
 126 #define TDA10046H_AGC_THR        0x44
 127 #define TDA10046H_AGC_RENORM     0x45
 128 #define TDA10046H_AGC_GAINS      0x46
 129 #define TDA10046H_AGC_TUN_MIN    0x47
 130 #define TDA10046H_AGC_TUN_MAX    0x48
 131 #define TDA10046H_AGC_IF_MIN     0x49
 132 #define TDA10046H_AGC_IF_MAX     0x4A
 133
 134 #define TDA10046H_FREQ_PHY2_MSB  0x4D
 135 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 136
 137 #define TDA10046H_CVBER_CTRL     0x4F
 138 #define TDA10046H_AGC_IF_LEVEL   0x52
 139 #define TDA10046H_CODE_CPT       0x57
 140 #define TDA10046H_CODE_IN        0x58
 141
 142
 143 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
 144 {
 145         int ret;
 146         u8 buf[] = { reg, data };
 147         struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
 148
 149         dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
 150
 151         msg.addr = state->config->demod_address;
 152         ret = i2c_transfer(state->i2c, &msg, 1);
 153
 154         if (ret != 1)
 155                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 156                         __FUNCTION__, reg, data, ret);
 157
 158         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 159                 reg, data, ret);
 160         return (ret != 1) ? -1 : 0;
 161 }
 162
 163 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
 164 {
 165         int ret;
 166         u8 b0[] = { reg };
 167         u8 b1[] = { 0 };
 168         struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
 169                                 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
 170
 171         dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
 172
 173         msg[0].addr = state->config->demod_address;
 174         msg[1].addr = state->config->demod_address;
 175         ret = i2c_transfer(state->i2c, msg, 2);
 176
 177         if (ret != 2) {
 178                 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
 179                         ret);
 180                 return -1;
 181         }
 182
 183         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 184                 reg, b1[0], ret);
 185         return b1[0];
 186 }
 187
 188 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
 189 {
 190         int val;
 191         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
 192                 mask, data);
 193
 194         // read a byte and check
 195         val = tda1004x_read_byte(state, reg);
 196         if (val < 0)
 197                 return val;
 198
 199         // mask if off
 200         val = val & ~mask;
 201         val |= data & 0xff;
 202
 203         // write it out again
 204         return tda1004x_write_byteI(state, reg, val);
 205 }
 206
 207 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
 208 {
 209         int i;
 210         int result;
 211
 212         dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
 213
 214         result = 0;
 215         for (i = 0; i < len; i++) {
 216                 result = tda1004x_write_byteI(state, reg + i, buf[i]);
 217                 if (result != 0)
 218                         break;
 219         }
 220
 221         return result;
 222 }
 223
 224 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
 225 {
 226         int result;
 227         dprintk("%s\n", __FUNCTION__);
 228
 229         result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
 230         msleep(20);
 231         return result;
 232 }
 233
 234 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
 235 {
 236         dprintk("%s\n", __FUNCTION__);
 237
 238         return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
 239 }
 240
 241 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
 242                                    fe_bandwidth_t bandwidth)
 243 {
 244         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 245         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 246         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 247
 248         switch (bandwidth) {
 249         case BANDWIDTH_6_MHZ:
 250                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 251                 break;
 252
 253         case BANDWIDTH_7_MHZ:
 254                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 255                 break;
 256
 257         case BANDWIDTH_8_MHZ:
 258                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 259                 break;
 260
 261         default:
 262                 return -EINVAL;
 263         }
 264
 265         tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
 266
 267         return 0;
 268 }
 269
 270 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
 271                                    fe_bandwidth_t bandwidth)
 272 {
 273         static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
 274         static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
 275         static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
 276
 277         static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
 278         static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
 279         static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
 280         int tda10046_clk53m;
 281
 282         if ((state->config->if_freq == TDA10046_FREQ_045) ||
 283             (state->config->if_freq == TDA10046_FREQ_052))
 284                 tda10046_clk53m = 0;
 285         else
 286                 tda10046_clk53m = 1;
 287         switch (bandwidth) {
 288         case BANDWIDTH_6_MHZ:
 289                 if (tda10046_clk53m)
 290                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
 291                                                   sizeof(bandwidth_6mhz_53M));
 292                 else
 293                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
 294                                                   sizeof(bandwidth_6mhz_48M));
 295                 if (state->config->if_freq == TDA10046_FREQ_045) {
 296                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
 297                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
 298                 }
 299                 break;
 300
 301         case BANDWIDTH_7_MHZ:
 302                 if (tda10046_clk53m)
 303                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
 304                                                   sizeof(bandwidth_7mhz_53M));
 305                 else
 306                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
 307                                                   sizeof(bandwidth_7mhz_48M));
 308                 if (state->config->if_freq == TDA10046_FREQ_045) {
 309                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
 310                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
 311                 }
 312                 break;
 313
 314         case BANDWIDTH_8_MHZ:
 315                 if (tda10046_clk53m)
 316                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
 317                                                   sizeof(bandwidth_8mhz_53M));
 318                 else
 319                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
 320                                                   sizeof(bandwidth_8mhz_48M));
 321                 if (state->config->if_freq == TDA10046_FREQ_045) {
 322                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
 323                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
 324                 }
 325                 break;
 326
 327         default:
 328                 return -EINVAL;
 329         }
 330
 331         return 0;
 332 }
 333
 334 static int tda1004x_do_upload(struct tda1004x_state *state,
 335                               unsigned char *mem, unsigned int len,
 336                               u8 dspCodeCounterReg, u8 dspCodeInReg)
 337 {
 338         u8 buf[65];
 339         struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
 340         int tx_size;
 341         int pos = 0;
 342
 343         /* clear code counter */
 344         tda1004x_write_byteI(state, dspCodeCounterReg, 0);
 345         fw_msg.addr = state->config->demod_address;
 346
 347         buf[0] = dspCodeInReg;
 348         while (pos != len) {
 349                 // work out how much to send this time
 350                 tx_size = len - pos;
 351                 if (tx_size > 0x10)
 352                         tx_size = 0x10;
 353
 354                 // send the chunk
 355                 memcpy(buf + 1, mem + pos, tx_size);
 356                 fw_msg.len = tx_size + 1;
 357                 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
 358                         printk(KERN_ERR "tda1004x: Error during firmware upload\n");
 359                         return -EIO;
 360                 }
 361                 pos += tx_size;
 362
 363                 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
 364         }
 365         // give the DSP a chance to settle 03/10/05 Hac
 366         msleep(100);
 367
 368         return 0;
 369 }
 370
 371 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
 372 {
 373         u8 data1, data2;
 374         unsigned long timeout;
 375
 376         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 377                 timeout = jiffies + 2 * HZ;
 378                 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
 379                         if (time_after(jiffies, timeout)) {
 380                                 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
 381                                 break;
 382                         }
 383                         msleep(1);
 384                 }
 385         } else
 386                 msleep(100);
 387
 388         // check upload was OK
 389         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 390         tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
 391
 392         data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
 393         data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
 394         if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
 395                 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
 396                 return -EIO;
 397         }
 398         printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
 399         return 0;
 400 }
 401
 402 static int tda10045_fwupload(struct dvb_frontend* fe)
 403 {
 404         struct tda1004x_state* state = fe->demodulator_priv;
 405         int ret;
 406         const struct firmware *fw;
 407
 408         /* don't re-upload unless necessary */
 409         if (tda1004x_check_upload_ok(state) == 0)
 410                 return 0;
 411
 412         /* request the firmware, this will block until someone uploads it */
 413         printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
 414         ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
 415         if (ret) {
 416                 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 417                 return ret;
 418         }
 419
 420         /* reset chip */
 421         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
 422         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 423         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 424         msleep(10);
 425
 426         /* set parameters */
 427         tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
 428
 429         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
 430         release_firmware(fw);
 431         if (ret)
 432                 return ret;
 433         printk(KERN_INFO "tda1004x: firmware upload complete\n");
 434
 435         /* wait for DSP to initialise */
 436         /* DSPREADY doesn't seem to work on the TDA10045H */
 437         msleep(100);
 438
 439         return tda1004x_check_upload_ok(state);
 440 }
 441
 442 static void tda10046_init_plls(struct dvb_frontend* fe)
 443 {
 444         struct tda1004x_state* state = fe->demodulator_priv;
 445         int tda10046_clk53m;
 446
 447         if ((state->config->if_freq == TDA10046_FREQ_045) ||
 448             (state->config->if_freq == TDA10046_FREQ_052))
 449                 tda10046_clk53m = 0;
 450         else
 451                 tda10046_clk53m = 1;
 452
 453         tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
 454         if(tda10046_clk53m) {
 455                 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
 456                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
 457         } else {
 458                 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
 459                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
 460         }
 461         if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
 462                 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
 463                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
 464         } else {
 465                 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
 466                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
 467         }
 468         if(tda10046_clk53m)
 469                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
 470         else
 471                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
 472         /* Note clock frequency is handled implicitly */
 473         switch (state->config->if_freq) {
 474         case TDA10046_FREQ_045:
 475                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
 476                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
 477                 break;
 478         case TDA10046_FREQ_052:
 479                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
 480                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
 481                 break;
 482         case TDA10046_FREQ_3617:
 483                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
 484                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
 485                 break;
 486         case TDA10046_FREQ_3613:
 487                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
 488                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
 489                 break;
 490         }
 491         tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
 492         /* let the PLLs settle */
 493         msleep(120);
 494 }
 495
 496 static int tda10046_fwupload(struct dvb_frontend* fe)
 497 {
 498         struct tda1004x_state* state = fe->demodulator_priv;
 499         int ret;
 500         const struct firmware *fw;
 501
 502         /* reset + wake up chip */
 503         if (state->config->xtal_freq == TDA10046_XTAL_4M) {
 504                 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
 505         } else {
 506                 dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __FUNCTION__);
 507                 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0x80);
 508         }
 509         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
 510         /* let the clocks recover from sleep */
 511         msleep(5);
 512
 513         /* The PLLs need to be reprogrammed after sleep */
 514         tda10046_init_plls(fe);
 515
 516         /* don't re-upload unless necessary */
 517         if (tda1004x_check_upload_ok(state) == 0)
 518                 return 0;
 519
 520         if (state->config->request_firmware != NULL) {
 521                 /* request the firmware, this will block until someone uploads it */
 522                 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
 523                 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
 524                 if (ret) {
 525                         printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 526                         return ret;
 527                 }
 528                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 529                 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
 530                 release_firmware(fw);
 531                 if (ret)
 532                         return ret;
 533         } else {
 534                 /* boot from firmware eeprom */
 535                 printk(KERN_INFO "tda1004x: booting from eeprom\n");
 536                 tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
 537                 msleep(300);
 538         }
 539         return tda1004x_check_upload_ok(state);
 540 }
 541
 542 static int tda1004x_encode_fec(int fec)
 543 {
 544         // convert known FEC values
 545         switch (fec) {
 546         case FEC_1_2:
 547                 return 0;
 548         case FEC_2_3:
 549                 return 1;
 550         case FEC_3_4:
 551                 return 2;
 552         case FEC_5_6:
 553                 return 3;
 554         case FEC_7_8:
 555                 return 4;
 556         }
 557
 558         // unsupported
 559         return -EINVAL;
 560 }
 561
 562 static int tda1004x_decode_fec(int tdafec)
 563 {
 564         // convert known FEC values
 565         switch (tdafec) {
 566         case 0:
 567                 return FEC_1_2;
 568         case 1:
 569                 return FEC_2_3;
 570         case 2:
 571                 return FEC_3_4;
 572         case 3:
 573                 return FEC_5_6;
 574         case 4:
 575                 return FEC_7_8;
 576         }
 577
 578         // unsupported
 579         return -1;
 580 }
 581
 582 int tda1004x_write(struct dvb_frontend* fe, u8 *buf, int len)
 583 {
 584         struct tda1004x_state* state = fe->demodulator_priv;
 585
 586         if (len != 2)
 587                 return -EINVAL;
 588
 589         return tda1004x_write_byteI(state, buf[0], buf[1]);
 590 }
 591
 592 static int tda10045_init(struct dvb_frontend* fe)
 593 {
 594         struct tda1004x_state* state = fe->demodulator_priv;
 595
 596         dprintk("%s\n", __FUNCTION__);
 597
 598         if (tda10045_fwupload(fe)) {
 599                 printk("tda1004x: firmware upload failed\n");
 600                 return -EIO;
 601         }
 602
 603         tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 604
 605         // tda setup
 606         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 607         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
 608         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
 609         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 610         tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 611         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 612         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 613         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 614         tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 615         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 616         tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
 617
 618         tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
 619
 620         return 0;
 621 }
 622
 623 static int tda10046_init(struct dvb_frontend* fe)
 624 {
 625         struct tda1004x_state* state = fe->demodulator_priv;
 626         dprintk("%s\n", __FUNCTION__);
 627
 628         if (tda10046_fwupload(fe)) {
 629                 printk("tda1004x: firmware upload failed\n");
 630                         return -EIO;
 631         }
 632
 633         // tda setup
 634         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 635         tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87);    // 100 ppm crystal, select HP stream
 636         tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88);      // enable pulse killer
 637
 638         switch (state->config->agc_config) {
 639         case TDA10046_AGC_DEFAULT:
 640                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
 641                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
 642                 break;
 643         case TDA10046_AGC_IFO_AUTO_NEG:
 644                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 645                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
 646                 break;
 647         case TDA10046_AGC_IFO_AUTO_POS:
 648                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 649                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x00); // set AGC polarities
 650                 break;
 651         case TDA10046_AGC_TDA827X:
 652                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02);   // AGC setup
 653                 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70);    // AGC Threshold
 654                 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
 655                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x6a); // set AGC polarities
 656                 break;
 657         case TDA10046_AGC_TDA827X_GPL:
 658                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02);   // AGC setup
 659                 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70);    // AGC Threshold
 660                 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
 661                 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
 662                 break;
 663         }
 664         tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
 665         tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
 666         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);    // }
 667         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 668         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0);     // }
 669         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 670         tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
 671         tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
 672         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 673         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
 674         // tda1004x_write_mask(state, 0x50, 0x80, 0x80);         // handle out of guard echoes
 675         tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
 676
 677         return 0;
 678 }
 679
 680 static int tda1004x_set_fe(struct dvb_frontend* fe,
 681                            struct dvb_frontend_parameters *fe_params)
 682 {
 683         struct tda1004x_state* state = fe->demodulator_priv;
 684         int tmp;
 685         int inversion;
 686
 687         dprintk("%s\n", __FUNCTION__);
 688
 689         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 690                 // setup auto offset
 691                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
 692                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
 693                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
 694
 695                 // disable agc_conf[2]
 696                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
 697         }
 698
 699         // set frequency
 700         if (fe->ops.tuner_ops.set_params) {
 701                 fe->ops.tuner_ops.set_params(fe, fe_params);
 702                 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
 703         }
 704
 705         // Hardcoded to use auto as much as possible on the TDA10045 as it
 706         // is very unreliable if AUTO mode is _not_ used.
 707         if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
 708                 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
 709                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
 710                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
 711         }
 712
 713         // Set standard params.. or put them to auto
 714         if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
 715                 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
 716                 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
 717                 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
 718                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1);        // enable auto
 719                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
 720                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
 721                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
 722         } else {
 723                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0);        // disable auto
 724
 725                 // set HP FEC
 726                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
 727                 if (tmp < 0)
 728                         return tmp;
 729                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
 730
 731                 // set LP FEC
 732                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
 733                 if (tmp < 0)
 734                         return tmp;
 735                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 736
 737                 // set constellation
 738                 switch (fe_params->u.ofdm.constellation) {
 739                 case QPSK:
 740                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
 741                         break;
 742
 743                 case QAM_16:
 744                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
 745                         break;
 746
 747                 case QAM_64:
 748                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
 749                         break;
 750
 751                 default:
 752                         return -EINVAL;
 753                 }
 754
 755                 // set hierarchy
 756                 switch (fe_params->u.ofdm.hierarchy_information) {
 757                 case HIERARCHY_NONE:
 758                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 759                         break;
 760
 761                 case HIERARCHY_1:
 762                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 763                         break;
 764
 765                 case HIERARCHY_2:
 766                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 767                         break;
 768
 769                 case HIERARCHY_4:
 770                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 771                         break;
 772
 773                 default:
 774                         return -EINVAL;
 775                 }
 776         }
 777
 778         // set bandwidth
 779         switch (state->demod_type) {
 780         case TDA1004X_DEMOD_TDA10045:
 781                 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 782                 break;
 783
 784         case TDA1004X_DEMOD_TDA10046:
 785                 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 786                 break;
 787         }
 788
 789         // set inversion
 790         inversion = fe_params->inversion;
 791         if (state->config->invert)
 792                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 793         switch (inversion) {
 794         case INVERSION_OFF:
 795                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
 796                 break;
 797
 798         case INVERSION_ON:
 799                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
 800                 break;
 801
 802         default:
 803                 return -EINVAL;
 804         }
 805
 806         // set guard interval
 807         switch (fe_params->u.ofdm.guard_interval) {
 808         case GUARD_INTERVAL_1_32:
 809                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 810                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 811                 break;
 812
 813         case GUARD_INTERVAL_1_16:
 814                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 815                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 816                 break;
 817
 818         case GUARD_INTERVAL_1_8:
 819                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 820                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 821                 break;
 822
 823         case GUARD_INTERVAL_1_4:
 824                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 825                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 826                 break;
 827
 828         case GUARD_INTERVAL_AUTO:
 829                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
 830                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 831                 break;
 832
 833         default:
 834                 return -EINVAL;
 835         }
 836
 837         // set transmission mode
 838         switch (fe_params->u.ofdm.transmission_mode) {
 839         case TRANSMISSION_MODE_2K:
 840                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 841                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 842                 break;
 843
 844         case TRANSMISSION_MODE_8K:
 845                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 846                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 847                 break;
 848
 849         case TRANSMISSION_MODE_AUTO:
 850                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
 851                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
 852                 break;
 853
 854         default:
 855                 return -EINVAL;
 856         }
 857
 858         // start the lock
 859         switch (state->demod_type) {
 860         case TDA1004X_DEMOD_TDA10045:
 861                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 862                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 863                 break;
 864
 865         case TDA1004X_DEMOD_TDA10046:
 866                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
 867                 msleep(1);
 868                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
 869                 break;
 870         }
 871
 872         msleep(10);
 873
 874         return 0;
 875 }
 876
 877 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
 878 {
 879         struct tda1004x_state* state = fe->demodulator_priv;
 880
 881         dprintk("%s\n", __FUNCTION__);
 882
 883         // inversion status
 884         fe_params->inversion = INVERSION_OFF;
 885         if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
 886                 fe_params->inversion = INVERSION_ON;
 887         if (state->config->invert)
 888                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
 889
 890         // bandwidth
 891         switch (state->demod_type) {
 892         case TDA1004X_DEMOD_TDA10045:
 893                 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
 894                 case 0x14:
 895                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 896                         break;
 897                 case 0xdb:
 898                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 899                         break;
 900                 case 0x4f:
 901                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 902                         break;
 903                 }
 904                 break;
 905         case TDA1004X_DEMOD_TDA10046:
 906                 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
 907                 case 0x5c:
 908                 case 0x54:
 909                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 910                         break;
 911                 case 0x6a:
 912                 case 0x60:
 913                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 914                         break;
 915                 case 0x7b:
 916                 case 0x70:
 917                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 918                         break;
 919                 }
 920                 break;
 921         }
 922
 923         // FEC
 924         fe_params->u.ofdm.code_rate_HP =
 925             tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
 926         fe_params->u.ofdm.code_rate_LP =
 927             tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
 928
 929         // constellation
 930         switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
 931         case 0:
 932                 fe_params->u.ofdm.constellation = QPSK;
 933                 break;
 934         case 1:
 935                 fe_params->u.ofdm.constellation = QAM_16;
 936                 break;
 937         case 2:
 938                 fe_params->u.ofdm.constellation = QAM_64;
 939                 break;
 940         }
 941
 942         // transmission mode
 943         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
 944         if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
 945                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
 946
 947         // guard interval
 948         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
 949         case 0:
 950                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
 951                 break;
 952         case 1:
 953                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
 954                 break;
 955         case 2:
 956                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
 957                 break;
 958         case 3:
 959                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
 960                 break;
 961         }
 962
 963         // hierarchy
 964         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
 965         case 0:
 966                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
 967                 break;
 968         case 1:
 969                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
 970                 break;
 971         case 2:
 972                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
 973                 break;
 974         case 3:
 975                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
 976                 break;
 977         }
 978
 979         return 0;
 980 }
 981
 982 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
 983 {
 984         struct tda1004x_state* state = fe->demodulator_priv;
 985         int status;
 986         int cber;
 987         int vber;
 988
 989         dprintk("%s\n", __FUNCTION__);
 990
 991         // read status
 992         status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
 993         if (status == -1)
 994                 return -EIO;
 995
 996         // decode
 997         *fe_status = 0;
 998         if (status & 4)
 999                 *fe_status |= FE_HAS_SIGNAL;
1000         if (status & 2)
1001                 *fe_status |= FE_HAS_CARRIER;
1002         if (status & 8)
1003                 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1004
1005         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1006         // is getting anything valid
1007         if (!(*fe_status & FE_HAS_VITERBI)) {
1008                 // read the CBER
1009                 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1010                 if (cber == -1)
1011                         return -EIO;
1012                 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1013                 if (status == -1)
1014                         return -EIO;
1015                 cber |= (status << 8);
1016                 // The address 0x20 should be read to cope with a TDA10046 bug
1017                 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1018
1019                 if (cber != 65535)
1020                         *fe_status |= FE_HAS_VITERBI;
1021         }
1022
1023         // if we DO have some valid VITERBI output, but don't already have SYNC
1024         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1025         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1026                 // read the VBER
1027                 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1028                 if (vber == -1)
1029                         return -EIO;
1030                 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1031                 if (status == -1)
1032                         return -EIO;
1033                 vber |= (status << 8);
1034                 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1035                 if (status == -1)
1036                         return -EIO;
1037                 vber |= (status & 0x0f) << 16;
1038                 // The CVBER_LUT should be read to cope with TDA10046 hardware bug
1039                 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1040
1041                 // if RS has passed some valid TS packets, then we must be
1042                 // getting some SYNC bytes
1043                 if (vber < 16632)
1044                         *fe_status |= FE_HAS_SYNC;
1045         }
1046
1047         // success
1048         dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1049         return 0;
1050 }
1051
1052 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1053 {
1054         struct tda1004x_state* state = fe->demodulator_priv;
1055         int tmp;
1056         int reg = 0;
1057
1058         dprintk("%s\n", __FUNCTION__);
1059
1060         // determine the register to use
1061         switch (state->demod_type) {
1062         case TDA1004X_DEMOD_TDA10045:
1063                 reg = TDA10045H_S_AGC;
1064                 break;
1065
1066         case TDA1004X_DEMOD_TDA10046:
1067                 reg = TDA10046H_AGC_IF_LEVEL;
1068                 break;
1069         }
1070
1071         // read it
1072         tmp = tda1004x_read_byte(state, reg);
1073         if (tmp < 0)
1074                 return -EIO;
1075
1076         *signal = (tmp << 8) | tmp;
1077         dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1078         return 0;
1079 }
1080
1081 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1082 {
1083         struct tda1004x_state* state = fe->demodulator_priv;
1084         int tmp;
1085
1086         dprintk("%s\n", __FUNCTION__);
1087
1088         // read it
1089         tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1090         if (tmp < 0)
1091                 return -EIO;
1092         tmp = 255 - tmp;
1093
1094         *snr = ((tmp << 8) | tmp);
1095         dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1096         return 0;
1097 }
1098
1099 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1100 {
1101         struct tda1004x_state* state = fe->demodulator_priv;
1102         int tmp;
1103         int tmp2;
1104         int counter;
1105
1106         dprintk("%s\n", __FUNCTION__);
1107
1108         // read the UCBLOCKS and reset
1109         counter = 0;
1110         tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1111         if (tmp < 0)
1112                 return -EIO;
1113         tmp &= 0x7f;
1114         while (counter++ < 5) {
1115                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1116                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1117                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1118
1119                 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1120                 if (tmp2 < 0)
1121                         return -EIO;
1122                 tmp2 &= 0x7f;
1123                 if ((tmp2 < tmp) || (tmp2 == 0))
1124                         break;
1125         }
1126
1127         if (tmp != 0x7f)
1128                 *ucblocks = tmp;
1129         else
1130                 *ucblocks = 0xffffffff;
1131
1132         dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1133         return 0;
1134 }
1135
1136 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1137 {
1138         struct tda1004x_state* state = fe->demodulator_priv;
1139         int tmp;
1140
1141         dprintk("%s\n", __FUNCTION__);
1142
1143         // read it in
1144         tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1145         if (tmp < 0)
1146                 return -EIO;
1147         *ber = tmp << 1;
1148         tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1149         if (tmp < 0)
1150                 return -EIO;
1151         *ber |= (tmp << 9);
1152         // The address 0x20 should be read to cope with a TDA10046 bug
1153         tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1154
1155         dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1156         return 0;
1157 }
1158
1159 static int tda1004x_sleep(struct dvb_frontend* fe)
1160 {
1161         struct tda1004x_state* state = fe->demodulator_priv;
1162
1163         switch (state->demod_type) {
1164         case TDA1004X_DEMOD_TDA10045:
1165                 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1166                 break;
1167
1168         case TDA1004X_DEMOD_TDA10046:
1169                 /* set outputs to tristate */
1170                 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
1171                 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1172                 break;
1173         }
1174
1175         return 0;
1176 }
1177
1178 static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
1179 {
1180         struct tda1004x_state* state = fe->demodulator_priv;
1181
1182         if (enable) {
1183                 return tda1004x_enable_tuner_i2c(state);
1184         } else {
1185                 return tda1004x_disable_tuner_i2c(state);
1186         }
1187 }
1188
1189 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1190 {
1191         fesettings->min_delay_ms = 800;
1192         /* Drift compensation makes no sense for DVB-T */
1193         fesettings->step_size = 0;
1194         fesettings->max_drift = 0;
1195         return 0;
1196 }
1197
1198 static void tda1004x_release(struct dvb_frontend* fe)
1199 {
1200         struct tda1004x_state *state = fe->demodulator_priv;
1201         kfree(state);
1202 }
1203
1204 static struct dvb_frontend_ops tda10045_ops = {
1205         .info = {
1206                 .name = "Philips TDA10045H DVB-T",
1207                 .type = FE_OFDM,
1208                 .frequency_min = 51000000,
1209                 .frequency_max = 858000000,
1210                 .frequency_stepsize = 166667,
1211                 .caps =
1212                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1213                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1214                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1215                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1216         },
1217
1218         .release = tda1004x_release,
1219
1220         .init = tda10045_init,
1221         .sleep = tda1004x_sleep,
1222         .write = tda1004x_write,
1223         .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1224
1225         .set_frontend = tda1004x_set_fe,
1226         .get_frontend = tda1004x_get_fe,
1227         .get_tune_settings = tda1004x_get_tune_settings,
1228
1229         .read_status = tda1004x_read_status,
1230         .read_ber = tda1004x_read_ber,
1231         .read_signal_strength = tda1004x_read_signal_strength,
1232         .read_snr = tda1004x_read_snr,
1233         .read_ucblocks = tda1004x_read_ucblocks,
1234 };
1235
1236 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1237                                      struct i2c_adapter* i2c)
1238 {
1239         struct tda1004x_state *state;
1240
1241         /* allocate memory for the internal state */
1242         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1243         if (!state)
1244                 return NULL;
1245
1246         /* setup the state */
1247         state->config = config;
1248         state->i2c = i2c;
1249         state->demod_type = TDA1004X_DEMOD_TDA10045;
1250
1251         /* check if the demod is there */
1252         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1253                 kfree(state);
1254                 return NULL;
1255         }
1256
1257         /* create dvb_frontend */
1258         memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1259         state->frontend.demodulator_priv = state;
1260         return &state->frontend;
1261 }
1262
1263 static struct dvb_frontend_ops tda10046_ops = {
1264         .info = {
1265                 .name = "Philips TDA10046H DVB-T",
1266                 .type = FE_OFDM,
1267                 .frequency_min = 51000000,
1268                 .frequency_max = 858000000,
1269                 .frequency_stepsize = 166667,
1270                 .caps =
1271                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1272                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1273                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1274                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1275         },
1276
1277         .release = tda1004x_release,
1278
1279         .init = tda10046_init,
1280         .sleep = tda1004x_sleep,
1281         .write = tda1004x_write,
1282         .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1283
1284         .set_frontend = tda1004x_set_fe,
1285         .get_frontend = tda1004x_get_fe,
1286         .get_tune_settings = tda1004x_get_tune_settings,
1287
1288         .read_status = tda1004x_read_status,
1289         .read_ber = tda1004x_read_ber,
1290         .read_signal_strength = tda1004x_read_signal_strength,
1291         .read_snr = tda1004x_read_snr,
1292         .read_ucblocks = tda1004x_read_ucblocks,
1293 };
1294
1295 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1296                                      struct i2c_adapter* i2c)
1297 {
1298         struct tda1004x_state *state;
1299
1300         /* allocate memory for the internal state */
1301         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1302         if (!state)
1303                 return NULL;
1304
1305         /* setup the state */
1306         state->config = config;
1307         state->i2c = i2c;
1308         state->demod_type = TDA1004X_DEMOD_TDA10046;
1309
1310         /* check if the demod is there */
1311         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1312                 kfree(state);
1313                 return NULL;
1314         }
1315
1316         /* create dvb_frontend */
1317         memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1318         state->frontend.demodulator_priv = state;
1319         return &state->frontend;
1320 }
1321
1322 module_param(debug, int, 0644);
1323 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1324
1325 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1326 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1327 MODULE_LICENSE("GPL");
1328
1329 EXPORT_SYMBOL(tda10045_attach);
1330 EXPORT_SYMBOL(tda10046_attach);