drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  33  */
  34
  35 #include <linux/init.h>
  36
  37 #include <ib_verbs.h>
  38 #include <ib_cache.h>
  39 #include <ib_pack.h>
  40
  41 #include "mthca_dev.h"
  42 #include "mthca_cmd.h"
  43 #include "mthca_memfree.h"
  44
  45 enum {
  46         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  47         MTHCA_ACK_REQ_FREQ       = 10,
  48         MTHCA_FLIGHT_LIMIT       = 9,
  49         MTHCA_UD_HEADER_SIZE     = 72 /* largest UD header possible */
  50 };
  51
  52 enum {
  53         MTHCA_QP_STATE_RST  = 0,
  54         MTHCA_QP_STATE_INIT = 1,
  55         MTHCA_QP_STATE_RTR  = 2,
  56         MTHCA_QP_STATE_RTS  = 3,
  57         MTHCA_QP_STATE_SQE  = 4,
  58         MTHCA_QP_STATE_SQD  = 5,
  59         MTHCA_QP_STATE_ERR  = 6,
  60         MTHCA_QP_STATE_DRAINING = 7
  61 };
  62
  63 enum {
  64         MTHCA_QP_ST_RC  = 0x0,
  65         MTHCA_QP_ST_UC  = 0x1,
  66         MTHCA_QP_ST_RD  = 0x2,
  67         MTHCA_QP_ST_UD  = 0x3,
  68         MTHCA_QP_ST_MLX = 0x7
  69 };
  70
  71 enum {
  72         MTHCA_QP_PM_MIGRATED = 0x3,
  73         MTHCA_QP_PM_ARMED    = 0x0,
  74         MTHCA_QP_PM_REARM    = 0x1
  75 };
  76
  77 enum {
  78         /* qp_context flags */
  79         MTHCA_QP_BIT_DE  = 1 <<  8,
  80         /* params1 */
  81         MTHCA_QP_BIT_SRE = 1 << 15,
  82         MTHCA_QP_BIT_SWE = 1 << 14,
  83         MTHCA_QP_BIT_SAE = 1 << 13,
  84         MTHCA_QP_BIT_SIC = 1 <<  4,
  85         MTHCA_QP_BIT_SSC = 1 <<  3,
  86         /* params2 */
  87         MTHCA_QP_BIT_RRE = 1 << 15,
  88         MTHCA_QP_BIT_RWE = 1 << 14,
  89         MTHCA_QP_BIT_RAE = 1 << 13,
  90         MTHCA_QP_BIT_RIC = 1 <<  4,
  91         MTHCA_QP_BIT_RSC = 1 <<  3
  92 };
  93
  94 struct mthca_qp_path {
  95         u32 port_pkey;
  96         u8  rnr_retry;
  97         u8  g_mylmc;
  98         u16 rlid;
  99         u8  ackto;
 100         u8  mgid_index;
 101         u8  static_rate;
 102         u8  hop_limit;
 103         u32 sl_tclass_flowlabel;
 104         u8  rgid[16];
 105 } __attribute__((packed));
 106
 107 struct mthca_qp_context {
 108         u32 flags;
 109         u32 tavor_sched_queue;  /* Reserved on Arbel */
 110         u8  mtu_msgmax;
 111         u8  rq_size_stride;     /* Reserved on Tavor */
 112         u8  sq_size_stride;     /* Reserved on Tavor */
 113         u8  rlkey_arbel_sched_queue;    /* Reserved on Tavor */
 114         u32 usr_page;
 115         u32 local_qpn;
 116         u32 remote_qpn;
 117         u32 reserved1[2];
 118         struct mthca_qp_path pri_path;
 119         struct mthca_qp_path alt_path;
 120         u32 rdd;
 121         u32 pd;
 122         u32 wqe_base;
 123         u32 wqe_lkey;
 124         u32 params1;
 125         u32 reserved2;
 126         u32 next_send_psn;
 127         u32 cqn_snd;
 128         u32 snd_wqe_base_l;     /* Next send WQE on Tavor */
 129         u32 snd_db_index;       /* (debugging only entries) */
 130         u32 last_acked_psn;
 131         u32 ssn;
 132         u32 params2;
 133         u32 rnr_nextrecvpsn;
 134         u32 ra_buff_indx;
 135         u32 cqn_rcv;
 136         u32 rcv_wqe_base_l;     /* Next recv WQE on Tavor */
 137         u32 rcv_db_index;       /* (debugging only entries) */
 138         u32 qkey;
 139         u32 srqn;
 140         u32 rmsn;
 141         u16 rq_wqe_counter;     /* reserved on Tavor */
 142         u16 sq_wqe_counter;     /* reserved on Tavor */
 143         u32 reserved3[18];
 144 } __attribute__((packed));
 145
 146 struct mthca_qp_param {
 147         u32 opt_param_mask;
 148         u32 reserved1;
 149         struct mthca_qp_context context;
 150         u32 reserved2[62];
 151 } __attribute__((packed));
 152
 153 enum {
 154         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 155         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 156         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 157         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 158         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 159         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 160         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 161         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 162         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 163         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 164         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 165         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 166         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 167         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 168         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 169         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 170         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 171 };
 172
 173 enum {
 174         MTHCA_NEXT_DBD       = 1 << 7,
 175         MTHCA_NEXT_FENCE     = 1 << 6,
 176         MTHCA_NEXT_CQ_UPDATE = 1 << 3,
 177         MTHCA_NEXT_EVENT_GEN = 1 << 2,
 178         MTHCA_NEXT_SOLICIT   = 1 << 1,
 179
 180         MTHCA_MLX_VL15       = 1 << 17,
 181         MTHCA_MLX_SLR        = 1 << 16
 182 };
 183
 184 struct mthca_next_seg {
 185         u32 nda_op;             /* [31:6] next WQE [4:0] next opcode */
 186         u32 ee_nds;             /* [31:8] next EE  [7] DBD [6] F [5:0] next WQE size */
 187         u32 flags;              /* [3] CQ [2] Event [1] Solicit */
 188         u32 imm;                /* immediate data */
 189 };
 190
 191 struct mthca_tavor_ud_seg {
 192         u32 reserved1;
 193         u32 lkey;
 194         u64 av_addr;
 195         u32 reserved2[4];
 196         u32 dqpn;
 197         u32 qkey;
 198         u32 reserved3[2];
 199 };
 200
 201 struct mthca_arbel_ud_seg {
 202         u32 av[8];
 203         u32 dqpn;
 204         u32 qkey;
 205         u32 reserved[2];
 206 };
 207
 208 struct mthca_bind_seg {
 209         u32 flags;              /* [31] Atomic [30] rem write [29] rem read */
 210         u32 reserved;
 211         u32 new_rkey;
 212         u32 lkey;
 213         u64 addr;
 214         u64 length;
 215 };
 216
 217 struct mthca_raddr_seg {
 218         u64 raddr;
 219         u32 rkey;
 220         u32 reserved;
 221 };
 222
 223 struct mthca_atomic_seg {
 224         u64 swap_add;
 225         u64 compare;
 226 };
 227
 228 struct mthca_data_seg {
 229         u32 byte_count;
 230         u32 lkey;
 231         u64 addr;
 232 };
 233
 234 struct mthca_mlx_seg {
 235         u32 nda_op;
 236         u32 nds;
 237         u32 flags;              /* [17] VL15 [16] SLR [14:12] static rate
 238                                    [11:8] SL [3] C [2] E */
 239         u16 rlid;
 240         u16 vcrc;
 241 };
 242
 243 static const u8 mthca_opcode[] = {
 244         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 245         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 246         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 247         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 248         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 249         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 250         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 251 };
 252
 253 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 254 {
 255         return qp->qpn >= dev->qp_table.sqp_start &&
 256                 qp->qpn <= dev->qp_table.sqp_start + 3;
 257 }
 258
 259 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 260 {
 261         return qp->qpn >= dev->qp_table.sqp_start &&
 262                 qp->qpn <= dev->qp_table.sqp_start + 1;
 263 }
 264
 265 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 266 {
 267         if (qp->is_direct)
 268                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 269         else
 270                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 271                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 272 }
 273
 274 static void *get_send_wqe(struct mthca_qp *qp, int n)
 275 {
 276         if (qp->is_direct)
 277                 return qp->queue.direct.buf + qp->send_wqe_offset +
 278                         (n << qp->sq.wqe_shift);
 279         else
 280                 return qp->queue.page_list[(qp->send_wqe_offset +
 281                                             (n << qp->sq.wqe_shift)) >>
 282                                            PAGE_SHIFT].buf +
 283                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 284                          (PAGE_SIZE - 1));
 285 }
 286
 287 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 288                     enum ib_event_type event_type)
 289 {
 290         struct mthca_qp *qp;
 291         struct ib_event event;
 292
 293         spin_lock(&dev->qp_table.lock);
 294         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 295         if (qp)
 296                 atomic_inc(&qp->refcount);
 297         spin_unlock(&dev->qp_table.lock);
 298
 299         if (!qp) {
 300                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 301                 return;
 302         }
 303
 304         event.device      = &dev->ib_dev;
 305         event.event       = event_type;
 306         event.element.qp  = &qp->ibqp;
 307         if (qp->ibqp.event_handler)
 308                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 309
 310         if (atomic_dec_and_test(&qp->refcount))
 311                 wake_up(&qp->wait);
 312 }
 313
 314 static int to_mthca_state(enum ib_qp_state ib_state)
 315 {
 316         switch (ib_state) {
 317         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 318         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 319         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 320         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 321         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 322         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 323         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 324         default:                return -1;
 325         }
 326 }
 327
 328 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 329
 330 static int to_mthca_st(int transport)
 331 {
 332         switch (transport) {
 333         case RC:  return MTHCA_QP_ST_RC;
 334         case UC:  return MTHCA_QP_ST_UC;
 335         case UD:  return MTHCA_QP_ST_UD;
 336         case RD:  return MTHCA_QP_ST_RD;
 337         case MLX: return MTHCA_QP_ST_MLX;
 338         default:  return -1;
 339         }
 340 }
 341
 342 static const struct {
 343         int trans;
 344         u32 req_param[NUM_TRANS];
 345         u32 opt_param[NUM_TRANS];
 346 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
 347         [IB_QPS_RESET] = {
 348                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 349                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 350                 [IB_QPS_INIT]  = {
 351                         .trans = MTHCA_TRANS_RST2INIT,
 352                         .req_param = {
 353                                 [UD]  = (IB_QP_PKEY_INDEX |
 354                                          IB_QP_PORT       |
 355                                          IB_QP_QKEY),
 356                                 [RC]  = (IB_QP_PKEY_INDEX |
 357                                          IB_QP_PORT       |
 358                                          IB_QP_ACCESS_FLAGS),
 359                                 [MLX] = (IB_QP_PKEY_INDEX |
 360                                          IB_QP_QKEY),
 361                         },
 362                         /* bug-for-bug compatibility with VAPI: */
 363                         .opt_param = {
 364                                 [MLX] = IB_QP_PORT
 365                         }
 366                 },
 367         },
 368         [IB_QPS_INIT]  = {
 369                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 370                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 371                 [IB_QPS_INIT]  = {
 372                         .trans = MTHCA_TRANS_INIT2INIT,
 373                         .opt_param = {
 374                                 [UD]  = (IB_QP_PKEY_INDEX |
 375                                          IB_QP_PORT       |
 376                                          IB_QP_QKEY),
 377                                 [RC]  = (IB_QP_PKEY_INDEX |
 378                                          IB_QP_PORT       |
 379                                          IB_QP_ACCESS_FLAGS),
 380                                 [MLX] = (IB_QP_PKEY_INDEX |
 381                                          IB_QP_QKEY),
 382                         }
 383                 },
 384                 [IB_QPS_RTR]   = {
 385                         .trans = MTHCA_TRANS_INIT2RTR,
 386                         .req_param = {
 387                                 [RC]  = (IB_QP_AV                  |
 388                                          IB_QP_PATH_MTU            |
 389                                          IB_QP_DEST_QPN            |
 390                                          IB_QP_RQ_PSN              |
 391                                          IB_QP_MAX_DEST_RD_ATOMIC  |
 392                                          IB_QP_MIN_RNR_TIMER),
 393                         },
 394                         .opt_param = {
 395                                 [UD]  = (IB_QP_PKEY_INDEX |
 396                                          IB_QP_QKEY),
 397                                 [RC]  = (IB_QP_ALT_PATH     |
 398                                          IB_QP_ACCESS_FLAGS |
 399                                          IB_QP_PKEY_INDEX),
 400                                 [MLX] = (IB_QP_PKEY_INDEX |
 401                                          IB_QP_QKEY),
 402                         }
 403                 }
 404         },
 405         [IB_QPS_RTR]   = {
 406                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 407                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 408                 [IB_QPS_RTS]   = {
 409                         .trans = MTHCA_TRANS_RTR2RTS,
 410                         .req_param = {
 411                                 [UD]  = IB_QP_SQ_PSN,
 412                                 [RC]  = (IB_QP_TIMEOUT           |
 413                                          IB_QP_RETRY_CNT         |
 414                                          IB_QP_RNR_RETRY         |
 415                                          IB_QP_SQ_PSN            |
 416                                          IB_QP_MAX_QP_RD_ATOMIC),
 417                                 [MLX] = IB_QP_SQ_PSN,
 418                         },
 419                         .opt_param = {
 420                                 [UD]  = (IB_QP_CUR_STATE             |
 421                                          IB_QP_QKEY),
 422                                 [RC]  = (IB_QP_CUR_STATE             |
 423                                          IB_QP_ALT_PATH              |
 424                                          IB_QP_ACCESS_FLAGS          |
 425                                          IB_QP_PKEY_INDEX            |
 426                                          IB_QP_MIN_RNR_TIMER         |
 427                                          IB_QP_PATH_MIG_STATE),
 428                                 [MLX] = (IB_QP_CUR_STATE             |
 429                                          IB_QP_QKEY),
 430                         }
 431                 }
 432         },
 433         [IB_QPS_RTS]   = {
 434                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 435                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 436                 [IB_QPS_RTS]   = {
 437                         .trans = MTHCA_TRANS_RTS2RTS,
 438                         .opt_param = {
 439                                 [UD]  = (IB_QP_CUR_STATE             |
 440                                          IB_QP_QKEY),
 441                                 [RC]  = (IB_QP_ACCESS_FLAGS          |
 442                                          IB_QP_ALT_PATH              |
 443                                          IB_QP_PATH_MIG_STATE        |
 444                                          IB_QP_MIN_RNR_TIMER),
 445                                 [MLX] = (IB_QP_CUR_STATE             |
 446                                          IB_QP_QKEY),
 447                         }
 448                 },
 449                 [IB_QPS_SQD]   = {
 450                         .trans = MTHCA_TRANS_RTS2SQD,
 451                 },
 452         },
 453         [IB_QPS_SQD]   = {
 454                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 455                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 456                 [IB_QPS_RTS]   = {
 457                         .trans = MTHCA_TRANS_SQD2RTS,
 458                         .opt_param = {
 459                                 [UD]  = (IB_QP_CUR_STATE             |
 460                                          IB_QP_QKEY),
 461                                 [RC]  = (IB_QP_CUR_STATE             |
 462                                          IB_QP_ALT_PATH              |
 463                                          IB_QP_ACCESS_FLAGS          |
 464                                          IB_QP_MIN_RNR_TIMER         |
 465                                          IB_QP_PATH_MIG_STATE),
 466                                 [MLX] = (IB_QP_CUR_STATE             |
 467                                          IB_QP_QKEY),
 468                         }
 469                 },
 470                 [IB_QPS_SQD]   = {
 471                         .trans = MTHCA_TRANS_SQD2SQD,
 472                         .opt_param = {
 473                                 [UD]  = (IB_QP_PKEY_INDEX            |
 474                                          IB_QP_QKEY),
 475                                 [RC]  = (IB_QP_AV                    |
 476                                          IB_QP_TIMEOUT               |
 477                                          IB_QP_RETRY_CNT             |
 478                                          IB_QP_RNR_RETRY             |
 479                                          IB_QP_MAX_QP_RD_ATOMIC      |
 480                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 481                                          IB_QP_CUR_STATE             |
 482                                          IB_QP_ALT_PATH              |
 483                                          IB_QP_ACCESS_FLAGS          |
 484                                          IB_QP_PKEY_INDEX            |
 485                                          IB_QP_MIN_RNR_TIMER         |
 486                                          IB_QP_PATH_MIG_STATE),
 487                                 [MLX] = (IB_QP_PKEY_INDEX            |
 488                                          IB_QP_QKEY),
 489                         }
 490                 }
 491         },
 492         [IB_QPS_SQE]   = {
 493                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 494                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 495                 [IB_QPS_RTS]   = {
 496                         .trans = MTHCA_TRANS_SQERR2RTS,
 497                         .opt_param = {
 498                                 [UD]  = (IB_QP_CUR_STATE             |
 499                                          IB_QP_QKEY),
 500                                 [RC]  = (IB_QP_CUR_STATE             |
 501                                          IB_QP_MIN_RNR_TIMER),
 502                                 [MLX] = (IB_QP_CUR_STATE             |
 503                                          IB_QP_QKEY),
 504                         }
 505                 }
 506         },
 507         [IB_QPS_ERR] = {
 508                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 509                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
 510         }
 511 };
 512
 513 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 514                         int attr_mask)
 515 {
 516         if (attr_mask & IB_QP_PKEY_INDEX)
 517                 sqp->pkey_index = attr->pkey_index;
 518         if (attr_mask & IB_QP_QKEY)
 519                 sqp->qkey = attr->qkey;
 520         if (attr_mask & IB_QP_SQ_PSN)
 521                 sqp->send_psn = attr->sq_psn;
 522 }
 523
 524 static void init_port(struct mthca_dev *dev, int port)
 525 {
 526         int err;
 527         u8 status;
 528         struct mthca_init_ib_param param;
 529
 530         memset(&param, 0, sizeof param);
 531
 532         param.enable_1x = 1;
 533         param.enable_4x = 1;
 534         param.vl_cap    = dev->limits.vl_cap;
 535         param.mtu_cap   = dev->limits.mtu_cap;
 536         param.gid_cap   = dev->limits.gid_table_len;
 537         param.pkey_cap  = dev->limits.pkey_table_len;
 538
 539         err = mthca_INIT_IB(dev, &param, port, &status);
 540         if (err)
 541                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 542         if (status)
 543                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 544 }
 545
 546 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 547 {
 548         struct mthca_dev *dev = to_mdev(ibqp->device);
 549         struct mthca_qp *qp = to_mqp(ibqp);
 550         enum ib_qp_state cur_state, new_state;
 551         void *mailbox = NULL;
 552         struct mthca_qp_param *qp_param;
 553         struct mthca_qp_context *qp_context;
 554         u32 req_param, opt_param;
 555         u8 status;
 556         int err;
 557
 558         if (attr_mask & IB_QP_CUR_STATE) {
 559                 if (attr->cur_qp_state != IB_QPS_RTR &&
 560                     attr->cur_qp_state != IB_QPS_RTS &&
 561                     attr->cur_qp_state != IB_QPS_SQD &&
 562                     attr->cur_qp_state != IB_QPS_SQE)
 563                         return -EINVAL;
 564                 else
 565                         cur_state = attr->cur_qp_state;
 566         } else {
 567                 spin_lock_irq(&qp->sq.lock);
 568                 spin_lock(&qp->rq.lock);
 569                 cur_state = qp->state;
 570                 spin_unlock(&qp->rq.lock);
 571                 spin_unlock_irq(&qp->sq.lock);
 572         }
 573
 574         if (attr_mask & IB_QP_STATE) {
 575                if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
 576                         return -EINVAL;
 577                 new_state = attr->qp_state;
 578         } else
 579                 new_state = cur_state;
 580
 581         if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
 582                 mthca_dbg(dev, "Illegal QP transition "
 583                           "%d->%d\n", cur_state, new_state);
 584                 return -EINVAL;
 585         }
 586
 587         req_param = state_table[cur_state][new_state].req_param[qp->transport];
 588         opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
 589
 590         if ((req_param & attr_mask) != req_param) {
 591                 mthca_dbg(dev, "QP transition "
 592                           "%d->%d missing req attr 0x%08x\n",
 593                           cur_state, new_state,
 594                           req_param & ~attr_mask);
 595                 return -EINVAL;
 596         }
 597
 598         if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
 599                 mthca_dbg(dev, "QP transition (transport %d) "
 600                           "%d->%d has extra attr 0x%08x\n",
 601                           qp->transport,
 602                           cur_state, new_state,
 603                           attr_mask & ~(req_param | opt_param |
 604                                                  IB_QP_STATE));
 605                 return -EINVAL;
 606         }
 607
 608         mailbox = kmalloc(sizeof (*qp_param) + MTHCA_CMD_MAILBOX_EXTRA, GFP_KERNEL);
 609         if (!mailbox)
 610                 return -ENOMEM;
 611         qp_param = MAILBOX_ALIGN(mailbox);
 612         qp_context = &qp_param->context;
 613         memset(qp_param, 0, sizeof *qp_param);
 614
 615         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 616                                              (to_mthca_st(qp->transport) << 16));
 617         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 618         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 619                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 620         else {
 621                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 622                 switch (attr->path_mig_state) {
 623                 case IB_MIG_MIGRATED:
 624                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 625                         break;
 626                 case IB_MIG_REARM:
 627                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 628                         break;
 629                 case IB_MIG_ARMED:
 630                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 631                         break;
 632                 }
 633         }
 634
 635         /* leave tavor_sched_queue as 0 */
 636
 637         if (qp->transport == MLX || qp->transport == UD)
 638                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 639         else if (attr_mask & IB_QP_PATH_MTU)
 640                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 641
 642         if (mthca_is_memfree(dev)) {
 643                 qp_context->rq_size_stride =
 644                         ((ffs(qp->rq.max) - 1) << 3) | (qp->rq.wqe_shift - 4);
 645                 qp_context->sq_size_stride =
 646                         ((ffs(qp->sq.max) - 1) << 3) | (qp->sq.wqe_shift - 4);
 647         }
 648
 649         /* leave arbel_sched_queue as 0 */
 650
 651         qp_context->usr_page   = cpu_to_be32(dev->driver_uar.index);
 652         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 653         if (attr_mask & IB_QP_DEST_QPN) {
 654                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 655         }
 656
 657         if (qp->transport == MLX)
 658                 qp_context->pri_path.port_pkey |=
 659                         cpu_to_be32(to_msqp(qp)->port << 24);
 660         else {
 661                 if (attr_mask & IB_QP_PORT) {
 662                         qp_context->pri_path.port_pkey |=
 663                                 cpu_to_be32(attr->port_num << 24);
 664                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 665                 }
 666         }
 667
 668         if (attr_mask & IB_QP_PKEY_INDEX) {
 669                 qp_context->pri_path.port_pkey |=
 670                         cpu_to_be32(attr->pkey_index);
 671                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 672         }
 673
 674         if (attr_mask & IB_QP_RNR_RETRY) {
 675                 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
 676                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
 677         }
 678
 679         if (attr_mask & IB_QP_AV) {
 680                 qp_context->pri_path.g_mylmc     = attr->ah_attr.src_path_bits & 0x7f;
 681                 qp_context->pri_path.rlid        = cpu_to_be16(attr->ah_attr.dlid);
 682                 qp_context->pri_path.static_rate = (!!attr->ah_attr.static_rate) << 3;
 683                 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
 684                         qp_context->pri_path.g_mylmc |= 1 << 7;
 685                         qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
 686                         qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
 687                         qp_context->pri_path.sl_tclass_flowlabel =
 688                                 cpu_to_be32((attr->ah_attr.sl << 28)                |
 689                                             (attr->ah_attr.grh.traffic_class << 20) |
 690                                             (attr->ah_attr.grh.flow_label));
 691                         memcpy(qp_context->pri_path.rgid,
 692                                attr->ah_attr.grh.dgid.raw, 16);
 693                 } else {
 694                         qp_context->pri_path.sl_tclass_flowlabel =
 695                                 cpu_to_be32(attr->ah_attr.sl << 28);
 696                 }
 697                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 698         }
 699
 700         if (attr_mask & IB_QP_TIMEOUT) {
 701                 qp_context->pri_path.ackto = attr->timeout;
 702                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 703         }
 704
 705         /* XXX alt_path */
 706
 707         /* leave rdd as 0 */
 708         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 709         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 710         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 711         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 712                                              (MTHCA_FLIGHT_LIMIT << 24) |
 713                                              MTHCA_QP_BIT_SRE           |
 714                                              MTHCA_QP_BIT_SWE           |
 715                                              MTHCA_QP_BIT_SAE);
 716         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 717                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 718         if (attr_mask & IB_QP_RETRY_CNT) {
 719                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 720                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 721         }
 722
 723         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 724                 qp_context->params1 |= cpu_to_be32(min(attr->max_dest_rd_atomic ?
 725                                                        ffs(attr->max_dest_rd_atomic) - 1 : 0,
 726                                                        7) << 21);
 727                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 728         }
 729
 730         if (attr_mask & IB_QP_SQ_PSN)
 731                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 732         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 733
 734         if (mthca_is_memfree(dev)) {
 735                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 736                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 737         }
 738
 739         if (attr_mask & IB_QP_ACCESS_FLAGS) {
 740                 /*
 741                  * Only enable RDMA/atomics if we have responder
 742                  * resources set to a non-zero value.
 743                  */
 744                 if (qp->resp_depth) {
 745                         qp_context->params2 |=
 746                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE ?
 747                                             MTHCA_QP_BIT_RWE : 0);
 748                         qp_context->params2 |=
 749                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_READ ?
 750                                             MTHCA_QP_BIT_RRE : 0);
 751                         qp_context->params2 |=
 752                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC ?
 753                                             MTHCA_QP_BIT_RAE : 0);
 754                 }
 755
 756                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 757                                                         MTHCA_QP_OPTPAR_RRE |
 758                                                         MTHCA_QP_OPTPAR_RAE);
 759
 760                 qp->atomic_rd_en = attr->qp_access_flags;
 761         }
 762
 763         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 764                 u8 rra_max;
 765
 766                 if (qp->resp_depth && !attr->max_rd_atomic) {
 767                         /*
 768                          * Lowering our responder resources to zero.
 769                          * Turn off RDMA/atomics as responder.
 770                          * (RWE/RRE/RAE in params2 already zero)
 771                          */
 772                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 773                                                                 MTHCA_QP_OPTPAR_RRE |
 774                                                                 MTHCA_QP_OPTPAR_RAE);
 775                 }
 776
 777                 if (!qp->resp_depth && attr->max_rd_atomic) {
 778                         /*
 779                          * Increasing our responder resources from
 780                          * zero.  Turn on RDMA/atomics as appropriate.
 781                          */
 782                         qp_context->params2 |=
 783                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_WRITE ?
 784                                             MTHCA_QP_BIT_RWE : 0);
 785                         qp_context->params2 |=
 786                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_READ ?
 787                                             MTHCA_QP_BIT_RRE : 0);
 788                         qp_context->params2 |=
 789                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_ATOMIC ?
 790                                             MTHCA_QP_BIT_RAE : 0);
 791
 792                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 793                                                                 MTHCA_QP_OPTPAR_RRE |
 794                                                                 MTHCA_QP_OPTPAR_RAE);
 795                 }
 796
 797                 for (rra_max = 0;
 798                      1 << rra_max < attr->max_rd_atomic &&
 799                              rra_max < dev->qp_table.rdb_shift;
 800                      ++rra_max)
 801                         ; /* nothing */
 802
 803                 qp_context->params2      |= cpu_to_be32(rra_max << 21);
 804                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 805
 806                 qp->resp_depth = attr->max_rd_atomic;
 807         }
 808
 809         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 810
 811         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 812                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 813                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 814         }
 815         if (attr_mask & IB_QP_RQ_PSN)
 816                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 817
 818         qp_context->ra_buff_indx =
 819                 cpu_to_be32(dev->qp_table.rdb_base +
 820                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 821                              dev->qp_table.rdb_shift));
 822
 823         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 824
 825         if (mthca_is_memfree(dev))
 826                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 827
 828         if (attr_mask & IB_QP_QKEY) {
 829                 qp_context->qkey = cpu_to_be32(attr->qkey);
 830                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 831         }
 832
 833         err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
 834                               qp->qpn, 0, qp_param, 0, &status);
 835         if (status) {
 836                 mthca_warn(dev, "modify QP %d returned status %02x.\n",
 837                            state_table[cur_state][new_state].trans, status);
 838                 err = -EINVAL;
 839         }
 840
 841         if (!err)
 842                 qp->state = new_state;
 843
 844         kfree(mailbox);
 845
 846         if (is_sqp(dev, qp))
 847                 store_attrs(to_msqp(qp), attr, attr_mask);
 848
 849         /*
 850          * If we are moving QP0 to RTR, bring the IB link up; if we
 851          * are moving QP0 to RESET or ERROR, bring the link back down.
 852          */
 853         if (is_qp0(dev, qp)) {
 854                 if (cur_state != IB_QPS_RTR &&
 855                     new_state == IB_QPS_RTR)
 856                         init_port(dev, to_msqp(qp)->port);
 857
 858                 if (cur_state != IB_QPS_RESET &&
 859                     cur_state != IB_QPS_ERR &&
 860                     (new_state == IB_QPS_RESET ||
 861                      new_state == IB_QPS_ERR))
 862                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 863         }
 864
 865         return err;
 866 }
 867
 868 /*
 869  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 870  * rq.max_gs and sq.max_gs must all be assigned.
 871  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 872  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 873  * queue)
 874  */
 875 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 876                                struct mthca_pd *pd,
 877                                struct mthca_qp *qp)
 878 {
 879         int size;
 880         int i;
 881         int npages, shift;
 882         dma_addr_t t;
 883         u64 *dma_list = NULL;
 884         int err = -ENOMEM;
 885
 886         size = sizeof (struct mthca_next_seg) +
 887                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 888
 889         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 890              qp->rq.wqe_shift++)
 891                 ; /* nothing */
 892
 893         size = sizeof (struct mthca_next_seg) +
 894                 qp->sq.max_gs * sizeof (struct mthca_data_seg);
 895         switch (qp->transport) {
 896         case MLX:
 897                 size += 2 * sizeof (struct mthca_data_seg);
 898                 break;
 899         case UD:
 900                 if (mthca_is_memfree(dev))
 901                         size += sizeof (struct mthca_arbel_ud_seg);
 902                 else
 903                         size += sizeof (struct mthca_tavor_ud_seg);
 904                 break;
 905         default:
 906                 /* bind seg is as big as atomic + raddr segs */
 907                 size += sizeof (struct mthca_bind_seg);
 908         }
 909
 910         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 911              qp->sq.wqe_shift++)
 912                 ; /* nothing */
 913
 914         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 915                                     1 << qp->sq.wqe_shift);
 916         size = PAGE_ALIGN(qp->send_wqe_offset +
 917                           (qp->sq.max << qp->sq.wqe_shift));
 918
 919         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
 920                            GFP_KERNEL);
 921         if (!qp->wrid)
 922                 goto err_out;
 923
 924         if (size <= MTHCA_MAX_DIRECT_QP_SIZE) {
 925                 qp->is_direct = 1;
 926                 npages = 1;
 927                 shift = get_order(size) + PAGE_SHIFT;
 928
 929                 if (0)
 930                         mthca_dbg(dev, "Creating direct QP of size %d (shift %d)\n",
 931                                   size, shift);
 932
 933                 qp->queue.direct.buf = pci_alloc_consistent(dev->pdev, size, &t);
 934                 if (!qp->queue.direct.buf)
 935                         goto err_out;
 936
 937                 pci_unmap_addr_set(&qp->queue.direct, mapping, t);
 938
 939                 memset(qp->queue.direct.buf, 0, size);
 940
 941                 while (t & ((1 << shift) - 1)) {
 942                         --shift;
 943                         npages *= 2;
 944                 }
 945
 946                 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
 947                 if (!dma_list)
 948                         goto err_out_free;
 949
 950                 for (i = 0; i < npages; ++i)
 951                         dma_list[i] = t + i * (1 << shift);
 952         } else {
 953                 qp->is_direct = 0;
 954                 npages = size / PAGE_SIZE;
 955                 shift = PAGE_SHIFT;
 956
 957                 if (0)
 958                         mthca_dbg(dev, "Creating indirect QP with %d pages\n", npages);
 959
 960                 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
 961                 if (!dma_list)
 962                         goto err_out;
 963
 964                 qp->queue.page_list = kmalloc(npages *
 965                                               sizeof *qp->queue.page_list,
 966                                               GFP_KERNEL);
 967                 if (!qp->queue.page_list)
 968                         goto err_out;
 969
 970                 for (i = 0; i < npages; ++i) {
 971                         qp->queue.page_list[i].buf =
 972                                 pci_alloc_consistent(dev->pdev, PAGE_SIZE, &t);
 973                         if (!qp->queue.page_list[i].buf)
 974                                 goto err_out_free;
 975
 976                         memset(qp->queue.page_list[i].buf, 0, PAGE_SIZE);
 977
 978                         pci_unmap_addr_set(&qp->queue.page_list[i], mapping, t);
 979                         dma_list[i] = t;
 980                 }
 981         }
 982
 983         err = mthca_mr_alloc_phys(dev, pd->pd_num, dma_list, shift,
 984                                   npages, 0, size,
 985                                   MTHCA_MPT_FLAG_LOCAL_READ,
 986                                   &qp->mr);
 987         if (err)
 988                 goto err_out_free;
 989
 990         kfree(dma_list);
 991         return 0;
 992
 993  err_out_free:
 994         if (qp->is_direct) {
 995                 pci_free_consistent(dev->pdev, size,
 996                                     qp->queue.direct.buf,
 997                                     pci_unmap_addr(&qp->queue.direct, mapping));
 998         } else
 999                 for (i = 0; i < npages; ++i) {
1000                         if (qp->queue.page_list[i].buf)
1001                                 pci_free_consistent(dev->pdev, PAGE_SIZE,
1002                                                     qp->queue.page_list[i].buf,
1003                                                     pci_unmap_addr(&qp->queue.page_list[i],
1004                                                                    mapping));
1005
1006                 }
1007
1008  err_out:
1009         kfree(qp->wrid);
1010         kfree(dma_list);
1011         return err;
1012 }
1013
1014 static int mthca_alloc_memfree(struct mthca_dev *dev,
1015                                struct mthca_qp *qp)
1016 {
1017         int ret = 0;
1018
1019         if (mthca_is_memfree(dev)) {
1020                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1021                 if (ret)
1022                         return ret;
1023
1024                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1025                 if (ret)
1026                         goto err_qpc;
1027
1028                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1029                                                  qp->qpn, &qp->rq.db);
1030                 if (qp->rq.db_index < 0) {
1031                         ret = -ENOMEM;
1032                         goto err_eqpc;
1033                 }
1034
1035                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1036                                                  qp->qpn, &qp->sq.db);
1037                 if (qp->sq.db_index < 0) {
1038                         ret = -ENOMEM;
1039                         goto err_rq_db;
1040                 }
1041         }
1042
1043         return 0;
1044
1045 err_rq_db:
1046         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1047
1048 err_eqpc:
1049         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1050
1051 err_qpc:
1052         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1053
1054         return ret;
1055 }
1056
1057 static void mthca_free_memfree(struct mthca_dev *dev,
1058                                struct mthca_qp *qp)
1059 {
1060         if (mthca_is_memfree(dev)) {
1061                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1062                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1063                 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1064                 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1065         }
1066 }
1067
1068 static void mthca_wq_init(struct mthca_wq* wq)
1069 {
1070         spin_lock_init(&wq->lock);
1071         wq->next_ind  = 0;
1072         wq->last_comp = wq->max - 1;
1073         wq->head      = 0;
1074         wq->tail      = 0;
1075         wq->last      = NULL;
1076 }
1077
1078 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1079                                  struct mthca_pd *pd,
1080                                  struct mthca_cq *send_cq,
1081                                  struct mthca_cq *recv_cq,
1082                                  enum ib_sig_type send_policy,
1083                                  struct mthca_qp *qp)
1084 {
1085         struct mthca_next_seg *wqe;
1086         int ret;
1087         int i;
1088
1089         atomic_set(&qp->refcount, 1);
1090         qp->state        = IB_QPS_RESET;
1091         qp->atomic_rd_en = 0;
1092         qp->resp_depth   = 0;
1093         qp->sq_policy    = send_policy;
1094         mthca_wq_init(&qp->sq);
1095         mthca_wq_init(&qp->rq);
1096
1097         ret = mthca_alloc_memfree(dev, qp);
1098         if (ret)
1099                 return ret;
1100
1101         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1102         if (ret) {
1103                 mthca_free_memfree(dev, qp);
1104                 return ret;
1105         }
1106
1107         if (mthca_is_memfree(dev)) {
1108                 for (i = 0; i < qp->rq.max; ++i) {
1109                         wqe = get_recv_wqe(qp, i);
1110                         wqe->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1111                                                   qp->rq.wqe_shift);
1112                         wqe->ee_nds = cpu_to_be32(1 << (qp->rq.wqe_shift - 4));
1113                 }
1114
1115                 for (i = 0; i < qp->sq.max; ++i) {
1116                         wqe = get_send_wqe(qp, i);
1117                         wqe->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1118                                                    qp->sq.wqe_shift) +
1119                                                   qp->send_wqe_offset);
1120                 }
1121         }
1122
1123         return 0;
1124 }
1125
1126 static void mthca_align_qp_size(struct mthca_dev *dev, struct mthca_qp *qp)
1127 {
1128         int i;
1129
1130         if (!mthca_is_memfree(dev))
1131                 return;
1132
1133         for (i = 0; 1 << i < qp->rq.max; ++i)
1134                 ; /* nothing */
1135
1136         qp->rq.max = 1 << i;
1137
1138         for (i = 0; 1 << i < qp->sq.max; ++i)
1139                 ; /* nothing */
1140
1141         qp->sq.max = 1 << i;
1142 }
1143
1144 int mthca_alloc_qp(struct mthca_dev *dev,
1145                    struct mthca_pd *pd,
1146                    struct mthca_cq *send_cq,
1147                    struct mthca_cq *recv_cq,
1148                    enum ib_qp_type type,
1149                    enum ib_sig_type send_policy,
1150                    struct mthca_qp *qp)
1151 {
1152         int err;
1153
1154         mthca_align_qp_size(dev, qp);
1155
1156         switch (type) {
1157         case IB_QPT_RC: qp->transport = RC; break;
1158         case IB_QPT_UC: qp->transport = UC; break;
1159         case IB_QPT_UD: qp->transport = UD; break;
1160         default: return -EINVAL;
1161         }
1162
1163         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1164         if (qp->qpn == -1)
1165                 return -ENOMEM;
1166
1167         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1168                                     send_policy, qp);
1169         if (err) {
1170                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1171                 return err;
1172         }
1173
1174         spin_lock_irq(&dev->qp_table.lock);
1175         mthca_array_set(&dev->qp_table.qp,
1176                         qp->qpn & (dev->limits.num_qps - 1), qp);
1177         spin_unlock_irq(&dev->qp_table.lock);
1178
1179         return 0;
1180 }
1181
1182 int mthca_alloc_sqp(struct mthca_dev *dev,
1183                     struct mthca_pd *pd,
1184                     struct mthca_cq *send_cq,
1185                     struct mthca_cq *recv_cq,
1186                     enum ib_sig_type send_policy,
1187                     int qpn,
1188                     int port,
1189                     struct mthca_sqp *sqp)
1190 {
1191         int err = 0;
1192         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1193
1194         mthca_align_qp_size(dev, &sqp->qp);
1195
1196         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1197         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1198                                              &sqp->header_dma, GFP_KERNEL);
1199         if (!sqp->header_buf)
1200                 return -ENOMEM;
1201
1202         spin_lock_irq(&dev->qp_table.lock);
1203         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1204                 err = -EBUSY;
1205         else
1206                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1207         spin_unlock_irq(&dev->qp_table.lock);
1208
1209         if (err)
1210                 goto err_out;
1211
1212         sqp->port = port;
1213         sqp->qp.qpn       = mqpn;
1214         sqp->qp.transport = MLX;
1215
1216         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1217                                     send_policy, &sqp->qp);
1218         if (err)
1219                 goto err_out_free;
1220
1221         atomic_inc(&pd->sqp_count);
1222
1223         return 0;
1224
1225  err_out_free:
1226         /*
1227          * Lock CQs here, so that CQ polling code can do QP lookup
1228          * without taking a lock.
1229          */
1230         spin_lock_irq(&send_cq->lock);
1231         if (send_cq != recv_cq)
1232                 spin_lock(&recv_cq->lock);
1233
1234         spin_lock(&dev->qp_table.lock);
1235         mthca_array_clear(&dev->qp_table.qp, mqpn);
1236         spin_unlock(&dev->qp_table.lock);
1237
1238         if (send_cq != recv_cq)
1239                 spin_unlock(&recv_cq->lock);
1240         spin_unlock_irq(&send_cq->lock);
1241
1242  err_out:
1243         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1244                           sqp->header_buf, sqp->header_dma);
1245
1246         return err;
1247 }
1248
1249 void mthca_free_qp(struct mthca_dev *dev,
1250                    struct mthca_qp *qp)
1251 {
1252         u8 status;
1253         int size;
1254         int i;
1255         struct mthca_cq *send_cq;
1256         struct mthca_cq *recv_cq;
1257
1258         send_cq = to_mcq(qp->ibqp.send_cq);
1259         recv_cq = to_mcq(qp->ibqp.recv_cq);
1260
1261         /*
1262          * Lock CQs here, so that CQ polling code can do QP lookup
1263          * without taking a lock.
1264          */
1265         spin_lock_irq(&send_cq->lock);
1266         if (send_cq != recv_cq)
1267                 spin_lock(&recv_cq->lock);
1268
1269         spin_lock(&dev->qp_table.lock);
1270         mthca_array_clear(&dev->qp_table.qp,
1271                           qp->qpn & (dev->limits.num_qps - 1));
1272         spin_unlock(&dev->qp_table.lock);
1273
1274         if (send_cq != recv_cq)
1275                 spin_unlock(&recv_cq->lock);
1276         spin_unlock_irq(&send_cq->lock);
1277
1278         atomic_dec(&qp->refcount);
1279         wait_event(qp->wait, !atomic_read(&qp->refcount));
1280
1281         if (qp->state != IB_QPS_RESET)
1282                 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1283
1284         mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn);
1285         if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1286                 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn);
1287
1288         mthca_free_mr(dev, &qp->mr);
1289
1290         size = PAGE_ALIGN(qp->send_wqe_offset +
1291                           (qp->sq.max << qp->sq.wqe_shift));
1292
1293         if (qp->is_direct) {
1294                 pci_free_consistent(dev->pdev, size,
1295                                     qp->queue.direct.buf,
1296                                     pci_unmap_addr(&qp->queue.direct, mapping));
1297         } else {
1298                 for (i = 0; i < size / PAGE_SIZE; ++i) {
1299                         pci_free_consistent(dev->pdev, PAGE_SIZE,
1300                                             qp->queue.page_list[i].buf,
1301                                             pci_unmap_addr(&qp->queue.page_list[i],
1302                                                            mapping));
1303                 }
1304         }
1305
1306         kfree(qp->wrid);
1307
1308         mthca_free_memfree(dev, qp);
1309
1310         if (is_sqp(dev, qp)) {
1311                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1312                 dma_free_coherent(&dev->pdev->dev,
1313                                   to_msqp(qp)->header_buf_size,
1314                                   to_msqp(qp)->header_buf,
1315                                   to_msqp(qp)->header_dma);
1316         } else
1317                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1318 }
1319
1320 /* Create UD header for an MLX send and build a data segment for it */
1321 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1322                             int ind, struct ib_send_wr *wr,
1323                             struct mthca_mlx_seg *mlx,
1324                             struct mthca_data_seg *data)
1325 {
1326         int header_size;
1327         int err;
1328
1329         ib_ud_header_init(256, /* assume a MAD */
1330                           sqp->ud_header.grh_present,
1331                           &sqp->ud_header);
1332
1333         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1334         if (err)
1335                 return err;
1336         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1337         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1338                                   (sqp->ud_header.lrh.destination_lid == 0xffff ?
1339                                    MTHCA_MLX_SLR : 0) |
1340                                   (sqp->ud_header.lrh.service_level << 8));
1341         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1342         mlx->vcrc = 0;
1343
1344         switch (wr->opcode) {
1345         case IB_WR_SEND:
1346                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1347                 sqp->ud_header.immediate_present = 0;
1348                 break;
1349         case IB_WR_SEND_WITH_IMM:
1350                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1351                 sqp->ud_header.immediate_present = 1;
1352                 sqp->ud_header.immediate_data = wr->imm_data;
1353                 break;
1354         default:
1355                 return -EINVAL;
1356         }
1357
1358         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1359         if (sqp->ud_header.lrh.destination_lid == 0xffff)
1360                 sqp->ud_header.lrh.source_lid = 0xffff;
1361         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1362         if (!sqp->qp.ibqp.qp_num)
1363                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1364                                    sqp->pkey_index,
1365                                    &sqp->ud_header.bth.pkey);
1366         else
1367                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1368                                    wr->wr.ud.pkey_index,
1369                                    &sqp->ud_header.bth.pkey);
1370         cpu_to_be16s(&sqp->ud_header.bth.pkey);
1371         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1372         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1373         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1374                                                sqp->qkey : wr->wr.ud.remote_qkey);
1375         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1376
1377         header_size = ib_ud_header_pack(&sqp->ud_header,
1378                                         sqp->header_buf +
1379                                         ind * MTHCA_UD_HEADER_SIZE);
1380
1381         data->byte_count = cpu_to_be32(header_size);
1382         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1383         data->addr       = cpu_to_be64(sqp->header_dma +
1384                                        ind * MTHCA_UD_HEADER_SIZE);
1385
1386         return 0;
1387 }
1388
1389 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1390                                     struct ib_cq *ib_cq)
1391 {
1392         unsigned cur;
1393         struct mthca_cq *cq;
1394
1395         cur = wq->head - wq->tail;
1396         if (likely(cur + nreq < wq->max))
1397                 return 0;
1398
1399         cq = to_mcq(ib_cq);
1400         spin_lock(&cq->lock);
1401         cur = wq->head - wq->tail;
1402         spin_unlock(&cq->lock);
1403
1404         return cur + nreq >= wq->max;
1405 }
1406
1407 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1408                           struct ib_send_wr **bad_wr)
1409 {
1410         struct mthca_dev *dev = to_mdev(ibqp->device);
1411         struct mthca_qp *qp = to_mqp(ibqp);
1412         void *wqe;
1413         void *prev_wqe;
1414         unsigned long flags;
1415         int err = 0;
1416         int nreq;
1417         int i;
1418         int size;
1419         int size0 = 0;
1420         u32 f0 = 0;
1421         int ind;
1422         u8 op0 = 0;
1423
1424         spin_lock_irqsave(&qp->sq.lock, flags);
1425
1426         /* XXX check that state is OK to post send */
1427
1428         ind = qp->sq.next_ind;
1429
1430         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1431                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1432                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1433                                         " %d max, %d nreq)\n", qp->qpn,
1434                                         qp->sq.head, qp->sq.tail,
1435                                         qp->sq.max, nreq);
1436                         err = -ENOMEM;
1437                         *bad_wr = wr;
1438                         goto out;
1439                 }
1440
1441                 wqe = get_send_wqe(qp, ind);
1442                 prev_wqe = qp->sq.last;
1443                 qp->sq.last = wqe;
1444
1445                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1446                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1447                 ((struct mthca_next_seg *) wqe)->flags =
1448                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1449                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1450                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1451                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1452                         cpu_to_be32(1);
1453                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1454                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1455                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1456
1457                 wqe += sizeof (struct mthca_next_seg);
1458                 size = sizeof (struct mthca_next_seg) / 16;
1459
1460                 switch (qp->transport) {
1461                 case RC:
1462                         switch (wr->opcode) {
1463                         case IB_WR_ATOMIC_CMP_AND_SWP:
1464                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1465                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1466                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1467                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1468                                         cpu_to_be32(wr->wr.atomic.rkey);
1469                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1470
1471                                 wqe += sizeof (struct mthca_raddr_seg);
1472
1473                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1474                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1475                                                 cpu_to_be64(wr->wr.atomic.swap);
1476                                         ((struct mthca_atomic_seg *) wqe)->compare =
1477                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1478                                 } else {
1479                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1480                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1481                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1482                                 }
1483
1484                                 wqe += sizeof (struct mthca_atomic_seg);
1485                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1486                                         sizeof (struct mthca_atomic_seg);
1487                                 break;
1488
1489                         case IB_WR_RDMA_WRITE:
1490                         case IB_WR_RDMA_WRITE_WITH_IMM:
1491                         case IB_WR_RDMA_READ:
1492                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1493                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1494                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1495                                         cpu_to_be32(wr->wr.rdma.rkey);
1496                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1497                                 wqe += sizeof (struct mthca_raddr_seg);
1498                                 size += sizeof (struct mthca_raddr_seg) / 16;
1499                                 break;
1500
1501                         default:
1502                                 /* No extra segments required for sends */
1503                                 break;
1504                         }
1505
1506                         break;
1507
1508                 case UD:
1509                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1510                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1511                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1512                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1513                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1514                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1515                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1516                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1517
1518                         wqe += sizeof (struct mthca_tavor_ud_seg);
1519                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1520                         break;
1521
1522                 case MLX:
1523                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1524                                                wqe - sizeof (struct mthca_next_seg),
1525                                                wqe);
1526                         if (err) {
1527                                 *bad_wr = wr;
1528                                 goto out;
1529                         }
1530                         wqe += sizeof (struct mthca_data_seg);
1531                         size += sizeof (struct mthca_data_seg) / 16;
1532                         break;
1533                 }
1534
1535                 if (wr->num_sge > qp->sq.max_gs) {
1536                         mthca_err(dev, "too many gathers\n");
1537                         err = -EINVAL;
1538                         *bad_wr = wr;
1539                         goto out;
1540                 }
1541
1542                 for (i = 0; i < wr->num_sge; ++i) {
1543                         ((struct mthca_data_seg *) wqe)->byte_count =
1544                                 cpu_to_be32(wr->sg_list[i].length);
1545                         ((struct mthca_data_seg *) wqe)->lkey =
1546                                 cpu_to_be32(wr->sg_list[i].lkey);
1547                         ((struct mthca_data_seg *) wqe)->addr =
1548                                 cpu_to_be64(wr->sg_list[i].addr);
1549                         wqe += sizeof (struct mthca_data_seg);
1550                         size += sizeof (struct mthca_data_seg) / 16;
1551                 }
1552
1553                 /* Add one more inline data segment for ICRC */
1554                 if (qp->transport == MLX) {
1555                         ((struct mthca_data_seg *) wqe)->byte_count =
1556                                 cpu_to_be32((1 << 31) | 4);
1557                         ((u32 *) wqe)[1] = 0;
1558                         wqe += sizeof (struct mthca_data_seg);
1559                         size += sizeof (struct mthca_data_seg) / 16;
1560                 }
1561
1562                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1563
1564                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1565                         mthca_err(dev, "opcode invalid\n");
1566                         err = -EINVAL;
1567                         *bad_wr = wr;
1568                         goto out;
1569                 }
1570
1571                 if (prev_wqe) {
1572                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1573                                 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1574                                              qp->send_wqe_offset) |
1575                                             mthca_opcode[wr->opcode]);
1576                         wmb();
1577                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1578                                 cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1579                 }
1580
1581                 if (!size0) {
1582                         size0 = size;
1583                         op0   = mthca_opcode[wr->opcode];
1584                 }
1585
1586                 ++ind;
1587                 if (unlikely(ind >= qp->sq.max))
1588                         ind -= qp->sq.max;
1589         }
1590
1591 out:
1592         if (likely(nreq)) {
1593                 u32 doorbell[2];
1594
1595                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1596                                            qp->send_wqe_offset) | f0 | op0);
1597                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1598
1599                 wmb();
1600
1601                 mthca_write64(doorbell,
1602                               dev->kar + MTHCA_SEND_DOORBELL,
1603                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1604         }
1605
1606         qp->sq.next_ind = ind;
1607         qp->sq.head    += nreq;
1608
1609         spin_unlock_irqrestore(&qp->sq.lock, flags);
1610         return err;
1611 }
1612
1613 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1614                              struct ib_recv_wr **bad_wr)
1615 {
1616         struct mthca_dev *dev = to_mdev(ibqp->device);
1617         struct mthca_qp *qp = to_mqp(ibqp);
1618         unsigned long flags;
1619         int err = 0;
1620         int nreq;
1621         int i;
1622         int size;
1623         int size0 = 0;
1624         int ind;
1625         void *wqe;
1626         void *prev_wqe;
1627
1628         spin_lock_irqsave(&qp->rq.lock, flags);
1629
1630         /* XXX check that state is OK to post receive */
1631
1632         ind = qp->rq.next_ind;
1633
1634         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1635                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1636                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1637                                         " %d max, %d nreq)\n", qp->qpn,
1638                                         qp->rq.head, qp->rq.tail,
1639                                         qp->rq.max, nreq);
1640                         err = -ENOMEM;
1641                         *bad_wr = wr;
1642                         goto out;
1643                 }
1644
1645                 wqe = get_recv_wqe(qp, ind);
1646                 prev_wqe = qp->rq.last;
1647                 qp->rq.last = wqe;
1648
1649                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1650                 ((struct mthca_next_seg *) wqe)->ee_nds =
1651                         cpu_to_be32(MTHCA_NEXT_DBD);
1652                 ((struct mthca_next_seg *) wqe)->flags = 0;
1653
1654                 wqe += sizeof (struct mthca_next_seg);
1655                 size = sizeof (struct mthca_next_seg) / 16;
1656
1657                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1658                         err = -EINVAL;
1659                         *bad_wr = wr;
1660                         goto out;
1661                 }
1662
1663                 for (i = 0; i < wr->num_sge; ++i) {
1664                         ((struct mthca_data_seg *) wqe)->byte_count =
1665                                 cpu_to_be32(wr->sg_list[i].length);
1666                         ((struct mthca_data_seg *) wqe)->lkey =
1667                                 cpu_to_be32(wr->sg_list[i].lkey);
1668                         ((struct mthca_data_seg *) wqe)->addr =
1669                                 cpu_to_be64(wr->sg_list[i].addr);
1670                         wqe += sizeof (struct mthca_data_seg);
1671                         size += sizeof (struct mthca_data_seg) / 16;
1672                 }
1673
1674                 qp->wrid[ind] = wr->wr_id;
1675
1676                 if (likely(prev_wqe)) {
1677                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1678                                 cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1679                         wmb();
1680                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1681                                 cpu_to_be32(MTHCA_NEXT_DBD | size);
1682                 }
1683
1684                 if (!size0)
1685                         size0 = size;
1686
1687                 ++ind;
1688                 if (unlikely(ind >= qp->rq.max))
1689                         ind -= qp->rq.max;
1690         }
1691
1692 out:
1693         if (likely(nreq)) {
1694                 u32 doorbell[2];
1695
1696                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1697                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1698
1699                 wmb();
1700
1701                 mthca_write64(doorbell,
1702                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1703                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1704         }
1705
1706         qp->rq.next_ind = ind;
1707         qp->rq.head    += nreq;
1708
1709         spin_unlock_irqrestore(&qp->rq.lock, flags);
1710         return err;
1711 }
1712
1713 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1714                           struct ib_send_wr **bad_wr)
1715 {
1716         struct mthca_dev *dev = to_mdev(ibqp->device);
1717         struct mthca_qp *qp = to_mqp(ibqp);
1718         void *wqe;
1719         void *prev_wqe;
1720         unsigned long flags;
1721         int err = 0;
1722         int nreq;
1723         int i;
1724         int size;
1725         int size0 = 0;
1726         u32 f0 = 0;
1727         int ind;
1728         u8 op0 = 0;
1729
1730         spin_lock_irqsave(&qp->sq.lock, flags);
1731
1732         /* XXX check that state is OK to post send */
1733
1734         ind = qp->sq.head & (qp->sq.max - 1);
1735
1736         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1737                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1738                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1739                                         " %d max, %d nreq)\n", qp->qpn,
1740                                         qp->sq.head, qp->sq.tail,
1741                                         qp->sq.max, nreq);
1742                         err = -ENOMEM;
1743                         *bad_wr = wr;
1744                         goto out;
1745                 }
1746
1747                 wqe = get_send_wqe(qp, ind);
1748                 prev_wqe = qp->sq.last;
1749                 qp->sq.last = wqe;
1750
1751                 ((struct mthca_next_seg *) wqe)->flags =
1752                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1753                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1754                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1755                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1756                         cpu_to_be32(1);
1757                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1758                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1759                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1760
1761                 wqe += sizeof (struct mthca_next_seg);
1762                 size = sizeof (struct mthca_next_seg) / 16;
1763
1764                 switch (qp->transport) {
1765                 case RC:
1766                         switch (wr->opcode) {
1767                         case IB_WR_ATOMIC_CMP_AND_SWP:
1768                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1769                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1770                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1771                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1772                                         cpu_to_be32(wr->wr.atomic.rkey);
1773                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1774
1775                                 wqe += sizeof (struct mthca_raddr_seg);
1776
1777                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1778                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1779                                                 cpu_to_be64(wr->wr.atomic.swap);
1780                                         ((struct mthca_atomic_seg *) wqe)->compare =
1781                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1782                                 } else {
1783                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1784                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1785                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1786                                 }
1787
1788                                 wqe += sizeof (struct mthca_atomic_seg);
1789                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1790                                         sizeof (struct mthca_atomic_seg);
1791                                 break;
1792
1793                         case IB_WR_RDMA_WRITE:
1794                         case IB_WR_RDMA_WRITE_WITH_IMM:
1795                         case IB_WR_RDMA_READ:
1796                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1797                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1798                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1799                                         cpu_to_be32(wr->wr.rdma.rkey);
1800                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1801                                 wqe += sizeof (struct mthca_raddr_seg);
1802                                 size += sizeof (struct mthca_raddr_seg) / 16;
1803                                 break;
1804
1805                         default:
1806                                 /* No extra segments required for sends */
1807                                 break;
1808                         }
1809
1810                         break;
1811
1812                 case UD:
1813                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1814                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1815                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1816                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1817                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1818                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1819
1820                         wqe += sizeof (struct mthca_arbel_ud_seg);
1821                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1822                         break;
1823
1824                 case MLX:
1825                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1826                                                wqe - sizeof (struct mthca_next_seg),
1827                                                wqe);
1828                         if (err) {
1829                                 *bad_wr = wr;
1830                                 goto out;
1831                         }
1832                         wqe += sizeof (struct mthca_data_seg);
1833                         size += sizeof (struct mthca_data_seg) / 16;
1834                         break;
1835                 }
1836
1837                 if (wr->num_sge > qp->sq.max_gs) {
1838                         mthca_err(dev, "too many gathers\n");
1839                         err = -EINVAL;
1840                         *bad_wr = wr;
1841                         goto out;
1842                 }
1843
1844                 for (i = 0; i < wr->num_sge; ++i) {
1845                         ((struct mthca_data_seg *) wqe)->byte_count =
1846                                 cpu_to_be32(wr->sg_list[i].length);
1847                         ((struct mthca_data_seg *) wqe)->lkey =
1848                                 cpu_to_be32(wr->sg_list[i].lkey);
1849                         ((struct mthca_data_seg *) wqe)->addr =
1850                                 cpu_to_be64(wr->sg_list[i].addr);
1851                         wqe += sizeof (struct mthca_data_seg);
1852                         size += sizeof (struct mthca_data_seg) / 16;
1853                 }
1854
1855                 /* Add one more inline data segment for ICRC */
1856                 if (qp->transport == MLX) {
1857                         ((struct mthca_data_seg *) wqe)->byte_count =
1858                                 cpu_to_be32((1 << 31) | 4);
1859                         ((u32 *) wqe)[1] = 0;
1860                         wqe += sizeof (struct mthca_data_seg);
1861                         size += sizeof (struct mthca_data_seg) / 16;
1862                 }
1863
1864                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1865
1866                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1867                         mthca_err(dev, "opcode invalid\n");
1868                         err = -EINVAL;
1869                         *bad_wr = wr;
1870                         goto out;
1871                 }
1872
1873                 if (likely(prev_wqe)) {
1874                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1875                                 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1876                                              qp->send_wqe_offset) |
1877                                             mthca_opcode[wr->opcode]);
1878                         wmb();
1879                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1880                                 cpu_to_be32(MTHCA_NEXT_DBD | size);
1881                 }
1882
1883                 if (!size0) {
1884                         size0 = size;
1885                         op0   = mthca_opcode[wr->opcode];
1886                 }
1887
1888                 ++ind;
1889                 if (unlikely(ind >= qp->sq.max))
1890                         ind -= qp->sq.max;
1891         }
1892
1893 out:
1894         if (likely(nreq)) {
1895                 u32 doorbell[2];
1896
1897                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
1898                                           ((qp->sq.head & 0xffff) << 8) |
1899                                           f0 | op0);
1900                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1901
1902                 qp->sq.head += nreq;
1903
1904                 /*
1905                  * Make sure that descriptors are written before
1906                  * doorbell record.
1907                  */
1908                 wmb();
1909                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1910
1911                 /*
1912                  * Make sure doorbell record is written before we
1913                  * write MMIO send doorbell.
1914                  */
1915                 wmb();
1916                 mthca_write64(doorbell,
1917                               dev->kar + MTHCA_SEND_DOORBELL,
1918                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1919         }
1920
1921         spin_unlock_irqrestore(&qp->sq.lock, flags);
1922         return err;
1923 }
1924
1925 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1926                              struct ib_recv_wr **bad_wr)
1927 {
1928         struct mthca_dev *dev = to_mdev(ibqp->device);
1929         struct mthca_qp *qp = to_mqp(ibqp);
1930         unsigned long flags;
1931         int err = 0;
1932         int nreq;
1933         int ind;
1934         int i;
1935         void *wqe;
1936
1937         spin_lock_irqsave(&qp->rq.lock, flags);
1938
1939         /* XXX check that state is OK to post receive */
1940
1941         ind = qp->rq.head & (qp->rq.max - 1);
1942
1943         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1944                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1945                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1946                                         " %d max, %d nreq)\n", qp->qpn,
1947                                         qp->rq.head, qp->rq.tail,
1948                                         qp->rq.max, nreq);
1949                         err = -ENOMEM;
1950                         *bad_wr = wr;
1951                         goto out;
1952                 }
1953
1954                 wqe = get_recv_wqe(qp, ind);
1955
1956                 ((struct mthca_next_seg *) wqe)->flags = 0;
1957
1958                 wqe += sizeof (struct mthca_next_seg);
1959
1960                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1961                         err = -EINVAL;
1962                         *bad_wr = wr;
1963                         goto out;
1964                 }
1965
1966                 for (i = 0; i < wr->num_sge; ++i) {
1967                         ((struct mthca_data_seg *) wqe)->byte_count =
1968                                 cpu_to_be32(wr->sg_list[i].length);
1969                         ((struct mthca_data_seg *) wqe)->lkey =
1970                                 cpu_to_be32(wr->sg_list[i].lkey);
1971                         ((struct mthca_data_seg *) wqe)->addr =
1972                                 cpu_to_be64(wr->sg_list[i].addr);
1973                         wqe += sizeof (struct mthca_data_seg);
1974                 }
1975
1976                 if (i < qp->rq.max_gs) {
1977                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
1978                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(0x100);
1979                         ((struct mthca_data_seg *) wqe)->addr = 0;
1980                 }
1981
1982                 qp->wrid[ind] = wr->wr_id;
1983
1984                 ++ind;
1985                 if (unlikely(ind >= qp->rq.max))
1986                         ind -= qp->rq.max;
1987         }
1988 out:
1989         if (likely(nreq)) {
1990                 qp->rq.head += nreq;
1991
1992                 /*
1993                  * Make sure that descriptors are written before
1994                  * doorbell record.
1995                  */
1996                 wmb();
1997                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
1998         }
1999
2000         spin_unlock_irqrestore(&qp->rq.lock, flags);
2001         return err;
2002 }
2003
2004 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2005                        int index, int *dbd, u32 *new_wqe)
2006 {
2007         struct mthca_next_seg *next;
2008
2009         if (is_send)
2010                 next = get_send_wqe(qp, index);
2011         else
2012                 next = get_recv_wqe(qp, index);
2013
2014         if (mthca_is_memfree(dev))
2015                 *dbd = 1;
2016         else
2017                 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2018         if (next->ee_nds & cpu_to_be32(0x3f))
2019                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2020                         (next->ee_nds & cpu_to_be32(0x3f));
2021         else
2022                 *new_wqe = 0;
2023
2024         return 0;
2025 }
2026
2027 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2028 {
2029         int err;
2030         u8 status;
2031         int i;
2032
2033         spin_lock_init(&dev->qp_table.lock);
2034
2035         /*
2036          * We reserve 2 extra QPs per port for the special QPs.  The
2037          * special QP for port 1 has to be even, so round up.
2038          */
2039         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2040         err = mthca_alloc_init(&dev->qp_table.alloc,
2041                                dev->limits.num_qps,
2042                                (1 << 24) - 1,
2043                                dev->qp_table.sqp_start +
2044                                MTHCA_MAX_PORTS * 2);
2045         if (err)
2046                 return err;
2047
2048         err = mthca_array_init(&dev->qp_table.qp,
2049                                dev->limits.num_qps);
2050         if (err) {
2051                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2052                 return err;
2053         }
2054
2055         for (i = 0; i < 2; ++i) {
2056                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2057                                             dev->qp_table.sqp_start + i * 2,
2058                                             &status);
2059                 if (err)
2060                         goto err_out;
2061                 if (status) {
2062                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2063                                    "status %02x, aborting.\n",
2064                                    status);
2065                         err = -EINVAL;
2066                         goto err_out;
2067                 }
2068         }
2069         return 0;
2070
2071  err_out:
2072         for (i = 0; i < 2; ++i)
2073                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2074
2075         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2076         mthca_alloc_cleanup(&dev->qp_table.alloc);
2077
2078         return err;
2079 }
2080
2081 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2082 {
2083         int i;
2084         u8 status;
2085
2086         for (i = 0; i < 2; ++i)
2087                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2088
2089         mthca_alloc_cleanup(&dev->qp_table.alloc);
2090 }