drivers/ide/pci/pdc202xx_old.c

   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.51    Jul 27, 2007
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *  Copyright (C) 2006-2007             MontaVista Software, Inc.
   6  *  Copyright (C) 2007                  Bartlomiej Zolnierkiewicz
   7  *
   8  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   9  *  compiled into the kernel if you have more than one card installed.
  10  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
  11  *  safe chipset tuning, including this support is harmless
  12  *
  13  *  Promise Ultra66 cards with BIOS v1.11 this
  14  *  compiled into the kernel if you have more than one card installed.
  15  *
  16  *  Promise Ultra100 cards.
  17  *
  18  *  The latest chipset code will support the following ::
  19  *  Three Ultra33 controllers and 12 drives.
  20  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  21  *  The 8/4 ratio is a BIOS code limit by promise.
  22  *
  23  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  24  *
  25  */
  26
  27 /*
  28  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  29  *  Author: Frank Tiernan (frankt@promise.com)
  30  *  Released under terms of General Public License
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/delay.h>
  37 #include <linux/timer.h>
  38 #include <linux/mm.h>
  39 #include <linux/ioport.h>
  40 #include <linux/blkdev.h>
  41 #include <linux/hdreg.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/init.h>
  45 #include <linux/ide.h>
  46
  47 #include <asm/io.h>
  48 #include <asm/irq.h>
  49
  50 #define PDC202XX_DEBUG_DRIVE_INFO       0
  51
  52 static const char *pdc_quirk_drives[] = {
  53         "QUANTUM FIREBALLlct08 08",
  54         "QUANTUM FIREBALLP KA6.4",
  55         "QUANTUM FIREBALLP KA9.1",
  56         "QUANTUM FIREBALLP LM20.4",
  57         "QUANTUM FIREBALLP KX13.6",
  58         "QUANTUM FIREBALLP KX20.5",
  59         "QUANTUM FIREBALLP KX27.3",
  60         "QUANTUM FIREBALLP LM20.5",
  61         NULL
  62 };
  63
  64 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
  65
  66 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
  67 {
  68         ide_hwif_t *hwif        = HWIF(drive);
  69         struct pci_dev *dev     = hwif->pci_dev;
  70         u8 drive_pci            = 0x60 + (drive->dn << 2);
  71
  72         u8                      AP = 0, BP = 0, CP = 0;
  73         u8                      TA = 0, TB = 0, TC = 0;
  74
  75 #if PDC202XX_DEBUG_DRIVE_INFO
  76         u32                     drive_conf = 0;
  77         pci_read_config_dword(dev, drive_pci, &drive_conf);
  78 #endif
  79
  80         /*
  81          * TODO: do this once per channel
  82          */
  83         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
  84                 pdc_old_disable_66MHz_clock(hwif);
  85
  86         pci_read_config_byte(dev, drive_pci,     &AP);
  87         pci_read_config_byte(dev, drive_pci + 1, &BP);
  88         pci_read_config_byte(dev, drive_pci + 2, &CP);
  89
  90         switch(speed) {
  91                 case XFER_UDMA_5:
  92                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
  93                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
  94                 case XFER_UDMA_3:
  95                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
  96                 case XFER_UDMA_0:
  97                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
  98                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
  99                 case XFER_MW_DMA_0:     TB = 0xE0; TC = 0x0F; break;
 100                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 101                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 102                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 103                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 104                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 105                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 106                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 107                 case XFER_PIO_0:
 108                 default:                TA = 0x09; TB = 0x13; break;
 109         }
 110
 111         if (speed < XFER_SW_DMA_0) {
 112                 /*
 113                  * preserve SYNC_INT / ERDDY_EN bits while clearing
 114                  * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
 115                  */
 116                 AP &= ~0x3f;
 117                 if (drive->id->capability & 4)
 118                         AP |= 0x20;     /* set IORDY_EN bit */
 119                 if (drive->media == ide_disk)
 120                         AP |= 0x10;     /* set Prefetch_EN bit */
 121                 /* clear PB[4:0] bits of register B */
 122                 BP &= ~0x1f;
 123                 pci_write_config_byte(dev, drive_pci,     AP | TA);
 124                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 125         } else {
 126                 /* clear MB[2:0] bits of register B */
 127                 BP &= ~0xe0;
 128                 /* clear MC[3:0] bits of register C */
 129                 CP &= ~0x0f;
 130                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 131                 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
 132         }
 133
 134 #if PDC202XX_DEBUG_DRIVE_INFO
 135         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 136                 drive->name, ide_xfer_verbose(speed),
 137                 drive->dn, drive_conf);
 138         pci_read_config_dword(dev, drive_pci, &drive_conf);
 139         printk("0x%08x\n", drive_conf);
 140 #endif
 141 }
 142
 143 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 144 {
 145         pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
 146 }
 147
 148 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 149 {
 150         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 151
 152         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 153
 154         return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 155 }
 156
 157 /*
 158  * Set the control register to use the 66MHz system
 159  * clock for UDMA 3/4/5 mode operation when necessary.
 160  *
 161  * FIXME: this register is shared by both channels, some locking is needed
 162  *
 163  * It may also be possible to leave the 66MHz clock on
 164  * and readjust the timing parameters.
 165  */
 166 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 167 {
 168         unsigned long clock_reg = hwif->dma_master + 0x11;
 169         u8 clock = inb(clock_reg);
 170
 171         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 172 }
 173
 174 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 175 {
 176         unsigned long clock_reg = hwif->dma_master + 0x11;
 177         u8 clock = inb(clock_reg);
 178
 179         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 180 }
 181
 182 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
 183 {
 184         if (ide_tune_dma(drive))
 185                 return 0;
 186
 187         if (ide_use_fast_pio(drive))
 188                 ide_set_max_pio(drive);
 189
 190         return -1;
 191 }
 192
 193 static int pdc202xx_quirkproc (ide_drive_t *drive)
 194 {
 195         const char **list, *model = drive->id->model;
 196
 197         for (list = pdc_quirk_drives; *list != NULL; list++)
 198                 if (strstr(model, *list) != NULL)
 199                         return 2;
 200         return 0;
 201 }
 202
 203 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 204 {
 205         if (drive->current_speed > XFER_UDMA_2)
 206                 pdc_old_enable_66MHz_clock(drive->hwif);
 207         if (drive->media != ide_disk || drive->addressing == 1) {
 208                 struct request *rq      = HWGROUP(drive)->rq;
 209                 ide_hwif_t *hwif        = HWIF(drive);
 210                 unsigned long high_16   = hwif->dma_master;
 211                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 212                 u32 word_count  = 0;
 213                 u8 clock = inb(high_16 + 0x11);
 214
 215                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
 216                 word_count = (rq->nr_sectors << 8);
 217                 word_count = (rq_data_dir(rq) == READ) ?
 218                                         word_count | 0x05000000 :
 219                                         word_count | 0x06000000;
 220                 outl(word_count, atapi_reg);
 221         }
 222         ide_dma_start(drive);
 223 }
 224
 225 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 226 {
 227         if (drive->media != ide_disk || drive->addressing == 1) {
 228                 ide_hwif_t *hwif        = HWIF(drive);
 229                 unsigned long high_16   = hwif->dma_master;
 230                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 231                 u8 clock                = 0;
 232
 233                 outl(0, atapi_reg); /* zero out extra */
 234                 clock = inb(high_16 + 0x11);
 235                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
 236         }
 237         if (drive->current_speed > XFER_UDMA_2)
 238                 pdc_old_disable_66MHz_clock(drive->hwif);
 239         return __ide_dma_end(drive);
 240 }
 241
 242 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 243 {
 244         ide_hwif_t *hwif        = HWIF(drive);
 245         unsigned long high_16   = hwif->dma_master;
 246         u8 dma_stat             = inb(hwif->dma_status);
 247         u8 sc1d                 = inb(high_16 + 0x001d);
 248
 249         if (hwif->channel) {
 250                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 251                 if ((sc1d & 0x50) == 0x50)
 252                         goto somebody_else;
 253                 else if ((sc1d & 0x40) == 0x40)
 254                         return (dma_stat & 4) == 4;
 255         } else {
 256                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 257                 if ((sc1d & 0x05) == 0x05)
 258                         goto somebody_else;
 259                 else if ((sc1d & 0x04) == 0x04)
 260                         return (dma_stat & 4) == 4;
 261         }
 262 somebody_else:
 263         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 264 }
 265
 266 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
 267 {
 268         ide_hwif_t *hwif = HWIF(drive);
 269
 270         if (hwif->resetproc != NULL)
 271                 hwif->resetproc(drive);
 272
 273         ide_dma_lost_irq(drive);
 274 }
 275
 276 static void pdc202xx_dma_timeout(ide_drive_t *drive)
 277 {
 278         ide_hwif_t *hwif = HWIF(drive);
 279
 280         if (hwif->resetproc != NULL)
 281                 hwif->resetproc(drive);
 282
 283         ide_dma_timeout(drive);
 284 }
 285
 286 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 287 {
 288         unsigned long high_16   = hwif->dma_master;
 289         u8 udma_speed_flag      = inb(high_16 | 0x001f);
 290
 291         outb(udma_speed_flag | 0x10, high_16 | 0x001f);
 292         mdelay(100);
 293         outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
 294         mdelay(2000);   /* 2 seconds ?! */
 295
 296         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 297                 hwif->channel ? "Secondary" : "Primary");
 298 }
 299
 300 static void pdc202xx_reset (ide_drive_t *drive)
 301 {
 302         ide_hwif_t *hwif        = HWIF(drive);
 303         ide_hwif_t *mate        = hwif->mate;
 304
 305         pdc202xx_reset_host(hwif);
 306         pdc202xx_reset_host(mate);
 307
 308         ide_set_max_pio(drive);
 309 }
 310
 311 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 312                                                         const char *name)
 313 {
 314         return dev->irq;
 315 }
 316
 317 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 318 {
 319         struct pci_dev *dev = hwif->pci_dev;
 320
 321         /* PDC20265 has problems with large LBA48 requests */
 322         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 323             (dev->device == PCI_DEVICE_ID_PROMISE_20265))
 324                 hwif->rqsize = 256;
 325
 326         hwif->autodma = 0;
 327
 328         hwif->set_pio_mode = &pdc202xx_set_pio_mode;
 329         hwif->set_dma_mode = &pdc202xx_set_mode;
 330
 331         hwif->quirkproc = &pdc202xx_quirkproc;
 332
 333         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
 334                 hwif->resetproc = &pdc202xx_reset;
 335
 336         hwif->err_stops_fifo = 1;
 337
 338         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 339
 340         if (hwif->dma_base == 0)
 341                 return;
 342
 343         hwif->ultra_mask = hwif->cds->udma_mask;
 344         hwif->mwdma_mask = 0x07;
 345         hwif->swdma_mask = 0x07;
 346         hwif->atapi_dma = 1;
 347
 348         hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
 349         hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
 350         hwif->dma_timeout = &pdc202xx_dma_timeout;
 351
 352         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 353                 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 354                         hwif->cbl = pdc202xx_old_cable_detect(hwif);
 355
 356                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 357                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 358         }
 359         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 360
 361         if (!noautodma)
 362                 hwif->autodma = 1;
 363         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 364 }
 365
 366 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 367 {
 368         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 369
 370         if (hwif->channel) {
 371                 ide_setup_dma(hwif, dmabase, 8);
 372                 return;
 373         }
 374
 375         udma_speed_flag = inb(dmabase | 0x1f);
 376         primary_mode    = inb(dmabase | 0x1a);
 377         secondary_mode  = inb(dmabase | 0x1b);
 378         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 379                 "Primary %s Mode " \
 380                 "Secondary %s Mode.\n", hwif->cds->name,
 381                 (udma_speed_flag & 1) ? "EN" : "DIS",
 382                 (primary_mode & 1) ? "MASTER" : "PCI",
 383                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 384
 385 #ifdef CONFIG_PDC202XX_BURST
 386         if (!(udma_speed_flag & 1)) {
 387                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 388                         hwif->cds->name, udma_speed_flag,
 389                         (udma_speed_flag|1));
 390                 outb(udma_speed_flag | 1, dmabase | 0x1f);
 391                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
 392         }
 393 #endif /* CONFIG_PDC202XX_BURST */
 394
 395         ide_setup_dma(hwif, dmabase, 8);
 396 }
 397
 398 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
 399                                            ide_pci_device_t *d)
 400 {
 401         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 402                 u8 irq = 0, irq2 = 0;
 403                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 404                 /* 0xbc */
 405                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 406                 if (irq != irq2) {
 407                         pci_write_config_byte(dev,
 408                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 409                         printk(KERN_INFO "%s: pci-config space interrupt "
 410                                 "mirror fixed.\n", d->name);
 411                 }
 412         }
 413         return ide_setup_pci_device(dev, d);
 414 }
 415
 416 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
 417                                          ide_pci_device_t *d)
 418 {
 419         if ((dev->bus->self) &&
 420             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 421             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 422              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 423                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 424                         "attached to I2O RAID controller.\n");
 425                 return -ENODEV;
 426         }
 427         return ide_setup_pci_device(dev, d);
 428 }
 429
 430 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
 431                                          ide_pci_device_t *d)
 432 {
 433         return ide_setup_pci_device(dev, d);
 434 }
 435
 436 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
 437         {       /* 0 */
 438                 .name           = "PDC20246",
 439                 .init_setup     = init_setup_pdc202ata4,
 440                 .init_chipset   = init_chipset_pdc202xx,
 441                 .init_hwif      = init_hwif_pdc202xx,
 442                 .init_dma       = init_dma_pdc202xx,
 443                 .autodma        = AUTODMA,
 444                 .bootable       = OFF_BOARD,
 445                 .extra          = 16,
 446                 .pio_mask       = ATA_PIO4,
 447                 .udma_mask      = 0x07, /* udma0-2 */
 448         },{     /* 1 */
 449                 .name           = "PDC20262",
 450                 .init_setup     = init_setup_pdc202ata4,
 451                 .init_chipset   = init_chipset_pdc202xx,
 452                 .init_hwif      = init_hwif_pdc202xx,
 453                 .init_dma       = init_dma_pdc202xx,
 454                 .autodma        = AUTODMA,
 455                 .bootable       = OFF_BOARD,
 456                 .extra          = 48,
 457                 .pio_mask       = ATA_PIO4,
 458                 .udma_mask      = 0x1f, /* udma0-4 */
 459         },{     /* 2 */
 460                 .name           = "PDC20263",
 461                 .init_setup     = init_setup_pdc202ata4,
 462                 .init_chipset   = init_chipset_pdc202xx,
 463                 .init_hwif      = init_hwif_pdc202xx,
 464                 .init_dma       = init_dma_pdc202xx,
 465                 .autodma        = AUTODMA,
 466                 .bootable       = OFF_BOARD,
 467                 .extra          = 48,
 468                 .pio_mask       = ATA_PIO4,
 469                 .udma_mask      = 0x1f, /* udma0-4 */
 470         },{     /* 3 */
 471                 .name           = "PDC20265",
 472                 .init_setup     = init_setup_pdc20265,
 473                 .init_chipset   = init_chipset_pdc202xx,
 474                 .init_hwif      = init_hwif_pdc202xx,
 475                 .init_dma       = init_dma_pdc202xx,
 476                 .autodma        = AUTODMA,
 477                 .bootable       = OFF_BOARD,
 478                 .extra          = 48,
 479                 .pio_mask       = ATA_PIO4,
 480                 .udma_mask      = 0x3f, /* udma0-5 */
 481         },{     /* 4 */
 482                 .name           = "PDC20267",
 483                 .init_setup     = init_setup_pdc202xx,
 484                 .init_chipset   = init_chipset_pdc202xx,
 485                 .init_hwif      = init_hwif_pdc202xx,
 486                 .init_dma       = init_dma_pdc202xx,
 487                 .autodma        = AUTODMA,
 488                 .bootable       = OFF_BOARD,
 489                 .extra          = 48,
 490                 .pio_mask       = ATA_PIO4,
 491                 .udma_mask      = 0x3f, /* udma0-5 */
 492         }
 493 };
 494
 495 /**
 496  *      pdc202xx_init_one       -       called when a PDC202xx is found
 497  *      @dev: the pdc202xx device
 498  *      @id: the matching pci id
 499  *
 500  *      Called when the PCI registration layer (or the IDE initialization)
 501  *      finds a device matching our IDE device tables.
 502  */
 503
 504 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 505 {
 506         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 507
 508         return d->init_setup(dev, d);
 509 }
 510
 511 static struct pci_device_id pdc202xx_pci_tbl[] = {
 512         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 513         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 514         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 515         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 516         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 517         { 0, },
 518 };
 519 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 520
 521 static struct pci_driver driver = {
 522         .name           = "Promise_Old_IDE",
 523         .id_table       = pdc202xx_pci_tbl,
 524         .probe          = pdc202xx_init_one,
 525 };
 526
 527 static int __init pdc202xx_ide_init(void)
 528 {
 529         return ide_pci_register_driver(&driver);
 530 }
 531
 532 module_init(pdc202xx_ide_init);
 533
 534 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 535 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 536 MODULE_LICENSE("GPL");