drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Copyright (C) 2004 - 2007 Texas Instruments.
   7  *
   8  * Originally written by MontaVista Software, Inc.
   9  * Additional contributions by:
  10  *      Tony Lindgren <tony@atomide.com>
  11  *      Imre Deak <imre.deak@nokia.com>
  12  *      Juha Yrjölä <juha.yrjola@solidboot.com>
  13  *      Syed Khasim <x0khasim@ti.com>
  14  *      Nishant Menon <nm@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 #include <linux/module.h>
  32 #include <linux/delay.h>
  33 #include <linux/i2c.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/completion.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/clk.h>
  39 #include <linux/io.h>
  40 #include <linux/slab.h>
  41 #include <linux/i2c-omap.h>
  42
  43 /* I2C controller revisions */
  44 #define OMAP_I2C_REV_2                  0x20
  45
  46 /* I2C controller revisions present on specific hardware */
  47 #define OMAP_I2C_REV_ON_2430            0x36
  48 #define OMAP_I2C_REV_ON_3430            0x3C
  49 #define OMAP_I2C_REV_ON_4430            0x40
  50
  51 /* timeout waiting for the controller to respond */
  52 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  53
  54 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
  55 enum {
  56         OMAP_I2C_REV_REG = 0,
  57         OMAP_I2C_IE_REG,
  58         OMAP_I2C_STAT_REG,
  59         OMAP_I2C_IV_REG,
  60         OMAP_I2C_WE_REG,
  61         OMAP_I2C_SYSS_REG,
  62         OMAP_I2C_BUF_REG,
  63         OMAP_I2C_CNT_REG,
  64         OMAP_I2C_DATA_REG,
  65         OMAP_I2C_SYSC_REG,
  66         OMAP_I2C_CON_REG,
  67         OMAP_I2C_OA_REG,
  68         OMAP_I2C_SA_REG,
  69         OMAP_I2C_PSC_REG,
  70         OMAP_I2C_SCLL_REG,
  71         OMAP_I2C_SCLH_REG,
  72         OMAP_I2C_SYSTEST_REG,
  73         OMAP_I2C_BUFSTAT_REG,
  74         OMAP_I2C_REVNB_LO,
  75         OMAP_I2C_REVNB_HI,
  76         OMAP_I2C_IRQSTATUS_RAW,
  77         OMAP_I2C_IRQENABLE_SET,
  78         OMAP_I2C_IRQENABLE_CLR,
  79 };
  80
  81 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  82 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
  83 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
  84 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  85 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  86 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  87 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  88 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  89
  90 /* I2C Status Register (OMAP_I2C_STAT): */
  91 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
  92 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
  93 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  94 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  95 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  96 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  97 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  98 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  99 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
 100 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
 101 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
 102 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
 103
 104 /* I2C WE wakeup enable register */
 105 #define OMAP_I2C_WE_XDR_WE      (1 << 14)       /* TX drain wakup */
 106 #define OMAP_I2C_WE_RDR_WE      (1 << 13)       /* RX drain wakeup */
 107 #define OMAP_I2C_WE_AAS_WE      (1 << 9)        /* Address as slave wakeup*/
 108 #define OMAP_I2C_WE_BF_WE       (1 << 8)        /* Bus free wakeup */
 109 #define OMAP_I2C_WE_STC_WE      (1 << 6)        /* Start condition wakeup */
 110 #define OMAP_I2C_WE_GC_WE       (1 << 5)        /* General call wakeup */
 111 #define OMAP_I2C_WE_DRDY_WE     (1 << 3)        /* TX/RX data ready wakeup */
 112 #define OMAP_I2C_WE_ARDY_WE     (1 << 2)        /* Reg access ready wakeup */
 113 #define OMAP_I2C_WE_NACK_WE     (1 << 1)        /* No acknowledgment wakeup */
 114 #define OMAP_I2C_WE_AL_WE       (1 << 0)        /* Arbitration lost wakeup */
 115
 116 #define OMAP_I2C_WE_ALL         (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
 117                                 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
 118                                 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
 119                                 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
 120                                 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
 121
 122 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
 123 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
 124 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
 125 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
 126 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
 127
 128 /* I2C Configuration Register (OMAP_I2C_CON): */
 129 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
 130 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
 131 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
 132 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 133 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 134 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 135 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 136 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 137 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 138 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 139
 140 /* I2C SCL time value when Master */
 141 #define OMAP_I2C_SCLL_HSSCLL    8
 142 #define OMAP_I2C_SCLH_HSSCLH    8
 143
 144 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 145 #ifdef DEBUG
 146 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 147 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 148 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 149 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 150 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 151 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 152 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 153 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 154 #endif
 155
 156 /* OCP_SYSSTATUS bit definitions */
 157 #define SYSS_RESETDONE_MASK             (1 << 0)
 158
 159 /* OCP_SYSCONFIG bit definitions */
 160 #define SYSC_CLOCKACTIVITY_MASK         (0x3 << 8)
 161 #define SYSC_SIDLEMODE_MASK             (0x3 << 3)
 162 #define SYSC_ENAWAKEUP_MASK             (1 << 2)
 163 #define SYSC_SOFTRESET_MASK             (1 << 1)
 164 #define SYSC_AUTOIDLE_MASK              (1 << 0)
 165
 166 #define SYSC_IDLEMODE_SMART             0x2
 167 #define SYSC_CLOCKACTIVITY_FCLK         0x2
 168
 169
 170 struct omap_i2c_dev {
 171         struct device           *dev;
 172         void __iomem            *base;          /* virtual */
 173         int                     irq;
 174         int                     reg_shift;      /* bit shift for I2C register addresses */
 175         struct clk              *iclk;          /* Interface clock */
 176         struct clk              *fclk;          /* Functional clock */
 177         struct completion       cmd_complete;
 178         struct resource         *ioarea;
 179         u32                     latency;        /* maximum mpu wkup latency */
 180         void                    (*set_mpu_wkup_lat)(struct device *dev,
 181                                                     long latency);
 182         u32                     speed;          /* Speed of bus in Khz */
 183         u16                     cmd_err;
 184         u8                      *buf;
 185         u8                      *regs;
 186         size_t                  buf_len;
 187         struct i2c_adapter      adapter;
 188         u8                      fifo_size;      /* use as flag and value
 189                                                  * fifo_size==0 implies no fifo
 190                                                  * if set, should be trsh+1
 191                                                  */
 192         u8                      rev;
 193         unsigned                b_hw:1;         /* bad h/w fixes */
 194         unsigned                idle:1;
 195         u16                     iestate;        /* Saved interrupt register */
 196         u16                     pscstate;
 197         u16                     scllstate;
 198         u16                     sclhstate;
 199         u16                     bufstate;
 200         u16                     syscstate;
 201         u16                     westate;
 202 };
 203
 204 const static u8 reg_map[] = {
 205         [OMAP_I2C_REV_REG] = 0x00,
 206         [OMAP_I2C_IE_REG] = 0x01,
 207         [OMAP_I2C_STAT_REG] = 0x02,
 208         [OMAP_I2C_IV_REG] = 0x03,
 209         [OMAP_I2C_WE_REG] = 0x03,
 210         [OMAP_I2C_SYSS_REG] = 0x04,
 211         [OMAP_I2C_BUF_REG] = 0x05,
 212         [OMAP_I2C_CNT_REG] = 0x06,
 213         [OMAP_I2C_DATA_REG] = 0x07,
 214         [OMAP_I2C_SYSC_REG] = 0x08,
 215         [OMAP_I2C_CON_REG] = 0x09,
 216         [OMAP_I2C_OA_REG] = 0x0a,
 217         [OMAP_I2C_SA_REG] = 0x0b,
 218         [OMAP_I2C_PSC_REG] = 0x0c,
 219         [OMAP_I2C_SCLL_REG] = 0x0d,
 220         [OMAP_I2C_SCLH_REG] = 0x0e,
 221         [OMAP_I2C_SYSTEST_REG] = 0x0f,
 222         [OMAP_I2C_BUFSTAT_REG] = 0x10,
 223 };
 224
 225 const static u8 omap4_reg_map[] = {
 226         [OMAP_I2C_REV_REG] = 0x04,
 227         [OMAP_I2C_IE_REG] = 0x2c,
 228         [OMAP_I2C_STAT_REG] = 0x28,
 229         [OMAP_I2C_IV_REG] = 0x34,
 230         [OMAP_I2C_WE_REG] = 0x34,
 231         [OMAP_I2C_SYSS_REG] = 0x90,
 232         [OMAP_I2C_BUF_REG] = 0x94,
 233         [OMAP_I2C_CNT_REG] = 0x98,
 234         [OMAP_I2C_DATA_REG] = 0x9c,
 235         [OMAP_I2C_SYSC_REG] = 0x20,
 236         [OMAP_I2C_CON_REG] = 0xa4,
 237         [OMAP_I2C_OA_REG] = 0xa8,
 238         [OMAP_I2C_SA_REG] = 0xac,
 239         [OMAP_I2C_PSC_REG] = 0xb0,
 240         [OMAP_I2C_SCLL_REG] = 0xb4,
 241         [OMAP_I2C_SCLH_REG] = 0xb8,
 242         [OMAP_I2C_SYSTEST_REG] = 0xbC,
 243         [OMAP_I2C_BUFSTAT_REG] = 0xc0,
 244         [OMAP_I2C_REVNB_LO] = 0x00,
 245         [OMAP_I2C_REVNB_HI] = 0x04,
 246         [OMAP_I2C_IRQSTATUS_RAW] = 0x24,
 247         [OMAP_I2C_IRQENABLE_SET] = 0x2c,
 248         [OMAP_I2C_IRQENABLE_CLR] = 0x30,
 249 };
 250
 251 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 252                                       int reg, u16 val)
 253 {
 254         __raw_writew(val, i2c_dev->base +
 255                         (i2c_dev->regs[reg] << i2c_dev->reg_shift));
 256 }
 257
 258 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 259 {
 260         return __raw_readw(i2c_dev->base +
 261                                 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
 262 }
 263
 264 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
 265 {
 266         int ret;
 267
 268         dev->iclk = clk_get(dev->dev, "ick");
 269         if (IS_ERR(dev->iclk)) {
 270                 ret = PTR_ERR(dev->iclk);
 271                 dev->iclk = NULL;
 272                 return ret;
 273         }
 274
 275         dev->fclk = clk_get(dev->dev, "fck");
 276         if (IS_ERR(dev->fclk)) {
 277                 ret = PTR_ERR(dev->fclk);
 278                 if (dev->iclk != NULL) {
 279                         clk_put(dev->iclk);
 280                         dev->iclk = NULL;
 281                 }
 282                 dev->fclk = NULL;
 283                 return ret;
 284         }
 285
 286         return 0;
 287 }
 288
 289 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 290 {
 291         clk_put(dev->fclk);
 292         dev->fclk = NULL;
 293         clk_put(dev->iclk);
 294         dev->iclk = NULL;
 295 }
 296
 297 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 298 {
 299         WARN_ON(!dev->idle);
 300
 301         clk_enable(dev->iclk);
 302         clk_enable(dev->fclk);
 303         if (cpu_is_omap34xx()) {
 304                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 305                 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
 306                 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
 307                 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
 308                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
 309                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
 310                 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
 311                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 312         }
 313         dev->idle = 0;
 314
 315         /*
 316          * Don't write to this register if the IE state is 0 as it can
 317          * cause deadlock.
 318          */
 319         if (dev->iestate)
 320                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 321 }
 322
 323 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 324 {
 325         u16 iv;
 326
 327         WARN_ON(dev->idle);
 328
 329         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 330         if (dev->rev >= OMAP_I2C_REV_ON_4430)
 331                 omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1);
 332         else
 333                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
 334
 335         if (dev->rev < OMAP_I2C_REV_2) {
 336                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
 337         } else {
 338                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
 339
 340                 /* Flush posted write before the dev->idle store occurs */
 341                 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 342         }
 343         dev->idle = 1;
 344         clk_disable(dev->fclk);
 345         clk_disable(dev->iclk);
 346 }
 347
 348 static int omap_i2c_init(struct omap_i2c_dev *dev)
 349 {
 350         u16 psc = 0, scll = 0, sclh = 0, buf = 0;
 351         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 352         unsigned long fclk_rate = 12000000;
 353         unsigned long timeout;
 354         unsigned long internal_clk = 0;
 355
 356         if (dev->rev >= OMAP_I2C_REV_2) {
 357                 /* Disable I2C controller before soft reset */
 358                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 359                         omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
 360                                 ~(OMAP_I2C_CON_EN));
 361
 362                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
 363                 /* For some reason we need to set the EN bit before the
 364                  * reset done bit gets set. */
 365                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 366                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 367                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 368                          SYSS_RESETDONE_MASK)) {
 369                         if (time_after(jiffies, timeout)) {
 370                                 dev_warn(dev->dev, "timeout waiting "
 371                                                 "for controller reset\n");
 372                                 return -ETIMEDOUT;
 373                         }
 374                         msleep(1);
 375                 }
 376
 377                 /* SYSC register is cleared by the reset; rewrite it */
 378                 if (dev->rev == OMAP_I2C_REV_ON_2430) {
 379
 380                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
 381                                            SYSC_AUTOIDLE_MASK);
 382
 383                 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
 384                         dev->syscstate = SYSC_AUTOIDLE_MASK;
 385                         dev->syscstate |= SYSC_ENAWAKEUP_MASK;
 386                         dev->syscstate |= (SYSC_IDLEMODE_SMART <<
 387                               __ffs(SYSC_SIDLEMODE_MASK));
 388                         dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
 389                               __ffs(SYSC_CLOCKACTIVITY_MASK));
 390
 391                         omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
 392                                                         dev->syscstate);
 393                         /*
 394                          * Enabling all wakup sources to stop I2C freezing on
 395                          * WFI instruction.
 396                          * REVISIT: Some wkup sources might not be needed.
 397                          */
 398                         dev->westate = OMAP_I2C_WE_ALL;
 399                         if (dev->rev < OMAP_I2C_REV_ON_4430)
 400                                 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
 401                                                                 dev->westate);
 402                 }
 403         }
 404         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 405
 406         if (cpu_class_is_omap1()) {
 407                 /*
 408                  * The I2C functional clock is the armxor_ck, so there's
 409                  * no need to get "armxor_ck" separately.  Now, if OMAP2420
 410                  * always returns 12MHz for the functional clock, we can
 411                  * do this bit unconditionally.
 412                  */
 413                 fclk_rate = clk_get_rate(dev->fclk);
 414
 415                 /* TRM for 5912 says the I2C clock must be prescaled to be
 416                  * between 7 - 12 MHz. The XOR input clock is typically
 417                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 418                  *
 419                  * XOR MHz      Divider         Prescaler
 420                  * 12           1               0
 421                  * 13           2               1
 422                  * 19.2         2               1
 423                  */
 424                 if (fclk_rate > 12000000)
 425                         psc = fclk_rate / 12000000;
 426         }
 427
 428         if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
 429
 430                 /*
 431                  * HSI2C controller internal clk rate should be 19.2 Mhz for
 432                  * HS and for all modes on 2430. On 34xx we can use lower rate
 433                  * to get longer filter period for better noise suppression.
 434                  * The filter is iclk (fclk for HS) period.
 435                  */
 436                 if (dev->speed > 400 || cpu_is_omap2430())
 437                         internal_clk = 19200;
 438                 else if (dev->speed > 100)
 439                         internal_clk = 9600;
 440                 else
 441                         internal_clk = 4000;
 442                 fclk_rate = clk_get_rate(dev->fclk) / 1000;
 443
 444                 /* Compute prescaler divisor */
 445                 psc = fclk_rate / internal_clk;
 446                 psc = psc - 1;
 447
 448                 /* If configured for High Speed */
 449                 if (dev->speed > 400) {
 450                         unsigned long scl;
 451
 452                         /* For first phase of HS mode */
 453                         scl = internal_clk / 400;
 454                         fsscll = scl - (scl / 3) - 7;
 455                         fssclh = (scl / 3) - 5;
 456
 457                         /* For second phase of HS mode */
 458                         scl = fclk_rate / dev->speed;
 459                         hsscll = scl - (scl / 3) - 7;
 460                         hssclh = (scl / 3) - 5;
 461                 } else if (dev->speed > 100) {
 462                         unsigned long scl;
 463
 464                         /* Fast mode */
 465                         scl = internal_clk / dev->speed;
 466                         fsscll = scl - (scl / 3) - 7;
 467                         fssclh = (scl / 3) - 5;
 468                 } else {
 469                         /* Standard mode */
 470                         fsscll = internal_clk / (dev->speed * 2) - 7;
 471                         fssclh = internal_clk / (dev->speed * 2) - 5;
 472                 }
 473                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 474                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 475         } else {
 476                 /* Program desired operating rate */
 477                 fclk_rate /= (psc + 1) * 1000;
 478                 if (psc > 2)
 479                         psc = 2;
 480                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
 481                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
 482         }
 483
 484         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 485         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 486
 487         /* SCL low and high time values */
 488         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
 489         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 490
 491         if (dev->fifo_size) {
 492                 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
 493                 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
 494                         (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
 495                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
 496         }
 497
 498         /* Take the I2C module out of reset: */
 499         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 500
 501         /* Enable interrupts */
 502         dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 503                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 504                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
 505                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
 506         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 507         if (cpu_is_omap34xx()) {
 508                 dev->pscstate = psc;
 509                 dev->scllstate = scll;
 510                 dev->sclhstate = sclh;
 511                 dev->bufstate = buf;
 512         }
 513         return 0;
 514 }
 515
 516 /*
 517  * Waiting on Bus Busy
 518  */
 519 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 520 {
 521         unsigned long timeout;
 522
 523         timeout = jiffies + OMAP_I2C_TIMEOUT;
 524         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 525                 if (time_after(jiffies, timeout)) {
 526                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 527                         return -ETIMEDOUT;
 528                 }
 529                 msleep(1);
 530         }
 531
 532         return 0;
 533 }
 534
 535 /*
 536  * Low level master read/write transaction.
 537  */
 538 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 539                              struct i2c_msg *msg, int stop)
 540 {
 541         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 542         int r;
 543         u16 w;
 544
 545         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 546                 msg->addr, msg->len, msg->flags, stop);
 547
 548         if (msg->len == 0)
 549                 return -EINVAL;
 550
 551         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 552
 553         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 554         dev->buf = msg->buf;
 555         dev->buf_len = msg->len;
 556
 557         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 558
 559         /* Clear the FIFO Buffers */
 560         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
 561         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
 562         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
 563
 564         init_completion(&dev->cmd_complete);
 565         dev->cmd_err = 0;
 566
 567         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 568
 569         /* High speed configuration */
 570         if (dev->speed > 400)
 571                 w |= OMAP_I2C_CON_OPMODE_HS;
 572
 573         if (msg->flags & I2C_M_TEN)
 574                 w |= OMAP_I2C_CON_XA;
 575         if (!(msg->flags & I2C_M_RD))
 576                 w |= OMAP_I2C_CON_TRX;
 577
 578         if (!dev->b_hw && stop)
 579                 w |= OMAP_I2C_CON_STP;
 580
 581         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 582
 583         /*
 584          * Don't write stt and stp together on some hardware.
 585          */
 586         if (dev->b_hw && stop) {
 587                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
 588                 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 589                 while (con & OMAP_I2C_CON_STT) {
 590                         con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 591
 592                         /* Let the user know if i2c is in a bad state */
 593                         if (time_after(jiffies, delay)) {
 594                                 dev_err(dev->dev, "controller timed out "
 595                                 "waiting for start condition to finish\n");
 596                                 return -ETIMEDOUT;
 597                         }
 598                         cpu_relax();
 599                 }
 600
 601                 w |= OMAP_I2C_CON_STP;
 602                 w &= ~OMAP_I2C_CON_STT;
 603                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 604         }
 605
 606         /*
 607          * REVISIT: We should abort the transfer on signals, but the bus goes
 608          * into arbitration and we're currently unable to recover from it.
 609          */
 610         if (dev->set_mpu_wkup_lat != NULL)
 611                 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
 612         r = wait_for_completion_timeout(&dev->cmd_complete,
 613                                         OMAP_I2C_TIMEOUT);
 614         if (dev->set_mpu_wkup_lat != NULL)
 615                 dev->set_mpu_wkup_lat(dev->dev, -1);
 616         dev->buf_len = 0;
 617         if (r < 0)
 618                 return r;
 619         if (r == 0) {
 620                 dev_err(dev->dev, "controller timed out\n");
 621                 omap_i2c_init(dev);
 622                 return -ETIMEDOUT;
 623         }
 624
 625         if (likely(!dev->cmd_err))
 626                 return 0;
 627
 628         /* We have an error */
 629         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 630                             OMAP_I2C_STAT_XUDF)) {
 631                 omap_i2c_init(dev);
 632                 return -EIO;
 633         }
 634
 635         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 636                 if (msg->flags & I2C_M_IGNORE_NAK)
 637                         return 0;
 638                 if (stop) {
 639                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 640                         w |= OMAP_I2C_CON_STP;
 641                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 642                 }
 643                 return -EREMOTEIO;
 644         }
 645         return -EIO;
 646 }
 647
 648
 649 /*
 650  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 651  * to do the work during IRQ processing.
 652  */
 653 static int
 654 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 655 {
 656         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 657         int i;
 658         int r;
 659
 660         omap_i2c_unidle(dev);
 661
 662         r = omap_i2c_wait_for_bb(dev);
 663         if (r < 0)
 664                 goto out;
 665
 666         for (i = 0; i < num; i++) {
 667                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 668                 if (r != 0)
 669                         break;
 670         }
 671
 672         if (r == 0)
 673                 r = num;
 674 out:
 675         omap_i2c_idle(dev);
 676         return r;
 677 }
 678
 679 static u32
 680 omap_i2c_func(struct i2c_adapter *adap)
 681 {
 682         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 683 }
 684
 685 static inline void
 686 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 687 {
 688         dev->cmd_err |= err;
 689         complete(&dev->cmd_complete);
 690 }
 691
 692 static inline void
 693 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 694 {
 695         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 696 }
 697
 698 /* rev1 devices are apparently only on some 15xx */
 699 #ifdef CONFIG_ARCH_OMAP15XX
 700
 701 static irqreturn_t
 702 omap_i2c_rev1_isr(int this_irq, void *dev_id)
 703 {
 704         struct omap_i2c_dev *dev = dev_id;
 705         u16 iv, w;
 706
 707         if (dev->idle)
 708                 return IRQ_NONE;
 709
 710         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 711         switch (iv) {
 712         case 0x00:      /* None */
 713                 break;
 714         case 0x01:      /* Arbitration lost */
 715                 dev_err(dev->dev, "Arbitration lost\n");
 716                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 717                 break;
 718         case 0x02:      /* No acknowledgement */
 719                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 720                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 721                 break;
 722         case 0x03:      /* Register access ready */
 723                 omap_i2c_complete_cmd(dev, 0);
 724                 break;
 725         case 0x04:      /* Receive data ready */
 726                 if (dev->buf_len) {
 727                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 728                         *dev->buf++ = w;
 729                         dev->buf_len--;
 730                         if (dev->buf_len) {
 731                                 *dev->buf++ = w >> 8;
 732                                 dev->buf_len--;
 733                         }
 734                 } else
 735                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 736                 break;
 737         case 0x05:      /* Transmit data ready */
 738                 if (dev->buf_len) {
 739                         w = *dev->buf++;
 740                         dev->buf_len--;
 741                         if (dev->buf_len) {
 742                                 w |= *dev->buf++ << 8;
 743                                 dev->buf_len--;
 744                         }
 745                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 746                 } else
 747                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 748                 break;
 749         default:
 750                 return IRQ_NONE;
 751         }
 752
 753         return IRQ_HANDLED;
 754 }
 755 #else
 756 #define omap_i2c_rev1_isr               NULL
 757 #endif
 758
 759 /*
 760  * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
 761  * data to DATA_REG. Otherwise some data bytes can be lost while transferring
 762  * them from the memory to the I2C interface.
 763  */
 764 static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
 765 {
 766         unsigned long timeout = 10000;
 767
 768         while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
 769                 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
 770                         omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY |
 771                                                         OMAP_I2C_STAT_XDR));
 772                         *err |= OMAP_I2C_STAT_XUDF;
 773                         return -ETIMEDOUT;
 774                 }
 775
 776                 cpu_relax();
 777                 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 778         }
 779
 780         if (!timeout) {
 781                 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
 782                 return 0;
 783         }
 784
 785         return 0;
 786 }
 787
 788 static irqreturn_t
 789 omap_i2c_isr(int this_irq, void *dev_id)
 790 {
 791         struct omap_i2c_dev *dev = dev_id;
 792         u16 bits;
 793         u16 stat, w;
 794         int err, count = 0;
 795
 796         if (dev->idle)
 797                 return IRQ_NONE;
 798
 799         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 800         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 801                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 802                 if (count++ == 100) {
 803                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 804                         break;
 805                 }
 806
 807                 err = 0;
 808 complete:
 809                 /*
 810                  * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
 811                  * acked after the data operation is complete.
 812                  * Ref: TRM SWPU114Q Figure 18-31
 813                  */
 814                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
 815                                 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
 816                                 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 817
 818                 if (stat & OMAP_I2C_STAT_NACK) {
 819                         err |= OMAP_I2C_STAT_NACK;
 820                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 821                                            OMAP_I2C_CON_STP);
 822                 }
 823                 if (stat & OMAP_I2C_STAT_AL) {
 824                         dev_err(dev->dev, "Arbitration lost\n");
 825                         err |= OMAP_I2C_STAT_AL;
 826                 }
 827                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 828                                         OMAP_I2C_STAT_AL)) {
 829                         omap_i2c_ack_stat(dev, stat &
 830                                 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
 831                                 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 832                         omap_i2c_complete_cmd(dev, err);
 833                         return IRQ_HANDLED;
 834                 }
 835                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
 836                         u8 num_bytes = 1;
 837                         if (dev->fifo_size) {
 838                                 if (stat & OMAP_I2C_STAT_RRDY)
 839                                         num_bytes = dev->fifo_size;
 840                                 else    /* read RXSTAT on RDR interrupt */
 841                                         num_bytes = (omap_i2c_read_reg(dev,
 842                                                         OMAP_I2C_BUFSTAT_REG)
 843                                                         >> 8) & 0x3F;
 844                         }
 845                         while (num_bytes) {
 846                                 num_bytes--;
 847                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 848                                 if (dev->buf_len) {
 849                                         *dev->buf++ = w;
 850                                         dev->buf_len--;
 851                                         /*
 852                                          * Data reg in 2430, omap3 and
 853                                          * omap4 is 8 bit wide
 854                                          */
 855                                         if (cpu_class_is_omap1() ||
 856                                                         cpu_is_omap2420()) {
 857                                                 if (dev->buf_len) {
 858                                                         *dev->buf++ = w >> 8;
 859                                                         dev->buf_len--;
 860                                                 }
 861                                         }
 862                                 } else {
 863                                         if (stat & OMAP_I2C_STAT_RRDY)
 864                                                 dev_err(dev->dev,
 865                                                         "RRDY IRQ while no data"
 866                                                                 " requested\n");
 867                                         if (stat & OMAP_I2C_STAT_RDR)
 868                                                 dev_err(dev->dev,
 869                                                         "RDR IRQ while no data"
 870                                                                 " requested\n");
 871                                         break;
 872                                 }
 873                         }
 874                         omap_i2c_ack_stat(dev,
 875                                 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
 876                         continue;
 877                 }
 878                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
 879                         u8 num_bytes = 1;
 880                         if (dev->fifo_size) {
 881                                 if (stat & OMAP_I2C_STAT_XRDY)
 882                                         num_bytes = dev->fifo_size;
 883                                 else    /* read TXSTAT on XDR interrupt */
 884                                         num_bytes = omap_i2c_read_reg(dev,
 885                                                         OMAP_I2C_BUFSTAT_REG)
 886                                                         & 0x3F;
 887                         }
 888                         while (num_bytes) {
 889                                 num_bytes--;
 890                                 w = 0;
 891                                 if (dev->buf_len) {
 892                                         w = *dev->buf++;
 893                                         dev->buf_len--;
 894                                         /*
 895                                          * Data reg in 2430, omap3 and
 896                                          * omap4 is 8 bit wide
 897                                          */
 898                                         if (cpu_class_is_omap1() ||
 899                                                         cpu_is_omap2420()) {
 900                                                 if (dev->buf_len) {
 901                                                         w |= *dev->buf++ << 8;
 902                                                         dev->buf_len--;
 903                                                 }
 904                                         }
 905                                 } else {
 906                                         if (stat & OMAP_I2C_STAT_XRDY)
 907                                                 dev_err(dev->dev,
 908                                                         "XRDY IRQ while no "
 909                                                         "data to send\n");
 910                                         if (stat & OMAP_I2C_STAT_XDR)
 911                                                 dev_err(dev->dev,
 912                                                         "XDR IRQ while no "
 913                                                         "data to send\n");
 914                                         break;
 915                                 }
 916
 917                                 if ((dev->rev <= OMAP_I2C_REV_ON_3430) &&
 918                                     errata_omap3_1p153(dev, &stat, &err))
 919                                         goto complete;
 920
 921                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 922                         }
 923                         omap_i2c_ack_stat(dev,
 924                                 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 925                         continue;
 926                 }
 927                 if (stat & OMAP_I2C_STAT_ROVR) {
 928                         dev_err(dev->dev, "Receive overrun\n");
 929                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 930                 }
 931                 if (stat & OMAP_I2C_STAT_XUDF) {
 932                         dev_err(dev->dev, "Transmit underflow\n");
 933                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 934                 }
 935         }
 936
 937         return count ? IRQ_HANDLED : IRQ_NONE;
 938 }
 939
 940 static const struct i2c_algorithm omap_i2c_algo = {
 941         .master_xfer    = omap_i2c_xfer,
 942         .functionality  = omap_i2c_func,
 943 };
 944
 945 static int __devinit
 946 omap_i2c_probe(struct platform_device *pdev)
 947 {
 948         struct omap_i2c_dev     *dev;
 949         struct i2c_adapter      *adap;
 950         struct resource         *mem, *irq, *ioarea;
 951         struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
 952         irq_handler_t isr;
 953         int r;
 954         u32 speed = 0;
 955
 956         /* NOTE: driver uses the static register mapping */
 957         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 958         if (!mem) {
 959                 dev_err(&pdev->dev, "no mem resource?\n");
 960                 return -ENODEV;
 961         }
 962         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 963         if (!irq) {
 964                 dev_err(&pdev->dev, "no irq resource?\n");
 965                 return -ENODEV;
 966         }
 967
 968         ioarea = request_mem_region(mem->start, resource_size(mem),
 969                         pdev->name);
 970         if (!ioarea) {
 971                 dev_err(&pdev->dev, "I2C region already claimed\n");
 972                 return -EBUSY;
 973         }
 974
 975         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 976         if (!dev) {
 977                 r = -ENOMEM;
 978                 goto err_release_region;
 979         }
 980
 981         if (pdata != NULL) {
 982                 speed = pdata->clkrate;
 983                 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
 984         } else {
 985                 speed = 100;    /* Default speed */
 986                 dev->set_mpu_wkup_lat = NULL;
 987         }
 988
 989         dev->speed = speed;
 990         dev->idle = 1;
 991         dev->dev = &pdev->dev;
 992         dev->irq = irq->start;
 993         dev->base = ioremap(mem->start, resource_size(mem));
 994         if (!dev->base) {
 995                 r = -ENOMEM;
 996                 goto err_free_mem;
 997         }
 998
 999         platform_set_drvdata(pdev, dev);
1000
1001         if (cpu_is_omap7xx())
1002                 dev->reg_shift = 1;
1003         else if (cpu_is_omap44xx())
1004                 dev->reg_shift = 0;
1005         else
1006                 dev->reg_shift = 2;
1007
1008         if ((r = omap_i2c_get_clocks(dev)) != 0)
1009                 goto err_iounmap;
1010
1011         if (cpu_is_omap44xx())
1012                 dev->regs = (u8 *) omap4_reg_map;
1013         else
1014                 dev->regs = (u8 *) reg_map;
1015
1016         omap_i2c_unidle(dev);
1017
1018         dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
1019
1020         if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
1021                 u16 s;
1022
1023                 /* Set up the fifo size - Get total size */
1024                 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1025                 dev->fifo_size = 0x8 << s;
1026
1027                 /*
1028                  * Set up notification threshold as half the total available
1029                  * size. This is to ensure that we can handle the status on int
1030                  * call back latencies.
1031                  */
1032                 if (dev->rev >= OMAP_I2C_REV_ON_4430) {
1033                         dev->fifo_size = 0;
1034                         dev->b_hw = 0; /* Disable hardware fixes */
1035                 } else {
1036                         dev->fifo_size = (dev->fifo_size / 2);
1037                         dev->b_hw = 1; /* Enable hardware fixes */
1038                 }
1039                 /* calculate wakeup latency constraint for MPU */
1040                 if (dev->set_mpu_wkup_lat != NULL)
1041                         dev->latency = (1000000 * dev->fifo_size) /
1042                                        (1000 * speed / 8);
1043         }
1044
1045         /* reset ASAP, clearing any IRQs */
1046         omap_i2c_init(dev);
1047
1048         isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
1049         r = request_irq(dev->irq, isr, 0, pdev->name, dev);
1050
1051         if (r) {
1052                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1053                 goto err_unuse_clocks;
1054         }
1055
1056         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
1057                  pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1058
1059         omap_i2c_idle(dev);
1060
1061         adap = &dev->adapter;
1062         i2c_set_adapdata(adap, dev);
1063         adap->owner = THIS_MODULE;
1064         adap->class = I2C_CLASS_HWMON;
1065         strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1066         adap->algo = &omap_i2c_algo;
1067         adap->dev.parent = &pdev->dev;
1068
1069         /* i2c device drivers may be active on return from add_adapter() */
1070         adap->nr = pdev->id;
1071         r = i2c_add_numbered_adapter(adap);
1072         if (r) {
1073                 dev_err(dev->dev, "failure adding adapter\n");
1074                 goto err_free_irq;
1075         }
1076
1077         return 0;
1078
1079 err_free_irq:
1080         free_irq(dev->irq, dev);
1081 err_unuse_clocks:
1082         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1083         omap_i2c_idle(dev);
1084         omap_i2c_put_clocks(dev);
1085 err_iounmap:
1086         iounmap(dev->base);
1087 err_free_mem:
1088         platform_set_drvdata(pdev, NULL);
1089         kfree(dev);
1090 err_release_region:
1091         release_mem_region(mem->start, resource_size(mem));
1092
1093         return r;
1094 }
1095
1096 static int
1097 omap_i2c_remove(struct platform_device *pdev)
1098 {
1099         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
1100         struct resource         *mem;
1101
1102         platform_set_drvdata(pdev, NULL);
1103
1104         free_irq(dev->irq, dev);
1105         i2c_del_adapter(&dev->adapter);
1106         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1107         omap_i2c_put_clocks(dev);
1108         iounmap(dev->base);
1109         kfree(dev);
1110         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1111         release_mem_region(mem->start, resource_size(mem));
1112         return 0;
1113 }
1114
1115 static struct platform_driver omap_i2c_driver = {
1116         .probe          = omap_i2c_probe,
1117         .remove         = omap_i2c_remove,
1118         .driver         = {
1119                 .name   = "i2c_omap",
1120                 .owner  = THIS_MODULE,
1121         },
1122 };
1123
1124 /* I2C may be needed to bring up other drivers */
1125 static int __init
1126 omap_i2c_init_driver(void)
1127 {
1128         return platform_driver_register(&omap_i2c_driver);
1129 }
1130 subsys_initcall(omap_i2c_init_driver);
1131
1132 static void __exit omap_i2c_exit_driver(void)
1133 {
1134         platform_driver_unregister(&omap_i2c_driver);
1135 }
1136 module_exit(omap_i2c_exit_driver);
1137
1138 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1139 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1140 MODULE_LICENSE("GPL");
1141 MODULE_ALIAS("platform:i2c_omap");