drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007, 2008   Jean Delvare <khali@linux-fr.org>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 */
  23
  24 /*
  25   Supports the following Intel I/O Controller Hubs (ICH):
  26
  27                                   I/O                     Block   I2C
  28                                   region  SMBus   Block   proc.   block
  29   Chip name             PCI ID    size    PEC     buffer  call    read
  30   ----------------------------------------------------------------------
  31   82801AA  (ICH)        0x2413     16      no      no      no      no
  32   82801AB  (ICH0)       0x2423     16      no      no      no      no
  33   82801BA  (ICH2)       0x2443     16      no      no      no      no
  34   82801CA  (ICH3)       0x2483     32     soft     no      no      no
  35   82801DB  (ICH4)       0x24c3     32     hard     yes     no      no
  36   82801E   (ICH5)       0x24d3     32     hard     yes     yes     yes
  37   6300ESB               0x25a4     32     hard     yes     yes     yes
  38   82801F   (ICH6)       0x266a     32     hard     yes     yes     yes
  39   6310ESB/6320ESB       0x269b     32     hard     yes     yes     yes
  40   82801G   (ICH7)       0x27da     32     hard     yes     yes     yes
  41   82801H   (ICH8)       0x283e     32     hard     yes     yes     yes
  42   82801I   (ICH9)       0x2930     32     hard     yes     yes     yes
  43   EP80579 (Tolapai)     0x5032     32     hard     yes     yes     yes
  44   ICH10                 0x3a30     32     hard     yes     yes     yes
  45   ICH10                 0x3a60     32     hard     yes     yes     yes
  46   5/3400 Series (PCH)   0x3b30     32     hard     yes     yes     yes
  47   6 Series (PCH)        0x1c22     32     hard     yes     yes     yes
  48   Patsburg (PCH)        0x1d22     32     hard     yes     yes     yes
  49   Patsburg (PCH) IDF    0x1d70     32     hard     yes     yes     yes
  50   Patsburg (PCH) IDF    0x1d71     32     hard     yes     yes     yes
  51   Patsburg (PCH) IDF    0x1d72     32     hard     yes     yes     yes
  52   DH89xxCC (PCH)        0x2330     32     hard     yes     yes     yes
  53   Panther Point (PCH)   0x1e22     32     hard     yes     yes     yes
  54   Lynx Point (PCH)      0x8c22     32     hard     yes     yes     yes
  55   Lynx Point-LP (PCH)   0x9c22     32     hard     yes     yes     yes
  56   Avoton (SOC)          0x1f3c     32     hard     yes     yes     yes
  57   Wellsburg (PCH)       0x8d22     32     hard     yes     yes     yes
  58   Wellsburg (PCH) MS    0x8d7d     32     hard     yes     yes     yes
  59   Wellsburg (PCH) MS    0x8d7e     32     hard     yes     yes     yes
  60   Wellsburg (PCH) MS    0x8d7f     32     hard     yes     yes     yes
  61   Coleto Creek (PCH)    0x23b0     32     hard     yes     yes     yes
  62   Wildcat Point-LP (PCH)   0x9ca2     32     hard     yes     yes     yes
  63
  64   Features supported by this driver:
  65   Software PEC                     no
  66   Hardware PEC                     yes
  67   Block buffer                     yes
  68   Block process call transaction   no
  69   I2C block read transaction       yes  (doesn't use the block buffer)
  70   Slave mode                       no
  71
  72   See the file Documentation/i2c/busses/i2c-i801 for details.
  73 */
  74
  75 #include <linux/module.h>
  76 #include <linux/pci.h>
  77 #include <linux/kernel.h>
  78 #include <linux/stddef.h>
  79 #include <linux/delay.h>
  80 #include <linux/ioport.h>
  81 #include <linux/init.h>
  82 #include <linux/i2c.h>
  83 #include <linux/acpi.h>
  84 #include <linux/io.h>
  85 #include <linux/dmi.h>
  86 #include <linux/slab.h>
  87
  88 /* I801 SMBus address offsets */
  89 #define SMBHSTSTS(p)    (0 + (p)->smba)
  90 #define SMBHSTCNT(p)    (2 + (p)->smba)
  91 #define SMBHSTCMD(p)    (3 + (p)->smba)
  92 #define SMBHSTADD(p)    (4 + (p)->smba)
  93 #define SMBHSTDAT0(p)   (5 + (p)->smba)
  94 #define SMBHSTDAT1(p)   (6 + (p)->smba)
  95 #define SMBBLKDAT(p)    (7 + (p)->smba)
  96 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
  97 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
  98 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
  99
 100 /* PCI Address Constants */
 101 #define SMBBAR          4
 102 #define SMBHSTCFG       0x040
 103
 104 /* Host configuration bits for SMBHSTCFG */
 105 #define SMBHSTCFG_HST_EN        1
 106 #define SMBHSTCFG_SMB_SMI_EN    2
 107 #define SMBHSTCFG_I2C_EN        4
 108
 109 /* Auxiliary control register bits, ICH4+ only */
 110 #define SMBAUXCTL_CRC           1
 111 #define SMBAUXCTL_E32B          2
 112
 113 /* kill bit for SMBHSTCNT */
 114 #define SMBHSTCNT_KILL          2
 115
 116 /* Other settings */
 117 #define MAX_TIMEOUT             100
 118 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
 119
 120 /* I801 command constants */
 121 #define I801_QUICK              0x00
 122 #define I801_BYTE               0x04
 123 #define I801_BYTE_DATA          0x08
 124 #define I801_WORD_DATA          0x0C
 125 #define I801_PROC_CALL          0x10    /* unimplemented */
 126 #define I801_BLOCK_DATA         0x14
 127 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 128 #define I801_BLOCK_LAST         0x34
 129 #define I801_I2C_BLOCK_LAST     0x38    /* ICH5 and later */
 130 #define I801_START              0x40
 131 #define I801_PEC_EN             0x80    /* ICH3 and later */
 132
 133 /* I801 Hosts Status register bits */
 134 #define SMBHSTSTS_BYTE_DONE     0x80
 135 #define SMBHSTSTS_INUSE_STS     0x40
 136 #define SMBHSTSTS_SMBALERT_STS  0x20
 137 #define SMBHSTSTS_FAILED        0x10
 138 #define SMBHSTSTS_BUS_ERR       0x08
 139 #define SMBHSTSTS_DEV_ERR       0x04
 140 #define SMBHSTSTS_INTR          0x02
 141 #define SMBHSTSTS_HOST_BUSY     0x01
 142
 143 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
 144                                  SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
 145                                  SMBHSTSTS_INTR)
 146
 147 /* Older devices have their ID defined in <linux/pci_ids.h> */
 148 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS   0x1c22
 149 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS      0x1d22
 150 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 151 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
 152 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
 153 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
 154 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS  0x1e22
 155 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS        0x1f3c
 156 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS      0x2330
 157 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS   0x23b0
 158 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
 159 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS     0x8c22
 160 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS     0x8d22
 161 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
 162 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
 163 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
 164 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS  0x9c22
 165 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 166
 167 struct i801_priv {
 168         struct i2c_adapter adapter;
 169         unsigned long smba;
 170         unsigned char original_hstcfg;
 171         struct pci_dev *pci_dev;
 172         unsigned int features;
 173 };
 174
 175 static struct pci_driver i801_driver;
 176
 177 #define FEATURE_SMBUS_PEC       (1 << 0)
 178 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 179 #define FEATURE_BLOCK_PROC      (1 << 2)
 180 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 181 /* Not really a feature, but it's convenient to handle it as such */
 182 #define FEATURE_IDF             (1 << 15)
 183
 184 static const char *i801_feature_names[] = {
 185         "SMBus PEC",
 186         "Block buffer",
 187         "Block process call",
 188         "I2C block read",
 189 };
 190
 191 static unsigned int disable_features;
 192 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 193 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
 194
 195 /* Make sure the SMBus host is ready to start transmitting.
 196    Return 0 if it is, -EBUSY if it is not. */
 197 static int i801_check_pre(struct i801_priv *priv)
 198 {
 199         int status;
 200
 201         status = inb_p(SMBHSTSTS(priv));
 202         if (status & SMBHSTSTS_HOST_BUSY) {
 203                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 204                 return -EBUSY;
 205         }
 206
 207         status &= STATUS_FLAGS;
 208         if (status) {
 209                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 210                         status);
 211                 outb_p(status, SMBHSTSTS(priv));
 212                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 213                 if (status) {
 214                         dev_err(&priv->pci_dev->dev,
 215                                 "Failed clearing status flags (%02x)\n",
 216                                 status);
 217                         return -EBUSY;
 218                 }
 219         }
 220
 221         return 0;
 222 }
 223
 224 /* Convert the status register to an error code, and clear it. */
 225 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
 226 {
 227         int result = 0;
 228
 229         /* If the SMBus is still busy, we give up */
 230         if (timeout) {
 231                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 232                 /* try to stop the current command */
 233                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 234                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 235                        SMBHSTCNT(priv));
 236                 msleep(1);
 237                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 238                        SMBHSTCNT(priv));
 239
 240                 /* Check if it worked */
 241                 status = inb_p(SMBHSTSTS(priv));
 242                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 243                     !(status & SMBHSTSTS_FAILED))
 244                         dev_err(&priv->pci_dev->dev,
 245                                 "Failed terminating the transaction\n");
 246                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 247                 return -ETIMEDOUT;
 248         }
 249
 250         if (status & SMBHSTSTS_FAILED) {
 251                 result = -EIO;
 252                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 253         }
 254         if (status & SMBHSTSTS_DEV_ERR) {
 255                 result = -ENXIO;
 256                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 257         }
 258         if (status & SMBHSTSTS_BUS_ERR) {
 259                 result = -EAGAIN;
 260                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 261         }
 262
 263         if (result) {
 264                 /* Clear error flags */
 265                 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
 266                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 267                 if (status) {
 268                         dev_warn(&priv->pci_dev->dev, "Failed clearing status "
 269                                  "flags at end of transaction (%02x)\n",
 270                                  status);
 271                 }
 272         }
 273
 274         return result;
 275 }
 276
 277 static int i801_transaction(struct i801_priv *priv, int xact)
 278 {
 279         int status;
 280         int result;
 281         int timeout = 0;
 282
 283         result = i801_check_pre(priv);
 284         if (result < 0)
 285                 return result;
 286
 287         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 288          * INTREN, SMBSCMD are passed in xact */
 289         outb_p(xact | I801_START, SMBHSTCNT(priv));
 290
 291         /* We will always wait for a fraction of a second! */
 292         do {
 293                 msleep(1);
 294                 status = inb_p(SMBHSTSTS(priv));
 295         } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
 296
 297         result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 298         if (result < 0)
 299                 return result;
 300
 301         outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 302         return 0;
 303 }
 304
 305 /* wait for INTR bit as advised by Intel */
 306 static void i801_wait_hwpec(struct i801_priv *priv)
 307 {
 308         int timeout = 0;
 309         int status;
 310
 311         do {
 312                 msleep(1);
 313                 status = inb_p(SMBHSTSTS(priv));
 314         } while ((!(status & SMBHSTSTS_INTR))
 315                  && (timeout++ < MAX_TIMEOUT));
 316
 317         if (timeout > MAX_TIMEOUT)
 318                 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
 319
 320         outb_p(status, SMBHSTSTS(priv));
 321 }
 322
 323 static int i801_block_transaction_by_block(struct i801_priv *priv,
 324                                            union i2c_smbus_data *data,
 325                                            char read_write, int hwpec)
 326 {
 327         int i, len;
 328         int status;
 329
 330         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 331
 332         /* Use 32-byte buffer to process this transaction */
 333         if (read_write == I2C_SMBUS_WRITE) {
 334                 len = data->block[0];
 335                 outb_p(len, SMBHSTDAT0(priv));
 336                 for (i = 0; i < len; i++)
 337                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 338         }
 339
 340         status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
 341                                   I801_PEC_EN * hwpec);
 342         if (status)
 343                 return status;
 344
 345         if (read_write == I2C_SMBUS_READ) {
 346                 len = inb_p(SMBHSTDAT0(priv));
 347                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 348                         return -EPROTO;
 349
 350                 data->block[0] = len;
 351                 for (i = 0; i < len; i++)
 352                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 353         }
 354         return 0;
 355 }
 356
 357 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 358                                                union i2c_smbus_data *data,
 359                                                char read_write, int command,
 360                                                int hwpec)
 361 {
 362         int i, len;
 363         int smbcmd;
 364         int status;
 365         int result;
 366         int timeout;
 367
 368         result = i801_check_pre(priv);
 369         if (result < 0)
 370                 return result;
 371
 372         len = data->block[0];
 373
 374         if (read_write == I2C_SMBUS_WRITE) {
 375                 outb_p(len, SMBHSTDAT0(priv));
 376                 outb_p(data->block[1], SMBBLKDAT(priv));
 377         }
 378
 379         for (i = 1; i <= len; i++) {
 380                 if (i == len && read_write == I2C_SMBUS_READ) {
 381                         if (command == I2C_SMBUS_I2C_BLOCK_DATA)
 382                                 smbcmd = I801_I2C_BLOCK_LAST;
 383                         else
 384                                 smbcmd = I801_BLOCK_LAST;
 385                 } else {
 386                         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 387                          && read_write == I2C_SMBUS_READ)
 388                                 smbcmd = I801_I2C_BLOCK_DATA;
 389                         else
 390                                 smbcmd = I801_BLOCK_DATA;
 391                 }
 392                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
 393
 394                 if (i == 1)
 395                         outb_p(inb(SMBHSTCNT(priv)) | I801_START,
 396                                SMBHSTCNT(priv));
 397
 398                 /* We will always wait for a fraction of a second! */
 399                 timeout = 0;
 400                 do {
 401                         msleep(1);
 402                         status = inb_p(SMBHSTSTS(priv));
 403                 } while ((!(status & SMBHSTSTS_BYTE_DONE))
 404                          && (timeout++ < MAX_TIMEOUT));
 405
 406                 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 407                 if (result < 0)
 408                         return result;
 409
 410                 if (i == 1 && read_write == I2C_SMBUS_READ
 411                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 412                         len = inb_p(SMBHSTDAT0(priv));
 413                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 414                                 dev_err(&priv->pci_dev->dev,
 415                                         "Illegal SMBus block read size %d\n",
 416                                         len);
 417                                 /* Recover */
 418                                 while (inb_p(SMBHSTSTS(priv)) &
 419                                        SMBHSTSTS_HOST_BUSY)
 420                                         outb_p(SMBHSTSTS_BYTE_DONE,
 421                                                SMBHSTSTS(priv));
 422                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 423                                 return -EPROTO;
 424                         }
 425                         data->block[0] = len;
 426                 }
 427
 428                 /* Retrieve/store value in SMBBLKDAT */
 429                 if (read_write == I2C_SMBUS_READ)
 430                         data->block[i] = inb_p(SMBBLKDAT(priv));
 431                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 432                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 433
 434                 /* signals SMBBLKDAT ready */
 435                 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
 436         }
 437
 438         return 0;
 439 }
 440
 441 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 442 {
 443         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 444         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 445                 return -EIO;
 446         return 0;
 447 }
 448
 449 /* Block transaction function */
 450 static int i801_block_transaction(struct i801_priv *priv,
 451                                   union i2c_smbus_data *data, char read_write,
 452                                   int command, int hwpec)
 453 {
 454         int result = 0;
 455         unsigned char hostc;
 456
 457         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 458                 if (read_write == I2C_SMBUS_WRITE) {
 459                         /* set I2C_EN bit in configuration register */
 460                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 461                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 462                                               hostc | SMBHSTCFG_I2C_EN);
 463                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 464                         dev_err(&priv->pci_dev->dev,
 465                                 "I2C block read is unsupported!\n");
 466                         return -EOPNOTSUPP;
 467                 }
 468         }
 469
 470         if (read_write == I2C_SMBUS_WRITE
 471          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 472                 if (data->block[0] < 1)
 473                         data->block[0] = 1;
 474                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 475                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 476         } else {
 477                 data->block[0] = 32;    /* max for SMBus block reads */
 478         }
 479
 480         /* Experience has shown that the block buffer can only be used for
 481            SMBus (not I2C) block transactions, even though the datasheet
 482            doesn't mention this limitation. */
 483         if ((priv->features & FEATURE_BLOCK_BUFFER)
 484          && command != I2C_SMBUS_I2C_BLOCK_DATA
 485          && i801_set_block_buffer_mode(priv) == 0)
 486                 result = i801_block_transaction_by_block(priv, data,
 487                                                          read_write, hwpec);
 488         else
 489                 result = i801_block_transaction_byte_by_byte(priv, data,
 490                                                              read_write,
 491                                                              command, hwpec);
 492
 493         if (result == 0 && hwpec)
 494                 i801_wait_hwpec(priv);
 495
 496         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 497          && read_write == I2C_SMBUS_WRITE) {
 498                 /* restore saved configuration register value */
 499                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 500         }
 501         return result;
 502 }
 503
 504 /* Return negative errno on error. */
 505 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 506                        unsigned short flags, char read_write, u8 command,
 507                        int size, union i2c_smbus_data *data)
 508 {
 509         int hwpec;
 510         int block = 0;
 511         int ret, xact = 0;
 512         struct i801_priv *priv = i2c_get_adapdata(adap);
 513
 514         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 515                 && size != I2C_SMBUS_QUICK
 516                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 517
 518         switch (size) {
 519         case I2C_SMBUS_QUICK:
 520                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 521                        SMBHSTADD(priv));
 522                 xact = I801_QUICK;
 523                 break;
 524         case I2C_SMBUS_BYTE:
 525                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 526                        SMBHSTADD(priv));
 527                 if (read_write == I2C_SMBUS_WRITE)
 528                         outb_p(command, SMBHSTCMD(priv));
 529                 xact = I801_BYTE;
 530                 break;
 531         case I2C_SMBUS_BYTE_DATA:
 532                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 533                        SMBHSTADD(priv));
 534                 outb_p(command, SMBHSTCMD(priv));
 535                 if (read_write == I2C_SMBUS_WRITE)
 536                         outb_p(data->byte, SMBHSTDAT0(priv));
 537                 xact = I801_BYTE_DATA;
 538                 break;
 539         case I2C_SMBUS_WORD_DATA:
 540                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 541                        SMBHSTADD(priv));
 542                 outb_p(command, SMBHSTCMD(priv));
 543                 if (read_write == I2C_SMBUS_WRITE) {
 544                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 545                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 546                 }
 547                 xact = I801_WORD_DATA;
 548                 break;
 549         case I2C_SMBUS_BLOCK_DATA:
 550                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 551                        SMBHSTADD(priv));
 552                 outb_p(command, SMBHSTCMD(priv));
 553                 block = 1;
 554                 break;
 555         case I2C_SMBUS_I2C_BLOCK_DATA:
 556                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 557                  * bit should be cleared here, even when reading */
 558                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 559                 if (read_write == I2C_SMBUS_READ) {
 560                         /* NB: page 240 of ICH5 datasheet also shows
 561                          * that DATA1 is the cmd field when reading */
 562                         outb_p(command, SMBHSTDAT1(priv));
 563                 } else
 564                         outb_p(command, SMBHSTCMD(priv));
 565                 block = 1;
 566                 break;
 567         default:
 568                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 569                         size);
 570                 return -EOPNOTSUPP;
 571         }
 572
 573         if (hwpec)      /* enable/disable hardware PEC */
 574                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 575         else
 576                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 577                        SMBAUXCTL(priv));
 578
 579         if (block)
 580                 ret = i801_block_transaction(priv, data, read_write, size,
 581                                              hwpec);
 582         else
 583                 ret = i801_transaction(priv, xact | ENABLE_INT9);
 584
 585         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 586            time, so we forcibly disable it after every transaction. Turn off
 587            E32B for the same reason. */
 588         if (hwpec || block)
 589                 outb_p(inb_p(SMBAUXCTL(priv)) &
 590                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 591
 592         if (block)
 593                 return ret;
 594         if (ret)
 595                 return ret;
 596         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 597                 return 0;
 598
 599         switch (xact & 0x7f) {
 600         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 601         case I801_BYTE_DATA:
 602                 data->byte = inb_p(SMBHSTDAT0(priv));
 603                 break;
 604         case I801_WORD_DATA:
 605                 data->word = inb_p(SMBHSTDAT0(priv)) +
 606                              (inb_p(SMBHSTDAT1(priv)) << 8);
 607                 break;
 608         }
 609         return 0;
 610 }
 611
 612
 613 static u32 i801_func(struct i2c_adapter *adapter)
 614 {
 615         struct i801_priv *priv = i2c_get_adapdata(adapter);
 616
 617         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 618                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 619                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 620                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 621                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 622                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 623 }
 624
 625 static const struct i2c_algorithm smbus_algorithm = {
 626         .smbus_xfer     = i801_access,
 627         .functionality  = i801_func,
 628 };
 629
 630 static const struct pci_device_id i801_ids[] = {
 631         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 632         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 633         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 634         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 635         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 636         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 637         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 638         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 639         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 640         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 641         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 642         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 643         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 644         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 645         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 646         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 647         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 648         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 649         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 650         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 651         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 652         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 653         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 654         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 655         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 656         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 657         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 658         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 659         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 660         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 661         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 662         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
 663         { 0, }
 664 };
 665
 666 MODULE_DEVICE_TABLE(pci, i801_ids);
 667
 668 #if defined CONFIG_X86 && defined CONFIG_DMI
 669 static unsigned char apanel_addr;
 670
 671 /* Scan the system ROM for the signature "FJKEYINF" */
 672 static __init const void __iomem *bios_signature(const void __iomem *bios)
 673 {
 674         ssize_t offset;
 675         const unsigned char signature[] = "FJKEYINF";
 676
 677         for (offset = 0; offset < 0x10000; offset += 0x10) {
 678                 if (check_signature(bios + offset, signature,
 679                                     sizeof(signature)-1))
 680                         return bios + offset;
 681         }
 682         return NULL;
 683 }
 684
 685 static void __init input_apanel_init(void)
 686 {
 687         void __iomem *bios;
 688         const void __iomem *p;
 689
 690         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 691         p = bios_signature(bios);
 692         if (p) {
 693                 /* just use the first address */
 694                 apanel_addr = readb(p + 8 + 3) >> 1;
 695         }
 696         iounmap(bios);
 697 }
 698
 699 struct dmi_onboard_device_info {
 700         const char *name;
 701         u8 type;
 702         unsigned short i2c_addr;
 703         const char *i2c_type;
 704 };
 705
 706 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
 707         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 708         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 709         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 710 };
 711
 712 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
 713                                                struct i2c_adapter *adap)
 714 {
 715         int i;
 716         struct i2c_board_info info;
 717
 718         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 719                 /* & ~0x80, ignore enabled/disabled bit */
 720                 if ((type & ~0x80) != dmi_devices[i].type)
 721                         continue;
 722                 if (strcasecmp(name, dmi_devices[i].name))
 723                         continue;
 724
 725                 memset(&info, 0, sizeof(struct i2c_board_info));
 726                 info.addr = dmi_devices[i].i2c_addr;
 727                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 728                 i2c_new_device(adap, &info);
 729                 break;
 730         }
 731 }
 732
 733 /* We use our own function to check for onboard devices instead of
 734    dmi_find_device() as some buggy BIOS's have the devices we are interested
 735    in marked as disabled */
 736 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
 737                                                 void *adap)
 738 {
 739         int i, count;
 740
 741         if (dm->type != 10)
 742                 return;
 743
 744         count = (dm->length - sizeof(struct dmi_header)) / 2;
 745         for (i = 0; i < count; i++) {
 746                 const u8 *d = (char *)(dm + 1) + (i * 2);
 747                 const char *name = ((char *) dm) + dm->length;
 748                 u8 type = d[0];
 749                 u8 s = d[1];
 750
 751                 if (!s)
 752                         continue;
 753                 s--;
 754                 while (s > 0 && name[0]) {
 755                         name += strlen(name) + 1;
 756                         s--;
 757                 }
 758                 if (name[0] == 0) /* Bogus string reference */
 759                         continue;
 760
 761                 dmi_check_onboard_device(type, name, adap);
 762         }
 763 }
 764
 765 /* Register optional slaves */
 766 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
 767 {
 768         /* Only register slaves on main SMBus channel */
 769         if (priv->features & FEATURE_IDF)
 770                 return;
 771
 772         if (apanel_addr) {
 773                 struct i2c_board_info info;
 774
 775                 memset(&info, 0, sizeof(struct i2c_board_info));
 776                 info.addr = apanel_addr;
 777                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 778                 i2c_new_device(&priv->adapter, &info);
 779         }
 780
 781         if (dmi_name_in_vendors("FUJITSU"))
 782                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 783 }
 784 #else
 785 static void __init input_apanel_init(void) {}
 786 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
 787 #endif  /* CONFIG_X86 && CONFIG_DMI */
 788
 789 static int __devinit i801_probe(struct pci_dev *dev,
 790                                 const struct pci_device_id *id)
 791 {
 792         unsigned char temp;
 793         int err, i;
 794         struct i801_priv *priv;
 795
 796         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 797         if (!priv)
 798                 return -ENOMEM;
 799
 800         i2c_set_adapdata(&priv->adapter, priv);
 801         priv->adapter.owner = THIS_MODULE;
 802         priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 803         priv->adapter.algo = &smbus_algorithm;
 804
 805         priv->pci_dev = dev;
 806         switch (dev->device) {
 807         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
 808         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
 809         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
 810         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
 811         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
 812         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
 813                 priv->features |= FEATURE_IDF;
 814                 /* fall through */
 815         default:
 816                 priv->features |= FEATURE_I2C_BLOCK_READ;
 817                 /* fall through */
 818         case PCI_DEVICE_ID_INTEL_82801DB_3:
 819                 priv->features |= FEATURE_SMBUS_PEC;
 820                 priv->features |= FEATURE_BLOCK_BUFFER;
 821                 /* fall through */
 822         case PCI_DEVICE_ID_INTEL_82801CA_3:
 823         case PCI_DEVICE_ID_INTEL_82801BA_2:
 824         case PCI_DEVICE_ID_INTEL_82801AB_3:
 825         case PCI_DEVICE_ID_INTEL_82801AA_3:
 826                 break;
 827         }
 828
 829         /* Disable features on user request */
 830         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
 831                 if (priv->features & disable_features & (1 << i))
 832                         dev_notice(&dev->dev, "%s disabled by user\n",
 833                                    i801_feature_names[i]);
 834         }
 835         priv->features &= ~disable_features;
 836
 837         err = pci_enable_device(dev);
 838         if (err) {
 839                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
 840                         err);
 841                 goto exit;
 842         }
 843
 844         /* Determine the address of the SMBus area */
 845         priv->smba = pci_resource_start(dev, SMBBAR);
 846         if (!priv->smba) {
 847                 dev_err(&dev->dev, "SMBus base address uninitialized, "
 848                         "upgrade BIOS\n");
 849                 err = -ENODEV;
 850                 goto exit;
 851         }
 852
 853         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
 854         if (err) {
 855                 err = -ENODEV;
 856                 goto exit;
 857         }
 858
 859         err = pci_request_region(dev, SMBBAR, i801_driver.name);
 860         if (err) {
 861                 dev_err(&dev->dev, "Failed to request SMBus region "
 862                         "0x%lx-0x%Lx\n", priv->smba,
 863                         (unsigned long long)pci_resource_end(dev, SMBBAR));
 864                 goto exit;
 865         }
 866
 867         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
 868         priv->original_hstcfg = temp;
 869         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
 870         if (!(temp & SMBHSTCFG_HST_EN)) {
 871                 dev_info(&dev->dev, "Enabling SMBus device\n");
 872                 temp |= SMBHSTCFG_HST_EN;
 873         }
 874         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
 875
 876         if (temp & SMBHSTCFG_SMB_SMI_EN)
 877                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
 878         else
 879                 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
 880
 881         /* Clear special mode bits */
 882         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
 883                 outb_p(inb_p(SMBAUXCTL(priv)) &
 884                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 885
 886         /* set up the sysfs linkage to our parent device */
 887         priv->adapter.dev.parent = &dev->dev;
 888
 889         /* Retry up to 3 times on lost arbitration */
 890         priv->adapter.retries = 3;
 891
 892         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
 893                 "SMBus I801 adapter at %04lx", priv->smba);
 894         err = i2c_add_adapter(&priv->adapter);
 895         if (err) {
 896                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
 897                 goto exit_release;
 898         }
 899
 900         i801_probe_optional_slaves(priv);
 901
 902         pci_set_drvdata(dev, priv);
 903         return 0;
 904
 905 exit_release:
 906         pci_release_region(dev, SMBBAR);
 907 exit:
 908         kfree(priv);
 909         return err;
 910 }
 911
 912 static void __devexit i801_remove(struct pci_dev *dev)
 913 {
 914         struct i801_priv *priv = pci_get_drvdata(dev);
 915
 916         i2c_del_adapter(&priv->adapter);
 917         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 918         pci_release_region(dev, SMBBAR);
 919         pci_set_drvdata(dev, NULL);
 920         kfree(priv);
 921         /*
 922          * do not call pci_disable_device(dev) since it can cause hard hangs on
 923          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
 924          */
 925 }
 926
 927 #ifdef CONFIG_PM
 928 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
 929 {
 930         struct i801_priv *priv = pci_get_drvdata(dev);
 931
 932         pci_save_state(dev);
 933         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 934         pci_set_power_state(dev, pci_choose_state(dev, mesg));
 935         return 0;
 936 }
 937
 938 static int i801_resume(struct pci_dev *dev)
 939 {
 940         pci_set_power_state(dev, PCI_D0);
 941         pci_restore_state(dev);
 942         return pci_enable_device(dev);
 943 }
 944 #else
 945 #define i801_suspend NULL
 946 #define i801_resume NULL
 947 #endif
 948
 949 static struct pci_driver i801_driver = {
 950         .name           = "i801_smbus",
 951         .id_table       = i801_ids,
 952         .probe          = i801_probe,
 953         .remove         = __devexit_p(i801_remove),
 954         .suspend        = i801_suspend,
 955         .resume         = i801_resume,
 956 };
 957
 958 static int __init i2c_i801_init(void)
 959 {
 960         if (dmi_name_in_vendors("FUJITSU"))
 961                 input_apanel_init();
 962         return pci_register_driver(&i801_driver);
 963 }
 964
 965 static void __exit i2c_i801_exit(void)
 966 {
 967         pci_unregister_driver(&i801_driver);
 968 }
 969
 970 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
 971               "Jean Delvare <khali@linux-fr.org>");
 972 MODULE_DESCRIPTION("I801 SMBus driver");
 973 MODULE_LICENSE("GPL");
 974
 975 module_init(i2c_i801_init);
 976 module_exit(i2c_i801_exit);