drivers/i2c/busses/i2c-eg20t.c

   1 /*
   2  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/i2c.h>
  24 #include <linux/fs.h>
  25 #include <linux/io.h>
  26 #include <linux/types.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/jiffies.h>
  29 #include <linux/pci.h>
  30 #include <linux/mutex.h>
  31 #include <linux/ktime.h>
  32 #include <linux/slab.h>
  33
  34 #define PCH_EVENT_SET   0       /* I2C Interrupt Event Set Status */
  35 #define PCH_EVENT_NONE  1       /* I2C Interrupt Event Clear Status */
  36 #define PCH_MAX_CLK             100000  /* Maximum Clock speed in MHz */
  37 #define PCH_BUFFER_MODE_ENABLE  0x0002  /* flag for Buffer mode enable */
  38 #define PCH_EEPROM_SW_RST_MODE_ENABLE   0x0008  /* EEPROM SW RST enable flag */
  39
  40 #define PCH_I2CSADR     0x00    /* I2C slave address register */
  41 #define PCH_I2CCTL      0x04    /* I2C control register */
  42 #define PCH_I2CSR       0x08    /* I2C status register */
  43 #define PCH_I2CDR       0x0C    /* I2C data register */
  44 #define PCH_I2CMON      0x10    /* I2C bus monitor register */
  45 #define PCH_I2CBC       0x14    /* I2C bus transfer rate setup counter */
  46 #define PCH_I2CMOD      0x18    /* I2C mode register */
  47 #define PCH_I2CBUFSLV   0x1C    /* I2C buffer mode slave address register */
  48 #define PCH_I2CBUFSUB   0x20    /* I2C buffer mode subaddress register */
  49 #define PCH_I2CBUFFOR   0x24    /* I2C buffer mode format register */
  50 #define PCH_I2CBUFCTL   0x28    /* I2C buffer mode control register */
  51 #define PCH_I2CBUFMSK   0x2C    /* I2C buffer mode interrupt mask register */
  52 #define PCH_I2CBUFSTA   0x30    /* I2C buffer mode status register */
  53 #define PCH_I2CBUFLEV   0x34    /* I2C buffer mode level register */
  54 #define PCH_I2CESRFOR   0x38    /* EEPROM software reset mode format register */
  55 #define PCH_I2CESRCTL   0x3C    /* EEPROM software reset mode ctrl register */
  56 #define PCH_I2CESRMSK   0x40    /* EEPROM software reset mode */
  57 #define PCH_I2CESRSTA   0x44    /* EEPROM software reset mode status register */
  58 #define PCH_I2CTMR      0x48    /* I2C timer register */
  59 #define PCH_I2CSRST     0xFC    /* I2C reset register */
  60 #define PCH_I2CNF       0xF8    /* I2C noise filter register */
  61
  62 #define BUS_IDLE_TIMEOUT        20
  63 #define PCH_I2CCTL_I2CMEN       0x0080
  64 #define TEN_BIT_ADDR_DEFAULT    0xF000
  65 #define TEN_BIT_ADDR_MASK       0xF0
  66 #define PCH_START               0x0020
  67 #define PCH_RESTART             0x0004
  68 #define PCH_ESR_START           0x0001
  69 #define PCH_BUFF_START          0x1
  70 #define PCH_REPSTART            0x0004
  71 #define PCH_ACK                 0x0008
  72 #define PCH_GETACK              0x0001
  73 #define CLR_REG                 0x0
  74 #define I2C_RD                  0x1
  75 #define I2CMCF_BIT              0x0080
  76 #define I2CMIF_BIT              0x0002
  77 #define I2CMAL_BIT              0x0010
  78 #define I2CBMFI_BIT             0x0001
  79 #define I2CBMAL_BIT             0x0002
  80 #define I2CBMNA_BIT             0x0004
  81 #define I2CBMTO_BIT             0x0008
  82 #define I2CBMIS_BIT             0x0010
  83 #define I2CESRFI_BIT            0X0001
  84 #define I2CESRTO_BIT            0x0002
  85 #define I2CESRFIIE_BIT          0x1
  86 #define I2CESRTOIE_BIT          0x2
  87 #define I2CBMDZ_BIT             0x0040
  88 #define I2CBMAG_BIT             0x0020
  89 #define I2CMBB_BIT              0x0020
  90 #define BUFFER_MODE_MASK        (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
  91                                 I2CBMTO_BIT | I2CBMIS_BIT)
  92 #define I2C_ADDR_MSK            0xFF
  93 #define I2C_MSB_2B_MSK          0x300
  94 #define FAST_MODE_CLK           400
  95 #define FAST_MODE_EN            0x0001
  96 #define SUB_ADDR_LEN_MAX        4
  97 #define BUF_LEN_MAX             32
  98 #define PCH_BUFFER_MODE         0x1
  99 #define EEPROM_SW_RST_MODE      0x0002
 100 #define NORMAL_INTR_ENBL        0x0300
 101 #define EEPROM_RST_INTR_ENBL    (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
 102 #define EEPROM_RST_INTR_DISBL   0x0
 103 #define BUFFER_MODE_INTR_ENBL   0x001F
 104 #define BUFFER_MODE_INTR_DISBL  0x0
 105 #define NORMAL_MODE             0x0
 106 #define BUFFER_MODE             0x1
 107 #define EEPROM_SR_MODE          0x2
 108 #define I2C_TX_MODE             0x0010
 109 #define PCH_BUF_TX              0xFFF7
 110 #define PCH_BUF_RD              0x0008
 111 #define I2C_ERROR_MASK  (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
 112                         I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
 113 #define I2CMAL_EVENT            0x0001
 114 #define I2CMCF_EVENT            0x0002
 115 #define I2CBMFI_EVENT           0x0004
 116 #define I2CBMAL_EVENT           0x0008
 117 #define I2CBMNA_EVENT           0x0010
 118 #define I2CBMTO_EVENT           0x0020
 119 #define I2CBMIS_EVENT           0x0040
 120 #define I2CESRFI_EVENT          0x0080
 121 #define I2CESRTO_EVENT          0x0100
 122 #define PCI_DEVICE_ID_PCH_I2C   0x8817
 123
 124 #define pch_dbg(adap, fmt, arg...)  \
 125         dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 126
 127 #define pch_err(adap, fmt, arg...)  \
 128         dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 129
 130 #define pch_pci_err(pdev, fmt, arg...)  \
 131         dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
 132
 133 #define pch_pci_dbg(pdev, fmt, arg...)  \
 134         dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
 135
 136 /*
 137 Set the number of I2C instance max
 138 Intel EG20T PCH :               1ch
 139 OKI SEMICONDUCTOR ML7213 IOH :  2ch
 140 */
 141 #define PCH_I2C_MAX_DEV                 2
 142
 143 /**
 144  * struct i2c_algo_pch_data - for I2C driver functionalities
 145  * @pch_adapter:                stores the reference to i2c_adapter structure
 146  * @p_adapter_info:             stores the reference to adapter_info structure
 147  * @pch_base_address:           specifies the remapped base address
 148  * @pch_buff_mode_en:           specifies if buffer mode is enabled
 149  * @pch_event_flag:             specifies occurrence of interrupt events
 150  * @pch_i2c_xfer_in_progress:   specifies whether the transfer is completed
 151  */
 152 struct i2c_algo_pch_data {
 153         struct i2c_adapter pch_adapter;
 154         struct adapter_info *p_adapter_info;
 155         void __iomem *pch_base_address;
 156         int pch_buff_mode_en;
 157         u32 pch_event_flag;
 158         bool pch_i2c_xfer_in_progress;
 159 };
 160
 161 /**
 162  * struct adapter_info - This structure holds the adapter information for the
 163                          PCH i2c controller
 164  * @pch_data:           stores a list of i2c_algo_pch_data
 165  * @pch_i2c_suspended:  specifies whether the system is suspended or not
 166  *                      perhaps with more lines and words.
 167  * @ch_num:             specifies the number of i2c instance
 168  *
 169  * pch_data has as many elements as maximum I2C channels
 170  */
 171 struct adapter_info {
 172         struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
 173         bool pch_i2c_suspended;
 174         int ch_num;
 175 };
 176
 177
 178 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
 179 static int pch_clk = 50000;     /* specifies I2C clock speed in KHz */
 180 static wait_queue_head_t pch_event;
 181 static DEFINE_MUTEX(pch_mutex);
 182
 183 /* Definition for ML7213 by OKI SEMICONDUCTOR */
 184 #define PCI_VENDOR_ID_ROHM              0x10DB
 185 #define PCI_DEVICE_ID_ML7213_I2C        0x802D
 186 #define PCI_DEVICE_ID_ML7223_I2C        0x8010
 187
 188 static struct pci_device_id __devinitdata pch_pcidev_id[] = {
 189         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C),   1, },
 190         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
 191         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
 192         {0,}
 193 };
 194
 195 static irqreturn_t pch_i2c_handler(int irq, void *pData);
 196
 197 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
 198 {
 199         u32 val;
 200         val = ioread32(addr + offset);
 201         val |= bitmask;
 202         iowrite32(val, addr + offset);
 203 }
 204
 205 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
 206 {
 207         u32 val;
 208         val = ioread32(addr + offset);
 209         val &= (~bitmask);
 210         iowrite32(val, addr + offset);
 211 }
 212
 213 /**
 214  * pch_i2c_init() - hardware initialization of I2C module
 215  * @adap:       Pointer to struct i2c_algo_pch_data.
 216  */
 217 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
 218 {
 219         void __iomem *p = adap->pch_base_address;
 220         u32 pch_i2cbc;
 221         u32 pch_i2ctmr;
 222         u32 reg_value;
 223
 224         /* reset I2C controller */
 225         iowrite32(0x01, p + PCH_I2CSRST);
 226         msleep(20);
 227         iowrite32(0x0, p + PCH_I2CSRST);
 228
 229         /* Initialize I2C registers */
 230         iowrite32(0x21, p + PCH_I2CNF);
 231
 232         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
 233
 234         if (pch_i2c_speed != 400)
 235                 pch_i2c_speed = 100;
 236
 237         reg_value = PCH_I2CCTL_I2CMEN;
 238         if (pch_i2c_speed == FAST_MODE_CLK) {
 239                 reg_value |= FAST_MODE_EN;
 240                 pch_dbg(adap, "Fast mode enabled\n");
 241         }
 242
 243         if (pch_clk > PCH_MAX_CLK)
 244                 pch_clk = 62500;
 245
 246         pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / pch_i2c_speed * 8;
 247         /* Set transfer speed in I2CBC */
 248         iowrite32(pch_i2cbc, p + PCH_I2CBC);
 249
 250         pch_i2ctmr = (pch_clk) / 8;
 251         iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
 252
 253         reg_value |= NORMAL_INTR_ENBL;  /* Enable interrupts in normal mode */
 254         iowrite32(reg_value, p + PCH_I2CCTL);
 255
 256         pch_dbg(adap,
 257                 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
 258                 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
 259
 260         init_waitqueue_head(&pch_event);
 261 }
 262
 263 static inline bool ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
 264 {
 265         return cmp1.tv64 < cmp2.tv64;
 266 }
 267
 268 /**
 269  * pch_i2c_wait_for_bus_idle() - check the status of bus.
 270  * @adap:       Pointer to struct i2c_algo_pch_data.
 271  * @timeout:    waiting time counter (us).
 272  */
 273 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
 274                                      s32 timeout)
 275 {
 276         void __iomem *p = adap->pch_base_address;
 277         ktime_t ns_val;
 278
 279         if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
 280                 return 0;
 281
 282         /* MAX timeout value is timeout*1000*1000nsec */
 283         ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
 284         do {
 285                 msleep(20);
 286                 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
 287                         return 0;
 288         } while (ktime_lt(ktime_get(), ns_val));
 289
 290         pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 291         pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME);
 292
 293         return -ETIME;
 294 }
 295
 296 /**
 297  * pch_i2c_start() - Generate I2C start condition in normal mode.
 298  * @adap:       Pointer to struct i2c_algo_pch_data.
 299  *
 300  * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
 301  */
 302 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
 303 {
 304         void __iomem *p = adap->pch_base_address;
 305         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 306         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 307 }
 308
 309 /**
 310  * pch_i2c_wait_for_xfer_complete() - initiates a wait for the tx complete event
 311  * @adap:       Pointer to struct i2c_algo_pch_data.
 312  */
 313 static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
 314 {
 315         long ret;
 316         ret = wait_event_timeout(pch_event,
 317                         (adap->pch_event_flag != 0), msecs_to_jiffies(50));
 318
 319         if (ret == 0) {
 320                 pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
 321                 return -ETIMEDOUT;
 322         }
 323
 324         if (adap->pch_event_flag & I2C_ERROR_MASK) {
 325                 pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
 326                 return -EIO;
 327         }
 328
 329         adap->pch_event_flag = 0;
 330
 331         return 0;
 332 }
 333
 334 /**
 335  * pch_i2c_getack() - to confirm ACK/NACK
 336  * @adap:       Pointer to struct i2c_algo_pch_data.
 337  */
 338 static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap)
 339 {
 340         u32 reg_val;
 341         void __iomem *p = adap->pch_base_address;
 342         reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
 343
 344         if (reg_val != 0) {
 345                 pch_err(adap, "return%d\n", -EPROTO);
 346                 return -EPROTO;
 347         }
 348
 349         return 0;
 350 }
 351
 352 /**
 353  * pch_i2c_stop() - generate stop condition in normal mode.
 354  * @adap:       Pointer to struct i2c_algo_pch_data.
 355  */
 356 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
 357 {
 358         void __iomem *p = adap->pch_base_address;
 359         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 360         /* clear the start bit */
 361         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 362 }
 363
 364 /**
 365  * pch_i2c_repstart() - generate repeated start condition in normal mode
 366  * @adap:       Pointer to struct i2c_algo_pch_data.
 367  */
 368 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
 369 {
 370         void __iomem *p = adap->pch_base_address;
 371         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 372         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
 373 }
 374
 375 /**
 376  * pch_i2c_writebytes() - write data to I2C bus in normal mode
 377  * @i2c_adap:   Pointer to the struct i2c_adapter.
 378  * @last:       specifies whether last message or not.
 379  *              In the case of compound mode it will be 1 for last message,
 380  *              otherwise 0.
 381  * @first:      specifies whether first message or not.
 382  *              1 for first message otherwise 0.
 383  */
 384 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
 385                               struct i2c_msg *msgs, u32 last, u32 first)
 386 {
 387         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 388         u8 *buf;
 389         u32 length;
 390         u32 addr;
 391         u32 addr_2_msb;
 392         u32 addr_8_lsb;
 393         s32 wrcount;
 394         void __iomem *p = adap->pch_base_address;
 395
 396         length = msgs->len;
 397         buf = msgs->buf;
 398         addr = msgs->addr;
 399
 400         /* enable master tx */
 401         pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 402
 403         pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
 404                 length);
 405
 406         if (first) {
 407                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 408                         return -ETIME;
 409         }
 410
 411         if (msgs->flags & I2C_M_TEN) {
 412                 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
 413                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 414                 if (first)
 415                         pch_i2c_start(adap);
 416                 if (pch_i2c_wait_for_xfer_complete(adap) == 0 &&
 417                     pch_i2c_getack(adap) == 0) {
 418                         addr_8_lsb = (addr & I2C_ADDR_MSK);
 419                         iowrite32(addr_8_lsb, p + PCH_I2CDR);
 420                 } else {
 421                         pch_i2c_stop(adap);
 422                         return -ETIME;
 423                 }
 424         } else {
 425                 /* set 7 bit slave address and R/W bit as 0 */
 426                 iowrite32(addr << 1, p + PCH_I2CDR);
 427                 if (first)
 428                         pch_i2c_start(adap);
 429         }
 430
 431         if ((pch_i2c_wait_for_xfer_complete(adap) == 0) &&
 432             (pch_i2c_getack(adap) == 0)) {
 433                 for (wrcount = 0; wrcount < length; ++wrcount) {
 434                         /* write buffer value to I2C data register */
 435                         iowrite32(buf[wrcount], p + PCH_I2CDR);
 436                         pch_dbg(adap, "writing %x to Data register\n",
 437                                 buf[wrcount]);
 438
 439                         if (pch_i2c_wait_for_xfer_complete(adap) != 0)
 440                                 return -ETIME;
 441
 442                         if (pch_i2c_getack(adap))
 443                                 return -EIO;
 444                 }
 445
 446                 /* check if this is the last message */
 447                 if (last)
 448                         pch_i2c_stop(adap);
 449                 else
 450                         pch_i2c_repstart(adap);
 451         } else {
 452                 pch_i2c_stop(adap);
 453                 return -EIO;
 454         }
 455
 456         pch_dbg(adap, "return=%d\n", wrcount);
 457
 458         return wrcount;
 459 }
 460
 461 /**
 462  * pch_i2c_sendack() - send ACK
 463  * @adap:       Pointer to struct i2c_algo_pch_data.
 464  */
 465 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
 466 {
 467         void __iomem *p = adap->pch_base_address;
 468         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 469         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 470 }
 471
 472 /**
 473  * pch_i2c_sendnack() - send NACK
 474  * @adap:       Pointer to struct i2c_algo_pch_data.
 475  */
 476 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
 477 {
 478         void __iomem *p = adap->pch_base_address;
 479         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 480         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 481 }
 482
 483 /**
 484  * pch_i2c_restart() - Generate I2C restart condition in normal mode.
 485  * @adap:       Pointer to struct i2c_algo_pch_data.
 486  *
 487  * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
 488  */
 489 static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
 490 {
 491         void __iomem *p = adap->pch_base_address;
 492         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 493         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
 494 }
 495
 496 /**
 497  * pch_i2c_readbytes() - read data  from I2C bus in normal mode.
 498  * @i2c_adap:   Pointer to the struct i2c_adapter.
 499  * @msgs:       Pointer to i2c_msg structure.
 500  * @last:       specifies whether last message or not.
 501  * @first:      specifies whether first message or not.
 502  */
 503 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
 504                              u32 last, u32 first)
 505 {
 506         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 507
 508         u8 *buf;
 509         u32 count;
 510         u32 length;
 511         u32 addr;
 512         u32 addr_2_msb;
 513         u32 addr_8_lsb;
 514         void __iomem *p = adap->pch_base_address;
 515
 516         length = msgs->len;
 517         buf = msgs->buf;
 518         addr = msgs->addr;
 519
 520         /* enable master reception */
 521         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 522
 523         if (first) {
 524                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 525                         return -ETIME;
 526         }
 527
 528         if (msgs->flags & I2C_M_TEN) {
 529                 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
 530                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 531                 if (first)
 532                         pch_i2c_start(adap);
 533
 534                 rtn = pch_i2c_wait_for_xfer_complete(adap);
 535                 if (rtn == 0) {
 536                         if (pch_i2c_getack(adap)) {
 537                                 pch_dbg(adap, "Receive NACK for slave address"
 538                                         "setting\n");
 539                                 return -EIO;
 540                         }
 541                         addr_8_lsb = (addr & I2C_ADDR_MSK);
 542                         iowrite32(addr_8_lsb, p + PCH_I2CDR);
 543                 } else if (rtn == -EIO) { /* Arbitration Lost */
 544                         pch_err(adap, "Lost Arbitration\n");
 545                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 546                                    I2CMAL_BIT);
 547                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 548                                    I2CMIF_BIT);
 549                         pch_i2c_init(adap);
 550                         return -EAGAIN;
 551                 } else { /* wait-event timeout */
 552                         pch_i2c_stop(adap);
 553                         return -ETIME;
 554                 }
 555                 pch_i2c_restart(adap);
 556                 rtn = pch_i2c_wait_for_xfer_complete(adap);
 557                 if (rtn == 0) {
 558                         if (pch_i2c_getack(adap)) {
 559                                 pch_dbg(adap, "Receive NACK for slave address"
 560                                         "setting\n");
 561                                 return -EIO;
 562                         }
 563                         addr_2_msb |= I2C_RD;
 564                         iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK,
 565                                   p + PCH_I2CDR);
 566                 } else if (rtn == -EIO) { /* Arbitration Lost */
 567                         pch_err(adap, "Lost Arbitration\n");
 568                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 569                                    I2CMAL_BIT);
 570                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 571                                    I2CMIF_BIT);
 572                         pch_i2c_init(adap);
 573                         return -EAGAIN;
 574                 } else { /* wait-event timeout */
 575                         pch_i2c_stop(adap);
 576                         return -ETIME;
 577                 }
 578         } else {
 579                 /* 7 address bits + R/W bit */
 580                 addr = (((addr) << 1) | (I2C_RD));
 581                 iowrite32(addr, p + PCH_I2CDR);
 582         }
 583
 584         /* check if it is the first message */
 585         if (first)
 586                 pch_i2c_start(adap);
 587
 588         if ((pch_i2c_wait_for_xfer_complete(adap) == 0) &&
 589             (pch_i2c_getack(adap) == 0)) {
 590                 pch_dbg(adap, "return %d\n", 0);
 591
 592                 if (length == 0) {
 593                         pch_i2c_stop(adap);
 594                         ioread32(p + PCH_I2CDR); /* Dummy read needs */
 595
 596                         count = length;
 597                 } else {
 598                         int read_index;
 599                         int loop;
 600                         pch_i2c_sendack(adap);
 601
 602                         /* Dummy read */
 603                         for (loop = 1, read_index = 0; loop < length; loop++) {
 604                                 buf[read_index] = ioread32(p + PCH_I2CDR);
 605
 606                                 if (loop != 1)
 607                                         read_index++;
 608
 609                                 if (pch_i2c_wait_for_xfer_complete(adap) != 0) {
 610                                         pch_i2c_stop(adap);
 611                                         return -ETIME;
 612                                 }
 613                         }       /* end for */
 614
 615                         pch_i2c_sendnack(adap);
 616
 617                         buf[read_index] = ioread32(p + PCH_I2CDR);
 618
 619                         if (length != 1)
 620                                 read_index++;
 621
 622                         if (pch_i2c_wait_for_xfer_complete(adap) == 0) {
 623                                 if (last)
 624                                         pch_i2c_stop(adap);
 625                                 else
 626                                         pch_i2c_repstart(adap);
 627
 628                                 buf[read_index++] = ioread32(p + PCH_I2CDR);
 629                                 count = read_index;
 630                         } else {
 631                                 count = -ETIME;
 632                         }
 633
 634                 }
 635         } else {
 636                 count = -ETIME;
 637                 pch_i2c_stop(adap);
 638         }
 639
 640         return count;
 641 }
 642
 643 /**
 644  * pch_i2c_cb() - Interrupt handler Call back function
 645  * @adap:       Pointer to struct i2c_algo_pch_data.
 646  */
 647 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
 648 {
 649         u32 sts;
 650         void __iomem *p = adap->pch_base_address;
 651
 652         sts = ioread32(p + PCH_I2CSR);
 653         sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
 654         if (sts & I2CMAL_BIT)
 655                 adap->pch_event_flag |= I2CMAL_EVENT;
 656
 657         if (sts & I2CMCF_BIT)
 658                 adap->pch_event_flag |= I2CMCF_EVENT;
 659
 660         /* clear the applicable bits */
 661         pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
 662
 663         pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 664
 665         wake_up(&pch_event);
 666 }
 667
 668 /**
 669  * pch_i2c_handler() - interrupt handler for the PCH I2C controller
 670  * @irq:        irq number.
 671  * @pData:      cookie passed back to the handler function.
 672  */
 673 static irqreturn_t pch_i2c_handler(int irq, void *pData)
 674 {
 675         u32 reg_val;
 676         int flag;
 677         int i;
 678         struct adapter_info *adap_info = pData;
 679         void __iomem *p;
 680         u32 mode;
 681
 682         for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
 683                 p = adap_info->pch_data[i].pch_base_address;
 684                 mode = ioread32(p + PCH_I2CMOD);
 685                 mode &= BUFFER_MODE | EEPROM_SR_MODE;
 686                 if (mode != NORMAL_MODE) {
 687                         pch_err(adap_info->pch_data,
 688                                 "I2C-%d mode(%d) is not supported\n", mode, i);
 689                         continue;
 690                 }
 691                 reg_val = ioread32(p + PCH_I2CSR);
 692                 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
 693                         pch_i2c_cb(&adap_info->pch_data[i]);
 694                         flag = 1;
 695                 }
 696         }
 697
 698         return flag ? IRQ_HANDLED : IRQ_NONE;
 699 }
 700
 701 /**
 702  * pch_i2c_xfer() - Reading adnd writing data through I2C bus
 703  * @i2c_adap:   Pointer to the struct i2c_adapter.
 704  * @msgs:       Pointer to i2c_msg structure.
 705  * @num:        number of messages.
 706  */
 707 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
 708                         struct i2c_msg *msgs, s32 num)
 709 {
 710         struct i2c_msg *pmsg;
 711         u32 i = 0;
 712         u32 status;
 713         u32 msglen;
 714         u32 subaddrlen;
 715         s32 ret;
 716
 717         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 718
 719         ret = mutex_lock_interruptible(&pch_mutex);
 720         if (ret)
 721                 return -ERESTARTSYS;
 722
 723         if (adap->p_adapter_info->pch_i2c_suspended) {
 724                 mutex_unlock(&pch_mutex);
 725                 return -EBUSY;
 726         }
 727
 728         pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
 729                 adap->p_adapter_info->pch_i2c_suspended);
 730         /* transfer not completed */
 731         adap->pch_i2c_xfer_in_progress = true;
 732
 733         for (i = 0; i < num && ret >= 0; i++) {
 734                 pmsg = &msgs[i];
 735                 pmsg->flags |= adap->pch_buff_mode_en;
 736                 status = pmsg->flags;
 737                 pch_dbg(adap,
 738                         "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
 739                 /* calculate sub address length and message length */
 740                 /* these are applicable only for buffer mode */
 741                 subaddrlen = pmsg->buf[0];
 742                 /* calculate actual message length excluding
 743                  * the sub address fields */
 744                 msglen = (pmsg->len) - (subaddrlen + 1);
 745
 746                 if ((status & (I2C_M_RD)) != false) {
 747                         ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
 748                                                 (i == 0));
 749                 } else {
 750                         ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
 751                                                  (i == 0));
 752                 }
 753         }
 754
 755         adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
 756
 757         mutex_unlock(&pch_mutex);
 758
 759         return (ret < 0) ? ret : num;
 760 }
 761
 762 /**
 763  * pch_i2c_func() - return the functionality of the I2C driver
 764  * @adap:       Pointer to struct i2c_algo_pch_data.
 765  */
 766 static u32 pch_i2c_func(struct i2c_adapter *adap)
 767 {
 768         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 769 }
 770
 771 static struct i2c_algorithm pch_algorithm = {
 772         .master_xfer = pch_i2c_xfer,
 773         .functionality = pch_i2c_func
 774 };
 775
 776 /**
 777  * pch_i2c_disbl_int() - Disable PCH I2C interrupts
 778  * @adap:       Pointer to struct i2c_algo_pch_data.
 779  */
 780 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
 781 {
 782         void __iomem *p = adap->pch_base_address;
 783
 784         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
 785
 786         iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
 787
 788         iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
 789 }
 790
 791 static int __devinit pch_i2c_probe(struct pci_dev *pdev,
 792                                    const struct pci_device_id *id)
 793 {
 794         void __iomem *base_addr;
 795         int ret;
 796         int i, j;
 797         struct adapter_info *adap_info;
 798         struct i2c_adapter *pch_adap;
 799
 800         pch_pci_dbg(pdev, "Entered.\n");
 801
 802         adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
 803         if (adap_info == NULL) {
 804                 pch_pci_err(pdev, "Memory allocation FAILED\n");
 805                 return -ENOMEM;
 806         }
 807
 808         ret = pci_enable_device(pdev);
 809         if (ret) {
 810                 pch_pci_err(pdev, "pci_enable_device FAILED\n");
 811                 goto err_pci_enable;
 812         }
 813
 814         ret = pci_request_regions(pdev, KBUILD_MODNAME);
 815         if (ret) {
 816                 pch_pci_err(pdev, "pci_request_regions FAILED\n");
 817                 goto err_pci_req;
 818         }
 819
 820         base_addr = pci_iomap(pdev, 1, 0);
 821
 822         if (base_addr == NULL) {
 823                 pch_pci_err(pdev, "pci_iomap FAILED\n");
 824                 ret = -ENOMEM;
 825                 goto err_pci_iomap;
 826         }
 827
 828         /* Set the number of I2C channel instance */
 829         adap_info->ch_num = id->driver_data;
 830
 831         for (i = 0; i < adap_info->ch_num; i++) {
 832                 pch_adap = &adap_info->pch_data[i].pch_adapter;
 833                 adap_info->pch_i2c_suspended = false;
 834
 835                 adap_info->pch_data[i].p_adapter_info = adap_info;
 836
 837                 pch_adap->owner = THIS_MODULE;
 838                 pch_adap->class = I2C_CLASS_HWMON;
 839                 strcpy(pch_adap->name, KBUILD_MODNAME);
 840                 pch_adap->algo = &pch_algorithm;
 841                 pch_adap->algo_data = &adap_info->pch_data[i];
 842
 843                 /* base_addr + offset; */
 844                 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
 845
 846                 pch_adap->dev.parent = &pdev->dev;
 847
 848                 ret = i2c_add_adapter(pch_adap);
 849                 if (ret) {
 850                         pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
 851                         goto err_i2c_add_adapter;
 852                 }
 853
 854                 pch_i2c_init(&adap_info->pch_data[i]);
 855         }
 856         ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
 857                   KBUILD_MODNAME, adap_info);
 858         if (ret) {
 859                 pch_pci_err(pdev, "request_irq FAILED\n");
 860                 goto err_i2c_add_adapter;
 861         }
 862
 863         pci_set_drvdata(pdev, adap_info);
 864         pch_pci_dbg(pdev, "returns %d.\n", ret);
 865         return 0;
 866
 867 err_i2c_add_adapter:
 868         for (j = 0; j < i; j++)
 869                 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
 870         pci_iounmap(pdev, base_addr);
 871 err_pci_iomap:
 872         pci_release_regions(pdev);
 873 err_pci_req:
 874         pci_disable_device(pdev);
 875 err_pci_enable:
 876         kfree(adap_info);
 877         return ret;
 878 }
 879
 880 static void __devexit pch_i2c_remove(struct pci_dev *pdev)
 881 {
 882         int i;
 883         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 884
 885         free_irq(pdev->irq, adap_info);
 886
 887         for (i = 0; i < adap_info->ch_num; i++) {
 888                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 889                 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
 890         }
 891
 892         if (adap_info->pch_data[0].pch_base_address)
 893                 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
 894
 895         for (i = 0; i < adap_info->ch_num; i++)
 896                 adap_info->pch_data[i].pch_base_address = 0;
 897
 898         pci_set_drvdata(pdev, NULL);
 899
 900         pci_release_regions(pdev);
 901
 902         pci_disable_device(pdev);
 903         kfree(adap_info);
 904 }
 905
 906 #ifdef CONFIG_PM
 907 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
 908 {
 909         int ret;
 910         int i;
 911         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 912         void __iomem *p = adap_info->pch_data[0].pch_base_address;
 913
 914         adap_info->pch_i2c_suspended = true;
 915
 916         for (i = 0; i < adap_info->ch_num; i++) {
 917                 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
 918                         /* Wait until all channel transfers are completed */
 919                         msleep(20);
 920                 }
 921         }
 922
 923         /* Disable the i2c interrupts */
 924         for (i = 0; i < adap_info->ch_num; i++)
 925                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 926
 927         pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
 928                 "invoked function pch_i2c_disbl_int successfully\n",
 929                 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
 930                 ioread32(p + PCH_I2CESRSTA));
 931
 932         ret = pci_save_state(pdev);
 933
 934         if (ret) {
 935                 pch_pci_err(pdev, "pci_save_state\n");
 936                 return ret;
 937         }
 938
 939         pci_enable_wake(pdev, PCI_D3hot, 0);
 940         pci_disable_device(pdev);
 941         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 942
 943         return 0;
 944 }
 945
 946 static int pch_i2c_resume(struct pci_dev *pdev)
 947 {
 948         int i;
 949         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 950
 951         pci_set_power_state(pdev, PCI_D0);
 952         pci_restore_state(pdev);
 953
 954         if (pci_enable_device(pdev) < 0) {
 955                 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
 956                 return -EIO;
 957         }
 958
 959         pci_enable_wake(pdev, PCI_D3hot, 0);
 960
 961         for (i = 0; i < adap_info->ch_num; i++)
 962                 pch_i2c_init(&adap_info->pch_data[i]);
 963
 964         adap_info->pch_i2c_suspended = false;
 965
 966         return 0;
 967 }
 968 #else
 969 #define pch_i2c_suspend NULL
 970 #define pch_i2c_resume NULL
 971 #endif
 972
 973 static struct pci_driver pch_pcidriver = {
 974         .name = KBUILD_MODNAME,
 975         .id_table = pch_pcidev_id,
 976         .probe = pch_i2c_probe,
 977         .remove = __devexit_p(pch_i2c_remove),
 978         .suspend = pch_i2c_suspend,
 979         .resume = pch_i2c_resume
 980 };
 981
 982 static int __init pch_pci_init(void)
 983 {
 984         return pci_register_driver(&pch_pcidriver);
 985 }
 986 module_init(pch_pci_init);
 987
 988 static void __exit pch_pci_exit(void)
 989 {
 990         pci_unregister_driver(&pch_pcidriver);
 991 }
 992 module_exit(pch_pci_exit);
 993
 994 MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH I2C Driver");
 995 MODULE_LICENSE("GPL");
 996 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.okisemi.com>");
 997 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
 998 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));