drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #include "atom.h"
  27 #ifdef CONFIG_ACPI
  28 #include <linux/acpi.h>
  29 #endif
  30 #include <linux/power_supply.h>
  31 #include <linux/hwmon.h>
  32 #include <linux/hwmon-sysfs.h>
  33
  34 #define RADEON_IDLE_LOOP_MS 100
  35 #define RADEON_RECLOCK_DELAY_MS 200
  36 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  37 #define RADEON_WAIT_IDLE_TIMEOUT 200
  38
  39 static const char *radeon_pm_state_type_name[5] = {
  40         "Default",
  41         "Powersave",
  42         "Battery",
  43         "Balanced",
  44         "Performance",
  45 };
  46
  47 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  48 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  49 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  50 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  51 static void radeon_pm_update_profile(struct radeon_device *rdev);
  52 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  53
  54 #define ACPI_AC_CLASS           "ac_adapter"
  55
  56 int radeon_pm_get_type_index(struct radeon_device *rdev,
  57                              enum radeon_pm_state_type ps_type,
  58                              int instance)
  59 {
  60         int i;
  61         int found_instance = -1;
  62
  63         for (i = 0; i < rdev->pm.num_power_states; i++) {
  64                 if (rdev->pm.power_state[i].type == ps_type) {
  65                         found_instance++;
  66                         if (found_instance == instance)
  67                                 return i;
  68                 }
  69         }
  70         /* return default if no match */
  71         return rdev->pm.default_power_state_index;
  72 }
  73
  74 #ifdef CONFIG_ACPI
  75 static int radeon_acpi_event(struct notifier_block *nb,
  76                              unsigned long val,
  77                              void *data)
  78 {
  79         struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
  80         struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
  81
  82         if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
  83                 if (power_supply_is_system_supplied() > 0)
  84                         DRM_DEBUG_DRIVER("pm: AC\n");
  85                 else
  86                         DRM_DEBUG_DRIVER("pm: DC\n");
  87
  88                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  89                         if (rdev->pm.profile == PM_PROFILE_AUTO) {
  90                                 mutex_lock(&rdev->pm.mutex);
  91                                 radeon_pm_update_profile(rdev);
  92                                 radeon_pm_set_clocks(rdev);
  93                                 mutex_unlock(&rdev->pm.mutex);
  94                         }
  95                 }
  96         }
  97
  98         return NOTIFY_OK;
  99 }
 100 #endif
 101
 102 static void radeon_pm_update_profile(struct radeon_device *rdev)
 103 {
 104         switch (rdev->pm.profile) {
 105         case PM_PROFILE_DEFAULT:
 106                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
 107                 break;
 108         case PM_PROFILE_AUTO:
 109                 if (power_supply_is_system_supplied() > 0) {
 110                         if (rdev->pm.active_crtc_count > 1)
 111                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 112                         else
 113                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 114                 } else {
 115                         if (rdev->pm.active_crtc_count > 1)
 116                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 117                         else
 118                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 119                 }
 120                 break;
 121         case PM_PROFILE_LOW:
 122                 if (rdev->pm.active_crtc_count > 1)
 123                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 124                 else
 125                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 126                 break;
 127         case PM_PROFILE_MID:
 128                 if (rdev->pm.active_crtc_count > 1)
 129                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 130                 else
 131                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 132                 break;
 133         case PM_PROFILE_HIGH:
 134                 if (rdev->pm.active_crtc_count > 1)
 135                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 136                 else
 137                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 138                 break;
 139         }
 140
 141         if (rdev->pm.active_crtc_count == 0) {
 142                 rdev->pm.requested_power_state_index =
 143                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 144                 rdev->pm.requested_clock_mode_index =
 145                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 146         } else {
 147                 rdev->pm.requested_power_state_index =
 148                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 149                 rdev->pm.requested_clock_mode_index =
 150                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 151         }
 152 }
 153
 154 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 155 {
 156         struct radeon_bo *bo, *n;
 157
 158         if (list_empty(&rdev->gem.objects))
 159                 return;
 160
 161         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 162                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 163                         ttm_bo_unmap_virtual(&bo->tbo);
 164         }
 165 }
 166
 167 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 168 {
 169         if (rdev->pm.active_crtcs) {
 170                 rdev->pm.vblank_sync = false;
 171                 wait_event_timeout(
 172                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 173                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 174         }
 175 }
 176
 177 static void radeon_set_power_state(struct radeon_device *rdev)
 178 {
 179         u32 sclk, mclk;
 180         bool misc_after = false;
 181
 182         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 183             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 184                 return;
 185
 186         if (radeon_gui_idle(rdev)) {
 187                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 188                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 189                 if (sclk > rdev->pm.default_sclk)
 190                         sclk = rdev->pm.default_sclk;
 191
 192                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 193                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 194                 if (mclk > rdev->pm.default_mclk)
 195                         mclk = rdev->pm.default_mclk;
 196
 197                 /* upvolt before raising clocks, downvolt after lowering clocks */
 198                 if (sclk < rdev->pm.current_sclk)
 199                         misc_after = true;
 200
 201                 radeon_sync_with_vblank(rdev);
 202
 203                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 204                         if (!radeon_pm_in_vbl(rdev))
 205                                 return;
 206                 }
 207
 208                 radeon_pm_prepare(rdev);
 209
 210                 if (!misc_after)
 211                         /* voltage, pcie lanes, etc.*/
 212                         radeon_pm_misc(rdev);
 213
 214                 /* set engine clock */
 215                 if (sclk != rdev->pm.current_sclk) {
 216                         radeon_pm_debug_check_in_vbl(rdev, false);
 217                         radeon_set_engine_clock(rdev, sclk);
 218                         radeon_pm_debug_check_in_vbl(rdev, true);
 219                         rdev->pm.current_sclk = sclk;
 220                         DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
 221                 }
 222
 223                 /* set memory clock */
 224                 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 225                         radeon_pm_debug_check_in_vbl(rdev, false);
 226                         radeon_set_memory_clock(rdev, mclk);
 227                         radeon_pm_debug_check_in_vbl(rdev, true);
 228                         rdev->pm.current_mclk = mclk;
 229                         DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
 230                 }
 231
 232                 if (misc_after)
 233                         /* voltage, pcie lanes, etc.*/
 234                         radeon_pm_misc(rdev);
 235
 236                 radeon_pm_finish(rdev);
 237
 238                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 239                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 240         } else
 241                 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 242 }
 243
 244 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 245 {
 246         int i;
 247
 248         /* no need to take locks, etc. if nothing's going to change */
 249         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 250             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 251                 return;
 252
 253         mutex_lock(&rdev->ddev->struct_mutex);
 254         mutex_lock(&rdev->vram_mutex);
 255         mutex_lock(&rdev->cp.mutex);
 256
 257         /* gui idle int has issues on older chips it seems */
 258         if (rdev->family >= CHIP_R600) {
 259                 if (rdev->irq.installed) {
 260                         /* wait for GPU idle */
 261                         rdev->pm.gui_idle = false;
 262                         rdev->irq.gui_idle = true;
 263                         radeon_irq_set(rdev);
 264                         wait_event_interruptible_timeout(
 265                                 rdev->irq.idle_queue, rdev->pm.gui_idle,
 266                                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
 267                         rdev->irq.gui_idle = false;
 268                         radeon_irq_set(rdev);
 269                 }
 270         } else {
 271                 if (rdev->cp.ready) {
 272                         struct radeon_fence *fence;
 273                         radeon_ring_alloc(rdev, 64);
 274                         radeon_fence_create(rdev, &fence);
 275                         radeon_fence_emit(rdev, fence);
 276                         radeon_ring_commit(rdev);
 277                         radeon_fence_wait(fence, false);
 278                         radeon_fence_unref(&fence);
 279                 }
 280         }
 281         radeon_unmap_vram_bos(rdev);
 282
 283         if (rdev->irq.installed) {
 284                 for (i = 0; i < rdev->num_crtc; i++) {
 285                         if (rdev->pm.active_crtcs & (1 << i)) {
 286                                 rdev->pm.req_vblank |= (1 << i);
 287                                 drm_vblank_get(rdev->ddev, i);
 288                         }
 289                 }
 290         }
 291
 292         radeon_set_power_state(rdev);
 293
 294         if (rdev->irq.installed) {
 295                 for (i = 0; i < rdev->num_crtc; i++) {
 296                         if (rdev->pm.req_vblank & (1 << i)) {
 297                                 rdev->pm.req_vblank &= ~(1 << i);
 298                                 drm_vblank_put(rdev->ddev, i);
 299                         }
 300                 }
 301         }
 302
 303         /* update display watermarks based on new power state */
 304         radeon_update_bandwidth_info(rdev);
 305         if (rdev->pm.active_crtc_count)
 306                 radeon_bandwidth_update(rdev);
 307
 308         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 309
 310         mutex_unlock(&rdev->cp.mutex);
 311         mutex_unlock(&rdev->vram_mutex);
 312         mutex_unlock(&rdev->ddev->struct_mutex);
 313 }
 314
 315 static void radeon_pm_print_states(struct radeon_device *rdev)
 316 {
 317         int i, j;
 318         struct radeon_power_state *power_state;
 319         struct radeon_pm_clock_info *clock_info;
 320
 321         DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
 322         for (i = 0; i < rdev->pm.num_power_states; i++) {
 323                 power_state = &rdev->pm.power_state[i];
 324                 DRM_DEBUG_DRIVER("State %d: %s\n", i,
 325                         radeon_pm_state_type_name[power_state->type]);
 326                 if (i == rdev->pm.default_power_state_index)
 327                         DRM_DEBUG_DRIVER("\tDefault");
 328                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 329                         DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 330                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 331                         DRM_DEBUG_DRIVER("\tSingle display only\n");
 332                 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 333                 for (j = 0; j < power_state->num_clock_modes; j++) {
 334                         clock_info = &(power_state->clock_info[j]);
 335                         if (rdev->flags & RADEON_IS_IGP)
 336                                 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
 337                                         j,
 338                                         clock_info->sclk * 10,
 339                                         clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
 340                         else
 341                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
 342                                         j,
 343                                         clock_info->sclk * 10,
 344                                         clock_info->mclk * 10,
 345                                         clock_info->voltage.voltage,
 346                                         clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
 347                 }
 348         }
 349 }
 350
 351 static ssize_t radeon_get_pm_profile(struct device *dev,
 352                                      struct device_attribute *attr,
 353                                      char *buf)
 354 {
 355         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 356         struct radeon_device *rdev = ddev->dev_private;
 357         int cp = rdev->pm.profile;
 358
 359         return snprintf(buf, PAGE_SIZE, "%s\n",
 360                         (cp == PM_PROFILE_AUTO) ? "auto" :
 361                         (cp == PM_PROFILE_LOW) ? "low" :
 362                         (cp == PM_PROFILE_MID) ? "mid" :
 363                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 364 }
 365
 366 static ssize_t radeon_set_pm_profile(struct device *dev,
 367                                      struct device_attribute *attr,
 368                                      const char *buf,
 369                                      size_t count)
 370 {
 371         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 372         struct radeon_device *rdev = ddev->dev_private;
 373
 374         mutex_lock(&rdev->pm.mutex);
 375         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 376                 if (strncmp("default", buf, strlen("default")) == 0)
 377                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 378                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 379                         rdev->pm.profile = PM_PROFILE_AUTO;
 380                 else if (strncmp("low", buf, strlen("low")) == 0)
 381                         rdev->pm.profile = PM_PROFILE_LOW;
 382                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 383                         rdev->pm.profile = PM_PROFILE_MID;
 384                 else if (strncmp("high", buf, strlen("high")) == 0)
 385                         rdev->pm.profile = PM_PROFILE_HIGH;
 386                 else {
 387                         count = -EINVAL;
 388                         goto fail;
 389                 }
 390                 radeon_pm_update_profile(rdev);
 391                 radeon_pm_set_clocks(rdev);
 392         } else
 393                 count = -EINVAL;
 394
 395 fail:
 396         mutex_unlock(&rdev->pm.mutex);
 397
 398         return count;
 399 }
 400
 401 static ssize_t radeon_get_pm_method(struct device *dev,
 402                                     struct device_attribute *attr,
 403                                     char *buf)
 404 {
 405         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 406         struct radeon_device *rdev = ddev->dev_private;
 407         int pm = rdev->pm.pm_method;
 408
 409         return snprintf(buf, PAGE_SIZE, "%s\n",
 410                         (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
 411 }
 412
 413 static ssize_t radeon_set_pm_method(struct device *dev,
 414                                     struct device_attribute *attr,
 415                                     const char *buf,
 416                                     size_t count)
 417 {
 418         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 419         struct radeon_device *rdev = ddev->dev_private;
 420
 421
 422         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 423                 mutex_lock(&rdev->pm.mutex);
 424                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 425                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 426                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 427                 mutex_unlock(&rdev->pm.mutex);
 428         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 429                 mutex_lock(&rdev->pm.mutex);
 430                 /* disable dynpm */
 431                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 432                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 433                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 434                 mutex_unlock(&rdev->pm.mutex);
 435                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 436         } else {
 437                 count = -EINVAL;
 438                 goto fail;
 439         }
 440         radeon_pm_compute_clocks(rdev);
 441 fail:
 442         return count;
 443 }
 444
 445 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 446 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 447
 448 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 449                                       struct device_attribute *attr,
 450                                       char *buf)
 451 {
 452         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 453         struct radeon_device *rdev = ddev->dev_private;
 454         int temp;
 455
 456         switch (rdev->pm.int_thermal_type) {
 457         case THERMAL_TYPE_RV6XX:
 458                 temp = rv6xx_get_temp(rdev);
 459                 break;
 460         case THERMAL_TYPE_RV770:
 461                 temp = rv770_get_temp(rdev);
 462                 break;
 463         case THERMAL_TYPE_EVERGREEN:
 464         case THERMAL_TYPE_NI:
 465                 temp = evergreen_get_temp(rdev);
 466                 break;
 467         case THERMAL_TYPE_SUMO:
 468                 temp = sumo_get_temp(rdev);
 469                 break;
 470         default:
 471                 temp = 0;
 472                 break;
 473         }
 474
 475         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 476 }
 477
 478 static ssize_t radeon_hwmon_show_name(struct device *dev,
 479                                       struct device_attribute *attr,
 480                                       char *buf)
 481 {
 482         return sprintf(buf, "radeon\n");
 483 }
 484
 485 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 486 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
 487
 488 static struct attribute *hwmon_attributes[] = {
 489         &sensor_dev_attr_temp1_input.dev_attr.attr,
 490         &sensor_dev_attr_name.dev_attr.attr,
 491         NULL
 492 };
 493
 494 static const struct attribute_group hwmon_attrgroup = {
 495         .attrs = hwmon_attributes,
 496 };
 497
 498 static int radeon_hwmon_init(struct radeon_device *rdev)
 499 {
 500         int err = 0;
 501
 502         rdev->pm.int_hwmon_dev = NULL;
 503
 504         switch (rdev->pm.int_thermal_type) {
 505         case THERMAL_TYPE_RV6XX:
 506         case THERMAL_TYPE_RV770:
 507         case THERMAL_TYPE_EVERGREEN:
 508         case THERMAL_TYPE_NI:
 509         case THERMAL_TYPE_SUMO:
 510                 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
 511                 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
 512                         err = PTR_ERR(rdev->pm.int_hwmon_dev);
 513                         dev_err(rdev->dev,
 514                                 "Unable to register hwmon device: %d\n", err);
 515                         break;
 516                 }
 517                 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
 518                 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
 519                                          &hwmon_attrgroup);
 520                 if (err) {
 521                         dev_err(rdev->dev,
 522                                 "Unable to create hwmon sysfs file: %d\n", err);
 523                         hwmon_device_unregister(rdev->dev);
 524                 }
 525                 break;
 526         default:
 527                 break;
 528         }
 529
 530         return err;
 531 }
 532
 533 static void radeon_hwmon_fini(struct radeon_device *rdev)
 534 {
 535         if (rdev->pm.int_hwmon_dev) {
 536                 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
 537                 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
 538         }
 539 }
 540
 541 void radeon_pm_suspend(struct radeon_device *rdev)
 542 {
 543         mutex_lock(&rdev->pm.mutex);
 544         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 545                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
 546                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
 547         }
 548         mutex_unlock(&rdev->pm.mutex);
 549
 550         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 551 }
 552
 553 void radeon_pm_resume(struct radeon_device *rdev)
 554 {
 555         /* set up the default clocks if the MC ucode is loaded */
 556         if ((rdev->family >= CHIP_BARTS) &&
 557             (rdev->family <= CHIP_CAYMAN) &&
 558             rdev->mc_fw) {
 559                 if (rdev->pm.default_vddc)
 560                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 561                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
 562                 if (rdev->pm.default_vddci)
 563                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 564                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
 565                 if (rdev->pm.default_sclk)
 566                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 567                 if (rdev->pm.default_mclk)
 568                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 569         }
 570         /* asic init will reset the default power state */
 571         mutex_lock(&rdev->pm.mutex);
 572         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 573         rdev->pm.current_clock_mode_index = 0;
 574         rdev->pm.current_sclk = rdev->pm.default_sclk;
 575         rdev->pm.current_mclk = rdev->pm.default_mclk;
 576         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
 577         rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
 578         if (rdev->pm.pm_method == PM_METHOD_DYNPM
 579             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
 580                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 581                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 582                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 583         }
 584         mutex_unlock(&rdev->pm.mutex);
 585         radeon_pm_compute_clocks(rdev);
 586 }
 587
 588 int radeon_pm_init(struct radeon_device *rdev)
 589 {
 590         int ret;
 591
 592         /* default to profile method */
 593         rdev->pm.pm_method = PM_METHOD_PROFILE;
 594         rdev->pm.profile = PM_PROFILE_DEFAULT;
 595         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 596         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 597         rdev->pm.dynpm_can_upclock = true;
 598         rdev->pm.dynpm_can_downclock = true;
 599         rdev->pm.default_sclk = rdev->clock.default_sclk;
 600         rdev->pm.default_mclk = rdev->clock.default_mclk;
 601         rdev->pm.current_sclk = rdev->clock.default_sclk;
 602         rdev->pm.current_mclk = rdev->clock.default_mclk;
 603         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
 604
 605         if (rdev->bios) {
 606                 if (rdev->is_atom_bios)
 607                         radeon_atombios_get_power_modes(rdev);
 608                 else
 609                         radeon_combios_get_power_modes(rdev);
 610                 radeon_pm_print_states(rdev);
 611                 radeon_pm_init_profile(rdev);
 612                 /* set up the default clocks if the MC ucode is loaded */
 613                 if ((rdev->family >= CHIP_BARTS) &&
 614                     (rdev->family <= CHIP_CAYMAN) &&
 615                     rdev->mc_fw) {
 616                         if (rdev->pm.default_vddc)
 617                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 618                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
 619                         if (rdev->pm.default_vddci)
 620                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 621                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
 622                         if (rdev->pm.default_sclk)
 623                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 624                         if (rdev->pm.default_mclk)
 625                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 626                 }
 627         }
 628
 629         /* set up the internal thermal sensor if applicable */
 630         ret = radeon_hwmon_init(rdev);
 631         if (ret)
 632                 return ret;
 633
 634         INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
 635
 636         if (rdev->pm.num_power_states > 1) {
 637                 /* where's the best place to put these? */
 638                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
 639                 if (ret)
 640                         DRM_ERROR("failed to create device file for power profile\n");
 641                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
 642                 if (ret)
 643                         DRM_ERROR("failed to create device file for power method\n");
 644
 645 #ifdef CONFIG_ACPI
 646                 rdev->acpi_nb.notifier_call = radeon_acpi_event;
 647                 register_acpi_notifier(&rdev->acpi_nb);
 648 #endif
 649                 if (radeon_debugfs_pm_init(rdev)) {
 650                         DRM_ERROR("Failed to register debugfs file for PM!\n");
 651                 }
 652
 653                 DRM_INFO("radeon: power management initialized\n");
 654         }
 655
 656         return 0;
 657 }
 658
 659 void radeon_pm_fini(struct radeon_device *rdev)
 660 {
 661         if (rdev->pm.num_power_states > 1) {
 662                 mutex_lock(&rdev->pm.mutex);
 663                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 664                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 665                         radeon_pm_update_profile(rdev);
 666                         radeon_pm_set_clocks(rdev);
 667                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 668                         /* reset default clocks */
 669                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 670                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 671                         radeon_pm_set_clocks(rdev);
 672                 }
 673                 mutex_unlock(&rdev->pm.mutex);
 674
 675                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 676
 677                 device_remove_file(rdev->dev, &dev_attr_power_profile);
 678                 device_remove_file(rdev->dev, &dev_attr_power_method);
 679 #ifdef CONFIG_ACPI
 680                 unregister_acpi_notifier(&rdev->acpi_nb);
 681 #endif
 682         }
 683
 684         if (rdev->pm.power_state)
 685                 kfree(rdev->pm.power_state);
 686
 687         radeon_hwmon_fini(rdev);
 688 }
 689
 690 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 691 {
 692         struct drm_device *ddev = rdev->ddev;
 693         struct drm_crtc *crtc;
 694         struct radeon_crtc *radeon_crtc;
 695
 696         if (rdev->pm.num_power_states < 2)
 697                 return;
 698
 699         mutex_lock(&rdev->pm.mutex);
 700
 701         rdev->pm.active_crtcs = 0;
 702         rdev->pm.active_crtc_count = 0;
 703         list_for_each_entry(crtc,
 704                 &ddev->mode_config.crtc_list, head) {
 705                 radeon_crtc = to_radeon_crtc(crtc);
 706                 if (radeon_crtc->enabled) {
 707                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 708                         rdev->pm.active_crtc_count++;
 709                 }
 710         }
 711
 712         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 713                 radeon_pm_update_profile(rdev);
 714                 radeon_pm_set_clocks(rdev);
 715         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 716                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
 717                         if (rdev->pm.active_crtc_count > 1) {
 718                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 719                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 720
 721                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 722                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 723                                         radeon_pm_get_dynpm_state(rdev);
 724                                         radeon_pm_set_clocks(rdev);
 725
 726                                         DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
 727                                 }
 728                         } else if (rdev->pm.active_crtc_count == 1) {
 729                                 /* TODO: Increase clocks if needed for current mode */
 730
 731                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
 732                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 733                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
 734                                         radeon_pm_get_dynpm_state(rdev);
 735                                         radeon_pm_set_clocks(rdev);
 736
 737                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 738                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 739                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
 740                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 741                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 742                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 743                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
 744                                 }
 745                         } else { /* count == 0 */
 746                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
 747                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 748
 749                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
 750                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
 751                                         radeon_pm_get_dynpm_state(rdev);
 752                                         radeon_pm_set_clocks(rdev);
 753                                 }
 754                         }
 755                 }
 756         }
 757
 758         mutex_unlock(&rdev->pm.mutex);
 759 }
 760
 761 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
 762 {
 763         int  crtc, vpos, hpos, vbl_status;
 764         bool in_vbl = true;
 765
 766         /* Iterate over all active crtc's. All crtc's must be in vblank,
 767          * otherwise return in_vbl == false.
 768          */
 769         for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
 770                 if (rdev->pm.active_crtcs & (1 << crtc)) {
 771                         vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
 772                         if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
 773                             !(vbl_status & DRM_SCANOUTPOS_INVBL))
 774                                 in_vbl = false;
 775                 }
 776         }
 777
 778         return in_vbl;
 779 }
 780
 781 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 782 {
 783         u32 stat_crtc = 0;
 784         bool in_vbl = radeon_pm_in_vbl(rdev);
 785
 786         if (in_vbl == false)
 787                 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
 788                          finish ? "exit" : "entry");
 789         return in_vbl;
 790 }
 791
 792 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
 793 {
 794         struct radeon_device *rdev;
 795         int resched;
 796         rdev = container_of(work, struct radeon_device,
 797                                 pm.dynpm_idle_work.work);
 798
 799         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 800         mutex_lock(&rdev->pm.mutex);
 801         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 802                 unsigned long irq_flags;
 803                 int not_processed = 0;
 804
 805                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 806                 if (!list_empty(&rdev->fence_drv.emited)) {
 807                         struct list_head *ptr;
 808                         list_for_each(ptr, &rdev->fence_drv.emited) {
 809                                 /* count up to 3, that's enought info */
 810                                 if (++not_processed >= 3)
 811                                         break;
 812                         }
 813                 }
 814                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 815
 816                 if (not_processed >= 3) { /* should upclock */
 817                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
 818                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 819                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 820                                    rdev->pm.dynpm_can_upclock) {
 821                                 rdev->pm.dynpm_planned_action =
 822                                         DYNPM_ACTION_UPCLOCK;
 823                                 rdev->pm.dynpm_action_timeout = jiffies +
 824                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 825                         }
 826                 } else if (not_processed == 0) { /* should downclock */
 827                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
 828                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 829                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 830                                    rdev->pm.dynpm_can_downclock) {
 831                                 rdev->pm.dynpm_planned_action =
 832                                         DYNPM_ACTION_DOWNCLOCK;
 833                                 rdev->pm.dynpm_action_timeout = jiffies +
 834                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 835                         }
 836                 }
 837
 838                 /* Note, radeon_pm_set_clocks is called with static_switch set
 839                  * to false since we want to wait for vbl to avoid flicker.
 840                  */
 841                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
 842                     jiffies > rdev->pm.dynpm_action_timeout) {
 843                         radeon_pm_get_dynpm_state(rdev);
 844                         radeon_pm_set_clocks(rdev);
 845                 }
 846
 847                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 848                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 849         }
 850         mutex_unlock(&rdev->pm.mutex);
 851         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 852 }
 853
 854 /*
 855  * Debugfs info
 856  */
 857 #if defined(CONFIG_DEBUG_FS)
 858
 859 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 860 {
 861         struct drm_info_node *node = (struct drm_info_node *) m->private;
 862         struct drm_device *dev = node->minor->dev;
 863         struct radeon_device *rdev = dev->dev_private;
 864
 865         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
 866         /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
 867         if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
 868                 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
 869         else
 870                 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 871         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
 872         if (rdev->asic->get_memory_clock)
 873                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 874         if (rdev->pm.current_vddc)
 875                 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
 876         if (rdev->asic->get_pcie_lanes)
 877                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 878
 879         return 0;
 880 }
 881
 882 static struct drm_info_list radeon_pm_info_list[] = {
 883         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 884 };
 885 #endif
 886
 887 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 888 {
 889 #if defined(CONFIG_DEBUG_FS)
 890         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 891 #else
 892         return 0;
 893 #endif
 894 }