drivers/gpu/drm/radeon/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 static void radeon_overscan_setup(struct drm_crtc *crtc,
  34                                   struct drm_display_mode *mode)
  35 {
  36         struct drm_device *dev = crtc->dev;
  37         struct radeon_device *rdev = dev->dev_private;
  38         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  39
  40         WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
  41         WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
  42         WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
  43 }
  44
  45 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
  46                                        struct drm_display_mode *mode)
  47 {
  48         struct drm_device *dev = crtc->dev;
  49         struct radeon_device *rdev = dev->dev_private;
  50         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  51         int xres = mode->hdisplay;
  52         int yres = mode->vdisplay;
  53         bool hscale = true, vscale = true;
  54         int hsync_wid;
  55         int vsync_wid;
  56         int hsync_start;
  57         int blank_width;
  58         u32 scale, inc, crtc_more_cntl;
  59         u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
  60         u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
  61         u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
  62         struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
  63
  64         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
  65                 (RADEON_VERT_STRETCH_RESERVED |
  66                  RADEON_VERT_AUTO_RATIO_INC);
  67         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
  68                 (RADEON_HORZ_FP_LOOP_STRETCH |
  69                  RADEON_HORZ_AUTO_RATIO_INC);
  70
  71         crtc_more_cntl = 0;
  72         if ((rdev->family == CHIP_RS100) ||
  73             (rdev->family == CHIP_RS200)) {
  74                 /* This is to workaround the asic bug for RMX, some versions
  75                    of BIOS dosen't have this register initialized correctly. */
  76                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  77         }
  78
  79
  80         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  81                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  82
  83         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  84         if (!hsync_wid)
  85                 hsync_wid = 1;
  86         hsync_start = mode->crtc_hsync_start - 8;
  87
  88         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  89                               | ((hsync_wid & 0x3f) << 16)
  90                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  91                                  ? RADEON_CRTC_H_SYNC_POL
  92                                  : 0));
  93
  94         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  95                                 | ((mode->crtc_vdisplay - 1) << 16));
  96
  97         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  98         if (!vsync_wid)
  99                 vsync_wid = 1;
 100
 101         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 102                               | ((vsync_wid & 0x1f) << 16)
 103                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 104                                  ? RADEON_CRTC_V_SYNC_POL
 105                                  : 0));
 106
 107         fp_horz_vert_active = 0;
 108
 109         if (native_mode->hdisplay == 0 ||
 110             native_mode->vdisplay == 0) {
 111                 hscale = false;
 112                 vscale = false;
 113         } else {
 114                 if (xres > native_mode->hdisplay)
 115                         xres = native_mode->hdisplay;
 116                 if (yres > native_mode->vdisplay)
 117                         yres = native_mode->vdisplay;
 118
 119                 if (xres == native_mode->hdisplay)
 120                         hscale = false;
 121                 if (yres == native_mode->vdisplay)
 122                         vscale = false;
 123         }
 124
 125         switch (radeon_crtc->rmx_type) {
 126         case RMX_FULL:
 127         case RMX_ASPECT:
 128                 if (!hscale)
 129                         fp_horz_stretch |= ((xres/8-1) << 16);
 130                 else {
 131                         inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 132                         scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 133                                 / native_mode->hdisplay + 1;
 134                         fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 135                                         RADEON_HORZ_STRETCH_BLEND |
 136                                         RADEON_HORZ_STRETCH_ENABLE |
 137                                         ((native_mode->hdisplay/8-1) << 16));
 138                 }
 139
 140                 if (!vscale)
 141                         fp_vert_stretch |= ((yres-1) << 12);
 142                 else {
 143                         inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 144                         scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 145                                 / native_mode->vdisplay + 1;
 146                         fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 147                                         RADEON_VERT_STRETCH_ENABLE |
 148                                         RADEON_VERT_STRETCH_BLEND |
 149                                         ((native_mode->vdisplay-1) << 12));
 150                 }
 151                 break;
 152         case RMX_CENTER:
 153                 fp_horz_stretch |= ((xres/8-1) << 16);
 154                 fp_vert_stretch |= ((yres-1) << 12);
 155
 156                 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 157                                 RADEON_CRTC_AUTO_VERT_CENTER_EN);
 158
 159                 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 160                 if (blank_width > 110)
 161                         blank_width = 110;
 162
 163                 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 164                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 165
 166                 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 167                 if (!hsync_wid)
 168                         hsync_wid = 1;
 169
 170                 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 171                                 | ((hsync_wid & 0x3f) << 16)
 172                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 173                                         ? RADEON_CRTC_H_SYNC_POL
 174                                         : 0));
 175
 176                 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 177                                 | ((mode->crtc_vdisplay - 1) << 16));
 178
 179                 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 180                 if (!vsync_wid)
 181                         vsync_wid = 1;
 182
 183                 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 184                                         | ((vsync_wid & 0x1f) << 16)
 185                                         | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 186                                                 ? RADEON_CRTC_V_SYNC_POL
 187                                                 : 0)));
 188
 189                 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
 190                                 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
 191                 break;
 192         case RMX_OFF:
 193         default:
 194                 fp_horz_stretch |= ((xres/8-1) << 16);
 195                 fp_vert_stretch |= ((yres-1) << 12);
 196                 break;
 197         }
 198
 199         WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 200         WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 201         WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 202         WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 203         WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 204         WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 205         WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 206         WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 207 }
 208
 209 void radeon_restore_common_regs(struct drm_device *dev)
 210 {
 211         /* don't need this yet */
 212 }
 213
 214 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
 215 {
 216         struct radeon_device *rdev = dev->dev_private;
 217         int i = 0;
 218
 219         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 220            the cause yet, but this workaround will mask the problem for now.
 221            Other chips usually will pass at the very first test, so the
 222            workaround shouldn't have any effect on them. */
 223         for (i = 0;
 224              (i < 10000 &&
 225               RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 226              i++);
 227 }
 228
 229 static void radeon_pll_write_update(struct drm_device *dev)
 230 {
 231         struct radeon_device *rdev = dev->dev_private;
 232
 233         while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 234
 235         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 236                            RADEON_PPLL_ATOMIC_UPDATE_W,
 237                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
 238 }
 239
 240 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
 241 {
 242         struct radeon_device *rdev = dev->dev_private;
 243         int i = 0;
 244
 245
 246         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 247            the cause yet, but this workaround will mask the problem for now.
 248            Other chips usually will pass at the very first test, so the
 249            workaround shouldn't have any effect on them. */
 250         for (i = 0;
 251              (i < 10000 &&
 252               RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 253              i++);
 254 }
 255
 256 static void radeon_pll2_write_update(struct drm_device *dev)
 257 {
 258         struct radeon_device *rdev = dev->dev_private;
 259
 260         while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 261
 262         WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 263                            RADEON_P2PLL_ATOMIC_UPDATE_W,
 264                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
 265 }
 266
 267 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
 268                                        uint16_t fb_div)
 269 {
 270         unsigned int vcoFreq;
 271
 272         if (!ref_div)
 273                 return 1;
 274
 275         vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
 276
 277         /*
 278          * This is horribly crude: the VCO frequency range is divided into
 279          * 3 parts, each part having a fixed PLL gain value.
 280          */
 281         if (vcoFreq >= 30000)
 282                 /*
 283                  * [300..max] MHz : 7
 284                  */
 285                 return 7;
 286         else if (vcoFreq >= 18000)
 287                 /*
 288                  * [180..300) MHz : 4
 289                  */
 290                 return 4;
 291         else
 292                 /*
 293                  * [0..180) MHz : 1
 294                  */
 295                 return 1;
 296 }
 297
 298 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 299 {
 300         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 301         struct drm_device *dev = crtc->dev;
 302         struct radeon_device *rdev = dev->dev_private;
 303         uint32_t mask;
 304
 305         if (radeon_crtc->crtc_id)
 306                 mask = (RADEON_CRTC2_DISP_DIS |
 307                         RADEON_CRTC2_VSYNC_DIS |
 308                         RADEON_CRTC2_HSYNC_DIS |
 309                         RADEON_CRTC2_DISP_REQ_EN_B);
 310         else
 311                 mask = (RADEON_CRTC_DISPLAY_DIS |
 312                         RADEON_CRTC_VSYNC_DIS |
 313                         RADEON_CRTC_HSYNC_DIS);
 314
 315         switch (mode) {
 316         case DRM_MODE_DPMS_ON:
 317                 radeon_crtc->enabled = true;
 318                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 319                 radeon_pm_compute_clocks(rdev);
 320                 if (radeon_crtc->crtc_id)
 321                         WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
 322                 else {
 323                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
 324                                                                          RADEON_CRTC_DISP_REQ_EN_B));
 325                         WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
 326                 }
 327                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 328                 radeon_crtc_load_lut(crtc);
 329                 break;
 330         case DRM_MODE_DPMS_STANDBY:
 331         case DRM_MODE_DPMS_SUSPEND:
 332         case DRM_MODE_DPMS_OFF:
 333                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 334                 if (radeon_crtc->crtc_id)
 335                         WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
 336                 else {
 337                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
 338                                                                                     RADEON_CRTC_DISP_REQ_EN_B));
 339                         WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
 340                 }
 341                 radeon_crtc->enabled = false;
 342                 /* adjust pm to dpms changes AFTER disabling crtcs */
 343                 radeon_pm_compute_clocks(rdev);
 344                 break;
 345         }
 346 }
 347
 348 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 349                          struct drm_framebuffer *old_fb)
 350 {
 351         return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
 352 }
 353
 354 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
 355                                 struct drm_framebuffer *fb,
 356                                 int x, int y, enum mode_set_atomic state)
 357 {
 358         return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
 359 }
 360
 361 int radeon_crtc_do_set_base(struct drm_crtc *crtc,
 362                          struct drm_framebuffer *fb,
 363                          int x, int y, int atomic)
 364 {
 365         struct drm_device *dev = crtc->dev;
 366         struct radeon_device *rdev = dev->dev_private;
 367         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 368         struct radeon_framebuffer *radeon_fb;
 369         struct drm_framebuffer *target_fb;
 370         struct drm_gem_object *obj;
 371         struct radeon_bo *rbo;
 372         uint64_t base;
 373         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 374         uint32_t crtc_pitch, pitch_pixels;
 375         uint32_t tiling_flags;
 376         int format;
 377         uint32_t gen_cntl_reg, gen_cntl_val;
 378         int r;
 379
 380         DRM_DEBUG_KMS("\n");
 381         /* no fb bound */
 382         if (!atomic && !crtc->fb) {
 383                 DRM_DEBUG_KMS("No FB bound\n");
 384                 return 0;
 385         }
 386
 387         if (atomic) {
 388                 radeon_fb = to_radeon_framebuffer(fb);
 389                 target_fb = fb;
 390         }
 391         else {
 392                 radeon_fb = to_radeon_framebuffer(crtc->fb);
 393                 target_fb = crtc->fb;
 394         }
 395
 396         switch (target_fb->bits_per_pixel) {
 397         case 8:
 398                 format = 2;
 399                 break;
 400         case 15:      /*  555 */
 401                 format = 3;
 402                 break;
 403         case 16:      /*  565 */
 404                 format = 4;
 405                 break;
 406         case 24:      /*  RGB */
 407                 format = 5;
 408                 break;
 409         case 32:      /* xRGB */
 410                 format = 6;
 411                 break;
 412         default:
 413                 return false;
 414         }
 415
 416         /* Pin framebuffer & get tilling informations */
 417         obj = radeon_fb->obj;
 418         rbo = gem_to_radeon_bo(obj);
 419         r = radeon_bo_reserve(rbo, false);
 420         if (unlikely(r != 0))
 421                 return r;
 422         /* Only 27 bit offset for legacy CRTC */
 423         r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
 424                                      &base);
 425         if (unlikely(r != 0)) {
 426                 radeon_bo_unreserve(rbo);
 427                 return -EINVAL;
 428         }
 429         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 430         radeon_bo_unreserve(rbo);
 431         if (tiling_flags & RADEON_TILING_MICRO)
 432                 DRM_ERROR("trying to scanout microtiled buffer\n");
 433
 434         /* if scanout was in GTT this really wouldn't work */
 435         /* crtc offset is from display base addr not FB location */
 436         radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
 437
 438         base -= radeon_crtc->legacy_display_base_addr;
 439
 440         crtc_offset_cntl = 0;
 441
 442         pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
 443         crtc_pitch  = (((pitch_pixels * target_fb->bits_per_pixel) +
 444                         ((target_fb->bits_per_pixel * 8) - 1)) /
 445                        (target_fb->bits_per_pixel * 8));
 446         crtc_pitch |= crtc_pitch << 16;
 447
 448         crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
 449         if (tiling_flags & RADEON_TILING_MACRO) {
 450                 if (ASIC_IS_R300(rdev))
 451                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 452                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 453                                              R300_CRTC_MACRO_TILE_EN);
 454                 else
 455                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 456         } else {
 457                 if (ASIC_IS_R300(rdev))
 458                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 459                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 460                                               R300_CRTC_MACRO_TILE_EN);
 461                 else
 462                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 463         }
 464
 465         if (tiling_flags & RADEON_TILING_MACRO) {
 466                 if (ASIC_IS_R300(rdev)) {
 467                         crtc_tile_x0_y0 = x | (y << 16);
 468                         base &= ~0x7ff;
 469                 } else {
 470                         int byteshift = target_fb->bits_per_pixel >> 4;
 471                         int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
 472                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 473                         crtc_offset_cntl |= (y % 16);
 474                 }
 475         } else {
 476                 int offset = y * pitch_pixels + x;
 477                 switch (target_fb->bits_per_pixel) {
 478                 case 8:
 479                         offset *= 1;
 480                         break;
 481                 case 15:
 482                 case 16:
 483                         offset *= 2;
 484                         break;
 485                 case 24:
 486                         offset *= 3;
 487                         break;
 488                 case 32:
 489                         offset *= 4;
 490                         break;
 491                 default:
 492                         return false;
 493                 }
 494                 base += offset;
 495         }
 496
 497         base &= ~7;
 498
 499         if (radeon_crtc->crtc_id == 1)
 500                 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
 501         else
 502                 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 503
 504         gen_cntl_val = RREG32(gen_cntl_reg);
 505         gen_cntl_val &= ~(0xf << 8);
 506         gen_cntl_val |= (format << 8);
 507         gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
 508         WREG32(gen_cntl_reg, gen_cntl_val);
 509
 510         crtc_offset = (u32)base;
 511
 512         WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 513
 514         if (ASIC_IS_R300(rdev)) {
 515                 if (radeon_crtc->crtc_id)
 516                         WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
 517                 else
 518                         WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 519         }
 520         WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
 521         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
 522         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 523
 524         if (!atomic && fb && fb != crtc->fb) {
 525                 radeon_fb = to_radeon_framebuffer(fb);
 526                 rbo = gem_to_radeon_bo(radeon_fb->obj);
 527                 r = radeon_bo_reserve(rbo, false);
 528                 if (unlikely(r != 0))
 529                         return r;
 530                 radeon_bo_unpin(rbo);
 531                 radeon_bo_unreserve(rbo);
 532         }
 533
 534         /* Bytes per pixel may have changed */
 535         radeon_bandwidth_update(rdev);
 536
 537         return 0;
 538 }
 539
 540 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 541 {
 542         struct drm_device *dev = crtc->dev;
 543         struct radeon_device *rdev = dev->dev_private;
 544         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 545         struct drm_encoder *encoder;
 546         int format;
 547         int hsync_start;
 548         int hsync_wid;
 549         int vsync_wid;
 550         uint32_t crtc_h_total_disp;
 551         uint32_t crtc_h_sync_strt_wid;
 552         uint32_t crtc_v_total_disp;
 553         uint32_t crtc_v_sync_strt_wid;
 554         bool is_tv = false;
 555
 556         DRM_DEBUG_KMS("\n");
 557         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 558                 if (encoder->crtc == crtc) {
 559                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 560                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 561                                 is_tv = true;
 562                                 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
 563                                 break;
 564                         }
 565                 }
 566         }
 567
 568         switch (crtc->fb->bits_per_pixel) {
 569         case 8:
 570                 format = 2;
 571                 break;
 572         case 15:      /*  555 */
 573                 format = 3;
 574                 break;
 575         case 16:      /*  565 */
 576                 format = 4;
 577                 break;
 578         case 24:      /*  RGB */
 579                 format = 5;
 580                 break;
 581         case 32:      /* xRGB */
 582                 format = 6;
 583                 break;
 584         default:
 585                 return false;
 586         }
 587
 588         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 589                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 590
 591         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 592         if (!hsync_wid)
 593                 hsync_wid = 1;
 594         hsync_start = mode->crtc_hsync_start - 8;
 595
 596         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 597                                 | ((hsync_wid & 0x3f) << 16)
 598                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 599                                    ? RADEON_CRTC_H_SYNC_POL
 600                                    : 0));
 601
 602         /* This works for double scan mode. */
 603         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 604                              | ((mode->crtc_vdisplay - 1) << 16));
 605
 606         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 607         if (!vsync_wid)
 608                 vsync_wid = 1;
 609
 610         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 611                                 | ((vsync_wid & 0x1f) << 16)
 612                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 613                                    ? RADEON_CRTC_V_SYNC_POL
 614                                    : 0));
 615
 616         if (radeon_crtc->crtc_id) {
 617                 uint32_t crtc2_gen_cntl;
 618                 uint32_t disp2_merge_cntl;
 619
 620                 /* if TV DAC is enabled for another crtc and keep it enabled */
 621                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
 622                 crtc2_gen_cntl |= ((format << 8)
 623                                    | RADEON_CRTC2_VSYNC_DIS
 624                                    | RADEON_CRTC2_HSYNC_DIS
 625                                    | RADEON_CRTC2_DISP_DIS
 626                                    | RADEON_CRTC2_DISP_REQ_EN_B
 627                                    | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 628                                       ? RADEON_CRTC2_DBL_SCAN_EN
 629                                       : 0)
 630                                    | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 631                                       ? RADEON_CRTC2_CSYNC_EN
 632                                       : 0)
 633                                    | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 634                                       ? RADEON_CRTC2_INTERLACE_EN
 635                                       : 0));
 636
 637                 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
 638                 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
 639                         crtc2_gen_cntl |= RADEON_CRTC2_EN;
 640
 641                 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 642                 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 643
 644                 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
 645                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 646
 647                 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 648                 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 649         } else {
 650                 uint32_t crtc_gen_cntl;
 651                 uint32_t crtc_ext_cntl;
 652                 uint32_t disp_merge_cntl;
 653
 654                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
 655                 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
 656                                  | (format << 8)
 657                                  | RADEON_CRTC_DISP_REQ_EN_B
 658                                  | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 659                                     ? RADEON_CRTC_DBL_SCAN_EN
 660                                     : 0)
 661                                  | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 662                                     ? RADEON_CRTC_CSYNC_EN
 663                                     : 0)
 664                                  | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 665                                     ? RADEON_CRTC_INTERLACE_EN
 666                                     : 0));
 667
 668                 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
 669                 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
 670                         crtc_gen_cntl |= RADEON_CRTC_EN;
 671
 672                 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 673                 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 674                                   RADEON_CRTC_VSYNC_DIS |
 675                                   RADEON_CRTC_HSYNC_DIS |
 676                                   RADEON_CRTC_DISPLAY_DIS);
 677
 678                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 679                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 680
 681                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 682                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 683                 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 684         }
 685
 686         if (is_tv)
 687                 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
 688                                                  &crtc_h_sync_strt_wid, &crtc_v_total_disp,
 689                                                  &crtc_v_sync_strt_wid);
 690
 691         WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
 692         WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
 693         WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
 694         WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 695
 696         return true;
 697 }
 698
 699 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 700 {
 701         struct drm_device *dev = crtc->dev;
 702         struct radeon_device *rdev = dev->dev_private;
 703         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 704         struct drm_encoder *encoder;
 705         uint32_t feedback_div = 0;
 706         uint32_t frac_fb_div = 0;
 707         uint32_t reference_div = 0;
 708         uint32_t post_divider = 0;
 709         uint32_t freq = 0;
 710         uint8_t pll_gain;
 711         bool use_bios_divs = false;
 712         /* PLL registers */
 713         uint32_t pll_ref_div = 0;
 714         uint32_t pll_fb_post_div = 0;
 715         uint32_t htotal_cntl = 0;
 716         bool is_tv = false;
 717         struct radeon_pll *pll;
 718
 719         struct {
 720                 int divider;
 721                 int bitvalue;
 722         } *post_div, post_divs[]   = {
 723                 /* From RAGE 128 VR/RAGE 128 GL Register
 724                  * Reference Manual (Technical Reference
 725                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 726                  * 3-17 (PLL_DIV_[3:0]).
 727                  */
 728                 {  1, 0 },              /* VCLK_SRC                 */
 729                 {  2, 1 },              /* VCLK_SRC/2               */
 730                 {  4, 2 },              /* VCLK_SRC/4               */
 731                 {  8, 3 },              /* VCLK_SRC/8               */
 732                 {  3, 4 },              /* VCLK_SRC/3               */
 733                 { 16, 5 },              /* VCLK_SRC/16              */
 734                 {  6, 6 },              /* VCLK_SRC/6               */
 735                 { 12, 7 },              /* VCLK_SRC/12              */
 736                 {  0, 0 }
 737         };
 738
 739         if (radeon_crtc->crtc_id)
 740                 pll = &rdev->clock.p2pll;
 741         else
 742                 pll = &rdev->clock.p1pll;
 743
 744         pll->flags = RADEON_PLL_LEGACY;
 745
 746         if (mode->clock > 200000) /* range limits??? */
 747                 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 748         else
 749                 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 750
 751         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 752                 if (encoder->crtc == crtc) {
 753                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 754
 755                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 756                                 is_tv = true;
 757                                 break;
 758                         }
 759
 760                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 761                                 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 762                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 763                                 if (!rdev->is_atom_bios) {
 764                                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 765                                         struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 766                                         if (lvds) {
 767                                                 if (lvds->use_bios_dividers) {
 768                                                         pll_ref_div = lvds->panel_ref_divider;
 769                                                         pll_fb_post_div   = (lvds->panel_fb_divider |
 770                                                                              (lvds->panel_post_divider << 16));
 771                                                         htotal_cntl  = 0;
 772                                                         use_bios_divs = true;
 773                                                 }
 774                                         }
 775                                 }
 776                                 pll->flags |= RADEON_PLL_USE_REF_DIV;
 777                         }
 778                 }
 779         }
 780
 781         DRM_DEBUG_KMS("\n");
 782
 783         if (!use_bios_divs) {
 784                 radeon_compute_pll_legacy(pll, mode->clock,
 785                                           &freq, &feedback_div, &frac_fb_div,
 786                                           &reference_div, &post_divider);
 787
 788                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 789                         if (post_div->divider == post_divider)
 790                                 break;
 791                 }
 792
 793                 if (!post_div->divider)
 794                         post_div = &post_divs[0];
 795
 796                 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
 797                           (unsigned)freq,
 798                           feedback_div,
 799                           reference_div,
 800                           post_divider);
 801
 802                 pll_ref_div   = reference_div;
 803 #if defined(__powerpc__) && (0) /* TODO */
 804                 /* apparently programming this otherwise causes a hang??? */
 805                 if (info->MacModel == RADEON_MAC_IBOOK)
 806                         pll_fb_post_div = 0x000600ad;
 807                 else
 808 #endif
 809                         pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 810
 811                 htotal_cntl    = mode->htotal & 0x7;
 812
 813         }
 814
 815         pll_gain = radeon_compute_pll_gain(pll->reference_freq,
 816                                            pll_ref_div & 0x3ff,
 817                                            pll_fb_post_div & 0x7ff);
 818
 819         if (radeon_crtc->crtc_id) {
 820                 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
 821                                           ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 822                                          RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 823
 824                 if (is_tv) {
 825                         radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
 826                                                      &pll_ref_div, &pll_fb_post_div,
 827                                                      &pixclks_cntl);
 828                 }
 829
 830                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 831                              RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 832                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 833
 834                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 835                              RADEON_P2PLL_RESET
 836                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 837                              | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 838                              ~(RADEON_P2PLL_RESET
 839                                | RADEON_P2PLL_ATOMIC_UPDATE_EN
 840                                | RADEON_P2PLL_PVG_MASK));
 841
 842                 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 843                              pll_ref_div,
 844                              ~RADEON_P2PLL_REF_DIV_MASK);
 845
 846                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 847                              pll_fb_post_div,
 848                              ~RADEON_P2PLL_FB0_DIV_MASK);
 849
 850                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 851                              pll_fb_post_div,
 852                              ~RADEON_P2PLL_POST0_DIV_MASK);
 853
 854                 radeon_pll2_write_update(dev);
 855                 radeon_pll2_wait_for_read_update_complete(dev);
 856
 857                 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 858
 859                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 860                              0,
 861                              ~(RADEON_P2PLL_RESET
 862                                | RADEON_P2PLL_SLEEP
 863                                | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 864
 865                 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 866                           (unsigned)pll_ref_div,
 867                           (unsigned)pll_fb_post_div,
 868                           (unsigned)htotal_cntl,
 869                           RREG32_PLL(RADEON_P2PLL_CNTL));
 870                 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
 871                           (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 872                           (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
 873                           (unsigned)((pll_fb_post_div &
 874                                       RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 875
 876                 mdelay(50); /* Let the clock to lock */
 877
 878                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 879                              RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 880                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 881
 882                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 883         } else {
 884                 uint32_t pixclks_cntl;
 885
 886
 887                 if (is_tv) {
 888                         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 889                         radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
 890                                                      &pll_fb_post_div, &pixclks_cntl);
 891                 }
 892
 893                 if (rdev->flags & RADEON_IS_MOBILITY) {
 894                         /* A temporal workaround for the occasional blanking on certain laptop panels.
 895                            This appears to related to the PLL divider registers (fail to lock?).
 896                            It occurs even when all dividers are the same with their old settings.
 897                            In this case we really don't need to fiddle with PLL registers.
 898                            By doing this we can avoid the blanking problem with some panels.
 899                         */
 900                         if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 901                             (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
 902                                                  (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 903                                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 904                                          RADEON_PLL_DIV_SEL,
 905                                          ~(RADEON_PLL_DIV_SEL));
 906                                 r100_pll_errata_after_index(rdev);
 907                                 return;
 908                         }
 909                 }
 910
 911                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 912                              RADEON_VCLK_SRC_SEL_CPUCLK,
 913                              ~(RADEON_VCLK_SRC_SEL_MASK));
 914                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 915                              RADEON_PPLL_RESET
 916                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 917                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 918                              | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 919                              ~(RADEON_PPLL_RESET
 920                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 921                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 922                                | RADEON_PPLL_PVG_MASK));
 923
 924                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 925                          RADEON_PLL_DIV_SEL,
 926                          ~(RADEON_PLL_DIV_SEL));
 927                 r100_pll_errata_after_index(rdev);
 928
 929                 if (ASIC_IS_R300(rdev) ||
 930                     (rdev->family == CHIP_RS300) ||
 931                     (rdev->family == CHIP_RS400) ||
 932                     (rdev->family == CHIP_RS480)) {
 933                         if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 934                                 /* When restoring console mode, use saved PPLL_REF_DIV
 935                                  * setting.
 936                                  */
 937                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 938                                              pll_ref_div,
 939                                              0);
 940                         } else {
 941                                 /* R300 uses ref_div_acc field as real ref divider */
 942                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 943                                              (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 944                                              ~R300_PPLL_REF_DIV_ACC_MASK);
 945                         }
 946                 } else
 947                         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 948                                      pll_ref_div,
 949                                      ~RADEON_PPLL_REF_DIV_MASK);
 950
 951                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 952                              pll_fb_post_div,
 953                              ~RADEON_PPLL_FB3_DIV_MASK);
 954
 955                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 956                              pll_fb_post_div,
 957                              ~RADEON_PPLL_POST3_DIV_MASK);
 958
 959                 radeon_pll_write_update(dev);
 960                 radeon_pll_wait_for_read_update_complete(dev);
 961
 962                 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
 963
 964                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 965                              0,
 966                              ~(RADEON_PPLL_RESET
 967                                | RADEON_PPLL_SLEEP
 968                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 969                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 970
 971                 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 972                           pll_ref_div,
 973                           pll_fb_post_div,
 974                           (unsigned)htotal_cntl,
 975                           RREG32_PLL(RADEON_PPLL_CNTL));
 976                 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
 977                           pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 978                           pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
 979                           (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
 980
 981                 mdelay(50); /* Let the clock to lock */
 982
 983                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 984                              RADEON_VCLK_SRC_SEL_PPLLCLK,
 985                              ~(RADEON_VCLK_SRC_SEL_MASK));
 986
 987                 if (is_tv)
 988                         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 989         }
 990 }
 991
 992 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
 993                                    const struct drm_display_mode *mode,
 994                                    struct drm_display_mode *adjusted_mode)
 995 {
 996         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
 997                 return false;
 998         return true;
 999 }
1000
1001 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1002                                  struct drm_display_mode *mode,
1003                                  struct drm_display_mode *adjusted_mode,
1004                                  int x, int y, struct drm_framebuffer *old_fb)
1005 {
1006         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1007
1008         /* TODO TV */
1009         radeon_crtc_set_base(crtc, x, y, old_fb);
1010         radeon_set_crtc_timing(crtc, adjusted_mode);
1011         radeon_set_pll(crtc, adjusted_mode);
1012         radeon_overscan_setup(crtc, adjusted_mode);
1013         if (radeon_crtc->crtc_id == 0) {
1014                 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1015         } else {
1016                 if (radeon_crtc->rmx_type != RMX_OFF) {
1017                         /* FIXME: only first crtc has rmx what should we
1018                          * do ?
1019                          */
1020                         DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1021                 }
1022         }
1023         return 0;
1024 }
1025
1026 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1027 {
1028         struct drm_device *dev = crtc->dev;
1029         struct drm_crtc *crtci;
1030
1031         /*
1032         * The hardware wedges sometimes if you reconfigure one CRTC
1033         * whilst another is running (see fdo bug #24611).
1034         */
1035         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1036                 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1037 }
1038
1039 static void radeon_crtc_commit(struct drm_crtc *crtc)
1040 {
1041         struct drm_device *dev = crtc->dev;
1042         struct drm_crtc *crtci;
1043
1044         /*
1045         * Reenable the CRTCs that should be running.
1046         */
1047         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1048                 if (crtci->enabled)
1049                         radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1050         }
1051 }
1052
1053 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1054         .dpms = radeon_crtc_dpms,
1055         .mode_fixup = radeon_crtc_mode_fixup,
1056         .mode_set = radeon_crtc_mode_set,
1057         .mode_set_base = radeon_crtc_set_base,
1058         .mode_set_base_atomic = radeon_crtc_set_base_atomic,
1059         .prepare = radeon_crtc_prepare,
1060         .commit = radeon_crtc_commit,
1061         .load_lut = radeon_crtc_load_lut,
1062 };
1063
1064
1065 void radeon_legacy_init_crtc(struct drm_device *dev,
1066                                struct radeon_crtc *radeon_crtc)
1067 {
1068         if (radeon_crtc->crtc_id == 1)
1069                 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1070         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1071 }