drivers/gpu/drm/radeon/radeon_i2c.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29 #include "atom.h"
  30
  31 /**
  32  * radeon_ddc_probe
  33  *
  34  */
  35 bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
  36 {
  37         u8 out = 0x0;
  38         u8 buf[8];
  39         int ret;
  40         struct i2c_msg msgs[] = {
  41                 {
  42                         .addr = 0x50,
  43                         .flags = 0,
  44                         .len = 1,
  45                         .buf = &out,
  46                 },
  47                 {
  48                         .addr = 0x50,
  49                         .flags = I2C_M_RD,
  50                         .len = 8,
  51                         .buf = buf,
  52                 }
  53         };
  54
  55         /* on hw with routers, select right port */
  56         if (radeon_connector->router.ddc_valid)
  57                 radeon_router_select_ddc_port(radeon_connector);
  58
  59         ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
  60         if (ret != 2)
  61                 /* Couldn't find an accessible DDC on this connector */
  62                 return false;
  63         /* Probe also for valid EDID header
  64          * EDID header starts with:
  65          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
  66          * Only the first 6 bytes must be valid as
  67          * drm_edid_block_valid() can fix the last 2 bytes */
  68         if (drm_edid_header_is_valid(buf) < 6) {
  69                 /* Couldn't find an accessible EDID on this
  70                  * connector */
  71                 return false;
  72         }
  73         return true;
  74 }
  75
  76 /* bit banging i2c */
  77
  78 static int pre_xfer(struct i2c_adapter *i2c_adap)
  79 {
  80         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
  81         struct radeon_device *rdev = i2c->dev->dev_private;
  82         struct radeon_i2c_bus_rec *rec = &i2c->rec;
  83         uint32_t temp;
  84
  85         /* RV410 appears to have a bug where the hw i2c in reset
  86          * holds the i2c port in a bad state - switch hw i2c away before
  87          * doing DDC - do this for all r200s/r300s/r400s for safety sake
  88          */
  89         if (rec->hw_capable) {
  90                 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
  91                         u32 reg;
  92
  93                         if (rdev->family >= CHIP_RV350)
  94                                 reg = RADEON_GPIO_MONID;
  95                         else if ((rdev->family == CHIP_R300) ||
  96                                  (rdev->family == CHIP_R350))
  97                                 reg = RADEON_GPIO_DVI_DDC;
  98                         else
  99                                 reg = RADEON_GPIO_CRT2_DDC;
 100
 101                         mutex_lock(&rdev->dc_hw_i2c_mutex);
 102                         if (rec->a_clk_reg == reg) {
 103                                 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
 104                                                                R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
 105                         } else {
 106                                 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
 107                                                                R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
 108                         }
 109                         mutex_unlock(&rdev->dc_hw_i2c_mutex);
 110                 }
 111         }
 112
 113         /* switch the pads to ddc mode */
 114         if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
 115                 temp = RREG32(rec->mask_clk_reg);
 116                 temp &= ~(1 << 16);
 117                 WREG32(rec->mask_clk_reg, temp);
 118         }
 119
 120         /* clear the output pin values */
 121         temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
 122         WREG32(rec->a_clk_reg, temp);
 123
 124         temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
 125         WREG32(rec->a_data_reg, temp);
 126
 127         /* set the pins to input */
 128         temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
 129         WREG32(rec->en_clk_reg, temp);
 130
 131         temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
 132         WREG32(rec->en_data_reg, temp);
 133
 134         /* mask the gpio pins for software use */
 135         temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
 136         WREG32(rec->mask_clk_reg, temp);
 137         temp = RREG32(rec->mask_clk_reg);
 138
 139         temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
 140         WREG32(rec->mask_data_reg, temp);
 141         temp = RREG32(rec->mask_data_reg);
 142
 143         return 0;
 144 }
 145
 146 static void post_xfer(struct i2c_adapter *i2c_adap)
 147 {
 148         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 149         struct radeon_device *rdev = i2c->dev->dev_private;
 150         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 151         uint32_t temp;
 152
 153         /* unmask the gpio pins for software use */
 154         temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
 155         WREG32(rec->mask_clk_reg, temp);
 156         temp = RREG32(rec->mask_clk_reg);
 157
 158         temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
 159         WREG32(rec->mask_data_reg, temp);
 160         temp = RREG32(rec->mask_data_reg);
 161 }
 162
 163 static int get_clock(void *i2c_priv)
 164 {
 165         struct radeon_i2c_chan *i2c = i2c_priv;
 166         struct radeon_device *rdev = i2c->dev->dev_private;
 167         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 168         uint32_t val;
 169
 170         /* read the value off the pin */
 171         val = RREG32(rec->y_clk_reg);
 172         val &= rec->y_clk_mask;
 173
 174         return (val != 0);
 175 }
 176
 177
 178 static int get_data(void *i2c_priv)
 179 {
 180         struct radeon_i2c_chan *i2c = i2c_priv;
 181         struct radeon_device *rdev = i2c->dev->dev_private;
 182         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 183         uint32_t val;
 184
 185         /* read the value off the pin */
 186         val = RREG32(rec->y_data_reg);
 187         val &= rec->y_data_mask;
 188
 189         return (val != 0);
 190 }
 191
 192 static void set_clock(void *i2c_priv, int clock)
 193 {
 194         struct radeon_i2c_chan *i2c = i2c_priv;
 195         struct radeon_device *rdev = i2c->dev->dev_private;
 196         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 197         uint32_t val;
 198
 199         /* set pin direction */
 200         val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
 201         val |= clock ? 0 : rec->en_clk_mask;
 202         WREG32(rec->en_clk_reg, val);
 203 }
 204
 205 static void set_data(void *i2c_priv, int data)
 206 {
 207         struct radeon_i2c_chan *i2c = i2c_priv;
 208         struct radeon_device *rdev = i2c->dev->dev_private;
 209         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 210         uint32_t val;
 211
 212         /* set pin direction */
 213         val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
 214         val |= data ? 0 : rec->en_data_mask;
 215         WREG32(rec->en_data_reg, val);
 216 }
 217
 218 /* hw i2c */
 219
 220 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
 221 {
 222         u32 sclk = rdev->pm.current_sclk;
 223         u32 prescale = 0;
 224         u32 nm;
 225         u8 n, m, loop;
 226         int i2c_clock;
 227
 228         switch (rdev->family) {
 229         case CHIP_R100:
 230         case CHIP_RV100:
 231         case CHIP_RS100:
 232         case CHIP_RV200:
 233         case CHIP_RS200:
 234         case CHIP_R200:
 235         case CHIP_RV250:
 236         case CHIP_RS300:
 237         case CHIP_RV280:
 238         case CHIP_R300:
 239         case CHIP_R350:
 240         case CHIP_RV350:
 241                 i2c_clock = 60;
 242                 nm = (sclk * 10) / (i2c_clock * 4);
 243                 for (loop = 1; loop < 255; loop++) {
 244                         if ((nm / loop) < loop)
 245                                 break;
 246                 }
 247                 n = loop - 1;
 248                 m = loop - 2;
 249                 prescale = m | (n << 8);
 250                 break;
 251         case CHIP_RV380:
 252         case CHIP_RS400:
 253         case CHIP_RS480:
 254         case CHIP_R420:
 255         case CHIP_R423:
 256         case CHIP_RV410:
 257                 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
 258                 break;
 259         case CHIP_RS600:
 260         case CHIP_RS690:
 261         case CHIP_RS740:
 262                 /* todo */
 263                 break;
 264         case CHIP_RV515:
 265         case CHIP_R520:
 266         case CHIP_RV530:
 267         case CHIP_RV560:
 268         case CHIP_RV570:
 269         case CHIP_R580:
 270                 i2c_clock = 50;
 271                 if (rdev->family == CHIP_R520)
 272                         prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
 273                 else
 274                         prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
 275                 break;
 276         case CHIP_R600:
 277         case CHIP_RV610:
 278         case CHIP_RV630:
 279         case CHIP_RV670:
 280                 /* todo */
 281                 break;
 282         case CHIP_RV620:
 283         case CHIP_RV635:
 284         case CHIP_RS780:
 285         case CHIP_RS880:
 286         case CHIP_RV770:
 287         case CHIP_RV730:
 288         case CHIP_RV710:
 289         case CHIP_RV740:
 290                 /* todo */
 291                 break;
 292         case CHIP_CEDAR:
 293         case CHIP_REDWOOD:
 294         case CHIP_JUNIPER:
 295         case CHIP_CYPRESS:
 296         case CHIP_HEMLOCK:
 297                 /* todo */
 298                 break;
 299         default:
 300                 DRM_ERROR("i2c: unhandled radeon chip\n");
 301                 break;
 302         }
 303         return prescale;
 304 }
 305
 306
 307 /* hw i2c engine for r1xx-4xx hardware
 308  * hw can buffer up to 15 bytes
 309  */
 310 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
 311                             struct i2c_msg *msgs, int num)
 312 {
 313         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 314         struct radeon_device *rdev = i2c->dev->dev_private;
 315         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 316         struct i2c_msg *p;
 317         int i, j, k, ret = num;
 318         u32 prescale;
 319         u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
 320         u32 tmp, reg;
 321
 322         mutex_lock(&rdev->dc_hw_i2c_mutex);
 323         /* take the pm lock since we need a constant sclk */
 324         mutex_lock(&rdev->pm.mutex);
 325
 326         prescale = radeon_get_i2c_prescale(rdev);
 327
 328         reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
 329                RADEON_I2C_DRIVE_EN |
 330                RADEON_I2C_START |
 331                RADEON_I2C_STOP |
 332                RADEON_I2C_GO);
 333
 334         if (rdev->is_atom_bios) {
 335                 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 336                 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
 337         }
 338
 339         if (rec->mm_i2c) {
 340                 i2c_cntl_0 = RADEON_I2C_CNTL_0;
 341                 i2c_cntl_1 = RADEON_I2C_CNTL_1;
 342                 i2c_data = RADEON_I2C_DATA;
 343         } else {
 344                 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
 345                 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
 346                 i2c_data = RADEON_DVI_I2C_DATA;
 347
 348                 switch (rdev->family) {
 349                 case CHIP_R100:
 350                 case CHIP_RV100:
 351                 case CHIP_RS100:
 352                 case CHIP_RV200:
 353                 case CHIP_RS200:
 354                 case CHIP_RS300:
 355                         switch (rec->mask_clk_reg) {
 356                         case RADEON_GPIO_DVI_DDC:
 357                                 /* no gpio select bit */
 358                                 break;
 359                         default:
 360                                 DRM_ERROR("gpio not supported with hw i2c\n");
 361                                 ret = -EINVAL;
 362                                 goto done;
 363                         }
 364                         break;
 365                 case CHIP_R200:
 366                         /* only bit 4 on r200 */
 367                         switch (rec->mask_clk_reg) {
 368                         case RADEON_GPIO_DVI_DDC:
 369                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 370                                 break;
 371                         case RADEON_GPIO_MONID:
 372                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 373                                 break;
 374                         default:
 375                                 DRM_ERROR("gpio not supported with hw i2c\n");
 376                                 ret = -EINVAL;
 377                                 goto done;
 378                         }
 379                         break;
 380                 case CHIP_RV250:
 381                 case CHIP_RV280:
 382                         /* bits 3 and 4 */
 383                         switch (rec->mask_clk_reg) {
 384                         case RADEON_GPIO_DVI_DDC:
 385                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 386                                 break;
 387                         case RADEON_GPIO_VGA_DDC:
 388                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
 389                                 break;
 390                         case RADEON_GPIO_CRT2_DDC:
 391                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 392                                 break;
 393                         default:
 394                                 DRM_ERROR("gpio not supported with hw i2c\n");
 395                                 ret = -EINVAL;
 396                                 goto done;
 397                         }
 398                         break;
 399                 case CHIP_R300:
 400                 case CHIP_R350:
 401                         /* only bit 4 on r300/r350 */
 402                         switch (rec->mask_clk_reg) {
 403                         case RADEON_GPIO_VGA_DDC:
 404                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 405                                 break;
 406                         case RADEON_GPIO_DVI_DDC:
 407                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 408                                 break;
 409                         default:
 410                                 DRM_ERROR("gpio not supported with hw i2c\n");
 411                                 ret = -EINVAL;
 412                                 goto done;
 413                         }
 414                         break;
 415                 case CHIP_RV350:
 416                 case CHIP_RV380:
 417                 case CHIP_R420:
 418                 case CHIP_R423:
 419                 case CHIP_RV410:
 420                 case CHIP_RS400:
 421                 case CHIP_RS480:
 422                         /* bits 3 and 4 */
 423                         switch (rec->mask_clk_reg) {
 424                         case RADEON_GPIO_VGA_DDC:
 425                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
 426                                 break;
 427                         case RADEON_GPIO_DVI_DDC:
 428                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
 429                                 break;
 430                         case RADEON_GPIO_MONID:
 431                                 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
 432                                 break;
 433                         default:
 434                                 DRM_ERROR("gpio not supported with hw i2c\n");
 435                                 ret = -EINVAL;
 436                                 goto done;
 437                         }
 438                         break;
 439                 default:
 440                         DRM_ERROR("unsupported asic\n");
 441                         ret = -EINVAL;
 442                         goto done;
 443                         break;
 444                 }
 445         }
 446
 447         /* check for bus probe */
 448         p = &msgs[0];
 449         if ((num == 1) && (p->len == 0)) {
 450                 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 451                                     RADEON_I2C_NACK |
 452                                     RADEON_I2C_HALT |
 453                                     RADEON_I2C_SOFT_RST));
 454                 WREG32(i2c_data, (p->addr << 1) & 0xff);
 455                 WREG32(i2c_data, 0);
 456                 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
 457                                     (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
 458                                     RADEON_I2C_EN |
 459                                     (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
 460                 WREG32(i2c_cntl_0, reg);
 461                 for (k = 0; k < 32; k++) {
 462                         udelay(10);
 463                         tmp = RREG32(i2c_cntl_0);
 464                         if (tmp & RADEON_I2C_GO)
 465                                 continue;
 466                         tmp = RREG32(i2c_cntl_0);
 467                         if (tmp & RADEON_I2C_DONE)
 468                                 break;
 469                         else {
 470                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 471                                 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
 472                                 ret = -EIO;
 473                                 goto done;
 474                         }
 475                 }
 476                 goto done;
 477         }
 478
 479         for (i = 0; i < num; i++) {
 480                 p = &msgs[i];
 481                 for (j = 0; j < p->len; j++) {
 482                         if (p->flags & I2C_M_RD) {
 483                                 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 484                                                     RADEON_I2C_NACK |
 485                                                     RADEON_I2C_HALT |
 486                                                     RADEON_I2C_SOFT_RST));
 487                                 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
 488                                 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
 489                                                     (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
 490                                                     RADEON_I2C_EN |
 491                                                     (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
 492                                 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
 493                                 for (k = 0; k < 32; k++) {
 494                                         udelay(10);
 495                                         tmp = RREG32(i2c_cntl_0);
 496                                         if (tmp & RADEON_I2C_GO)
 497                                                 continue;
 498                                         tmp = RREG32(i2c_cntl_0);
 499                                         if (tmp & RADEON_I2C_DONE)
 500                                                 break;
 501                                         else {
 502                                                 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
 503                                                 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
 504                                                 ret = -EIO;
 505                                                 goto done;
 506                                         }
 507                                 }
 508                                 p->buf[j] = RREG32(i2c_data) & 0xff;
 509                         } else {
 510                                 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 511                                                     RADEON_I2C_NACK |
 512                                                     RADEON_I2C_HALT |
 513                                                     RADEON_I2C_SOFT_RST));
 514                                 WREG32(i2c_data, (p->addr << 1) & 0xff);
 515                                 WREG32(i2c_data, p->buf[j]);
 516                                 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
 517                                                     (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
 518                                                     RADEON_I2C_EN |
 519                                                     (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
 520                                 WREG32(i2c_cntl_0, reg);
 521                                 for (k = 0; k < 32; k++) {
 522                                         udelay(10);
 523                                         tmp = RREG32(i2c_cntl_0);
 524                                         if (tmp & RADEON_I2C_GO)
 525                                                 continue;
 526                                         tmp = RREG32(i2c_cntl_0);
 527                                         if (tmp & RADEON_I2C_DONE)
 528                                                 break;
 529                                         else {
 530                                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 531                                                 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
 532                                                 ret = -EIO;
 533                                                 goto done;
 534                                         }
 535                                 }
 536                         }
 537                 }
 538         }
 539
 540 done:
 541         WREG32(i2c_cntl_0, 0);
 542         WREG32(i2c_cntl_1, 0);
 543         WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
 544                             RADEON_I2C_NACK |
 545                             RADEON_I2C_HALT |
 546                             RADEON_I2C_SOFT_RST));
 547
 548         if (rdev->is_atom_bios) {
 549                 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 550                 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
 551                 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
 552         }
 553
 554         mutex_unlock(&rdev->pm.mutex);
 555         mutex_unlock(&rdev->dc_hw_i2c_mutex);
 556
 557         return ret;
 558 }
 559
 560 /* hw i2c engine for r5xx hardware
 561  * hw can buffer up to 15 bytes
 562  */
 563 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
 564                             struct i2c_msg *msgs, int num)
 565 {
 566         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 567         struct radeon_device *rdev = i2c->dev->dev_private;
 568         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 569         struct i2c_msg *p;
 570         int i, j, remaining, current_count, buffer_offset, ret = num;
 571         u32 prescale;
 572         u32 tmp, reg;
 573         u32 saved1, saved2;
 574
 575         mutex_lock(&rdev->dc_hw_i2c_mutex);
 576         /* take the pm lock since we need a constant sclk */
 577         mutex_lock(&rdev->pm.mutex);
 578
 579         prescale = radeon_get_i2c_prescale(rdev);
 580
 581         /* clear gpio mask bits */
 582         tmp = RREG32(rec->mask_clk_reg);
 583         tmp &= ~rec->mask_clk_mask;
 584         WREG32(rec->mask_clk_reg, tmp);
 585         tmp = RREG32(rec->mask_clk_reg);
 586
 587         tmp = RREG32(rec->mask_data_reg);
 588         tmp &= ~rec->mask_data_mask;
 589         WREG32(rec->mask_data_reg, tmp);
 590         tmp = RREG32(rec->mask_data_reg);
 591
 592         /* clear pin values */
 593         tmp = RREG32(rec->a_clk_reg);
 594         tmp &= ~rec->a_clk_mask;
 595         WREG32(rec->a_clk_reg, tmp);
 596         tmp = RREG32(rec->a_clk_reg);
 597
 598         tmp = RREG32(rec->a_data_reg);
 599         tmp &= ~rec->a_data_mask;
 600         WREG32(rec->a_data_reg, tmp);
 601         tmp = RREG32(rec->a_data_reg);
 602
 603         /* set the pins to input */
 604         tmp = RREG32(rec->en_clk_reg);
 605         tmp &= ~rec->en_clk_mask;
 606         WREG32(rec->en_clk_reg, tmp);
 607         tmp = RREG32(rec->en_clk_reg);
 608
 609         tmp = RREG32(rec->en_data_reg);
 610         tmp &= ~rec->en_data_mask;
 611         WREG32(rec->en_data_reg, tmp);
 612         tmp = RREG32(rec->en_data_reg);
 613
 614         /* */
 615         tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 616         WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
 617         saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
 618         saved2 = RREG32(0x494);
 619         WREG32(0x494, saved2 | 0x1);
 620
 621         WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
 622         for (i = 0; i < 50; i++) {
 623                 udelay(1);
 624                 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
 625                         break;
 626         }
 627         if (i == 50) {
 628                 DRM_ERROR("failed to get i2c bus\n");
 629                 ret = -EBUSY;
 630                 goto done;
 631         }
 632
 633         reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
 634         switch (rec->mask_clk_reg) {
 635         case AVIVO_DC_GPIO_DDC1_MASK:
 636                 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
 637                 break;
 638         case AVIVO_DC_GPIO_DDC2_MASK:
 639                 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
 640                 break;
 641         case AVIVO_DC_GPIO_DDC3_MASK:
 642                 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
 643                 break;
 644         default:
 645                 DRM_ERROR("gpio not supported with hw i2c\n");
 646                 ret = -EINVAL;
 647                 goto done;
 648         }
 649
 650         /* check for bus probe */
 651         p = &msgs[0];
 652         if ((num == 1) && (p->len == 0)) {
 653                 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 654                                               AVIVO_DC_I2C_NACK |
 655                                               AVIVO_DC_I2C_HALT));
 656                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 657                 udelay(1);
 658                 WREG32(AVIVO_DC_I2C_RESET, 0);
 659
 660                 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
 661                 WREG32(AVIVO_DC_I2C_DATA, 0);
 662
 663                 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
 664                 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
 665                                                AVIVO_DC_I2C_DATA_COUNT(1) |
 666                                                (prescale << 16)));
 667                 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
 668                 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
 669                 for (j = 0; j < 200; j++) {
 670                         udelay(50);
 671                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 672                         if (tmp & AVIVO_DC_I2C_GO)
 673                                 continue;
 674                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 675                         if (tmp & AVIVO_DC_I2C_DONE)
 676                                 break;
 677                         else {
 678                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 679                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
 680                                 ret = -EIO;
 681                                 goto done;
 682                         }
 683                 }
 684                 goto done;
 685         }
 686
 687         for (i = 0; i < num; i++) {
 688                 p = &msgs[i];
 689                 remaining = p->len;
 690                 buffer_offset = 0;
 691                 if (p->flags & I2C_M_RD) {
 692                         while (remaining) {
 693                                 if (remaining > 15)
 694                                         current_count = 15;
 695                                 else
 696                                         current_count = remaining;
 697                                 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 698                                                               AVIVO_DC_I2C_NACK |
 699                                                               AVIVO_DC_I2C_HALT));
 700                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 701                                 udelay(1);
 702                                 WREG32(AVIVO_DC_I2C_RESET, 0);
 703
 704                                 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
 705                                 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
 706                                 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
 707                                                                AVIVO_DC_I2C_DATA_COUNT(current_count) |
 708                                                                (prescale << 16)));
 709                                 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
 710                                 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
 711                                 for (j = 0; j < 200; j++) {
 712                                         udelay(50);
 713                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 714                                         if (tmp & AVIVO_DC_I2C_GO)
 715                                                 continue;
 716                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 717                                         if (tmp & AVIVO_DC_I2C_DONE)
 718                                                 break;
 719                                         else {
 720                                                 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
 721                                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
 722                                                 ret = -EIO;
 723                                                 goto done;
 724                                         }
 725                                 }
 726                                 for (j = 0; j < current_count; j++)
 727                                         p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
 728                                 remaining -= current_count;
 729                                 buffer_offset += current_count;
 730                         }
 731                 } else {
 732                         while (remaining) {
 733                                 if (remaining > 15)
 734                                         current_count = 15;
 735                                 else
 736                                         current_count = remaining;
 737                                 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 738                                                               AVIVO_DC_I2C_NACK |
 739                                                               AVIVO_DC_I2C_HALT));
 740                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 741                                 udelay(1);
 742                                 WREG32(AVIVO_DC_I2C_RESET, 0);
 743
 744                                 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
 745                                 for (j = 0; j < current_count; j++)
 746                                         WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
 747
 748                                 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
 749                                 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
 750                                                                AVIVO_DC_I2C_DATA_COUNT(current_count) |
 751                                                                (prescale << 16)));
 752                                 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
 753                                 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
 754                                 for (j = 0; j < 200; j++) {
 755                                         udelay(50);
 756                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 757                                         if (tmp & AVIVO_DC_I2C_GO)
 758                                                 continue;
 759                                         tmp = RREG32(AVIVO_DC_I2C_STATUS1);
 760                                         if (tmp & AVIVO_DC_I2C_DONE)
 761                                                 break;
 762                                         else {
 763                                                 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
 764                                                 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
 765                                                 ret = -EIO;
 766                                                 goto done;
 767                                         }
 768                                 }
 769                                 remaining -= current_count;
 770                                 buffer_offset += current_count;
 771                         }
 772                 }
 773         }
 774
 775 done:
 776         WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
 777                                       AVIVO_DC_I2C_NACK |
 778                                       AVIVO_DC_I2C_HALT));
 779         WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
 780         udelay(1);
 781         WREG32(AVIVO_DC_I2C_RESET, 0);
 782
 783         WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
 784         WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
 785         WREG32(0x494, saved2);
 786         tmp = RREG32(RADEON_BIOS_6_SCRATCH);
 787         tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
 788         WREG32(RADEON_BIOS_6_SCRATCH, tmp);
 789
 790         mutex_unlock(&rdev->pm.mutex);
 791         mutex_unlock(&rdev->dc_hw_i2c_mutex);
 792
 793         return ret;
 794 }
 795
 796 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
 797                               struct i2c_msg *msgs, int num)
 798 {
 799         struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
 800         struct radeon_device *rdev = i2c->dev->dev_private;
 801         struct radeon_i2c_bus_rec *rec = &i2c->rec;
 802         int ret = 0;
 803
 804         switch (rdev->family) {
 805         case CHIP_R100:
 806         case CHIP_RV100:
 807         case CHIP_RS100:
 808         case CHIP_RV200:
 809         case CHIP_RS200:
 810         case CHIP_R200:
 811         case CHIP_RV250:
 812         case CHIP_RS300:
 813         case CHIP_RV280:
 814         case CHIP_R300:
 815         case CHIP_R350:
 816         case CHIP_RV350:
 817         case CHIP_RV380:
 818         case CHIP_R420:
 819         case CHIP_R423:
 820         case CHIP_RV410:
 821         case CHIP_RS400:
 822         case CHIP_RS480:
 823                 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
 824                 break;
 825         case CHIP_RS600:
 826         case CHIP_RS690:
 827         case CHIP_RS740:
 828                 /* XXX fill in hw i2c implementation */
 829                 break;
 830         case CHIP_RV515:
 831         case CHIP_R520:
 832         case CHIP_RV530:
 833         case CHIP_RV560:
 834         case CHIP_RV570:
 835         case CHIP_R580:
 836                 if (rec->mm_i2c)
 837                         ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
 838                 else
 839                         ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
 840                 break;
 841         case CHIP_R600:
 842         case CHIP_RV610:
 843         case CHIP_RV630:
 844         case CHIP_RV670:
 845                 /* XXX fill in hw i2c implementation */
 846                 break;
 847         case CHIP_RV620:
 848         case CHIP_RV635:
 849         case CHIP_RS780:
 850         case CHIP_RS880:
 851         case CHIP_RV770:
 852         case CHIP_RV730:
 853         case CHIP_RV710:
 854         case CHIP_RV740:
 855                 /* XXX fill in hw i2c implementation */
 856                 break;
 857         case CHIP_CEDAR:
 858         case CHIP_REDWOOD:
 859         case CHIP_JUNIPER:
 860         case CHIP_CYPRESS:
 861         case CHIP_HEMLOCK:
 862                 /* XXX fill in hw i2c implementation */
 863                 break;
 864         default:
 865                 DRM_ERROR("i2c: unhandled radeon chip\n");
 866                 ret = -EIO;
 867                 break;
 868         }
 869
 870         return ret;
 871 }
 872
 873 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
 874 {
 875         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 876 }
 877
 878 static const struct i2c_algorithm radeon_i2c_algo = {
 879         .master_xfer = radeon_hw_i2c_xfer,
 880         .functionality = radeon_hw_i2c_func,
 881 };
 882
 883 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
 884                                           struct radeon_i2c_bus_rec *rec,
 885                                           const char *name)
 886 {
 887         struct radeon_device *rdev = dev->dev_private;
 888         struct radeon_i2c_chan *i2c;
 889         int ret;
 890
 891         i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
 892         if (i2c == NULL)
 893                 return NULL;
 894
 895         i2c->rec = *rec;
 896         i2c->adapter.owner = THIS_MODULE;
 897         i2c->adapter.class = I2C_CLASS_DDC;
 898         i2c->dev = dev;
 899         i2c_set_adapdata(&i2c->adapter, i2c);
 900         if (rec->mm_i2c ||
 901             (rec->hw_capable &&
 902              radeon_hw_i2c &&
 903              ((rdev->family <= CHIP_RS480) ||
 904               ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
 905                 /* set the radeon hw i2c adapter */
 906                 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
 907                          "Radeon i2c hw bus %s", name);
 908                 i2c->adapter.algo = &radeon_i2c_algo;
 909                 ret = i2c_add_adapter(&i2c->adapter);
 910                 if (ret) {
 911                         DRM_ERROR("Failed to register hw i2c %s\n", name);
 912                         goto out_free;
 913                 }
 914         } else {
 915                 /* set the radeon bit adapter */
 916                 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
 917                          "Radeon i2c bit bus %s", name);
 918                 i2c->adapter.algo_data = &i2c->algo.bit;
 919                 i2c->algo.bit.pre_xfer = pre_xfer;
 920                 i2c->algo.bit.post_xfer = post_xfer;
 921                 i2c->algo.bit.setsda = set_data;
 922                 i2c->algo.bit.setscl = set_clock;
 923                 i2c->algo.bit.getsda = get_data;
 924                 i2c->algo.bit.getscl = get_clock;
 925                 i2c->algo.bit.udelay = 20;
 926                 /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
 927                  * make this, 2 jiffies is a lot more reliable */
 928                 i2c->algo.bit.timeout = 2;
 929                 i2c->algo.bit.data = i2c;
 930                 ret = i2c_bit_add_bus(&i2c->adapter);
 931                 if (ret) {
 932                         DRM_ERROR("Failed to register bit i2c %s\n", name);
 933                         goto out_free;
 934                 }
 935         }
 936
 937         return i2c;
 938 out_free:
 939         kfree(i2c);
 940         return NULL;
 941
 942 }
 943
 944 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
 945                                              struct radeon_i2c_bus_rec *rec,
 946                                              const char *name)
 947 {
 948         struct radeon_i2c_chan *i2c;
 949         int ret;
 950
 951         i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
 952         if (i2c == NULL)
 953                 return NULL;
 954
 955         i2c->rec = *rec;
 956         i2c->adapter.owner = THIS_MODULE;
 957         i2c->adapter.class = I2C_CLASS_DDC;
 958         i2c->dev = dev;
 959         snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
 960                  "Radeon aux bus %s", name);
 961         i2c_set_adapdata(&i2c->adapter, i2c);
 962         i2c->adapter.algo_data = &i2c->algo.dp;
 963         i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch;
 964         i2c->algo.dp.address = 0;
 965         ret = i2c_dp_aux_add_bus(&i2c->adapter);
 966         if (ret) {
 967                 DRM_INFO("Failed to register i2c %s\n", name);
 968                 goto out_free;
 969         }
 970
 971         return i2c;
 972 out_free:
 973         kfree(i2c);
 974         return NULL;
 975
 976 }
 977
 978 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
 979 {
 980         if (!i2c)
 981                 return;
 982         i2c_del_adapter(&i2c->adapter);
 983         kfree(i2c);
 984 }
 985
 986 /* Add the default buses */
 987 void radeon_i2c_init(struct radeon_device *rdev)
 988 {
 989         if (rdev->is_atom_bios)
 990                 radeon_atombios_i2c_init(rdev);
 991         else
 992                 radeon_combios_i2c_init(rdev);
 993 }
 994
 995 /* remove all the buses */
 996 void radeon_i2c_fini(struct radeon_device *rdev)
 997 {
 998         int i;
 999
1000         for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1001                 if (rdev->i2c_bus[i]) {
1002                         radeon_i2c_destroy(rdev->i2c_bus[i]);
1003                         rdev->i2c_bus[i] = NULL;
1004                 }
1005         }
1006 }
1007
1008 /* Add additional buses */
1009 void radeon_i2c_add(struct radeon_device *rdev,
1010                     struct radeon_i2c_bus_rec *rec,
1011                     const char *name)
1012 {
1013         struct drm_device *dev = rdev->ddev;
1014         int i;
1015
1016         for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1017                 if (!rdev->i2c_bus[i]) {
1018                         rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1019                         return;
1020                 }
1021         }
1022 }
1023
1024 /* looks up bus based on id */
1025 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1026                                           struct radeon_i2c_bus_rec *i2c_bus)
1027 {
1028         int i;
1029
1030         for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1031                 if (rdev->i2c_bus[i] &&
1032                     (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1033                         return rdev->i2c_bus[i];
1034                 }
1035         }
1036         return NULL;
1037 }
1038
1039 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
1040 {
1041         return NULL;
1042 }
1043
1044 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1045                          u8 slave_addr,
1046                          u8 addr,
1047                          u8 *val)
1048 {
1049         u8 out_buf[2];
1050         u8 in_buf[2];
1051         struct i2c_msg msgs[] = {
1052                 {
1053                         .addr = slave_addr,
1054                         .flags = 0,
1055                         .len = 1,
1056                         .buf = out_buf,
1057                 },
1058                 {
1059                         .addr = slave_addr,
1060                         .flags = I2C_M_RD,
1061                         .len = 1,
1062                         .buf = in_buf,
1063                 }
1064         };
1065
1066         out_buf[0] = addr;
1067         out_buf[1] = 0;
1068
1069         if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1070                 *val = in_buf[0];
1071                 DRM_DEBUG("val = 0x%02x\n", *val);
1072         } else {
1073                 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1074                           addr, *val);
1075         }
1076 }
1077
1078 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1079                          u8 slave_addr,
1080                          u8 addr,
1081                          u8 val)
1082 {
1083         uint8_t out_buf[2];
1084         struct i2c_msg msg = {
1085                 .addr = slave_addr,
1086                 .flags = 0,
1087                 .len = 2,
1088                 .buf = out_buf,
1089         };
1090
1091         out_buf[0] = addr;
1092         out_buf[1] = val;
1093
1094         if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1095                 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1096                           addr, val);
1097 }
1098
1099 /* ddc router switching */
1100 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1101 {
1102         u8 val;
1103
1104         if (!radeon_connector->router.ddc_valid)
1105                 return;
1106
1107         if (!radeon_connector->router_bus)
1108                 return;
1109
1110         radeon_i2c_get_byte(radeon_connector->router_bus,
1111                             radeon_connector->router.i2c_addr,
1112                             0x3, &val);
1113         val &= ~radeon_connector->router.ddc_mux_control_pin;
1114         radeon_i2c_put_byte(radeon_connector->router_bus,
1115                             radeon_connector->router.i2c_addr,
1116                             0x3, val);
1117         radeon_i2c_get_byte(radeon_connector->router_bus,
1118                             radeon_connector->router.i2c_addr,
1119                             0x1, &val);
1120         val &= ~radeon_connector->router.ddc_mux_control_pin;
1121         val |= radeon_connector->router.ddc_mux_state;
1122         radeon_i2c_put_byte(radeon_connector->router_bus,
1123                             radeon_connector->router.i2c_addr,
1124                             0x1, val);
1125 }
1126
1127 /* clock/data router switching */
1128 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1129 {
1130         u8 val;
1131
1132         if (!radeon_connector->router.cd_valid)
1133                 return;
1134
1135         if (!radeon_connector->router_bus)
1136                 return;
1137
1138         radeon_i2c_get_byte(radeon_connector->router_bus,
1139                             radeon_connector->router.i2c_addr,
1140                             0x3, &val);
1141         val &= ~radeon_connector->router.cd_mux_control_pin;
1142         radeon_i2c_put_byte(radeon_connector->router_bus,
1143                             radeon_connector->router.i2c_addr,
1144                             0x3, val);
1145         radeon_i2c_get_byte(radeon_connector->router_bus,
1146                             radeon_connector->router.i2c_addr,
1147                             0x1, &val);
1148         val &= ~radeon_connector->router.cd_mux_control_pin;
1149         val |= radeon_connector->router.cd_mux_state;
1150         radeon_i2c_put_byte(radeon_connector->router_bus,
1151                             radeon_connector->router.i2c_addr,
1152                             0x1, val);
1153 }
1154