drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <linux/pm_runtime.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_edid.h>
  36
  37 #include <linux/gcd.h>
  38
  39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  40 {
  41         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  42         struct drm_device *dev = crtc->dev;
  43         struct radeon_device *rdev = dev->dev_private;
  44         int i;
  45
  46         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  47         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  48
  49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  51         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  52
  53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  55         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  56
  57         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  58         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  59         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  60
  61         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  62         for (i = 0; i < 256; i++) {
  63                 WREG32(AVIVO_DC_LUT_30_COLOR,
  64                              (radeon_crtc->lut_r[i] << 20) |
  65                              (radeon_crtc->lut_g[i] << 10) |
  66                              (radeon_crtc->lut_b[i] << 0));
  67         }
  68
  69         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  70 }
  71
  72 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  73 {
  74         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  75         struct drm_device *dev = crtc->dev;
  76         struct radeon_device *rdev = dev->dev_private;
  77         int i;
  78
  79         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  80         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  81
  82         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  83         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  84         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  85
  86         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  87         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  88         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  89
  90         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  91         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  92
  93         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  94         for (i = 0; i < 256; i++) {
  95                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  96                        (radeon_crtc->lut_r[i] << 20) |
  97                        (radeon_crtc->lut_g[i] << 10) |
  98                        (radeon_crtc->lut_b[i] << 0));
  99         }
 100 }
 101
 102 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 103 {
 104         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 105         struct drm_device *dev = crtc->dev;
 106         struct radeon_device *rdev = dev->dev_private;
 107         int i;
 108
 109         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 110
 111         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 112                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 113                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 114         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 115                NI_GRPH_PRESCALE_BYPASS);
 116         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 117                NI_OVL_PRESCALE_BYPASS);
 118         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 119                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 120                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 121
 122         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 123
 124         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 125         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 126         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 127
 128         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 129         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 130         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 131
 132         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 133         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 134
 135         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 136         for (i = 0; i < 256; i++) {
 137                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 138                        (radeon_crtc->lut_r[i] << 20) |
 139                        (radeon_crtc->lut_g[i] << 10) |
 140                        (radeon_crtc->lut_b[i] << 0));
 141         }
 142
 143         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 144                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 145                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 146                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 147                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 148         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 149                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 150                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 151         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 152                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 153                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 154         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 155                (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 156                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 157         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 158         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 159         if (ASIC_IS_DCE8(rdev)) {
 160                 /* XXX this only needs to be programmed once per crtc at startup,
 161                  * not sure where the best place for it is
 162                  */
 163                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 164                        CIK_CURSOR_ALPHA_BLND_ENA);
 165         }
 166 }
 167
 168 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 169 {
 170         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 171         struct drm_device *dev = crtc->dev;
 172         struct radeon_device *rdev = dev->dev_private;
 173         int i;
 174         uint32_t dac2_cntl;
 175
 176         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 177         if (radeon_crtc->crtc_id == 0)
 178                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 179         else
 180                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 181         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 182
 183         WREG8(RADEON_PALETTE_INDEX, 0);
 184         for (i = 0; i < 256; i++) {
 185                 WREG32(RADEON_PALETTE_30_DATA,
 186                              (radeon_crtc->lut_r[i] << 20) |
 187                              (radeon_crtc->lut_g[i] << 10) |
 188                              (radeon_crtc->lut_b[i] << 0));
 189         }
 190 }
 191
 192 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 193 {
 194         struct drm_device *dev = crtc->dev;
 195         struct radeon_device *rdev = dev->dev_private;
 196
 197         if (!crtc->enabled)
 198                 return;
 199
 200         if (ASIC_IS_DCE5(rdev))
 201                 dce5_crtc_load_lut(crtc);
 202         else if (ASIC_IS_DCE4(rdev))
 203                 dce4_crtc_load_lut(crtc);
 204         else if (ASIC_IS_AVIVO(rdev))
 205                 avivo_crtc_load_lut(crtc);
 206         else
 207                 legacy_crtc_load_lut(crtc);
 208 }
 209
 210 /** Sets the color ramps on behalf of fbcon */
 211 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 212                               u16 blue, int regno)
 213 {
 214         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 215
 216         radeon_crtc->lut_r[regno] = red >> 6;
 217         radeon_crtc->lut_g[regno] = green >> 6;
 218         radeon_crtc->lut_b[regno] = blue >> 6;
 219 }
 220
 221 /** Gets the color ramps on behalf of fbcon */
 222 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 223                               u16 *blue, int regno)
 224 {
 225         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 226
 227         *red = radeon_crtc->lut_r[regno] << 6;
 228         *green = radeon_crtc->lut_g[regno] << 6;
 229         *blue = radeon_crtc->lut_b[regno] << 6;
 230 }
 231
 232 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 233                                   u16 *blue, uint32_t start, uint32_t size)
 234 {
 235         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 236         int end = (start + size > 256) ? 256 : start + size, i;
 237
 238         /* userspace palettes are always correct as is */
 239         for (i = start; i < end; i++) {
 240                 radeon_crtc->lut_r[i] = red[i] >> 6;
 241                 radeon_crtc->lut_g[i] = green[i] >> 6;
 242                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 243         }
 244         radeon_crtc_load_lut(crtc);
 245 }
 246
 247 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 248 {
 249         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 250
 251         drm_crtc_cleanup(crtc);
 252         kfree(radeon_crtc);
 253 }
 254
 255 /*
 256  * Handle unpin events outside the interrupt handler proper.
 257  */
 258 static void radeon_unpin_work_func(struct work_struct *__work)
 259 {
 260         struct radeon_unpin_work *work =
 261                 container_of(__work, struct radeon_unpin_work, work);
 262         int r;
 263
 264         /* unpin of the old buffer */
 265         r = radeon_bo_reserve(work->old_rbo, false);
 266         if (likely(r == 0)) {
 267                 r = radeon_bo_unpin(work->old_rbo);
 268                 if (unlikely(r != 0)) {
 269                         DRM_ERROR("failed to unpin buffer after flip\n");
 270                 }
 271                 radeon_bo_unreserve(work->old_rbo);
 272         } else
 273                 DRM_ERROR("failed to reserve buffer after flip\n");
 274
 275         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 276         kfree(work);
 277 }
 278
 279 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 280 {
 281         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 282         struct radeon_unpin_work *work;
 283         unsigned long flags;
 284         u32 update_pending;
 285         int vpos, hpos;
 286
 287         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 288         work = radeon_crtc->unpin_work;
 289         if (work == NULL ||
 290             (work->fence && !radeon_fence_signaled(work->fence))) {
 291                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 292                 return;
 293         }
 294         /* New pageflip, or just completion of a previous one? */
 295         if (!radeon_crtc->deferred_flip_completion) {
 296                 /* do the flip (mmio) */
 297                 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 298         } else {
 299                 /* This is just a completion of a flip queued in crtc
 300                  * at last invocation. Make sure we go directly to
 301                  * completion routine.
 302                  */
 303                 update_pending = 0;
 304                 radeon_crtc->deferred_flip_completion = 0;
 305         }
 306
 307         /* Has the pageflip already completed in crtc, or is it certain
 308          * to complete in this vblank?
 309          */
 310         if (update_pending &&
 311             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
 312                                                                &vpos, &hpos, NULL, NULL)) &&
 313             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 314              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 315                 /* crtc didn't flip in this target vblank interval,
 316                  * but flip is pending in crtc. Based on the current
 317                  * scanout position we know that the current frame is
 318                  * (nearly) complete and the flip will (likely)
 319                  * complete before the start of the next frame.
 320                  */
 321                 update_pending = 0;
 322         }
 323         if (update_pending) {
 324                 /* crtc didn't flip in this target vblank interval,
 325                  * but flip is pending in crtc. It will complete it
 326                  * in next vblank interval, so complete the flip at
 327                  * next vblank irq.
 328                  */
 329                 radeon_crtc->deferred_flip_completion = 1;
 330                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 331                 return;
 332         }
 333
 334         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
 335         radeon_crtc->unpin_work = NULL;
 336
 337         /* wakeup userspace */
 338         if (work->event)
 339                 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
 340
 341         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 342
 343         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 344         radeon_fence_unref(&work->fence);
 345         radeon_post_page_flip(work->rdev, work->crtc_id);
 346         schedule_work(&work->work);
 347 }
 348
 349 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 350                                  struct drm_framebuffer *fb,
 351                                  struct drm_pending_vblank_event *event,
 352                                  uint32_t page_flip_flags)
 353 {
 354         struct drm_device *dev = crtc->dev;
 355         struct radeon_device *rdev = dev->dev_private;
 356         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 357         struct radeon_framebuffer *old_radeon_fb;
 358         struct radeon_framebuffer *new_radeon_fb;
 359         struct drm_gem_object *obj;
 360         struct radeon_bo *rbo;
 361         struct radeon_unpin_work *work;
 362         unsigned long flags;
 363         u32 tiling_flags, pitch_pixels;
 364         u64 base;
 365         int r;
 366
 367         work = kzalloc(sizeof *work, GFP_KERNEL);
 368         if (work == NULL)
 369                 return -ENOMEM;
 370
 371         work->event = event;
 372         work->rdev = rdev;
 373         work->crtc_id = radeon_crtc->crtc_id;
 374         old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 375         new_radeon_fb = to_radeon_framebuffer(fb);
 376         /* schedule unpin of the old buffer */
 377         obj = old_radeon_fb->obj;
 378         /* take a reference to the old object */
 379         drm_gem_object_reference(obj);
 380         rbo = gem_to_radeon_bo(obj);
 381         work->old_rbo = rbo;
 382         obj = new_radeon_fb->obj;
 383         rbo = gem_to_radeon_bo(obj);
 384
 385         spin_lock(&rbo->tbo.bdev->fence_lock);
 386         if (rbo->tbo.sync_obj)
 387                 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
 388         spin_unlock(&rbo->tbo.bdev->fence_lock);
 389
 390         INIT_WORK(&work->work, radeon_unpin_work_func);
 391
 392         /* We borrow the event spin lock for protecting unpin_work */
 393         spin_lock_irqsave(&dev->event_lock, flags);
 394         if (radeon_crtc->unpin_work) {
 395                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 396                 r = -EBUSY;
 397                 goto unlock_free;
 398         }
 399         radeon_crtc->unpin_work = work;
 400         radeon_crtc->deferred_flip_completion = 0;
 401         spin_unlock_irqrestore(&dev->event_lock, flags);
 402
 403         /* pin the new buffer */
 404         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 405                          work->old_rbo, rbo);
 406
 407         r = radeon_bo_reserve(rbo, false);
 408         if (unlikely(r != 0)) {
 409                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 410                 goto pflip_cleanup;
 411         }
 412         /* Only 27 bit offset for legacy CRTC */
 413         r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
 414                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 415         if (unlikely(r != 0)) {
 416                 radeon_bo_unreserve(rbo);
 417                 r = -EINVAL;
 418                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 419                 goto pflip_cleanup;
 420         }
 421         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 422         radeon_bo_unreserve(rbo);
 423
 424         if (!ASIC_IS_AVIVO(rdev)) {
 425                 /* crtc offset is from display base addr not FB location */
 426                 base -= radeon_crtc->legacy_display_base_addr;
 427                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 428
 429                 if (tiling_flags & RADEON_TILING_MACRO) {
 430                         if (ASIC_IS_R300(rdev)) {
 431                                 base &= ~0x7ff;
 432                         } else {
 433                                 int byteshift = fb->bits_per_pixel >> 4;
 434                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 435                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 436                         }
 437                 } else {
 438                         int offset = crtc->y * pitch_pixels + crtc->x;
 439                         switch (fb->bits_per_pixel) {
 440                         case 8:
 441                         default:
 442                                 offset *= 1;
 443                                 break;
 444                         case 15:
 445                         case 16:
 446                                 offset *= 2;
 447                                 break;
 448                         case 24:
 449                                 offset *= 3;
 450                                 break;
 451                         case 32:
 452                                 offset *= 4;
 453                                 break;
 454                         }
 455                         base += offset;
 456                 }
 457                 base &= ~7;
 458         }
 459
 460         spin_lock_irqsave(&dev->event_lock, flags);
 461         work->new_crtc_base = base;
 462         spin_unlock_irqrestore(&dev->event_lock, flags);
 463
 464         /* update crtc fb */
 465         crtc->primary->fb = fb;
 466
 467         r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 468         if (r) {
 469                 DRM_ERROR("failed to get vblank before flip\n");
 470                 goto pflip_cleanup1;
 471         }
 472
 473         /* set the proper interrupt */
 474         radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 475
 476         return 0;
 477
 478 pflip_cleanup1:
 479         if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
 480                 DRM_ERROR("failed to reserve new rbo in error path\n");
 481                 goto pflip_cleanup;
 482         }
 483         if (unlikely(radeon_bo_unpin(rbo) != 0)) {
 484                 DRM_ERROR("failed to unpin new rbo in error path\n");
 485         }
 486         radeon_bo_unreserve(rbo);
 487
 488 pflip_cleanup:
 489         spin_lock_irqsave(&dev->event_lock, flags);
 490         radeon_crtc->unpin_work = NULL;
 491 unlock_free:
 492         spin_unlock_irqrestore(&dev->event_lock, flags);
 493         drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
 494         radeon_fence_unref(&work->fence);
 495         kfree(work);
 496
 497         return r;
 498 }
 499
 500 static int
 501 radeon_crtc_set_config(struct drm_mode_set *set)
 502 {
 503         struct drm_device *dev;
 504         struct radeon_device *rdev;
 505         struct drm_crtc *crtc;
 506         bool active = false;
 507         int ret;
 508
 509         if (!set || !set->crtc)
 510                 return -EINVAL;
 511
 512         dev = set->crtc->dev;
 513
 514         ret = pm_runtime_get_sync(dev->dev);
 515         if (ret < 0)
 516                 return ret;
 517
 518         ret = drm_crtc_helper_set_config(set);
 519
 520         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 521                 if (crtc->enabled)
 522                         active = true;
 523
 524         pm_runtime_mark_last_busy(dev->dev);
 525
 526         rdev = dev->dev_private;
 527         /* if we have active crtcs and we don't have a power ref,
 528            take the current one */
 529         if (active && !rdev->have_disp_power_ref) {
 530                 rdev->have_disp_power_ref = true;
 531                 return ret;
 532         }
 533         /* if we have no active crtcs, then drop the power ref
 534            we got before */
 535         if (!active && rdev->have_disp_power_ref) {
 536                 pm_runtime_put_autosuspend(dev->dev);
 537                 rdev->have_disp_power_ref = false;
 538         }
 539
 540         /* drop the power reference we got coming in here */
 541         pm_runtime_put_autosuspend(dev->dev);
 542         return ret;
 543 }
 544 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 545         .cursor_set = radeon_crtc_cursor_set,
 546         .cursor_move = radeon_crtc_cursor_move,
 547         .gamma_set = radeon_crtc_gamma_set,
 548         .set_config = radeon_crtc_set_config,
 549         .destroy = radeon_crtc_destroy,
 550         .page_flip = radeon_crtc_page_flip,
 551 };
 552
 553 static void radeon_crtc_init(struct drm_device *dev, int index)
 554 {
 555         struct radeon_device *rdev = dev->dev_private;
 556         struct radeon_crtc *radeon_crtc;
 557         int i;
 558
 559         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 560         if (radeon_crtc == NULL)
 561                 return;
 562
 563         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 564
 565         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 566         radeon_crtc->crtc_id = index;
 567         rdev->mode_info.crtcs[index] = radeon_crtc;
 568
 569         if (rdev->family >= CHIP_BONAIRE) {
 570                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 571                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 572         } else {
 573                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 574                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 575         }
 576         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 577         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 578
 579 #if 0
 580         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 581         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 582         radeon_crtc->mode_set.num_connectors = 0;
 583 #endif
 584
 585         for (i = 0; i < 256; i++) {
 586                 radeon_crtc->lut_r[i] = i << 2;
 587                 radeon_crtc->lut_g[i] = i << 2;
 588                 radeon_crtc->lut_b[i] = i << 2;
 589         }
 590
 591         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 592                 radeon_atombios_init_crtc(dev, radeon_crtc);
 593         else
 594                 radeon_legacy_init_crtc(dev, radeon_crtc);
 595 }
 596
 597 static const char *encoder_names[38] = {
 598         "NONE",
 599         "INTERNAL_LVDS",
 600         "INTERNAL_TMDS1",
 601         "INTERNAL_TMDS2",
 602         "INTERNAL_DAC1",
 603         "INTERNAL_DAC2",
 604         "INTERNAL_SDVOA",
 605         "INTERNAL_SDVOB",
 606         "SI170B",
 607         "CH7303",
 608         "CH7301",
 609         "INTERNAL_DVO1",
 610         "EXTERNAL_SDVOA",
 611         "EXTERNAL_SDVOB",
 612         "TITFP513",
 613         "INTERNAL_LVTM1",
 614         "VT1623",
 615         "HDMI_SI1930",
 616         "HDMI_INTERNAL",
 617         "INTERNAL_KLDSCP_TMDS1",
 618         "INTERNAL_KLDSCP_DVO1",
 619         "INTERNAL_KLDSCP_DAC1",
 620         "INTERNAL_KLDSCP_DAC2",
 621         "SI178",
 622         "MVPU_FPGA",
 623         "INTERNAL_DDI",
 624         "VT1625",
 625         "HDMI_SI1932",
 626         "DP_AN9801",
 627         "DP_DP501",
 628         "INTERNAL_UNIPHY",
 629         "INTERNAL_KLDSCP_LVTMA",
 630         "INTERNAL_UNIPHY1",
 631         "INTERNAL_UNIPHY2",
 632         "NUTMEG",
 633         "TRAVIS",
 634         "INTERNAL_VCE",
 635         "INTERNAL_UNIPHY3",
 636 };
 637
 638 static const char *hpd_names[6] = {
 639         "HPD1",
 640         "HPD2",
 641         "HPD3",
 642         "HPD4",
 643         "HPD5",
 644         "HPD6",
 645 };
 646
 647 static void radeon_print_display_setup(struct drm_device *dev)
 648 {
 649         struct drm_connector *connector;
 650         struct radeon_connector *radeon_connector;
 651         struct drm_encoder *encoder;
 652         struct radeon_encoder *radeon_encoder;
 653         uint32_t devices;
 654         int i = 0;
 655
 656         DRM_INFO("Radeon Display Connectors\n");
 657         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 658                 radeon_connector = to_radeon_connector(connector);
 659                 DRM_INFO("Connector %d:\n", i);
 660                 DRM_INFO("  %s\n", drm_get_connector_name(connector));
 661                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 662                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 663                 if (radeon_connector->ddc_bus) {
 664                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 665                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 666                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 667                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 668                                  radeon_connector->ddc_bus->rec.a_data_reg,
 669                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 670                                  radeon_connector->ddc_bus->rec.en_data_reg,
 671                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 672                                  radeon_connector->ddc_bus->rec.y_data_reg);
 673                         if (radeon_connector->router.ddc_valid)
 674                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 675                                          radeon_connector->router.ddc_mux_control_pin,
 676                                          radeon_connector->router.ddc_mux_state);
 677                         if (radeon_connector->router.cd_valid)
 678                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 679                                          radeon_connector->router.cd_mux_control_pin,
 680                                          radeon_connector->router.cd_mux_state);
 681                 } else {
 682                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 683                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 684                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 685                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 686                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 687                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 688                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 689                 }
 690                 DRM_INFO("  Encoders:\n");
 691                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 692                         radeon_encoder = to_radeon_encoder(encoder);
 693                         devices = radeon_encoder->devices & radeon_connector->devices;
 694                         if (devices) {
 695                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 696                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 697                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 698                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 699                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 700                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 701                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 702                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 703                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 704                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 705                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 706                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 707                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 708                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 709                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 710                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 711                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 712                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 713                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 714                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 715                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 716                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 717                         }
 718                 }
 719                 i++;
 720         }
 721 }
 722
 723 static bool radeon_setup_enc_conn(struct drm_device *dev)
 724 {
 725         struct radeon_device *rdev = dev->dev_private;
 726         bool ret = false;
 727
 728         if (rdev->bios) {
 729                 if (rdev->is_atom_bios) {
 730                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 731                         if (ret == false)
 732                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 733                 } else {
 734                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 735                         if (ret == false)
 736                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 737                 }
 738         } else {
 739                 if (!ASIC_IS_AVIVO(rdev))
 740                         ret = radeon_get_legacy_connector_info_from_table(dev);
 741         }
 742         if (ret) {
 743                 radeon_setup_encoder_clones(dev);
 744                 radeon_print_display_setup(dev);
 745         }
 746
 747         return ret;
 748 }
 749
 750 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 751 {
 752         struct drm_device *dev = radeon_connector->base.dev;
 753         struct radeon_device *rdev = dev->dev_private;
 754         int ret = 0;
 755
 756         /* on hw with routers, select right port */
 757         if (radeon_connector->router.ddc_valid)
 758                 radeon_router_select_ddc_port(radeon_connector);
 759
 760         if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
 761             ENCODER_OBJECT_ID_NONE) {
 762                 if (radeon_connector->ddc_bus->has_aux)
 763                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 764                                                               &radeon_connector->ddc_bus->aux.ddc);
 765         } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 766                    (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 767                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 768
 769                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 770                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 771                     radeon_connector->ddc_bus->has_aux)
 772                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 773                                                               &radeon_connector->ddc_bus->aux.ddc);
 774                 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
 775                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 776                                                               &radeon_connector->ddc_bus->adapter);
 777         } else {
 778                 if (radeon_connector->ddc_bus && !radeon_connector->edid)
 779                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 780                                                               &radeon_connector->ddc_bus->adapter);
 781         }
 782
 783         if (!radeon_connector->edid) {
 784                 if (rdev->is_atom_bios) {
 785                         /* some laptops provide a hardcoded edid in rom for LCDs */
 786                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 787                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 788                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 789                 } else
 790                         /* some servers provide a hardcoded edid in rom for KVMs */
 791                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 792         }
 793         if (radeon_connector->edid) {
 794                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 795                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 796                 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
 797                 return ret;
 798         }
 799         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 800         return 0;
 801 }
 802
 803 /* avivo */
 804
 805 /**
 806  * avivo_reduce_ratio - fractional number reduction
 807  *
 808  * @nom: nominator
 809  * @den: denominator
 810  * @nom_min: minimum value for nominator
 811  * @den_min: minimum value for denominator
 812  *
 813  * Find the greatest common divisor and apply it on both nominator and
 814  * denominator, but make nominator and denominator are at least as large
 815  * as their minimum values.
 816  */
 817 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 818                                unsigned nom_min, unsigned den_min)
 819 {
 820         unsigned tmp;
 821
 822         /* reduce the numbers to a simpler ratio */
 823         tmp = gcd(*nom, *den);
 824         *nom /= tmp;
 825         *den /= tmp;
 826
 827         /* make sure nominator is large enough */
 828         if (*nom < nom_min) {
 829                 tmp = (nom_min + *nom - 1) / *nom;
 830                 *nom *= tmp;
 831                 *den *= tmp;
 832         }
 833
 834         /* make sure the denominator is large enough */
 835         if (*den < den_min) {
 836                 tmp = (den_min + *den - 1) / *den;
 837                 *nom *= tmp;
 838                 *den *= tmp;
 839         }
 840 }
 841
 842 /**
 843  * avivo_get_fb_ref_div - feedback and ref divider calculation
 844  *
 845  * @nom: nominator
 846  * @den: denominator
 847  * @post_div: post divider
 848  * @fb_div_max: feedback divider maximum
 849  * @ref_div_max: reference divider maximum
 850  * @fb_div: resulting feedback divider
 851  * @ref_div: resulting reference divider
 852  *
 853  * Calculate feedback and reference divider for a given post divider. Makes
 854  * sure we stay within the limits.
 855  */
 856 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
 857                                  unsigned fb_div_max, unsigned ref_div_max,
 858                                  unsigned *fb_div, unsigned *ref_div)
 859 {
 860         /* limit reference * post divider to a maximum */
 861         ref_div_max = min(210 / post_div, ref_div_max);
 862
 863         /* get matching reference and feedback divider */
 864         *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
 865         *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
 866
 867         /* limit fb divider to its maximum */
 868         if (*fb_div > fb_div_max) {
 869                 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
 870                 *fb_div = fb_div_max;
 871         }
 872 }
 873
 874 /**
 875  * radeon_compute_pll_avivo - compute PLL paramaters
 876  *
 877  * @pll: information about the PLL
 878  * @dot_clock_p: resulting pixel clock
 879  * fb_div_p: resulting feedback divider
 880  * frac_fb_div_p: fractional part of the feedback divider
 881  * ref_div_p: resulting reference divider
 882  * post_div_p: resulting reference divider
 883  *
 884  * Try to calculate the PLL parameters to generate the given frequency:
 885  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 886  */
 887 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 888                               u32 freq,
 889                               u32 *dot_clock_p,
 890                               u32 *fb_div_p,
 891                               u32 *frac_fb_div_p,
 892                               u32 *ref_div_p,
 893                               u32 *post_div_p)
 894 {
 895         unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
 896                 freq : freq / 10;
 897
 898         unsigned fb_div_min, fb_div_max, fb_div;
 899         unsigned post_div_min, post_div_max, post_div;
 900         unsigned ref_div_min, ref_div_max, ref_div;
 901         unsigned post_div_best, diff_best;
 902         unsigned nom, den;
 903
 904         /* determine allowed feedback divider range */
 905         fb_div_min = pll->min_feedback_div;
 906         fb_div_max = pll->max_feedback_div;
 907
 908         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 909                 fb_div_min *= 10;
 910                 fb_div_max *= 10;
 911         }
 912
 913         /* determine allowed ref divider range */
 914         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 915                 ref_div_min = pll->reference_div;
 916         else
 917                 ref_div_min = pll->min_ref_div;
 918
 919         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
 920             pll->flags & RADEON_PLL_USE_REF_DIV)
 921                 ref_div_max = pll->reference_div;
 922         else
 923                 ref_div_max = pll->max_ref_div;
 924
 925         /* determine allowed post divider range */
 926         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
 927                 post_div_min = pll->post_div;
 928                 post_div_max = pll->post_div;
 929         } else {
 930                 unsigned vco_min, vco_max;
 931
 932                 if (pll->flags & RADEON_PLL_IS_LCD) {
 933                         vco_min = pll->lcd_pll_out_min;
 934                         vco_max = pll->lcd_pll_out_max;
 935                 } else {
 936                         vco_min = pll->pll_out_min;
 937                         vco_max = pll->pll_out_max;
 938                 }
 939
 940                 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 941                         vco_min *= 10;
 942                         vco_max *= 10;
 943                 }
 944
 945                 post_div_min = vco_min / target_clock;
 946                 if ((target_clock * post_div_min) < vco_min)
 947                         ++post_div_min;
 948                 if (post_div_min < pll->min_post_div)
 949                         post_div_min = pll->min_post_div;
 950
 951                 post_div_max = vco_max / target_clock;
 952                 if ((target_clock * post_div_max) > vco_max)
 953                         --post_div_max;
 954                 if (post_div_max > pll->max_post_div)
 955                         post_div_max = pll->max_post_div;
 956         }
 957
 958         /* represent the searched ratio as fractional number */
 959         nom = target_clock;
 960         den = pll->reference_freq;
 961
 962         /* reduce the numbers to a simpler ratio */
 963         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
 964
 965         /* now search for a post divider */
 966         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
 967                 post_div_best = post_div_min;
 968         else
 969                 post_div_best = post_div_max;
 970         diff_best = ~0;
 971
 972         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
 973                 unsigned diff;
 974                 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
 975                                      ref_div_max, &fb_div, &ref_div);
 976                 diff = abs(target_clock - (pll->reference_freq * fb_div) /
 977                         (ref_div * post_div));
 978
 979                 if (diff < diff_best || (diff == diff_best &&
 980                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
 981
 982                         post_div_best = post_div;
 983                         diff_best = diff;
 984                 }
 985         }
 986         post_div = post_div_best;
 987
 988         /* get the feedback and reference divider for the optimal value */
 989         avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
 990                              &fb_div, &ref_div);
 991
 992         /* reduce the numbers to a simpler ratio once more */
 993         /* this also makes sure that the reference divider is large enough */
 994         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
 995
 996         /* and finally save the result */
 997         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 998                 *fb_div_p = fb_div / 10;
 999                 *frac_fb_div_p = fb_div % 10;
1000         } else {
1001                 *fb_div_p = fb_div;
1002                 *frac_fb_div_p = 0;
1003         }
1004
1005         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1006                         (pll->reference_freq * *frac_fb_div_p)) /
1007                        (ref_div * post_div * 10);
1008         *ref_div_p = ref_div;
1009         *post_div_p = post_div;
1010
1011         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1012                       freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1013                       ref_div, post_div);
1014 }
1015
1016 /* pre-avivo */
1017 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1018 {
1019         uint64_t mod;
1020
1021         n += d / 2;
1022
1023         mod = do_div(n, d);
1024         return n;
1025 }
1026
1027 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1028                                uint64_t freq,
1029                                uint32_t *dot_clock_p,
1030                                uint32_t *fb_div_p,
1031                                uint32_t *frac_fb_div_p,
1032                                uint32_t *ref_div_p,
1033                                uint32_t *post_div_p)
1034 {
1035         uint32_t min_ref_div = pll->min_ref_div;
1036         uint32_t max_ref_div = pll->max_ref_div;
1037         uint32_t min_post_div = pll->min_post_div;
1038         uint32_t max_post_div = pll->max_post_div;
1039         uint32_t min_fractional_feed_div = 0;
1040         uint32_t max_fractional_feed_div = 0;
1041         uint32_t best_vco = pll->best_vco;
1042         uint32_t best_post_div = 1;
1043         uint32_t best_ref_div = 1;
1044         uint32_t best_feedback_div = 1;
1045         uint32_t best_frac_feedback_div = 0;
1046         uint32_t best_freq = -1;
1047         uint32_t best_error = 0xffffffff;
1048         uint32_t best_vco_diff = 1;
1049         uint32_t post_div;
1050         u32 pll_out_min, pll_out_max;
1051
1052         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1053         freq = freq * 1000;
1054
1055         if (pll->flags & RADEON_PLL_IS_LCD) {
1056                 pll_out_min = pll->lcd_pll_out_min;
1057                 pll_out_max = pll->lcd_pll_out_max;
1058         } else {
1059                 pll_out_min = pll->pll_out_min;
1060                 pll_out_max = pll->pll_out_max;
1061         }
1062
1063         if (pll_out_min > 64800)
1064                 pll_out_min = 64800;
1065
1066         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1067                 min_ref_div = max_ref_div = pll->reference_div;
1068         else {
1069                 while (min_ref_div < max_ref_div-1) {
1070                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1071                         uint32_t pll_in = pll->reference_freq / mid;
1072                         if (pll_in < pll->pll_in_min)
1073                                 max_ref_div = mid;
1074                         else if (pll_in > pll->pll_in_max)
1075                                 min_ref_div = mid;
1076                         else
1077                                 break;
1078                 }
1079         }
1080
1081         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1082                 min_post_div = max_post_div = pll->post_div;
1083
1084         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1085                 min_fractional_feed_div = pll->min_frac_feedback_div;
1086                 max_fractional_feed_div = pll->max_frac_feedback_div;
1087         }
1088
1089         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1090                 uint32_t ref_div;
1091
1092                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1093                         continue;
1094
1095                 /* legacy radeons only have a few post_divs */
1096                 if (pll->flags & RADEON_PLL_LEGACY) {
1097                         if ((post_div == 5) ||
1098                             (post_div == 7) ||
1099                             (post_div == 9) ||
1100                             (post_div == 10) ||
1101                             (post_div == 11) ||
1102                             (post_div == 13) ||
1103                             (post_div == 14) ||
1104                             (post_div == 15))
1105                                 continue;
1106                 }
1107
1108                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1109                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1110                         uint32_t pll_in = pll->reference_freq / ref_div;
1111                         uint32_t min_feed_div = pll->min_feedback_div;
1112                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1113
1114                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1115                                 continue;
1116
1117                         while (min_feed_div < max_feed_div) {
1118                                 uint32_t vco;
1119                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1120                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1121                                 uint32_t frac_feedback_div;
1122                                 uint64_t tmp;
1123
1124                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1125
1126                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1127                                 vco = radeon_div(tmp, ref_div);
1128
1129                                 if (vco < pll_out_min) {
1130                                         min_feed_div = feedback_div + 1;
1131                                         continue;
1132                                 } else if (vco > pll_out_max) {
1133                                         max_feed_div = feedback_div;
1134                                         continue;
1135                                 }
1136
1137                                 while (min_frac_feed_div < max_frac_feed_div) {
1138                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1139                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1140                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1141                                         current_freq = radeon_div(tmp, ref_div * post_div);
1142
1143                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1144                                                 if (freq < current_freq)
1145                                                         error = 0xffffffff;
1146                                                 else
1147                                                         error = freq - current_freq;
1148                                         } else
1149                                                 error = abs(current_freq - freq);
1150                                         vco_diff = abs(vco - best_vco);
1151
1152                                         if ((best_vco == 0 && error < best_error) ||
1153                                             (best_vco != 0 &&
1154                                              ((best_error > 100 && error < best_error - 100) ||
1155                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1156                                                 best_post_div = post_div;
1157                                                 best_ref_div = ref_div;
1158                                                 best_feedback_div = feedback_div;
1159                                                 best_frac_feedback_div = frac_feedback_div;
1160                                                 best_freq = current_freq;
1161                                                 best_error = error;
1162                                                 best_vco_diff = vco_diff;
1163                                         } else if (current_freq == freq) {
1164                                                 if (best_freq == -1) {
1165                                                         best_post_div = post_div;
1166                                                         best_ref_div = ref_div;
1167                                                         best_feedback_div = feedback_div;
1168                                                         best_frac_feedback_div = frac_feedback_div;
1169                                                         best_freq = current_freq;
1170                                                         best_error = error;
1171                                                         best_vco_diff = vco_diff;
1172                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1173                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1174                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1175                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1176                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1177                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1178                                                         best_post_div = post_div;
1179                                                         best_ref_div = ref_div;
1180                                                         best_feedback_div = feedback_div;
1181                                                         best_frac_feedback_div = frac_feedback_div;
1182                                                         best_freq = current_freq;
1183                                                         best_error = error;
1184                                                         best_vco_diff = vco_diff;
1185                                                 }
1186                                         }
1187                                         if (current_freq < freq)
1188                                                 min_frac_feed_div = frac_feedback_div + 1;
1189                                         else
1190                                                 max_frac_feed_div = frac_feedback_div;
1191                                 }
1192                                 if (current_freq < freq)
1193                                         min_feed_div = feedback_div + 1;
1194                                 else
1195                                         max_feed_div = feedback_div;
1196                         }
1197                 }
1198         }
1199
1200         *dot_clock_p = best_freq / 10000;
1201         *fb_div_p = best_feedback_div;
1202         *frac_fb_div_p = best_frac_feedback_div;
1203         *ref_div_p = best_ref_div;
1204         *post_div_p = best_post_div;
1205         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1206                       (long long)freq,
1207                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1208                       best_ref_div, best_post_div);
1209
1210 }
1211
1212 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1213 {
1214         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1215
1216         if (radeon_fb->obj) {
1217                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1218         }
1219         drm_framebuffer_cleanup(fb);
1220         kfree(radeon_fb);
1221 }
1222
1223 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1224                                                   struct drm_file *file_priv,
1225                                                   unsigned int *handle)
1226 {
1227         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1228
1229         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1230 }
1231
1232 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1233         .destroy = radeon_user_framebuffer_destroy,
1234         .create_handle = radeon_user_framebuffer_create_handle,
1235 };
1236
1237 int
1238 radeon_framebuffer_init(struct drm_device *dev,
1239                         struct radeon_framebuffer *rfb,
1240                         struct drm_mode_fb_cmd2 *mode_cmd,
1241                         struct drm_gem_object *obj)
1242 {
1243         int ret;
1244         rfb->obj = obj;
1245         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1246         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1247         if (ret) {
1248                 rfb->obj = NULL;
1249                 return ret;
1250         }
1251         return 0;
1252 }
1253
1254 static struct drm_framebuffer *
1255 radeon_user_framebuffer_create(struct drm_device *dev,
1256                                struct drm_file *file_priv,
1257                                struct drm_mode_fb_cmd2 *mode_cmd)
1258 {
1259         struct drm_gem_object *obj;
1260         struct radeon_framebuffer *radeon_fb;
1261         int ret;
1262
1263         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1264         if (obj ==  NULL) {
1265                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1266                         "can't create framebuffer\n", mode_cmd->handles[0]);
1267                 return ERR_PTR(-ENOENT);
1268         }
1269
1270         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1271         if (radeon_fb == NULL) {
1272                 drm_gem_object_unreference_unlocked(obj);
1273                 return ERR_PTR(-ENOMEM);
1274         }
1275
1276         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1277         if (ret) {
1278                 kfree(radeon_fb);
1279                 drm_gem_object_unreference_unlocked(obj);
1280                 return ERR_PTR(ret);
1281         }
1282
1283         return &radeon_fb->base;
1284 }
1285
1286 static void radeon_output_poll_changed(struct drm_device *dev)
1287 {
1288         struct radeon_device *rdev = dev->dev_private;
1289         radeon_fb_output_poll_changed(rdev);
1290 }
1291
1292 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1293         .fb_create = radeon_user_framebuffer_create,
1294         .output_poll_changed = radeon_output_poll_changed
1295 };
1296
1297 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1298 {       { 0, "driver" },
1299         { 1, "bios" },
1300 };
1301
1302 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1303 {       { TV_STD_NTSC, "ntsc" },
1304         { TV_STD_PAL, "pal" },
1305         { TV_STD_PAL_M, "pal-m" },
1306         { TV_STD_PAL_60, "pal-60" },
1307         { TV_STD_NTSC_J, "ntsc-j" },
1308         { TV_STD_SCART_PAL, "scart-pal" },
1309         { TV_STD_PAL_CN, "pal-cn" },
1310         { TV_STD_SECAM, "secam" },
1311 };
1312
1313 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1314 {       { UNDERSCAN_OFF, "off" },
1315         { UNDERSCAN_ON, "on" },
1316         { UNDERSCAN_AUTO, "auto" },
1317 };
1318
1319 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1320 {       { RADEON_AUDIO_DISABLE, "off" },
1321         { RADEON_AUDIO_ENABLE, "on" },
1322         { RADEON_AUDIO_AUTO, "auto" },
1323 };
1324
1325 /* XXX support different dither options? spatial, temporal, both, etc. */
1326 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1327 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1328         { RADEON_FMT_DITHER_ENABLE, "on" },
1329 };
1330
1331 static int radeon_modeset_create_props(struct radeon_device *rdev)
1332 {
1333         int sz;
1334
1335         if (rdev->is_atom_bios) {
1336                 rdev->mode_info.coherent_mode_property =
1337                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1338                 if (!rdev->mode_info.coherent_mode_property)
1339                         return -ENOMEM;
1340         }
1341
1342         if (!ASIC_IS_AVIVO(rdev)) {
1343                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1344                 rdev->mode_info.tmds_pll_property =
1345                         drm_property_create_enum(rdev->ddev, 0,
1346                                             "tmds_pll",
1347                                             radeon_tmds_pll_enum_list, sz);
1348         }
1349
1350         rdev->mode_info.load_detect_property =
1351                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1352         if (!rdev->mode_info.load_detect_property)
1353                 return -ENOMEM;
1354
1355         drm_mode_create_scaling_mode_property(rdev->ddev);
1356
1357         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1358         rdev->mode_info.tv_std_property =
1359                 drm_property_create_enum(rdev->ddev, 0,
1360                                     "tv standard",
1361                                     radeon_tv_std_enum_list, sz);
1362
1363         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1364         rdev->mode_info.underscan_property =
1365                 drm_property_create_enum(rdev->ddev, 0,
1366                                     "underscan",
1367                                     radeon_underscan_enum_list, sz);
1368
1369         rdev->mode_info.underscan_hborder_property =
1370                 drm_property_create_range(rdev->ddev, 0,
1371                                         "underscan hborder", 0, 128);
1372         if (!rdev->mode_info.underscan_hborder_property)
1373                 return -ENOMEM;
1374
1375         rdev->mode_info.underscan_vborder_property =
1376                 drm_property_create_range(rdev->ddev, 0,
1377                                         "underscan vborder", 0, 128);
1378         if (!rdev->mode_info.underscan_vborder_property)
1379                 return -ENOMEM;
1380
1381         sz = ARRAY_SIZE(radeon_audio_enum_list);
1382         rdev->mode_info.audio_property =
1383                 drm_property_create_enum(rdev->ddev, 0,
1384                                          "audio",
1385                                          radeon_audio_enum_list, sz);
1386
1387         sz = ARRAY_SIZE(radeon_dither_enum_list);
1388         rdev->mode_info.dither_property =
1389                 drm_property_create_enum(rdev->ddev, 0,
1390                                          "dither",
1391                                          radeon_dither_enum_list, sz);
1392
1393         return 0;
1394 }
1395
1396 void radeon_update_display_priority(struct radeon_device *rdev)
1397 {
1398         /* adjustment options for the display watermarks */
1399         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1400                 /* set display priority to high for r3xx, rv515 chips
1401                  * this avoids flickering due to underflow to the
1402                  * display controllers during heavy acceleration.
1403                  * Don't force high on rs4xx igp chips as it seems to
1404                  * affect the sound card.  See kernel bug 15982.
1405                  */
1406                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1407                     !(rdev->flags & RADEON_IS_IGP))
1408                         rdev->disp_priority = 2;
1409                 else
1410                         rdev->disp_priority = 0;
1411         } else
1412                 rdev->disp_priority = radeon_disp_priority;
1413
1414 }
1415
1416 /*
1417  * Allocate hdmi structs and determine register offsets
1418  */
1419 static void radeon_afmt_init(struct radeon_device *rdev)
1420 {
1421         int i;
1422
1423         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1424                 rdev->mode_info.afmt[i] = NULL;
1425
1426         if (ASIC_IS_NODCE(rdev)) {
1427                 /* nothing to do */
1428         } else if (ASIC_IS_DCE4(rdev)) {
1429                 static uint32_t eg_offsets[] = {
1430                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1431                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1432                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1433                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1434                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1435                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1436                         0x13830 - 0x7030,
1437                 };
1438                 int num_afmt;
1439
1440                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1441                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1442                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1443                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1444                 if (ASIC_IS_DCE8(rdev))
1445                         num_afmt = 7;
1446                 else if (ASIC_IS_DCE6(rdev))
1447                         num_afmt = 6;
1448                 else if (ASIC_IS_DCE5(rdev))
1449                         num_afmt = 6;
1450                 else if (ASIC_IS_DCE41(rdev))
1451                         num_afmt = 2;
1452                 else /* DCE4 */
1453                         num_afmt = 6;
1454
1455                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1456                 for (i = 0; i < num_afmt; i++) {
1457                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1458                         if (rdev->mode_info.afmt[i]) {
1459                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1460                                 rdev->mode_info.afmt[i]->id = i;
1461                         }
1462                 }
1463         } else if (ASIC_IS_DCE3(rdev)) {
1464                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1465                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1466                 if (rdev->mode_info.afmt[0]) {
1467                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1468                         rdev->mode_info.afmt[0]->id = 0;
1469                 }
1470                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1471                 if (rdev->mode_info.afmt[1]) {
1472                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1473                         rdev->mode_info.afmt[1]->id = 1;
1474                 }
1475         } else if (ASIC_IS_DCE2(rdev)) {
1476                 /* DCE2 has at least 1 routable audio block */
1477                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1478                 if (rdev->mode_info.afmt[0]) {
1479                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1480                         rdev->mode_info.afmt[0]->id = 0;
1481                 }
1482                 /* r6xx has 2 routable audio blocks */
1483                 if (rdev->family >= CHIP_R600) {
1484                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1485                         if (rdev->mode_info.afmt[1]) {
1486                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1487                                 rdev->mode_info.afmt[1]->id = 1;
1488                         }
1489                 }
1490         }
1491 }
1492
1493 static void radeon_afmt_fini(struct radeon_device *rdev)
1494 {
1495         int i;
1496
1497         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1498                 kfree(rdev->mode_info.afmt[i]);
1499                 rdev->mode_info.afmt[i] = NULL;
1500         }
1501 }
1502
1503 int radeon_modeset_init(struct radeon_device *rdev)
1504 {
1505         int i;
1506         int ret;
1507
1508         drm_mode_config_init(rdev->ddev);
1509         rdev->mode_info.mode_config_initialized = true;
1510
1511         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1512
1513         if (ASIC_IS_DCE5(rdev)) {
1514                 rdev->ddev->mode_config.max_width = 16384;
1515                 rdev->ddev->mode_config.max_height = 16384;
1516         } else if (ASIC_IS_AVIVO(rdev)) {
1517                 rdev->ddev->mode_config.max_width = 8192;
1518                 rdev->ddev->mode_config.max_height = 8192;
1519         } else {
1520                 rdev->ddev->mode_config.max_width = 4096;
1521                 rdev->ddev->mode_config.max_height = 4096;
1522         }
1523
1524         rdev->ddev->mode_config.preferred_depth = 24;
1525         rdev->ddev->mode_config.prefer_shadow = 1;
1526
1527         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1528
1529         ret = radeon_modeset_create_props(rdev);
1530         if (ret) {
1531                 return ret;
1532         }
1533
1534         /* init i2c buses */
1535         radeon_i2c_init(rdev);
1536
1537         /* check combios for a valid hardcoded EDID - Sun servers */
1538         if (!rdev->is_atom_bios) {
1539                 /* check for hardcoded EDID in BIOS */
1540                 radeon_combios_check_hardcoded_edid(rdev);
1541         }
1542
1543         /* allocate crtcs */
1544         for (i = 0; i < rdev->num_crtc; i++) {
1545                 radeon_crtc_init(rdev->ddev, i);
1546         }
1547
1548         /* okay we should have all the bios connectors */
1549         ret = radeon_setup_enc_conn(rdev->ddev);
1550         if (!ret) {
1551                 return ret;
1552         }
1553
1554         /* init dig PHYs, disp eng pll */
1555         if (rdev->is_atom_bios) {
1556                 radeon_atom_encoder_init(rdev);
1557                 radeon_atom_disp_eng_pll_init(rdev);
1558         }
1559
1560         /* initialize hpd */
1561         radeon_hpd_init(rdev);
1562
1563         /* setup afmt */
1564         radeon_afmt_init(rdev);
1565
1566         radeon_fbdev_init(rdev);
1567         drm_kms_helper_poll_init(rdev->ddev);
1568
1569         if (rdev->pm.dpm_enabled) {
1570                 /* do dpm late init */
1571                 ret = radeon_pm_late_init(rdev);
1572                 if (ret) {
1573                         rdev->pm.dpm_enabled = false;
1574                         DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1575                 }
1576                 /* set the dpm state for PX since there won't be
1577                  * a modeset to call this.
1578                  */
1579                 radeon_pm_compute_clocks(rdev);
1580         }
1581
1582         return 0;
1583 }
1584
1585 void radeon_modeset_fini(struct radeon_device *rdev)
1586 {
1587         radeon_fbdev_fini(rdev);
1588         kfree(rdev->mode_info.bios_hardcoded_edid);
1589
1590         if (rdev->mode_info.mode_config_initialized) {
1591                 radeon_afmt_fini(rdev);
1592                 drm_kms_helper_poll_fini(rdev->ddev);
1593                 radeon_hpd_fini(rdev);
1594                 drm_mode_config_cleanup(rdev->ddev);
1595                 rdev->mode_info.mode_config_initialized = false;
1596         }
1597         /* free i2c buses */
1598         radeon_i2c_fini(rdev);
1599 }
1600
1601 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1602 {
1603         /* try and guess if this is a tv or a monitor */
1604         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1605             (mode->vdisplay == 576) || /* 576p */
1606             (mode->vdisplay == 720) || /* 720p */
1607             (mode->vdisplay == 1080)) /* 1080p */
1608                 return true;
1609         else
1610                 return false;
1611 }
1612
1613 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1614                                 const struct drm_display_mode *mode,
1615                                 struct drm_display_mode *adjusted_mode)
1616 {
1617         struct drm_device *dev = crtc->dev;
1618         struct radeon_device *rdev = dev->dev_private;
1619         struct drm_encoder *encoder;
1620         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1621         struct radeon_encoder *radeon_encoder;
1622         struct drm_connector *connector;
1623         struct radeon_connector *radeon_connector;
1624         bool first = true;
1625         u32 src_v = 1, dst_v = 1;
1626         u32 src_h = 1, dst_h = 1;
1627
1628         radeon_crtc->h_border = 0;
1629         radeon_crtc->v_border = 0;
1630
1631         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1632                 if (encoder->crtc != crtc)
1633                         continue;
1634                 radeon_encoder = to_radeon_encoder(encoder);
1635                 connector = radeon_get_connector_for_encoder(encoder);
1636                 radeon_connector = to_radeon_connector(connector);
1637
1638                 if (first) {
1639                         /* set scaling */
1640                         if (radeon_encoder->rmx_type == RMX_OFF)
1641                                 radeon_crtc->rmx_type = RMX_OFF;
1642                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1643                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1644                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1645                         else
1646                                 radeon_crtc->rmx_type = RMX_OFF;
1647                         /* copy native mode */
1648                         memcpy(&radeon_crtc->native_mode,
1649                                &radeon_encoder->native_mode,
1650                                 sizeof(struct drm_display_mode));
1651                         src_v = crtc->mode.vdisplay;
1652                         dst_v = radeon_crtc->native_mode.vdisplay;
1653                         src_h = crtc->mode.hdisplay;
1654                         dst_h = radeon_crtc->native_mode.hdisplay;
1655
1656                         /* fix up for overscan on hdmi */
1657                         if (ASIC_IS_AVIVO(rdev) &&
1658                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1659                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1660                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1661                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1662                               is_hdtv_mode(mode)))) {
1663                                 if (radeon_encoder->underscan_hborder != 0)
1664                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1665                                 else
1666                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1667                                 if (radeon_encoder->underscan_vborder != 0)
1668                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1669                                 else
1670                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1671                                 radeon_crtc->rmx_type = RMX_FULL;
1672                                 src_v = crtc->mode.vdisplay;
1673                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1674                                 src_h = crtc->mode.hdisplay;
1675                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1676                         }
1677                         first = false;
1678                 } else {
1679                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1680                                 /* WARNING: Right now this can't happen but
1681                                  * in the future we need to check that scaling
1682                                  * are consistent across different encoder
1683                                  * (ie all encoder can work with the same
1684                                  *  scaling).
1685                                  */
1686                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1687                                 return false;
1688                         }
1689                 }
1690         }
1691         if (radeon_crtc->rmx_type != RMX_OFF) {
1692                 fixed20_12 a, b;
1693                 a.full = dfixed_const(src_v);
1694                 b.full = dfixed_const(dst_v);
1695                 radeon_crtc->vsc.full = dfixed_div(a, b);
1696                 a.full = dfixed_const(src_h);
1697                 b.full = dfixed_const(dst_h);
1698                 radeon_crtc->hsc.full = dfixed_div(a, b);
1699         } else {
1700                 radeon_crtc->vsc.full = dfixed_const(1);
1701                 radeon_crtc->hsc.full = dfixed_const(1);
1702         }
1703         return true;
1704 }
1705
1706 /*
1707  * Retrieve current video scanout position of crtc on a given gpu, and
1708  * an optional accurate timestamp of when query happened.
1709  *
1710  * \param dev Device to query.
1711  * \param crtc Crtc to query.
1712  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1713  * \param *vpos Location where vertical scanout position should be stored.
1714  * \param *hpos Location where horizontal scanout position should go.
1715  * \param *stime Target location for timestamp taken immediately before
1716  *               scanout position query. Can be NULL to skip timestamp.
1717  * \param *etime Target location for timestamp taken immediately after
1718  *               scanout position query. Can be NULL to skip timestamp.
1719  *
1720  * Returns vpos as a positive number while in active scanout area.
1721  * Returns vpos as a negative number inside vblank, counting the number
1722  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1723  * until start of active scanout / end of vblank."
1724  *
1725  * \return Flags, or'ed together as follows:
1726  *
1727  * DRM_SCANOUTPOS_VALID = Query successful.
1728  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1729  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1730  * this flag means that returned position may be offset by a constant but
1731  * unknown small number of scanlines wrt. real scanout position.
1732  *
1733  */
1734 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1735                                int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1736 {
1737         u32 stat_crtc = 0, vbl = 0, position = 0;
1738         int vbl_start, vbl_end, vtotal, ret = 0;
1739         bool in_vbl = true;
1740
1741         struct radeon_device *rdev = dev->dev_private;
1742
1743         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1744
1745         /* Get optional system timestamp before query. */
1746         if (stime)
1747                 *stime = ktime_get();
1748
1749         if (ASIC_IS_DCE4(rdev)) {
1750                 if (crtc == 0) {
1751                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1752                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1753                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1754                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1755                         ret |= DRM_SCANOUTPOS_VALID;
1756                 }
1757                 if (crtc == 1) {
1758                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1759                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1760                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1761                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1762                         ret |= DRM_SCANOUTPOS_VALID;
1763                 }
1764                 if (crtc == 2) {
1765                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1766                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1767                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1768                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1769                         ret |= DRM_SCANOUTPOS_VALID;
1770                 }
1771                 if (crtc == 3) {
1772                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1773                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1774                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1775                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1776                         ret |= DRM_SCANOUTPOS_VALID;
1777                 }
1778                 if (crtc == 4) {
1779                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1780                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1781                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1782                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1783                         ret |= DRM_SCANOUTPOS_VALID;
1784                 }
1785                 if (crtc == 5) {
1786                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1787                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1788                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1789                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1790                         ret |= DRM_SCANOUTPOS_VALID;
1791                 }
1792         } else if (ASIC_IS_AVIVO(rdev)) {
1793                 if (crtc == 0) {
1794                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1795                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1796                         ret |= DRM_SCANOUTPOS_VALID;
1797                 }
1798                 if (crtc == 1) {
1799                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1800                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1801                         ret |= DRM_SCANOUTPOS_VALID;
1802                 }
1803         } else {
1804                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1805                 if (crtc == 0) {
1806                         /* Assume vbl_end == 0, get vbl_start from
1807                          * upper 16 bits.
1808                          */
1809                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1810                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1811                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1812                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1813                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1814                         if (!(stat_crtc & 1))
1815                                 in_vbl = false;
1816
1817                         ret |= DRM_SCANOUTPOS_VALID;
1818                 }
1819                 if (crtc == 1) {
1820                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1821                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1822                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1823                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1824                         if (!(stat_crtc & 1))
1825                                 in_vbl = false;
1826
1827                         ret |= DRM_SCANOUTPOS_VALID;
1828                 }
1829         }
1830
1831         /* Get optional system timestamp after query. */
1832         if (etime)
1833                 *etime = ktime_get();
1834
1835         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1836
1837         /* Decode into vertical and horizontal scanout position. */
1838         *vpos = position & 0x1fff;
1839         *hpos = (position >> 16) & 0x1fff;
1840
1841         /* Valid vblank area boundaries from gpu retrieved? */
1842         if (vbl > 0) {
1843                 /* Yes: Decode. */
1844                 ret |= DRM_SCANOUTPOS_ACCURATE;
1845                 vbl_start = vbl & 0x1fff;
1846                 vbl_end = (vbl >> 16) & 0x1fff;
1847         }
1848         else {
1849                 /* No: Fake something reasonable which gives at least ok results. */
1850                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1851                 vbl_end = 0;
1852         }
1853
1854         /* Test scanout position against vblank region. */
1855         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1856                 in_vbl = false;
1857
1858         /* Check if inside vblank area and apply corrective offsets:
1859          * vpos will then be >=0 in video scanout area, but negative
1860          * within vblank area, counting down the number of lines until
1861          * start of scanout.
1862          */
1863
1864         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1865         if (in_vbl && (*vpos >= vbl_start)) {
1866                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1867                 *vpos = *vpos - vtotal;
1868         }
1869
1870         /* Correct for shifted end of vbl at vbl_end. */
1871         *vpos = *vpos - vbl_end;
1872
1873         /* In vblank? */
1874         if (in_vbl)
1875                 ret |= DRM_SCANOUTPOS_INVBL;
1876
1877         /* Is vpos outside nominal vblank area, but less than
1878          * 1/100 of a frame height away from start of vblank?
1879          * If so, assume this isn't a massively delayed vblank
1880          * interrupt, but a vblank interrupt that fired a few
1881          * microseconds before true start of vblank. Compensate
1882          * by adding a full frame duration to the final timestamp.
1883          * Happens, e.g., on ATI R500, R600.
1884          *
1885          * We only do this if DRM_CALLED_FROM_VBLIRQ.
1886          */
1887         if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1888                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1889                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1890
1891                 if (vbl_start - *vpos < vtotal / 100) {
1892                         *vpos -= vtotal;
1893
1894                         /* Signal this correction as "applied". */
1895                         ret |= 0x8;
1896                 }
1897         }
1898
1899         return ret;
1900 }