drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40
  41 #define PFP_UCODE_SIZE 576
  42 #define PM4_UCODE_SIZE 1792
  43 #define RLC_UCODE_SIZE 768
  44 #define R700_PFP_UCODE_SIZE 848
  45 #define R700_PM4_UCODE_SIZE 1360
  46 #define R700_RLC_UCODE_SIZE 1024
  47 #define EVERGREEN_PFP_UCODE_SIZE 1120
  48 #define EVERGREEN_PM4_UCODE_SIZE 1376
  49 #define EVERGREEN_RLC_UCODE_SIZE 768
  50
  51 /* Firmware Names */
  52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  53 MODULE_FIRMWARE("radeon/R600_me.bin");
  54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV610_me.bin");
  56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV630_me.bin");
  58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV620_me.bin");
  60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV635_me.bin");
  62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV670_me.bin");
  64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RS780_me.bin");
  66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RV770_me.bin");
  68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  69 MODULE_FIRMWARE("radeon/RV730_me.bin");
  70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  71 MODULE_FIRMWARE("radeon/RV710_me.bin");
  72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  86
  87 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  88
  89 /* r600,rv610,rv630,rv620,rv635,rv670 */
  90 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  91 void r600_gpu_init(struct radeon_device *rdev);
  92 void r600_fini(struct radeon_device *rdev);
  93 void r600_irq_disable(struct radeon_device *rdev);
  94
  95 /* hpd for digital panel detect/disconnect */
  96 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  97 {
  98         bool connected = false;
  99
 100         if (ASIC_IS_DCE3(rdev)) {
 101                 switch (hpd) {
 102                 case RADEON_HPD_1:
 103                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 104                                 connected = true;
 105                         break;
 106                 case RADEON_HPD_2:
 107                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 108                                 connected = true;
 109                         break;
 110                 case RADEON_HPD_3:
 111                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 112                                 connected = true;
 113                         break;
 114                 case RADEON_HPD_4:
 115                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 116                                 connected = true;
 117                         break;
 118                         /* DCE 3.2 */
 119                 case RADEON_HPD_5:
 120                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 121                                 connected = true;
 122                         break;
 123                 case RADEON_HPD_6:
 124                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 125                                 connected = true;
 126                         break;
 127                 default:
 128                         break;
 129                 }
 130         } else {
 131                 switch (hpd) {
 132                 case RADEON_HPD_1:
 133                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 134                                 connected = true;
 135                         break;
 136                 case RADEON_HPD_2:
 137                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 138                                 connected = true;
 139                         break;
 140                 case RADEON_HPD_3:
 141                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 142                                 connected = true;
 143                         break;
 144                 default:
 145                         break;
 146                 }
 147         }
 148         return connected;
 149 }
 150
 151 void r600_hpd_set_polarity(struct radeon_device *rdev,
 152                            enum radeon_hpd_id hpd)
 153 {
 154         u32 tmp;
 155         bool connected = r600_hpd_sense(rdev, hpd);
 156
 157         if (ASIC_IS_DCE3(rdev)) {
 158                 switch (hpd) {
 159                 case RADEON_HPD_1:
 160                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 161                         if (connected)
 162                                 tmp &= ~DC_HPDx_INT_POLARITY;
 163                         else
 164                                 tmp |= DC_HPDx_INT_POLARITY;
 165                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 166                         break;
 167                 case RADEON_HPD_2:
 168                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 169                         if (connected)
 170                                 tmp &= ~DC_HPDx_INT_POLARITY;
 171                         else
 172                                 tmp |= DC_HPDx_INT_POLARITY;
 173                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 174                         break;
 175                 case RADEON_HPD_3:
 176                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 177                         if (connected)
 178                                 tmp &= ~DC_HPDx_INT_POLARITY;
 179                         else
 180                                 tmp |= DC_HPDx_INT_POLARITY;
 181                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 182                         break;
 183                 case RADEON_HPD_4:
 184                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 185                         if (connected)
 186                                 tmp &= ~DC_HPDx_INT_POLARITY;
 187                         else
 188                                 tmp |= DC_HPDx_INT_POLARITY;
 189                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 190                         break;
 191                 case RADEON_HPD_5:
 192                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 193                         if (connected)
 194                                 tmp &= ~DC_HPDx_INT_POLARITY;
 195                         else
 196                                 tmp |= DC_HPDx_INT_POLARITY;
 197                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 198                         break;
 199                         /* DCE 3.2 */
 200                 case RADEON_HPD_6:
 201                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 202                         if (connected)
 203                                 tmp &= ~DC_HPDx_INT_POLARITY;
 204                         else
 205                                 tmp |= DC_HPDx_INT_POLARITY;
 206                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 207                         break;
 208                 default:
 209                         break;
 210                 }
 211         } else {
 212                 switch (hpd) {
 213                 case RADEON_HPD_1:
 214                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 215                         if (connected)
 216                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 217                         else
 218                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 219                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 220                         break;
 221                 case RADEON_HPD_2:
 222                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 223                         if (connected)
 224                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 225                         else
 226                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 227                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 228                         break;
 229                 case RADEON_HPD_3:
 230                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 231                         if (connected)
 232                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 233                         else
 234                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 235                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 236                         break;
 237                 default:
 238                         break;
 239                 }
 240         }
 241 }
 242
 243 void r600_hpd_init(struct radeon_device *rdev)
 244 {
 245         struct drm_device *dev = rdev->ddev;
 246         struct drm_connector *connector;
 247
 248         if (ASIC_IS_DCE3(rdev)) {
 249                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 250                 if (ASIC_IS_DCE32(rdev))
 251                         tmp |= DC_HPDx_EN;
 252
 253                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 254                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 255                         switch (radeon_connector->hpd.hpd) {
 256                         case RADEON_HPD_1:
 257                                 WREG32(DC_HPD1_CONTROL, tmp);
 258                                 rdev->irq.hpd[0] = true;
 259                                 break;
 260                         case RADEON_HPD_2:
 261                                 WREG32(DC_HPD2_CONTROL, tmp);
 262                                 rdev->irq.hpd[1] = true;
 263                                 break;
 264                         case RADEON_HPD_3:
 265                                 WREG32(DC_HPD3_CONTROL, tmp);
 266                                 rdev->irq.hpd[2] = true;
 267                                 break;
 268                         case RADEON_HPD_4:
 269                                 WREG32(DC_HPD4_CONTROL, tmp);
 270                                 rdev->irq.hpd[3] = true;
 271                                 break;
 272                                 /* DCE 3.2 */
 273                         case RADEON_HPD_5:
 274                                 WREG32(DC_HPD5_CONTROL, tmp);
 275                                 rdev->irq.hpd[4] = true;
 276                                 break;
 277                         case RADEON_HPD_6:
 278                                 WREG32(DC_HPD6_CONTROL, tmp);
 279                                 rdev->irq.hpd[5] = true;
 280                                 break;
 281                         default:
 282                                 break;
 283                         }
 284                 }
 285         } else {
 286                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 287                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 288                         switch (radeon_connector->hpd.hpd) {
 289                         case RADEON_HPD_1:
 290                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 291                                 rdev->irq.hpd[0] = true;
 292                                 break;
 293                         case RADEON_HPD_2:
 294                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 295                                 rdev->irq.hpd[1] = true;
 296                                 break;
 297                         case RADEON_HPD_3:
 298                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 299                                 rdev->irq.hpd[2] = true;
 300                                 break;
 301                         default:
 302                                 break;
 303                         }
 304                 }
 305         }
 306         if (rdev->irq.installed)
 307                 r600_irq_set(rdev);
 308 }
 309
 310 void r600_hpd_fini(struct radeon_device *rdev)
 311 {
 312         struct drm_device *dev = rdev->ddev;
 313         struct drm_connector *connector;
 314
 315         if (ASIC_IS_DCE3(rdev)) {
 316                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 317                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 318                         switch (radeon_connector->hpd.hpd) {
 319                         case RADEON_HPD_1:
 320                                 WREG32(DC_HPD1_CONTROL, 0);
 321                                 rdev->irq.hpd[0] = false;
 322                                 break;
 323                         case RADEON_HPD_2:
 324                                 WREG32(DC_HPD2_CONTROL, 0);
 325                                 rdev->irq.hpd[1] = false;
 326                                 break;
 327                         case RADEON_HPD_3:
 328                                 WREG32(DC_HPD3_CONTROL, 0);
 329                                 rdev->irq.hpd[2] = false;
 330                                 break;
 331                         case RADEON_HPD_4:
 332                                 WREG32(DC_HPD4_CONTROL, 0);
 333                                 rdev->irq.hpd[3] = false;
 334                                 break;
 335                                 /* DCE 3.2 */
 336                         case RADEON_HPD_5:
 337                                 WREG32(DC_HPD5_CONTROL, 0);
 338                                 rdev->irq.hpd[4] = false;
 339                                 break;
 340                         case RADEON_HPD_6:
 341                                 WREG32(DC_HPD6_CONTROL, 0);
 342                                 rdev->irq.hpd[5] = false;
 343                                 break;
 344                         default:
 345                                 break;
 346                         }
 347                 }
 348         } else {
 349                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 350                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 351                         switch (radeon_connector->hpd.hpd) {
 352                         case RADEON_HPD_1:
 353                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 354                                 rdev->irq.hpd[0] = false;
 355                                 break;
 356                         case RADEON_HPD_2:
 357                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 358                                 rdev->irq.hpd[1] = false;
 359                                 break;
 360                         case RADEON_HPD_3:
 361                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 362                                 rdev->irq.hpd[2] = false;
 363                                 break;
 364                         default:
 365                                 break;
 366                         }
 367                 }
 368         }
 369 }
 370
 371 /*
 372  * R600 PCIE GART
 373  */
 374 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 375 {
 376         unsigned i;
 377         u32 tmp;
 378
 379         /* flush hdp cache so updates hit vram */
 380         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 381
 382         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 383         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 384         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 385         for (i = 0; i < rdev->usec_timeout; i++) {
 386                 /* read MC_STATUS */
 387                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 388                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 389                 if (tmp == 2) {
 390                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 391                         return;
 392                 }
 393                 if (tmp) {
 394                         return;
 395                 }
 396                 udelay(1);
 397         }
 398 }
 399
 400 int r600_pcie_gart_init(struct radeon_device *rdev)
 401 {
 402         int r;
 403
 404         if (rdev->gart.table.vram.robj) {
 405                 WARN(1, "R600 PCIE GART already initialized.\n");
 406                 return 0;
 407         }
 408         /* Initialize common gart structure */
 409         r = radeon_gart_init(rdev);
 410         if (r)
 411                 return r;
 412         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 413         return radeon_gart_table_vram_alloc(rdev);
 414 }
 415
 416 int r600_pcie_gart_enable(struct radeon_device *rdev)
 417 {
 418         u32 tmp;
 419         int r, i;
 420
 421         if (rdev->gart.table.vram.robj == NULL) {
 422                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 423                 return -EINVAL;
 424         }
 425         r = radeon_gart_table_vram_pin(rdev);
 426         if (r)
 427                 return r;
 428         radeon_gart_restore(rdev);
 429
 430         /* Setup L2 cache */
 431         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 432                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 433                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 434         WREG32(VM_L2_CNTL2, 0);
 435         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 436         /* Setup TLB control */
 437         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 438                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 439                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 440                 ENABLE_WAIT_L2_QUERY;
 441         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 442         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 443         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 444         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 445         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 446         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 447         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 448         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 449         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 450         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 451         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 452         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 453         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 454         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 455         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 456         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 457         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 458         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 459                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 460         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 461                         (u32)(rdev->dummy_page.addr >> 12));
 462         for (i = 1; i < 7; i++)
 463                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 464
 465         r600_pcie_gart_tlb_flush(rdev);
 466         rdev->gart.ready = true;
 467         return 0;
 468 }
 469
 470 void r600_pcie_gart_disable(struct radeon_device *rdev)
 471 {
 472         u32 tmp;
 473         int i, r;
 474
 475         /* Disable all tables */
 476         for (i = 0; i < 7; i++)
 477                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 478
 479         /* Disable L2 cache */
 480         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 481                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 482         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 483         /* Setup L1 TLB control */
 484         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 485                 ENABLE_WAIT_L2_QUERY;
 486         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 487         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 488         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 489         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 490         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 491         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 492         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 493         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 494         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 495         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 496         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 497         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 498         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 499         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 500         if (rdev->gart.table.vram.robj) {
 501                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 502                 if (likely(r == 0)) {
 503                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 504                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 505                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 506                 }
 507         }
 508 }
 509
 510 void r600_pcie_gart_fini(struct radeon_device *rdev)
 511 {
 512         radeon_gart_fini(rdev);
 513         r600_pcie_gart_disable(rdev);
 514         radeon_gart_table_vram_free(rdev);
 515 }
 516
 517 void r600_agp_enable(struct radeon_device *rdev)
 518 {
 519         u32 tmp;
 520         int i;
 521
 522         /* Setup L2 cache */
 523         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 524                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 525                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 526         WREG32(VM_L2_CNTL2, 0);
 527         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 528         /* Setup TLB control */
 529         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 530                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 531                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 532                 ENABLE_WAIT_L2_QUERY;
 533         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 534         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 535         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 536         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 537         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 538         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 539         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 540         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 541         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 542         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 543         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 544         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 545         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 546         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 547         for (i = 0; i < 7; i++)
 548                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 549 }
 550
 551 int r600_mc_wait_for_idle(struct radeon_device *rdev)
 552 {
 553         unsigned i;
 554         u32 tmp;
 555
 556         for (i = 0; i < rdev->usec_timeout; i++) {
 557                 /* read MC_STATUS */
 558                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
 559                 if (!tmp)
 560                         return 0;
 561                 udelay(1);
 562         }
 563         return -1;
 564 }
 565
 566 static void r600_mc_program(struct radeon_device *rdev)
 567 {
 568         struct rv515_mc_save save;
 569         u32 tmp;
 570         int i, j;
 571
 572         /* Initialize HDP */
 573         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 574                 WREG32((0x2c14 + j), 0x00000000);
 575                 WREG32((0x2c18 + j), 0x00000000);
 576                 WREG32((0x2c1c + j), 0x00000000);
 577                 WREG32((0x2c20 + j), 0x00000000);
 578                 WREG32((0x2c24 + j), 0x00000000);
 579         }
 580         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 581
 582         rv515_mc_stop(rdev, &save);
 583         if (r600_mc_wait_for_idle(rdev)) {
 584                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 585         }
 586         /* Lockout access through VGA aperture (doesn't exist before R600) */
 587         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 588         /* Update configuration */
 589         if (rdev->flags & RADEON_IS_AGP) {
 590                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 591                         /* VRAM before AGP */
 592                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 593                                 rdev->mc.vram_start >> 12);
 594                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 595                                 rdev->mc.gtt_end >> 12);
 596                 } else {
 597                         /* VRAM after AGP */
 598                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 599                                 rdev->mc.gtt_start >> 12);
 600                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 601                                 rdev->mc.vram_end >> 12);
 602                 }
 603         } else {
 604                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
 605                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
 606         }
 607         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 608         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 609         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 610         WREG32(MC_VM_FB_LOCATION, tmp);
 611         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 612         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 613         WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
 614         if (rdev->flags & RADEON_IS_AGP) {
 615                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
 616                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
 617                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 618         } else {
 619                 WREG32(MC_VM_AGP_BASE, 0);
 620                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 621                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 622         }
 623         if (r600_mc_wait_for_idle(rdev)) {
 624                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 625         }
 626         rv515_mc_resume(rdev, &save);
 627         /* we need to own VRAM, so turn off the VGA renderer here
 628          * to stop it overwriting our objects */
 629         rv515_vga_render_disable(rdev);
 630 }
 631
 632 /**
 633  * r600_vram_gtt_location - try to find VRAM & GTT location
 634  * @rdev: radeon device structure holding all necessary informations
 635  * @mc: memory controller structure holding memory informations
 636  *
 637  * Function will place try to place VRAM at same place as in CPU (PCI)
 638  * address space as some GPU seems to have issue when we reprogram at
 639  * different address space.
 640  *
 641  * If there is not enough space to fit the unvisible VRAM after the
 642  * aperture then we limit the VRAM size to the aperture.
 643  *
 644  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
 645  * them to be in one from GPU point of view so that we can program GPU to
 646  * catch access outside them (weird GPU policy see ??).
 647  *
 648  * This function will never fails, worst case are limiting VRAM or GTT.
 649  *
 650  * Note: GTT start, end, size should be initialized before calling this
 651  * function on AGP platform.
 652  */
 653 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 654 {
 655         u64 size_bf, size_af;
 656
 657         if (mc->mc_vram_size > 0xE0000000) {
 658                 /* leave room for at least 512M GTT */
 659                 dev_warn(rdev->dev, "limiting VRAM\n");
 660                 mc->real_vram_size = 0xE0000000;
 661                 mc->mc_vram_size = 0xE0000000;
 662         }
 663         if (rdev->flags & RADEON_IS_AGP) {
 664                 size_bf = mc->gtt_start;
 665                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
 666                 if (size_bf > size_af) {
 667                         if (mc->mc_vram_size > size_bf) {
 668                                 dev_warn(rdev->dev, "limiting VRAM\n");
 669                                 mc->real_vram_size = size_bf;
 670                                 mc->mc_vram_size = size_bf;
 671                         }
 672                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
 673                 } else {
 674                         if (mc->mc_vram_size > size_af) {
 675                                 dev_warn(rdev->dev, "limiting VRAM\n");
 676                                 mc->real_vram_size = size_af;
 677                                 mc->mc_vram_size = size_af;
 678                         }
 679                         mc->vram_start = mc->gtt_end;
 680                 }
 681                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 682                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
 683                                 mc->mc_vram_size >> 20, mc->vram_start,
 684                                 mc->vram_end, mc->real_vram_size >> 20);
 685         } else {
 686                 u64 base = 0;
 687                 if (rdev->flags & RADEON_IS_IGP)
 688                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
 689                 radeon_vram_location(rdev, &rdev->mc, base);
 690                 radeon_gtt_location(rdev, mc);
 691         }
 692 }
 693
 694 int r600_mc_init(struct radeon_device *rdev)
 695 {
 696         u32 tmp;
 697         int chansize, numchan;
 698
 699         /* Get VRAM informations */
 700         rdev->mc.vram_is_ddr = true;
 701         tmp = RREG32(RAMCFG);
 702         if (tmp & CHANSIZE_OVERRIDE) {
 703                 chansize = 16;
 704         } else if (tmp & CHANSIZE_MASK) {
 705                 chansize = 64;
 706         } else {
 707                 chansize = 32;
 708         }
 709         tmp = RREG32(CHMAP);
 710         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 711         case 0:
 712         default:
 713                 numchan = 1;
 714                 break;
 715         case 1:
 716                 numchan = 2;
 717                 break;
 718         case 2:
 719                 numchan = 4;
 720                 break;
 721         case 3:
 722                 numchan = 8;
 723                 break;
 724         }
 725         rdev->mc.vram_width = numchan * chansize;
 726         /* Could aper size report 0 ? */
 727         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 728         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 729         /* Setup GPU memory space */
 730         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 731         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 732         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 733         /* FIXME remove this once we support unmappable VRAM */
 734         if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
 735                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
 736                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 737         }
 738         r600_vram_gtt_location(rdev, &rdev->mc);
 739
 740         if (rdev->flags & RADEON_IS_IGP)
 741                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 742         radeon_update_bandwidth_info(rdev);
 743         return 0;
 744 }
 745
 746 /* We doesn't check that the GPU really needs a reset we simply do the
 747  * reset, it's up to the caller to determine if the GPU needs one. We
 748  * might add an helper function to check that.
 749  */
 750 int r600_gpu_soft_reset(struct radeon_device *rdev)
 751 {
 752         struct rv515_mc_save save;
 753         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
 754                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
 755                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
 756                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
 757                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
 758                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
 759                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
 760                                 S_008010_GUI_ACTIVE(1);
 761         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
 762                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
 763                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
 764                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
 765                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
 766                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
 767                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
 768                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
 769         u32 tmp;
 770
 771         dev_info(rdev->dev, "GPU softreset \n");
 772         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 773                 RREG32(R_008010_GRBM_STATUS));
 774         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 775                 RREG32(R_008014_GRBM_STATUS2));
 776         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 777                 RREG32(R_000E50_SRBM_STATUS));
 778         rv515_mc_stop(rdev, &save);
 779         if (r600_mc_wait_for_idle(rdev)) {
 780                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 781         }
 782         /* Disable CP parsing/prefetching */
 783         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
 784         /* Check if any of the rendering block is busy and reset it */
 785         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
 786             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
 787                 tmp = S_008020_SOFT_RESET_CR(1) |
 788                         S_008020_SOFT_RESET_DB(1) |
 789                         S_008020_SOFT_RESET_CB(1) |
 790                         S_008020_SOFT_RESET_PA(1) |
 791                         S_008020_SOFT_RESET_SC(1) |
 792                         S_008020_SOFT_RESET_SMX(1) |
 793                         S_008020_SOFT_RESET_SPI(1) |
 794                         S_008020_SOFT_RESET_SX(1) |
 795                         S_008020_SOFT_RESET_SH(1) |
 796                         S_008020_SOFT_RESET_TC(1) |
 797                         S_008020_SOFT_RESET_TA(1) |
 798                         S_008020_SOFT_RESET_VC(1) |
 799                         S_008020_SOFT_RESET_VGT(1);
 800                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 801                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 802                 RREG32(R_008020_GRBM_SOFT_RESET);
 803                 mdelay(15);
 804                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
 805         }
 806         /* Reset CP (we always reset CP) */
 807         tmp = S_008020_SOFT_RESET_CP(1);
 808         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 809         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 810         RREG32(R_008020_GRBM_SOFT_RESET);
 811         mdelay(15);
 812         WREG32(R_008020_GRBM_SOFT_RESET, 0);
 813         /* Wait a little for things to settle down */
 814         mdelay(1);
 815         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 816                 RREG32(R_008010_GRBM_STATUS));
 817         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 818                 RREG32(R_008014_GRBM_STATUS2));
 819         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 820                 RREG32(R_000E50_SRBM_STATUS));
 821         rv515_mc_resume(rdev, &save);
 822         return 0;
 823 }
 824
 825 bool r600_gpu_is_lockup(struct radeon_device *rdev)
 826 {
 827         u32 srbm_status;
 828         u32 grbm_status;
 829         u32 grbm_status2;
 830         int r;
 831
 832         srbm_status = RREG32(R_000E50_SRBM_STATUS);
 833         grbm_status = RREG32(R_008010_GRBM_STATUS);
 834         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
 835         if (!G_008010_GUI_ACTIVE(grbm_status)) {
 836                 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
 837                 return false;
 838         }
 839         /* force CP activities */
 840         r = radeon_ring_lock(rdev, 2);
 841         if (!r) {
 842                 /* PACKET2 NOP */
 843                 radeon_ring_write(rdev, 0x80000000);
 844                 radeon_ring_write(rdev, 0x80000000);
 845                 radeon_ring_unlock_commit(rdev);
 846         }
 847         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
 848         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
 849 }
 850
 851 int r600_asic_reset(struct radeon_device *rdev)
 852 {
 853         return r600_gpu_soft_reset(rdev);
 854 }
 855
 856 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 857                                              u32 num_backends,
 858                                              u32 backend_disable_mask)
 859 {
 860         u32 backend_map = 0;
 861         u32 enabled_backends_mask;
 862         u32 enabled_backends_count;
 863         u32 cur_pipe;
 864         u32 swizzle_pipe[R6XX_MAX_PIPES];
 865         u32 cur_backend;
 866         u32 i;
 867
 868         if (num_tile_pipes > R6XX_MAX_PIPES)
 869                 num_tile_pipes = R6XX_MAX_PIPES;
 870         if (num_tile_pipes < 1)
 871                 num_tile_pipes = 1;
 872         if (num_backends > R6XX_MAX_BACKENDS)
 873                 num_backends = R6XX_MAX_BACKENDS;
 874         if (num_backends < 1)
 875                 num_backends = 1;
 876
 877         enabled_backends_mask = 0;
 878         enabled_backends_count = 0;
 879         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 880                 if (((backend_disable_mask >> i) & 1) == 0) {
 881                         enabled_backends_mask |= (1 << i);
 882                         ++enabled_backends_count;
 883                 }
 884                 if (enabled_backends_count == num_backends)
 885                         break;
 886         }
 887
 888         if (enabled_backends_count == 0) {
 889                 enabled_backends_mask = 1;
 890                 enabled_backends_count = 1;
 891         }
 892
 893         if (enabled_backends_count != num_backends)
 894                 num_backends = enabled_backends_count;
 895
 896         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 897         switch (num_tile_pipes) {
 898         case 1:
 899                 swizzle_pipe[0] = 0;
 900                 break;
 901         case 2:
 902                 swizzle_pipe[0] = 0;
 903                 swizzle_pipe[1] = 1;
 904                 break;
 905         case 3:
 906                 swizzle_pipe[0] = 0;
 907                 swizzle_pipe[1] = 1;
 908                 swizzle_pipe[2] = 2;
 909                 break;
 910         case 4:
 911                 swizzle_pipe[0] = 0;
 912                 swizzle_pipe[1] = 1;
 913                 swizzle_pipe[2] = 2;
 914                 swizzle_pipe[3] = 3;
 915                 break;
 916         case 5:
 917                 swizzle_pipe[0] = 0;
 918                 swizzle_pipe[1] = 1;
 919                 swizzle_pipe[2] = 2;
 920                 swizzle_pipe[3] = 3;
 921                 swizzle_pipe[4] = 4;
 922                 break;
 923         case 6:
 924                 swizzle_pipe[0] = 0;
 925                 swizzle_pipe[1] = 2;
 926                 swizzle_pipe[2] = 4;
 927                 swizzle_pipe[3] = 5;
 928                 swizzle_pipe[4] = 1;
 929                 swizzle_pipe[5] = 3;
 930                 break;
 931         case 7:
 932                 swizzle_pipe[0] = 0;
 933                 swizzle_pipe[1] = 2;
 934                 swizzle_pipe[2] = 4;
 935                 swizzle_pipe[3] = 6;
 936                 swizzle_pipe[4] = 1;
 937                 swizzle_pipe[5] = 3;
 938                 swizzle_pipe[6] = 5;
 939                 break;
 940         case 8:
 941                 swizzle_pipe[0] = 0;
 942                 swizzle_pipe[1] = 2;
 943                 swizzle_pipe[2] = 4;
 944                 swizzle_pipe[3] = 6;
 945                 swizzle_pipe[4] = 1;
 946                 swizzle_pipe[5] = 3;
 947                 swizzle_pipe[6] = 5;
 948                 swizzle_pipe[7] = 7;
 949                 break;
 950         }
 951
 952         cur_backend = 0;
 953         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 954                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 955                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 956
 957                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 958
 959                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 960         }
 961
 962         return backend_map;
 963 }
 964
 965 int r600_count_pipe_bits(uint32_t val)
 966 {
 967         int i, ret = 0;
 968
 969         for (i = 0; i < 32; i++) {
 970                 ret += val & 1;
 971                 val >>= 1;
 972         }
 973         return ret;
 974 }
 975
 976 void r600_gpu_init(struct radeon_device *rdev)
 977 {
 978         u32 tiling_config;
 979         u32 ramcfg;
 980         u32 backend_map;
 981         u32 cc_rb_backend_disable;
 982         u32 cc_gc_shader_pipe_config;
 983         u32 tmp;
 984         int i, j;
 985         u32 sq_config;
 986         u32 sq_gpr_resource_mgmt_1 = 0;
 987         u32 sq_gpr_resource_mgmt_2 = 0;
 988         u32 sq_thread_resource_mgmt = 0;
 989         u32 sq_stack_resource_mgmt_1 = 0;
 990         u32 sq_stack_resource_mgmt_2 = 0;
 991
 992         /* FIXME: implement */
 993         switch (rdev->family) {
 994         case CHIP_R600:
 995                 rdev->config.r600.max_pipes = 4;
 996                 rdev->config.r600.max_tile_pipes = 8;
 997                 rdev->config.r600.max_simds = 4;
 998                 rdev->config.r600.max_backends = 4;
 999                 rdev->config.r600.max_gprs = 256;
1000                 rdev->config.r600.max_threads = 192;
1001                 rdev->config.r600.max_stack_entries = 256;
1002                 rdev->config.r600.max_hw_contexts = 8;
1003                 rdev->config.r600.max_gs_threads = 16;
1004                 rdev->config.r600.sx_max_export_size = 128;
1005                 rdev->config.r600.sx_max_export_pos_size = 16;
1006                 rdev->config.r600.sx_max_export_smx_size = 128;
1007                 rdev->config.r600.sq_num_cf_insts = 2;
1008                 break;
1009         case CHIP_RV630:
1010         case CHIP_RV635:
1011                 rdev->config.r600.max_pipes = 2;
1012                 rdev->config.r600.max_tile_pipes = 2;
1013                 rdev->config.r600.max_simds = 3;
1014                 rdev->config.r600.max_backends = 1;
1015                 rdev->config.r600.max_gprs = 128;
1016                 rdev->config.r600.max_threads = 192;
1017                 rdev->config.r600.max_stack_entries = 128;
1018                 rdev->config.r600.max_hw_contexts = 8;
1019                 rdev->config.r600.max_gs_threads = 4;
1020                 rdev->config.r600.sx_max_export_size = 128;
1021                 rdev->config.r600.sx_max_export_pos_size = 16;
1022                 rdev->config.r600.sx_max_export_smx_size = 128;
1023                 rdev->config.r600.sq_num_cf_insts = 2;
1024                 break;
1025         case CHIP_RV610:
1026         case CHIP_RV620:
1027         case CHIP_RS780:
1028         case CHIP_RS880:
1029                 rdev->config.r600.max_pipes = 1;
1030                 rdev->config.r600.max_tile_pipes = 1;
1031                 rdev->config.r600.max_simds = 2;
1032                 rdev->config.r600.max_backends = 1;
1033                 rdev->config.r600.max_gprs = 128;
1034                 rdev->config.r600.max_threads = 192;
1035                 rdev->config.r600.max_stack_entries = 128;
1036                 rdev->config.r600.max_hw_contexts = 4;
1037                 rdev->config.r600.max_gs_threads = 4;
1038                 rdev->config.r600.sx_max_export_size = 128;
1039                 rdev->config.r600.sx_max_export_pos_size = 16;
1040                 rdev->config.r600.sx_max_export_smx_size = 128;
1041                 rdev->config.r600.sq_num_cf_insts = 1;
1042                 break;
1043         case CHIP_RV670:
1044                 rdev->config.r600.max_pipes = 4;
1045                 rdev->config.r600.max_tile_pipes = 4;
1046                 rdev->config.r600.max_simds = 4;
1047                 rdev->config.r600.max_backends = 4;
1048                 rdev->config.r600.max_gprs = 192;
1049                 rdev->config.r600.max_threads = 192;
1050                 rdev->config.r600.max_stack_entries = 256;
1051                 rdev->config.r600.max_hw_contexts = 8;
1052                 rdev->config.r600.max_gs_threads = 16;
1053                 rdev->config.r600.sx_max_export_size = 128;
1054                 rdev->config.r600.sx_max_export_pos_size = 16;
1055                 rdev->config.r600.sx_max_export_smx_size = 128;
1056                 rdev->config.r600.sq_num_cf_insts = 2;
1057                 break;
1058         default:
1059                 break;
1060         }
1061
1062         /* Initialize HDP */
1063         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1064                 WREG32((0x2c14 + j), 0x00000000);
1065                 WREG32((0x2c18 + j), 0x00000000);
1066                 WREG32((0x2c1c + j), 0x00000000);
1067                 WREG32((0x2c20 + j), 0x00000000);
1068                 WREG32((0x2c24 + j), 0x00000000);
1069         }
1070
1071         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1072
1073         /* Setup tiling */
1074         tiling_config = 0;
1075         ramcfg = RREG32(RAMCFG);
1076         switch (rdev->config.r600.max_tile_pipes) {
1077         case 1:
1078                 tiling_config |= PIPE_TILING(0);
1079                 break;
1080         case 2:
1081                 tiling_config |= PIPE_TILING(1);
1082                 break;
1083         case 4:
1084                 tiling_config |= PIPE_TILING(2);
1085                 break;
1086         case 8:
1087                 tiling_config |= PIPE_TILING(3);
1088                 break;
1089         default:
1090                 break;
1091         }
1092         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1093         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1094         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1095         tiling_config |= GROUP_SIZE(0);
1096         rdev->config.r600.tiling_group_size = 256;
1097         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1098         if (tmp > 3) {
1099                 tiling_config |= ROW_TILING(3);
1100                 tiling_config |= SAMPLE_SPLIT(3);
1101         } else {
1102                 tiling_config |= ROW_TILING(tmp);
1103                 tiling_config |= SAMPLE_SPLIT(tmp);
1104         }
1105         tiling_config |= BANK_SWAPS(1);
1106
1107         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1108         cc_rb_backend_disable |=
1109                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1110
1111         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1112         cc_gc_shader_pipe_config |=
1113                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1114         cc_gc_shader_pipe_config |=
1115                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1116
1117         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1118                                                         (R6XX_MAX_BACKENDS -
1119                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1120                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1121                                                         (cc_rb_backend_disable >> 16));
1122
1123         tiling_config |= BACKEND_MAP(backend_map);
1124         WREG32(GB_TILING_CONFIG, tiling_config);
1125         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1126         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1127
1128         /* Setup pipes */
1129         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1130         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1131         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1132
1133         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1134         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1135         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1136
1137         /* Setup some CP states */
1138         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1139         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1140
1141         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1142                              SYNC_WALKER | SYNC_ALIGNER));
1143         /* Setup various GPU states */
1144         if (rdev->family == CHIP_RV670)
1145                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1146
1147         tmp = RREG32(SX_DEBUG_1);
1148         tmp |= SMX_EVENT_RELEASE;
1149         if ((rdev->family > CHIP_R600))
1150                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1151         WREG32(SX_DEBUG_1, tmp);
1152
1153         if (((rdev->family) == CHIP_R600) ||
1154             ((rdev->family) == CHIP_RV630) ||
1155             ((rdev->family) == CHIP_RV610) ||
1156             ((rdev->family) == CHIP_RV620) ||
1157             ((rdev->family) == CHIP_RS780) ||
1158             ((rdev->family) == CHIP_RS880)) {
1159                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1160         } else {
1161                 WREG32(DB_DEBUG, 0);
1162         }
1163         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1164                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1165
1166         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1167         WREG32(VGT_NUM_INSTANCES, 0);
1168
1169         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1170         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1171
1172         tmp = RREG32(SQ_MS_FIFO_SIZES);
1173         if (((rdev->family) == CHIP_RV610) ||
1174             ((rdev->family) == CHIP_RV620) ||
1175             ((rdev->family) == CHIP_RS780) ||
1176             ((rdev->family) == CHIP_RS880)) {
1177                 tmp = (CACHE_FIFO_SIZE(0xa) |
1178                        FETCH_FIFO_HIWATER(0xa) |
1179                        DONE_FIFO_HIWATER(0xe0) |
1180                        ALU_UPDATE_FIFO_HIWATER(0x8));
1181         } else if (((rdev->family) == CHIP_R600) ||
1182                    ((rdev->family) == CHIP_RV630)) {
1183                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1184                 tmp |= DONE_FIFO_HIWATER(0x4);
1185         }
1186         WREG32(SQ_MS_FIFO_SIZES, tmp);
1187
1188         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1189          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1190          */
1191         sq_config = RREG32(SQ_CONFIG);
1192         sq_config &= ~(PS_PRIO(3) |
1193                        VS_PRIO(3) |
1194                        GS_PRIO(3) |
1195                        ES_PRIO(3));
1196         sq_config |= (DX9_CONSTS |
1197                       VC_ENABLE |
1198                       PS_PRIO(0) |
1199                       VS_PRIO(1) |
1200                       GS_PRIO(2) |
1201                       ES_PRIO(3));
1202
1203         if ((rdev->family) == CHIP_R600) {
1204                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1205                                           NUM_VS_GPRS(124) |
1206                                           NUM_CLAUSE_TEMP_GPRS(4));
1207                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1208                                           NUM_ES_GPRS(0));
1209                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1210                                            NUM_VS_THREADS(48) |
1211                                            NUM_GS_THREADS(4) |
1212                                            NUM_ES_THREADS(4));
1213                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1214                                             NUM_VS_STACK_ENTRIES(128));
1215                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1216                                             NUM_ES_STACK_ENTRIES(0));
1217         } else if (((rdev->family) == CHIP_RV610) ||
1218                    ((rdev->family) == CHIP_RV620) ||
1219                    ((rdev->family) == CHIP_RS780) ||
1220                    ((rdev->family) == CHIP_RS880)) {
1221                 /* no vertex cache */
1222                 sq_config &= ~VC_ENABLE;
1223
1224                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1225                                           NUM_VS_GPRS(44) |
1226                                           NUM_CLAUSE_TEMP_GPRS(2));
1227                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1228                                           NUM_ES_GPRS(17));
1229                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1230                                            NUM_VS_THREADS(78) |
1231                                            NUM_GS_THREADS(4) |
1232                                            NUM_ES_THREADS(31));
1233                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1234                                             NUM_VS_STACK_ENTRIES(40));
1235                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1236                                             NUM_ES_STACK_ENTRIES(16));
1237         } else if (((rdev->family) == CHIP_RV630) ||
1238                    ((rdev->family) == CHIP_RV635)) {
1239                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1240                                           NUM_VS_GPRS(44) |
1241                                           NUM_CLAUSE_TEMP_GPRS(2));
1242                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1243                                           NUM_ES_GPRS(18));
1244                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1245                                            NUM_VS_THREADS(78) |
1246                                            NUM_GS_THREADS(4) |
1247                                            NUM_ES_THREADS(31));
1248                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1249                                             NUM_VS_STACK_ENTRIES(40));
1250                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1251                                             NUM_ES_STACK_ENTRIES(16));
1252         } else if ((rdev->family) == CHIP_RV670) {
1253                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1254                                           NUM_VS_GPRS(44) |
1255                                           NUM_CLAUSE_TEMP_GPRS(2));
1256                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1257                                           NUM_ES_GPRS(17));
1258                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1259                                            NUM_VS_THREADS(78) |
1260                                            NUM_GS_THREADS(4) |
1261                                            NUM_ES_THREADS(31));
1262                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1263                                             NUM_VS_STACK_ENTRIES(64));
1264                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1265                                             NUM_ES_STACK_ENTRIES(64));
1266         }
1267
1268         WREG32(SQ_CONFIG, sq_config);
1269         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1270         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1271         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1272         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1273         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1274
1275         if (((rdev->family) == CHIP_RV610) ||
1276             ((rdev->family) == CHIP_RV620) ||
1277             ((rdev->family) == CHIP_RS780) ||
1278             ((rdev->family) == CHIP_RS880)) {
1279                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1280         } else {
1281                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1282         }
1283
1284         /* More default values. 2D/3D driver should adjust as needed */
1285         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1286                                          S1_X(0x4) | S1_Y(0xc)));
1287         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1288                                          S1_X(0x2) | S1_Y(0x2) |
1289                                          S2_X(0xa) | S2_Y(0x6) |
1290                                          S3_X(0x6) | S3_Y(0xa)));
1291         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1292                                              S1_X(0x4) | S1_Y(0xc) |
1293                                              S2_X(0x1) | S2_Y(0x6) |
1294                                              S3_X(0xa) | S3_Y(0xe)));
1295         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1296                                              S5_X(0x0) | S5_Y(0x0) |
1297                                              S6_X(0xb) | S6_Y(0x4) |
1298                                              S7_X(0x7) | S7_Y(0x8)));
1299
1300         WREG32(VGT_STRMOUT_EN, 0);
1301         tmp = rdev->config.r600.max_pipes * 16;
1302         switch (rdev->family) {
1303         case CHIP_RV610:
1304         case CHIP_RV620:
1305         case CHIP_RS780:
1306         case CHIP_RS880:
1307                 tmp += 32;
1308                 break;
1309         case CHIP_RV670:
1310                 tmp += 128;
1311                 break;
1312         default:
1313                 break;
1314         }
1315         if (tmp > 256) {
1316                 tmp = 256;
1317         }
1318         WREG32(VGT_ES_PER_GS, 128);
1319         WREG32(VGT_GS_PER_ES, tmp);
1320         WREG32(VGT_GS_PER_VS, 2);
1321         WREG32(VGT_GS_VERTEX_REUSE, 16);
1322
1323         /* more default values. 2D/3D driver should adjust as needed */
1324         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1325         WREG32(VGT_STRMOUT_EN, 0);
1326         WREG32(SX_MISC, 0);
1327         WREG32(PA_SC_MODE_CNTL, 0);
1328         WREG32(PA_SC_AA_CONFIG, 0);
1329         WREG32(PA_SC_LINE_STIPPLE, 0);
1330         WREG32(SPI_INPUT_Z, 0);
1331         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1332         WREG32(CB_COLOR7_FRAG, 0);
1333
1334         /* Clear render buffer base addresses */
1335         WREG32(CB_COLOR0_BASE, 0);
1336         WREG32(CB_COLOR1_BASE, 0);
1337         WREG32(CB_COLOR2_BASE, 0);
1338         WREG32(CB_COLOR3_BASE, 0);
1339         WREG32(CB_COLOR4_BASE, 0);
1340         WREG32(CB_COLOR5_BASE, 0);
1341         WREG32(CB_COLOR6_BASE, 0);
1342         WREG32(CB_COLOR7_BASE, 0);
1343         WREG32(CB_COLOR7_FRAG, 0);
1344
1345         switch (rdev->family) {
1346         case CHIP_RV610:
1347         case CHIP_RV620:
1348         case CHIP_RS780:
1349         case CHIP_RS880:
1350                 tmp = TC_L2_SIZE(8);
1351                 break;
1352         case CHIP_RV630:
1353         case CHIP_RV635:
1354                 tmp = TC_L2_SIZE(4);
1355                 break;
1356         case CHIP_R600:
1357                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1358                 break;
1359         default:
1360                 tmp = TC_L2_SIZE(0);
1361                 break;
1362         }
1363         WREG32(TC_CNTL, tmp);
1364
1365         tmp = RREG32(HDP_HOST_PATH_CNTL);
1366         WREG32(HDP_HOST_PATH_CNTL, tmp);
1367
1368         tmp = RREG32(ARB_POP);
1369         tmp |= ENABLE_TC128;
1370         WREG32(ARB_POP, tmp);
1371
1372         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1373         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1374                                NUM_CLIP_SEQ(3)));
1375         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1376 }
1377
1378
1379 /*
1380  * Indirect registers accessor
1381  */
1382 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1383 {
1384         u32 r;
1385
1386         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1387         (void)RREG32(PCIE_PORT_INDEX);
1388         r = RREG32(PCIE_PORT_DATA);
1389         return r;
1390 }
1391
1392 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1393 {
1394         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1395         (void)RREG32(PCIE_PORT_INDEX);
1396         WREG32(PCIE_PORT_DATA, (v));
1397         (void)RREG32(PCIE_PORT_DATA);
1398 }
1399
1400 /*
1401  * CP & Ring
1402  */
1403 void r600_cp_stop(struct radeon_device *rdev)
1404 {
1405         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1406 }
1407
1408 int r600_init_microcode(struct radeon_device *rdev)
1409 {
1410         struct platform_device *pdev;
1411         const char *chip_name;
1412         const char *rlc_chip_name;
1413         size_t pfp_req_size, me_req_size, rlc_req_size;
1414         char fw_name[30];
1415         int err;
1416
1417         DRM_DEBUG("\n");
1418
1419         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1420         err = IS_ERR(pdev);
1421         if (err) {
1422                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1423                 return -EINVAL;
1424         }
1425
1426         switch (rdev->family) {
1427         case CHIP_R600:
1428                 chip_name = "R600";
1429                 rlc_chip_name = "R600";
1430                 break;
1431         case CHIP_RV610:
1432                 chip_name = "RV610";
1433                 rlc_chip_name = "R600";
1434                 break;
1435         case CHIP_RV630:
1436                 chip_name = "RV630";
1437                 rlc_chip_name = "R600";
1438                 break;
1439         case CHIP_RV620:
1440                 chip_name = "RV620";
1441                 rlc_chip_name = "R600";
1442                 break;
1443         case CHIP_RV635:
1444                 chip_name = "RV635";
1445                 rlc_chip_name = "R600";
1446                 break;
1447         case CHIP_RV670:
1448                 chip_name = "RV670";
1449                 rlc_chip_name = "R600";
1450                 break;
1451         case CHIP_RS780:
1452         case CHIP_RS880:
1453                 chip_name = "RS780";
1454                 rlc_chip_name = "R600";
1455                 break;
1456         case CHIP_RV770:
1457                 chip_name = "RV770";
1458                 rlc_chip_name = "R700";
1459                 break;
1460         case CHIP_RV730:
1461         case CHIP_RV740:
1462                 chip_name = "RV730";
1463                 rlc_chip_name = "R700";
1464                 break;
1465         case CHIP_RV710:
1466                 chip_name = "RV710";
1467                 rlc_chip_name = "R700";
1468                 break;
1469         case CHIP_CEDAR:
1470                 chip_name = "CEDAR";
1471                 rlc_chip_name = "CEDAR";
1472                 break;
1473         case CHIP_REDWOOD:
1474                 chip_name = "REDWOOD";
1475                 rlc_chip_name = "REDWOOD";
1476                 break;
1477         case CHIP_JUNIPER:
1478                 chip_name = "JUNIPER";
1479                 rlc_chip_name = "JUNIPER";
1480                 break;
1481         case CHIP_CYPRESS:
1482         case CHIP_HEMLOCK:
1483                 chip_name = "CYPRESS";
1484                 rlc_chip_name = "CYPRESS";
1485                 break;
1486         default: BUG();
1487         }
1488
1489         if (rdev->family >= CHIP_CEDAR) {
1490                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1491                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
1492                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
1493         } else if (rdev->family >= CHIP_RV770) {
1494                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1495                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1496                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1497         } else {
1498                 pfp_req_size = PFP_UCODE_SIZE * 4;
1499                 me_req_size = PM4_UCODE_SIZE * 12;
1500                 rlc_req_size = RLC_UCODE_SIZE * 4;
1501         }
1502
1503         DRM_INFO("Loading %s Microcode\n", chip_name);
1504
1505         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1506         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1507         if (err)
1508                 goto out;
1509         if (rdev->pfp_fw->size != pfp_req_size) {
1510                 printk(KERN_ERR
1511                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1512                        rdev->pfp_fw->size, fw_name);
1513                 err = -EINVAL;
1514                 goto out;
1515         }
1516
1517         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1518         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1519         if (err)
1520                 goto out;
1521         if (rdev->me_fw->size != me_req_size) {
1522                 printk(KERN_ERR
1523                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1524                        rdev->me_fw->size, fw_name);
1525                 err = -EINVAL;
1526         }
1527
1528         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1529         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1530         if (err)
1531                 goto out;
1532         if (rdev->rlc_fw->size != rlc_req_size) {
1533                 printk(KERN_ERR
1534                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1535                        rdev->rlc_fw->size, fw_name);
1536                 err = -EINVAL;
1537         }
1538
1539 out:
1540         platform_device_unregister(pdev);
1541
1542         if (err) {
1543                 if (err != -EINVAL)
1544                         printk(KERN_ERR
1545                                "r600_cp: Failed to load firmware \"%s\"\n",
1546                                fw_name);
1547                 release_firmware(rdev->pfp_fw);
1548                 rdev->pfp_fw = NULL;
1549                 release_firmware(rdev->me_fw);
1550                 rdev->me_fw = NULL;
1551                 release_firmware(rdev->rlc_fw);
1552                 rdev->rlc_fw = NULL;
1553         }
1554         return err;
1555 }
1556
1557 static int r600_cp_load_microcode(struct radeon_device *rdev)
1558 {
1559         const __be32 *fw_data;
1560         int i;
1561
1562         if (!rdev->me_fw || !rdev->pfp_fw)
1563                 return -EINVAL;
1564
1565         r600_cp_stop(rdev);
1566
1567         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1568
1569         /* Reset cp */
1570         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1571         RREG32(GRBM_SOFT_RESET);
1572         mdelay(15);
1573         WREG32(GRBM_SOFT_RESET, 0);
1574
1575         WREG32(CP_ME_RAM_WADDR, 0);
1576
1577         fw_data = (const __be32 *)rdev->me_fw->data;
1578         WREG32(CP_ME_RAM_WADDR, 0);
1579         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1580                 WREG32(CP_ME_RAM_DATA,
1581                        be32_to_cpup(fw_data++));
1582
1583         fw_data = (const __be32 *)rdev->pfp_fw->data;
1584         WREG32(CP_PFP_UCODE_ADDR, 0);
1585         for (i = 0; i < PFP_UCODE_SIZE; i++)
1586                 WREG32(CP_PFP_UCODE_DATA,
1587                        be32_to_cpup(fw_data++));
1588
1589         WREG32(CP_PFP_UCODE_ADDR, 0);
1590         WREG32(CP_ME_RAM_WADDR, 0);
1591         WREG32(CP_ME_RAM_RADDR, 0);
1592         return 0;
1593 }
1594
1595 int r600_cp_start(struct radeon_device *rdev)
1596 {
1597         int r;
1598         uint32_t cp_me;
1599
1600         r = radeon_ring_lock(rdev, 7);
1601         if (r) {
1602                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1603                 return r;
1604         }
1605         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1606         radeon_ring_write(rdev, 0x1);
1607         if (rdev->family >= CHIP_CEDAR) {
1608                 radeon_ring_write(rdev, 0x0);
1609                 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1610         } else if (rdev->family >= CHIP_RV770) {
1611                 radeon_ring_write(rdev, 0x0);
1612                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1613         } else {
1614                 radeon_ring_write(rdev, 0x3);
1615                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1616         }
1617         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1618         radeon_ring_write(rdev, 0);
1619         radeon_ring_write(rdev, 0);
1620         radeon_ring_unlock_commit(rdev);
1621
1622         cp_me = 0xff;
1623         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1624         return 0;
1625 }
1626
1627 int r600_cp_resume(struct radeon_device *rdev)
1628 {
1629         u32 tmp;
1630         u32 rb_bufsz;
1631         int r;
1632
1633         /* Reset cp */
1634         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1635         RREG32(GRBM_SOFT_RESET);
1636         mdelay(15);
1637         WREG32(GRBM_SOFT_RESET, 0);
1638
1639         /* Set ring buffer size */
1640         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1641         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1642 #ifdef __BIG_ENDIAN
1643         tmp |= BUF_SWAP_32BIT;
1644 #endif
1645         WREG32(CP_RB_CNTL, tmp);
1646         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1647
1648         /* Set the write pointer delay */
1649         WREG32(CP_RB_WPTR_DELAY, 0);
1650
1651         /* Initialize the ring buffer's read and write pointers */
1652         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1653         WREG32(CP_RB_RPTR_WR, 0);
1654         WREG32(CP_RB_WPTR, 0);
1655         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1656         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1657         mdelay(1);
1658         WREG32(CP_RB_CNTL, tmp);
1659
1660         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1661         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1662
1663         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1664         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1665
1666         r600_cp_start(rdev);
1667         rdev->cp.ready = true;
1668         r = radeon_ring_test(rdev);
1669         if (r) {
1670                 rdev->cp.ready = false;
1671                 return r;
1672         }
1673         return 0;
1674 }
1675
1676 void r600_cp_commit(struct radeon_device *rdev)
1677 {
1678         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1679         (void)RREG32(CP_RB_WPTR);
1680 }
1681
1682 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1683 {
1684         u32 rb_bufsz;
1685
1686         /* Align ring size */
1687         rb_bufsz = drm_order(ring_size / 8);
1688         ring_size = (1 << (rb_bufsz + 1)) * 4;
1689         rdev->cp.ring_size = ring_size;
1690         rdev->cp.align_mask = 16 - 1;
1691 }
1692
1693 void r600_cp_fini(struct radeon_device *rdev)
1694 {
1695         r600_cp_stop(rdev);
1696         radeon_ring_fini(rdev);
1697 }
1698
1699
1700 /*
1701  * GPU scratch registers helpers function.
1702  */
1703 void r600_scratch_init(struct radeon_device *rdev)
1704 {
1705         int i;
1706
1707         rdev->scratch.num_reg = 7;
1708         for (i = 0; i < rdev->scratch.num_reg; i++) {
1709                 rdev->scratch.free[i] = true;
1710                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1711         }
1712 }
1713
1714 int r600_ring_test(struct radeon_device *rdev)
1715 {
1716         uint32_t scratch;
1717         uint32_t tmp = 0;
1718         unsigned i;
1719         int r;
1720
1721         r = radeon_scratch_get(rdev, &scratch);
1722         if (r) {
1723                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1724                 return r;
1725         }
1726         WREG32(scratch, 0xCAFEDEAD);
1727         r = radeon_ring_lock(rdev, 3);
1728         if (r) {
1729                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1730                 radeon_scratch_free(rdev, scratch);
1731                 return r;
1732         }
1733         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1734         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1735         radeon_ring_write(rdev, 0xDEADBEEF);
1736         radeon_ring_unlock_commit(rdev);
1737         for (i = 0; i < rdev->usec_timeout; i++) {
1738                 tmp = RREG32(scratch);
1739                 if (tmp == 0xDEADBEEF)
1740                         break;
1741                 DRM_UDELAY(1);
1742         }
1743         if (i < rdev->usec_timeout) {
1744                 DRM_INFO("ring test succeeded in %d usecs\n", i);
1745         } else {
1746                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1747                           scratch, tmp);
1748                 r = -EINVAL;
1749         }
1750         radeon_scratch_free(rdev, scratch);
1751         return r;
1752 }
1753
1754 void r600_wb_disable(struct radeon_device *rdev)
1755 {
1756         int r;
1757
1758         WREG32(SCRATCH_UMSK, 0);
1759         if (rdev->wb.wb_obj) {
1760                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1761                 if (unlikely(r != 0))
1762                         return;
1763                 radeon_bo_kunmap(rdev->wb.wb_obj);
1764                 radeon_bo_unpin(rdev->wb.wb_obj);
1765                 radeon_bo_unreserve(rdev->wb.wb_obj);
1766         }
1767 }
1768
1769 void r600_wb_fini(struct radeon_device *rdev)
1770 {
1771         r600_wb_disable(rdev);
1772         if (rdev->wb.wb_obj) {
1773                 radeon_bo_unref(&rdev->wb.wb_obj);
1774                 rdev->wb.wb = NULL;
1775                 rdev->wb.wb_obj = NULL;
1776         }
1777 }
1778
1779 int r600_wb_enable(struct radeon_device *rdev)
1780 {
1781         int r;
1782
1783         if (rdev->wb.wb_obj == NULL) {
1784                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1785                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1786                 if (r) {
1787                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1788                         return r;
1789                 }
1790                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1791                 if (unlikely(r != 0)) {
1792                         r600_wb_fini(rdev);
1793                         return r;
1794                 }
1795                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1796                                 &rdev->wb.gpu_addr);
1797                 if (r) {
1798                         radeon_bo_unreserve(rdev->wb.wb_obj);
1799                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1800                         r600_wb_fini(rdev);
1801                         return r;
1802                 }
1803                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1804                 radeon_bo_unreserve(rdev->wb.wb_obj);
1805                 if (r) {
1806                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1807                         r600_wb_fini(rdev);
1808                         return r;
1809                 }
1810         }
1811         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1812         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1813         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1814         WREG32(SCRATCH_UMSK, 0xff);
1815         return 0;
1816 }
1817
1818 void r600_fence_ring_emit(struct radeon_device *rdev,
1819                           struct radeon_fence *fence)
1820 {
1821         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
1822
1823         radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
1824         radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
1825         /* wait for 3D idle clean */
1826         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1827         radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1828         radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
1829         /* Emit fence sequence & fire IRQ */
1830         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1831         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1832         radeon_ring_write(rdev, fence->seq);
1833         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1834         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1835         radeon_ring_write(rdev, RB_INT_STAT);
1836 }
1837
1838 int r600_copy_blit(struct radeon_device *rdev,
1839                    uint64_t src_offset, uint64_t dst_offset,
1840                    unsigned num_pages, struct radeon_fence *fence)
1841 {
1842         int r;
1843
1844         mutex_lock(&rdev->r600_blit.mutex);
1845         rdev->r600_blit.vb_ib = NULL;
1846         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1847         if (r) {
1848                 if (rdev->r600_blit.vb_ib)
1849                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1850                 mutex_unlock(&rdev->r600_blit.mutex);
1851                 return r;
1852         }
1853         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1854         r600_blit_done_copy(rdev, fence);
1855         mutex_unlock(&rdev->r600_blit.mutex);
1856         return 0;
1857 }
1858
1859 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1860                          uint32_t tiling_flags, uint32_t pitch,
1861                          uint32_t offset, uint32_t obj_size)
1862 {
1863         /* FIXME: implement */
1864         return 0;
1865 }
1866
1867 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1868 {
1869         /* FIXME: implement */
1870 }
1871
1872
1873 bool r600_card_posted(struct radeon_device *rdev)
1874 {
1875         uint32_t reg;
1876
1877         /* first check CRTCs */
1878         reg = RREG32(D1CRTC_CONTROL) |
1879                 RREG32(D2CRTC_CONTROL);
1880         if (reg & CRTC_EN)
1881                 return true;
1882
1883         /* then check MEM_SIZE, in case the crtcs are off */
1884         if (RREG32(CONFIG_MEMSIZE))
1885                 return true;
1886
1887         return false;
1888 }
1889
1890 int r600_startup(struct radeon_device *rdev)
1891 {
1892         int r;
1893
1894         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1895                 r = r600_init_microcode(rdev);
1896                 if (r) {
1897                         DRM_ERROR("Failed to load firmware!\n");
1898                         return r;
1899                 }
1900         }
1901
1902         r600_mc_program(rdev);
1903         if (rdev->flags & RADEON_IS_AGP) {
1904                 r600_agp_enable(rdev);
1905         } else {
1906                 r = r600_pcie_gart_enable(rdev);
1907                 if (r)
1908                         return r;
1909         }
1910         r600_gpu_init(rdev);
1911         r = r600_blit_init(rdev);
1912         if (r) {
1913                 r600_blit_fini(rdev);
1914                 rdev->asic->copy = NULL;
1915                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1916         }
1917         /* pin copy shader into vram */
1918         if (rdev->r600_blit.shader_obj) {
1919                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1920                 if (unlikely(r != 0))
1921                         return r;
1922                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1923                                 &rdev->r600_blit.shader_gpu_addr);
1924                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1925                 if (r) {
1926                         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1927                         return r;
1928                 }
1929         }
1930         /* Enable IRQ */
1931         r = r600_irq_init(rdev);
1932         if (r) {
1933                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1934                 radeon_irq_kms_fini(rdev);
1935                 return r;
1936         }
1937         r600_irq_set(rdev);
1938
1939         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1940         if (r)
1941                 return r;
1942         r = r600_cp_load_microcode(rdev);
1943         if (r)
1944                 return r;
1945         r = r600_cp_resume(rdev);
1946         if (r)
1947                 return r;
1948         /* write back buffer are not vital so don't worry about failure */
1949         r600_wb_enable(rdev);
1950         return 0;
1951 }
1952
1953 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1954 {
1955         uint32_t temp;
1956
1957         temp = RREG32(CONFIG_CNTL);
1958         if (state == false) {
1959                 temp &= ~(1<<0);
1960                 temp |= (1<<1);
1961         } else {
1962                 temp &= ~(1<<1);
1963         }
1964         WREG32(CONFIG_CNTL, temp);
1965 }
1966
1967 int r600_resume(struct radeon_device *rdev)
1968 {
1969         int r;
1970
1971         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1972          * posting will perform necessary task to bring back GPU into good
1973          * shape.
1974          */
1975         /* post card */
1976         atom_asic_init(rdev->mode_info.atom_context);
1977         /* Initialize clocks */
1978         r = radeon_clocks_init(rdev);
1979         if (r) {
1980                 return r;
1981         }
1982
1983         r = r600_startup(rdev);
1984         if (r) {
1985                 DRM_ERROR("r600 startup failed on resume\n");
1986                 return r;
1987         }
1988
1989         r = r600_ib_test(rdev);
1990         if (r) {
1991                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1992                 return r;
1993         }
1994
1995         r = r600_audio_init(rdev);
1996         if (r) {
1997                 DRM_ERROR("radeon: audio resume failed\n");
1998                 return r;
1999         }
2000
2001         return r;
2002 }
2003
2004 int r600_suspend(struct radeon_device *rdev)
2005 {
2006         int r;
2007
2008         r600_audio_fini(rdev);
2009         /* FIXME: we should wait for ring to be empty */
2010         r600_cp_stop(rdev);
2011         rdev->cp.ready = false;
2012         r600_irq_suspend(rdev);
2013         r600_wb_disable(rdev);
2014         r600_pcie_gart_disable(rdev);
2015         /* unpin shaders bo */
2016         if (rdev->r600_blit.shader_obj) {
2017                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2018                 if (!r) {
2019                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2020                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2021                 }
2022         }
2023         return 0;
2024 }
2025
2026 /* Plan is to move initialization in that function and use
2027  * helper function so that radeon_device_init pretty much
2028  * do nothing more than calling asic specific function. This
2029  * should also allow to remove a bunch of callback function
2030  * like vram_info.
2031  */
2032 int r600_init(struct radeon_device *rdev)
2033 {
2034         int r;
2035
2036         r = radeon_dummy_page_init(rdev);
2037         if (r)
2038                 return r;
2039         if (r600_debugfs_mc_info_init(rdev)) {
2040                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2041         }
2042         /* This don't do much */
2043         r = radeon_gem_init(rdev);
2044         if (r)
2045                 return r;
2046         /* Read BIOS */
2047         if (!radeon_get_bios(rdev)) {
2048                 if (ASIC_IS_AVIVO(rdev))
2049                         return -EINVAL;
2050         }
2051         /* Must be an ATOMBIOS */
2052         if (!rdev->is_atom_bios) {
2053                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2054                 return -EINVAL;
2055         }
2056         r = radeon_atombios_init(rdev);
2057         if (r)
2058                 return r;
2059         /* Post card if necessary */
2060         if (!r600_card_posted(rdev)) {
2061                 if (!rdev->bios) {
2062                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2063                         return -EINVAL;
2064                 }
2065                 DRM_INFO("GPU not posted. posting now...\n");
2066                 atom_asic_init(rdev->mode_info.atom_context);
2067         }
2068         /* Initialize scratch registers */
2069         r600_scratch_init(rdev);
2070         /* Initialize surface registers */
2071         radeon_surface_init(rdev);
2072         /* Initialize clocks */
2073         radeon_get_clock_info(rdev->ddev);
2074         r = radeon_clocks_init(rdev);
2075         if (r)
2076                 return r;
2077         /* Initialize power management */
2078         radeon_pm_init(rdev);
2079         /* Fence driver */
2080         r = radeon_fence_driver_init(rdev);
2081         if (r)
2082                 return r;
2083         if (rdev->flags & RADEON_IS_AGP) {
2084                 r = radeon_agp_init(rdev);
2085                 if (r)
2086                         radeon_agp_disable(rdev);
2087         }
2088         r = r600_mc_init(rdev);
2089         if (r)
2090                 return r;
2091         /* Memory manager */
2092         r = radeon_bo_init(rdev);
2093         if (r)
2094                 return r;
2095
2096         r = radeon_irq_kms_init(rdev);
2097         if (r)
2098                 return r;
2099
2100         rdev->cp.ring_obj = NULL;
2101         r600_ring_init(rdev, 1024 * 1024);
2102
2103         rdev->ih.ring_obj = NULL;
2104         r600_ih_ring_init(rdev, 64 * 1024);
2105
2106         r = r600_pcie_gart_init(rdev);
2107         if (r)
2108                 return r;
2109
2110         rdev->accel_working = true;
2111         r = r600_startup(rdev);
2112         if (r) {
2113                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2114                 r600_cp_fini(rdev);
2115                 r600_wb_fini(rdev);
2116                 r600_irq_fini(rdev);
2117                 radeon_irq_kms_fini(rdev);
2118                 r600_pcie_gart_fini(rdev);
2119                 rdev->accel_working = false;
2120         }
2121         if (rdev->accel_working) {
2122                 r = radeon_ib_pool_init(rdev);
2123                 if (r) {
2124                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2125                         rdev->accel_working = false;
2126                 } else {
2127                         r = r600_ib_test(rdev);
2128                         if (r) {
2129                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2130                                 rdev->accel_working = false;
2131                         }
2132                 }
2133         }
2134
2135         r = r600_audio_init(rdev);
2136         if (r)
2137                 return r; /* TODO error handling */
2138         return 0;
2139 }
2140
2141 void r600_fini(struct radeon_device *rdev)
2142 {
2143         radeon_pm_fini(rdev);
2144         r600_audio_fini(rdev);
2145         r600_blit_fini(rdev);
2146         r600_cp_fini(rdev);
2147         r600_wb_fini(rdev);
2148         r600_irq_fini(rdev);
2149         radeon_irq_kms_fini(rdev);
2150         r600_pcie_gart_fini(rdev);
2151         radeon_agp_fini(rdev);
2152         radeon_gem_fini(rdev);
2153         radeon_fence_driver_fini(rdev);
2154         radeon_clocks_fini(rdev);
2155         radeon_bo_fini(rdev);
2156         radeon_atombios_fini(rdev);
2157         kfree(rdev->bios);
2158         rdev->bios = NULL;
2159         radeon_dummy_page_fini(rdev);
2160 }
2161
2162
2163 /*
2164  * CS stuff
2165  */
2166 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2167 {
2168         /* FIXME: implement */
2169         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2170         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2171         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2172         radeon_ring_write(rdev, ib->length_dw);
2173 }
2174
2175 int r600_ib_test(struct radeon_device *rdev)
2176 {
2177         struct radeon_ib *ib;
2178         uint32_t scratch;
2179         uint32_t tmp = 0;
2180         unsigned i;
2181         int r;
2182
2183         r = radeon_scratch_get(rdev, &scratch);
2184         if (r) {
2185                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2186                 return r;
2187         }
2188         WREG32(scratch, 0xCAFEDEAD);
2189         r = radeon_ib_get(rdev, &ib);
2190         if (r) {
2191                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2192                 return r;
2193         }
2194         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2195         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2196         ib->ptr[2] = 0xDEADBEEF;
2197         ib->ptr[3] = PACKET2(0);
2198         ib->ptr[4] = PACKET2(0);
2199         ib->ptr[5] = PACKET2(0);
2200         ib->ptr[6] = PACKET2(0);
2201         ib->ptr[7] = PACKET2(0);
2202         ib->ptr[8] = PACKET2(0);
2203         ib->ptr[9] = PACKET2(0);
2204         ib->ptr[10] = PACKET2(0);
2205         ib->ptr[11] = PACKET2(0);
2206         ib->ptr[12] = PACKET2(0);
2207         ib->ptr[13] = PACKET2(0);
2208         ib->ptr[14] = PACKET2(0);
2209         ib->ptr[15] = PACKET2(0);
2210         ib->length_dw = 16;
2211         r = radeon_ib_schedule(rdev, ib);
2212         if (r) {
2213                 radeon_scratch_free(rdev, scratch);
2214                 radeon_ib_free(rdev, &ib);
2215                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2216                 return r;
2217         }
2218         r = radeon_fence_wait(ib->fence, false);
2219         if (r) {
2220                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2221                 return r;
2222         }
2223         for (i = 0; i < rdev->usec_timeout; i++) {
2224                 tmp = RREG32(scratch);
2225                 if (tmp == 0xDEADBEEF)
2226                         break;
2227                 DRM_UDELAY(1);
2228         }
2229         if (i < rdev->usec_timeout) {
2230                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2231         } else {
2232                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2233                           scratch, tmp);
2234                 r = -EINVAL;
2235         }
2236         radeon_scratch_free(rdev, scratch);
2237         radeon_ib_free(rdev, &ib);
2238         return r;
2239 }
2240
2241 /*
2242  * Interrupts
2243  *
2244  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2245  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2246  * writing to the ring and the GPU consuming, the GPU writes to the ring
2247  * and host consumes.  As the host irq handler processes interrupts, it
2248  * increments the rptr.  When the rptr catches up with the wptr, all the
2249  * current interrupts have been processed.
2250  */
2251
2252 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2253 {
2254         u32 rb_bufsz;
2255
2256         /* Align ring size */
2257         rb_bufsz = drm_order(ring_size / 4);
2258         ring_size = (1 << rb_bufsz) * 4;
2259         rdev->ih.ring_size = ring_size;
2260         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2261         rdev->ih.rptr = 0;
2262 }
2263
2264 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2265 {
2266         int r;
2267
2268         /* Allocate ring buffer */
2269         if (rdev->ih.ring_obj == NULL) {
2270                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2271                                      true,
2272                                      RADEON_GEM_DOMAIN_GTT,
2273                                      &rdev->ih.ring_obj);
2274                 if (r) {
2275                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2276                         return r;
2277                 }
2278                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2279                 if (unlikely(r != 0))
2280                         return r;
2281                 r = radeon_bo_pin(rdev->ih.ring_obj,
2282                                   RADEON_GEM_DOMAIN_GTT,
2283                                   &rdev->ih.gpu_addr);
2284                 if (r) {
2285                         radeon_bo_unreserve(rdev->ih.ring_obj);
2286                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2287                         return r;
2288                 }
2289                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2290                                    (void **)&rdev->ih.ring);
2291                 radeon_bo_unreserve(rdev->ih.ring_obj);
2292                 if (r) {
2293                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2294                         return r;
2295                 }
2296         }
2297         return 0;
2298 }
2299
2300 static void r600_ih_ring_fini(struct radeon_device *rdev)
2301 {
2302         int r;
2303         if (rdev->ih.ring_obj) {
2304                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2305                 if (likely(r == 0)) {
2306                         radeon_bo_kunmap(rdev->ih.ring_obj);
2307                         radeon_bo_unpin(rdev->ih.ring_obj);
2308                         radeon_bo_unreserve(rdev->ih.ring_obj);
2309                 }
2310                 radeon_bo_unref(&rdev->ih.ring_obj);
2311                 rdev->ih.ring = NULL;
2312                 rdev->ih.ring_obj = NULL;
2313         }
2314 }
2315
2316 void r600_rlc_stop(struct radeon_device *rdev)
2317 {
2318
2319         if ((rdev->family >= CHIP_RV770) &&
2320             (rdev->family <= CHIP_RV740)) {
2321                 /* r7xx asics need to soft reset RLC before halting */
2322                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2323                 RREG32(SRBM_SOFT_RESET);
2324                 udelay(15000);
2325                 WREG32(SRBM_SOFT_RESET, 0);
2326                 RREG32(SRBM_SOFT_RESET);
2327         }
2328
2329         WREG32(RLC_CNTL, 0);
2330 }
2331
2332 static void r600_rlc_start(struct radeon_device *rdev)
2333 {
2334         WREG32(RLC_CNTL, RLC_ENABLE);
2335 }
2336
2337 static int r600_rlc_init(struct radeon_device *rdev)
2338 {
2339         u32 i;
2340         const __be32 *fw_data;
2341
2342         if (!rdev->rlc_fw)
2343                 return -EINVAL;
2344
2345         r600_rlc_stop(rdev);
2346
2347         WREG32(RLC_HB_BASE, 0);
2348         WREG32(RLC_HB_CNTL, 0);
2349         WREG32(RLC_HB_RPTR, 0);
2350         WREG32(RLC_HB_WPTR, 0);
2351         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2352         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2353         WREG32(RLC_MC_CNTL, 0);
2354         WREG32(RLC_UCODE_CNTL, 0);
2355
2356         fw_data = (const __be32 *)rdev->rlc_fw->data;
2357         if (rdev->family >= CHIP_CEDAR) {
2358                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2359                         WREG32(RLC_UCODE_ADDR, i);
2360                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2361                 }
2362         } else if (rdev->family >= CHIP_RV770) {
2363                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2364                         WREG32(RLC_UCODE_ADDR, i);
2365                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2366                 }
2367         } else {
2368                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2369                         WREG32(RLC_UCODE_ADDR, i);
2370                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2371                 }
2372         }
2373         WREG32(RLC_UCODE_ADDR, 0);
2374
2375         r600_rlc_start(rdev);
2376
2377         return 0;
2378 }
2379
2380 static void r600_enable_interrupts(struct radeon_device *rdev)
2381 {
2382         u32 ih_cntl = RREG32(IH_CNTL);
2383         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2384
2385         ih_cntl |= ENABLE_INTR;
2386         ih_rb_cntl |= IH_RB_ENABLE;
2387         WREG32(IH_CNTL, ih_cntl);
2388         WREG32(IH_RB_CNTL, ih_rb_cntl);
2389         rdev->ih.enabled = true;
2390 }
2391
2392 void r600_disable_interrupts(struct radeon_device *rdev)
2393 {
2394         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2395         u32 ih_cntl = RREG32(IH_CNTL);
2396
2397         ih_rb_cntl &= ~IH_RB_ENABLE;
2398         ih_cntl &= ~ENABLE_INTR;
2399         WREG32(IH_RB_CNTL, ih_rb_cntl);
2400         WREG32(IH_CNTL, ih_cntl);
2401         /* set rptr, wptr to 0 */
2402         WREG32(IH_RB_RPTR, 0);
2403         WREG32(IH_RB_WPTR, 0);
2404         rdev->ih.enabled = false;
2405         rdev->ih.wptr = 0;
2406         rdev->ih.rptr = 0;
2407 }
2408
2409 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2410 {
2411         u32 tmp;
2412
2413         WREG32(CP_INT_CNTL, 0);
2414         WREG32(GRBM_INT_CNTL, 0);
2415         WREG32(DxMODE_INT_MASK, 0);
2416         if (ASIC_IS_DCE3(rdev)) {
2417                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2418                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2419                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2420                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2421                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2422                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2423                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2424                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2425                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2426                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2427                 if (ASIC_IS_DCE32(rdev)) {
2428                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2429                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2430                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2431                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2432                 }
2433         } else {
2434                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2435                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2436                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2437                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2438                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2439                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2440                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2441                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2442         }
2443 }
2444
2445 int r600_irq_init(struct radeon_device *rdev)
2446 {
2447         int ret = 0;
2448         int rb_bufsz;
2449         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2450
2451         /* allocate ring */
2452         ret = r600_ih_ring_alloc(rdev);
2453         if (ret)
2454                 return ret;
2455
2456         /* disable irqs */
2457         r600_disable_interrupts(rdev);
2458
2459         /* init rlc */
2460         ret = r600_rlc_init(rdev);
2461         if (ret) {
2462                 r600_ih_ring_fini(rdev);
2463                 return ret;
2464         }
2465
2466         /* setup interrupt control */
2467         /* set dummy read address to ring address */
2468         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2469         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2470         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2471          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2472          */
2473         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2474         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2475         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2476         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2477
2478         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2479         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2480
2481         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2482                       IH_WPTR_OVERFLOW_CLEAR |
2483                       (rb_bufsz << 1));
2484         /* WPTR writeback, not yet */
2485         /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2486         WREG32(IH_RB_WPTR_ADDR_LO, 0);
2487         WREG32(IH_RB_WPTR_ADDR_HI, 0);
2488
2489         WREG32(IH_RB_CNTL, ih_rb_cntl);
2490
2491         /* set rptr, wptr to 0 */
2492         WREG32(IH_RB_RPTR, 0);
2493         WREG32(IH_RB_WPTR, 0);
2494
2495         /* Default settings for IH_CNTL (disabled at first) */
2496         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2497         /* RPTR_REARM only works if msi's are enabled */
2498         if (rdev->msi_enabled)
2499                 ih_cntl |= RPTR_REARM;
2500
2501 #ifdef __BIG_ENDIAN
2502         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2503 #endif
2504         WREG32(IH_CNTL, ih_cntl);
2505
2506         /* force the active interrupt state to all disabled */
2507         if (rdev->family >= CHIP_CEDAR)
2508                 evergreen_disable_interrupt_state(rdev);
2509         else
2510                 r600_disable_interrupt_state(rdev);
2511
2512         /* enable irqs */
2513         r600_enable_interrupts(rdev);
2514
2515         return ret;
2516 }
2517
2518 void r600_irq_suspend(struct radeon_device *rdev)
2519 {
2520         r600_irq_disable(rdev);
2521         r600_rlc_stop(rdev);
2522 }
2523
2524 void r600_irq_fini(struct radeon_device *rdev)
2525 {
2526         r600_irq_suspend(rdev);
2527         r600_ih_ring_fini(rdev);
2528 }
2529
2530 int r600_irq_set(struct radeon_device *rdev)
2531 {
2532         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2533         u32 mode_int = 0;
2534         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2535
2536         if (!rdev->irq.installed) {
2537                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2538                 return -EINVAL;
2539         }
2540         /* don't enable anything if the ih is disabled */
2541         if (!rdev->ih.enabled) {
2542                 r600_disable_interrupts(rdev);
2543                 /* force the active interrupt state to all disabled */
2544                 r600_disable_interrupt_state(rdev);
2545                 return 0;
2546         }
2547
2548         if (ASIC_IS_DCE3(rdev)) {
2549                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2550                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2551                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2552                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2553                 if (ASIC_IS_DCE32(rdev)) {
2554                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2555                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2556                 }
2557         } else {
2558                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2559                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2560                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2561         }
2562
2563         if (rdev->irq.sw_int) {
2564                 DRM_DEBUG("r600_irq_set: sw int\n");
2565                 cp_int_cntl |= RB_INT_ENABLE;
2566         }
2567         if (rdev->irq.crtc_vblank_int[0]) {
2568                 DRM_DEBUG("r600_irq_set: vblank 0\n");
2569                 mode_int |= D1MODE_VBLANK_INT_MASK;
2570         }
2571         if (rdev->irq.crtc_vblank_int[1]) {
2572                 DRM_DEBUG("r600_irq_set: vblank 1\n");
2573                 mode_int |= D2MODE_VBLANK_INT_MASK;
2574         }
2575         if (rdev->irq.hpd[0]) {
2576                 DRM_DEBUG("r600_irq_set: hpd 1\n");
2577                 hpd1 |= DC_HPDx_INT_EN;
2578         }
2579         if (rdev->irq.hpd[1]) {
2580                 DRM_DEBUG("r600_irq_set: hpd 2\n");
2581                 hpd2 |= DC_HPDx_INT_EN;
2582         }
2583         if (rdev->irq.hpd[2]) {
2584                 DRM_DEBUG("r600_irq_set: hpd 3\n");
2585                 hpd3 |= DC_HPDx_INT_EN;
2586         }
2587         if (rdev->irq.hpd[3]) {
2588                 DRM_DEBUG("r600_irq_set: hpd 4\n");
2589                 hpd4 |= DC_HPDx_INT_EN;
2590         }
2591         if (rdev->irq.hpd[4]) {
2592                 DRM_DEBUG("r600_irq_set: hpd 5\n");
2593                 hpd5 |= DC_HPDx_INT_EN;
2594         }
2595         if (rdev->irq.hpd[5]) {
2596                 DRM_DEBUG("r600_irq_set: hpd 6\n");
2597                 hpd6 |= DC_HPDx_INT_EN;
2598         }
2599
2600         WREG32(CP_INT_CNTL, cp_int_cntl);
2601         WREG32(DxMODE_INT_MASK, mode_int);
2602         if (ASIC_IS_DCE3(rdev)) {
2603                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2604                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2605                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2606                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2607                 if (ASIC_IS_DCE32(rdev)) {
2608                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2609                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2610                 }
2611         } else {
2612                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2613                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2614                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2615         }
2616
2617         return 0;
2618 }
2619
2620 static inline void r600_irq_ack(struct radeon_device *rdev,
2621                                 u32 *disp_int,
2622                                 u32 *disp_int_cont,
2623                                 u32 *disp_int_cont2)
2624 {
2625         u32 tmp;
2626
2627         if (ASIC_IS_DCE3(rdev)) {
2628                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2629                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2630                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2631         } else {
2632                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2633                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2634                 *disp_int_cont2 = 0;
2635         }
2636
2637         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2638                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2639         if (*disp_int & LB_D1_VLINE_INTERRUPT)
2640                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2641         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2642                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2643         if (*disp_int & LB_D2_VLINE_INTERRUPT)
2644                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2645         if (*disp_int & DC_HPD1_INTERRUPT) {
2646                 if (ASIC_IS_DCE3(rdev)) {
2647                         tmp = RREG32(DC_HPD1_INT_CONTROL);
2648                         tmp |= DC_HPDx_INT_ACK;
2649                         WREG32(DC_HPD1_INT_CONTROL, tmp);
2650                 } else {
2651                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2652                         tmp |= DC_HPDx_INT_ACK;
2653                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2654                 }
2655         }
2656         if (*disp_int & DC_HPD2_INTERRUPT) {
2657                 if (ASIC_IS_DCE3(rdev)) {
2658                         tmp = RREG32(DC_HPD2_INT_CONTROL);
2659                         tmp |= DC_HPDx_INT_ACK;
2660                         WREG32(DC_HPD2_INT_CONTROL, tmp);
2661                 } else {
2662                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2663                         tmp |= DC_HPDx_INT_ACK;
2664                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2665                 }
2666         }
2667         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2668                 if (ASIC_IS_DCE3(rdev)) {
2669                         tmp = RREG32(DC_HPD3_INT_CONTROL);
2670                         tmp |= DC_HPDx_INT_ACK;
2671                         WREG32(DC_HPD3_INT_CONTROL, tmp);
2672                 } else {
2673                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2674                         tmp |= DC_HPDx_INT_ACK;
2675                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2676                 }
2677         }
2678         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2679                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2680                 tmp |= DC_HPDx_INT_ACK;
2681                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2682         }
2683         if (ASIC_IS_DCE32(rdev)) {
2684                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2685                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2686                         tmp |= DC_HPDx_INT_ACK;
2687                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2688                 }
2689                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2690                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2691                         tmp |= DC_HPDx_INT_ACK;
2692                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2693                 }
2694         }
2695 }
2696
2697 void r600_irq_disable(struct radeon_device *rdev)
2698 {
2699         u32 disp_int, disp_int_cont, disp_int_cont2;
2700
2701         r600_disable_interrupts(rdev);
2702         /* Wait and acknowledge irq */
2703         mdelay(1);
2704         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2705         r600_disable_interrupt_state(rdev);
2706 }
2707
2708 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2709 {
2710         u32 wptr, tmp;
2711
2712         /* XXX use writeback */
2713         wptr = RREG32(IH_RB_WPTR);
2714
2715         if (wptr & RB_OVERFLOW) {
2716                 /* When a ring buffer overflow happen start parsing interrupt
2717                  * from the last not overwritten vector (wptr + 16). Hopefully
2718                  * this should allow us to catchup.
2719                  */
2720                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2721                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2722                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2723                 tmp = RREG32(IH_RB_CNTL);
2724                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2725                 WREG32(IH_RB_CNTL, tmp);
2726         }
2727         return (wptr & rdev->ih.ptr_mask);
2728 }
2729
2730 /*        r600 IV Ring
2731  * Each IV ring entry is 128 bits:
2732  * [7:0]    - interrupt source id
2733  * [31:8]   - reserved
2734  * [59:32]  - interrupt source data
2735  * [127:60]  - reserved
2736  *
2737  * The basic interrupt vector entries
2738  * are decoded as follows:
2739  * src_id  src_data  description
2740  *      1         0  D1 Vblank
2741  *      1         1  D1 Vline
2742  *      5         0  D2 Vblank
2743  *      5         1  D2 Vline
2744  *     19         0  FP Hot plug detection A
2745  *     19         1  FP Hot plug detection B
2746  *     19         2  DAC A auto-detection
2747  *     19         3  DAC B auto-detection
2748  *    176         -  CP_INT RB
2749  *    177         -  CP_INT IB1
2750  *    178         -  CP_INT IB2
2751  *    181         -  EOP Interrupt
2752  *    233         -  GUI Idle
2753  *
2754  * Note, these are based on r600 and may need to be
2755  * adjusted or added to on newer asics
2756  */
2757
2758 int r600_irq_process(struct radeon_device *rdev)
2759 {
2760         u32 wptr = r600_get_ih_wptr(rdev);
2761         u32 rptr = rdev->ih.rptr;
2762         u32 src_id, src_data;
2763         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2764         unsigned long flags;
2765         bool queue_hotplug = false;
2766
2767         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2768         if (!rdev->ih.enabled)
2769                 return IRQ_NONE;
2770
2771         spin_lock_irqsave(&rdev->ih.lock, flags);
2772
2773         if (rptr == wptr) {
2774                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2775                 return IRQ_NONE;
2776         }
2777         if (rdev->shutdown) {
2778                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2779                 return IRQ_NONE;
2780         }
2781
2782 restart_ih:
2783         /* display interrupts */
2784         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2785
2786         rdev->ih.wptr = wptr;
2787         while (rptr != wptr) {
2788                 /* wptr/rptr are in bytes! */
2789                 ring_index = rptr / 4;
2790                 src_id =  rdev->ih.ring[ring_index] & 0xff;
2791                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2792
2793                 switch (src_id) {
2794                 case 1: /* D1 vblank/vline */
2795                         switch (src_data) {
2796                         case 0: /* D1 vblank */
2797                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2798                                         drm_handle_vblank(rdev->ddev, 0);
2799                                         rdev->pm.vblank_sync = true;
2800                                         wake_up(&rdev->irq.vblank_queue);
2801                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2802                                         DRM_DEBUG("IH: D1 vblank\n");
2803                                 }
2804                                 break;
2805                         case 1: /* D1 vline */
2806                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2807                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
2808                                         DRM_DEBUG("IH: D1 vline\n");
2809                                 }
2810                                 break;
2811                         default:
2812                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2813                                 break;
2814                         }
2815                         break;
2816                 case 5: /* D2 vblank/vline */
2817                         switch (src_data) {
2818                         case 0: /* D2 vblank */
2819                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2820                                         drm_handle_vblank(rdev->ddev, 1);
2821                                         rdev->pm.vblank_sync = true;
2822                                         wake_up(&rdev->irq.vblank_queue);
2823                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2824                                         DRM_DEBUG("IH: D2 vblank\n");
2825                                 }
2826                                 break;
2827                         case 1: /* D1 vline */
2828                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2829                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
2830                                         DRM_DEBUG("IH: D2 vline\n");
2831                                 }
2832                                 break;
2833                         default:
2834                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2835                                 break;
2836                         }
2837                         break;
2838                 case 19: /* HPD/DAC hotplug */
2839                         switch (src_data) {
2840                         case 0:
2841                                 if (disp_int & DC_HPD1_INTERRUPT) {
2842                                         disp_int &= ~DC_HPD1_INTERRUPT;
2843                                         queue_hotplug = true;
2844                                         DRM_DEBUG("IH: HPD1\n");
2845                                 }
2846                                 break;
2847                         case 1:
2848                                 if (disp_int & DC_HPD2_INTERRUPT) {
2849                                         disp_int &= ~DC_HPD2_INTERRUPT;
2850                                         queue_hotplug = true;
2851                                         DRM_DEBUG("IH: HPD2\n");
2852                                 }
2853                                 break;
2854                         case 4:
2855                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2856                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
2857                                         queue_hotplug = true;
2858                                         DRM_DEBUG("IH: HPD3\n");
2859                                 }
2860                                 break;
2861                         case 5:
2862                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2863                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
2864                                         queue_hotplug = true;
2865                                         DRM_DEBUG("IH: HPD4\n");
2866                                 }
2867                                 break;
2868                         case 10:
2869                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2870                                         disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
2871                                         queue_hotplug = true;
2872                                         DRM_DEBUG("IH: HPD5\n");
2873                                 }
2874                                 break;
2875                         case 12:
2876                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2877                                         disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
2878                                         queue_hotplug = true;
2879                                         DRM_DEBUG("IH: HPD6\n");
2880                                 }
2881                                 break;
2882                         default:
2883                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2884                                 break;
2885                         }
2886                         break;
2887                 case 176: /* CP_INT in ring buffer */
2888                 case 177: /* CP_INT in IB1 */
2889                 case 178: /* CP_INT in IB2 */
2890                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2891                         radeon_fence_process(rdev);
2892                         break;
2893                 case 181: /* CP EOP event */
2894                         DRM_DEBUG("IH: CP EOP\n");
2895                         break;
2896                 default:
2897                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2898                         break;
2899                 }
2900
2901                 /* wptr/rptr are in bytes! */
2902                 rptr += 16;
2903                 rptr &= rdev->ih.ptr_mask;
2904         }
2905         /* make sure wptr hasn't changed while processing */
2906         wptr = r600_get_ih_wptr(rdev);
2907         if (wptr != rdev->ih.wptr)
2908                 goto restart_ih;
2909         if (queue_hotplug)
2910                 queue_work(rdev->wq, &rdev->hotplug_work);
2911         rdev->ih.rptr = rptr;
2912         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2913         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2914         return IRQ_HANDLED;
2915 }
2916
2917 /*
2918  * Debugfs info
2919  */
2920 #if defined(CONFIG_DEBUG_FS)
2921
2922 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2923 {
2924         struct drm_info_node *node = (struct drm_info_node *) m->private;
2925         struct drm_device *dev = node->minor->dev;
2926         struct radeon_device *rdev = dev->dev_private;
2927         unsigned count, i, j;
2928
2929         radeon_ring_free_size(rdev);
2930         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2931         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2932         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2933         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2934         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2935         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2936         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2937         seq_printf(m, "%u dwords in ring\n", count);
2938         i = rdev->cp.rptr;
2939         for (j = 0; j <= count; j++) {
2940                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2941                 i = (i + 1) & rdev->cp.ptr_mask;
2942         }
2943         return 0;
2944 }
2945
2946 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2947 {
2948         struct drm_info_node *node = (struct drm_info_node *) m->private;
2949         struct drm_device *dev = node->minor->dev;
2950         struct radeon_device *rdev = dev->dev_private;
2951
2952         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2953         DREG32_SYS(m, rdev, VM_L2_STATUS);
2954         return 0;
2955 }
2956
2957 static struct drm_info_list r600_mc_info_list[] = {
2958         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2959         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2960 };
2961 #endif
2962
2963 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2964 {
2965 #if defined(CONFIG_DEBUG_FS)
2966         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2967 #else
2968         return 0;
2969 #endif
2970 }
2971
2972 /**
2973  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2974  * rdev: radeon device structure
2975  * bo: buffer object struct which userspace is waiting for idle
2976  *
2977  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2978  * through ring buffer, this leads to corruption in rendering, see
2979  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2980  * directly perform HDP flush by writing register through MMIO.
2981  */
2982 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2983 {
2984         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2985 }