cbf49f4f408ed01b885e21741d08edb2b0ccfac3
[pandora-kernel.git] / drivers / gpu / drm / radeon / r100.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "r100d.h"
37 #include "rs100d.h"
38 #include "rv200d.h"
39 #include "rv250d.h"
40 #include "atom.h"
41
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
44 #include <linux/module.h>
45
46 #include "r100_reg_safe.h"
47 #include "rn50_reg_safe.h"
48
49 /* Firmware Names */
50 #define FIRMWARE_R100           "radeon/R100_cp.bin"
51 #define FIRMWARE_R200           "radeon/R200_cp.bin"
52 #define FIRMWARE_R300           "radeon/R300_cp.bin"
53 #define FIRMWARE_R420           "radeon/R420_cp.bin"
54 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
55 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
56 #define FIRMWARE_R520           "radeon/R520_cp.bin"
57
58 MODULE_FIRMWARE(FIRMWARE_R100);
59 MODULE_FIRMWARE(FIRMWARE_R200);
60 MODULE_FIRMWARE(FIRMWARE_R300);
61 MODULE_FIRMWARE(FIRMWARE_R420);
62 MODULE_FIRMWARE(FIRMWARE_RS690);
63 MODULE_FIRMWARE(FIRMWARE_RS600);
64 MODULE_FIRMWARE(FIRMWARE_R520);
65
66 #include "r100_track.h"
67
68 /* This files gather functions specifics to:
69  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
70  */
71
72 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
73                             struct radeon_cs_packet *pkt,
74                             unsigned idx,
75                             unsigned reg)
76 {
77         int r;
78         u32 tile_flags = 0;
79         u32 tmp;
80         struct radeon_cs_reloc *reloc;
81         u32 value;
82
83         r = r100_cs_packet_next_reloc(p, &reloc);
84         if (r) {
85                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
86                           idx, reg);
87                 r100_cs_dump_packet(p, pkt);
88                 return r;
89         }
90         value = radeon_get_ib_value(p, idx);
91         tmp = value & 0x003fffff;
92         tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
93
94         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
95                 tile_flags |= RADEON_DST_TILE_MACRO;
96         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
97                 if (reg == RADEON_SRC_PITCH_OFFSET) {
98                         DRM_ERROR("Cannot src blit from microtiled surface\n");
99                         r100_cs_dump_packet(p, pkt);
100                         return -EINVAL;
101                 }
102                 tile_flags |= RADEON_DST_TILE_MICRO;
103         }
104
105         tmp |= tile_flags;
106         p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
107         return 0;
108 }
109
110 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
111                              struct radeon_cs_packet *pkt,
112                              int idx)
113 {
114         unsigned c, i;
115         struct radeon_cs_reloc *reloc;
116         struct r100_cs_track *track;
117         int r = 0;
118         volatile uint32_t *ib;
119         u32 idx_value;
120
121         ib = p->ib->ptr;
122         track = (struct r100_cs_track *)p->track;
123         c = radeon_get_ib_value(p, idx++) & 0x1F;
124         if (c > 16) {
125             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
126                       pkt->opcode);
127             r100_cs_dump_packet(p, pkt);
128             return -EINVAL;
129         }
130         track->num_arrays = c;
131         for (i = 0; i < (c - 1); i+=2, idx+=3) {
132                 r = r100_cs_packet_next_reloc(p, &reloc);
133                 if (r) {
134                         DRM_ERROR("No reloc for packet3 %d\n",
135                                   pkt->opcode);
136                         r100_cs_dump_packet(p, pkt);
137                         return r;
138                 }
139                 idx_value = radeon_get_ib_value(p, idx);
140                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
141
142                 track->arrays[i + 0].esize = idx_value >> 8;
143                 track->arrays[i + 0].robj = reloc->robj;
144                 track->arrays[i + 0].esize &= 0x7F;
145                 r = r100_cs_packet_next_reloc(p, &reloc);
146                 if (r) {
147                         DRM_ERROR("No reloc for packet3 %d\n",
148                                   pkt->opcode);
149                         r100_cs_dump_packet(p, pkt);
150                         return r;
151                 }
152                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
153                 track->arrays[i + 1].robj = reloc->robj;
154                 track->arrays[i + 1].esize = idx_value >> 24;
155                 track->arrays[i + 1].esize &= 0x7F;
156         }
157         if (c & 1) {
158                 r = r100_cs_packet_next_reloc(p, &reloc);
159                 if (r) {
160                         DRM_ERROR("No reloc for packet3 %d\n",
161                                           pkt->opcode);
162                         r100_cs_dump_packet(p, pkt);
163                         return r;
164                 }
165                 idx_value = radeon_get_ib_value(p, idx);
166                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
167                 track->arrays[i + 0].robj = reloc->robj;
168                 track->arrays[i + 0].esize = idx_value >> 8;
169                 track->arrays[i + 0].esize &= 0x7F;
170         }
171         return r;
172 }
173
174 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
175 {
176         /* enable the pflip int */
177         radeon_irq_kms_pflip_irq_get(rdev, crtc);
178 }
179
180 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
181 {
182         /* disable the pflip int */
183         radeon_irq_kms_pflip_irq_put(rdev, crtc);
184 }
185
186 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
187 {
188         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
189         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
190
191         /* Lock the graphics update lock */
192         /* update the scanout addresses */
193         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
194
195         /* Wait for update_pending to go high. */
196         while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET));
197         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
198
199         /* Unlock the lock, so double-buffering can take place inside vblank */
200         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
201         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
202
203         /* Return current update_pending status: */
204         return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
205 }
206
207 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
208 {
209         int i;
210         rdev->pm.dynpm_can_upclock = true;
211         rdev->pm.dynpm_can_downclock = true;
212
213         switch (rdev->pm.dynpm_planned_action) {
214         case DYNPM_ACTION_MINIMUM:
215                 rdev->pm.requested_power_state_index = 0;
216                 rdev->pm.dynpm_can_downclock = false;
217                 break;
218         case DYNPM_ACTION_DOWNCLOCK:
219                 if (rdev->pm.current_power_state_index == 0) {
220                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
221                         rdev->pm.dynpm_can_downclock = false;
222                 } else {
223                         if (rdev->pm.active_crtc_count > 1) {
224                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
225                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
226                                                 continue;
227                                         else if (i >= rdev->pm.current_power_state_index) {
228                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
229                                                 break;
230                                         } else {
231                                                 rdev->pm.requested_power_state_index = i;
232                                                 break;
233                                         }
234                                 }
235                         } else
236                                 rdev->pm.requested_power_state_index =
237                                         rdev->pm.current_power_state_index - 1;
238                 }
239                 /* don't use the power state if crtcs are active and no display flag is set */
240                 if ((rdev->pm.active_crtc_count > 0) &&
241                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
242                      RADEON_PM_MODE_NO_DISPLAY)) {
243                         rdev->pm.requested_power_state_index++;
244                 }
245                 break;
246         case DYNPM_ACTION_UPCLOCK:
247                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
248                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
249                         rdev->pm.dynpm_can_upclock = false;
250                 } else {
251                         if (rdev->pm.active_crtc_count > 1) {
252                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
253                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
254                                                 continue;
255                                         else if (i <= rdev->pm.current_power_state_index) {
256                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
257                                                 break;
258                                         } else {
259                                                 rdev->pm.requested_power_state_index = i;
260                                                 break;
261                                         }
262                                 }
263                         } else
264                                 rdev->pm.requested_power_state_index =
265                                         rdev->pm.current_power_state_index + 1;
266                 }
267                 break;
268         case DYNPM_ACTION_DEFAULT:
269                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
270                 rdev->pm.dynpm_can_upclock = false;
271                 break;
272         case DYNPM_ACTION_NONE:
273         default:
274                 DRM_ERROR("Requested mode for not defined action\n");
275                 return;
276         }
277         /* only one clock mode per power state */
278         rdev->pm.requested_clock_mode_index = 0;
279
280         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
281                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
282                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
283                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
284                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
285                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
286                   pcie_lanes);
287 }
288
289 void r100_pm_init_profile(struct radeon_device *rdev)
290 {
291         /* default */
292         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
293         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
294         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
295         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
296         /* low sh */
297         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
298         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
299         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
300         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
301         /* mid sh */
302         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
303         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
304         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
305         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
306         /* high sh */
307         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
308         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
309         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
310         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
311         /* low mh */
312         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
313         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
314         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
315         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
316         /* mid mh */
317         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
318         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
319         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
320         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
321         /* high mh */
322         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
323         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
324         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
325         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
326 }
327
328 void r100_pm_misc(struct radeon_device *rdev)
329 {
330         int requested_index = rdev->pm.requested_power_state_index;
331         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
332         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
333         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
334
335         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
336                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
337                         tmp = RREG32(voltage->gpio.reg);
338                         if (voltage->active_high)
339                                 tmp |= voltage->gpio.mask;
340                         else
341                                 tmp &= ~(voltage->gpio.mask);
342                         WREG32(voltage->gpio.reg, tmp);
343                         if (voltage->delay)
344                                 udelay(voltage->delay);
345                 } else {
346                         tmp = RREG32(voltage->gpio.reg);
347                         if (voltage->active_high)
348                                 tmp &= ~voltage->gpio.mask;
349                         else
350                                 tmp |= voltage->gpio.mask;
351                         WREG32(voltage->gpio.reg, tmp);
352                         if (voltage->delay)
353                                 udelay(voltage->delay);
354                 }
355         }
356
357         sclk_cntl = RREG32_PLL(SCLK_CNTL);
358         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
359         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
360         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
361         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
362         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
363                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
364                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
365                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
366                 else
367                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
368                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
369                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
370                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
371                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
372         } else
373                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
374
375         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
376                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
377                 if (voltage->delay) {
378                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
379                         switch (voltage->delay) {
380                         case 33:
381                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
382                                 break;
383                         case 66:
384                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
385                                 break;
386                         case 99:
387                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
388                                 break;
389                         case 132:
390                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
391                                 break;
392                         }
393                 } else
394                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
395         } else
396                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
397
398         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
399                 sclk_cntl &= ~FORCE_HDP;
400         else
401                 sclk_cntl |= FORCE_HDP;
402
403         WREG32_PLL(SCLK_CNTL, sclk_cntl);
404         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
405         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
406
407         /* set pcie lanes */
408         if ((rdev->flags & RADEON_IS_PCIE) &&
409             !(rdev->flags & RADEON_IS_IGP) &&
410             rdev->asic->set_pcie_lanes &&
411             (ps->pcie_lanes !=
412              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
413                 radeon_set_pcie_lanes(rdev,
414                                       ps->pcie_lanes);
415                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
416         }
417 }
418
419 void r100_pm_prepare(struct radeon_device *rdev)
420 {
421         struct drm_device *ddev = rdev->ddev;
422         struct drm_crtc *crtc;
423         struct radeon_crtc *radeon_crtc;
424         u32 tmp;
425
426         /* disable any active CRTCs */
427         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
428                 radeon_crtc = to_radeon_crtc(crtc);
429                 if (radeon_crtc->enabled) {
430                         if (radeon_crtc->crtc_id) {
431                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
432                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
433                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
434                         } else {
435                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
436                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
437                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
438                         }
439                 }
440         }
441 }
442
443 void r100_pm_finish(struct radeon_device *rdev)
444 {
445         struct drm_device *ddev = rdev->ddev;
446         struct drm_crtc *crtc;
447         struct radeon_crtc *radeon_crtc;
448         u32 tmp;
449
450         /* enable any active CRTCs */
451         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
452                 radeon_crtc = to_radeon_crtc(crtc);
453                 if (radeon_crtc->enabled) {
454                         if (radeon_crtc->crtc_id) {
455                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
456                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
457                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
458                         } else {
459                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
460                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
461                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
462                         }
463                 }
464         }
465 }
466
467 bool r100_gui_idle(struct radeon_device *rdev)
468 {
469         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
470                 return false;
471         else
472                 return true;
473 }
474
475 /* hpd for digital panel detect/disconnect */
476 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
477 {
478         bool connected = false;
479
480         switch (hpd) {
481         case RADEON_HPD_1:
482                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
483                         connected = true;
484                 break;
485         case RADEON_HPD_2:
486                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
487                         connected = true;
488                 break;
489         default:
490                 break;
491         }
492         return connected;
493 }
494
495 void r100_hpd_set_polarity(struct radeon_device *rdev,
496                            enum radeon_hpd_id hpd)
497 {
498         u32 tmp;
499         bool connected = r100_hpd_sense(rdev, hpd);
500
501         switch (hpd) {
502         case RADEON_HPD_1:
503                 tmp = RREG32(RADEON_FP_GEN_CNTL);
504                 if (connected)
505                         tmp &= ~RADEON_FP_DETECT_INT_POL;
506                 else
507                         tmp |= RADEON_FP_DETECT_INT_POL;
508                 WREG32(RADEON_FP_GEN_CNTL, tmp);
509                 break;
510         case RADEON_HPD_2:
511                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
512                 if (connected)
513                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
514                 else
515                         tmp |= RADEON_FP2_DETECT_INT_POL;
516                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
517                 break;
518         default:
519                 break;
520         }
521 }
522
523 void r100_hpd_init(struct radeon_device *rdev)
524 {
525         struct drm_device *dev = rdev->ddev;
526         struct drm_connector *connector;
527
528         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
529                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
530                 switch (radeon_connector->hpd.hpd) {
531                 case RADEON_HPD_1:
532                         rdev->irq.hpd[0] = true;
533                         break;
534                 case RADEON_HPD_2:
535                         rdev->irq.hpd[1] = true;
536                         break;
537                 default:
538                         break;
539                 }
540         }
541         if (rdev->irq.installed)
542                 r100_irq_set(rdev);
543 }
544
545 void r100_hpd_fini(struct radeon_device *rdev)
546 {
547         struct drm_device *dev = rdev->ddev;
548         struct drm_connector *connector;
549
550         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
551                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
552                 switch (radeon_connector->hpd.hpd) {
553                 case RADEON_HPD_1:
554                         rdev->irq.hpd[0] = false;
555                         break;
556                 case RADEON_HPD_2:
557                         rdev->irq.hpd[1] = false;
558                         break;
559                 default:
560                         break;
561                 }
562         }
563 }
564
565 /*
566  * PCI GART
567  */
568 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
569 {
570         /* TODO: can we do somethings here ? */
571         /* It seems hw only cache one entry so we should discard this
572          * entry otherwise if first GPU GART read hit this entry it
573          * could end up in wrong address. */
574 }
575
576 int r100_pci_gart_init(struct radeon_device *rdev)
577 {
578         int r;
579
580         if (rdev->gart.table.ram.ptr) {
581                 WARN(1, "R100 PCI GART already initialized\n");
582                 return 0;
583         }
584         /* Initialize common gart structure */
585         r = radeon_gart_init(rdev);
586         if (r)
587                 return r;
588         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
589         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
590         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
591         return radeon_gart_table_ram_alloc(rdev);
592 }
593
594 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
595 void r100_enable_bm(struct radeon_device *rdev)
596 {
597         uint32_t tmp;
598         /* Enable bus mastering */
599         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
600         WREG32(RADEON_BUS_CNTL, tmp);
601 }
602
603 int r100_pci_gart_enable(struct radeon_device *rdev)
604 {
605         uint32_t tmp;
606
607         radeon_gart_restore(rdev);
608         /* discard memory request outside of configured range */
609         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
610         WREG32(RADEON_AIC_CNTL, tmp);
611         /* set address range for PCI address translate */
612         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
613         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
614         /* set PCI GART page-table base address */
615         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
616         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
617         WREG32(RADEON_AIC_CNTL, tmp);
618         r100_pci_gart_tlb_flush(rdev);
619         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
620                  (unsigned)(rdev->mc.gtt_size >> 20),
621                  (unsigned long long)rdev->gart.table_addr);
622         rdev->gart.ready = true;
623         return 0;
624 }
625
626 void r100_pci_gart_disable(struct radeon_device *rdev)
627 {
628         uint32_t tmp;
629
630         /* discard memory request outside of configured range */
631         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
632         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
633         WREG32(RADEON_AIC_LO_ADDR, 0);
634         WREG32(RADEON_AIC_HI_ADDR, 0);
635 }
636
637 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
638 {
639         if (i < 0 || i > rdev->gart.num_gpu_pages) {
640                 return -EINVAL;
641         }
642         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
643         return 0;
644 }
645
646 void r100_pci_gart_fini(struct radeon_device *rdev)
647 {
648         radeon_gart_fini(rdev);
649         r100_pci_gart_disable(rdev);
650         radeon_gart_table_ram_free(rdev);
651 }
652
653 int r100_irq_set(struct radeon_device *rdev)
654 {
655         uint32_t tmp = 0;
656
657         if (!rdev->irq.installed) {
658                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
659                 WREG32(R_000040_GEN_INT_CNTL, 0);
660                 return -EINVAL;
661         }
662         if (rdev->irq.sw_int) {
663                 tmp |= RADEON_SW_INT_ENABLE;
664         }
665         if (rdev->irq.gui_idle) {
666                 tmp |= RADEON_GUI_IDLE_MASK;
667         }
668         if (rdev->irq.crtc_vblank_int[0] ||
669             rdev->irq.pflip[0]) {
670                 tmp |= RADEON_CRTC_VBLANK_MASK;
671         }
672         if (rdev->irq.crtc_vblank_int[1] ||
673             rdev->irq.pflip[1]) {
674                 tmp |= RADEON_CRTC2_VBLANK_MASK;
675         }
676         if (rdev->irq.hpd[0]) {
677                 tmp |= RADEON_FP_DETECT_MASK;
678         }
679         if (rdev->irq.hpd[1]) {
680                 tmp |= RADEON_FP2_DETECT_MASK;
681         }
682         WREG32(RADEON_GEN_INT_CNTL, tmp);
683         return 0;
684 }
685
686 void r100_irq_disable(struct radeon_device *rdev)
687 {
688         u32 tmp;
689
690         WREG32(R_000040_GEN_INT_CNTL, 0);
691         /* Wait and acknowledge irq */
692         mdelay(1);
693         tmp = RREG32(R_000044_GEN_INT_STATUS);
694         WREG32(R_000044_GEN_INT_STATUS, tmp);
695 }
696
697 static uint32_t r100_irq_ack(struct radeon_device *rdev)
698 {
699         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
700         uint32_t irq_mask = RADEON_SW_INT_TEST |
701                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
702                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
703
704         /* the interrupt works, but the status bit is permanently asserted */
705         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
706                 if (!rdev->irq.gui_idle_acked)
707                         irq_mask |= RADEON_GUI_IDLE_STAT;
708         }
709
710         if (irqs) {
711                 WREG32(RADEON_GEN_INT_STATUS, irqs);
712         }
713         return irqs & irq_mask;
714 }
715
716 int r100_irq_process(struct radeon_device *rdev)
717 {
718         uint32_t status, msi_rearm;
719         bool queue_hotplug = false;
720
721         /* reset gui idle ack.  the status bit is broken */
722         rdev->irq.gui_idle_acked = false;
723
724         status = r100_irq_ack(rdev);
725         if (!status) {
726                 return IRQ_NONE;
727         }
728         if (rdev->shutdown) {
729                 return IRQ_NONE;
730         }
731         while (status) {
732                 /* SW interrupt */
733                 if (status & RADEON_SW_INT_TEST) {
734                         radeon_fence_process(rdev);
735                 }
736                 /* gui idle interrupt */
737                 if (status & RADEON_GUI_IDLE_STAT) {
738                         rdev->irq.gui_idle_acked = true;
739                         rdev->pm.gui_idle = true;
740                         wake_up(&rdev->irq.idle_queue);
741                 }
742                 /* Vertical blank interrupts */
743                 if (status & RADEON_CRTC_VBLANK_STAT) {
744                         if (rdev->irq.crtc_vblank_int[0]) {
745                                 drm_handle_vblank(rdev->ddev, 0);
746                                 rdev->pm.vblank_sync = true;
747                                 wake_up(&rdev->irq.vblank_queue);
748                         }
749                         if (rdev->irq.pflip[0])
750                                 radeon_crtc_handle_flip(rdev, 0);
751                 }
752                 if (status & RADEON_CRTC2_VBLANK_STAT) {
753                         if (rdev->irq.crtc_vblank_int[1]) {
754                                 drm_handle_vblank(rdev->ddev, 1);
755                                 rdev->pm.vblank_sync = true;
756                                 wake_up(&rdev->irq.vblank_queue);
757                         }
758                         if (rdev->irq.pflip[1])
759                                 radeon_crtc_handle_flip(rdev, 1);
760                 }
761                 if (status & RADEON_FP_DETECT_STAT) {
762                         queue_hotplug = true;
763                         DRM_DEBUG("HPD1\n");
764                 }
765                 if (status & RADEON_FP2_DETECT_STAT) {
766                         queue_hotplug = true;
767                         DRM_DEBUG("HPD2\n");
768                 }
769                 status = r100_irq_ack(rdev);
770         }
771         /* reset gui idle ack.  the status bit is broken */
772         rdev->irq.gui_idle_acked = false;
773         if (queue_hotplug)
774                 schedule_work(&rdev->hotplug_work);
775         if (rdev->msi_enabled) {
776                 switch (rdev->family) {
777                 case CHIP_RS400:
778                 case CHIP_RS480:
779                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
780                         WREG32(RADEON_AIC_CNTL, msi_rearm);
781                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
782                         break;
783                 default:
784                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
785                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
786                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
787                         break;
788                 }
789         }
790         return IRQ_HANDLED;
791 }
792
793 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
794 {
795         if (crtc == 0)
796                 return RREG32(RADEON_CRTC_CRNT_FRAME);
797         else
798                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
799 }
800
801 /* Who ever call radeon_fence_emit should call ring_lock and ask
802  * for enough space (today caller are ib schedule and buffer move) */
803 void r100_fence_ring_emit(struct radeon_device *rdev,
804                           struct radeon_fence *fence)
805 {
806         /* We have to make sure that caches are flushed before
807          * CPU might read something from VRAM. */
808         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
809         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
810         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
811         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
812         /* Wait until IDLE & CLEAN */
813         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
814         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
815         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
816         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
817                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
818         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
819         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
820         /* Emit fence sequence & fire IRQ */
821         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
822         radeon_ring_write(rdev, fence->seq);
823         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
824         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
825 }
826
827 int r100_copy_blit(struct radeon_device *rdev,
828                    uint64_t src_offset,
829                    uint64_t dst_offset,
830                    unsigned num_gpu_pages,
831                    struct radeon_fence *fence)
832 {
833         uint32_t cur_pages;
834         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
835         uint32_t pitch;
836         uint32_t stride_pixels;
837         unsigned ndw;
838         int num_loops;
839         int r = 0;
840
841         /* radeon limited to 16k stride */
842         stride_bytes &= 0x3fff;
843         /* radeon pitch is /64 */
844         pitch = stride_bytes / 64;
845         stride_pixels = stride_bytes / 4;
846         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
847
848         /* Ask for enough room for blit + flush + fence */
849         ndw = 64 + (10 * num_loops);
850         r = radeon_ring_lock(rdev, ndw);
851         if (r) {
852                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
853                 return -EINVAL;
854         }
855         while (num_gpu_pages > 0) {
856                 cur_pages = num_gpu_pages;
857                 if (cur_pages > 8191) {
858                         cur_pages = 8191;
859                 }
860                 num_gpu_pages -= cur_pages;
861
862                 /* pages are in Y direction - height
863                    page width in X direction - width */
864                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
865                 radeon_ring_write(rdev,
866                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
867                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
868                                   RADEON_GMC_SRC_CLIPPING |
869                                   RADEON_GMC_DST_CLIPPING |
870                                   RADEON_GMC_BRUSH_NONE |
871                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
872                                   RADEON_GMC_SRC_DATATYPE_COLOR |
873                                   RADEON_ROP3_S |
874                                   RADEON_DP_SRC_SOURCE_MEMORY |
875                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
876                                   RADEON_GMC_WR_MSK_DIS);
877                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
878                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
879                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
880                 radeon_ring_write(rdev, 0);
881                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
882                 radeon_ring_write(rdev, num_gpu_pages);
883                 radeon_ring_write(rdev, num_gpu_pages);
884                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
885         }
886         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
887         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
888         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
889         radeon_ring_write(rdev,
890                           RADEON_WAIT_2D_IDLECLEAN |
891                           RADEON_WAIT_HOST_IDLECLEAN |
892                           RADEON_WAIT_DMA_GUI_IDLE);
893         if (fence) {
894                 r = radeon_fence_emit(rdev, fence);
895         }
896         radeon_ring_unlock_commit(rdev);
897         return r;
898 }
899
900 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
901 {
902         unsigned i;
903         u32 tmp;
904
905         for (i = 0; i < rdev->usec_timeout; i++) {
906                 tmp = RREG32(R_000E40_RBBM_STATUS);
907                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
908                         return 0;
909                 }
910                 udelay(1);
911         }
912         return -1;
913 }
914
915 void r100_ring_start(struct radeon_device *rdev)
916 {
917         int r;
918
919         r = radeon_ring_lock(rdev, 2);
920         if (r) {
921                 return;
922         }
923         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
924         radeon_ring_write(rdev,
925                           RADEON_ISYNC_ANY2D_IDLE3D |
926                           RADEON_ISYNC_ANY3D_IDLE2D |
927                           RADEON_ISYNC_WAIT_IDLEGUI |
928                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
929         radeon_ring_unlock_commit(rdev);
930 }
931
932
933 /* Load the microcode for the CP */
934 static int r100_cp_init_microcode(struct radeon_device *rdev)
935 {
936         struct platform_device *pdev;
937         const char *fw_name = NULL;
938         int err;
939
940         DRM_DEBUG_KMS("\n");
941
942         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
943         err = IS_ERR(pdev);
944         if (err) {
945                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
946                 return -EINVAL;
947         }
948         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
949             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
950             (rdev->family == CHIP_RS200)) {
951                 DRM_INFO("Loading R100 Microcode\n");
952                 fw_name = FIRMWARE_R100;
953         } else if ((rdev->family == CHIP_R200) ||
954                    (rdev->family == CHIP_RV250) ||
955                    (rdev->family == CHIP_RV280) ||
956                    (rdev->family == CHIP_RS300)) {
957                 DRM_INFO("Loading R200 Microcode\n");
958                 fw_name = FIRMWARE_R200;
959         } else if ((rdev->family == CHIP_R300) ||
960                    (rdev->family == CHIP_R350) ||
961                    (rdev->family == CHIP_RV350) ||
962                    (rdev->family == CHIP_RV380) ||
963                    (rdev->family == CHIP_RS400) ||
964                    (rdev->family == CHIP_RS480)) {
965                 DRM_INFO("Loading R300 Microcode\n");
966                 fw_name = FIRMWARE_R300;
967         } else if ((rdev->family == CHIP_R420) ||
968                    (rdev->family == CHIP_R423) ||
969                    (rdev->family == CHIP_RV410)) {
970                 DRM_INFO("Loading R400 Microcode\n");
971                 fw_name = FIRMWARE_R420;
972         } else if ((rdev->family == CHIP_RS690) ||
973                    (rdev->family == CHIP_RS740)) {
974                 DRM_INFO("Loading RS690/RS740 Microcode\n");
975                 fw_name = FIRMWARE_RS690;
976         } else if (rdev->family == CHIP_RS600) {
977                 DRM_INFO("Loading RS600 Microcode\n");
978                 fw_name = FIRMWARE_RS600;
979         } else if ((rdev->family == CHIP_RV515) ||
980                    (rdev->family == CHIP_R520) ||
981                    (rdev->family == CHIP_RV530) ||
982                    (rdev->family == CHIP_R580) ||
983                    (rdev->family == CHIP_RV560) ||
984                    (rdev->family == CHIP_RV570)) {
985                 DRM_INFO("Loading R500 Microcode\n");
986                 fw_name = FIRMWARE_R520;
987         }
988
989         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
990         platform_device_unregister(pdev);
991         if (err) {
992                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
993                        fw_name);
994         } else if (rdev->me_fw->size % 8) {
995                 printk(KERN_ERR
996                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
997                        rdev->me_fw->size, fw_name);
998                 err = -EINVAL;
999                 release_firmware(rdev->me_fw);
1000                 rdev->me_fw = NULL;
1001         }
1002         return err;
1003 }
1004
1005 static void r100_cp_load_microcode(struct radeon_device *rdev)
1006 {
1007         const __be32 *fw_data;
1008         int i, size;
1009
1010         if (r100_gui_wait_for_idle(rdev)) {
1011                 printk(KERN_WARNING "Failed to wait GUI idle while "
1012                        "programming pipes. Bad things might happen.\n");
1013         }
1014
1015         if (rdev->me_fw) {
1016                 size = rdev->me_fw->size / 4;
1017                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1018                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1019                 for (i = 0; i < size; i += 2) {
1020                         WREG32(RADEON_CP_ME_RAM_DATAH,
1021                                be32_to_cpup(&fw_data[i]));
1022                         WREG32(RADEON_CP_ME_RAM_DATAL,
1023                                be32_to_cpup(&fw_data[i + 1]));
1024                 }
1025         }
1026 }
1027
1028 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1029 {
1030         unsigned rb_bufsz;
1031         unsigned rb_blksz;
1032         unsigned max_fetch;
1033         unsigned pre_write_timer;
1034         unsigned pre_write_limit;
1035         unsigned indirect2_start;
1036         unsigned indirect1_start;
1037         uint32_t tmp;
1038         int r;
1039
1040         if (r100_debugfs_cp_init(rdev)) {
1041                 DRM_ERROR("Failed to register debugfs file for CP !\n");
1042         }
1043         if (!rdev->me_fw) {
1044                 r = r100_cp_init_microcode(rdev);
1045                 if (r) {
1046                         DRM_ERROR("Failed to load firmware!\n");
1047                         return r;
1048                 }
1049         }
1050
1051         /* Align ring size */
1052         rb_bufsz = drm_order(ring_size / 8);
1053         ring_size = (1 << (rb_bufsz + 1)) * 4;
1054         r100_cp_load_microcode(rdev);
1055         r = radeon_ring_init(rdev, ring_size);
1056         if (r) {
1057                 return r;
1058         }
1059         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1060          * the rptr copy in system ram */
1061         rb_blksz = 9;
1062         /* cp will read 128bytes at a time (4 dwords) */
1063         max_fetch = 1;
1064         rdev->cp.align_mask = 16 - 1;
1065         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1066         pre_write_timer = 64;
1067         /* Force CP_RB_WPTR write if written more than one time before the
1068          * delay expire
1069          */
1070         pre_write_limit = 0;
1071         /* Setup the cp cache like this (cache size is 96 dwords) :
1072          *      RING            0  to 15
1073          *      INDIRECT1       16 to 79
1074          *      INDIRECT2       80 to 95
1075          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1076          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1077          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1078          * Idea being that most of the gpu cmd will be through indirect1 buffer
1079          * so it gets the bigger cache.
1080          */
1081         indirect2_start = 80;
1082         indirect1_start = 16;
1083         /* cp setup */
1084         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1085         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1086                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1087                REG_SET(RADEON_MAX_FETCH, max_fetch));
1088 #ifdef __BIG_ENDIAN
1089         tmp |= RADEON_BUF_SWAP_32BIT;
1090 #endif
1091         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1092
1093         /* Set ring address */
1094         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1095         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1096         /* Force read & write ptr to 0 */
1097         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1098         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1099         rdev->cp.wptr = 0;
1100         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1101
1102         /* set the wb address whether it's enabled or not */
1103         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1104                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1105         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1106
1107         if (rdev->wb.enabled)
1108                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1109         else {
1110                 tmp |= RADEON_RB_NO_UPDATE;
1111                 WREG32(R_000770_SCRATCH_UMSK, 0);
1112         }
1113
1114         WREG32(RADEON_CP_RB_CNTL, tmp);
1115         udelay(10);
1116         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1117         /* Set cp mode to bus mastering & enable cp*/
1118         WREG32(RADEON_CP_CSQ_MODE,
1119                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1120                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1121         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1122         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1123         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1124         radeon_ring_start(rdev);
1125         r = radeon_ring_test(rdev);
1126         if (r) {
1127                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1128                 return r;
1129         }
1130         rdev->cp.ready = true;
1131         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1132         return 0;
1133 }
1134
1135 void r100_cp_fini(struct radeon_device *rdev)
1136 {
1137         if (r100_cp_wait_for_idle(rdev)) {
1138                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1139         }
1140         /* Disable ring */
1141         r100_cp_disable(rdev);
1142         radeon_ring_fini(rdev);
1143         DRM_INFO("radeon: cp finalized\n");
1144 }
1145
1146 void r100_cp_disable(struct radeon_device *rdev)
1147 {
1148         /* Disable ring */
1149         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1150         rdev->cp.ready = false;
1151         WREG32(RADEON_CP_CSQ_MODE, 0);
1152         WREG32(RADEON_CP_CSQ_CNTL, 0);
1153         WREG32(R_000770_SCRATCH_UMSK, 0);
1154         if (r100_gui_wait_for_idle(rdev)) {
1155                 printk(KERN_WARNING "Failed to wait GUI idle while "
1156                        "programming pipes. Bad things might happen.\n");
1157         }
1158 }
1159
1160 void r100_cp_commit(struct radeon_device *rdev)
1161 {
1162         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1163         (void)RREG32(RADEON_CP_RB_WPTR);
1164 }
1165
1166
1167 /*
1168  * CS functions
1169  */
1170 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1171                           struct radeon_cs_packet *pkt,
1172                           const unsigned *auth, unsigned n,
1173                           radeon_packet0_check_t check)
1174 {
1175         unsigned reg;
1176         unsigned i, j, m;
1177         unsigned idx;
1178         int r;
1179
1180         idx = pkt->idx + 1;
1181         reg = pkt->reg;
1182         /* Check that register fall into register range
1183          * determined by the number of entry (n) in the
1184          * safe register bitmap.
1185          */
1186         if (pkt->one_reg_wr) {
1187                 if ((reg >> 7) > n) {
1188                         return -EINVAL;
1189                 }
1190         } else {
1191                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1192                         return -EINVAL;
1193                 }
1194         }
1195         for (i = 0; i <= pkt->count; i++, idx++) {
1196                 j = (reg >> 7);
1197                 m = 1 << ((reg >> 2) & 31);
1198                 if (auth[j] & m) {
1199                         r = check(p, pkt, idx, reg);
1200                         if (r) {
1201                                 return r;
1202                         }
1203                 }
1204                 if (pkt->one_reg_wr) {
1205                         if (!(auth[j] & m)) {
1206                                 break;
1207                         }
1208                 } else {
1209                         reg += 4;
1210                 }
1211         }
1212         return 0;
1213 }
1214
1215 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1216                          struct radeon_cs_packet *pkt)
1217 {
1218         volatile uint32_t *ib;
1219         unsigned i;
1220         unsigned idx;
1221
1222         ib = p->ib->ptr;
1223         idx = pkt->idx;
1224         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1225                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1226         }
1227 }
1228
1229 /**
1230  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1231  * @parser:     parser structure holding parsing context.
1232  * @pkt:        where to store packet informations
1233  *
1234  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1235  * if packet is bigger than remaining ib size. or if packets is unknown.
1236  **/
1237 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1238                          struct radeon_cs_packet *pkt,
1239                          unsigned idx)
1240 {
1241         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1242         uint32_t header;
1243
1244         if (idx >= ib_chunk->length_dw) {
1245                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1246                           idx, ib_chunk->length_dw);
1247                 return -EINVAL;
1248         }
1249         header = radeon_get_ib_value(p, idx);
1250         pkt->idx = idx;
1251         pkt->type = CP_PACKET_GET_TYPE(header);
1252         pkt->count = CP_PACKET_GET_COUNT(header);
1253         switch (pkt->type) {
1254         case PACKET_TYPE0:
1255                 pkt->reg = CP_PACKET0_GET_REG(header);
1256                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1257                 break;
1258         case PACKET_TYPE3:
1259                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1260                 break;
1261         case PACKET_TYPE2:
1262                 pkt->count = -1;
1263                 break;
1264         default:
1265                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1266                 return -EINVAL;
1267         }
1268         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1269                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1270                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1271                 return -EINVAL;
1272         }
1273         return 0;
1274 }
1275
1276 /**
1277  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1278  * @parser:             parser structure holding parsing context.
1279  *
1280  * Userspace sends a special sequence for VLINE waits.
1281  * PACKET0 - VLINE_START_END + value
1282  * PACKET0 - WAIT_UNTIL +_value
1283  * RELOC (P3) - crtc_id in reloc.
1284  *
1285  * This function parses this and relocates the VLINE START END
1286  * and WAIT UNTIL packets to the correct crtc.
1287  * It also detects a switched off crtc and nulls out the
1288  * wait in that case.
1289  */
1290 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1291 {
1292         struct drm_mode_object *obj;
1293         struct drm_crtc *crtc;
1294         struct radeon_crtc *radeon_crtc;
1295         struct radeon_cs_packet p3reloc, waitreloc;
1296         int crtc_id;
1297         int r;
1298         uint32_t header, h_idx, reg;
1299         volatile uint32_t *ib;
1300
1301         ib = p->ib->ptr;
1302
1303         /* parse the wait until */
1304         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1305         if (r)
1306                 return r;
1307
1308         /* check its a wait until and only 1 count */
1309         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1310             waitreloc.count != 0) {
1311                 DRM_ERROR("vline wait had illegal wait until segment\n");
1312                 return -EINVAL;
1313         }
1314
1315         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1316                 DRM_ERROR("vline wait had illegal wait until\n");
1317                 return -EINVAL;
1318         }
1319
1320         /* jump over the NOP */
1321         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1322         if (r)
1323                 return r;
1324
1325         h_idx = p->idx - 2;
1326         p->idx += waitreloc.count + 2;
1327         p->idx += p3reloc.count + 2;
1328
1329         header = radeon_get_ib_value(p, h_idx);
1330         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1331         reg = CP_PACKET0_GET_REG(header);
1332         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1333         if (!obj) {
1334                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1335                 return -EINVAL;
1336         }
1337         crtc = obj_to_crtc(obj);
1338         radeon_crtc = to_radeon_crtc(crtc);
1339         crtc_id = radeon_crtc->crtc_id;
1340
1341         if (!crtc->enabled) {
1342                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1343                 ib[h_idx + 2] = PACKET2(0);
1344                 ib[h_idx + 3] = PACKET2(0);
1345         } else if (crtc_id == 1) {
1346                 switch (reg) {
1347                 case AVIVO_D1MODE_VLINE_START_END:
1348                         header &= ~R300_CP_PACKET0_REG_MASK;
1349                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1350                         break;
1351                 case RADEON_CRTC_GUI_TRIG_VLINE:
1352                         header &= ~R300_CP_PACKET0_REG_MASK;
1353                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1354                         break;
1355                 default:
1356                         DRM_ERROR("unknown crtc reloc\n");
1357                         return -EINVAL;
1358                 }
1359                 ib[h_idx] = header;
1360                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1361         }
1362
1363         return 0;
1364 }
1365
1366 /**
1367  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1368  * @parser:             parser structure holding parsing context.
1369  * @data:               pointer to relocation data
1370  * @offset_start:       starting offset
1371  * @offset_mask:        offset mask (to align start offset on)
1372  * @reloc:              reloc informations
1373  *
1374  * Check next packet is relocation packet3, do bo validation and compute
1375  * GPU offset using the provided start.
1376  **/
1377 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1378                               struct radeon_cs_reloc **cs_reloc)
1379 {
1380         struct radeon_cs_chunk *relocs_chunk;
1381         struct radeon_cs_packet p3reloc;
1382         unsigned idx;
1383         int r;
1384
1385         if (p->chunk_relocs_idx == -1) {
1386                 DRM_ERROR("No relocation chunk !\n");
1387                 return -EINVAL;
1388         }
1389         *cs_reloc = NULL;
1390         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1391         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1392         if (r) {
1393                 return r;
1394         }
1395         p->idx += p3reloc.count + 2;
1396         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1397                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1398                           p3reloc.idx);
1399                 r100_cs_dump_packet(p, &p3reloc);
1400                 return -EINVAL;
1401         }
1402         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1403         if (idx >= relocs_chunk->length_dw) {
1404                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1405                           idx, relocs_chunk->length_dw);
1406                 r100_cs_dump_packet(p, &p3reloc);
1407                 return -EINVAL;
1408         }
1409         /* FIXME: we assume reloc size is 4 dwords */
1410         *cs_reloc = p->relocs_ptr[(idx / 4)];
1411         return 0;
1412 }
1413
1414 static int r100_get_vtx_size(uint32_t vtx_fmt)
1415 {
1416         int vtx_size;
1417         vtx_size = 2;
1418         /* ordered according to bits in spec */
1419         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1420                 vtx_size++;
1421         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1422                 vtx_size += 3;
1423         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1424                 vtx_size++;
1425         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1426                 vtx_size++;
1427         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1428                 vtx_size += 3;
1429         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1430                 vtx_size++;
1431         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1432                 vtx_size++;
1433         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1434                 vtx_size += 2;
1435         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1436                 vtx_size += 2;
1437         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1438                 vtx_size++;
1439         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1440                 vtx_size += 2;
1441         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1442                 vtx_size++;
1443         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1444                 vtx_size += 2;
1445         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1446                 vtx_size++;
1447         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1448                 vtx_size++;
1449         /* blend weight */
1450         if (vtx_fmt & (0x7 << 15))
1451                 vtx_size += (vtx_fmt >> 15) & 0x7;
1452         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1453                 vtx_size += 3;
1454         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1455                 vtx_size += 2;
1456         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1457                 vtx_size++;
1458         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1459                 vtx_size++;
1460         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1461                 vtx_size++;
1462         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1463                 vtx_size++;
1464         return vtx_size;
1465 }
1466
1467 static int r100_packet0_check(struct radeon_cs_parser *p,
1468                               struct radeon_cs_packet *pkt,
1469                               unsigned idx, unsigned reg)
1470 {
1471         struct radeon_cs_reloc *reloc;
1472         struct r100_cs_track *track;
1473         volatile uint32_t *ib;
1474         uint32_t tmp;
1475         int r;
1476         int i, face;
1477         u32 tile_flags = 0;
1478         u32 idx_value;
1479
1480         ib = p->ib->ptr;
1481         track = (struct r100_cs_track *)p->track;
1482
1483         idx_value = radeon_get_ib_value(p, idx);
1484
1485         switch (reg) {
1486         case RADEON_CRTC_GUI_TRIG_VLINE:
1487                 r = r100_cs_packet_parse_vline(p);
1488                 if (r) {
1489                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1490                                   idx, reg);
1491                         r100_cs_dump_packet(p, pkt);
1492                         return r;
1493                 }
1494                 break;
1495                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1496                  * range access */
1497         case RADEON_DST_PITCH_OFFSET:
1498         case RADEON_SRC_PITCH_OFFSET:
1499                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1500                 if (r)
1501                         return r;
1502                 break;
1503         case RADEON_RB3D_DEPTHOFFSET:
1504                 r = r100_cs_packet_next_reloc(p, &reloc);
1505                 if (r) {
1506                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1507                                   idx, reg);
1508                         r100_cs_dump_packet(p, pkt);
1509                         return r;
1510                 }
1511                 track->zb.robj = reloc->robj;
1512                 track->zb.offset = idx_value;
1513                 track->zb_dirty = true;
1514                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1515                 break;
1516         case RADEON_RB3D_COLOROFFSET:
1517                 r = r100_cs_packet_next_reloc(p, &reloc);
1518                 if (r) {
1519                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1520                                   idx, reg);
1521                         r100_cs_dump_packet(p, pkt);
1522                         return r;
1523                 }
1524                 track->cb[0].robj = reloc->robj;
1525                 track->cb[0].offset = idx_value;
1526                 track->cb_dirty = true;
1527                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1528                 break;
1529         case RADEON_PP_TXOFFSET_0:
1530         case RADEON_PP_TXOFFSET_1:
1531         case RADEON_PP_TXOFFSET_2:
1532                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1533                 r = r100_cs_packet_next_reloc(p, &reloc);
1534                 if (r) {
1535                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1536                                   idx, reg);
1537                         r100_cs_dump_packet(p, pkt);
1538                         return r;
1539                 }
1540                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1541                 track->textures[i].robj = reloc->robj;
1542                 track->tex_dirty = true;
1543                 break;
1544         case RADEON_PP_CUBIC_OFFSET_T0_0:
1545         case RADEON_PP_CUBIC_OFFSET_T0_1:
1546         case RADEON_PP_CUBIC_OFFSET_T0_2:
1547         case RADEON_PP_CUBIC_OFFSET_T0_3:
1548         case RADEON_PP_CUBIC_OFFSET_T0_4:
1549                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1550                 r = r100_cs_packet_next_reloc(p, &reloc);
1551                 if (r) {
1552                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1553                                   idx, reg);
1554                         r100_cs_dump_packet(p, pkt);
1555                         return r;
1556                 }
1557                 track->textures[0].cube_info[i].offset = idx_value;
1558                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1559                 track->textures[0].cube_info[i].robj = reloc->robj;
1560                 track->tex_dirty = true;
1561                 break;
1562         case RADEON_PP_CUBIC_OFFSET_T1_0:
1563         case RADEON_PP_CUBIC_OFFSET_T1_1:
1564         case RADEON_PP_CUBIC_OFFSET_T1_2:
1565         case RADEON_PP_CUBIC_OFFSET_T1_3:
1566         case RADEON_PP_CUBIC_OFFSET_T1_4:
1567                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1568                 r = r100_cs_packet_next_reloc(p, &reloc);
1569                 if (r) {
1570                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1571                                   idx, reg);
1572                         r100_cs_dump_packet(p, pkt);
1573                         return r;
1574                 }
1575                 track->textures[1].cube_info[i].offset = idx_value;
1576                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1577                 track->textures[1].cube_info[i].robj = reloc->robj;
1578                 track->tex_dirty = true;
1579                 break;
1580         case RADEON_PP_CUBIC_OFFSET_T2_0:
1581         case RADEON_PP_CUBIC_OFFSET_T2_1:
1582         case RADEON_PP_CUBIC_OFFSET_T2_2:
1583         case RADEON_PP_CUBIC_OFFSET_T2_3:
1584         case RADEON_PP_CUBIC_OFFSET_T2_4:
1585                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1586                 r = r100_cs_packet_next_reloc(p, &reloc);
1587                 if (r) {
1588                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1589                                   idx, reg);
1590                         r100_cs_dump_packet(p, pkt);
1591                         return r;
1592                 }
1593                 track->textures[2].cube_info[i].offset = idx_value;
1594                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1595                 track->textures[2].cube_info[i].robj = reloc->robj;
1596                 track->tex_dirty = true;
1597                 break;
1598         case RADEON_RE_WIDTH_HEIGHT:
1599                 track->maxy = ((idx_value >> 16) & 0x7FF);
1600                 track->cb_dirty = true;
1601                 track->zb_dirty = true;
1602                 break;
1603         case RADEON_RB3D_COLORPITCH:
1604                 r = r100_cs_packet_next_reloc(p, &reloc);
1605                 if (r) {
1606                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1607                                   idx, reg);
1608                         r100_cs_dump_packet(p, pkt);
1609                         return r;
1610                 }
1611
1612                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1613                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1614                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1615                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1616
1617                 tmp = idx_value & ~(0x7 << 16);
1618                 tmp |= tile_flags;
1619                 ib[idx] = tmp;
1620
1621                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1622                 track->cb_dirty = true;
1623                 break;
1624         case RADEON_RB3D_DEPTHPITCH:
1625                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1626                 track->zb_dirty = true;
1627                 break;
1628         case RADEON_RB3D_CNTL:
1629                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1630                 case 7:
1631                 case 8:
1632                 case 9:
1633                 case 11:
1634                 case 12:
1635                         track->cb[0].cpp = 1;
1636                         break;
1637                 case 3:
1638                 case 4:
1639                 case 15:
1640                         track->cb[0].cpp = 2;
1641                         break;
1642                 case 6:
1643                         track->cb[0].cpp = 4;
1644                         break;
1645                 default:
1646                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1647                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1648                         return -EINVAL;
1649                 }
1650                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1651                 track->cb_dirty = true;
1652                 track->zb_dirty = true;
1653                 break;
1654         case RADEON_RB3D_ZSTENCILCNTL:
1655                 switch (idx_value & 0xf) {
1656                 case 0:
1657                         track->zb.cpp = 2;
1658                         break;
1659                 case 2:
1660                 case 3:
1661                 case 4:
1662                 case 5:
1663                 case 9:
1664                 case 11:
1665                         track->zb.cpp = 4;
1666                         break;
1667                 default:
1668                         break;
1669                 }
1670                 track->zb_dirty = true;
1671                 break;
1672         case RADEON_RB3D_ZPASS_ADDR:
1673                 r = r100_cs_packet_next_reloc(p, &reloc);
1674                 if (r) {
1675                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1676                                   idx, reg);
1677                         r100_cs_dump_packet(p, pkt);
1678                         return r;
1679                 }
1680                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1681                 break;
1682         case RADEON_PP_CNTL:
1683                 {
1684                         uint32_t temp = idx_value >> 4;
1685                         for (i = 0; i < track->num_texture; i++)
1686                                 track->textures[i].enabled = !!(temp & (1 << i));
1687                         track->tex_dirty = true;
1688                 }
1689                 break;
1690         case RADEON_SE_VF_CNTL:
1691                 track->vap_vf_cntl = idx_value;
1692                 break;
1693         case RADEON_SE_VTX_FMT:
1694                 track->vtx_size = r100_get_vtx_size(idx_value);
1695                 break;
1696         case RADEON_PP_TEX_SIZE_0:
1697         case RADEON_PP_TEX_SIZE_1:
1698         case RADEON_PP_TEX_SIZE_2:
1699                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1700                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1701                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1702                 track->tex_dirty = true;
1703                 break;
1704         case RADEON_PP_TEX_PITCH_0:
1705         case RADEON_PP_TEX_PITCH_1:
1706         case RADEON_PP_TEX_PITCH_2:
1707                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1708                 track->textures[i].pitch = idx_value + 32;
1709                 track->tex_dirty = true;
1710                 break;
1711         case RADEON_PP_TXFILTER_0:
1712         case RADEON_PP_TXFILTER_1:
1713         case RADEON_PP_TXFILTER_2:
1714                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1715                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1716                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1717                 tmp = (idx_value >> 23) & 0x7;
1718                 if (tmp == 2 || tmp == 6)
1719                         track->textures[i].roundup_w = false;
1720                 tmp = (idx_value >> 27) & 0x7;
1721                 if (tmp == 2 || tmp == 6)
1722                         track->textures[i].roundup_h = false;
1723                 track->tex_dirty = true;
1724                 break;
1725         case RADEON_PP_TXFORMAT_0:
1726         case RADEON_PP_TXFORMAT_1:
1727         case RADEON_PP_TXFORMAT_2:
1728                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1729                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1730                         track->textures[i].use_pitch = 1;
1731                 } else {
1732                         track->textures[i].use_pitch = 0;
1733                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1734                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1735                 }
1736                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1737                         track->textures[i].tex_coord_type = 2;
1738                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1739                 case RADEON_TXFORMAT_I8:
1740                 case RADEON_TXFORMAT_RGB332:
1741                 case RADEON_TXFORMAT_Y8:
1742                         track->textures[i].cpp = 1;
1743                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1744                         break;
1745                 case RADEON_TXFORMAT_AI88:
1746                 case RADEON_TXFORMAT_ARGB1555:
1747                 case RADEON_TXFORMAT_RGB565:
1748                 case RADEON_TXFORMAT_ARGB4444:
1749                 case RADEON_TXFORMAT_VYUY422:
1750                 case RADEON_TXFORMAT_YVYU422:
1751                 case RADEON_TXFORMAT_SHADOW16:
1752                 case RADEON_TXFORMAT_LDUDV655:
1753                 case RADEON_TXFORMAT_DUDV88:
1754                         track->textures[i].cpp = 2;
1755                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1756                         break;
1757                 case RADEON_TXFORMAT_ARGB8888:
1758                 case RADEON_TXFORMAT_RGBA8888:
1759                 case RADEON_TXFORMAT_SHADOW32:
1760                 case RADEON_TXFORMAT_LDUDUV8888:
1761                         track->textures[i].cpp = 4;
1762                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1763                         break;
1764                 case RADEON_TXFORMAT_DXT1:
1765                         track->textures[i].cpp = 1;
1766                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1767                         break;
1768                 case RADEON_TXFORMAT_DXT23:
1769                 case RADEON_TXFORMAT_DXT45:
1770                         track->textures[i].cpp = 1;
1771                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1772                         break;
1773                 }
1774                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1775                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1776                 track->tex_dirty = true;
1777                 break;
1778         case RADEON_PP_CUBIC_FACES_0:
1779         case RADEON_PP_CUBIC_FACES_1:
1780         case RADEON_PP_CUBIC_FACES_2:
1781                 tmp = idx_value;
1782                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1783                 for (face = 0; face < 4; face++) {
1784                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1785                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1786                 }
1787                 track->tex_dirty = true;
1788                 break;
1789         default:
1790                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1791                        reg, idx);
1792                 return -EINVAL;
1793         }
1794         return 0;
1795 }
1796
1797 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1798                                          struct radeon_cs_packet *pkt,
1799                                          struct radeon_bo *robj)
1800 {
1801         unsigned idx;
1802         u32 value;
1803         idx = pkt->idx + 1;
1804         value = radeon_get_ib_value(p, idx + 2);
1805         if ((value + 1) > radeon_bo_size(robj)) {
1806                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1807                           "(need %u have %lu) !\n",
1808                           value + 1,
1809                           radeon_bo_size(robj));
1810                 return -EINVAL;
1811         }
1812         return 0;
1813 }
1814
1815 static int r100_packet3_check(struct radeon_cs_parser *p,
1816                               struct radeon_cs_packet *pkt)
1817 {
1818         struct radeon_cs_reloc *reloc;
1819         struct r100_cs_track *track;
1820         unsigned idx;
1821         volatile uint32_t *ib;
1822         int r;
1823
1824         ib = p->ib->ptr;
1825         idx = pkt->idx + 1;
1826         track = (struct r100_cs_track *)p->track;
1827         switch (pkt->opcode) {
1828         case PACKET3_3D_LOAD_VBPNTR:
1829                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1830                 if (r)
1831                         return r;
1832                 break;
1833         case PACKET3_INDX_BUFFER:
1834                 r = r100_cs_packet_next_reloc(p, &reloc);
1835                 if (r) {
1836                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1837                         r100_cs_dump_packet(p, pkt);
1838                         return r;
1839                 }
1840                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1841                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1842                 if (r) {
1843                         return r;
1844                 }
1845                 break;
1846         case 0x23:
1847                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1848                 r = r100_cs_packet_next_reloc(p, &reloc);
1849                 if (r) {
1850                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1851                         r100_cs_dump_packet(p, pkt);
1852                         return r;
1853                 }
1854                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1855                 track->num_arrays = 1;
1856                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1857
1858                 track->arrays[0].robj = reloc->robj;
1859                 track->arrays[0].esize = track->vtx_size;
1860
1861                 track->max_indx = radeon_get_ib_value(p, idx+1);
1862
1863                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1864                 track->immd_dwords = pkt->count - 1;
1865                 r = r100_cs_track_check(p->rdev, track);
1866                 if (r)
1867                         return r;
1868                 break;
1869         case PACKET3_3D_DRAW_IMMD:
1870                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1871                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1872                         return -EINVAL;
1873                 }
1874                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1875                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1876                 track->immd_dwords = pkt->count - 1;
1877                 r = r100_cs_track_check(p->rdev, track);
1878                 if (r)
1879                         return r;
1880                 break;
1881                 /* triggers drawing using in-packet vertex data */
1882         case PACKET3_3D_DRAW_IMMD_2:
1883                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1884                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1885                         return -EINVAL;
1886                 }
1887                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1888                 track->immd_dwords = pkt->count;
1889                 r = r100_cs_track_check(p->rdev, track);
1890                 if (r)
1891                         return r;
1892                 break;
1893                 /* triggers drawing using in-packet vertex data */
1894         case PACKET3_3D_DRAW_VBUF_2:
1895                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1896                 r = r100_cs_track_check(p->rdev, track);
1897                 if (r)
1898                         return r;
1899                 break;
1900                 /* triggers drawing of vertex buffers setup elsewhere */
1901         case PACKET3_3D_DRAW_INDX_2:
1902                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1903                 r = r100_cs_track_check(p->rdev, track);
1904                 if (r)
1905                         return r;
1906                 break;
1907                 /* triggers drawing using indices to vertex buffer */
1908         case PACKET3_3D_DRAW_VBUF:
1909                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1910                 r = r100_cs_track_check(p->rdev, track);
1911                 if (r)
1912                         return r;
1913                 break;
1914                 /* triggers drawing of vertex buffers setup elsewhere */
1915         case PACKET3_3D_DRAW_INDX:
1916                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1917                 r = r100_cs_track_check(p->rdev, track);
1918                 if (r)
1919                         return r;
1920                 break;
1921                 /* triggers drawing using indices to vertex buffer */
1922         case PACKET3_3D_CLEAR_HIZ:
1923         case PACKET3_3D_CLEAR_ZMASK:
1924                 if (p->rdev->hyperz_filp != p->filp)
1925                         return -EINVAL;
1926                 break;
1927         case PACKET3_NOP:
1928                 break;
1929         default:
1930                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1931                 return -EINVAL;
1932         }
1933         return 0;
1934 }
1935
1936 int r100_cs_parse(struct radeon_cs_parser *p)
1937 {
1938         struct radeon_cs_packet pkt;
1939         struct r100_cs_track *track;
1940         int r;
1941
1942         track = kzalloc(sizeof(*track), GFP_KERNEL);
1943         r100_cs_track_clear(p->rdev, track);
1944         p->track = track;
1945         do {
1946                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1947                 if (r) {
1948                         return r;
1949                 }
1950                 p->idx += pkt.count + 2;
1951                 switch (pkt.type) {
1952                         case PACKET_TYPE0:
1953                                 if (p->rdev->family >= CHIP_R200)
1954                                         r = r100_cs_parse_packet0(p, &pkt,
1955                                                                   p->rdev->config.r100.reg_safe_bm,
1956                                                                   p->rdev->config.r100.reg_safe_bm_size,
1957                                                                   &r200_packet0_check);
1958                                 else
1959                                         r = r100_cs_parse_packet0(p, &pkt,
1960                                                                   p->rdev->config.r100.reg_safe_bm,
1961                                                                   p->rdev->config.r100.reg_safe_bm_size,
1962                                                                   &r100_packet0_check);
1963                                 break;
1964                         case PACKET_TYPE2:
1965                                 break;
1966                         case PACKET_TYPE3:
1967                                 r = r100_packet3_check(p, &pkt);
1968                                 break;
1969                         default:
1970                                 DRM_ERROR("Unknown packet type %d !\n",
1971                                           pkt.type);
1972                                 return -EINVAL;
1973                 }
1974                 if (r) {
1975                         return r;
1976                 }
1977         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1978         return 0;
1979 }
1980
1981
1982 /*
1983  * Global GPU functions
1984  */
1985 void r100_errata(struct radeon_device *rdev)
1986 {
1987         rdev->pll_errata = 0;
1988
1989         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1990                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1991         }
1992
1993         if (rdev->family == CHIP_RV100 ||
1994             rdev->family == CHIP_RS100 ||
1995             rdev->family == CHIP_RS200) {
1996                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1997         }
1998 }
1999
2000 /* Wait for vertical sync on primary CRTC */
2001 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2002 {
2003         uint32_t crtc_gen_cntl, tmp;
2004         int i;
2005
2006         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2007         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2008             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2009                 return;
2010         }
2011         /* Clear the CRTC_VBLANK_SAVE bit */
2012         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2013         for (i = 0; i < rdev->usec_timeout; i++) {
2014                 tmp = RREG32(RADEON_CRTC_STATUS);
2015                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2016                         return;
2017                 }
2018                 DRM_UDELAY(1);
2019         }
2020 }
2021
2022 /* Wait for vertical sync on secondary CRTC */
2023 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2024 {
2025         uint32_t crtc2_gen_cntl, tmp;
2026         int i;
2027
2028         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2029         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2030             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2031                 return;
2032
2033         /* Clear the CRTC_VBLANK_SAVE bit */
2034         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2035         for (i = 0; i < rdev->usec_timeout; i++) {
2036                 tmp = RREG32(RADEON_CRTC2_STATUS);
2037                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2038                         return;
2039                 }
2040                 DRM_UDELAY(1);
2041         }
2042 }
2043
2044 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2045 {
2046         unsigned i;
2047         uint32_t tmp;
2048
2049         for (i = 0; i < rdev->usec_timeout; i++) {
2050                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2051                 if (tmp >= n) {
2052                         return 0;
2053                 }
2054                 DRM_UDELAY(1);
2055         }
2056         return -1;
2057 }
2058
2059 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2060 {
2061         unsigned i;
2062         uint32_t tmp;
2063
2064         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2065                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2066                        " Bad things might happen.\n");
2067         }
2068         for (i = 0; i < rdev->usec_timeout; i++) {
2069                 tmp = RREG32(RADEON_RBBM_STATUS);
2070                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2071                         return 0;
2072                 }
2073                 DRM_UDELAY(1);
2074         }
2075         return -1;
2076 }
2077
2078 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2079 {
2080         unsigned i;
2081         uint32_t tmp;
2082
2083         for (i = 0; i < rdev->usec_timeout; i++) {
2084                 /* read MC_STATUS */
2085                 tmp = RREG32(RADEON_MC_STATUS);
2086                 if (tmp & RADEON_MC_IDLE) {
2087                         return 0;
2088                 }
2089                 DRM_UDELAY(1);
2090         }
2091         return -1;
2092 }
2093
2094 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2095 {
2096         lockup->last_cp_rptr = cp->rptr;
2097         lockup->last_jiffies = jiffies;
2098 }
2099
2100 /**
2101  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2102  * @rdev:       radeon device structure
2103  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
2104  * @cp:         radeon_cp structure holding CP information
2105  *
2106  * We don't need to initialize the lockup tracking information as we will either
2107  * have CP rptr to a different value of jiffies wrap around which will force
2108  * initialization of the lockup tracking informations.
2109  *
2110  * A possible false positivie is if we get call after while and last_cp_rptr ==
2111  * the current CP rptr, even if it's unlikely it might happen. To avoid this
2112  * if the elapsed time since last call is bigger than 2 second than we return
2113  * false and update the tracking information. Due to this the caller must call
2114  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2115  * the fencing code should be cautious about that.
2116  *
2117  * Caller should write to the ring to force CP to do something so we don't get
2118  * false positive when CP is just gived nothing to do.
2119  *
2120  **/
2121 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2122 {
2123         unsigned long cjiffies, elapsed;
2124
2125         cjiffies = jiffies;
2126         if (!time_after(cjiffies, lockup->last_jiffies)) {
2127                 /* likely a wrap around */
2128                 lockup->last_cp_rptr = cp->rptr;
2129                 lockup->last_jiffies = jiffies;
2130                 return false;
2131         }
2132         if (cp->rptr != lockup->last_cp_rptr) {
2133                 /* CP is still working no lockup */
2134                 lockup->last_cp_rptr = cp->rptr;
2135                 lockup->last_jiffies = jiffies;
2136                 return false;
2137         }
2138         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2139         if (elapsed >= 10000) {
2140                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2141                 return true;
2142         }
2143         /* give a chance to the GPU ... */
2144         return false;
2145 }
2146
2147 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2148 {
2149         u32 rbbm_status;
2150         int r;
2151
2152         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2153         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2154                 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2155                 return false;
2156         }
2157         /* force CP activities */
2158         r = radeon_ring_lock(rdev, 2);
2159         if (!r) {
2160                 /* PACKET2 NOP */
2161                 radeon_ring_write(rdev, 0x80000000);
2162                 radeon_ring_write(rdev, 0x80000000);
2163                 radeon_ring_unlock_commit(rdev);
2164         }
2165         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2166         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2167 }
2168
2169 void r100_bm_disable(struct radeon_device *rdev)
2170 {
2171         u32 tmp;
2172
2173         /* disable bus mastering */
2174         tmp = RREG32(R_000030_BUS_CNTL);
2175         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2176         mdelay(1);
2177         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2178         mdelay(1);
2179         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2180         tmp = RREG32(RADEON_BUS_CNTL);
2181         mdelay(1);
2182         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2183         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2184         mdelay(1);
2185 }
2186
2187 int r100_asic_reset(struct radeon_device *rdev)
2188 {
2189         struct r100_mc_save save;
2190         u32 status, tmp;
2191         int ret = 0;
2192
2193         status = RREG32(R_000E40_RBBM_STATUS);
2194         if (!G_000E40_GUI_ACTIVE(status)) {
2195                 return 0;
2196         }
2197         r100_mc_stop(rdev, &save);
2198         status = RREG32(R_000E40_RBBM_STATUS);
2199         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2200         /* stop CP */
2201         WREG32(RADEON_CP_CSQ_CNTL, 0);
2202         tmp = RREG32(RADEON_CP_RB_CNTL);
2203         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2204         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2205         WREG32(RADEON_CP_RB_WPTR, 0);
2206         WREG32(RADEON_CP_RB_CNTL, tmp);
2207         /* save PCI state */
2208         pci_save_state(rdev->pdev);
2209         /* disable bus mastering */
2210         r100_bm_disable(rdev);
2211         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2212                                         S_0000F0_SOFT_RESET_RE(1) |
2213                                         S_0000F0_SOFT_RESET_PP(1) |
2214                                         S_0000F0_SOFT_RESET_RB(1));
2215         RREG32(R_0000F0_RBBM_SOFT_RESET);
2216         mdelay(500);
2217         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2218         mdelay(1);
2219         status = RREG32(R_000E40_RBBM_STATUS);
2220         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2221         /* reset CP */
2222         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2223         RREG32(R_0000F0_RBBM_SOFT_RESET);
2224         mdelay(500);
2225         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2226         mdelay(1);
2227         status = RREG32(R_000E40_RBBM_STATUS);
2228         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2229         /* restore PCI & busmastering */
2230         pci_restore_state(rdev->pdev);
2231         r100_enable_bm(rdev);
2232         /* Check if GPU is idle */
2233         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2234                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2235                 dev_err(rdev->dev, "failed to reset GPU\n");
2236                 rdev->gpu_lockup = true;
2237                 ret = -1;
2238         } else
2239                 dev_info(rdev->dev, "GPU reset succeed\n");
2240         r100_mc_resume(rdev, &save);
2241         return ret;
2242 }
2243
2244 void r100_set_common_regs(struct radeon_device *rdev)
2245 {
2246         struct drm_device *dev = rdev->ddev;
2247         bool force_dac2 = false;
2248         u32 tmp;
2249
2250         /* set these so they don't interfere with anything */
2251         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2252         WREG32(RADEON_SUBPIC_CNTL, 0);
2253         WREG32(RADEON_VIPH_CONTROL, 0);
2254         WREG32(RADEON_I2C_CNTL_1, 0);
2255         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2256         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2257         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2258
2259         /* always set up dac2 on rn50 and some rv100 as lots
2260          * of servers seem to wire it up to a VGA port but
2261          * don't report it in the bios connector
2262          * table.
2263          */
2264         switch (dev->pdev->device) {
2265                 /* RN50 */
2266         case 0x515e:
2267         case 0x5969:
2268                 force_dac2 = true;
2269                 break;
2270                 /* RV100*/
2271         case 0x5159:
2272         case 0x515a:
2273                 /* DELL triple head servers */
2274                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2275                     ((dev->pdev->subsystem_device == 0x016c) ||
2276                      (dev->pdev->subsystem_device == 0x016d) ||
2277                      (dev->pdev->subsystem_device == 0x016e) ||
2278                      (dev->pdev->subsystem_device == 0x016f) ||
2279                      (dev->pdev->subsystem_device == 0x0170) ||
2280                      (dev->pdev->subsystem_device == 0x017d) ||
2281                      (dev->pdev->subsystem_device == 0x017e) ||
2282                      (dev->pdev->subsystem_device == 0x0183) ||
2283                      (dev->pdev->subsystem_device == 0x018a) ||
2284                      (dev->pdev->subsystem_device == 0x019a)))
2285                         force_dac2 = true;
2286                 break;
2287         }
2288
2289         if (force_dac2) {
2290                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2291                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2292                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2293
2294                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2295                    enable it, even it's detected.
2296                 */
2297
2298                 /* force it to crtc0 */
2299                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2300                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2301                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2302
2303                 /* set up the TV DAC */
2304                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2305                                  RADEON_TV_DAC_STD_MASK |
2306                                  RADEON_TV_DAC_RDACPD |
2307                                  RADEON_TV_DAC_GDACPD |
2308                                  RADEON_TV_DAC_BDACPD |
2309                                  RADEON_TV_DAC_BGADJ_MASK |
2310                                  RADEON_TV_DAC_DACADJ_MASK);
2311                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2312                                 RADEON_TV_DAC_NHOLD |
2313                                 RADEON_TV_DAC_STD_PS2 |
2314                                 (0x58 << 16));
2315
2316                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2317                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2318                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2319         }
2320
2321         /* switch PM block to ACPI mode */
2322         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2323         tmp &= ~RADEON_PM_MODE_SEL;
2324         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2325
2326 }
2327
2328 /*
2329  * VRAM info
2330  */
2331 static void r100_vram_get_type(struct radeon_device *rdev)
2332 {
2333         uint32_t tmp;
2334
2335         rdev->mc.vram_is_ddr = false;
2336         if (rdev->flags & RADEON_IS_IGP)
2337                 rdev->mc.vram_is_ddr = true;
2338         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2339                 rdev->mc.vram_is_ddr = true;
2340         if ((rdev->family == CHIP_RV100) ||
2341             (rdev->family == CHIP_RS100) ||
2342             (rdev->family == CHIP_RS200)) {
2343                 tmp = RREG32(RADEON_MEM_CNTL);
2344                 if (tmp & RV100_HALF_MODE) {
2345                         rdev->mc.vram_width = 32;
2346                 } else {
2347                         rdev->mc.vram_width = 64;
2348                 }
2349                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2350                         rdev->mc.vram_width /= 4;
2351                         rdev->mc.vram_is_ddr = true;
2352                 }
2353         } else if (rdev->family <= CHIP_RV280) {
2354                 tmp = RREG32(RADEON_MEM_CNTL);
2355                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2356                         rdev->mc.vram_width = 128;
2357                 } else {
2358                         rdev->mc.vram_width = 64;
2359                 }
2360         } else {
2361                 /* newer IGPs */
2362                 rdev->mc.vram_width = 128;
2363         }
2364 }
2365
2366 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2367 {
2368         u32 aper_size;
2369         u8 byte;
2370
2371         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2372
2373         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2374          * that is has the 2nd generation multifunction PCI interface
2375          */
2376         if (rdev->family == CHIP_RV280 ||
2377             rdev->family >= CHIP_RV350) {
2378                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2379                        ~RADEON_HDP_APER_CNTL);
2380                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2381                 return aper_size * 2;
2382         }
2383
2384         /* Older cards have all sorts of funny issues to deal with. First
2385          * check if it's a multifunction card by reading the PCI config
2386          * header type... Limit those to one aperture size
2387          */
2388         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2389         if (byte & 0x80) {
2390                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2391                 DRM_INFO("Limiting VRAM to one aperture\n");
2392                 return aper_size;
2393         }
2394
2395         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2396          * have set it up. We don't write this as it's broken on some ASICs but
2397          * we expect the BIOS to have done the right thing (might be too optimistic...)
2398          */
2399         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2400                 return aper_size * 2;
2401         return aper_size;
2402 }
2403
2404 void r100_vram_init_sizes(struct radeon_device *rdev)
2405 {
2406         u64 config_aper_size;
2407
2408         /* work out accessible VRAM */
2409         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2410         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2411         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2412         /* FIXME we don't use the second aperture yet when we could use it */
2413         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2414                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2415         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2416         if (rdev->flags & RADEON_IS_IGP) {
2417                 uint32_t tom;
2418                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2419                 tom = RREG32(RADEON_NB_TOM);
2420                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2421                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2422                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2423         } else {
2424                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2425                 /* Some production boards of m6 will report 0
2426                  * if it's 8 MB
2427                  */
2428                 if (rdev->mc.real_vram_size == 0) {
2429                         rdev->mc.real_vram_size = 8192 * 1024;
2430                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2431                 }
2432                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 
2433                  * Novell bug 204882 + along with lots of ubuntu ones
2434                  */
2435                 if (rdev->mc.aper_size > config_aper_size)
2436                         config_aper_size = rdev->mc.aper_size;
2437
2438                 if (config_aper_size > rdev->mc.real_vram_size)
2439                         rdev->mc.mc_vram_size = config_aper_size;
2440                 else
2441                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2442         }
2443 }
2444
2445 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2446 {
2447         uint32_t temp;
2448
2449         temp = RREG32(RADEON_CONFIG_CNTL);
2450         if (state == false) {
2451                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2452                 temp |= RADEON_CFG_VGA_IO_DIS;
2453         } else {
2454                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2455         }
2456         WREG32(RADEON_CONFIG_CNTL, temp);
2457 }
2458
2459 void r100_mc_init(struct radeon_device *rdev)
2460 {
2461         u64 base;
2462
2463         r100_vram_get_type(rdev);
2464         r100_vram_init_sizes(rdev);
2465         base = rdev->mc.aper_base;
2466         if (rdev->flags & RADEON_IS_IGP)
2467                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2468         radeon_vram_location(rdev, &rdev->mc, base);
2469         rdev->mc.gtt_base_align = 0;
2470         if (!(rdev->flags & RADEON_IS_AGP))
2471                 radeon_gtt_location(rdev, &rdev->mc);
2472         radeon_update_bandwidth_info(rdev);
2473 }
2474
2475
2476 /*
2477  * Indirect registers accessor
2478  */
2479 void r100_pll_errata_after_index(struct radeon_device *rdev)
2480 {
2481         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2482                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2483                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2484         }
2485 }
2486
2487 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2488 {
2489         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2490          * or the chip could hang on a subsequent access
2491          */
2492         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2493                 udelay(5000);
2494         }
2495
2496         /* This function is required to workaround a hardware bug in some (all?)
2497          * revisions of the R300.  This workaround should be called after every
2498          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2499          * may not be correct.
2500          */
2501         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2502                 uint32_t save, tmp;
2503
2504                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2505                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2506                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2507                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2508                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2509         }
2510 }
2511
2512 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2513 {
2514         uint32_t data;
2515
2516         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2517         r100_pll_errata_after_index(rdev);
2518         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2519         r100_pll_errata_after_data(rdev);
2520         return data;
2521 }
2522
2523 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2524 {
2525         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2526         r100_pll_errata_after_index(rdev);
2527         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2528         r100_pll_errata_after_data(rdev);
2529 }
2530
2531 void r100_set_safe_registers(struct radeon_device *rdev)
2532 {
2533         if (ASIC_IS_RN50(rdev)) {
2534                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2535                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2536         } else if (rdev->family < CHIP_R200) {
2537                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2538                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2539         } else {
2540                 r200_set_safe_registers(rdev);
2541         }
2542 }
2543
2544 /*
2545  * Debugfs info
2546  */
2547 #if defined(CONFIG_DEBUG_FS)
2548 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2549 {
2550         struct drm_info_node *node = (struct drm_info_node *) m->private;
2551         struct drm_device *dev = node->minor->dev;
2552         struct radeon_device *rdev = dev->dev_private;
2553         uint32_t reg, value;
2554         unsigned i;
2555
2556         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2557         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2558         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2559         for (i = 0; i < 64; i++) {
2560                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2561                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2562                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2563                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2564                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2565         }
2566         return 0;
2567 }
2568
2569 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2570 {
2571         struct drm_info_node *node = (struct drm_info_node *) m->private;
2572         struct drm_device *dev = node->minor->dev;
2573         struct radeon_device *rdev = dev->dev_private;
2574         uint32_t rdp, wdp;
2575         unsigned count, i, j;
2576
2577         radeon_ring_free_size(rdev);
2578         rdp = RREG32(RADEON_CP_RB_RPTR);
2579         wdp = RREG32(RADEON_CP_RB_WPTR);
2580         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2581         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2582         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2583         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2584         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2585         seq_printf(m, "%u dwords in ring\n", count);
2586         for (j = 0; j <= count; j++) {
2587                 i = (rdp + j) & rdev->cp.ptr_mask;
2588                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2589         }
2590         return 0;
2591 }
2592
2593
2594 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2595 {
2596         struct drm_info_node *node = (struct drm_info_node *) m->private;
2597         struct drm_device *dev = node->minor->dev;
2598         struct radeon_device *rdev = dev->dev_private;
2599         uint32_t csq_stat, csq2_stat, tmp;
2600         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2601         unsigned i;
2602
2603         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2604         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2605         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2606         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2607         r_rptr = (csq_stat >> 0) & 0x3ff;
2608         r_wptr = (csq_stat >> 10) & 0x3ff;
2609         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2610         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2611         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2612         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2613         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2614         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2615         seq_printf(m, "Ring rptr %u\n", r_rptr);
2616         seq_printf(m, "Ring wptr %u\n", r_wptr);
2617         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2618         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2619         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2620         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2621         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2622          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2623         seq_printf(m, "Ring fifo:\n");
2624         for (i = 0; i < 256; i++) {
2625                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2626                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2627                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2628         }
2629         seq_printf(m, "Indirect1 fifo:\n");
2630         for (i = 256; i <= 512; i++) {
2631                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2632                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2633                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2634         }
2635         seq_printf(m, "Indirect2 fifo:\n");
2636         for (i = 640; i < ib1_wptr; i++) {
2637                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2638                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2639                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2640         }
2641         return 0;
2642 }
2643
2644 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2645 {
2646         struct drm_info_node *node = (struct drm_info_node *) m->private;
2647         struct drm_device *dev = node->minor->dev;
2648         struct radeon_device *rdev = dev->dev_private;
2649         uint32_t tmp;
2650
2651         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2652         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2653         tmp = RREG32(RADEON_MC_FB_LOCATION);
2654         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2655         tmp = RREG32(RADEON_BUS_CNTL);
2656         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2657         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2658         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2659         tmp = RREG32(RADEON_AGP_BASE);
2660         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2661         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2662         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2663         tmp = RREG32(0x01D0);
2664         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2665         tmp = RREG32(RADEON_AIC_LO_ADDR);
2666         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2667         tmp = RREG32(RADEON_AIC_HI_ADDR);
2668         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2669         tmp = RREG32(0x01E4);
2670         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2671         return 0;
2672 }
2673
2674 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2675         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2676 };
2677
2678 static struct drm_info_list r100_debugfs_cp_list[] = {
2679         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2680         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2681 };
2682
2683 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2684         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2685 };
2686 #endif
2687
2688 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2689 {
2690 #if defined(CONFIG_DEBUG_FS)
2691         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2692 #else
2693         return 0;
2694 #endif
2695 }
2696
2697 int r100_debugfs_cp_init(struct radeon_device *rdev)
2698 {
2699 #if defined(CONFIG_DEBUG_FS)
2700         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2701 #else
2702         return 0;
2703 #endif
2704 }
2705
2706 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2707 {
2708 #if defined(CONFIG_DEBUG_FS)
2709         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2710 #else
2711         return 0;
2712 #endif
2713 }
2714
2715 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2716                          uint32_t tiling_flags, uint32_t pitch,
2717                          uint32_t offset, uint32_t obj_size)
2718 {
2719         int surf_index = reg * 16;
2720         int flags = 0;
2721
2722         if (rdev->family <= CHIP_RS200) {
2723                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2724                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2725                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2726                 if (tiling_flags & RADEON_TILING_MACRO)
2727                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2728         } else if (rdev->family <= CHIP_RV280) {
2729                 if (tiling_flags & (RADEON_TILING_MACRO))
2730                         flags |= R200_SURF_TILE_COLOR_MACRO;
2731                 if (tiling_flags & RADEON_TILING_MICRO)
2732                         flags |= R200_SURF_TILE_COLOR_MICRO;
2733         } else {
2734                 if (tiling_flags & RADEON_TILING_MACRO)
2735                         flags |= R300_SURF_TILE_MACRO;
2736                 if (tiling_flags & RADEON_TILING_MICRO)
2737                         flags |= R300_SURF_TILE_MICRO;
2738         }
2739
2740         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2741                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2742         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2743                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2744
2745         /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2746         if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2747                 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2748                         if (ASIC_IS_RN50(rdev))
2749                                 pitch /= 16;
2750         }
2751
2752         /* r100/r200 divide by 16 */
2753         if (rdev->family < CHIP_R300)
2754                 flags |= pitch / 16;
2755         else
2756                 flags |= pitch / 8;
2757
2758
2759         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2760         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2761         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2762         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2763         return 0;
2764 }
2765
2766 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2767 {
2768         int surf_index = reg * 16;
2769         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2770 }
2771
2772 void r100_bandwidth_update(struct radeon_device *rdev)
2773 {
2774         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2775         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2776         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2777         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2778         fixed20_12 memtcas_ff[8] = {
2779                 dfixed_init(1),
2780                 dfixed_init(2),
2781                 dfixed_init(3),
2782                 dfixed_init(0),
2783                 dfixed_init_half(1),
2784                 dfixed_init_half(2),
2785                 dfixed_init(0),
2786         };
2787         fixed20_12 memtcas_rs480_ff[8] = {
2788                 dfixed_init(0),
2789                 dfixed_init(1),
2790                 dfixed_init(2),
2791                 dfixed_init(3),
2792                 dfixed_init(0),
2793                 dfixed_init_half(1),
2794                 dfixed_init_half(2),
2795                 dfixed_init_half(3),
2796         };
2797         fixed20_12 memtcas2_ff[8] = {
2798                 dfixed_init(0),
2799                 dfixed_init(1),
2800                 dfixed_init(2),
2801                 dfixed_init(3),
2802                 dfixed_init(4),
2803                 dfixed_init(5),
2804                 dfixed_init(6),
2805                 dfixed_init(7),
2806         };
2807         fixed20_12 memtrbs[8] = {
2808                 dfixed_init(1),
2809                 dfixed_init_half(1),
2810                 dfixed_init(2),
2811                 dfixed_init_half(2),
2812                 dfixed_init(3),
2813                 dfixed_init_half(3),
2814                 dfixed_init(4),
2815                 dfixed_init_half(4)
2816         };
2817         fixed20_12 memtrbs_r4xx[8] = {
2818                 dfixed_init(4),
2819                 dfixed_init(5),
2820                 dfixed_init(6),
2821                 dfixed_init(7),
2822                 dfixed_init(8),
2823                 dfixed_init(9),
2824                 dfixed_init(10),
2825                 dfixed_init(11)
2826         };
2827         fixed20_12 min_mem_eff;
2828         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2829         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2830         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2831                 disp_drain_rate2, read_return_rate;
2832         fixed20_12 time_disp1_drop_priority;
2833         int c;
2834         int cur_size = 16;       /* in octawords */
2835         int critical_point = 0, critical_point2;
2836 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2837         int stop_req, max_stop_req;
2838         struct drm_display_mode *mode1 = NULL;
2839         struct drm_display_mode *mode2 = NULL;
2840         uint32_t pixel_bytes1 = 0;
2841         uint32_t pixel_bytes2 = 0;
2842
2843         radeon_update_display_priority(rdev);
2844
2845         if (rdev->mode_info.crtcs[0]->base.enabled) {
2846                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2847                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2848         }
2849         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2850                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2851                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2852                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2853                 }
2854         }
2855
2856         min_mem_eff.full = dfixed_const_8(0);
2857         /* get modes */
2858         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2859                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2860                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2861                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2862                 /* check crtc enables */
2863                 if (mode2)
2864                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2865                 if (mode1)
2866                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2867                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2868         }
2869
2870         /*
2871          * determine is there is enough bw for current mode
2872          */
2873         sclk_ff = rdev->pm.sclk;
2874         mclk_ff = rdev->pm.mclk;
2875
2876         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2877         temp_ff.full = dfixed_const(temp);
2878         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2879
2880         pix_clk.full = 0;
2881         pix_clk2.full = 0;
2882         peak_disp_bw.full = 0;
2883         if (mode1) {
2884                 temp_ff.full = dfixed_const(1000);
2885                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2886                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2887                 temp_ff.full = dfixed_const(pixel_bytes1);
2888                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2889         }
2890         if (mode2) {
2891                 temp_ff.full = dfixed_const(1000);
2892                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2893                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2894                 temp_ff.full = dfixed_const(pixel_bytes2);
2895                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2896         }
2897
2898         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2899         if (peak_disp_bw.full >= mem_bw.full) {
2900                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2901                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2902         }
2903
2904         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2905         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2906         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2907                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2908                 mem_trp  = ((temp & 0x3)) + 1;
2909                 mem_tras = ((temp & 0x70) >> 4) + 1;
2910         } else if (rdev->family == CHIP_R300 ||
2911                    rdev->family == CHIP_R350) { /* r300, r350 */
2912                 mem_trcd = (temp & 0x7) + 1;
2913                 mem_trp = ((temp >> 8) & 0x7) + 1;
2914                 mem_tras = ((temp >> 11) & 0xf) + 4;
2915         } else if (rdev->family == CHIP_RV350 ||
2916                    rdev->family <= CHIP_RV380) {
2917                 /* rv3x0 */
2918                 mem_trcd = (temp & 0x7) + 3;
2919                 mem_trp = ((temp >> 8) & 0x7) + 3;
2920                 mem_tras = ((temp >> 11) & 0xf) + 6;
2921         } else if (rdev->family == CHIP_R420 ||
2922                    rdev->family == CHIP_R423 ||
2923                    rdev->family == CHIP_RV410) {
2924                 /* r4xx */
2925                 mem_trcd = (temp & 0xf) + 3;
2926                 if (mem_trcd > 15)
2927                         mem_trcd = 15;
2928                 mem_trp = ((temp >> 8) & 0xf) + 3;
2929                 if (mem_trp > 15)
2930                         mem_trp = 15;
2931                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2932                 if (mem_tras > 31)
2933                         mem_tras = 31;
2934         } else { /* RV200, R200 */
2935                 mem_trcd = (temp & 0x7) + 1;
2936                 mem_trp = ((temp >> 8) & 0x7) + 1;
2937                 mem_tras = ((temp >> 12) & 0xf) + 4;
2938         }
2939         /* convert to FF */
2940         trcd_ff.full = dfixed_const(mem_trcd);
2941         trp_ff.full = dfixed_const(mem_trp);
2942         tras_ff.full = dfixed_const(mem_tras);
2943
2944         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2945         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2946         data = (temp & (7 << 20)) >> 20;
2947         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2948                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2949                         tcas_ff = memtcas_rs480_ff[data];
2950                 else
2951                         tcas_ff = memtcas_ff[data];
2952         } else
2953                 tcas_ff = memtcas2_ff[data];
2954
2955         if (rdev->family == CHIP_RS400 ||
2956             rdev->family == CHIP_RS480) {
2957                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2958                 data = (temp >> 23) & 0x7;
2959                 if (data < 5)
2960                         tcas_ff.full += dfixed_const(data);
2961         }
2962
2963         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2964                 /* on the R300, Tcas is included in Trbs.
2965                  */
2966                 temp = RREG32(RADEON_MEM_CNTL);
2967                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2968                 if (data == 1) {
2969                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2970                                 temp = RREG32(R300_MC_IND_INDEX);
2971                                 temp &= ~R300_MC_IND_ADDR_MASK;
2972                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2973                                 WREG32(R300_MC_IND_INDEX, temp);
2974                                 temp = RREG32(R300_MC_IND_DATA);
2975                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2976                         } else {
2977                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2978                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2979                         }
2980                 } else {
2981                  &nbs