drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35 #include "evergreen_blit_shaders.h"
  36
  37 #define EVERGREEN_PFP_UCODE_SIZE 1120
  38 #define EVERGREEN_PM4_UCODE_SIZE 1376
  39
  40 static void evergreen_gpu_init(struct radeon_device *rdev);
  41 void evergreen_fini(struct radeon_device *rdev);
  42 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  43
  44 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
  45 {
  46         u16 ctl, v;
  47         int cap, err;
  48
  49         cap = pci_pcie_cap(rdev->pdev);
  50         if (!cap)
  51                 return;
  52
  53         err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
  54         if (err)
  55                 return;
  56
  57         v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
  58
  59         /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
  60          * to avoid hangs or perfomance issues
  61          */
  62         if ((v == 0) || (v == 6) || (v == 7)) {
  63                 ctl &= ~PCI_EXP_DEVCTL_READRQ;
  64                 ctl |= (2 << 12);
  65                 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
  66         }
  67 }
  68
  69 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
  70 {
  71         /* enable the pflip int */
  72         radeon_irq_kms_pflip_irq_get(rdev, crtc);
  73 }
  74
  75 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
  76 {
  77         /* disable the pflip int */
  78         radeon_irq_kms_pflip_irq_put(rdev, crtc);
  79 }
  80
  81 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  82 {
  83         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  84         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
  85         int i;
  86
  87         /* Lock the graphics update lock */
  88         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
  89         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  90
  91         /* update the scanout addresses */
  92         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  93                upper_32_bits(crtc_base));
  94         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  95                (u32)crtc_base);
  96
  97         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  98                upper_32_bits(crtc_base));
  99         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 100                (u32)crtc_base);
 101
 102         /* Wait for update_pending to go high. */
 103         for (i = 0; i < rdev->usec_timeout; i++) {
 104                 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
 105                         break;
 106                 udelay(1);
 107         }
 108         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 109
 110         /* Unlock the lock, so double-buffering can take place inside vblank */
 111         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
 112         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 113
 114         /* Return current update_pending status: */
 115         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
 116 }
 117
 118 /* get temperature in millidegrees */
 119 int evergreen_get_temp(struct radeon_device *rdev)
 120 {
 121         u32 temp, toffset;
 122         int actual_temp = 0;
 123
 124         if (rdev->family == CHIP_JUNIPER) {
 125                 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
 126                         TOFFSET_SHIFT;
 127                 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
 128                         TS0_ADC_DOUT_SHIFT;
 129
 130                 if (toffset & 0x100)
 131                         actual_temp = temp / 2 - (0x200 - toffset);
 132                 else
 133                         actual_temp = temp / 2 + toffset;
 134
 135                 actual_temp = actual_temp * 1000;
 136
 137         } else {
 138                 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 139                         ASIC_T_SHIFT;
 140
 141                 if (temp & 0x400)
 142                         actual_temp = -256;
 143                 else if (temp & 0x200)
 144                         actual_temp = 255;
 145                 else if (temp & 0x100) {
 146                         actual_temp = temp & 0x1ff;
 147                         actual_temp |= ~0x1ff;
 148                 } else
 149                         actual_temp = temp & 0xff;
 150
 151                 actual_temp = (actual_temp * 1000) / 2;
 152         }
 153
 154         return actual_temp;
 155 }
 156
 157 int sumo_get_temp(struct radeon_device *rdev)
 158 {
 159         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 160         int actual_temp = temp - 49;
 161
 162         return actual_temp * 1000;
 163 }
 164
 165 void sumo_pm_init_profile(struct radeon_device *rdev)
 166 {
 167         int idx;
 168
 169         /* default */
 170         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 171         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 172         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 173         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 174
 175         /* low,mid sh/mh */
 176         if (rdev->flags & RADEON_IS_MOBILITY)
 177                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 178         else
 179                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 180
 181         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 182         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 183         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 184         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 185
 186         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 187         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 188         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 189         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 190
 191         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 192         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 193         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 194         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 195
 196         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 197         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 198         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 199         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 200
 201         /* high sh/mh */
 202         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 203         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 204         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 205         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 206         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
 207                 rdev->pm.power_state[idx].num_clock_modes - 1;
 208
 209         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 210         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 211         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 212         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
 213                 rdev->pm.power_state[idx].num_clock_modes - 1;
 214 }
 215
 216 void evergreen_pm_misc(struct radeon_device *rdev)
 217 {
 218         int req_ps_idx = rdev->pm.requested_power_state_index;
 219         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 220         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 221         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 222
 223         if (voltage->type == VOLTAGE_SW) {
 224                 /* 0xff01 is a flag rather then an actual voltage */
 225                 if (voltage->voltage == 0xff01)
 226                         return;
 227                 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
 228                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 229                         rdev->pm.current_vddc = voltage->voltage;
 230                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
 231                 }
 232                 /* 0xff01 is a flag rather then an actual voltage */
 233                 if (voltage->vddci == 0xff01)
 234                         return;
 235                 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
 236                         radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
 237                         rdev->pm.current_vddci = voltage->vddci;
 238                         DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
 239                 }
 240         }
 241 }
 242
 243 void evergreen_pm_prepare(struct radeon_device *rdev)
 244 {
 245         struct drm_device *ddev = rdev->ddev;
 246         struct drm_crtc *crtc;
 247         struct radeon_crtc *radeon_crtc;
 248         u32 tmp;
 249
 250         /* disable any active CRTCs */
 251         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 252                 radeon_crtc = to_radeon_crtc(crtc);
 253                 if (radeon_crtc->enabled) {
 254                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 255                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 256                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 257                 }
 258         }
 259 }
 260
 261 void evergreen_pm_finish(struct radeon_device *rdev)
 262 {
 263         struct drm_device *ddev = rdev->ddev;
 264         struct drm_crtc *crtc;
 265         struct radeon_crtc *radeon_crtc;
 266         u32 tmp;
 267
 268         /* enable any active CRTCs */
 269         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 270                 radeon_crtc = to_radeon_crtc(crtc);
 271                 if (radeon_crtc->enabled) {
 272                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 273                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 274                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 275                 }
 276         }
 277 }
 278
 279 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 280 {
 281         bool connected = false;
 282
 283         switch (hpd) {
 284         case RADEON_HPD_1:
 285                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 286                         connected = true;
 287                 break;
 288         case RADEON_HPD_2:
 289                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 290                         connected = true;
 291                 break;
 292         case RADEON_HPD_3:
 293                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 294                         connected = true;
 295                 break;
 296         case RADEON_HPD_4:
 297                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 298                         connected = true;
 299                 break;
 300         case RADEON_HPD_5:
 301                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 302                         connected = true;
 303                 break;
 304         case RADEON_HPD_6:
 305                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 306                         connected = true;
 307                         break;
 308         default:
 309                 break;
 310         }
 311
 312         return connected;
 313 }
 314
 315 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 316                                 enum radeon_hpd_id hpd)
 317 {
 318         u32 tmp;
 319         bool connected = evergreen_hpd_sense(rdev, hpd);
 320
 321         switch (hpd) {
 322         case RADEON_HPD_1:
 323                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 324                 if (connected)
 325                         tmp &= ~DC_HPDx_INT_POLARITY;
 326                 else
 327                         tmp |= DC_HPDx_INT_POLARITY;
 328                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 329                 break;
 330         case RADEON_HPD_2:
 331                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 332                 if (connected)
 333                         tmp &= ~DC_HPDx_INT_POLARITY;
 334                 else
 335                         tmp |= DC_HPDx_INT_POLARITY;
 336                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 337                 break;
 338         case RADEON_HPD_3:
 339                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 340                 if (connected)
 341                         tmp &= ~DC_HPDx_INT_POLARITY;
 342                 else
 343                         tmp |= DC_HPDx_INT_POLARITY;
 344                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 345                 break;
 346         case RADEON_HPD_4:
 347                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 348                 if (connected)
 349                         tmp &= ~DC_HPDx_INT_POLARITY;
 350                 else
 351                         tmp |= DC_HPDx_INT_POLARITY;
 352                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 353                 break;
 354         case RADEON_HPD_5:
 355                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 356                 if (connected)
 357                         tmp &= ~DC_HPDx_INT_POLARITY;
 358                 else
 359                         tmp |= DC_HPDx_INT_POLARITY;
 360                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 361                         break;
 362         case RADEON_HPD_6:
 363                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 364                 if (connected)
 365                         tmp &= ~DC_HPDx_INT_POLARITY;
 366                 else
 367                         tmp |= DC_HPDx_INT_POLARITY;
 368                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 369                 break;
 370         default:
 371                 break;
 372         }
 373 }
 374
 375 void evergreen_hpd_init(struct radeon_device *rdev)
 376 {
 377         struct drm_device *dev = rdev->ddev;
 378         struct drm_connector *connector;
 379         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 380                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 381
 382         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 383                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 384                 switch (radeon_connector->hpd.hpd) {
 385                 case RADEON_HPD_1:
 386                         WREG32(DC_HPD1_CONTROL, tmp);
 387                         rdev->irq.hpd[0] = true;
 388                         break;
 389                 case RADEON_HPD_2:
 390                         WREG32(DC_HPD2_CONTROL, tmp);
 391                         rdev->irq.hpd[1] = true;
 392                         break;
 393                 case RADEON_HPD_3:
 394                         WREG32(DC_HPD3_CONTROL, tmp);
 395                         rdev->irq.hpd[2] = true;
 396                         break;
 397                 case RADEON_HPD_4:
 398                         WREG32(DC_HPD4_CONTROL, tmp);
 399                         rdev->irq.hpd[3] = true;
 400                         break;
 401                 case RADEON_HPD_5:
 402                         WREG32(DC_HPD5_CONTROL, tmp);
 403                         rdev->irq.hpd[4] = true;
 404                         break;
 405                 case RADEON_HPD_6:
 406                         WREG32(DC_HPD6_CONTROL, tmp);
 407                         rdev->irq.hpd[5] = true;
 408                         break;
 409                 default:
 410                         break;
 411                 }
 412                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 413         }
 414         if (rdev->irq.installed)
 415                 evergreen_irq_set(rdev);
 416 }
 417
 418 void evergreen_hpd_fini(struct radeon_device *rdev)
 419 {
 420         struct drm_device *dev = rdev->ddev;
 421         struct drm_connector *connector;
 422
 423         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 424                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 425                 switch (radeon_connector->hpd.hpd) {
 426                 case RADEON_HPD_1:
 427                         WREG32(DC_HPD1_CONTROL, 0);
 428                         rdev->irq.hpd[0] = false;
 429                         break;
 430                 case RADEON_HPD_2:
 431                         WREG32(DC_HPD2_CONTROL, 0);
 432                         rdev->irq.hpd[1] = false;
 433                         break;
 434                 case RADEON_HPD_3:
 435                         WREG32(DC_HPD3_CONTROL, 0);
 436                         rdev->irq.hpd[2] = false;
 437                         break;
 438                 case RADEON_HPD_4:
 439                         WREG32(DC_HPD4_CONTROL, 0);
 440                         rdev->irq.hpd[3] = false;
 441                         break;
 442                 case RADEON_HPD_5:
 443                         WREG32(DC_HPD5_CONTROL, 0);
 444                         rdev->irq.hpd[4] = false;
 445                         break;
 446                 case RADEON_HPD_6:
 447                         WREG32(DC_HPD6_CONTROL, 0);
 448                         rdev->irq.hpd[5] = false;
 449                         break;
 450                 default:
 451                         break;
 452                 }
 453         }
 454 }
 455
 456 /* watermark setup */
 457
 458 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 459                                         struct radeon_crtc *radeon_crtc,
 460                                         struct drm_display_mode *mode,
 461                                         struct drm_display_mode *other_mode)
 462 {
 463         u32 tmp;
 464         /*
 465          * Line Buffer Setup
 466          * There are 3 line buffers, each one shared by 2 display controllers.
 467          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 468          * the display controllers.  The paritioning is done via one of four
 469          * preset allocations specified in bits 2:0:
 470          * first display controller
 471          *  0 - first half of lb (3840 * 2)
 472          *  1 - first 3/4 of lb (5760 * 2)
 473          *  2 - whole lb (7680 * 2), other crtc must be disabled
 474          *  3 - first 1/4 of lb (1920 * 2)
 475          * second display controller
 476          *  4 - second half of lb (3840 * 2)
 477          *  5 - second 3/4 of lb (5760 * 2)
 478          *  6 - whole lb (7680 * 2), other crtc must be disabled
 479          *  7 - last 1/4 of lb (1920 * 2)
 480          */
 481         /* this can get tricky if we have two large displays on a paired group
 482          * of crtcs.  Ideally for multiple large displays we'd assign them to
 483          * non-linked crtcs for maximum line buffer allocation.
 484          */
 485         if (radeon_crtc->base.enabled && mode) {
 486                 if (other_mode)
 487                         tmp = 0; /* 1/2 */
 488                 else
 489                         tmp = 2; /* whole */
 490         } else
 491                 tmp = 0;
 492
 493         /* second controller of the pair uses second half of the lb */
 494         if (radeon_crtc->crtc_id % 2)
 495                 tmp += 4;
 496         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 497
 498         if (radeon_crtc->base.enabled && mode) {
 499                 switch (tmp) {
 500                 case 0:
 501                 case 4:
 502                 default:
 503                         if (ASIC_IS_DCE5(rdev))
 504                                 return 4096 * 2;
 505                         else
 506                                 return 3840 * 2;
 507                 case 1:
 508                 case 5:
 509                         if (ASIC_IS_DCE5(rdev))
 510                                 return 6144 * 2;
 511                         else
 512                                 return 5760 * 2;
 513                 case 2:
 514                 case 6:
 515                         if (ASIC_IS_DCE5(rdev))
 516                                 return 8192 * 2;
 517                         else
 518                                 return 7680 * 2;
 519                 case 3:
 520                 case 7:
 521                         if (ASIC_IS_DCE5(rdev))
 522                                 return 2048 * 2;
 523                         else
 524                                 return 1920 * 2;
 525                 }
 526         }
 527
 528         /* controller not enabled, so no lb used */
 529         return 0;
 530 }
 531
 532 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 533 {
 534         u32 tmp = RREG32(MC_SHARED_CHMAP);
 535
 536         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 537         case 0:
 538         default:
 539                 return 1;
 540         case 1:
 541                 return 2;
 542         case 2:
 543                 return 4;
 544         case 3:
 545                 return 8;
 546         }
 547 }
 548
 549 struct evergreen_wm_params {
 550         u32 dram_channels; /* number of dram channels */
 551         u32 yclk;          /* bandwidth per dram data pin in kHz */
 552         u32 sclk;          /* engine clock in kHz */
 553         u32 disp_clk;      /* display clock in kHz */
 554         u32 src_width;     /* viewport width */
 555         u32 active_time;   /* active display time in ns */
 556         u32 blank_time;    /* blank time in ns */
 557         bool interlaced;    /* mode is interlaced */
 558         fixed20_12 vsc;    /* vertical scale ratio */
 559         u32 num_heads;     /* number of active crtcs */
 560         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 561         u32 lb_size;       /* line buffer allocated to pipe */
 562         u32 vtaps;         /* vertical scaler taps */
 563 };
 564
 565 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 566 {
 567         /* Calculate DRAM Bandwidth and the part allocated to display. */
 568         fixed20_12 dram_efficiency; /* 0.7 */
 569         fixed20_12 yclk, dram_channels, bandwidth;
 570         fixed20_12 a;
 571
 572         a.full = dfixed_const(1000);
 573         yclk.full = dfixed_const(wm->yclk);
 574         yclk.full = dfixed_div(yclk, a);
 575         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 576         a.full = dfixed_const(10);
 577         dram_efficiency.full = dfixed_const(7);
 578         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 579         bandwidth.full = dfixed_mul(dram_channels, yclk);
 580         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 581
 582         return dfixed_trunc(bandwidth);
 583 }
 584
 585 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 586 {
 587         /* Calculate DRAM Bandwidth and the part allocated to display. */
 588         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 589         fixed20_12 yclk, dram_channels, bandwidth;
 590         fixed20_12 a;
 591
 592         a.full = dfixed_const(1000);
 593         yclk.full = dfixed_const(wm->yclk);
 594         yclk.full = dfixed_div(yclk, a);
 595         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 596         a.full = dfixed_const(10);
 597         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 598         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 599         bandwidth.full = dfixed_mul(dram_channels, yclk);
 600         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 601
 602         return dfixed_trunc(bandwidth);
 603 }
 604
 605 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 606 {
 607         /* Calculate the display Data return Bandwidth */
 608         fixed20_12 return_efficiency; /* 0.8 */
 609         fixed20_12 sclk, bandwidth;
 610         fixed20_12 a;
 611
 612         a.full = dfixed_const(1000);
 613         sclk.full = dfixed_const(wm->sclk);
 614         sclk.full = dfixed_div(sclk, a);
 615         a.full = dfixed_const(10);
 616         return_efficiency.full = dfixed_const(8);
 617         return_efficiency.full = dfixed_div(return_efficiency, a);
 618         a.full = dfixed_const(32);
 619         bandwidth.full = dfixed_mul(a, sclk);
 620         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 621
 622         return dfixed_trunc(bandwidth);
 623 }
 624
 625 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 626 {
 627         /* Calculate the DMIF Request Bandwidth */
 628         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 629         fixed20_12 disp_clk, bandwidth;
 630         fixed20_12 a;
 631
 632         a.full = dfixed_const(1000);
 633         disp_clk.full = dfixed_const(wm->disp_clk);
 634         disp_clk.full = dfixed_div(disp_clk, a);
 635         a.full = dfixed_const(10);
 636         disp_clk_request_efficiency.full = dfixed_const(8);
 637         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 638         a.full = dfixed_const(32);
 639         bandwidth.full = dfixed_mul(a, disp_clk);
 640         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 641
 642         return dfixed_trunc(bandwidth);
 643 }
 644
 645 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 646 {
 647         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 648         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 649         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 650         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 651
 652         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 653 }
 654
 655 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 656 {
 657         /* Calculate the display mode Average Bandwidth
 658          * DisplayMode should contain the source and destination dimensions,
 659          * timing, etc.
 660          */
 661         fixed20_12 bpp;
 662         fixed20_12 line_time;
 663         fixed20_12 src_width;
 664         fixed20_12 bandwidth;
 665         fixed20_12 a;
 666
 667         a.full = dfixed_const(1000);
 668         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 669         line_time.full = dfixed_div(line_time, a);
 670         bpp.full = dfixed_const(wm->bytes_per_pixel);
 671         src_width.full = dfixed_const(wm->src_width);
 672         bandwidth.full = dfixed_mul(src_width, bpp);
 673         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 674         bandwidth.full = dfixed_div(bandwidth, line_time);
 675
 676         return dfixed_trunc(bandwidth);
 677 }
 678
 679 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 680 {
 681         /* First calcualte the latency in ns */
 682         u32 mc_latency = 2000; /* 2000 ns. */
 683         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 684         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 685         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 686         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 687         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 688                 (wm->num_heads * cursor_line_pair_return_time);
 689         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 690         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 691         fixed20_12 a, b, c;
 692
 693         if (wm->num_heads == 0)
 694                 return 0;
 695
 696         a.full = dfixed_const(2);
 697         b.full = dfixed_const(1);
 698         if ((wm->vsc.full > a.full) ||
 699             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 700             (wm->vtaps >= 5) ||
 701             ((wm->vsc.full >= a.full) && wm->interlaced))
 702                 max_src_lines_per_dst_line = 4;
 703         else
 704                 max_src_lines_per_dst_line = 2;
 705
 706         a.full = dfixed_const(available_bandwidth);
 707         b.full = dfixed_const(wm->num_heads);
 708         a.full = dfixed_div(a, b);
 709
 710         b.full = dfixed_const(1000);
 711         c.full = dfixed_const(wm->disp_clk);
 712         b.full = dfixed_div(c, b);
 713         c.full = dfixed_const(wm->bytes_per_pixel);
 714         b.full = dfixed_mul(b, c);
 715
 716         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 717
 718         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 719         b.full = dfixed_const(1000);
 720         c.full = dfixed_const(lb_fill_bw);
 721         b.full = dfixed_div(c, b);
 722         a.full = dfixed_div(a, b);
 723         line_fill_time = dfixed_trunc(a);
 724
 725         if (line_fill_time < wm->active_time)
 726                 return latency;
 727         else
 728                 return latency + (line_fill_time - wm->active_time);
 729
 730 }
 731
 732 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 733 {
 734         if (evergreen_average_bandwidth(wm) <=
 735             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 736                 return true;
 737         else
 738                 return false;
 739 };
 740
 741 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 742 {
 743         if (evergreen_average_bandwidth(wm) <=
 744             (evergreen_available_bandwidth(wm) / wm->num_heads))
 745                 return true;
 746         else
 747                 return false;
 748 };
 749
 750 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 751 {
 752         u32 lb_partitions = wm->lb_size / wm->src_width;
 753         u32 line_time = wm->active_time + wm->blank_time;
 754         u32 latency_tolerant_lines;
 755         u32 latency_hiding;
 756         fixed20_12 a;
 757
 758         a.full = dfixed_const(1);
 759         if (wm->vsc.full > a.full)
 760                 latency_tolerant_lines = 1;
 761         else {
 762                 if (lb_partitions <= (wm->vtaps + 1))
 763                         latency_tolerant_lines = 1;
 764                 else
 765                         latency_tolerant_lines = 2;
 766         }
 767
 768         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 769
 770         if (evergreen_latency_watermark(wm) <= latency_hiding)
 771                 return true;
 772         else
 773                 return false;
 774 }
 775
 776 static void evergreen_program_watermarks(struct radeon_device *rdev,
 777                                          struct radeon_crtc *radeon_crtc,
 778                                          u32 lb_size, u32 num_heads)
 779 {
 780         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 781         struct evergreen_wm_params wm;
 782         u32 pixel_period;
 783         u32 line_time = 0;
 784         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 785         u32 priority_a_mark = 0, priority_b_mark = 0;
 786         u32 priority_a_cnt = PRIORITY_OFF;
 787         u32 priority_b_cnt = PRIORITY_OFF;
 788         u32 pipe_offset = radeon_crtc->crtc_id * 16;
 789         u32 tmp, arb_control3;
 790         fixed20_12 a, b, c;
 791
 792         if (radeon_crtc->base.enabled && num_heads && mode) {
 793                 pixel_period = 1000000 / (u32)mode->clock;
 794                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 795                 priority_a_cnt = 0;
 796                 priority_b_cnt = 0;
 797
 798                 wm.yclk = rdev->pm.current_mclk * 10;
 799                 wm.sclk = rdev->pm.current_sclk * 10;
 800                 wm.disp_clk = mode->clock;
 801                 wm.src_width = mode->crtc_hdisplay;
 802                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 803                 wm.blank_time = line_time - wm.active_time;
 804                 wm.interlaced = false;
 805                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 806                         wm.interlaced = true;
 807                 wm.vsc = radeon_crtc->vsc;
 808                 wm.vtaps = 1;
 809                 if (radeon_crtc->rmx_type != RMX_OFF)
 810                         wm.vtaps = 2;
 811                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 812                 wm.lb_size = lb_size;
 813                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
 814                 wm.num_heads = num_heads;
 815
 816                 /* set for high clocks */
 817                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
 818                 /* set for low clocks */
 819                 /* wm.yclk = low clk; wm.sclk = low clk */
 820                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
 821
 822                 /* possibly force display priority to high */
 823                 /* should really do this at mode validation time... */
 824                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 825                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
 826                     !evergreen_check_latency_hiding(&wm) ||
 827                     (rdev->disp_priority == 2)) {
 828                         DRM_DEBUG_KMS("force priority to high\n");
 829                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 830                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 831                 }
 832
 833                 a.full = dfixed_const(1000);
 834                 b.full = dfixed_const(mode->clock);
 835                 b.full = dfixed_div(b, a);
 836                 c.full = dfixed_const(latency_watermark_a);
 837                 c.full = dfixed_mul(c, b);
 838                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 839                 c.full = dfixed_div(c, a);
 840                 a.full = dfixed_const(16);
 841                 c.full = dfixed_div(c, a);
 842                 priority_a_mark = dfixed_trunc(c);
 843                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 844
 845                 a.full = dfixed_const(1000);
 846                 b.full = dfixed_const(mode->clock);
 847                 b.full = dfixed_div(b, a);
 848                 c.full = dfixed_const(latency_watermark_b);
 849                 c.full = dfixed_mul(c, b);
 850                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 851                 c.full = dfixed_div(c, a);
 852                 a.full = dfixed_const(16);
 853                 c.full = dfixed_div(c, a);
 854                 priority_b_mark = dfixed_trunc(c);
 855                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 856         }
 857
 858         /* select wm A */
 859         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 860         tmp = arb_control3;
 861         tmp &= ~LATENCY_WATERMARK_MASK(3);
 862         tmp |= LATENCY_WATERMARK_MASK(1);
 863         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 864         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 865                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
 866                 LATENCY_HIGH_WATERMARK(line_time)));
 867         /* select wm B */
 868         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 869         tmp &= ~LATENCY_WATERMARK_MASK(3);
 870         tmp |= LATENCY_WATERMARK_MASK(2);
 871         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 872         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 873                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
 874                 LATENCY_HIGH_WATERMARK(line_time)));
 875         /* restore original selection */
 876         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
 877
 878         /* write the priority marks */
 879         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
 880         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 881
 882 }
 883
 884 void evergreen_bandwidth_update(struct radeon_device *rdev)
 885 {
 886         struct drm_display_mode *mode0 = NULL;
 887         struct drm_display_mode *mode1 = NULL;
 888         u32 num_heads = 0, lb_size;
 889         int i;
 890
 891         radeon_update_display_priority(rdev);
 892
 893         for (i = 0; i < rdev->num_crtc; i++) {
 894                 if (rdev->mode_info.crtcs[i]->base.enabled)
 895                         num_heads++;
 896         }
 897         for (i = 0; i < rdev->num_crtc; i += 2) {
 898                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
 899                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
 900                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
 901                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
 902                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
 903                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
 904         }
 905 }
 906
 907 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
 908 {
 909         unsigned i;
 910         u32 tmp;
 911
 912         for (i = 0; i < rdev->usec_timeout; i++) {
 913                 /* read MC_STATUS */
 914                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
 915                 if (!tmp)
 916                         return 0;
 917                 udelay(1);
 918         }
 919         return -1;
 920 }
 921
 922 /*
 923  * GART
 924  */
 925 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
 926 {
 927         unsigned i;
 928         u32 tmp;
 929
 930         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 931
 932         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 933         for (i = 0; i < rdev->usec_timeout; i++) {
 934                 /* read MC_STATUS */
 935                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 936                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 937                 if (tmp == 2) {
 938                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 939                         return;
 940                 }
 941                 if (tmp) {
 942                         return;
 943                 }
 944                 udelay(1);
 945         }
 946 }
 947
 948 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
 949 {
 950         u32 tmp;
 951         int r;
 952
 953         if (rdev->gart.robj == NULL) {
 954                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 955                 return -EINVAL;
 956         }
 957         r = radeon_gart_table_vram_pin(rdev);
 958         if (r)
 959                 return r;
 960         radeon_gart_restore(rdev);
 961         /* Setup L2 cache */
 962         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 963                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 964                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 965         WREG32(VM_L2_CNTL2, 0);
 966         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 967         /* Setup TLB control */
 968         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 969                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 970                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 971                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 972         if (rdev->flags & RADEON_IS_IGP) {
 973                 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
 974                 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
 975                 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
 976         } else {
 977                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 978                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 979                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 980                 if ((rdev->family == CHIP_JUNIPER) ||
 981                     (rdev->family == CHIP_CYPRESS) ||
 982                     (rdev->family == CHIP_HEMLOCK) ||
 983                     (rdev->family == CHIP_BARTS))
 984                         WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
 985         }
 986         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 987         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 988         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 989         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 990         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 991         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 992         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 993         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 994                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 995         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 996                         (u32)(rdev->dummy_page.addr >> 12));
 997         WREG32(VM_CONTEXT1_CNTL, 0);
 998
 999         evergreen_pcie_gart_tlb_flush(rdev);
1000         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1001                  (unsigned)(rdev->mc.gtt_size >> 20),
1002                  (unsigned long long)rdev->gart.table_addr);
1003         rdev->gart.ready = true;
1004         return 0;
1005 }
1006
1007 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1008 {
1009         u32 tmp;
1010
1011         /* Disable all tables */
1012         WREG32(VM_CONTEXT0_CNTL, 0);
1013         WREG32(VM_CONTEXT1_CNTL, 0);
1014
1015         /* Setup L2 cache */
1016         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1017                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1018         WREG32(VM_L2_CNTL2, 0);
1019         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1020         /* Setup TLB control */
1021         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1022         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1023         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1024         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1025         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1026         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1027         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1028         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1029         radeon_gart_table_vram_unpin(rdev);
1030 }
1031
1032 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1033 {
1034         evergreen_pcie_gart_disable(rdev);
1035         radeon_gart_table_vram_free(rdev);
1036         radeon_gart_fini(rdev);
1037 }
1038
1039
1040 void evergreen_agp_enable(struct radeon_device *rdev)
1041 {
1042         u32 tmp;
1043
1044         /* Setup L2 cache */
1045         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1046                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1047                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1048         WREG32(VM_L2_CNTL2, 0);
1049         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1050         /* Setup TLB control */
1051         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1052                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1053                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1054                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1055         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1056         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1057         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1058         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1059         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1060         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1061         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1062         WREG32(VM_CONTEXT0_CNTL, 0);
1063         WREG32(VM_CONTEXT1_CNTL, 0);
1064 }
1065
1066 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1067 {
1068         save->vga_control[0] = RREG32(D1VGA_CONTROL);
1069         save->vga_control[1] = RREG32(D2VGA_CONTROL);
1070         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1071         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1072         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1073         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1074         if (rdev->num_crtc >= 4) {
1075                 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1076                 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1077                 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1078                 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1079         }
1080         if (rdev->num_crtc >= 6) {
1081                 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1082                 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1083                 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1084                 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1085         }
1086
1087         /* Stop all video */
1088         WREG32(VGA_RENDER_CONTROL, 0);
1089         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1090         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1091         if (rdev->num_crtc >= 4) {
1092                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1093                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1094         }
1095         if (rdev->num_crtc >= 6) {
1096                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1097                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1098         }
1099         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1100         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1101         if (rdev->num_crtc >= 4) {
1102                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1103                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1104         }
1105         if (rdev->num_crtc >= 6) {
1106                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1107                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1108         }
1109         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1110         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1111         if (rdev->num_crtc >= 4) {
1112                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1113                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1114         }
1115         if (rdev->num_crtc >= 6) {
1116                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1117                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1118         }
1119
1120         WREG32(D1VGA_CONTROL, 0);
1121         WREG32(D2VGA_CONTROL, 0);
1122         if (rdev->num_crtc >= 4) {
1123                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1124                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1125         }
1126         if (rdev->num_crtc >= 6) {
1127                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1128                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1129         }
1130 }
1131
1132 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1133 {
1134         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1135                upper_32_bits(rdev->mc.vram_start));
1136         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1137                upper_32_bits(rdev->mc.vram_start));
1138         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1139                (u32)rdev->mc.vram_start);
1140         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1141                (u32)rdev->mc.vram_start);
1142
1143         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1144                upper_32_bits(rdev->mc.vram_start));
1145         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1146                upper_32_bits(rdev->mc.vram_start));
1147         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1148                (u32)rdev->mc.vram_start);
1149         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1150                (u32)rdev->mc.vram_start);
1151
1152         if (rdev->num_crtc >= 4) {
1153                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1154                        upper_32_bits(rdev->mc.vram_start));
1155                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1156                        upper_32_bits(rdev->mc.vram_start));
1157                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1158                        (u32)rdev->mc.vram_start);
1159                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1160                        (u32)rdev->mc.vram_start);
1161
1162                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1163                        upper_32_bits(rdev->mc.vram_start));
1164                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1165                        upper_32_bits(rdev->mc.vram_start));
1166                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1167                        (u32)rdev->mc.vram_start);
1168                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1169                        (u32)rdev->mc.vram_start);
1170         }
1171         if (rdev->num_crtc >= 6) {
1172                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1173                        upper_32_bits(rdev->mc.vram_start));
1174                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1175                        upper_32_bits(rdev->mc.vram_start));
1176                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1177                        (u32)rdev->mc.vram_start);
1178                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1179                        (u32)rdev->mc.vram_start);
1180
1181                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1182                        upper_32_bits(rdev->mc.vram_start));
1183                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1184                        upper_32_bits(rdev->mc.vram_start));
1185                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1186                        (u32)rdev->mc.vram_start);
1187                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1188                        (u32)rdev->mc.vram_start);
1189         }
1190
1191         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1192         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1193         /* Unlock host access */
1194         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1195         mdelay(1);
1196         /* Restore video state */
1197         WREG32(D1VGA_CONTROL, save->vga_control[0]);
1198         WREG32(D2VGA_CONTROL, save->vga_control[1]);
1199         if (rdev->num_crtc >= 4) {
1200                 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1201                 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1202         }
1203         if (rdev->num_crtc >= 6) {
1204                 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1205                 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1206         }
1207         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1208         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1209         if (rdev->num_crtc >= 4) {
1210                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1211                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1212         }
1213         if (rdev->num_crtc >= 6) {
1214                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1215                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1216         }
1217         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1218         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1219         if (rdev->num_crtc >= 4) {
1220                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1221                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1222         }
1223         if (rdev->num_crtc >= 6) {
1224                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1225                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1226         }
1227         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1228         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1229         if (rdev->num_crtc >= 4) {
1230                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1231                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1232         }
1233         if (rdev->num_crtc >= 6) {
1234                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1235                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1236         }
1237         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1238 }
1239
1240 void evergreen_mc_program(struct radeon_device *rdev)
1241 {
1242         struct evergreen_mc_save save;
1243         u32 tmp;
1244         int i, j;
1245
1246         /* Initialize HDP */
1247         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1248                 WREG32((0x2c14 + j), 0x00000000);
1249                 WREG32((0x2c18 + j), 0x00000000);
1250                 WREG32((0x2c1c + j), 0x00000000);
1251                 WREG32((0x2c20 + j), 0x00000000);
1252                 WREG32((0x2c24 + j), 0x00000000);
1253         }
1254         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1255
1256         evergreen_mc_stop(rdev, &save);
1257         if (evergreen_mc_wait_for_idle(rdev)) {
1258                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1259         }
1260         /* Lockout access through VGA aperture*/
1261         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1262         /* Update configuration */
1263         if (rdev->flags & RADEON_IS_AGP) {
1264                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1265                         /* VRAM before AGP */
1266                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1267                                 rdev->mc.vram_start >> 12);
1268                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1269                                 rdev->mc.gtt_end >> 12);
1270                 } else {
1271                         /* VRAM after AGP */
1272                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1273                                 rdev->mc.gtt_start >> 12);
1274                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1275                                 rdev->mc.vram_end >> 12);
1276                 }
1277         } else {
1278                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1279                         rdev->mc.vram_start >> 12);
1280                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1281                         rdev->mc.vram_end >> 12);
1282         }
1283         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1284         if (rdev->flags & RADEON_IS_IGP) {
1285                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1286                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1287                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1288                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1289         }
1290         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1291         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1292         WREG32(MC_VM_FB_LOCATION, tmp);
1293         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1294         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1295         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1296         if (rdev->flags & RADEON_IS_AGP) {
1297                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1298                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1299                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1300         } else {
1301                 WREG32(MC_VM_AGP_BASE, 0);
1302                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1303                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1304         }
1305         if (evergreen_mc_wait_for_idle(rdev)) {
1306                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1307         }
1308         evergreen_mc_resume(rdev, &save);
1309         /* we need to own VRAM, so turn off the VGA renderer here
1310          * to stop it overwriting our objects */
1311         rv515_vga_render_disable(rdev);
1312 }
1313
1314 /*
1315  * CP.
1316  */
1317 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1318 {
1319         /* set to DX10/11 mode */
1320         radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1321         radeon_ring_write(rdev, 1);
1322         /* FIXME: implement */
1323         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1324         radeon_ring_write(rdev,
1325 #ifdef __BIG_ENDIAN
1326                           (2 << 0) |
1327 #endif
1328                           (ib->gpu_addr & 0xFFFFFFFC));
1329         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1330         radeon_ring_write(rdev, ib->length_dw);
1331 }
1332
1333
1334 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1335 {
1336         const __be32 *fw_data;
1337         int i;
1338
1339         if (!rdev->me_fw || !rdev->pfp_fw)
1340                 return -EINVAL;
1341
1342         r700_cp_stop(rdev);
1343         WREG32(CP_RB_CNTL,
1344 #ifdef __BIG_ENDIAN
1345                BUF_SWAP_32BIT |
1346 #endif
1347                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1348
1349         fw_data = (const __be32 *)rdev->pfp_fw->data;
1350         WREG32(CP_PFP_UCODE_ADDR, 0);
1351         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1352                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1353         WREG32(CP_PFP_UCODE_ADDR, 0);
1354
1355         fw_data = (const __be32 *)rdev->me_fw->data;
1356         WREG32(CP_ME_RAM_WADDR, 0);
1357         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1358                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1359
1360         WREG32(CP_PFP_UCODE_ADDR, 0);
1361         WREG32(CP_ME_RAM_WADDR, 0);
1362         WREG32(CP_ME_RAM_RADDR, 0);
1363         return 0;
1364 }
1365
1366 static int evergreen_cp_start(struct radeon_device *rdev)
1367 {
1368         int r, i;
1369         uint32_t cp_me;
1370
1371         r = radeon_ring_lock(rdev, 7);
1372         if (r) {
1373                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1374                 return r;
1375         }
1376         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1377         radeon_ring_write(rdev, 0x1);
1378         radeon_ring_write(rdev, 0x0);
1379         radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1380         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1381         radeon_ring_write(rdev, 0);
1382         radeon_ring_write(rdev, 0);
1383         radeon_ring_unlock_commit(rdev);
1384
1385         cp_me = 0xff;
1386         WREG32(CP_ME_CNTL, cp_me);
1387
1388         r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1389         if (r) {
1390                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1391                 return r;
1392         }
1393
1394         /* setup clear context state */
1395         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1396         radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1397
1398         for (i = 0; i < evergreen_default_size; i++)
1399                 radeon_ring_write(rdev, evergreen_default_state[i]);
1400
1401         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1402         radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1403
1404         /* set clear context state */
1405         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1406         radeon_ring_write(rdev, 0);
1407
1408         /* SQ_VTX_BASE_VTX_LOC */
1409         radeon_ring_write(rdev, 0xc0026f00);
1410         radeon_ring_write(rdev, 0x00000000);
1411         radeon_ring_write(rdev, 0x00000000);
1412         radeon_ring_write(rdev, 0x00000000);
1413
1414         /* Clear consts */
1415         radeon_ring_write(rdev, 0xc0036f00);
1416         radeon_ring_write(rdev, 0x00000bc4);
1417         radeon_ring_write(rdev, 0xffffffff);
1418         radeon_ring_write(rdev, 0xffffffff);
1419         radeon_ring_write(rdev, 0xffffffff);
1420
1421         radeon_ring_write(rdev, 0xc0026900);
1422         radeon_ring_write(rdev, 0x00000316);
1423         radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1424         radeon_ring_write(rdev, 0x00000010); /*  */
1425
1426         radeon_ring_unlock_commit(rdev);
1427
1428         return 0;
1429 }
1430
1431 int evergreen_cp_resume(struct radeon_device *rdev)
1432 {
1433         u32 tmp;
1434         u32 rb_bufsz;
1435         int r;
1436
1437         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1438         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1439                                  SOFT_RESET_PA |
1440                                  SOFT_RESET_SH |
1441                                  SOFT_RESET_VGT |
1442                                  SOFT_RESET_SPI |
1443                                  SOFT_RESET_SX));
1444         RREG32(GRBM_SOFT_RESET);
1445         mdelay(15);
1446         WREG32(GRBM_SOFT_RESET, 0);
1447         RREG32(GRBM_SOFT_RESET);
1448
1449         /* Set ring buffer size */
1450         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1451         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1452 #ifdef __BIG_ENDIAN
1453         tmp |= BUF_SWAP_32BIT;
1454 #endif
1455         WREG32(CP_RB_CNTL, tmp);
1456         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1457
1458         /* Set the write pointer delay */
1459         WREG32(CP_RB_WPTR_DELAY, 0);
1460
1461         /* Initialize the ring buffer's read and write pointers */
1462         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1463         WREG32(CP_RB_RPTR_WR, 0);
1464         rdev->cp.wptr = 0;
1465         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1466
1467         /* set the wb address wether it's enabled or not */
1468         WREG32(CP_RB_RPTR_ADDR,
1469                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1470         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1471         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1472
1473         if (rdev->wb.enabled)
1474                 WREG32(SCRATCH_UMSK, 0xff);
1475         else {
1476                 tmp |= RB_NO_UPDATE;
1477                 WREG32(SCRATCH_UMSK, 0);
1478         }
1479
1480         mdelay(1);
1481         WREG32(CP_RB_CNTL, tmp);
1482
1483         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1484         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1485
1486         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1487
1488         evergreen_cp_start(rdev);
1489         rdev->cp.ready = true;
1490         r = radeon_ring_test(rdev);
1491         if (r) {
1492                 rdev->cp.ready = false;
1493                 return r;
1494         }
1495         return 0;
1496 }
1497
1498 /*
1499  * Core functions
1500  */
1501 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1502                                                   u32 num_tile_pipes,
1503                                                   u32 num_backends,
1504                                                   u32 backend_disable_mask)
1505 {
1506         u32 backend_map = 0;
1507         u32 enabled_backends_mask = 0;
1508         u32 enabled_backends_count = 0;
1509         u32 cur_pipe;
1510         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1511         u32 cur_backend = 0;
1512         u32 i;
1513         bool force_no_swizzle;
1514
1515         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1516                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1517         if (num_tile_pipes < 1)
1518                 num_tile_pipes = 1;
1519         if (num_backends > EVERGREEN_MAX_BACKENDS)
1520                 num_backends = EVERGREEN_MAX_BACKENDS;
1521         if (num_backends < 1)
1522                 num_backends = 1;
1523
1524         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1525                 if (((backend_disable_mask >> i) & 1) == 0) {
1526                         enabled_backends_mask |= (1 << i);
1527                         ++enabled_backends_count;
1528                 }
1529                 if (enabled_backends_count == num_backends)
1530                         break;
1531         }
1532
1533         if (enabled_backends_count == 0) {
1534                 enabled_backends_mask = 1;
1535                 enabled_backends_count = 1;
1536         }
1537
1538         if (enabled_backends_count != num_backends)
1539                 num_backends = enabled_backends_count;
1540
1541         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1542         switch (rdev->family) {
1543         case CHIP_CEDAR:
1544         case CHIP_REDWOOD:
1545         case CHIP_PALM:
1546         case CHIP_SUMO:
1547         case CHIP_SUMO2:
1548         case CHIP_TURKS:
1549         case CHIP_CAICOS:
1550                 force_no_swizzle = false;
1551                 break;
1552         case CHIP_CYPRESS:
1553         case CHIP_HEMLOCK:
1554         case CHIP_JUNIPER:
1555         case CHIP_BARTS:
1556         default:
1557                 force_no_swizzle = true;
1558                 break;
1559         }
1560         if (force_no_swizzle) {
1561                 bool last_backend_enabled = false;
1562
1563                 force_no_swizzle = false;
1564                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1565                         if (((enabled_backends_mask >> i) & 1) == 1) {
1566                                 if (last_backend_enabled)
1567                                         force_no_swizzle = true;
1568                                 last_backend_enabled = true;
1569                         } else
1570                                 last_backend_enabled = false;
1571                 }
1572         }
1573
1574         switch (num_tile_pipes) {
1575         case 1:
1576         case 3:
1577         case 5:
1578         case 7:
1579                 DRM_ERROR("odd number of pipes!\n");
1580                 break;
1581         case 2:
1582                 swizzle_pipe[0] = 0;
1583                 swizzle_pipe[1] = 1;
1584                 break;
1585         case 4:
1586                 if (force_no_swizzle) {
1587                         swizzle_pipe[0] = 0;
1588                         swizzle_pipe[1] = 1;
1589                         swizzle_pipe[2] = 2;
1590                         swizzle_pipe[3] = 3;
1591                 } else {
1592                         swizzle_pipe[0] = 0;
1593                         swizzle_pipe[1] = 2;
1594                         swizzle_pipe[2] = 1;
1595                         swizzle_pipe[3] = 3;
1596                 }
1597                 break;
1598         case 6:
1599                 if (force_no_swizzle) {
1600                         swizzle_pipe[0] = 0;
1601                         swizzle_pipe[1] = 1;
1602                         swizzle_pipe[2] = 2;
1603                         swizzle_pipe[3] = 3;
1604                         swizzle_pipe[4] = 4;
1605                         swizzle_pipe[5] = 5;
1606                 } else {
1607                         swizzle_pipe[0] = 0;
1608                         swizzle_pipe[1] = 2;
1609                         swizzle_pipe[2] = 4;
1610                         swizzle_pipe[3] = 1;
1611                         swizzle_pipe[4] = 3;
1612                         swizzle_pipe[5] = 5;
1613                 }
1614                 break;
1615         case 8:
1616                 if (force_no_swizzle) {
1617                         swizzle_pipe[0] = 0;
1618                         swizzle_pipe[1] = 1;
1619                         swizzle_pipe[2] = 2;
1620                         swizzle_pipe[3] = 3;
1621                         swizzle_pipe[4] = 4;
1622                         swizzle_pipe[5] = 5;
1623                         swizzle_pipe[6] = 6;
1624                         swizzle_pipe[7] = 7;
1625                 } else {
1626                         swizzle_pipe[0] = 0;
1627                         swizzle_pipe[1] = 2;
1628                         swizzle_pipe[2] = 4;
1629                         swizzle_pipe[3] = 6;
1630                         swizzle_pipe[4] = 1;
1631                         swizzle_pipe[5] = 3;
1632                         swizzle_pipe[6] = 5;
1633                         swizzle_pipe[7] = 7;
1634                 }
1635                 break;
1636         }
1637
1638         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1639                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1640                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1641
1642                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1643
1644                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1645         }
1646
1647         return backend_map;
1648 }
1649
1650 static void evergreen_gpu_init(struct radeon_device *rdev)
1651 {
1652         u32 cc_rb_backend_disable = 0;
1653         u32 cc_gc_shader_pipe_config;
1654         u32 gb_addr_config = 0;
1655         u32 mc_shared_chmap, mc_arb_ramcfg;
1656         u32 gb_backend_map;
1657         u32 grbm_gfx_index;
1658         u32 sx_debug_1;
1659         u32 smx_dc_ctl0;
1660         u32 sq_config;
1661         u32 sq_lds_resource_mgmt;
1662         u32 sq_gpr_resource_mgmt_1;
1663         u32 sq_gpr_resource_mgmt_2;
1664         u32 sq_gpr_resource_mgmt_3;
1665         u32 sq_thread_resource_mgmt;
1666         u32 sq_thread_resource_mgmt_2;
1667         u32 sq_stack_resource_mgmt_1;
1668         u32 sq_stack_resource_mgmt_2;
1669         u32 sq_stack_resource_mgmt_3;
1670         u32 vgt_cache_invalidation;
1671         u32 hdp_host_path_cntl, tmp;
1672         int i, j, num_shader_engines, ps_thread_count;
1673
1674         switch (rdev->family) {
1675         case CHIP_CYPRESS:
1676         case CHIP_HEMLOCK:
1677                 rdev->config.evergreen.num_ses = 2;
1678                 rdev->config.evergreen.max_pipes = 4;
1679                 rdev->config.evergreen.max_tile_pipes = 8;
1680                 rdev->config.evergreen.max_simds = 10;
1681                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1682                 rdev->config.evergreen.max_gprs = 256;
1683                 rdev->config.evergreen.max_threads = 248;
1684                 rdev->config.evergreen.max_gs_threads = 32;
1685                 rdev->config.evergreen.max_stack_entries = 512;
1686                 rdev->config.evergreen.sx_num_of_sets = 4;
1687                 rdev->config.evergreen.sx_max_export_size = 256;
1688                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1689                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1690                 rdev->config.evergreen.max_hw_contexts = 8;
1691                 rdev->config.evergreen.sq_num_cf_insts = 2;
1692
1693                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1694                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1695                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1696                 break;
1697         case CHIP_JUNIPER:
1698                 rdev->config.evergreen.num_ses = 1;
1699                 rdev->config.evergreen.max_pipes = 4;
1700                 rdev->config.evergreen.max_tile_pipes = 4;
1701                 rdev->config.evergreen.max_simds = 10;
1702                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1703                 rdev->config.evergreen.max_gprs = 256;
1704                 rdev->config.evergreen.max_threads = 248;
1705                 rdev->config.evergreen.max_gs_threads = 32;
1706                 rdev->config.evergreen.max_stack_entries = 512;
1707                 rdev->config.evergreen.sx_num_of_sets = 4;
1708                 rdev->config.evergreen.sx_max_export_size = 256;
1709                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1710                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1711                 rdev->config.evergreen.max_hw_contexts = 8;
1712                 rdev->config.evergreen.sq_num_cf_insts = 2;
1713
1714                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1715                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1716                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1717                 break;
1718         case CHIP_REDWOOD:
1719                 rdev->config.evergreen.num_ses = 1;
1720                 rdev->config.evergreen.max_pipes = 4;
1721                 rdev->config.evergreen.max_tile_pipes = 4;
1722                 rdev->config.evergreen.max_simds = 5;
1723                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1724                 rdev->config.evergreen.max_gprs = 256;
1725                 rdev->config.evergreen.max_threads = 248;
1726                 rdev->config.evergreen.max_gs_threads = 32;
1727                 rdev->config.evergreen.max_stack_entries = 256;
1728                 rdev->config.evergreen.sx_num_of_sets = 4;
1729                 rdev->config.evergreen.sx_max_export_size = 256;
1730                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1731                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1732                 rdev->config.evergreen.max_hw_contexts = 8;
1733                 rdev->config.evergreen.sq_num_cf_insts = 2;
1734
1735                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1736                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1737                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1738                 break;
1739         case CHIP_CEDAR:
1740         default:
1741                 rdev->config.evergreen.num_ses = 1;
1742                 rdev->config.evergreen.max_pipes = 2;
1743                 rdev->config.evergreen.max_tile_pipes = 2;
1744                 rdev->config.evergreen.max_simds = 2;
1745                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1746                 rdev->config.evergreen.max_gprs = 256;
1747                 rdev->config.evergreen.max_threads = 192;
1748                 rdev->config.evergreen.max_gs_threads = 16;
1749                 rdev->config.evergreen.max_stack_entries = 256;
1750                 rdev->config.evergreen.sx_num_of_sets = 4;
1751                 rdev->config.evergreen.sx_max_export_size = 128;
1752                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1753                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1754                 rdev->config.evergreen.max_hw_contexts = 4;
1755                 rdev->config.evergreen.sq_num_cf_insts = 1;
1756
1757                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1758                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1759                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1760                 break;
1761         case CHIP_PALM:
1762                 rdev->config.evergreen.num_ses = 1;
1763                 rdev->config.evergreen.max_pipes = 2;
1764                 rdev->config.evergreen.max_tile_pipes = 2;
1765                 rdev->config.evergreen.max_simds = 2;
1766                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1767                 rdev->config.evergreen.max_gprs = 256;
1768                 rdev->config.evergreen.max_threads = 192;
1769                 rdev->config.evergreen.max_gs_threads = 16;
1770                 rdev->config.evergreen.max_stack_entries = 256;
1771                 rdev->config.evergreen.sx_num_of_sets = 4;
1772                 rdev->config.evergreen.sx_max_export_size = 128;
1773                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1774                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1775                 rdev->config.evergreen.max_hw_contexts = 4;
1776                 rdev->config.evergreen.sq_num_cf_insts = 1;
1777
1778                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1779                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1780                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1781                 break;
1782         case CHIP_SUMO:
1783                 rdev->config.evergreen.num_ses = 1;
1784                 rdev->config.evergreen.max_pipes = 4;
1785                 rdev->config.evergreen.max_tile_pipes = 2;
1786                 if (rdev->pdev->device == 0x9648)
1787                         rdev->config.evergreen.max_simds = 3;
1788                 else if ((rdev->pdev->device == 0x9647) ||
1789                          (rdev->pdev->device == 0x964a))
1790                         rdev->config.evergreen.max_simds = 4;
1791                 else
1792                         rdev->config.evergreen.max_simds = 5;
1793                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1794                 rdev->config.evergreen.max_gprs = 256;
1795                 rdev->config.evergreen.max_threads = 248;
1796                 rdev->config.evergreen.max_gs_threads = 32;
1797                 rdev->config.evergreen.max_stack_entries = 256;
1798                 rdev->config.evergreen.sx_num_of_sets = 4;
1799                 rdev->config.evergreen.sx_max_export_size = 256;
1800                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1801                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1802                 rdev->config.evergreen.max_hw_contexts = 8;
1803                 rdev->config.evergreen.sq_num_cf_insts = 2;
1804
1805                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1806                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1807                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1808                 break;
1809         case CHIP_SUMO2:
1810                 rdev->config.evergreen.num_ses = 1;
1811                 rdev->config.evergreen.max_pipes = 4;
1812                 rdev->config.evergreen.max_tile_pipes = 4;
1813                 rdev->config.evergreen.max_simds = 2;
1814                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1815                 rdev->config.evergreen.max_gprs = 256;
1816                 rdev->config.evergreen.max_threads = 248;
1817                 rdev->config.evergreen.max_gs_threads = 32;
1818                 rdev->config.evergreen.max_stack_entries = 512;
1819                 rdev->config.evergreen.sx_num_of_sets = 4;
1820                 rdev->config.evergreen.sx_max_export_size = 256;
1821                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1822                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1823                 rdev->config.evergreen.max_hw_contexts = 8;
1824                 rdev->config.evergreen.sq_num_cf_insts = 2;
1825
1826                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1827                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1828                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1829                 break;
1830         case CHIP_BARTS:
1831                 rdev->config.evergreen.num_ses = 2;
1832                 rdev->config.evergreen.max_pipes = 4;
1833                 rdev->config.evergreen.max_tile_pipes = 8;
1834                 rdev->config.evergreen.max_simds = 7;
1835                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1836                 rdev->config.evergreen.max_gprs = 256;
1837                 rdev->config.evergreen.max_threads = 248;
1838                 rdev->config.evergreen.max_gs_threads = 32;
1839                 rdev->config.evergreen.max_stack_entries = 512;
1840                 rdev->config.evergreen.sx_num_of_sets = 4;
1841                 rdev->config.evergreen.sx_max_export_size = 256;
1842                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1843                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1844                 rdev->config.evergreen.max_hw_contexts = 8;
1845                 rdev->config.evergreen.sq_num_cf_insts = 2;
1846
1847                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1848                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1849                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1850                 break;
1851         case CHIP_TURKS:
1852                 rdev->config.evergreen.num_ses = 1;
1853                 rdev->config.evergreen.max_pipes = 4;
1854                 rdev->config.evergreen.max_tile_pipes = 4;
1855                 rdev->config.evergreen.max_simds = 6;
1856                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1857                 rdev->config.evergreen.max_gprs = 256;
1858                 rdev->config.evergreen.max_threads = 248;
1859                 rdev->config.evergreen.max_gs_threads = 32;
1860                 rdev->config.evergreen.max_stack_entries = 256;
1861                 rdev->config.evergreen.sx_num_of_sets = 4;
1862                 rdev->config.evergreen.sx_max_export_size = 256;
1863                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1864                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1865                 rdev->config.evergreen.max_hw_contexts = 8;
1866                 rdev->config.evergreen.sq_num_cf_insts = 2;
1867
1868                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1869                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1870                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1871                 break;
1872         case CHIP_CAICOS:
1873                 rdev->config.evergreen.num_ses = 1;
1874                 rdev->config.evergreen.max_pipes = 4;
1875                 rdev->config.evergreen.max_tile_pipes = 2;
1876                 rdev->config.evergreen.max_simds = 2;
1877                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1878                 rdev->config.evergreen.max_gprs = 256;
1879                 rdev->config.evergreen.max_threads = 192;
1880                 rdev->config.evergreen.max_gs_threads = 16;
1881                 rdev->config.evergreen.max_stack_entries = 256;
1882                 rdev->config.evergreen.sx_num_of_sets = 4;
1883                 rdev->config.evergreen.sx_max_export_size = 128;
1884                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1885                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1886                 rdev->config.evergreen.max_hw_contexts = 4;
1887                 rdev->config.evergreen.sq_num_cf_insts = 1;
1888
1889                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1890                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1891                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1892                 break;
1893         }
1894
1895         /* Initialize HDP */
1896         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1897                 WREG32((0x2c14 + j), 0x00000000);
1898                 WREG32((0x2c18 + j), 0x00000000);
1899                 WREG32((0x2c1c + j), 0x00000000);
1900                 WREG32((0x2c20 + j), 0x00000000);
1901                 WREG32((0x2c24 + j), 0x00000000);
1902         }
1903
1904         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1905
1906         evergreen_fix_pci_max_read_req_size(rdev);
1907
1908         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1909
1910         cc_gc_shader_pipe_config |=
1911                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1912                                   & EVERGREEN_MAX_PIPES_MASK);
1913         cc_gc_shader_pipe_config |=
1914                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1915                                & EVERGREEN_MAX_SIMDS_MASK);
1916
1917         cc_rb_backend_disable =
1918                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1919                                 & EVERGREEN_MAX_BACKENDS_MASK);
1920
1921
1922         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1923         if (rdev->flags & RADEON_IS_IGP)
1924                 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1925         else
1926                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1927
1928         switch (rdev->config.evergreen.max_tile_pipes) {
1929         case 1:
1930         default:
1931                 gb_addr_config |= NUM_PIPES(0);
1932                 break;
1933         case 2:
1934                 gb_addr_config |= NUM_PIPES(1);
1935                 break;
1936         case 4:
1937                 gb_addr_config |= NUM_PIPES(2);
1938                 break;
1939         case 8:
1940                 gb_addr_config |= NUM_PIPES(3);
1941                 break;
1942         }
1943
1944         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1945         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1946         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1947         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1948         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1949         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1950
1951         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1952                 gb_addr_config |= ROW_SIZE(2);
1953         else
1954                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1955
1956         if (rdev->ddev->pdev->device == 0x689e) {
1957                 u32 efuse_straps_4;
1958                 u32 efuse_straps_3;
1959                 u8 efuse_box_bit_131_124;
1960
1961                 WREG32(RCU_IND_INDEX, 0x204);
1962                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1963                 WREG32(RCU_IND_INDEX, 0x203);
1964                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1965                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1966
1967                 switch(efuse_box_bit_131_124) {
1968                 case 0x00:
1969                         gb_backend_map = 0x76543210;
1970                         break;
1971                 case 0x55:
1972                         gb_backend_map = 0x77553311;
1973                         break;
1974                 case 0x56:
1975                         gb_backend_map = 0x77553300;
1976                         break;
1977                 case 0x59:
1978                         gb_backend_map = 0x77552211;
1979                         break;
1980                 case 0x66:
1981                         gb_backend_map = 0x77443300;
1982                         break;
1983                 case 0x99:
1984                         gb_backend_map = 0x66552211;
1985                         break;
1986                 case 0x5a:
1987                         gb_backend_map = 0x77552200;
1988                         break;
1989                 case 0xaa:
1990                         gb_backend_map = 0x66442200;
1991                         break;
1992                 case 0x95:
1993                         gb_backend_map = 0x66553311;
1994                         break;
1995                 default:
1996                         DRM_ERROR("bad backend map, using default\n");
1997                         gb_backend_map =
1998                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1999                                                                        rdev->config.evergreen.max_tile_pipes,
2000                                                                        rdev->config.evergreen.max_backends,
2001                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2002                                                                    rdev->config.evergreen.max_backends) &
2003                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2004                         break;
2005                 }
2006         } else if (rdev->ddev->pdev->device == 0x68b9) {
2007                 u32 efuse_straps_3;
2008                 u8 efuse_box_bit_127_124;
2009
2010                 WREG32(RCU_IND_INDEX, 0x203);
2011                 efuse_straps_3 = RREG32(RCU_IND_DATA);
2012                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
2013
2014                 switch(efuse_box_bit_127_124) {
2015                 case 0x0:
2016                         gb_backend_map = 0x00003210;
2017                         break;
2018                 case 0x5:
2019                 case 0x6:
2020                 case 0x9:
2021                 case 0xa:
2022                         gb_backend_map = 0x00003311;
2023                         break;
2024                 default:
2025                         DRM_ERROR("bad backend map, using default\n");
2026                         gb_backend_map =
2027                                 evergreen_get_tile_pipe_to_backend_map(rdev,
2028                                                                        rdev->config.evergreen.max_tile_pipes,
2029                                                                        rdev->config.evergreen.max_backends,
2030                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2031                                                                    rdev->config.evergreen.max_backends) &
2032                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2033                         break;
2034                 }
2035         } else {
2036                 switch (rdev->family) {
2037                 case CHIP_CYPRESS:
2038                 case CHIP_HEMLOCK:
2039                 case CHIP_BARTS:
2040                         gb_backend_map = 0x66442200;
2041                         break;
2042                 case CHIP_JUNIPER:
2043                         gb_backend_map = 0x00002200;
2044                         break;
2045                 default:
2046                         gb_backend_map =
2047                                 evergreen_get_tile_pipe_to_backend_map(rdev,
2048                                                                        rdev->config.evergreen.max_tile_pipes,
2049                                                                        rdev->config.evergreen.max_backends,
2050                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2051                                                                          rdev->config.evergreen.max_backends) &
2052                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2053                 }
2054         }
2055
2056         /* setup tiling info dword.  gb_addr_config is not adequate since it does
2057          * not have bank info, so create a custom tiling dword.
2058          * bits 3:0   num_pipes
2059          * bits 7:4   num_banks
2060          * bits 11:8  group_size
2061          * bits 15:12 row_size
2062          */
2063         rdev->config.evergreen.tile_config = 0;
2064         switch (rdev->config.evergreen.max_tile_pipes) {
2065         case 1:
2066         default:
2067                 rdev->config.evergreen.tile_config |= (0 << 0);
2068                 break;
2069         case 2:
2070                 rdev->config.evergreen.tile_config |= (1 << 0);
2071                 break;
2072         case 4:
2073                 rdev->config.evergreen.tile_config |= (2 << 0);
2074                 break;
2075         case 8:
2076                 rdev->config.evergreen.tile_config |= (3 << 0);
2077                 break;
2078         }
2079         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2080         if (rdev->flags & RADEON_IS_IGP)
2081                 rdev->config.evergreen.tile_config |= 1 << 4;
2082         else {
2083                 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
2084                 case 0: /* four banks */
2085                         rdev->config.evergreen.tile_config |= 0 << 4;
2086                         break;
2087                 case 1: /* eight banks */
2088                         rdev->config.evergreen.tile_config |= 1 << 4;
2089                         break;
2090                 case 2: /* sixteen banks */
2091                 default:
2092                         rdev->config.evergreen.tile_config |= 2 << 4;
2093                         break;
2094                 }
2095         }
2096         rdev->config.evergreen.tile_config |=
2097                 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2098         rdev->config.evergreen.tile_config |=
2099                 ((gb_addr_config & 0x30000000) >> 28) << 12;
2100
2101         rdev->config.evergreen.backend_map = gb_backend_map;
2102         WREG32(GB_BACKEND_MAP, gb_backend_map);
2103         WREG32(GB_ADDR_CONFIG, gb_addr_config);
2104         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2105         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2106
2107         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2108         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2109
2110         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2111                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2112                 u32 sp = cc_gc_shader_pipe_config;
2113                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2114
2115                 if (i == num_shader_engines) {
2116                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2117                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2118                 }
2119
2120                 WREG32(GRBM_GFX_INDEX, gfx);
2121                 WREG32(RLC_GFX_INDEX, gfx);
2122
2123                 WREG32(CC_RB_BACKEND_DISABLE, rb);
2124                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2125                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2126                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2127         }
2128
2129         grbm_gfx_index = INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES;
2130         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2131         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2132
2133         WREG32(CGTS_SYS_TCC_DISABLE, 0);
2134         WREG32(CGTS_TCC_DISABLE, 0);
2135         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2136         WREG32(CGTS_USER_TCC_DISABLE, 0);
2137
2138         /* set HW defaults for 3D engine */
2139         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2140                                      ROQ_IB2_START(0x2b)));
2141
2142         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2143
2144         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2145                              SYNC_GRADIENT |
2146                              SYNC_WALKER |
2147                              SYNC_ALIGNER));
2148
2149         sx_debug_1 = RREG32(SX_DEBUG_1);
2150         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2151         WREG32(SX_DEBUG_1, sx_debug_1);
2152
2153
2154         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2155         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2156         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2157         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2158
2159         if (rdev->family <= CHIP_SUMO2)
2160                 WREG32(SMX_SAR_CTL0, 0x00010000);
2161
2162         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2163                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2164                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2165
2166         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2167                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2168                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2169
2170         WREG32(VGT_NUM_INSTANCES, 1);
2171         WREG32(SPI_CONFIG_CNTL, 0);
2172         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2173         WREG32(CP_PERFMON_CNTL, 0);
2174
2175         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2176                                   FETCH_FIFO_HIWATER(0x4) |
2177                                   DONE_FIFO_HIWATER(0xe0) |
2178                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2179
2180         sq_config = RREG32(SQ_CONFIG);
2181         sq_config &= ~(PS_PRIO(3) |
2182                        VS_PRIO(3) |
2183                        GS_PRIO(3) |
2184                        ES_PRIO(3));
2185         sq_config |= (VC_ENABLE |
2186                       EXPORT_SRC_C |
2187                       PS_PRIO(0) |
2188                       VS_PRIO(1) |
2189                       GS_PRIO(2) |
2190                       ES_PRIO(3));
2191
2192         switch (rdev->family) {
2193         case CHIP_CEDAR:
2194         case CHIP_PALM:
2195         case CHIP_SUMO:
2196         case CHIP_SUMO2:
2197         case CHIP_CAICOS:
2198                 /* no vertex cache */
2199                 sq_config &= ~VC_ENABLE;
2200                 break;
2201         default:
2202                 break;
2203         }
2204
2205         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2206
2207         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2208         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2209         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2210         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2211         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2212         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2213         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2214
2215         switch (rdev->family) {
2216         case CHIP_CEDAR:
2217         case CHIP_PALM:
2218         case CHIP_SUMO:
2219         case CHIP_SUMO2:
2220                 ps_thread_count = 96;
2221                 break;
2222         default:
2223                 ps_thread_count = 128;
2224                 break;
2225         }
2226
2227         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2228         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2229         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2230         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2231         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2232         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2233
2234         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2235         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2236         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2237         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2238         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2239         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2240
2241         WREG32(SQ_CONFIG, sq_config);
2242         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2243         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2244         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2245         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2246         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2247         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2248         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2249         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2250         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2251         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2252
2253         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2254                                           FORCE_EOV_MAX_REZ_CNT(255)));
2255
2256         switch (rdev->family) {
2257         case CHIP_CEDAR:
2258         case CHIP_PALM:
2259         case CHIP_SUMO:
2260         case CHIP_SUMO2:
2261         case CHIP_CAICOS:
2262                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2263                 break;
2264         default:
2265                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2266                 break;
2267         }
2268         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2269         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2270
2271         WREG32(VGT_GS_VERTEX_REUSE, 16);
2272         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2273         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2274
2275         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2276         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2277
2278         WREG32(CB_PERF_CTR0_SEL_0, 0);
2279         WREG32(CB_PERF_CTR0_SEL_1, 0);
2280         WREG32(CB_PERF_CTR1_SEL_0, 0);
2281         WREG32(CB_PERF_CTR1_SEL_1, 0);
2282         WREG32(CB_PERF_CTR2_SEL_0, 0);
2283         WREG32(CB_PERF_CTR2_SEL_1, 0);
2284         WREG32(CB_PERF_CTR3_SEL_0, 0);
2285         WREG32(CB_PERF_CTR3_SEL_1, 0);
2286
2287         /* clear render buffer base addresses */
2288         WREG32(CB_COLOR0_BASE, 0);
2289         WREG32(CB_COLOR1_BASE, 0);
2290         WREG32(CB_COLOR2_BASE, 0);
2291         WREG32(CB_COLOR3_BASE, 0);
2292         WREG32(CB_COLOR4_BASE, 0);
2293         WREG32(CB_COLOR5_BASE, 0);
2294         WREG32(CB_COLOR6_BASE, 0);
2295         WREG32(CB_COLOR7_BASE, 0);
2296         WREG32(CB_COLOR8_BASE, 0);
2297         WREG32(CB_COLOR9_BASE, 0);
2298         WREG32(CB_COLOR10_BASE, 0);
2299         WREG32(CB_COLOR11_BASE, 0);
2300
2301         /* set the shader const cache sizes to 0 */
2302         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2303                 WREG32(i, 0);
2304         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2305                 WREG32(i, 0);
2306
2307         tmp = RREG32(HDP_MISC_CNTL);
2308         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2309         WREG32(HDP_MISC_CNTL, tmp);
2310
2311         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2312         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2313
2314         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2315
2316         udelay(50);
2317
2318 }
2319
2320 int evergreen_mc_init(struct radeon_device *rdev)
2321 {
2322         u32 tmp;
2323         int chansize, numchan;
2324
2325         /* Get VRAM informations */
2326         rdev->mc.vram_is_ddr = true;
2327         if (rdev->flags & RADEON_IS_IGP)
2328                 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2329         else
2330                 tmp = RREG32(MC_ARB_RAMCFG);
2331         if (tmp & CHANSIZE_OVERRIDE) {
2332                 chansize = 16;
2333         } else if (tmp & CHANSIZE_MASK) {
2334                 chansize = 64;
2335         } else {
2336                 chansize = 32;
2337         }
2338         tmp = RREG32(MC_SHARED_CHMAP);
2339         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2340         case 0:
2341         default:
2342                 numchan = 1;
2343                 break;
2344         case 1:
2345                 numchan = 2;
2346                 break;
2347         case 2:
2348                 numchan = 4;
2349                 break;
2350         case 3:
2351                 numchan = 8;
2352                 break;
2353         }
2354         rdev->mc.vram_width = numchan * chansize;
2355         /* Could aper size report 0 ? */
2356         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2357         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2358         /* Setup GPU memory space */
2359         if (rdev->flags & RADEON_IS_IGP) {
2360                 /* size in bytes on fusion */
2361                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2362                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2363         } else {
2364                 /* size in MB on evergreen */
2365                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2366                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2367         }
2368         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2369         r700_vram_gtt_location(rdev, &rdev->mc);
2370         radeon_update_bandwidth_info(rdev);
2371
2372         return 0;
2373 }
2374
2375 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2376 {
2377         u32 srbm_status;
2378         u32 grbm_status;
2379         u32 grbm_status_se0, grbm_status_se1;
2380         struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2381         int r;
2382
2383         srbm_status = RREG32(SRBM_STATUS);
2384         grbm_status = RREG32(GRBM_STATUS);
2385         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2386         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2387         if (!(grbm_status & GUI_ACTIVE)) {
2388                 r100_gpu_lockup_update(lockup, &rdev->cp);
2389                 return false;
2390         }
2391         /* force CP activities */
2392         r = radeon_ring_lock(rdev, 2);
2393         if (!r) {
2394                 /* PACKET2 NOP */
2395                 radeon_ring_write(rdev, 0x80000000);
2396                 radeon_ring_write(rdev, 0x80000000);
2397                 radeon_ring_unlock_commit(rdev);
2398         }
2399         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2400         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2401 }
2402
2403 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2404 {
2405         struct evergreen_mc_save save;
2406         u32 grbm_reset = 0;
2407
2408         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2409                 return 0;
2410
2411         dev_info(rdev->dev, "GPU softreset \n");
2412         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2413                 RREG32(GRBM_STATUS));
2414         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2415                 RREG32(GRBM_STATUS_SE0));
2416         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2417                 RREG32(GRBM_STATUS_SE1));
2418         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2419                 RREG32(SRBM_STATUS));
2420         evergreen_mc_stop(rdev, &save);
2421         if (evergreen_mc_wait_for_idle(rdev)) {
2422                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2423         }
2424         /* Disable CP parsing/prefetching */
2425         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2426
2427         /* reset all the gfx blocks */
2428         grbm_reset = (SOFT_RESET_CP |
2429                       SOFT_RESET_CB |
2430                       SOFT_RESET_DB |
2431                       SOFT_RESET_PA |
2432                       SOFT_RESET_SC |
2433                       SOFT_RESET_SPI |
2434                       SOFT_RESET_SH |
2435                       SOFT_RESET_SX |
2436                       SOFT_RESET_TC |
2437                       SOFT_RESET_TA |
2438                       SOFT_RESET_VC |
2439                       SOFT_RESET_VGT);
2440
2441         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2442         WREG32(GRBM_SOFT_RESET, grbm_reset);
2443         (void)RREG32(GRBM_SOFT_RESET);
2444         udelay(50);
2445         WREG32(GRBM_SOFT_RESET, 0);
2446         (void)RREG32(GRBM_SOFT_RESET);
2447         /* Wait a little for things to settle down */
2448         udelay(50);
2449         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2450                 RREG32(GRBM_STATUS));
2451         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2452                 RREG32(GRBM_STATUS_SE0));
2453         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2454                 RREG32(GRBM_STATUS_SE1));
2455         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2456                 RREG32(SRBM_STATUS));
2457         evergreen_mc_resume(rdev, &save);
2458         return 0;
2459 }
2460
2461 int evergreen_asic_reset(struct radeon_device *rdev)
2462 {
2463         return evergreen_gpu_soft_reset(rdev);
2464 }
2465
2466 /* Interrupts */
2467
2468 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2469 {
2470         switch (crtc) {
2471         case 0:
2472                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2473         case 1:
2474                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2475         case 2:
2476                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2477         case 3:
2478                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2479         case 4:
2480                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2481         case 5:
2482                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2483         default:
2484                 return 0;
2485         }
2486 }
2487
2488 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2489 {
2490         u32 tmp;
2491
2492         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2493         WREG32(GRBM_INT_CNTL, 0);
2494         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2495         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2496         if (rdev->num_crtc >= 4) {
2497                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2498                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2499         }
2500         if (rdev->num_crtc >= 6) {
2501                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2502                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2503         }
2504
2505         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2506         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2507         if (rdev->num_crtc >= 4) {
2508                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2509                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2510         }
2511         if (rdev->num_crtc >= 6) {
2512                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2513                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2514         }
2515
2516         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2517         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2518
2519         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2520         WREG32(DC_HPD1_INT_CONTROL, tmp);
2521         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2522         WREG32(DC_HPD2_INT_CONTROL, tmp);
2523         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2524         WREG32(DC_HPD3_INT_CONTROL, tmp);
2525         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2526         WREG32(DC_HPD4_INT_CONTROL, tmp);
2527         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2528         WREG32(DC_HPD5_INT_CONTROL, tmp);
2529         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2530         WREG32(DC_HPD6_INT_CONTROL, tmp);
2531
2532 }
2533
2534 int evergreen_irq_set(struct radeon_device *rdev)
2535 {
2536         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2537         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2538         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2539         u32 grbm_int_cntl = 0;
2540         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2541
2542         if (!rdev->irq.installed) {
2543                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2544                 return -EINVAL;
2545         }
2546         /* don't enable anything if the ih is disabled */
2547         if (!rdev->ih.enabled) {
2548                 r600_disable_interrupts(rdev);
2549                 /* force the active interrupt state to all disabled */
2550                 evergreen_disable_interrupt_state(rdev);
2551                 return 0;
2552         }
2553
2554         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2555         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2556         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2557         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2558         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2559         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2560
2561         if (rdev->irq.sw_int) {
2562                 DRM_DEBUG("evergreen_irq_set: sw int\n");
2563                 cp_int_cntl |= RB_INT_ENABLE;
2564                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2565         }
2566         if (rdev->irq.crtc_vblank_int[0] ||
2567             rdev->irq.pflip[0]) {
2568                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2569                 crtc1 |= VBLANK_INT_MASK;
2570         }
2571         if (rdev->irq.crtc_vblank_int[1] ||
2572             rdev->irq.pflip[1]) {
2573                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2574                 crtc2 |= VBLANK_INT_MASK;
2575         }
2576         if (rdev->irq.crtc_vblank_int[2] ||
2577             rdev->irq.pflip[2]) {
2578                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2579                 crtc3 |= VBLANK_INT_MASK;
2580         }
2581         if (rdev->irq.crtc_vblank_int[3] ||
2582             rdev->irq.pflip[3]) {
2583                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2584                 crtc4 |= VBLANK_INT_MASK;
2585         }
2586         if (rdev->irq.crtc_vblank_int[4] ||
2587             rdev->irq.pflip[4]) {
2588                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2589                 crtc5 |= VBLANK_INT_MASK;
2590         }
2591         if (rdev->irq.crtc_vblank_int[5] ||
2592             rdev->irq.pflip[5]) {
2593                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2594                 crtc6 |= VBLANK_INT_MASK;
2595         }
2596         if (rdev->irq.hpd[0]) {
2597                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2598                 hpd1 |= DC_HPDx_INT_EN;
2599         }
2600         if (rdev->irq.hpd[1]) {
2601                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2602                 hpd2 |= DC_HPDx_INT_EN;
2603         }
2604         if (rdev->irq.hpd[2]) {
2605                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2606                 hpd3 |= DC_HPDx_INT_EN;
2607         }
2608         if (rdev->irq.hpd[3]) {
2609                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2610                 hpd4 |= DC_HPDx_INT_EN;
2611         }
2612         if (rdev->irq.hpd[4]) {
2613                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2614                 hpd5 |= DC_HPDx_INT_EN;
2615         }
2616         if (rdev->irq.hpd[5]) {
2617                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2618                 hpd6 |= DC_HPDx_INT_EN;
2619         }
2620         if (rdev->irq.gui_idle) {
2621                 DRM_DEBUG("gui idle\n");
2622                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2623         }
2624
2625         WREG32(CP_INT_CNTL, cp_int_cntl);
2626         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2627
2628         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2629         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2630         if (rdev->num_crtc >= 4) {
2631                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2632                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2633         }
2634         if (rdev->num_crtc >= 6) {
2635                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2636                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2637         }
2638
2639         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2640         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2641         if (rdev->num_crtc >= 4) {
2642                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2643                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2644         }
2645         if (rdev->num_crtc >= 6) {
2646                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2647                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2648         }
2649
2650         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2651         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2652         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2653         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2654         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2655         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2656
2657         return 0;
2658 }
2659
2660 static void evergreen_irq_ack(struct radeon_device *rdev)
2661 {
2662         u32 tmp;
2663
2664         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2665         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2666         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2667         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2668         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2669         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2670         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2671         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2672         if (rdev->num_crtc >= 4) {
2673                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2674                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2675         }
2676         if (rdev->num_crtc >= 6) {
2677                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2678                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2679         }
2680
2681         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2682                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2683         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2684                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2685         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2686                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2687         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2688                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2689         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2690                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2691         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2692                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2693
2694         if (rdev->num_crtc >= 4) {
2695                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2696                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2697                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2698                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2699                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2700                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2701                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2702                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2703                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2704                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2705                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2706                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2707         }
2708
2709         if (rdev->num_crtc >= 6) {
2710                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2711                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2712                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2713                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2714                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2715                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2716                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2717                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2718                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2719                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2720                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2721                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2722         }
2723
2724         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2725                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2726                 tmp |= DC_HPDx_INT_ACK;
2727                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2728         }
2729         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2730                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2731                 tmp |= DC_HPDx_INT_ACK;
2732                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2733         }
2734         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2735                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2736                 tmp |= DC_HPDx_INT_ACK;
2737                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2738         }
2739         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2740                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2741                 tmp |= DC_HPDx_INT_ACK;
2742                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2743         }
2744         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2745                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2746                 tmp |= DC_HPDx_INT_ACK;
2747                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2748         }
2749         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2750                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2751                 tmp |= DC_HPDx_INT_ACK;
2752                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2753         }
2754 }
2755
2756 void evergreen_irq_disable(struct radeon_device *rdev)
2757 {
2758         r600_disable_interrupts(rdev);
2759         /* Wait and acknowledge irq */
2760         mdelay(1);
2761         evergreen_irq_ack(rdev);
2762         evergreen_disable_interrupt_state(rdev);
2763 }
2764
2765 void evergreen_irq_suspend(struct radeon_device *rdev)
2766 {
2767         evergreen_irq_disable(rdev);
2768         r600_rlc_stop(rdev);
2769 }
2770
2771 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2772 {
2773         u32 wptr, tmp;
2774
2775         if (rdev->wb.enabled)
2776                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2777         else
2778                 wptr = RREG32(IH_RB_WPTR);
2779
2780         if (wptr & RB_OVERFLOW) {
2781                 /* When a ring buffer overflow happen start parsing interrupt
2782                  * from the last not overwritten vector (wptr + 16). Hopefully
2783                  * this should allow us to catchup.
2784                  */
2785                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2786                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2787                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2788                 tmp = RREG32(IH_RB_CNTL);
2789                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2790                 WREG32(IH_RB_CNTL, tmp);
2791         }
2792         return (wptr & rdev->ih.ptr_mask);
2793 }
2794
2795 int evergreen_irq_process(struct radeon_device *rdev)
2796 {
2797         u32 wptr;
2798         u32 rptr;
2799         u32 src_id, src_data;
2800         u32 ring_index;
2801         unsigned long flags;
2802         bool queue_hotplug = false;
2803
2804         if (!rdev->ih.enabled || rdev->shutdown)
2805                 return IRQ_NONE;
2806
2807         wptr = evergreen_get_ih_wptr(rdev);
2808         rptr = rdev->ih.rptr;
2809         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2810
2811         spin_lock_irqsave(&rdev->ih.lock, flags);
2812         if (rptr == wptr) {
2813                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2814                 return IRQ_NONE;
2815         }
2816 restart_ih:
2817         /* Order reading of wptr vs. reading of IH ring data */
2818         rmb();
2819
2820         /* display interrupts */
2821         evergreen_irq_ack(rdev);
2822
2823         rdev->ih.wptr = wptr;
2824         while (rptr != wptr) {
2825                 /* wptr/rptr are in bytes! */
2826                 ring_index = rptr / 4;
2827                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2828                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2829
2830                 switch (src_id) {
2831                 case 1: /* D1 vblank/vline */
2832                         switch (src_data) {
2833                         case 0: /* D1 vblank */
2834                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2835                                         if (rdev->irq.crtc_vblank_int[0]) {
2836                                                 drm_handle_vblank(rdev->ddev, 0);
2837                                                 rdev->pm.vblank_sync = true;
2838                                                 wake_up(&rdev->irq.vblank_queue);
2839                                         }
2840                                         if (rdev->irq.pflip[0])
2841                                                 radeon_crtc_handle_flip(rdev, 0);
2842                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2843                                         DRM_DEBUG("IH: D1 vblank\n");
2844                                 }
2845                                 break;
2846                         case 1: /* D1 vline */
2847                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2848                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2849                                         DRM_DEBUG("IH: D1 vline\n");
2850                                 }
2851                                 break;
2852                         default:
2853                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2854                                 break;
2855                         }
2856                         break;
2857                 case 2: /* D2 vblank/vline */
2858                         switch (src_data) {
2859                         case 0: /* D2 vblank */
2860                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2861                                         if (rdev->irq.crtc_vblank_int[1]) {
2862                                                 drm_handle_vblank(rdev->ddev, 1);
2863                                                 rdev->pm.vblank_sync = true;
2864                                                 wake_up(&rdev->irq.vblank_queue);
2865                                         }
2866                                         if (rdev->irq.pflip[1])
2867                                                 radeon_crtc_handle_flip(rdev, 1);
2868                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2869                                         DRM_DEBUG("IH: D2 vblank\n");
2870                                 }
2871                                 break;
2872                         case 1: /* D2 vline */
2873                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2874                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2875                                         DRM_DEBUG("IH: D2 vline\n");
2876                                 }
2877                                 break;
2878                         default:
2879                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2880                                 break;
2881                         }
2882                         break;
2883                 case 3: /* D3 vblank/vline */
2884                         switch (src_data) {
2885                         case 0: /* D3 vblank */
2886                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2887                                         if (rdev->irq.crtc_vblank_int[2]) {
2888                                                 drm_handle_vblank(rdev->ddev, 2);
2889                                                 rdev->pm.vblank_sync = true;
2890                                                 wake_up(&rdev->irq.vblank_queue);
2891                                         }
2892                                         if (rdev->irq.pflip[2])
2893                                                 radeon_crtc_handle_flip(rdev, 2);
2894                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2895                                         DRM_DEBUG("IH: D3 vblank\n");
2896                                 }
2897                                 break;
2898                         case 1: /* D3 vline */
2899                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2900                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2901                                         DRM_DEBUG("IH: D3 vline\n");
2902                                 }
2903                                 break;
2904                         default:
2905                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2906                                 break;
2907                         }
2908                         break;
2909                 case 4: /* D4 vblank/vline */
2910                         switch (src_data) {
2911                         case 0: /* D4 vblank */
2912                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2913                                         if (rdev->irq.crtc_vblank_int[3]) {
2914                                                 drm_handle_vblank(rdev->ddev, 3);
2915                                                 rdev->pm.vblank_sync = true;
2916                                                 wake_up(&rdev->irq.vblank_queue);
2917                                         }
2918                                         if (rdev->irq.pflip[3])
2919                                                 radeon_crtc_handle_flip(rdev, 3);
2920                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2921                                         DRM_DEBUG("IH: D4 vblank\n");
2922                                 }
2923                                 break;
2924                         case 1: /* D4 vline */
2925                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2926                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2927                                         DRM_DEBUG("IH: D4 vline\n");
2928                                 }
2929                                 break;
2930                         default:
2931                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2932                                 break;
2933                         }
2934                         break;
2935                 case 5: /* D5 vblank/vline */
2936                         switch (src_data) {
2937                         case 0: /* D5 vblank */
2938                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2939                                         if (rdev->irq.crtc_vblank_int[4]) {
2940                                                 drm_handle_vblank(rdev->ddev, 4);
2941                                                 rdev->pm.vblank_sync = true;
2942                                                 wake_up(&rdev->irq.vblank_queue);
2943                                         }
2944                                         if (rdev->irq.pflip[4])
2945                                                 radeon_crtc_handle_flip(rdev, 4);
2946                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2947                                         DRM_DEBUG("IH: D5 vblank\n");
2948                                 }
2949                                 break;
2950                         case 1: /* D5 vline */
2951                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2952                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2953                                         DRM_DEBUG("IH: D5 vline\n");
2954                                 }
2955                                 break;
2956                         default:
2957                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2958                                 break;
2959                         }
2960                         break;
2961                 case 6: /* D6 vblank/vline */
2962                         switch (src_data) {
2963                         case 0: /* D6 vblank */
2964                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2965                                         if (rdev->irq.crtc_vblank_int[5]) {
2966                                                 drm_handle_vblank(rdev->ddev, 5);
2967                                                 rdev->pm.vblank_sync = true;
2968                                                 wake_up(&rdev->irq.vblank_queue);
2969                                         }
2970                                         if (rdev->irq.pflip[5])
2971                                                 radeon_crtc_handle_flip(rdev, 5);
2972                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2973                                         DRM_DEBUG("IH: D6 vblank\n");
2974                                 }
2975                                 break;
2976                         case 1: /* D6 vline */
2977                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2978                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2979                                         DRM_DEBUG("IH: D6 vline\n");
2980                                 }
2981                                 break;
2982                         default:
2983                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2984                                 break;
2985                         }
2986                         break;
2987                 case 42: /* HPD hotplug */
2988                         switch (src_data) {
2989                         case 0:
2990                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2991                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2992                                         queue_hotplug = true;
2993                                         DRM_DEBUG("IH: HPD1\n");
2994                                 }
2995                                 break;
2996                         case 1:
2997                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2998                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2999                                         queue_hotplug = true;
3000                                         DRM_DEBUG("IH: HPD2\n");
3001                                 }
3002                                 break;
3003                         case 2:
3004                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3005                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3006                                         queue_hotplug = true;
3007                                         DRM_DEBUG("IH: HPD3\n");
3008                                 }
3009                                 break;
3010                         case 3:
3011                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3012                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3013                                         queue_hotplug = true;
3014                                         DRM_DEBUG("IH: HPD4\n");
3015                                 }
3016                                 break;
3017                         case 4:
3018                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3019                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3020                                         queue_hotplug = true;
3021                                         DRM_DEBUG("IH: HPD5\n");
3022                                 }
3023                                 break;
3024                         case 5:
3025                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3026                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3027                                         queue_hotplug = true;
3028                                         DRM_DEBUG("IH: HPD6\n");
3029                                 }
3030                                 break;
3031                         default:
3032                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3033                                 break;
3034                         }
3035                         break;
3036                 case 176: /* CP_INT in ring buffer */
3037                 case 177: /* CP_INT in IB1 */
3038                 case 178: /* CP_INT in IB2 */
3039                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3040                         radeon_fence_process(rdev);
3041                         break;
3042                 case 181: /* CP EOP event */
3043                         DRM_DEBUG("IH: CP EOP\n");
3044                         radeon_fence_process(rdev);
3045                         break;
3046                 case 233: /* GUI IDLE */
3047                         DRM_DEBUG("IH: GUI idle\n");
3048                         rdev->pm.gui_idle = true;
3049                         wake_up(&rdev->irq.idle_queue);
3050                         break;
3051                 default:
3052                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3053                         break;
3054                 }
3055
3056                 /* wptr/rptr are in bytes! */
3057                 rptr += 16;
3058                 rptr &= rdev->ih.ptr_mask;
3059         }
3060         /* make sure wptr hasn't changed while processing */
3061         wptr = evergreen_get_ih_wptr(rdev);
3062         if (wptr != rdev->ih.wptr)
3063                 goto restart_ih;
3064         if (queue_hotplug)
3065                 schedule_work(&rdev->hotplug_work);
3066         rdev->ih.rptr = rptr;
3067         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3068         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3069         return IRQ_HANDLED;
3070 }
3071
3072 static int evergreen_startup(struct radeon_device *rdev)
3073 {
3074         int r;
3075
3076         /* enable pcie gen2 link */
3077         evergreen_pcie_gen2_enable(rdev);
3078
3079         if (ASIC_IS_DCE5(rdev)) {
3080                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3081                         r = ni_init_microcode(rdev);
3082                         if (r) {
3083                                 DRM_ERROR("Failed to load firmware!\n");
3084                                 return r;
3085                         }
3086                 }
3087                 r = ni_mc_load_microcode(rdev);
3088                 if (r) {
3089                         DRM_ERROR("Failed to load MC firmware!\n");
3090                         return r;
3091                 }
3092         } else {
3093                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3094                         r = r600_init_microcode(rdev);
3095                         if (r) {
3096                                 DRM_ERROR("Failed to load firmware!\n");
3097                                 return r;
3098                         }
3099                 }
3100         }
3101
3102         r = r600_vram_scratch_init(rdev);
3103         if (r)
3104                 return r;
3105
3106         evergreen_mc_program(rdev);
3107         if (rdev->flags & RADEON_IS_AGP) {
3108                 evergreen_agp_enable(rdev);
3109         } else {
3110                 r = evergreen_pcie_gart_enable(rdev);
3111                 if (r)
3112                         return r;
3113         }
3114         evergreen_gpu_init(rdev);
3115
3116         r = evergreen_blit_init(rdev);
3117         if (r) {
3118                 r600_blit_fini(rdev);
3119                 rdev->asic->copy = NULL;
3120                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3121         }
3122
3123         /* allocate wb buffer */
3124         r = radeon_wb_init(rdev);
3125         if (r)
3126                 return r;
3127
3128         /* Enable IRQ */
3129         r = r600_irq_init(rdev);
3130         if (r) {
3131                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3132                 radeon_irq_kms_fini(rdev);
3133                 return r;
3134         }
3135         evergreen_irq_set(rdev);
3136
3137         r = radeon_ring_init(rdev, rdev->cp.ring_size);
3138         if (r)
3139                 return r;
3140         r = evergreen_cp_load_microcode(rdev);
3141         if (r)
3142                 return r;
3143         r = evergreen_cp_resume(rdev);
3144         if (r)
3145                 return r;
3146
3147         return 0;
3148 }
3149
3150 int evergreen_resume(struct radeon_device *rdev)
3151 {
3152         int r;
3153
3154         /* reset the asic, the gfx blocks are often in a bad state
3155          * after the driver is unloaded or after a resume
3156          */
3157         if (radeon_asic_reset(rdev))
3158                 dev_warn(rdev->dev, "GPU reset failed !\n");
3159         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3160          * posting will perform necessary task to bring back GPU into good
3161          * shape.
3162          */
3163         /* post card */
3164         atom_asic_init(rdev->mode_info.atom_context);
3165
3166         r = evergreen_startup(rdev);
3167         if (r) {
3168                 DRM_ERROR("evergreen startup failed on resume\n");
3169                 return r;
3170         }
3171
3172         r = r600_ib_test(rdev);
3173         if (r) {
3174                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3175                 return r;
3176         }
3177
3178         return r;
3179
3180 }
3181
3182 int evergreen_suspend(struct radeon_device *rdev)
3183 {
3184         /* FIXME: we should wait for ring to be empty */
3185         r700_cp_stop(rdev);
3186         rdev->cp.ready = false;
3187         evergreen_irq_suspend(rdev);
3188         radeon_wb_disable(rdev);
3189         evergreen_pcie_gart_disable(rdev);
3190         r600_blit_suspend(rdev);
3191
3192         return 0;
3193 }
3194
3195 /* Plan is to move initialization in that function and use
3196  * helper function so that radeon_device_init pretty much
3197  * do nothing more than calling asic specific function. This
3198  * should also allow to remove a bunch of callback function
3199  * like vram_info.
3200  */
3201 int evergreen_init(struct radeon_device *rdev)
3202 {
3203         int r;
3204
3205         /* This don't do much */
3206         r = radeon_gem_init(rdev);
3207         if (r)
3208                 return r;
3209         /* Read BIOS */
3210         if (!radeon_get_bios(rdev)) {
3211                 if (ASIC_IS_AVIVO(rdev))
3212                         return -EINVAL;
3213         }
3214         /* Must be an ATOMBIOS */
3215         if (!rdev->is_atom_bios) {
3216                 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3217                 return -EINVAL;
3218         }
3219         r = radeon_atombios_init(rdev);
3220         if (r)
3221                 return r;
3222         /* reset the asic, the gfx blocks are often in a bad state
3223          * after the driver is unloaded or after a resume
3224          */
3225         if (radeon_asic_reset(rdev))
3226                 dev_warn(rdev->dev, "GPU reset failed !\n");
3227         /* Post card if necessary */
3228         if (!radeon_card_posted(rdev)) {
3229                 if (!rdev->bios) {
3230                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3231                         return -EINVAL;
3232                 }
3233                 DRM_INFO("GPU not posted. posting now...\n");
3234                 atom_asic_init(rdev->mode_info.atom_context);
3235         }
3236         /* Initialize scratch registers */
3237         r600_scratch_init(rdev);
3238         /* Initialize surface registers */
3239         radeon_surface_init(rdev);
3240         /* Initialize clocks */
3241         radeon_get_clock_info(rdev->ddev);
3242         /* Fence driver */
3243         r = radeon_fence_driver_init(rdev);
3244         if (r)
3245                 return r;
3246         /* initialize AGP */
3247         if (rdev->flags & RADEON_IS_AGP) {
3248                 r = radeon_agp_init(rdev);
3249                 if (r)
3250                         radeon_agp_disable(rdev);
3251         }
3252         /* initialize memory controller */
3253         r = evergreen_mc_init(rdev);
3254         if (r)
3255                 return r;
3256         /* Memory manager */
3257         r = radeon_bo_init(rdev);
3258         if (r)
3259                 return r;
3260
3261         r = radeon_irq_kms_init(rdev);
3262         if (r)
3263                 return r;
3264
3265         rdev->cp.ring_obj = NULL;
3266         r600_ring_init(rdev, 1024 * 1024);
3267
3268         rdev->ih.ring_obj = NULL;
3269         r600_ih_ring_init(rdev, 64 * 1024);
3270
3271         r = r600_pcie_gart_init(rdev);
3272         if (r)
3273                 return r;
3274
3275         rdev->accel_working = true;
3276         r = evergreen_startup(rdev);
3277         if (r) {
3278                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3279                 r700_cp_fini(rdev);
3280                 r600_irq_fini(rdev);
3281                 radeon_wb_fini(rdev);
3282                 radeon_irq_kms_fini(rdev);
3283                 evergreen_pcie_gart_fini(rdev);
3284                 rdev->accel_working = false;
3285         }
3286         if (rdev->accel_working) {
3287                 r = radeon_ib_pool_init(rdev);
3288                 if (r) {
3289                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3290                         rdev->accel_working = false;
3291                 }
3292                 r = r600_ib_test(rdev);
3293                 if (r) {
3294                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3295                         rdev->accel_working = false;
3296                 }
3297         }
3298
3299         /* Don't start up if the MC ucode is missing on BTC parts.
3300          * The default clocks and voltages before the MC ucode
3301          * is loaded are not suffient for advanced operations.
3302          */
3303         if (ASIC_IS_DCE5(rdev)) {
3304                 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3305                         DRM_ERROR("radeon: MC ucode required for NI+.\n");
3306                         return -EINVAL;
3307                 }
3308         }
3309
3310         return 0;
3311 }
3312
3313 void evergreen_fini(struct radeon_device *rdev)
3314 {
3315         r600_blit_fini(rdev);
3316         r700_cp_fini(rdev);
3317         r600_irq_fini(rdev);
3318         radeon_wb_fini(rdev);
3319         radeon_ib_pool_fini(rdev);
3320         radeon_irq_kms_fini(rdev);
3321         evergreen_pcie_gart_fini(rdev);
3322         r600_vram_scratch_fini(rdev);
3323         radeon_gem_fini(rdev);
3324         radeon_fence_driver_fini(rdev);
3325         radeon_agp_fini(rdev);
3326         radeon_bo_fini(rdev);
3327         radeon_atombios_fini(rdev);
3328         kfree(rdev->bios);
3329         rdev->bios = NULL;
3330 }
3331
3332 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3333 {
3334         u32 link_width_cntl, speed_cntl;
3335
3336         if (radeon_pcie_gen2 == 0)
3337                 return;
3338
3339         if (rdev->flags & RADEON_IS_IGP)
3340                 return;
3341
3342         if (!(rdev->flags & RADEON_IS_PCIE))
3343                 return;
3344
3345         /* x2 cards have a special sequence */
3346         if (ASIC_IS_X2(rdev))
3347                 return;
3348
3349         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3350         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3351             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3352
3353                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3354                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3355                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3356
3357                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3358                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3359                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3360
3361                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3362                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3363                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3364
3365                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3366                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3367                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3368
3369                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3370                 speed_cntl |= LC_GEN2_EN_STRAP;
3371                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3372
3373         } else {
3374                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3375                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3376                 if (1)
3377                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3378                 else
3379                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3380                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3381         }
3382 }