2e30160687c8224215d7bab7962cdf944eb56273
[pandora-kernel.git] / drivers / gpu / drm / radeon / evergreen.c
1 /*
2  * Copyright 2010 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include "drmP.h"
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
36
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
39
40 static void evergreen_gpu_init(struct radeon_device *rdev);
41 void evergreen_fini(struct radeon_device *rdev);
42 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
43
44 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
45 {
46         u16 ctl, v;
47         int cap, err;
48
49         cap = pci_pcie_cap(rdev->pdev);
50         if (!cap)
51                 return;
52
53         err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
54         if (err)
55                 return;
56
57         v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
58
59         /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
60          * to avoid hangs or perfomance issues
61          */
62         if ((v == 0) || (v == 6) || (v == 7)) {
63                 ctl &= ~PCI_EXP_DEVCTL_READRQ;
64                 ctl |= (2 << 12);
65                 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
66         }
67 }
68
69 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
70 {
71         /* enable the pflip int */
72         radeon_irq_kms_pflip_irq_get(rdev, crtc);
73 }
74
75 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
76 {
77         /* disable the pflip int */
78         radeon_irq_kms_pflip_irq_put(rdev, crtc);
79 }
80
81 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
82 {
83         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
84         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
85
86         /* Lock the graphics update lock */
87         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
88         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
89
90         /* update the scanout addresses */
91         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
92                upper_32_bits(crtc_base));
93         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
94                (u32)crtc_base);
95
96         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
97                upper_32_bits(crtc_base));
98         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
99                (u32)crtc_base);
100
101         /* Wait for update_pending to go high. */
102         while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
103         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
104
105         /* Unlock the lock, so double-buffering can take place inside vblank */
106         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
107         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
108
109         /* Return current update_pending status: */
110         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
111 }
112
113 /* get temperature in millidegrees */
114 int evergreen_get_temp(struct radeon_device *rdev)
115 {
116         u32 temp, toffset;
117         int actual_temp = 0;
118
119         if (rdev->family == CHIP_JUNIPER) {
120                 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
121                         TOFFSET_SHIFT;
122                 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
123                         TS0_ADC_DOUT_SHIFT;
124
125                 if (toffset & 0x100)
126                         actual_temp = temp / 2 - (0x200 - toffset);
127                 else
128                         actual_temp = temp / 2 + toffset;
129
130                 actual_temp = actual_temp * 1000;
131
132         } else {
133                 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
134                         ASIC_T_SHIFT;
135
136                 if (temp & 0x400)
137                         actual_temp = -256;
138                 else if (temp & 0x200)
139                         actual_temp = 255;
140                 else if (temp & 0x100) {
141                         actual_temp = temp & 0x1ff;
142                         actual_temp |= ~0x1ff;
143                 } else
144                         actual_temp = temp & 0xff;
145
146                 actual_temp = (actual_temp * 1000) / 2;
147         }
148
149         return actual_temp;
150 }
151
152 int sumo_get_temp(struct radeon_device *rdev)
153 {
154         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
155         int actual_temp = temp - 49;
156
157         return actual_temp * 1000;
158 }
159
160 void evergreen_pm_misc(struct radeon_device *rdev)
161 {
162         int req_ps_idx = rdev->pm.requested_power_state_index;
163         int req_cm_idx = rdev->pm.requested_clock_mode_index;
164         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
165         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
166
167         if (voltage->type == VOLTAGE_SW) {
168                 /* 0xff01 is a flag rather then an actual voltage */
169                 if (voltage->voltage == 0xff01)
170                         return;
171                 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
172                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
173                         rdev->pm.current_vddc = voltage->voltage;
174                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
175                 }
176                 /* 0xff01 is a flag rather then an actual voltage */
177                 if (voltage->vddci == 0xff01)
178                         return;
179                 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
180                         radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
181                         rdev->pm.current_vddci = voltage->vddci;
182                         DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
183                 }
184         }
185 }
186
187 void evergreen_pm_prepare(struct radeon_device *rdev)
188 {
189         struct drm_device *ddev = rdev->ddev;
190         struct drm_crtc *crtc;
191         struct radeon_crtc *radeon_crtc;
192         u32 tmp;
193
194         /* disable any active CRTCs */
195         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
196                 radeon_crtc = to_radeon_crtc(crtc);
197                 if (radeon_crtc->enabled) {
198                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
199                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
200                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
201                 }
202         }
203 }
204
205 void evergreen_pm_finish(struct radeon_device *rdev)
206 {
207         struct drm_device *ddev = rdev->ddev;
208         struct drm_crtc *crtc;
209         struct radeon_crtc *radeon_crtc;
210         u32 tmp;
211
212         /* enable any active CRTCs */
213         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
214                 radeon_crtc = to_radeon_crtc(crtc);
215                 if (radeon_crtc->enabled) {
216                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
217                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
218                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
219                 }
220         }
221 }
222
223 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
224 {
225         bool connected = false;
226
227         switch (hpd) {
228         case RADEON_HPD_1:
229                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
230                         connected = true;
231                 break;
232         case RADEON_HPD_2:
233                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
234                         connected = true;
235                 break;
236         case RADEON_HPD_3:
237                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
238                         connected = true;
239                 break;
240         case RADEON_HPD_4:
241                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
242                         connected = true;
243                 break;
244         case RADEON_HPD_5:
245                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
246                         connected = true;
247                 break;
248         case RADEON_HPD_6:
249                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
250                         connected = true;
251                         break;
252         default:
253                 break;
254         }
255
256         return connected;
257 }
258
259 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
260                                 enum radeon_hpd_id hpd)
261 {
262         u32 tmp;
263         bool connected = evergreen_hpd_sense(rdev, hpd);
264
265         switch (hpd) {
266         case RADEON_HPD_1:
267                 tmp = RREG32(DC_HPD1_INT_CONTROL);
268                 if (connected)
269                         tmp &= ~DC_HPDx_INT_POLARITY;
270                 else
271                         tmp |= DC_HPDx_INT_POLARITY;
272                 WREG32(DC_HPD1_INT_CONTROL, tmp);
273                 break;
274         case RADEON_HPD_2:
275                 tmp = RREG32(DC_HPD2_INT_CONTROL);
276                 if (connected)
277                         tmp &= ~DC_HPDx_INT_POLARITY;
278                 else
279                         tmp |= DC_HPDx_INT_POLARITY;
280                 WREG32(DC_HPD2_INT_CONTROL, tmp);
281                 break;
282         case RADEON_HPD_3:
283                 tmp = RREG32(DC_HPD3_INT_CONTROL);
284                 if (connected)
285                         tmp &= ~DC_HPDx_INT_POLARITY;
286                 else
287                         tmp |= DC_HPDx_INT_POLARITY;
288                 WREG32(DC_HPD3_INT_CONTROL, tmp);
289                 break;
290         case RADEON_HPD_4:
291                 tmp = RREG32(DC_HPD4_INT_CONTROL);
292                 if (connected)
293                         tmp &= ~DC_HPDx_INT_POLARITY;
294                 else
295                         tmp |= DC_HPDx_INT_POLARITY;
296                 WREG32(DC_HPD4_INT_CONTROL, tmp);
297                 break;
298         case RADEON_HPD_5:
299                 tmp = RREG32(DC_HPD5_INT_CONTROL);
300                 if (connected)
301                         tmp &= ~DC_HPDx_INT_POLARITY;
302                 else
303                         tmp |= DC_HPDx_INT_POLARITY;
304                 WREG32(DC_HPD5_INT_CONTROL, tmp);
305                         break;
306         case RADEON_HPD_6:
307                 tmp = RREG32(DC_HPD6_INT_CONTROL);
308                 if (connected)
309                         tmp &= ~DC_HPDx_INT_POLARITY;
310                 else
311                         tmp |= DC_HPDx_INT_POLARITY;
312                 WREG32(DC_HPD6_INT_CONTROL, tmp);
313                 break;
314         default:
315                 break;
316         }
317 }
318
319 void evergreen_hpd_init(struct radeon_device *rdev)
320 {
321         struct drm_device *dev = rdev->ddev;
322         struct drm_connector *connector;
323         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
324                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
325
326         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
327                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
328                 switch (radeon_connector->hpd.hpd) {
329                 case RADEON_HPD_1:
330                         WREG32(DC_HPD1_CONTROL, tmp);
331                         rdev->irq.hpd[0] = true;
332                         break;
333                 case RADEON_HPD_2:
334                         WREG32(DC_HPD2_CONTROL, tmp);
335                         rdev->irq.hpd[1] = true;
336                         break;
337                 case RADEON_HPD_3:
338                         WREG32(DC_HPD3_CONTROL, tmp);
339                         rdev->irq.hpd[2] = true;
340                         break;
341                 case RADEON_HPD_4:
342                         WREG32(DC_HPD4_CONTROL, tmp);
343                         rdev->irq.hpd[3] = true;
344                         break;
345                 case RADEON_HPD_5:
346                         WREG32(DC_HPD5_CONTROL, tmp);
347                         rdev->irq.hpd[4] = true;
348                         break;
349                 case RADEON_HPD_6:
350                         WREG32(DC_HPD6_CONTROL, tmp);
351                         rdev->irq.hpd[5] = true;
352                         break;
353                 default:
354                         break;
355                 }
356                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
357         }
358         if (rdev->irq.installed)
359                 evergreen_irq_set(rdev);
360 }
361
362 void evergreen_hpd_fini(struct radeon_device *rdev)
363 {
364         struct drm_device *dev = rdev->ddev;
365         struct drm_connector *connector;
366
367         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
368                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
369                 switch (radeon_connector->hpd.hpd) {
370                 case RADEON_HPD_1:
371                         WREG32(DC_HPD1_CONTROL, 0);
372                         rdev->irq.hpd[0] = false;
373                         break;
374                 case RADEON_HPD_2:
375                         WREG32(DC_HPD2_CONTROL, 0);
376                         rdev->irq.hpd[1] = false;
377                         break;
378                 case RADEON_HPD_3:
379                         WREG32(DC_HPD3_CONTROL, 0);
380                         rdev->irq.hpd[2] = false;
381                         break;
382                 case RADEON_HPD_4:
383                         WREG32(DC_HPD4_CONTROL, 0);
384                         rdev->irq.hpd[3] = false;
385                         break;
386                 case RADEON_HPD_5:
387                         WREG32(DC_HPD5_CONTROL, 0);
388                         rdev->irq.hpd[4] = false;
389                         break;
390                 case RADEON_HPD_6:
391                         WREG32(DC_HPD6_CONTROL, 0);
392                         rdev->irq.hpd[5] = false;
393                         break;
394                 default:
395                         break;
396                 }
397         }
398 }
399
400 /* watermark setup */
401
402 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
403                                         struct radeon_crtc *radeon_crtc,
404                                         struct drm_display_mode *mode,
405                                         struct drm_display_mode *other_mode)
406 {
407         u32 tmp;
408         /*
409          * Line Buffer Setup
410          * There are 3 line buffers, each one shared by 2 display controllers.
411          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
412          * the display controllers.  The paritioning is done via one of four
413          * preset allocations specified in bits 2:0:
414          * first display controller
415          *  0 - first half of lb (3840 * 2)
416          *  1 - first 3/4 of lb (5760 * 2)
417          *  2 - whole lb (7680 * 2), other crtc must be disabled
418          *  3 - first 1/4 of lb (1920 * 2)
419          * second display controller
420          *  4 - second half of lb (3840 * 2)
421          *  5 - second 3/4 of lb (5760 * 2)
422          *  6 - whole lb (7680 * 2), other crtc must be disabled
423          *  7 - last 1/4 of lb (1920 * 2)
424          */
425         /* this can get tricky if we have two large displays on a paired group
426          * of crtcs.  Ideally for multiple large displays we'd assign them to
427          * non-linked crtcs for maximum line buffer allocation.
428          */
429         if (radeon_crtc->base.enabled && mode) {
430                 if (other_mode)
431                         tmp = 0; /* 1/2 */
432                 else
433                         tmp = 2; /* whole */
434         } else
435                 tmp = 0;
436
437         /* second controller of the pair uses second half of the lb */
438         if (radeon_crtc->crtc_id % 2)
439                 tmp += 4;
440         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
441
442         if (radeon_crtc->base.enabled && mode) {
443                 switch (tmp) {
444                 case 0:
445                 case 4:
446                 default:
447                         if (ASIC_IS_DCE5(rdev))
448                                 return 4096 * 2;
449                         else
450                                 return 3840 * 2;
451                 case 1:
452                 case 5:
453                         if (ASIC_IS_DCE5(rdev))
454                                 return 6144 * 2;
455                         else
456                                 return 5760 * 2;
457                 case 2:
458                 case 6:
459                         if (ASIC_IS_DCE5(rdev))
460                                 return 8192 * 2;
461                         else
462                                 return 7680 * 2;
463                 case 3:
464                 case 7:
465                         if (ASIC_IS_DCE5(rdev))
466                                 return 2048 * 2;
467                         else
468                                 return 1920 * 2;
469                 }
470         }
471
472         /* controller not enabled, so no lb used */
473         return 0;
474 }
475
476 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
477 {
478         u32 tmp = RREG32(MC_SHARED_CHMAP);
479
480         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
481         case 0:
482         default:
483                 return 1;
484         case 1:
485                 return 2;
486         case 2:
487                 return 4;
488         case 3:
489                 return 8;
490         }
491 }
492
493 struct evergreen_wm_params {
494         u32 dram_channels; /* number of dram channels */
495         u32 yclk;          /* bandwidth per dram data pin in kHz */
496         u32 sclk;          /* engine clock in kHz */
497         u32 disp_clk;      /* display clock in kHz */
498         u32 src_width;     /* viewport width */
499         u32 active_time;   /* active display time in ns */
500         u32 blank_time;    /* blank time in ns */
501         bool interlaced;    /* mode is interlaced */
502         fixed20_12 vsc;    /* vertical scale ratio */
503         u32 num_heads;     /* number of active crtcs */
504         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
505         u32 lb_size;       /* line buffer allocated to pipe */
506         u32 vtaps;         /* vertical scaler taps */
507 };
508
509 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
510 {
511         /* Calculate DRAM Bandwidth and the part allocated to display. */
512         fixed20_12 dram_efficiency; /* 0.7 */
513         fixed20_12 yclk, dram_channels, bandwidth;
514         fixed20_12 a;
515
516         a.full = dfixed_const(1000);
517         yclk.full = dfixed_const(wm->yclk);
518         yclk.full = dfixed_div(yclk, a);
519         dram_channels.full = dfixed_const(wm->dram_channels * 4);
520         a.full = dfixed_const(10);
521         dram_efficiency.full = dfixed_const(7);
522         dram_efficiency.full = dfixed_div(dram_efficiency, a);
523         bandwidth.full = dfixed_mul(dram_channels, yclk);
524         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
525
526         return dfixed_trunc(bandwidth);
527 }
528
529 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
530 {
531         /* Calculate DRAM Bandwidth and the part allocated to display. */
532         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
533         fixed20_12 yclk, dram_channels, bandwidth;
534         fixed20_12 a;
535
536         a.full = dfixed_const(1000);
537         yclk.full = dfixed_const(wm->yclk);
538         yclk.full = dfixed_div(yclk, a);
539         dram_channels.full = dfixed_const(wm->dram_channels * 4);
540         a.full = dfixed_const(10);
541         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
542         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
543         bandwidth.full = dfixed_mul(dram_channels, yclk);
544         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
545
546         return dfixed_trunc(bandwidth);
547 }
548
549 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
550 {
551         /* Calculate the display Data return Bandwidth */
552         fixed20_12 return_efficiency; /* 0.8 */
553         fixed20_12 sclk, bandwidth;
554         fixed20_12 a;
555
556         a.full = dfixed_const(1000);
557         sclk.full = dfixed_const(wm->sclk);
558         sclk.full = dfixed_div(sclk, a);
559         a.full = dfixed_const(10);
560         return_efficiency.full = dfixed_const(8);
561         return_efficiency.full = dfixed_div(return_efficiency, a);
562         a.full = dfixed_const(32);
563         bandwidth.full = dfixed_mul(a, sclk);
564         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
565
566         return dfixed_trunc(bandwidth);
567 }
568
569 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
570 {
571         /* Calculate the DMIF Request Bandwidth */
572         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
573         fixed20_12 disp_clk, bandwidth;
574         fixed20_12 a;
575
576         a.full = dfixed_const(1000);
577         disp_clk.full = dfixed_const(wm->disp_clk);
578         disp_clk.full = dfixed_div(disp_clk, a);
579         a.full = dfixed_const(10);
580         disp_clk_request_efficiency.full = dfixed_const(8);
581         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
582         a.full = dfixed_const(32);
583         bandwidth.full = dfixed_mul(a, disp_clk);
584         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
585
586         return dfixed_trunc(bandwidth);
587 }
588
589 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
590 {
591         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
592         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
593         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
594         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
595
596         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
597 }
598
599 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
600 {
601         /* Calculate the display mode Average Bandwidth
602          * DisplayMode should contain the source and destination dimensions,
603          * timing, etc.
604          */
605         fixed20_12 bpp;
606         fixed20_12 line_time;
607         fixed20_12 src_width;
608         fixed20_12 bandwidth;
609         fixed20_12 a;
610
611         a.full = dfixed_const(1000);
612         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
613         line_time.full = dfixed_div(line_time, a);
614         bpp.full = dfixed_const(wm->bytes_per_pixel);
615         src_width.full = dfixed_const(wm->src_width);
616         bandwidth.full = dfixed_mul(src_width, bpp);
617         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
618         bandwidth.full = dfixed_div(bandwidth, line_time);
619
620         return dfixed_trunc(bandwidth);
621 }
622
623 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
624 {
625         /* First calcualte the latency in ns */
626         u32 mc_latency = 2000; /* 2000 ns. */
627         u32 available_bandwidth = evergreen_available_bandwidth(wm);
628         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
629         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
630         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
631         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
632                 (wm->num_heads * cursor_line_pair_return_time);
633         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
634         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
635         fixed20_12 a, b, c;
636
637         if (wm->num_heads == 0)
638                 return 0;
639
640         a.full = dfixed_const(2);
641         b.full = dfixed_const(1);
642         if ((wm->vsc.full > a.full) ||
643             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
644             (wm->vtaps >= 5) ||
645             ((wm->vsc.full >= a.full) && wm->interlaced))
646                 max_src_lines_per_dst_line = 4;
647         else
648                 max_src_lines_per_dst_line = 2;
649
650         a.full = dfixed_const(available_bandwidth);
651         b.full = dfixed_const(wm->num_heads);
652         a.full = dfixed_div(a, b);
653
654         b.full = dfixed_const(1000);
655         c.full = dfixed_const(wm->disp_clk);
656         b.full = dfixed_div(c, b);
657         c.full = dfixed_const(wm->bytes_per_pixel);
658         b.full = dfixed_mul(b, c);
659
660         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
661
662         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
663         b.full = dfixed_const(1000);
664         c.full = dfixed_const(lb_fill_bw);
665         b.full = dfixed_div(c, b);
666         a.full = dfixed_div(a, b);
667         line_fill_time = dfixed_trunc(a);
668
669         if (line_fill_time < wm->active_time)
670                 return latency;
671         else
672                 return latency + (line_fill_time - wm->active_time);
673
674 }
675
676 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
677 {
678         if (evergreen_average_bandwidth(wm) <=
679             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
680                 return true;
681         else
682                 return false;
683 };
684
685 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
686 {
687         if (evergreen_average_bandwidth(wm) <=
688             (evergreen_available_bandwidth(wm) / wm->num_heads))
689                 return true;
690         else
691                 return false;
692 };
693
694 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
695 {
696         u32 lb_partitions = wm->lb_size / wm->src_width;
697         u32 line_time = wm->active_time + wm->blank_time;
698         u32 latency_tolerant_lines;
699         u32 latency_hiding;
700         fixed20_12 a;
701
702         a.full = dfixed_const(1);
703         if (wm->vsc.full > a.full)
704                 latency_tolerant_lines = 1;
705         else {
706                 if (lb_partitions <= (wm->vtaps + 1))
707                         latency_tolerant_lines = 1;
708                 else
709                         latency_tolerant_lines = 2;
710         }
711
712         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
713
714         if (evergreen_latency_watermark(wm) <= latency_hiding)
715                 return true;
716         else
717                 return false;
718 }
719
720 static void evergreen_program_watermarks(struct radeon_device *rdev,
721                                          struct radeon_crtc *radeon_crtc,
722                                          u32 lb_size, u32 num_heads)
723 {
724         struct drm_display_mode *mode = &radeon_crtc->base.mode;
725         struct evergreen_wm_params wm;
726         u32 pixel_period;
727         u32 line_time = 0;
728         u32 latency_watermark_a = 0, latency_watermark_b = 0;
729         u32 priority_a_mark = 0, priority_b_mark = 0;
730         u32 priority_a_cnt = PRIORITY_OFF;
731         u32 priority_b_cnt = PRIORITY_OFF;
732         u32 pipe_offset = radeon_crtc->crtc_id * 16;
733         u32 tmp, arb_control3;
734         fixed20_12 a, b, c;
735
736         if (radeon_crtc->base.enabled && num_heads && mode) {
737                 pixel_period = 1000000 / (u32)mode->clock;
738                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
739                 priority_a_cnt = 0;
740                 priority_b_cnt = 0;
741
742                 wm.yclk = rdev->pm.current_mclk * 10;
743                 wm.sclk = rdev->pm.current_sclk * 10;
744                 wm.disp_clk = mode->clock;
745                 wm.src_width = mode->crtc_hdisplay;
746                 wm.active_time = mode->crtc_hdisplay * pixel_period;
747                 wm.blank_time = line_time - wm.active_time;
748                 wm.interlaced = false;
749                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
750                         wm.interlaced = true;
751                 wm.vsc = radeon_crtc->vsc;
752                 wm.vtaps = 1;
753                 if (radeon_crtc->rmx_type != RMX_OFF)
754                         wm.vtaps = 2;
755                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
756                 wm.lb_size = lb_size;
757                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
758                 wm.num_heads = num_heads;
759
760                 /* set for high clocks */
761                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
762                 /* set for low clocks */
763                 /* wm.yclk = low clk; wm.sclk = low clk */
764                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
765
766                 /* possibly force display priority to high */
767                 /* should really do this at mode validation time... */
768                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
769                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
770                     !evergreen_check_latency_hiding(&wm) ||
771                     (rdev->disp_priority == 2)) {
772                         DRM_DEBUG_KMS("force priority to high\n");
773                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
774                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
775                 }
776
777                 a.full = dfixed_const(1000);
778                 b.full = dfixed_const(mode->clock);
779                 b.full = dfixed_div(b, a);
780                 c.full = dfixed_const(latency_watermark_a);
781                 c.full = dfixed_mul(c, b);
782                 c.full = dfixed_mul(c, radeon_crtc->hsc);
783                 c.full = dfixed_div(c, a);
784                 a.full = dfixed_const(16);
785                 c.full = dfixed_div(c, a);
786                 priority_a_mark = dfixed_trunc(c);
787                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
788
789                 a.full = dfixed_const(1000);
790                 b.full = dfixed_const(mode->clock);
791                 b.full = dfixed_div(b, a);
792                 c.full = dfixed_const(latency_watermark_b);
793                 c.full = dfixed_mul(c, b);
794                 c.full = dfixed_mul(c, radeon_crtc->hsc);
795                 c.full = dfixed_div(c, a);
796                 a.full = dfixed_const(16);
797                 c.full = dfixed_div(c, a);
798                 priority_b_mark = dfixed_trunc(c);
799                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
800         }
801
802         /* select wm A */
803         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
804         tmp = arb_control3;
805         tmp &= ~LATENCY_WATERMARK_MASK(3);
806         tmp |= LATENCY_WATERMARK_MASK(1);
807         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
808         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
809                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
810                 LATENCY_HIGH_WATERMARK(line_time)));
811         /* select wm B */
812         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
813         tmp &= ~LATENCY_WATERMARK_MASK(3);
814         tmp |= LATENCY_WATERMARK_MASK(2);
815         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
816         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
817                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
818                 LATENCY_HIGH_WATERMARK(line_time)));
819         /* restore original selection */
820         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
821
822         /* write the priority marks */
823         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
824         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
825
826 }
827
828 void evergreen_bandwidth_update(struct radeon_device *rdev)
829 {
830         struct drm_display_mode *mode0 = NULL;
831         struct drm_display_mode *mode1 = NULL;
832         u32 num_heads = 0, lb_size;
833         int i;
834
835         radeon_update_display_priority(rdev);
836
837         for (i = 0; i < rdev->num_crtc; i++) {
838                 if (rdev->mode_info.crtcs[i]->base.enabled)
839                         num_heads++;
840         }
841         for (i = 0; i < rdev->num_crtc; i += 2) {
842                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
843                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
844                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
845                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
846                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
847                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
848         }
849 }
850
851 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
852 {
853         unsigned i;
854         u32 tmp;
855
856         for (i = 0; i < rdev->usec_timeout; i++) {
857                 /* read MC_STATUS */
858                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
859                 if (!tmp)
860                         return 0;
861                 udelay(1);
862         }
863         return -1;
864 }
865
866 /*
867  * GART
868  */
869 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
870 {
871         unsigned i;
872         u32 tmp;
873
874         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
875
876         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
877         for (i = 0; i < rdev->usec_timeout; i++) {
878                 /* read MC_STATUS */
879                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
880                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
881                 if (tmp == 2) {
882                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
883                         return;
884                 }
885                 if (tmp) {
886                         return;
887                 }
888                 udelay(1);
889         }
890 }
891
892 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
893 {
894         u32 tmp;
895         int r;
896
897         if (rdev->gart.robj == NULL) {
898                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
899                 return -EINVAL;
900         }
901         r = radeon_gart_table_vram_pin(rdev);
902         if (r)
903                 return r;
904         radeon_gart_restore(rdev);
905         /* Setup L2 cache */
906         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
907                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
908                                 EFFECTIVE_L2_QUEUE_SIZE(7));
909         WREG32(VM_L2_CNTL2, 0);
910         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
911         /* Setup TLB control */
912         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
913                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
914                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
915                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
916         if (rdev->flags & RADEON_IS_IGP) {
917                 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
918                 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
919                 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
920         } else {
921                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
922                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
923                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
924         }
925         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
926         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
927         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
928         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
929         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
930         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
931         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
932         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
933                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
934         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
935                         (u32)(rdev->dummy_page.addr >> 12));
936         WREG32(VM_CONTEXT1_CNTL, 0);
937
938         evergreen_pcie_gart_tlb_flush(rdev);
939         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
940                  (unsigned)(rdev->mc.gtt_size >> 20),
941                  (unsigned long long)rdev->gart.table_addr);
942         rdev->gart.ready = true;
943         return 0;
944 }
945
946 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
947 {
948         u32 tmp;
949
950         /* Disable all tables */
951         WREG32(VM_CONTEXT0_CNTL, 0);
952         WREG32(VM_CONTEXT1_CNTL, 0);
953
954         /* Setup L2 cache */
955         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
956                                 EFFECTIVE_L2_QUEUE_SIZE(7));
957         WREG32(VM_L2_CNTL2, 0);
958         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
959         /* Setup TLB control */
960         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
961         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
962         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
963         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
964         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
965         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
966         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
967         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
968         radeon_gart_table_vram_unpin(rdev);
969 }
970
971 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
972 {
973         evergreen_pcie_gart_disable(rdev);
974         radeon_gart_table_vram_free(rdev);
975         radeon_gart_fini(rdev);
976 }
977
978
979 void evergreen_agp_enable(struct radeon_device *rdev)
980 {
981         u32 tmp;
982
983         /* Setup L2 cache */
984         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
985                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
986                                 EFFECTIVE_L2_QUEUE_SIZE(7));
987         WREG32(VM_L2_CNTL2, 0);
988         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
989         /* Setup TLB control */
990         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
991                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
992                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
993                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
994         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
995         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
996         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
997         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
998         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
999         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1000         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1001         WREG32(VM_CONTEXT0_CNTL, 0);
1002         WREG32(VM_CONTEXT1_CNTL, 0);
1003 }
1004
1005 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1006 {
1007         save->vga_control[0] = RREG32(D1VGA_CONTROL);
1008         save->vga_control[1] = RREG32(D2VGA_CONTROL);
1009         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1010         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1011         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1012         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1013         if (rdev->num_crtc >= 4) {
1014                 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1015                 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1016                 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1017                 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1018         }
1019         if (rdev->num_crtc >= 6) {
1020                 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1021                 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1022                 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1023                 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1024         }
1025
1026         /* Stop all video */
1027         WREG32(VGA_RENDER_CONTROL, 0);
1028         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1029         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1030         if (rdev->num_crtc >= 4) {
1031                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1032                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1033         }
1034         if (rdev->num_crtc >= 6) {
1035                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1036                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1037         }
1038         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1039         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1040         if (rdev->num_crtc >= 4) {
1041                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1042                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1043         }
1044         if (rdev->num_crtc >= 6) {
1045                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1046                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1047         }
1048         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1049         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1050         if (rdev->num_crtc >= 4) {
1051                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1052                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1053         }
1054         if (rdev->num_crtc >= 6) {
1055                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1056                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1057         }
1058
1059         WREG32(D1VGA_CONTROL, 0);
1060         WREG32(D2VGA_CONTROL, 0);
1061         if (rdev->num_crtc >= 4) {
1062                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1063                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1064         }
1065         if (rdev->num_crtc >= 6) {
1066                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1067                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1068         }
1069 }
1070
1071 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1072 {
1073         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1074                upper_32_bits(rdev->mc.vram_start));
1075         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1076                upper_32_bits(rdev->mc.vram_start));
1077         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1078                (u32)rdev->mc.vram_start);
1079         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1080                (u32)rdev->mc.vram_start);
1081
1082         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1083                upper_32_bits(rdev->mc.vram_start));
1084         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1085                upper_32_bits(rdev->mc.vram_start));
1086         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1087                (u32)rdev->mc.vram_start);
1088         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1089                (u32)rdev->mc.vram_start);
1090
1091         if (rdev->num_crtc >= 4) {
1092                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1093                        upper_32_bits(rdev->mc.vram_start));
1094                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1095                        upper_32_bits(rdev->mc.vram_start));
1096                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1097                        (u32)rdev->mc.vram_start);
1098                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1099                        (u32)rdev->mc.vram_start);
1100
1101                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1102                        upper_32_bits(rdev->mc.vram_start));
1103                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1104                        upper_32_bits(rdev->mc.vram_start));
1105                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1106                        (u32)rdev->mc.vram_start);
1107                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1108                        (u32)rdev->mc.vram_start);
1109         }
1110         if (rdev->num_crtc >= 6) {
1111                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1112                        upper_32_bits(rdev->mc.vram_start));
1113                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1114                        upper_32_bits(rdev->mc.vram_start));
1115                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1116                        (u32)rdev->mc.vram_start);
1117                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1118                        (u32)rdev->mc.vram_start);
1119
1120                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1121                        upper_32_bits(rdev->mc.vram_start));
1122                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1123                        upper_32_bits(rdev->mc.vram_start));
1124                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1125                        (u32)rdev->mc.vram_start);
1126                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1127                        (u32)rdev->mc.vram_start);
1128         }
1129
1130         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1131         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1132         /* Unlock host access */
1133         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1134         mdelay(1);
1135         /* Restore video state */
1136         WREG32(D1VGA_CONTROL, save->vga_control[0]);
1137         WREG32(D2VGA_CONTROL, save->vga_control[1]);
1138         if (rdev->num_crtc >= 4) {
1139                 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1140                 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1141         }
1142         if (rdev->num_crtc >= 6) {
1143                 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1144                 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1145         }
1146         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1147         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1148         if (rdev->num_crtc >= 4) {
1149                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1150                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1151         }
1152         if (rdev->num_crtc >= 6) {
1153                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1154                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1155         }
1156         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1157         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1158         if (rdev->num_crtc >= 4) {
1159                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1160                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1161         }
1162         if (rdev->num_crtc >= 6) {
1163                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1164                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1165         }
1166         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1167         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1168         if (rdev->num_crtc >= 4) {
1169                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1170                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1171         }
1172         if (rdev->num_crtc >= 6) {
1173                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1174                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1175         }
1176         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1177 }
1178
1179 void evergreen_mc_program(struct radeon_device *rdev)
1180 {
1181         struct evergreen_mc_save save;
1182         u32 tmp;
1183         int i, j;
1184
1185         /* Initialize HDP */
1186         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1187                 WREG32((0x2c14 + j), 0x00000000);
1188                 WREG32((0x2c18 + j), 0x00000000);
1189                 WREG32((0x2c1c + j), 0x00000000);
1190                 WREG32((0x2c20 + j), 0x00000000);
1191                 WREG32((0x2c24 + j), 0x00000000);
1192         }
1193         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1194
1195         evergreen_mc_stop(rdev, &save);
1196         if (evergreen_mc_wait_for_idle(rdev)) {
1197                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1198         }
1199         /* Lockout access through VGA aperture*/
1200         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1201         /* Update configuration */
1202         if (rdev->flags & RADEON_IS_AGP) {
1203                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1204                         /* VRAM before AGP */
1205                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1206                                 rdev->mc.vram_start >> 12);
1207                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1208                                 rdev->mc.gtt_end >> 12);
1209                 } else {
1210                         /* VRAM after AGP */
1211                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1212                                 rdev->mc.gtt_start >> 12);
1213                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1214                                 rdev->mc.vram_end >> 12);
1215                 }
1216         } else {
1217                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1218                         rdev->mc.vram_start >> 12);
1219                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1220                         rdev->mc.vram_end >> 12);
1221         }
1222         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1223         if (rdev->flags & RADEON_IS_IGP) {
1224                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1225                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1226                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1227                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1228         }
1229         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1230         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1231         WREG32(MC_VM_FB_LOCATION, tmp);
1232         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1233         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1234         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1235         if (rdev->flags & RADEON_IS_AGP) {
1236                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1237                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1238                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1239         } else {
1240                 WREG32(MC_VM_AGP_BASE, 0);
1241                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1242                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1243         }
1244         if (evergreen_mc_wait_for_idle(rdev)) {
1245                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1246         }
1247         evergreen_mc_resume(rdev, &save);
1248         /* we need to own VRAM, so turn off the VGA renderer here
1249          * to stop it overwriting our objects */
1250         rv515_vga_render_disable(rdev);
1251 }
1252
1253 /*
1254  * CP.
1255  */
1256 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1257 {
1258         /* set to DX10/11 mode */
1259         radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1260         radeon_ring_write(rdev, 1);
1261         /* FIXME: implement */
1262         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1263         radeon_ring_write(rdev,
1264 #ifdef __BIG_ENDIAN
1265                           (2 << 0) |
1266 #endif
1267                           (ib->gpu_addr & 0xFFFFFFFC));
1268         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1269         radeon_ring_write(rdev, ib->length_dw);
1270 }
1271
1272
1273 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1274 {
1275         const __be32 *fw_data;
1276         int i;
1277
1278         if (!rdev->me_fw || !rdev->pfp_fw)
1279                 return -EINVAL;
1280
1281         r700_cp_stop(rdev);
1282         WREG32(CP_RB_CNTL,
1283 #ifdef __BIG_ENDIAN
1284                BUF_SWAP_32BIT |
1285 #endif
1286                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1287
1288         fw_data = (const __be32 *)rdev->pfp_fw->data;
1289         WREG32(CP_PFP_UCODE_ADDR, 0);
1290         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1291                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1292         WREG32(CP_PFP_UCODE_ADDR, 0);
1293
1294         fw_data = (const __be32 *)rdev->me_fw->data;
1295         WREG32(CP_ME_RAM_WADDR, 0);
1296         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1297                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1298
1299         WREG32(CP_PFP_UCODE_ADDR, 0);
1300         WREG32(CP_ME_RAM_WADDR, 0);
1301         WREG32(CP_ME_RAM_RADDR, 0);
1302         return 0;
1303 }
1304
1305 static int evergreen_cp_start(struct radeon_device *rdev)
1306 {
1307         int r, i;
1308         uint32_t cp_me;
1309
1310         r = radeon_ring_lock(rdev, 7);
1311         if (r) {
1312                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1313                 return r;
1314         }
1315         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1316         radeon_ring_write(rdev, 0x1);
1317         radeon_ring_write(rdev, 0x0);
1318         radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1319         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1320         radeon_ring_write(rdev, 0);
1321         radeon_ring_write(rdev, 0);
1322         radeon_ring_unlock_commit(rdev);
1323
1324         cp_me = 0xff;
1325         WREG32(CP_ME_CNTL, cp_me);
1326
1327         r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1328         if (r) {
1329                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1330                 return r;
1331         }
1332
1333         /* setup clear context state */
1334         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1335         radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1336
1337         for (i = 0; i < evergreen_default_size; i++)
1338                 radeon_ring_write(rdev, evergreen_default_state[i]);
1339
1340         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1341         radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1342
1343         /* set clear context state */
1344         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1345         radeon_ring_write(rdev, 0);
1346
1347         /* SQ_VTX_BASE_VTX_LOC */
1348         radeon_ring_write(rdev, 0xc0026f00);
1349         radeon_ring_write(rdev, 0x00000000);
1350         radeon_ring_write(rdev, 0x00000000);
1351         radeon_ring_write(rdev, 0x00000000);
1352
1353         /* Clear consts */
1354         radeon_ring_write(rdev, 0xc0036f00);
1355         radeon_ring_write(rdev, 0x00000bc4);
1356         radeon_ring_write(rdev, 0xffffffff);
1357         radeon_ring_write(rdev, 0xffffffff);
1358         radeon_ring_write(rdev, 0xffffffff);
1359
1360         radeon_ring_write(rdev, 0xc0026900);
1361         radeon_ring_write(rdev, 0x00000316);
1362         radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1363         radeon_ring_write(rdev, 0x00000010); /*  */
1364
1365         radeon_ring_unlock_commit(rdev);
1366
1367         return 0;
1368 }
1369
1370 int evergreen_cp_resume(struct radeon_device *rdev)
1371 {
1372         u32 tmp;
1373         u32 rb_bufsz;
1374         int r;
1375
1376         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1377         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1378                                  SOFT_RESET_PA |
1379                                  SOFT_RESET_SH |
1380                                  SOFT_RESET_VGT |
1381                                  SOFT_RESET_SPI |
1382                                  SOFT_RESET_SX));
1383         RREG32(GRBM_SOFT_RESET);
1384         mdelay(15);
1385         WREG32(GRBM_SOFT_RESET, 0);
1386         RREG32(GRBM_SOFT_RESET);
1387
1388         /* Set ring buffer size */
1389         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1390         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1391 #ifdef __BIG_ENDIAN
1392         tmp |= BUF_SWAP_32BIT;
1393 #endif
1394         WREG32(CP_RB_CNTL, tmp);
1395         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1396
1397         /* Set the write pointer delay */
1398         WREG32(CP_RB_WPTR_DELAY, 0);
1399
1400         /* Initialize the ring buffer's read and write pointers */
1401         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1402         WREG32(CP_RB_RPTR_WR, 0);
1403         rdev->cp.wptr = 0;
1404         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1405
1406         /* set the wb address wether it's enabled or not */
1407         WREG32(CP_RB_RPTR_ADDR,
1408                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1409         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1410         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1411
1412         if (rdev->wb.enabled)
1413                 WREG32(SCRATCH_UMSK, 0xff);
1414         else {
1415                 tmp |= RB_NO_UPDATE;
1416                 WREG32(SCRATCH_UMSK, 0);
1417         }
1418
1419         mdelay(1);
1420         WREG32(CP_RB_CNTL, tmp);
1421
1422         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1423         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1424
1425         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1426
1427         evergreen_cp_start(rdev);
1428         rdev->cp.ready = true;
1429         r = radeon_ring_test(rdev);
1430         if (r) {
1431                 rdev->cp.ready = false;
1432                 return r;
1433         }
1434         return 0;
1435 }
1436
1437 /*
1438  * Core functions
1439  */
1440 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1441                                                   u32 num_tile_pipes,
1442                                                   u32 num_backends,
1443                                                   u32 backend_disable_mask)
1444 {
1445         u32 backend_map = 0;
1446         u32 enabled_backends_mask = 0;
1447         u32 enabled_backends_count = 0;
1448         u32 cur_pipe;
1449         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1450         u32 cur_backend = 0;
1451         u32 i;
1452         bool force_no_swizzle;
1453
1454         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1455                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1456         if (num_tile_pipes < 1)
1457                 num_tile_pipes = 1;
1458         if (num_backends > EVERGREEN_MAX_BACKENDS)
1459                 num_backends = EVERGREEN_MAX_BACKENDS;
1460         if (num_backends < 1)
1461                 num_backends = 1;
1462
1463         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1464                 if (((backend_disable_mask >> i) & 1) == 0) {
1465                         enabled_backends_mask |= (1 << i);
1466                         ++enabled_backends_count;
1467                 }
1468                 if (enabled_backends_count == num_backends)
1469                         break;
1470         }
1471
1472         if (enabled_backends_count == 0) {
1473                 enabled_backends_mask = 1;
1474                 enabled_backends_count = 1;
1475         }
1476
1477         if (enabled_backends_count != num_backends)
1478                 num_backends = enabled_backends_count;
1479
1480         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1481         switch (rdev->family) {
1482         case CHIP_CEDAR:
1483         case CHIP_REDWOOD:
1484         case CHIP_PALM:
1485         case CHIP_SUMO:
1486         case CHIP_SUMO2:
1487         case CHIP_TURKS:
1488         case CHIP_CAICOS:
1489                 force_no_swizzle = false;
1490                 break;
1491         case CHIP_CYPRESS:
1492         case CHIP_HEMLOCK:
1493         case CHIP_JUNIPER:
1494         case CHIP_BARTS:
1495         default:
1496                 force_no_swizzle = true;
1497                 break;
1498         }
1499         if (force_no_swizzle) {
1500                 bool last_backend_enabled = false;
1501
1502                 force_no_swizzle = false;
1503                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1504                         if (((enabled_backends_mask >> i) & 1) == 1) {
1505                                 if (last_backend_enabled)
1506                                         force_no_swizzle = true;
1507                                 last_backend_enabled = true;
1508                         } else
1509                                 last_backend_enabled = false;
1510                 }
1511         }
1512
1513         switch (num_tile_pipes) {
1514         case 1:
1515         case 3:
1516         case 5:
1517         case 7:
1518                 DRM_ERROR("odd number of pipes!\n");
1519                 break;
1520         case 2:
1521                 swizzle_pipe[0] = 0;
1522                 swizzle_pipe[1] = 1;
1523                 break;
1524         case 4:
1525                 if (force_no_swizzle) {
1526                         swizzle_pipe[0] = 0;
1527                         swizzle_pipe[1] = 1;
1528                         swizzle_pipe[2] = 2;
1529                         swizzle_pipe[3] = 3;
1530                 } else {
1531                         swizzle_pipe[0] = 0;
1532                         swizzle_pipe[1] = 2;
1533                         swizzle_pipe[2] = 1;
1534                         swizzle_pipe[3] = 3;
1535                 }
1536                 break;
1537         case 6:
1538                 if (force_no_swizzle) {
1539                         swizzle_pipe[0] = 0;
1540                         swizzle_pipe[1] = 1;
1541                         swizzle_pipe[2] = 2;
1542                         swizzle_pipe[3] = 3;
1543                         swizzle_pipe[4] = 4;
1544                         swizzle_pipe[5] = 5;
1545                 } else {
1546                         swizzle_pipe[0] = 0;
1547                         swizzle_pipe[1] = 2;
1548                         swizzle_pipe[2] = 4;
1549                         swizzle_pipe[3] = 1;
1550                         swizzle_pipe[4] = 3;
1551                         swizzle_pipe[5] = 5;
1552                 }
1553                 break;
1554         case 8:
1555                 if (force_no_swizzle) {
1556                         swizzle_pipe[0] = 0;
1557                         swizzle_pipe[1] = 1;
1558                         swizzle_pipe[2] = 2;
1559                         swizzle_pipe[3] = 3;
1560                         swizzle_pipe[4] = 4;
1561                         swizzle_pipe[5] = 5;
1562                         swizzle_pipe[6] = 6;
1563                         swizzle_pipe[7] = 7;
1564                 } else {
1565                         swizzle_pipe[0] = 0;
1566                         swizzle_pipe[1] = 2;
1567                         swizzle_pipe[2] = 4;
1568                         swizzle_pipe[3] = 6;
1569                         swizzle_pipe[4] = 1;
1570                         swizzle_pipe[5] = 3;
1571                         swizzle_pipe[6] = 5;
1572                         swizzle_pipe[7] = 7;
1573                 }
1574                 break;
1575         }
1576
1577         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1578                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1579                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1580
1581                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1582
1583                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1584         }
1585
1586         return backend_map;
1587 }
1588
1589 static void evergreen_gpu_init(struct radeon_device *rdev)
1590 {
1591         u32 cc_rb_backend_disable = 0;
1592         u32 cc_gc_shader_pipe_config;
1593         u32 gb_addr_config = 0;
1594         u32 mc_shared_chmap, mc_arb_ramcfg;
1595         u32 gb_backend_map;
1596         u32 grbm_gfx_index;
1597         u32 sx_debug_1;
1598         u32 smx_dc_ctl0;
1599         u32 sq_config;
1600         u32 sq_lds_resource_mgmt;
1601         u32 sq_gpr_resource_mgmt_1;
1602         u32 sq_gpr_resource_mgmt_2;
1603         u32 sq_gpr_resource_mgmt_3;
1604         u32 sq_thread_resource_mgmt;
1605         u32 sq_thread_resource_mgmt_2;
1606         u32 sq_stack_resource_mgmt_1;
1607         u32 sq_stack_resource_mgmt_2;
1608         u32 sq_stack_resource_mgmt_3;
1609         u32 vgt_cache_invalidation;
1610         u32 hdp_host_path_cntl, tmp;
1611         int i, j, num_shader_engines, ps_thread_count;
1612
1613         switch (rdev->family) {
1614         case CHIP_CYPRESS:
1615         case CHIP_HEMLOCK:
1616                 rdev->config.evergreen.num_ses = 2;
1617                 rdev->config.evergreen.max_pipes = 4;
1618                 rdev->config.evergreen.max_tile_pipes = 8;
1619                 rdev->config.evergreen.max_simds = 10;
1620                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1621                 rdev->config.evergreen.max_gprs = 256;
1622                 rdev->config.evergreen.max_threads = 248;
1623                 rdev->config.evergreen.max_gs_threads = 32;
1624                 rdev->config.evergreen.max_stack_entries = 512;
1625                 rdev->config.evergreen.sx_num_of_sets = 4;
1626                 rdev->config.evergreen.sx_max_export_size = 256;
1627                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1628                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1629                 rdev->config.evergreen.max_hw_contexts = 8;
1630                 rdev->config.evergreen.sq_num_cf_insts = 2;
1631
1632                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1633                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1634                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1635                 break;
1636         case CHIP_JUNIPER:
1637                 rdev->config.evergreen.num_ses = 1;
1638                 rdev->config.evergreen.max_pipes = 4;
1639                 rdev->config.evergreen.max_tile_pipes = 4;
1640                 rdev->config.evergreen.max_simds = 10;
1641                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1642                 rdev->config.evergreen.max_gprs = 256;
1643                 rdev->config.evergreen.max_threads = 248;
1644                 rdev->config.evergreen.max_gs_threads = 32;
1645                 rdev->config.evergreen.max_stack_entries = 512;
1646                 rdev->config.evergreen.sx_num_of_sets = 4;
1647                 rdev->config.evergreen.sx_max_export_size = 256;
1648                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1649                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1650                 rdev->config.evergreen.max_hw_contexts = 8;
1651                 rdev->config.evergreen.sq_num_cf_insts = 2;
1652
1653                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1654                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1655                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1656                 break;
1657         case CHIP_REDWOOD:
1658                 rdev->config.evergreen.num_ses = 1;
1659                 rdev->config.evergreen.max_pipes = 4;
1660                 rdev->config.evergreen.max_tile_pipes = 4;
1661                 rdev->config.evergreen.max_simds = 5;
1662                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1663                 rdev->config.evergreen.max_gprs = 256;
1664                 rdev->config.evergreen.max_threads = 248;
1665                 rdev->config.evergreen.max_gs_threads = 32;
1666                 rdev->config.evergreen.max_stack_entries = 256;
1667                 rdev->config.evergreen.sx_num_of_sets = 4;
1668                 rdev->config.evergreen.sx_max_export_size = 256;
1669                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1670                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1671                 rdev->config.evergreen.max_hw_contexts = 8;
1672                 rdev->config.evergreen.sq_num_cf_insts = 2;
1673
1674                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1675                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1676                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1677                 break;
1678         case CHIP_CEDAR:
1679         default:
1680                 rdev->config.evergreen.num_ses = 1;
1681                 rdev->config.evergreen.max_pipes = 2;
1682                 rdev->config.evergreen.max_tile_pipes = 2;
1683                 rdev->config.evergreen.max_simds = 2;
1684                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1685                 rdev->config.evergreen.max_gprs = 256;
1686                 rdev->config.evergreen.max_threads = 192;
1687                 rdev->config.evergreen.max_gs_threads = 16;
1688                 rdev->config.evergreen.max_stack_entries = 256;
1689                 rdev->config.evergreen.sx_num_of_sets = 4;
1690                 rdev->config.evergreen.sx_max_export_size = 128;
1691                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1692                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1693                 rdev->config.evergreen.max_hw_contexts = 4;
1694                 rdev->config.evergreen.sq_num_cf_insts = 1;
1695
1696                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1697                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1698                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1699                 break;
1700         case CHIP_PALM:
1701                 rdev->config.evergreen.num_ses = 1;
1702                 rdev->config.evergreen.max_pipes = 2;
1703                 rdev->config.evergreen.max_tile_pipes = 2;
1704                 rdev->config.evergreen.max_simds = 2;
1705                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1706                 rdev->config.evergreen.max_gprs = 256;
1707                 rdev->config.evergreen.max_threads = 192;
1708                 rdev->config.evergreen.max_gs_threads = 16;
1709                 rdev->config.evergreen.max_stack_entries = 256;
1710                 rdev->config.evergreen.sx_num_of_sets = 4;
1711                 rdev->config.evergreen.sx_max_export_size = 128;
1712                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1713                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1714                 rdev->config.evergreen.max_hw_contexts = 4;
1715                 rdev->config.evergreen.sq_num_cf_insts = 1;
1716
1717                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1718                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1719                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1720                 break;
1721         case CHIP_SUMO:
1722                 rdev->config.evergreen.num_ses = 1;
1723                 rdev->config.evergreen.max_pipes = 4;
1724                 rdev->config.evergreen.max_tile_pipes = 2;
1725                 if (rdev->pdev->device == 0x9648)
1726                         rdev->config.evergreen.max_simds = 3;
1727                 else if ((rdev->pdev->device == 0x9647) ||
1728                          (rdev->pdev->device == 0x964a))
1729                         rdev->config.evergreen.max_simds = 4;
1730                 else
1731                         rdev->config.evergreen.max_simds = 5;
1732                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1733                 rdev->config.evergreen.max_gprs = 256;
1734                 rdev->config.evergreen.max_threads = 248;
1735                 rdev->config.evergreen.max_gs_threads = 32;
1736                 rdev->config.evergreen.max_stack_entries = 256;
1737                 rdev->config.evergreen.sx_num_of_sets = 4;
1738                 rdev->config.evergreen.sx_max_export_size = 256;
1739                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1740                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1741                 rdev->config.evergreen.max_hw_contexts = 8;
1742                 rdev->config.evergreen.sq_num_cf_insts = 2;
1743
1744                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1745                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1746                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1747                 break;
1748         case CHIP_SUMO2:
1749                 rdev->config.evergreen.num_ses = 1;
1750                 rdev->config.evergreen.max_pipes = 4;
1751                 rdev->config.evergreen.max_tile_pipes = 4;
1752                 rdev->config.evergreen.max_simds = 2;
1753                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1754                 rdev->config.evergreen.max_gprs = 256;
1755                 rdev->config.evergreen.max_threads = 248;
1756                 rdev->config.evergreen.max_gs_threads = 32;
1757                 rdev->config.evergreen.max_stack_entries = 512;
1758                 rdev->config.evergreen.sx_num_of_sets = 4;
1759                 rdev->config.evergreen.sx_max_export_size = 256;
1760                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1761                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1762                 rdev->config.evergreen.max_hw_contexts = 8;
1763                 rdev->config.evergreen.sq_num_cf_insts = 2;
1764
1765                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1766                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1767                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1768                 break;
1769         case CHIP_BARTS:
1770                 rdev->config.evergreen.num_ses = 2;
1771                 rdev->config.evergreen.max_pipes = 4;
1772                 rdev->config.evergreen.max_tile_pipes = 8;
1773                 rdev->config.evergreen.max_simds = 7;
1774                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1775                 rdev->config.evergreen.max_gprs = 256;
1776                 rdev->config.evergreen.max_threads = 248;
1777                 rdev->config.evergreen.max_gs_threads = 32;
1778                 rdev->config.evergreen.max_stack_entries = 512;
1779                 rdev->config.evergreen.sx_num_of_sets = 4;
1780                 rdev->config.evergreen.sx_max_export_size = 256;
1781                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1782                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1783                 rdev->config.evergreen.max_hw_contexts = 8;
1784                 rdev->config.evergreen.sq_num_cf_insts = 2;
1785
1786                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1787                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1788                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1789                 break;
1790         case CHIP_TURKS:
1791                 rdev->config.evergreen.num_ses = 1;
1792                 rdev->config.evergreen.max_pipes = 4;
1793                 rdev->config.evergreen.max_tile_pipes = 4;
1794                 rdev->config.evergreen.max_simds = 6;
1795                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1796                 rdev->config.evergreen.max_gprs = 256;
1797                 rdev->config.evergreen.max_threads = 248;
1798                 rdev->config.evergreen.max_gs_threads = 32;
1799                 rdev->config.evergreen.max_stack_entries = 256;
1800                 rdev->config.evergreen.sx_num_of_sets = 4;
1801                 rdev->config.evergreen.sx_max_export_size = 256;
1802                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1803                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1804                 rdev->config.evergreen.max_hw_contexts = 8;
1805                 rdev->config.evergreen.sq_num_cf_insts = 2;
1806
1807                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1808                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1809                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1810                 break;
1811         case CHIP_CAICOS:
1812                 rdev->config.evergreen.num_ses = 1;
1813                 rdev->config.evergreen.max_pipes = 4;
1814                 rdev->config.evergreen.max_tile_pipes = 2;
1815                 rdev->config.evergreen.max_simds = 2;
1816                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1817                 rdev->config.evergreen.max_gprs = 256;
1818                 rdev->config.evergreen.max_threads = 192;
1819                 rdev->config.evergreen.max_gs_threads = 16;
1820                 rdev->config.evergreen.max_stack_entries = 256;
1821                 rdev->config.evergreen.sx_num_of_sets = 4;
1822                 rdev->config.evergreen.sx_max_export_size = 128;
1823                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1824                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1825                 rdev->config.evergreen.max_hw_contexts = 4;
1826                 rdev->config.evergreen.sq_num_cf_insts = 1;
1827
1828                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1829                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1830                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1831                 break;
1832         }
1833
1834         /* Initialize HDP */
1835         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1836                 WREG32((0x2c14 + j), 0x00000000);
1837                 WREG32((0x2c18 + j), 0x00000000);
1838                 WREG32((0x2c1c + j), 0x00000000);
1839                 WREG32((0x2c20 + j), 0x00000000);
1840                 WREG32((0x2c24 + j), 0x00000000);
1841         }
1842
1843         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1844
1845         evergreen_fix_pci_max_read_req_size(rdev);
1846
1847         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1848
1849         cc_gc_shader_pipe_config |=
1850                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1851                                   & EVERGREEN_MAX_PIPES_MASK);
1852         cc_gc_shader_pipe_config |=
1853                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1854                                & EVERGREEN_MAX_SIMDS_MASK);
1855
1856         cc_rb_backend_disable =
1857                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1858                                 & EVERGREEN_MAX_BACKENDS_MASK);
1859
1860
1861         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1862         if (rdev->flags & RADEON_IS_IGP)
1863                 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1864         else
1865                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1866
1867         switch (rdev->config.evergreen.max_tile_pipes) {
1868         case 1:
1869         default:
1870                 gb_addr_config |= NUM_PIPES(0);
1871                 break;
1872         case 2:
1873                 gb_addr_config |= NUM_PIPES(1);
1874                 break;
1875         case 4:
1876                 gb_addr_config |= NUM_PIPES(2);
1877                 break;
1878         case 8:
1879                 gb_addr_config |= NUM_PIPES(3);
1880                 break;
1881         }
1882
1883         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1884         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1885         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1886         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1887         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1888         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1889
1890         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1891                 gb_addr_config |= ROW_SIZE(2);
1892         else
1893                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1894
1895         if (rdev->ddev->pdev->device == 0x689e) {
1896                 u32 efuse_straps_4;
1897                 u32 efuse_straps_3;
1898                 u8 efuse_box_bit_131_124;
1899
1900                 WREG32(RCU_IND_INDEX, 0x204);
1901                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1902                 WREG32(RCU_IND_INDEX, 0x203);
1903                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1904                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1905
1906                 switch(efuse_box_bit_131_124) {
1907                 case 0x00:
1908                         gb_backend_map = 0x76543210;
1909                         break;
1910                 case 0x55:
1911                         gb_backend_map = 0x77553311;
1912                         break;
1913                 case 0x56:
1914                         gb_backend_map = 0x77553300;
1915                         break;
1916                 case 0x59:
1917                         gb_backend_map = 0x77552211;
1918                         break;
1919                 case 0x66:
1920                         gb_backend_map = 0x77443300;
1921                         break;
1922                 case 0x99:
1923                         gb_backend_map = 0x66552211;
1924                         break;
1925                 case 0x5a:
1926                         gb_backend_map = 0x77552200;
1927                         break;
1928                 case 0xaa:
1929                         gb_backend_map = 0x66442200;
1930                         break;
1931                 case 0x95:
1932                         gb_backend_map = 0x66553311;
1933                         break;
1934                 default:
1935                         DRM_ERROR("bad backend map, using default\n");
1936                         gb_backend_map =
1937                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1938                                                                        rdev->config.evergreen.max_tile_pipes,
1939                                                                        rdev->config.evergreen.max_backends,
1940                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1941                                                                    rdev->config.evergreen.max_backends) &
1942                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1943                         break;
1944                 }
1945         } else if (rdev->ddev->pdev->device == 0x68b9) {
1946                 u32 efuse_straps_3;
1947                 u8 efuse_box_bit_127_124;
1948
1949                 WREG32(RCU_IND_INDEX, 0x203);
1950                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1951                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1952
1953                 switch(efuse_box_bit_127_124) {
1954                 case 0x0:
1955                         gb_backend_map = 0x00003210;
1956                         break;
1957                 case 0x5:
1958                 case 0x6:
1959                 case 0x9:
1960                 case 0xa:
1961                         gb_backend_map = 0x00003311;
1962                         break;
1963                 default:
1964                         DRM_ERROR("bad backend map, using default\n");
1965                         gb_backend_map =
1966                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1967                                                                        rdev->config.evergreen.max_tile_pipes,
1968                                                                        rdev->config.evergreen.max_backends,
1969                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1970                                                                    rdev->config.evergreen.max_backends) &
1971                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1972                         break;
1973                 }
1974         } else {
1975                 switch (rdev->family) {
1976                 case CHIP_CYPRESS:
1977                 case CHIP_HEMLOCK:
1978                 case CHIP_BARTS:
1979                         gb_backend_map = 0x66442200;
1980                         break;
1981                 case CHIP_JUNIPER:
1982                         gb_backend_map = 0x00002200;
1983                         break;
1984                 default:
1985                         gb_backend_map =
1986                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1987                                                                        rdev->config.evergreen.max_tile_pipes,
1988                                                                        rdev->config.evergreen.max_backends,
1989                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1990                                                                          rdev->config.evergreen.max_backends) &
1991                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1992                 }
1993         }
1994
1995         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1996          * not have bank info, so create a custom tiling dword.
1997          * bits 3:0   num_pipes
1998          * bits 7:4   num_banks
1999          * bits 11:8  group_size
2000          * bits 15:12 row_size
2001          */
2002         rdev->config.evergreen.tile_config = 0;
2003         switch (rdev->config.evergreen.max_tile_pipes) {
2004         case 1:
2005         default:
2006                 rdev->config.evergreen.tile_config |= (0 << 0);
2007                 break;
2008         case 2:
2009                 rdev->config.evergreen.tile_config |= (1 << 0);
2010                 break;
2011         case 4:
2012                 rdev->config.evergreen.tile_config |= (2 << 0);
2013                 break;
2014         case 8:
2015                 rdev->config.evergreen.tile_config |= (3 << 0);
2016                 break;
2017         }
2018         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2019         if (rdev->flags & RADEON_IS_IGP)
2020                 rdev->config.evergreen.tile_config |= 1 << 4;
2021         else
2022                 rdev->config.evergreen.tile_config |=
2023                         ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
2024         rdev->config.evergreen.tile_config |=
2025                 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2026         rdev->config.evergreen.tile_config |=
2027                 ((gb_addr_config & 0x30000000) >> 28) << 12;
2028
2029         rdev->config.evergreen.backend_map = gb_backend_map;
2030         WREG32(GB_BACKEND_MAP, gb_backend_map);
2031         WREG32(GB_ADDR_CONFIG, gb_addr_config);
2032         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2033         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2034
2035         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2036         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2037
2038         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2039                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2040                 u32 sp = cc_gc_shader_pipe_config;
2041                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2042
2043                 if (i == num_shader_engines) {
2044                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2045                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2046                 }
2047
2048                 WREG32(GRBM_GFX_INDEX, gfx);
2049                 WREG32(RLC_GFX_INDEX, gfx);
2050
2051                 WREG32(CC_RB_BACKEND_DISABLE, rb);
2052                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2053                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2054                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2055         }
2056
2057         grbm_gfx_index |= SE_BROADCAST_WRITES;
2058         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2059         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2060
2061         WREG32(CGTS_SYS_TCC_DISABLE, 0);
2062         WREG32(CGTS_TCC_DISABLE, 0);
2063         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2064         WREG32(CGTS_USER_TCC_DISABLE, 0);
2065
2066         /* set HW defaults for 3D engine */
2067         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2068                                      ROQ_IB2_START(0x2b)));
2069
2070         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2071
2072         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2073                              SYNC_GRADIENT |
2074                              SYNC_WALKER |
2075                              SYNC_ALIGNER));
2076
2077         sx_debug_1 = RREG32(SX_DEBUG_1);
2078         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2079         WREG32(SX_DEBUG_1, sx_debug_1);
2080
2081
2082         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2083         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2084         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2085         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2086
2087         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2088                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2089                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2090
2091         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2092                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2093                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2094
2095         WREG32(VGT_NUM_INSTANCES, 1);
2096         WREG32(SPI_CONFIG_CNTL, 0);
2097         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2098         WREG32(CP_PERFMON_CNTL, 0);
2099
2100         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2101                                   FETCH_FIFO_HIWATER(0x4) |
2102                                   DONE_FIFO_HIWATER(0xe0) |
2103                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2104
2105         sq_config = RREG32(SQ_CONFIG);
2106         sq_config &= ~(PS_PRIO(3) |
2107                        VS_PRIO(3) |
2108                        GS_PRIO(3) |
2109                        ES_PRIO(3));
2110         sq_config |= (VC_ENABLE |
2111                       EXPORT_SRC_C |
2112                       PS_PRIO(0) |
2113                       VS_PRIO(1) |
2114                       GS_PRIO(2) |
2115                       ES_PRIO(3));
2116
2117         switch (rdev->family) {
2118         case CHIP_CEDAR:
2119         case CHIP_PALM:
2120         case CHIP_SUMO:
2121         case CHIP_SUMO2:
2122         case CHIP_CAICOS:
2123                 /* no vertex cache */
2124                 sq_config &= ~VC_ENABLE;
2125                 break;
2126         default:
2127                 break;
2128         }
2129
2130         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2131
2132         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2133         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2134         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2135         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2136         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2137         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2138         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2139
2140         switch (rdev->family) {
2141         case CHIP_CEDAR:
2142         case CHIP_PALM:
2143         case CHIP_SUMO:
2144         case CHIP_SUMO2:
2145                 ps_thread_count = 96;
2146                 break;
2147         default:
2148                 ps_thread_count = 128;
2149                 break;
2150         }
2151
2152         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2153         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2154         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2155         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2156         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2157         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2158
2159         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2160         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2161         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2162         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2163         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2164         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2165
2166         WREG32(SQ_CONFIG, sq_config);
2167         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2168         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2169         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2170         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2171         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2172         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2173         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2174         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2175         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2176         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2177
2178         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2179                                           FORCE_EOV_MAX_REZ_CNT(255)));
2180
2181         switch (rdev->family) {
2182         case CHIP_CEDAR:
2183         case CHIP_PALM:
2184         case CHIP_SUMO:
2185         case CHIP_SUMO2:
2186         case CHIP_CAICOS:
2187                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2188                 break;
2189         default:
2190                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2191                 break;
2192         }
2193         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2194         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2195
2196         WREG32(VGT_GS_VERTEX_REUSE, 16);
2197         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2198         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2199
2200         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2201         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2202
2203         WREG32(CB_PERF_CTR0_SEL_0, 0);
2204         WREG32(CB_PERF_CTR0_SEL_1, 0);
2205         WREG32(CB_PERF_CTR1_SEL_0, 0);
2206         WREG32(CB_PERF_CTR1_SEL_1, 0);
2207         WREG32(CB_PERF_CTR2_SEL_0, 0);
2208         WREG32(CB_PERF_CTR2_SEL_1, 0);
2209         WREG32(CB_PERF_CTR3_SEL_0, 0);
2210         WREG32(CB_PERF_CTR3_SEL_1, 0);
2211
2212         /* clear render buffer base addresses */
2213         WREG32(CB_COLOR0_BASE, 0);
2214         WREG32(CB_COLOR1_BASE, 0);
2215         WREG32(CB_COLOR2_BASE, 0);
2216         WREG32(CB_COLOR3_BASE, 0);
2217         WREG32(CB_COLOR4_BASE, 0);
2218         WREG32(CB_COLOR5_BASE, 0);
2219         WREG32(CB_COLOR6_BASE, 0);
2220         WREG32(CB_COLOR7_BASE, 0);
2221         WREG32(CB_COLOR8_BASE, 0);
2222         WREG32(CB_COLOR9_BASE, 0);
2223         WREG32(CB_COLOR10_BASE, 0);
2224         WREG32(CB_COLOR11_BASE, 0);
2225
2226         /* set the shader const cache sizes to 0 */
2227         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2228                 WREG32(i, 0);
2229         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2230                 WREG32(i, 0);
2231
2232         tmp = RREG32(HDP_MISC_CNTL);
2233         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2234         WREG32(HDP_MISC_CNTL, tmp);
2235
2236         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2237         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2238
2239         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2240
2241         udelay(50);
2242
2243 }
2244
2245 int evergreen_mc_init(struct radeon_device *rdev)
2246 {
2247         u32 tmp;
2248         int chansize, numchan;
2249
2250         /* Get VRAM informations */
2251         rdev->mc.vram_is_ddr = true;
2252         if (rdev->flags & RADEON_IS_IGP)
2253                 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2254         else
2255                 tmp = RREG32(MC_ARB_RAMCFG);
2256         if (tmp & CHANSIZE_OVERRIDE) {
2257                 chansize = 16;
2258         } else if (tmp & CHANSIZE_MASK) {
2259                 chansize = 64;
2260         } else {
2261                 chansize = 32;
2262         }
2263         tmp = RREG32(MC_SHARED_CHMAP);
2264         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2265         case 0:
2266         default:
2267                 numchan = 1;
2268                 break;
2269         case 1:
2270                 numchan = 2;
2271                 break;
2272         case 2:
2273                 numchan = 4;
2274                 break;
2275         case 3:
2276                 numchan = 8;
2277                 break;
2278         }
2279         rdev->mc.vram_width = numchan * chansize;
2280         /* Could aper size report 0 ? */
2281         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2282         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2283         /* Setup GPU memory space */
2284         if (rdev->flags & RADEON_IS_IGP) {
2285                 /* size in bytes on fusion */
2286                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2287                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2288         } else {
2289                 /* size in MB on evergreen */
2290                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2291                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2292         }
2293         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2294         r700_vram_gtt_location(rdev, &rdev->mc);
2295         radeon_update_bandwidth_info(rdev);
2296
2297         return 0;
2298 }
2299
2300 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2301 {
2302         u32 srbm_status;
2303         u32 grbm_status;
2304         u32 grbm_status_se0, grbm_status_se1;
2305         struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2306         int r;
2307
2308         srbm_status = RREG32(SRBM_STATUS);
2309         grbm_status = RREG32(GRBM_STATUS);
2310         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2311         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2312         if (!(grbm_status & GUI_ACTIVE)) {
2313                 r100_gpu_lockup_update(lockup, &rdev->cp);
2314                 return false;
2315         }
2316         /* force CP activities */
2317         r = radeon_ring_lock(rdev, 2);
2318         if (!r) {
2319                 /* PACKET2 NOP */
2320                 radeon_ring_write(rdev, 0x80000000);
2321                 radeon_ring_write(rdev, 0x80000000);
2322                 radeon_ring_unlock_commit(rdev);
2323         }
2324         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2325         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2326 }
2327
2328 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2329 {
2330         struct evergreen_mc_save save;
2331         u32 grbm_reset = 0;
2332
2333         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2334                 return 0;
2335
2336         dev_info(rdev->dev, "GPU softreset \n");
2337         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2338                 RREG32(GRBM_STATUS));
2339         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2340                 RREG32(GRBM_STATUS_SE0));
2341         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2342                 RREG32(GRBM_STATUS_SE1));
2343         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2344                 RREG32(SRBM_STATUS));
2345         evergreen_mc_stop(rdev, &save);
2346         if (evergreen_mc_wait_for_idle(rdev)) {
2347                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2348         }
2349         /* Disable CP parsing/prefetching */
2350         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2351
2352         /* reset all the gfx blocks */
2353         grbm_reset = (SOFT_RESET_CP |
2354                       SOFT_RESET_CB |
2355                       SOFT_RESET_DB |
2356                       SOFT_RESET_PA |
2357                       SOFT_RESET_SC |
2358                       SOFT_RESET_SPI |
2359                       SOFT_RESET_SH |
2360                       SOFT_RESET_SX |
2361                       SOFT_RESET_TC |
2362                       SOFT_RESET_TA |
2363                       SOFT_RESET_VC |
2364                       SOFT_RESET_VGT);
2365
2366         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2367         WREG32(GRBM_SOFT_RESET, grbm_reset);
2368         (void)RREG32(GRBM_SOFT_RESET);
2369         udelay(50);
2370         WREG32(GRBM_SOFT_RESET, 0);
2371         (void)RREG32(GRBM_SOFT_RESET);
2372         /* Wait a little for things to settle down */
2373         udelay(50);
2374         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2375                 RREG32(GRBM_STATUS));
2376         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2377                 RREG32(GRBM_STATUS_SE0));
2378         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2379                 RREG32(GRBM_STATUS_SE1));
2380         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2381                 RREG32(SRBM_STATUS));
2382         evergreen_mc_resume(rdev, &save);
2383         return 0;
2384 }
2385
2386 int evergreen_asic_reset(struct radeon_device *rdev)
2387 {
2388         return evergreen_gpu_soft_reset(rdev);
2389 }
2390
2391 /* Interrupts */
2392
2393 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2394 {
2395         switch (crtc) {
2396         case 0:
2397                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2398         case 1:
2399                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2400         case 2:
2401                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2402         case 3:
2403                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2404         case 4:
2405                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2406         case 5:
2407                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2408         default:
2409                 return 0;
2410         }
2411 }
2412
2413 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2414 {
2415         u32 tmp;
2416
2417         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2418         WREG32(GRBM_INT_CNTL, 0);
2419         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2420         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2421         if (rdev->num_crtc >= 4) {
2422                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2423                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2424         }
2425         if (rdev->num_crtc >= 6) {
2426                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2427                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2428         }
2429
2430         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2431         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2432         if (rdev->num_crtc >= 4) {
2433                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2434                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2435         }
2436         if (rdev->num_crtc >= 6) {
2437                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2438                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2439         }
2440
2441         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2442         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2443
2444         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2445         WREG32(DC_HPD1_INT_CONTROL, tmp);
2446         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2447         WREG32(DC_HPD2_INT_CONTROL, tmp);
2448         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2449         WREG32(DC_HPD3_INT_CONTROL, tmp);
2450         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2451         WREG32(DC_HPD4_INT_CONTROL, tmp);
2452         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2453         WREG32(DC_HPD5_INT_CONTROL, tmp);
2454         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2455         WREG32(DC_HPD6_INT_CONTROL, tmp);
2456
2457 }
2458
2459 int evergreen_irq_set(struct radeon_device *rdev)
2460 {
2461         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2462         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2463         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2464         u32 grbm_int_cntl = 0;
2465         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2466
2467         if (!rdev->irq.installed) {
2468                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2469                 return -EINVAL;
2470         }
2471         /* don't enable anything if the ih is disabled */
2472         if (!rdev->ih.enabled) {
2473                 r600_disable_interrupts(rdev);
2474                 /* force the active interrupt state to all disabled */
2475                 evergreen_disable_interrupt_state(rdev);
2476                 return 0;
2477         }
2478
2479         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2480         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2481         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2482         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2483         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2484         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2485
2486         if (rdev->irq.sw_int) {
2487                 DRM_DEBUG("evergreen_irq_set: sw int\n");
2488                 cp_int_cntl |= RB_INT_ENABLE;
2489                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2490         }
2491         if (rdev->irq.crtc_vblank_int[0] ||
2492             rdev->irq.pflip[0]) {
2493                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2494                 crtc1 |= VBLANK_INT_MASK;
2495         }
2496         if (rdev->irq.crtc_vblank_int[1] ||
2497             rdev->irq.pflip[1]) {
2498                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2499                 crtc2 |= VBLANK_INT_MASK;
2500         }
2501         if (rdev->irq.crtc_vblank_int[2] ||
2502             rdev->irq.pflip[2]) {
2503                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2504                 crtc3 |= VBLANK_INT_MASK;
2505         }
2506         if (rdev->irq.crtc_vblank_int[3] ||
2507             rdev->irq.pflip[3]) {
2508                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2509                 crtc4 |= VBLANK_INT_MASK;
2510         }
2511         if (rdev->irq.crtc_vblank_int[4] ||
2512             rdev->irq.pflip[4]) {
2513                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2514                 crtc5 |= VBLANK_INT_MASK;
2515         }
2516         if (rdev->irq.crtc_vblank_int[5] ||
2517             rdev->irq.pflip[5]) {
2518                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2519                 crtc6 |= VBLANK_INT_MASK;
2520         }
2521         if (rdev->irq.hpd[0]) {
2522                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2523                 hpd1 |= DC_HPDx_INT_EN;
2524         }
2525         if (rdev->irq.hpd[1]) {
2526                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2527                 hpd2 |= DC_HPDx_INT_EN;
2528         }
2529         if (rdev->irq.hpd[2]) {
2530                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2531                 hpd3 |= DC_HPDx_INT_EN;
2532         }
2533         if (rdev->irq.hpd[3]) {
2534                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2535                 hpd4 |= DC_HPDx_INT_EN;
2536         }
2537         if (rdev->irq.hpd[4]) {
2538                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2539                 hpd5 |= DC_HPDx_INT_EN;
2540         }
2541         if (rdev->irq.hpd[5]) {
2542                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2543                 hpd6 |= DC_HPDx_INT_EN;
2544         }
2545         if (rdev->irq.gui_idle) {
2546                 DRM_DEBUG("gui idle\n");
2547                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2548         }
2549
2550         WREG32(CP_INT_CNTL, cp_int_cntl);
2551         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2552
2553         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2554         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2555         if (rdev->num_crtc >= 4) {
2556                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2557                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2558         }
2559         if (rdev->num_crtc >= 6) {
2560                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2561                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2562         }
2563
2564         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2565         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2566         if (rdev->num_crtc >= 4) {
2567                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2568                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2569         }
2570         if (rdev->num_crtc >= 6) {
2571                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2572                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2573         }
2574
2575         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2576         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2577         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2578         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2579         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2580         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2581
2582         return 0;
2583 }
2584
2585 static void evergreen_irq_ack(struct radeon_device *rdev)
2586 {
2587         u32 tmp;
2588
2589         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2590         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2591         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2592         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2593         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2594         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2595         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2596         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2597         if (rdev->num_crtc >= 4) {
2598                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2599                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2600         }
2601         if (rdev->num_crtc >= 6) {
2602                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2603                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2604         }
2605
2606         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2607                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2608         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2609                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2610         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2611                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2612         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2613                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2614         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2615                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2616         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2617                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2618
2619         if (rdev->num_crtc >= 4) {
2620                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2621                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2622                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2623                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2624                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2625                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2626                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2627                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2628                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2629                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2630                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2631                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2632         }
2633
2634         if (rdev->num_crtc >= 6) {
2635                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2636                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2637                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2638                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2639                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2640                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2641                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2642                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2643                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2644                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2645                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2646                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2647         }
2648
2649         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2650                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2651                 tmp |= DC_HPDx_INT_ACK;
2652                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2653         }
2654         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2655                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2656                 tmp |= DC_HPDx_INT_ACK;
2657                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2658         }
2659         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2660                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2661                 tmp |= DC_HPDx_INT_ACK;
2662                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2663         }
2664         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2665                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2666                 tmp |= DC_HPDx_INT_ACK;
2667                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2668         }
2669         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2670                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2671                 tmp |= DC_HPDx_INT_ACK;
2672                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2673         }
2674         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2675                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2676                 tmp |= DC_HPDx_INT_ACK;
2677                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2678         }
2679 }
2680
2681 void evergreen_irq_disable(struct radeon_device *rdev)
2682 {
2683         r600_disable_interrupts(rdev);
2684         /* Wait and acknowledge irq */
2685         mdelay(1);
2686         evergreen_irq_ack(rdev);
2687         evergreen_disable_interrupt_state(rdev);
2688 }
2689
2690 void evergreen_irq_suspend(struct radeon_device *rdev)
2691 {
2692         evergreen_irq_disable(rdev);
2693         r600_rlc_stop(rdev);
2694 }
2695
2696 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2697 {
2698         u32 wptr, tmp;
2699
2700         if (rdev->wb.enabled)
2701                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2702         else
2703                 wptr = RREG32(IH_RB_WPTR);
2704
2705         if (wptr & RB_OVERFLOW) {
2706                 /* When a ring buffer overflow happen start parsing interrupt
2707                  * from the last not overwritten vector (wptr + 16). Hopefully
2708                  * this should allow us to catchup.
2709                  */
2710                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2711                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2712                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2713                 tmp = RREG32(IH_RB_CNTL);
2714                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2715                 WREG32(IH_RB_CNTL, tmp);
2716         }
2717         return (wptr & rdev->ih.ptr_mask);
2718 }
2719
2720 int evergreen_irq_process(struct radeon_device *rdev)
2721 {
2722         u32 wptr;
2723         u32 rptr;
2724         u32 src_id, src_data;
2725         u32 ring_index;
2726         unsigned long flags;
2727         bool queue_hotplug = false;
2728
2729         if (!rdev->ih.enabled || rdev->shutdown)
2730                 return IRQ_NONE;
2731
2732         wptr = evergreen_get_ih_wptr(rdev);
2733         rptr = rdev->ih.rptr;
2734         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2735
2736         spin_lock_irqsave(&rdev->ih.lock, flags);
2737         if (rptr == wptr) {
2738                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2739                 return IRQ_NONE;
2740         }
2741 restart_ih:
2742         /* Order reading of wptr vs. reading of IH ring data */
2743         rmb();
2744
2745         /* display interrupts */
2746         evergreen_irq_ack(rdev);
2747
2748         rdev->ih.wptr = wptr;
2749         while (rptr != wptr) {
2750                 /* wptr/rptr are in bytes! */
2751                 ring_index = rptr / 4;
2752                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2753                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2754
2755                 switch (src_id) {
2756                 case 1: /* D1 vblank/vline */
2757                         switch (src_data) {
2758                         case 0: /* D1 vblank */
2759                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2760                                         if (rdev->irq.crtc_vblank_int[0]) {
2761                                                 drm_handle_vblank(rdev->ddev, 0);
2762                                                 rdev->pm.vblank_sync = true;
2763                                                 wake_up(&rdev->irq.vblank_queue);
2764                                         }
2765                                         if (rdev->irq.pflip[0])
2766                                                 radeon_crtc_handle_flip(rdev, 0);
2767                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2768                                         DRM_DEBUG("IH: D1 vblank\n");
2769                                 }
2770                                 break;
2771                         case 1: /* D1 vline */
2772                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2773                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2774                                         DRM_DEBUG("IH: D1 vline\n");
2775                                 }
2776                                 break;
2777                         default:
2778                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2779                                 break;
2780                         }
2781                         break;
2782                 case 2: /* D2 vblank/vline */
2783                         switch (src_data) {
2784                         case 0: /* D2 vblank */
2785                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2786                                         if (rdev->irq.crtc_vblank_int[1]) {
2787                                                 drm_handle_vblank(rdev->ddev, 1);
2788                                                 rdev->pm.vblank_sync = true;
2789                                                 wake_up(&rdev->irq.vblank_queue);
2790                                         }
2791                                         if (rdev->irq.pflip[1])
2792                                                 radeon_crtc_handle_flip(rdev, 1);
2793                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2794                                         DRM_DEBUG("IH: D2 vblank\n");
2795                                 }
2796                                 break;
2797                         case 1: /* D2 vline */
2798                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2799                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2800                                         DRM_DEBUG("IH: D2 vline\n");
2801                                 }
2802                                 break;
2803                         default:
2804                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2805                                 break;
2806                         }
2807                         break;
2808                 case 3: /* D3 vblank/vline */
2809                         switch (src_data) {
2810                         case 0: /* D3 vblank */
2811                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2812                                         if (rdev->irq.crtc_vblank_int[2]) {
2813                                                 drm_handle_vblank(rdev->ddev, 2);
2814                                                 rdev->pm.vblank_sync = true;
2815                                                 wake_up(&rdev->irq.vblank_queue);
2816                                         }
2817                                         if (rdev->irq.pflip[2])
2818                                                 radeon_crtc_handle_flip(rdev, 2);
2819                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2820                                         DRM_DEBUG("IH: D3 vblank\n");
2821                                 }
2822                                 break;
2823                         case 1: /* D3 vline */
2824                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2825                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2826                                         DRM_DEBUG("IH: D3 vline\n");
2827                                 }
2828                                 break;
2829                         default:
2830                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2831                                 break;
2832                         }
2833                         break;
2834                 case 4: /* D4 vblank/vline */
2835                         switch (src_data) {
2836                         case 0: /* D4 vblank */
2837                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2838                                         if (rdev->irq.crtc_vblank_int[3]) {
2839                                                 drm_handle_vblank(rdev->ddev, 3);
2840                                                 rdev->pm.vblank_sync = true;
2841                                                 wake_up(&rdev->irq.vblank_queue);
2842                                         }
2843                                         if (rdev->irq.pflip[3])
2844                                                 radeon_crtc_handle_flip(rdev, 3);
2845                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2846                                         DRM_DEBUG("IH: D4 vblank\n");
2847                                 }
2848                                 break;
2849                         case 1: /* D4 vline */
2850                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2851                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2852                                         DRM_DEBUG("IH: D4 vline\n");
2853                                 }
2854                                 break;
2855                         default:
2856                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2857                                 break;
2858                         }
2859                         break;
2860                 case 5: /* D5 vblank/vline */
2861                         switch (src_data) {
2862                         case 0: /* D5 vblank */
2863                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2864                                         if (rdev->irq.crtc_vblank_int[4]) {
2865                                                 drm_handle_vblank(rdev->ddev, 4);
2866                                                 rdev->pm.vblank_sync = true;
2867                                                 wake_up(&rdev->irq.vblank_queue);
2868                                         }
2869                                         if (rdev->irq.pflip[4])
2870                                                 radeon_crtc_handle_flip(rdev, 4);
2871                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2872                                         DRM_DEBUG("IH: D5 vblank\n");
2873                                 }
2874                                 break;
2875                         case 1: /* D5 vline */
2876                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2877                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2878                                         DRM_DEBUG("IH: D5 vline\n");
2879                                 }
2880                                 break;
2881                         default:
2882                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2883                                 break;
2884                         }
2885                         break;
2886                 case 6: /* D6 vblank/vline */
2887                         switch (src_data) {
2888                         case 0: /* D6 vblank */
2889                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2890                                         if (rdev->irq.crtc_vblank_int[5]) {
2891                                                 drm_handle_vblank(rdev->ddev, 5);
2892                                                 rdev->pm.vblank_sync = true;