2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
41 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
42 switch (radeon_encoder->encoder_id) {
43 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
44 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
45 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
46 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
47 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
48 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
49 case ENCODER_OBJECT_ID_INTERNAL_DDI:
50 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
51 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
52 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
53 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
60 static struct drm_connector *
61 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
63 struct drm_device *dev = encoder->dev;
64 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
65 struct drm_connector *connector;
66 struct radeon_connector *radeon_connector;
68 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
69 radeon_connector = to_radeon_connector(connector);
70 if (radeon_encoder->devices & radeon_connector->devices)
76 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
77 struct drm_display_mode *mode,
78 struct drm_display_mode *adjusted_mode)
80 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
81 struct drm_device *dev = encoder->dev;
82 struct radeon_device *rdev = dev->dev_private;
84 /* set the active encoder to connector routing */
85 radeon_encoder_set_active_device(encoder);
86 drm_mode_set_crtcinfo(adjusted_mode, 0);
89 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
90 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
91 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
93 /* get the native mode for LVDS */
94 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
95 radeon_panel_mode_fixup(encoder, adjusted_mode);
97 /* get the native mode for TV */
98 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
99 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 if (tv_dac->tv_std == TV_STD_NTSC ||
102 tv_dac->tv_std == TV_STD_NTSC_J ||
103 tv_dac->tv_std == TV_STD_PAL_M)
104 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
106 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
110 if (ASIC_IS_DCE3(rdev) &&
111 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
112 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
113 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
114 radeon_dp_set_link_config(connector, mode);
121 atombios_dac_setup(struct drm_encoder *encoder, int action)
123 struct drm_device *dev = encoder->dev;
124 struct radeon_device *rdev = dev->dev_private;
125 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
126 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
128 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
130 memset(&args, 0, sizeof(args));
132 switch (radeon_encoder->encoder_id) {
133 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
134 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
135 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
137 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
139 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
143 args.ucAction = action;
145 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
146 args.ucDacStandard = ATOM_DAC1_PS2;
147 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
148 args.ucDacStandard = ATOM_DAC1_CV;
150 switch (dac_info->tv_std) {
153 case TV_STD_SCART_PAL:
156 args.ucDacStandard = ATOM_DAC1_PAL;
162 args.ucDacStandard = ATOM_DAC1_NTSC;
166 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
173 atombios_tv_setup(struct drm_encoder *encoder, int action)
175 struct drm_device *dev = encoder->dev;
176 struct radeon_device *rdev = dev->dev_private;
177 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
178 TV_ENCODER_CONTROL_PS_ALLOCATION args;
180 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
182 memset(&args, 0, sizeof(args));
184 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
186 args.sTVEncoder.ucAction = action;
188 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
189 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
191 switch (dac_info->tv_std) {
193 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
196 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
199 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
202 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
205 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
207 case TV_STD_SCART_PAL:
208 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
211 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
214 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
217 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
222 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
224 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
228 union dvo_encoder_control {
229 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
230 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
231 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
235 atombios_dvo_setup(struct drm_encoder *encoder, int action)
237 struct drm_device *dev = encoder->dev;
238 struct radeon_device *rdev = dev->dev_private;
239 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
240 union dvo_encoder_control args;
241 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
244 memset(&args, 0, sizeof(args));
246 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
254 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
256 if (radeon_encoder->pixel_clock > 165000)
257 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
259 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
263 args.dvo.sDVOEncoder.ucAction = action;
264 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
265 /* DFP1, CRT1, TV1 depending on the type of port */
266 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
268 if (radeon_encoder->pixel_clock > 165000)
269 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
273 args.dvo_v3.ucAction = action;
274 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
275 args.dvo_v3.ucDVOConfig = 0; /* XXX */
278 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
283 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
287 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
290 union lvds_encoder_control {
291 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
292 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
296 atombios_digital_setup(struct drm_encoder *encoder, int action)
298 struct drm_device *dev = encoder->dev;
299 struct radeon_device *rdev = dev->dev_private;
300 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
301 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
302 union lvds_encoder_control args;
304 int hdmi_detected = 0;
310 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
313 memset(&args, 0, sizeof(args));
315 switch (radeon_encoder->encoder_id) {
316 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
317 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
319 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
320 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
321 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
323 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
324 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
325 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
327 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
331 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
340 args.v1.ucAction = action;
342 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
343 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
344 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
345 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
346 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
347 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
348 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
351 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
352 if (radeon_encoder->pixel_clock > 165000)
353 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
354 /*if (pScrn->rgbBits == 8) */
355 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
361 args.v2.ucAction = action;
363 if (dig->coherent_mode)
364 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
367 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
368 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
369 args.v2.ucTruncate = 0;
370 args.v2.ucSpatial = 0;
371 args.v2.ucTemporal = 0;
373 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
374 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
375 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
376 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
377 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
378 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
379 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
381 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
382 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
383 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
384 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
385 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
386 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
390 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
391 if (radeon_encoder->pixel_clock > 165000)
392 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
396 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
401 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
405 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
409 atombios_get_encoder_mode(struct drm_encoder *encoder)
411 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
412 struct drm_device *dev = encoder->dev;
413 struct radeon_device *rdev = dev->dev_private;
414 struct drm_connector *connector;
415 struct radeon_connector *radeon_connector;
416 struct radeon_connector_atom_dig *dig_connector;
418 /* dp bridges are always DP */
419 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
420 return ATOM_ENCODER_MODE_DP;
422 /* DVO is always DVO */
423 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
424 return ATOM_ENCODER_MODE_DVO;
426 connector = radeon_get_connector_for_encoder(encoder);
427 /* if we don't have an active device yet, just use one of
428 * the connectors tied to the encoder.
431 connector = radeon_get_connector_for_encoder_init(encoder);
432 radeon_connector = to_radeon_connector(connector);
434 switch (connector->connector_type) {
435 case DRM_MODE_CONNECTOR_DVII:
436 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
437 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
439 if (ASIC_IS_DCE4(rdev))
440 return ATOM_ENCODER_MODE_DVI;
442 return ATOM_ENCODER_MODE_HDMI;
443 } else if (radeon_connector->use_digital)
444 return ATOM_ENCODER_MODE_DVI;
446 return ATOM_ENCODER_MODE_CRT;
448 case DRM_MODE_CONNECTOR_DVID:
449 case DRM_MODE_CONNECTOR_HDMIA:
451 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
453 if (ASIC_IS_DCE4(rdev))
454 return ATOM_ENCODER_MODE_DVI;
456 return ATOM_ENCODER_MODE_HDMI;
458 return ATOM_ENCODER_MODE_DVI;
460 case DRM_MODE_CONNECTOR_LVDS:
461 return ATOM_ENCODER_MODE_LVDS;
463 case DRM_MODE_CONNECTOR_DisplayPort:
464 dig_connector = radeon_connector->con_priv;
465 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
466 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
467 return ATOM_ENCODER_MODE_DP;
468 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
470 if (ASIC_IS_DCE4(rdev))
471 return ATOM_ENCODER_MODE_DVI;
473 return ATOM_ENCODER_MODE_HDMI;
475 return ATOM_ENCODER_MODE_DVI;
477 case DRM_MODE_CONNECTOR_eDP:
478 return ATOM_ENCODER_MODE_DP;
479 case DRM_MODE_CONNECTOR_DVIA:
480 case DRM_MODE_CONNECTOR_VGA:
481 return ATOM_ENCODER_MODE_CRT;
483 case DRM_MODE_CONNECTOR_Composite:
484 case DRM_MODE_CONNECTOR_SVIDEO:
485 case DRM_MODE_CONNECTOR_9PinDIN:
487 return ATOM_ENCODER_MODE_TV;
488 /*return ATOM_ENCODER_MODE_CV;*/
494 * DIG Encoder/Transmitter Setup
497 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
498 * Supports up to 3 digital outputs
499 * - 2 DIG encoder blocks.
500 * DIG1 can drive UNIPHY link A or link B
501 * DIG2 can drive UNIPHY link B or LVTMA
504 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
505 * Supports up to 5 digital outputs
506 * - 2 DIG encoder blocks.
507 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
510 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
511 * Supports up to 6 digital outputs
512 * - 6 DIG encoder blocks.
513 * - DIG to PHY mapping is hardcoded
514 * DIG1 drives UNIPHY0 link A, A+B
515 * DIG2 drives UNIPHY0 link B
516 * DIG3 drives UNIPHY1 link A, A+B
517 * DIG4 drives UNIPHY1 link B
518 * DIG5 drives UNIPHY2 link A, A+B
519 * DIG6 drives UNIPHY2 link B
522 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
523 * Supports up to 6 digital outputs
524 * - 2 DIG encoder blocks.
525 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
528 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
530 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
531 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
532 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
533 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
536 union dig_encoder_control {
537 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
538 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
539 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
540 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
544 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
546 struct drm_device *dev = encoder->dev;
547 struct radeon_device *rdev = dev->dev_private;
548 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
549 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
550 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
551 union dig_encoder_control args;
555 int dp_lane_count = 0;
556 int hpd_id = RADEON_HPD_NONE;
560 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
561 struct radeon_connector_atom_dig *dig_connector =
562 radeon_connector->con_priv;
564 dp_clock = dig_connector->dp_clock;
565 dp_lane_count = dig_connector->dp_lane_count;
566 hpd_id = radeon_connector->hpd.hpd;
567 bpc = connector->display_info.bpc;
570 /* no dig encoder assigned */
571 if (dig->dig_encoder == -1)
574 memset(&args, 0, sizeof(args));
576 if (ASIC_IS_DCE4(rdev))
577 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
579 if (dig->dig_encoder)
580 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
582 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
585 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
592 args.v1.ucAction = action;
593 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
594 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
595 args.v3.ucPanelMode = panel_mode;
597 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
599 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
600 args.v1.ucLaneNum = dp_lane_count;
601 else if (radeon_encoder->pixel_clock > 165000)
602 args.v1.ucLaneNum = 8;
604 args.v1.ucLaneNum = 4;
606 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
607 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
608 switch (radeon_encoder->encoder_id) {
609 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
610 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
612 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
613 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
614 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
616 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
617 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
621 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
623 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
627 args.v3.ucAction = action;
628 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
629 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
630 args.v3.ucPanelMode = panel_mode;
632 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
634 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
635 args.v3.ucLaneNum = dp_lane_count;
636 else if (radeon_encoder->pixel_clock > 165000)
637 args.v3.ucLaneNum = 8;
639 args.v3.ucLaneNum = 4;
641 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
642 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
643 args.v3.acConfig.ucDigSel = dig->dig_encoder;
646 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
649 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
653 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
656 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
659 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
662 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
667 args.v4.ucAction = action;
668 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
669 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
670 args.v4.ucPanelMode = panel_mode;
672 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
674 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
675 args.v4.ucLaneNum = dp_lane_count;
676 else if (radeon_encoder->pixel_clock > 165000)
677 args.v4.ucLaneNum = 8;
679 args.v4.ucLaneNum = 4;
681 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
682 if (dp_clock == 270000)
683 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
684 else if (dp_clock == 540000)
685 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
687 args.v4.acConfig.ucDigSel = dig->dig_encoder;
690 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
693 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
697 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
700 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
703 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
706 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
709 if (hpd_id == RADEON_HPD_NONE)
710 args.v4.ucHPD_ID = 0;
712 args.v4.ucHPD_ID = hpd_id + 1;
715 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
720 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
724 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
728 union dig_transmitter_control {
729 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
730 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
731 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
732 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
736 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
738 struct drm_device *dev = encoder->dev;
739 struct radeon_device *rdev = dev->dev_private;
740 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
741 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
742 struct drm_connector *connector;
743 union dig_transmitter_control args;
749 int dp_lane_count = 0;
750 int connector_object_id = 0;
751 int igp_lane_info = 0;
752 int dig_encoder = dig->dig_encoder;
754 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
755 connector = radeon_get_connector_for_encoder_init(encoder);
756 /* just needed to avoid bailing in the encoder check. the encoder
757 * isn't used for init
761 connector = radeon_get_connector_for_encoder(encoder);
764 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
765 struct radeon_connector_atom_dig *dig_connector =
766 radeon_connector->con_priv;
768 dp_clock = dig_connector->dp_clock;
769 dp_lane_count = dig_connector->dp_lane_count;
770 connector_object_id =
771 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
772 igp_lane_info = dig_connector->igp_lane_info;
776 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
777 pll_id = radeon_crtc->pll_id;
780 /* no dig encoder assigned */
781 if (dig_encoder == -1)
784 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
787 memset(&args, 0, sizeof(args));
789 switch (radeon_encoder->encoder_id) {
790 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
791 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
793 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
794 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
795 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
796 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
798 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
799 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
803 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
810 args.v1.ucAction = action;
811 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
812 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
813 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
814 args.v1.asMode.ucLaneSel = lane_num;
815 args.v1.asMode.ucLaneSet = lane_set;
818 args.v1.usPixelClock =
819 cpu_to_le16(dp_clock / 10);
820 else if (radeon_encoder->pixel_clock > 165000)
821 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
823 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
826 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
829 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
831 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
833 if ((rdev->flags & RADEON_IS_IGP) &&
834 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
835 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
836 if (igp_lane_info & 0x1)
837 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
838 else if (igp_lane_info & 0x2)
839 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
840 else if (igp_lane_info & 0x4)
841 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
842 else if (igp_lane_info & 0x8)
843 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
845 if (igp_lane_info & 0x3)
846 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
847 else if (igp_lane_info & 0xc)
848 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
853 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
855 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
858 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
859 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
860 if (dig->coherent_mode)
861 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
862 if (radeon_encoder->pixel_clock > 165000)
863 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
867 args.v2.ucAction = action;
868 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
869 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
870 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
871 args.v2.asMode.ucLaneSel = lane_num;
872 args.v2.asMode.ucLaneSet = lane_set;
875 args.v2.usPixelClock =
876 cpu_to_le16(dp_clock / 10);
877 else if (radeon_encoder->pixel_clock > 165000)
878 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
880 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
883 args.v2.acConfig.ucEncoderSel = dig_encoder;
885 args.v2.acConfig.ucLinkSel = 1;
887 switch (radeon_encoder->encoder_id) {
888 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
889 args.v2.acConfig.ucTransmitterSel = 0;
891 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
892 args.v2.acConfig.ucTransmitterSel = 1;
894 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
895 args.v2.acConfig.ucTransmitterSel = 2;
900 args.v2.acConfig.fCoherentMode = 1;
901 args.v2.acConfig.fDPConnector = 1;
902 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
903 if (dig->coherent_mode)
904 args.v2.acConfig.fCoherentMode = 1;
905 if (radeon_encoder->pixel_clock > 165000)
906 args.v2.acConfig.fDualLinkConnector = 1;
910 args.v3.ucAction = action;
911 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
912 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
913 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
914 args.v3.asMode.ucLaneSel = lane_num;
915 args.v3.asMode.ucLaneSet = lane_set;
918 args.v3.usPixelClock =
919 cpu_to_le16(dp_clock / 10);
920 else if (radeon_encoder->pixel_clock > 165000)
921 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
923 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
927 args.v3.ucLaneNum = dp_lane_count;
928 else if (radeon_encoder->pixel_clock > 165000)
929 args.v3.ucLaneNum = 8;
931 args.v3.ucLaneNum = 4;
934 args.v3.acConfig.ucLinkSel = 1;
936 args.v3.acConfig.ucEncoderSel = 1;
938 /* Select the PLL for the PHY
939 * DP PHY should be clocked from external src if there is
942 /* On DCE4, if there is an external clock, it generates the DP ref clock */
943 if (is_dp && rdev->clock.dp_extclk)
944 args.v3.acConfig.ucRefClkSource = 2; /* external src */
946 args.v3.acConfig.ucRefClkSource = pll_id;
948 switch (radeon_encoder->encoder_id) {
949 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
950 args.v3.acConfig.ucTransmitterSel = 0;
952 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
953 args.v3.acConfig.ucTransmitterSel = 1;
955 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
956 args.v3.acConfig.ucTransmitterSel = 2;
961 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
962 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
963 if (dig->coherent_mode)
964 args.v3.acConfig.fCoherentMode = 1;
965 if (radeon_encoder->pixel_clock > 165000)
966 args.v3.acConfig.fDualLinkConnector = 1;
970 args.v4.ucAction = action;
971 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
972 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
973 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
974 args.v4.asMode.ucLaneSel = lane_num;
975 args.v4.asMode.ucLaneSet = lane_set;
978 args.v4.usPixelClock =
979 cpu_to_le16(dp_clock / 10);
980 else if (radeon_encoder->pixel_clock > 165000)
981 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
983 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
987 args.v4.ucLaneNum = dp_lane_count;
988 else if (radeon_encoder->pixel_clock > 165000)
989 args.v4.ucLaneNum = 8;
991 args.v4.ucLaneNum = 4;
994 args.v4.acConfig.ucLinkSel = 1;
996 args.v4.acConfig.ucEncoderSel = 1;
998 /* Select the PLL for the PHY
999 * DP PHY should be clocked from external src if there is
1002 /* On DCE5 DCPLL usually generates the DP ref clock */
1004 if (rdev->clock.dp_extclk)
1005 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1007 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1009 args.v4.acConfig.ucRefClkSource = pll_id;
1011 switch (radeon_encoder->encoder_id) {
1012 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1013 args.v4.acConfig.ucTransmitterSel = 0;
1015 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1016 args.v4.acConfig.ucTransmitterSel = 1;
1018 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1019 args.v4.acConfig.ucTransmitterSel = 2;
1024 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1025 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1026 if (dig->coherent_mode)
1027 args.v4.acConfig.fCoherentMode = 1;
1028 if (radeon_encoder->pixel_clock > 165000)
1029 args.v4.acConfig.fDualLinkConnector = 1;
1033 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1038 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1042 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1046 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1048 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1049 struct drm_device *dev = radeon_connector->base.dev;
1050 struct radeon_device *rdev = dev->dev_private;
1051 union dig_transmitter_control args;
1052 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1055 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1058 if (!ASIC_IS_DCE4(rdev))
1061 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1062 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1065 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1068 memset(&args, 0, sizeof(args));
1070 args.v1.ucAction = action;
1072 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1074 /* wait for the panel to power up */
1075 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1078 for (i = 0; i < 300; i++) {
1079 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1089 union external_encoder_control {
1090 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1091 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1095 atombios_external_encoder_setup(struct drm_encoder *encoder,
1096 struct drm_encoder *ext_encoder,
1099 struct drm_device *dev = encoder->dev;
1100 struct radeon_device *rdev = dev->dev_private;
1101 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1102 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1103 union external_encoder_control args;
1104 struct drm_connector *connector;
1105 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1108 int dp_lane_count = 0;
1109 int connector_object_id = 0;
1110 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1113 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1114 connector = radeon_get_connector_for_encoder_init(encoder);
1116 connector = radeon_get_connector_for_encoder(encoder);
1119 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1120 struct radeon_connector_atom_dig *dig_connector =
1121 radeon_connector->con_priv;
1123 dp_clock = dig_connector->dp_clock;
1124 dp_lane_count = dig_connector->dp_lane_count;
1125 connector_object_id =
1126 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1127 bpc = connector->display_info.bpc;
1130 memset(&args, 0, sizeof(args));
1132 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1137 /* no params on frev 1 */
1143 args.v1.sDigEncoder.ucAction = action;
1144 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1145 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1147 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1148 if (dp_clock == 270000)
1149 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1150 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1151 } else if (radeon_encoder->pixel_clock > 165000)
1152 args.v1.sDigEncoder.ucLaneNum = 8;
1154 args.v1.sDigEncoder.ucLaneNum = 4;
1157 args.v3.sExtEncoder.ucAction = action;
1158 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1159 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1161 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1162 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1164 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1165 if (dp_clock == 270000)
1166 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1167 else if (dp_clock == 540000)
1168 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1169 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1170 } else if (radeon_encoder->pixel_clock > 165000)
1171 args.v3.sExtEncoder.ucLaneNum = 8;
1173 args.v3.sExtEncoder.ucLaneNum = 4;
1175 case GRAPH_OBJECT_ENUM_ID1:
1176 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1178 case GRAPH_OBJECT_ENUM_ID2:
1179 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1181 case GRAPH_OBJECT_ENUM_ID3:
1182 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1187 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1190 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1194 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1197 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1200 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1203 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1208 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1213 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1216 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1220 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1222 struct drm_device *dev = encoder->dev;
1223 struct radeon_device *rdev = dev->dev_private;
1224 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1226 ENABLE_YUV_PS_ALLOCATION args;
1227 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1230 memset(&args, 0, sizeof(args));
1232 if (rdev->family >= CHIP_R600)
1233 reg = R600_BIOS_3_SCRATCH;
1235 reg = RADEON_BIOS_3_SCRATCH;
1237 /* XXX: fix up scratch reg handling */
1239 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1240 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1241 (radeon_crtc->crtc_id << 18)));
1242 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1243 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1248 args.ucEnable = ATOM_ENABLE;
1249 args.ucCRTC = radeon_crtc->crtc_id;
1251 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1257 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1259 struct drm_device *dev = encoder->dev;
1260 struct radeon_device *rdev = dev->dev_private;
1261 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1262 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1265 memset(&args, 0, sizeof(args));
1267 switch (radeon_encoder->encoder_id) {
1268 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1269 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1270 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1272 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1273 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1274 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1275 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1277 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1278 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1280 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1281 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1282 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1284 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1286 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1287 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1288 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1289 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1290 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1291 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1293 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1295 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1296 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1297 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1298 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1299 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1300 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1302 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1309 case DRM_MODE_DPMS_ON:
1310 args.ucAction = ATOM_ENABLE;
1311 /* workaround for DVOOutputControl on some RS690 systems */
1312 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1313 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1314 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1315 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1316 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1318 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1319 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1320 args.ucAction = ATOM_LCD_BLON;
1321 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1324 case DRM_MODE_DPMS_STANDBY:
1325 case DRM_MODE_DPMS_SUSPEND:
1326 case DRM_MODE_DPMS_OFF:
1327 args.ucAction = ATOM_DISABLE;
1328 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1329 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1330 args.ucAction = ATOM_LCD_BLOFF;
1331 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1338 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1340 struct drm_device *dev = encoder->dev;
1341 struct radeon_device *rdev = dev->dev_private;
1342 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1343 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1344 struct radeon_connector *radeon_connector = NULL;
1345 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1348 radeon_connector = to_radeon_connector(connector);
1349 radeon_dig_connector = radeon_connector->con_priv;
1353 case DRM_MODE_DPMS_ON:
1354 /* some early dce3.2 boards have a bug in their transmitter control table */
1355 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730) ||
1356 ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev))
1357 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1359 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1360 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1361 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1362 atombios_set_edp_panel_power(connector,
1363 ATOM_TRANSMITTER_ACTION_POWER_ON);
1364 radeon_dig_connector->edp_on = true;
1366 radeon_dp_link_train(encoder, connector);
1367 if (ASIC_IS_DCE4(rdev))
1368 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1370 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1371 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1373 case DRM_MODE_DPMS_STANDBY:
1374 case DRM_MODE_DPMS_SUSPEND:
1375 case DRM_MODE_DPMS_OFF:
1376 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev))
1377 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1379 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1380 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1381 if (ASIC_IS_DCE4(rdev))
1382 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1383 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1384 atombios_set_edp_panel_power(connector,
1385 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1386 radeon_dig_connector->edp_on = false;
1389 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1390 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1396 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1397 struct drm_encoder *ext_encoder,
1400 struct drm_device *dev = encoder->dev;
1401 struct radeon_device *rdev = dev->dev_private;
1404 case DRM_MODE_DPMS_ON:
1406 if (ASIC_IS_DCE41(rdev)) {
1407 atombios_external_encoder_setup(encoder, ext_encoder,
1408 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1409 atombios_external_encoder_setup(encoder, ext_encoder,
1410 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1412 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1414 case DRM_MODE_DPMS_STANDBY:
1415 case DRM_MODE_DPMS_SUSPEND:
1416 case DRM_MODE_DPMS_OFF:
1417 if (ASIC_IS_DCE41(rdev)) {
1418 atombios_external_encoder_setup(encoder, ext_encoder,
1419 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1420 atombios_external_encoder_setup(encoder, ext_encoder,
1421 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1423 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1429 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1431 struct drm_device *dev = encoder->dev;
1432 struct radeon_device *rdev = dev->dev_private;
1433 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1434 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1436 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1437 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1438 radeon_encoder->active_device);
1439 switch (radeon_encoder->encoder_id) {
1440 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1441 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1442 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1443 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1444 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1445 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1446 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1447 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1448 radeon_atom_encoder_dpms_avivo(encoder, mode);
1450 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1451 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1452 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1453 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1454 radeon_atom_encoder_dpms_dig(encoder, mode);
1456 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1457 if (ASIC_IS_DCE5(rdev)) {
1459 case DRM_MODE_DPMS_ON:
1460 atombios_dvo_setup(encoder, ATOM_ENABLE);
1462 case DRM_MODE_DPMS_STANDBY:
1463 case DRM_MODE_DPMS_SUSPEND:
1464 case DRM_MODE_DPMS_OFF:
1465 atombios_dvo_setup(encoder, ATOM_DISABLE);
1468 } else if (ASIC_IS_DCE3(rdev))
1469 radeon_atom_encoder_dpms_dig(encoder, mode);
1471 radeon_atom_encoder_dpms_avivo(encoder, mode);
1473 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1474 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1475 if (ASIC_IS_DCE5(rdev)) {
1477 case DRM_MODE_DPMS_ON:
1478 atombios_dac_setup(encoder, ATOM_ENABLE);
1480 case DRM_MODE_DPMS_STANDBY:
1481 case DRM_MODE_DPMS_SUSPEND:
1482 case DRM_MODE_DPMS_OFF:
1483 atombios_dac_setup(encoder, ATOM_DISABLE);
1487 radeon_atom_encoder_dpms_avivo(encoder, mode);
1494 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1496 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1500 union crtc_source_param {
1501 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1502 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1506 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1508 struct drm_device *dev = encoder->dev;
1509 struct radeon_device *rdev = dev->dev_private;
1510 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1511 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1512 union crtc_source_param args;
1513 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1515 struct radeon_encoder_atom_dig *dig;
1517 memset(&args, 0, sizeof(args));
1519 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1527 if (ASIC_IS_AVIVO(rdev))
1528 args.v1.ucCRTC = radeon_crtc->crtc_id;
1530 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1531 args.v1.ucCRTC = radeon_crtc->crtc_id;
1533 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1536 switch (radeon_encoder->encoder_id) {
1537 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1538 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1539 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1541 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1542 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1543 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1544 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1546 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1548 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1549 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1550 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1551 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1553 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1554 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1555 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1556 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1557 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1558 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1560 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1562 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1563 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1564 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1565 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1566 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1567 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1569 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1574 args.v2.ucCRTC = radeon_crtc->crtc_id;
1575 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1576 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1578 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1579 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1580 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1581 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1583 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1585 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1586 switch (radeon_encoder->encoder_id) {
1587 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1588 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1589 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1590 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1591 dig = radeon_encoder->enc_priv;
1592 switch (dig->dig_encoder) {
1594 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1597 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1600 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1603 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1606 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1609 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1613 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1614 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1616 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1617 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1618 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1619 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1620 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1622 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1624 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1625 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1626 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1627 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1628 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1630 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1637 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1641 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1643 /* update scratch regs with new routing */
1644 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1648 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1649 struct drm_display_mode *mode)
1651 struct drm_device *dev = encoder->dev;
1652 struct radeon_device *rdev = dev->dev_private;
1653 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1654 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1656 /* Funky macbooks */
1657 if ((dev->pdev->device == 0x71C5) &&
1658 (dev->pdev->subsystem_vendor == 0x106b) &&
1659 (dev->pdev->subsystem_device == 0x0080)) {
1660 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1661 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1663 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1664 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1666 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1670 /* set scaler clears this on some chips */
1671 if (ASIC_IS_AVIVO(rdev) &&
1672 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1673 if (ASIC_IS_DCE4(rdev)) {
1674 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1675 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1676 EVERGREEN_INTERLEAVE_EN);
1678 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1680 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1681 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1682 AVIVO_D1MODE_INTERLEAVE_EN);
1684 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1689 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1691 struct drm_device *dev = encoder->dev;
1692 struct radeon_device *rdev = dev->dev_private;
1693 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1694 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1695 struct drm_encoder *test_encoder;
1696 struct radeon_encoder_atom_dig *dig;
1697 uint32_t dig_enc_in_use = 0;
1700 if (ASIC_IS_DCE4(rdev)) {
1701 dig = radeon_encoder->enc_priv;
1702 if (ASIC_IS_DCE41(rdev)) {
1703 /* ontario follows DCE4 */
1704 if (rdev->family == CHIP_PALM) {
1710 /* llano follows DCE3.2 */
1711 return radeon_crtc->crtc_id;
1713 switch (radeon_encoder->encoder_id) {
1714 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1720 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1726 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1736 /* on DCE32 and encoder can driver any block so just crtc id */
1737 if (ASIC_IS_DCE32(rdev)) {
1738 return radeon_crtc->crtc_id;
1741 /* on DCE3 - LVTMA can only be driven by DIGB */
1742 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1743 struct radeon_encoder *radeon_test_encoder;
1745 if (encoder == test_encoder)
1748 if (!radeon_encoder_is_digital(test_encoder))
1751 radeon_test_encoder = to_radeon_encoder(test_encoder);
1752 dig = radeon_test_encoder->enc_priv;
1754 if (dig->dig_encoder >= 0)
1755 dig_enc_in_use |= (1 << dig->dig_encoder);
1758 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1759 if (dig_enc_in_use & 0x2)
1760 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1763 if (!(dig_enc_in_use & 1))
1768 /* This only needs to be called once at startup */
1770 radeon_atom_encoder_init(struct radeon_device *rdev)
1772 struct drm_device *dev = rdev->ddev;
1773 struct drm_encoder *encoder;
1775 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1776 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1777 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1779 switch (radeon_encoder->encoder_id) {
1780 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1781 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1782 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1783 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1784 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1790 if (ext_encoder && ASIC_IS_DCE41(rdev))
1791 atombios_external_encoder_setup(encoder, ext_encoder,
1792 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1797 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1798 struct drm_display_mode *mode,
1799 struct drm_display_mode *adjusted_mode)
1801 struct drm_device *dev = encoder->dev;
1802 struct radeon_device *rdev = dev->dev_private;
1803 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1804 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1806 radeon_encoder->pixel_clock = adjusted_mode->clock;
1808 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1809 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1810 atombios_yuv_setup(encoder, true);
1812 atombios_yuv_setup(encoder, false);
1815 switch (radeon_encoder->encoder_id) {
1816 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1817 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1818 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1819 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1820 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1822 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1823 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1824 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1825 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1826 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1827 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1828 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1831 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1833 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1835 /* setup and enable the encoder */
1836 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1837 atombios_dig_encoder_setup(encoder,
1838 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1840 } else if (ASIC_IS_DCE4(rdev)) {
1841 /* disable the transmitter */
1842 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1843 /* setup and enable the encoder */
1844 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1846 /* enable the transmitter */
1847 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1849 /* disable the encoder and transmitter */
1850 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1851 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1853 /* setup and enable the encoder and transmitter */
1854 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1855 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1856 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1859 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1860 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1861 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1862 atombios_dvo_setup(encoder, ATOM_ENABLE);
1864 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1865 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1866 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1867 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1868 atombios_dac_setup(encoder, ATOM_ENABLE);
1869 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1870 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1871 atombios_tv_setup(encoder, ATOM_ENABLE);
1873 atombios_tv_setup(encoder, ATOM_DISABLE);
1879 if (ASIC_IS_DCE41(rdev))
1880 atombios_external_encoder_setup(encoder, ext_encoder,
1881 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1883 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1886 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1888 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1889 r600_hdmi_enable(encoder);
1890 r600_hdmi_setmode(encoder, adjusted_mode);
1895 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1897 struct drm_device *dev = encoder->dev;
1898 struct radeon_device *rdev = dev->dev_private;
1899 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1900 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1902 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1903 ATOM_DEVICE_CV_SUPPORT |
1904 ATOM_DEVICE_CRT_SUPPORT)) {
1905 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1906 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1909 memset(&args, 0, sizeof(args));
1911 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1914 args.sDacload.ucMisc = 0;
1916 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1917 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1918 args.sDacload.ucDacType = ATOM_DAC_A;
1920 args.sDacload.ucDacType = ATOM_DAC_B;
1922 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1923 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1924 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1925 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1926 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1927 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1929 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1930 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1931 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1933 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1936 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1943 static enum drm_connector_status
1944 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1946 struct drm_device *dev = encoder->dev;
1947 struct radeon_device *rdev = dev->dev_private;
1948 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1949 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1950 uint32_t bios_0_scratch;
1952 if (!atombios_dac_load_detect(encoder, connector)) {
1953 DRM_DEBUG_KMS("detect returned false \n");
1954 return connector_status_unknown;
1957 if (rdev->family >= CHIP_R600)
1958 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1960 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1962 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1963 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1964 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1965 return connector_status_connected;
1967 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1968 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1969 return connector_status_connected;
1971 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1972 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1973 return connector_status_connected;
1975 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1976 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1977 return connector_status_connected; /* CTV */
1978 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1979 return connector_status_connected; /* STV */
1981 return connector_status_disconnected;
1984 static enum drm_connector_status
1985 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1987 struct drm_device *dev = encoder->dev;
1988 struct radeon_device *rdev = dev->dev_private;
1989 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1990 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1991 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1994 if (!ASIC_IS_DCE4(rdev))
1995 return connector_status_unknown;
1998 return connector_status_unknown;
2000 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2001 return connector_status_unknown;
2003 /* load detect on the dp bridge */
2004 atombios_external_encoder_setup(encoder, ext_encoder,
2005 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2007 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2009 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2010 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2011 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2012 return connector_status_connected;
2014 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2015 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2016 return connector_status_connected;
2018 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2019 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2020 return connector_status_connected;
2022 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2023 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2024 return connector_status_connected; /* CTV */
2025 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2026 return connector_status_connected; /* STV */
2028 return connector_status_disconnected;
2032 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2034 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2037 /* ddc_setup on the dp bridge */
2038 atombios_external_encoder_setup(encoder, ext_encoder,
2039 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2043 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2045 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2046 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2048 if ((radeon_encoder->active_device &
2049 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2050 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2051 ENCODER_OBJECT_ID_NONE)) {
2052 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2054 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2057 radeon_atom_output_lock(encoder, true);
2058 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2061 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2063 /* select the clock/data port if it uses a router */
2064 if (radeon_connector->router.cd_valid)
2065 radeon_router_select_cd_port(radeon_connector);
2067 /* turn eDP panel on for mode set */
2068 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2069 atombios_set_edp_panel_power(connector,
2070 ATOM_TRANSMITTER_ACTION_POWER_ON);
2073 /* this is needed for the pll/ss setup to work correctly in some cases */
2074 atombios_set_encoder_crtc_source(encoder);
2077 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2079 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2080 radeon_atom_output_lock(encoder, false);
2083 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2085 struct drm_device *dev = encoder->dev;
2086 struct radeon_device *rdev = dev->dev_private;
2087 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2088 struct radeon_encoder_atom_dig *dig;
2090 /* check for pre-DCE3 cards with shared encoders;
2091 * can't really use the links individually, so don't disable
2092 * the encoder if it's in use by another connector
2094 if (!ASIC_IS_DCE3(rdev)) {
2095 struct drm_encoder *other_encoder;
2096 struct radeon_encoder *other_radeon_encoder;
2098 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2099 other_radeon_encoder = to_radeon_encoder(other_encoder);
2100 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2101 drm_helper_encoder_in_use(other_encoder))
2106 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2108 switch (radeon_encoder->encoder_id) {
2109 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2110 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2111 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2112 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2113 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2115 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2116 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2117 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2118 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2119 if (ASIC_IS_DCE4(rdev))
2120 /* disable the transmitter */
2121 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2123 /* disable the encoder and transmitter */
2124 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2125 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2128 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2129 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2130 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2131 atombios_dvo_setup(encoder, ATOM_DISABLE);
2133 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2134 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2135 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2136 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2137 atombios_dac_setup(encoder, ATOM_DISABLE);
2138 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2139 atombios_tv_setup(encoder, ATOM_DISABLE);
2144 if (radeon_encoder_is_digital(encoder)) {
2145 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2146 r600_hdmi_disable(encoder);
2147 dig = radeon_encoder->enc_priv;
2148 dig->dig_encoder = -1;
2150 radeon_encoder->active_device = 0;
2153 /* these are handled by the primary encoders */
2154 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2159 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2165 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2166 struct drm_display_mode *mode,
2167 struct drm_display_mode *adjusted_mode)
2172 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2178 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2183 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2184 struct drm_display_mode *mode,
2185 struct drm_display_mode *adjusted_mode)
2190 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2191 .dpms = radeon_atom_ext_dpms,
2192 .mode_fixup = radeon_atom_ext_mode_fixup,
2193 .prepare = radeon_atom_ext_prepare,
2194 .mode_set = radeon_atom_ext_mode_set,
2195 .commit = radeon_atom_ext_commit,
2196 .disable = radeon_atom_ext_disable,
2197 /* no detect for TMDS/LVDS yet */
2200 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2201 .dpms = radeon_atom_encoder_dpms,
2202 .mode_fixup = radeon_atom_mode_fixup,
2203 .prepare = radeon_atom_encoder_prepare,
2204 .mode_set = radeon_atom_encoder_mode_set,
2205 .commit = radeon_atom_encoder_commit,
2206 .disable = radeon_atom_encoder_disable,
2207 .detect = radeon_atom_dig_detect,
2210 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2211 .dpms = radeon_atom_encoder_dpms,
2212 .mode_fixup = radeon_atom_mode_fixup,
2213 .prepare = radeon_atom_encoder_prepare,
2214 .mode_set = radeon_atom_encoder_mode_set,
2215 .commit = radeon_atom_encoder_commit,
2216 .detect = radeon_atom_dac_detect,
2219 void radeon_enc_destroy(struct drm_encoder *encoder)
2221 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2222 kfree(radeon_encoder->enc_priv);
2223 drm_encoder_cleanup(encoder);
2224 kfree(radeon_encoder);
2227 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2228 .destroy = radeon_enc_destroy,
2231 struct radeon_encoder_atom_dac *
2232 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2234 struct drm_device *dev = radeon_encoder->base.dev;
2235 struct radeon_device *rdev = dev->dev_private;
2236 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2241 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2245 struct radeon_encoder_atom_dig *
2246 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2248 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2249 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2254 /* coherent mode by default */
2255 dig->coherent_mode = true;
2256 dig->dig_encoder = -1;
2258 if (encoder_enum == 2)
2267 radeon_add_atom_encoder(struct drm_device *dev,
2268 uint32_t encoder_enum,
2269 uint32_t supported_device,
2272 struct radeon_device *rdev = dev->dev_private;
2273 struct drm_encoder *encoder;
2274 struct radeon_encoder *radeon_encoder;
2276 /* see if we already added it */
2277 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2278 radeon_encoder = to_radeon_encoder(encoder);
2279 if (radeon_encoder->encoder_enum == encoder_enum) {
2280 radeon_encoder->devices |= supported_device;
2287 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2288 if (!radeon_encoder)
2291 encoder = &radeon_encoder->base;
2292 switch (rdev->num_crtc) {
2294 encoder->possible_crtcs = 0x1;
2298 encoder->possible_crtcs = 0x3;
2301 encoder->possible_crtcs = 0xf;
2304 encoder->possible_crtcs = 0x3f;
2308 radeon_encoder->enc_priv = NULL;
2310 radeon_encoder->encoder_enum = encoder_enum;
2311 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2312 radeon_encoder->devices = supported_device;
2313 radeon_encoder->rmx_type = RMX_OFF;
2314 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2315 radeon_encoder->is_ext_encoder = false;
2316 radeon_encoder->caps = caps;
2318 switch (radeon_encoder->encoder_id) {
2319 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2320 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2321 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2322 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2323 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2324 radeon_encoder->rmx_type = RMX_FULL;
2325 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2326 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2328 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2329 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2331 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2333 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2334 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2335 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2336 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2338 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2339 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2340 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2341 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2342 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2343 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2345 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2346 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2347 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2348 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2349 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2350 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2351 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2352 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2353 radeon_encoder->rmx_type = RMX_FULL;
2354 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2355 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2356 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2357 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2358 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2360 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2361 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2363 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2365 case ENCODER_OBJECT_ID_SI170B:
2366 case ENCODER_OBJECT_ID_CH7303:
2367 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2368 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2369 case ENCODER_OBJECT_ID_TITFP513:
2370 case ENCODER_OBJECT_ID_VT1623:
2371 case ENCODER_OBJECT_ID_HDMI_SI1930:
2372 case ENCODER_OBJECT_ID_TRAVIS:
2373 case ENCODER_OBJECT_ID_NUTMEG:
2374 /* these are handled by the primary encoders */
2375 radeon_encoder->is_ext_encoder = true;
2376 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2377 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2378 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2379 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2381 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2382 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);