drivers/gpu/drm/nouveau/nv40_graph.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_grctx.h"
  31
  32 static int nv40_graph_register(struct drm_device *);
  33 static void nv40_graph_isr(struct drm_device *);
  34
  35 struct nouveau_channel *
  36 nv40_graph_channel(struct drm_device *dev)
  37 {
  38         struct drm_nouveau_private *dev_priv = dev->dev_private;
  39         uint32_t inst;
  40         int i;
  41
  42         inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
  43         if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
  44                 return NULL;
  45         inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;
  46
  47         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
  48                 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
  49
  50                 if (chan && chan->ramin_grctx &&
  51                     chan->ramin_grctx->pinst == inst)
  52                         return chan;
  53         }
  54
  55         return NULL;
  56 }
  57
  58 int
  59 nv40_graph_create_context(struct nouveau_channel *chan)
  60 {
  61         struct drm_device *dev = chan->dev;
  62         struct drm_nouveau_private *dev_priv = dev->dev_private;
  63         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
  64         struct nouveau_grctx ctx = {};
  65         int ret;
  66
  67         ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
  68                                  NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx);
  69         if (ret)
  70                 return ret;
  71
  72         /* Initialise default context values */
  73         ctx.dev = chan->dev;
  74         ctx.mode = NOUVEAU_GRCTX_VALS;
  75         ctx.data = chan->ramin_grctx;
  76         nv40_grctx_init(&ctx);
  77
  78         nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst);
  79         return 0;
  80 }
  81
  82 void
  83 nv40_graph_destroy_context(struct nouveau_channel *chan)
  84 {
  85         struct drm_device *dev = chan->dev;
  86         struct drm_nouveau_private *dev_priv = dev->dev_private;
  87         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
  88         unsigned long flags;
  89
  90         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
  91         pgraph->fifo_access(dev, false);
  92
  93         /* Unload the context if it's the currently active one */
  94         if (pgraph->channel(dev) == chan)
  95                 pgraph->unload_context(dev);
  96
  97         pgraph->fifo_access(dev, true);
  98         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
  99
 100         /* Free the context resources */
 101         nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
 102 }
 103
 104 static int
 105 nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
 106 {
 107         uint32_t old_cp, tv = 1000, tmp;
 108         int i;
 109
 110         old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
 111         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
 112
 113         tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
 114         tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
 115                       NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
 116         nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);
 117
 118         tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
 119         tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
 120         nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);
 121
 122         nouveau_wait_for_idle(dev);
 123
 124         for (i = 0; i < tv; i++) {
 125                 if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
 126                         break;
 127         }
 128
 129         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
 130
 131         if (i == tv) {
 132                 uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
 133                 NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
 134                 NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
 135                          ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
 136                          ucstat  & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
 137                 NV_ERROR(dev, "0x40030C = 0x%08x\n",
 138                          nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
 139                 return -EBUSY;
 140         }
 141
 142         return 0;
 143 }
 144
 145 /* Restore the context for a specific channel into PGRAPH */
 146 int
 147 nv40_graph_load_context(struct nouveau_channel *chan)
 148 {
 149         struct drm_device *dev = chan->dev;
 150         uint32_t inst;
 151         int ret;
 152
 153         if (!chan->ramin_grctx)
 154                 return -EINVAL;
 155         inst = chan->ramin_grctx->pinst >> 4;
 156
 157         ret = nv40_graph_transfer_context(dev, inst, 0);
 158         if (ret)
 159                 return ret;
 160
 161         /* 0x40032C, no idea of it's exact function.  Could simply be a
 162          * record of the currently active PGRAPH context.  It's currently
 163          * unknown as to what bit 24 does.  The nv ddx has it set, so we will
 164          * set it here too.
 165          */
 166         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
 167         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR,
 168                  (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) |
 169                   NV40_PGRAPH_CTXCTL_CUR_LOADED);
 170         /* 0x32E0 records the instance address of the active FIFO's PGRAPH
 171          * context.  If at any time this doesn't match 0x40032C, you will
 172          * recieve PGRAPH_INTR_CONTEXT_SWITCH
 173          */
 174         nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
 175         return 0;
 176 }
 177
 178 int
 179 nv40_graph_unload_context(struct drm_device *dev)
 180 {
 181         uint32_t inst;
 182         int ret;
 183
 184         inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
 185         if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
 186                 return 0;
 187         inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;
 188
 189         ret = nv40_graph_transfer_context(dev, inst, 1);
 190
 191         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
 192         return ret;
 193 }
 194
 195 void
 196 nv40_graph_set_tile_region(struct drm_device *dev, int i)
 197 {
 198         struct drm_nouveau_private *dev_priv = dev->dev_private;
 199         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
 200
 201         switch (dev_priv->chipset) {
 202         case 0x44:
 203         case 0x4a:
 204         case 0x4e:
 205                 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
 206                 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
 207                 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
 208                 break;
 209
 210         case 0x46:
 211         case 0x47:
 212         case 0x49:
 213         case 0x4b:
 214                 nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
 215                 nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
 216                 nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
 217                 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
 218                 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
 219                 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
 220                 break;
 221
 222         default:
 223                 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
 224                 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
 225                 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
 226                 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
 227                 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
 228                 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
 229                 break;
 230         }
 231 }
 232
 233 /*
 234  * G70          0x47
 235  * G71          0x49
 236  * NV45         0x48
 237  * G72[M]       0x46
 238  * G73          0x4b
 239  * C51_G7X      0x4c
 240  * C51          0x4e
 241  */
 242 int
 243 nv40_graph_init(struct drm_device *dev)
 244 {
 245         struct drm_nouveau_private *dev_priv =
 246                 (struct drm_nouveau_private *)dev->dev_private;
 247         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
 248         struct nouveau_grctx ctx = {};
 249         uint32_t vramsz, *cp;
 250         int ret, i, j;
 251
 252         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
 253                         ~NV_PMC_ENABLE_PGRAPH);
 254         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 255                          NV_PMC_ENABLE_PGRAPH);
 256
 257         cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
 258         if (!cp)
 259                 return -ENOMEM;
 260
 261         ctx.dev = dev;
 262         ctx.mode = NOUVEAU_GRCTX_PROG;
 263         ctx.data = cp;
 264         ctx.ctxprog_max = 256;
 265         nv40_grctx_init(&ctx);
 266         dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
 267
 268         nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
 269         for (i = 0; i < ctx.ctxprog_len; i++)
 270                 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
 271
 272         kfree(cp);
 273
 274         ret = nv40_graph_register(dev);
 275         if (ret)
 276                 return ret;
 277
 278         /* No context present currently */
 279         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
 280
 281         nouveau_irq_register(dev, 12, nv40_graph_isr);
 282         nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
 283         nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
 284
 285         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
 286         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
 287         nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
 288         nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
 289         nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
 290         nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
 291
 292         nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
 293         nv_wr32(dev, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 294
 295         j = nv_rd32(dev, 0x1540) & 0xff;
 296         if (j) {
 297                 for (i = 0; !(j & 1); j >>= 1, i++)
 298                         ;
 299                 nv_wr32(dev, 0x405000, i);
 300         }
 301
 302         if (dev_priv->chipset == 0x40) {
 303                 nv_wr32(dev, 0x4009b0, 0x83280fff);
 304                 nv_wr32(dev, 0x4009b4, 0x000000a0);
 305         } else {
 306                 nv_wr32(dev, 0x400820, 0x83280eff);
 307                 nv_wr32(dev, 0x400824, 0x000000a0);
 308         }
 309
 310         switch (dev_priv->chipset) {
 311         case 0x40:
 312         case 0x45:
 313                 nv_wr32(dev, 0x4009b8, 0x0078e366);
 314                 nv_wr32(dev, 0x4009bc, 0x0000014c);
 315                 break;
 316         case 0x41:
 317         case 0x42: /* pciid also 0x00Cx */
 318         /* case 0x0120: XXX (pciid) */
 319                 nv_wr32(dev, 0x400828, 0x007596ff);
 320                 nv_wr32(dev, 0x40082c, 0x00000108);
 321                 break;
 322         case 0x43:
 323                 nv_wr32(dev, 0x400828, 0x0072cb77);
 324                 nv_wr32(dev, 0x40082c, 0x00000108);
 325                 break;
 326         case 0x44:
 327         case 0x46: /* G72 */
 328         case 0x4a:
 329         case 0x4c: /* G7x-based C51 */
 330         case 0x4e:
 331                 nv_wr32(dev, 0x400860, 0);
 332                 nv_wr32(dev, 0x400864, 0);
 333                 break;
 334         case 0x47: /* G70 */
 335         case 0x49: /* G71 */
 336         case 0x4b: /* G73 */
 337                 nv_wr32(dev, 0x400828, 0x07830610);
 338                 nv_wr32(dev, 0x40082c, 0x0000016A);
 339                 break;
 340         default:
 341                 break;
 342         }
 343
 344         nv_wr32(dev, 0x400b38, 0x2ffff800);
 345         nv_wr32(dev, 0x400b3c, 0x00006000);
 346
 347         /* Tiling related stuff. */
 348         switch (dev_priv->chipset) {
 349         case 0x44:
 350         case 0x4a:
 351                 nv_wr32(dev, 0x400bc4, 0x1003d888);
 352                 nv_wr32(dev, 0x400bbc, 0xb7a7b500);
 353                 break;
 354         case 0x46:
 355                 nv_wr32(dev, 0x400bc4, 0x0000e024);
 356                 nv_wr32(dev, 0x400bbc, 0xb7a7b520);
 357                 break;
 358         case 0x4c:
 359         case 0x4e:
 360         case 0x67:
 361                 nv_wr32(dev, 0x400bc4, 0x1003d888);
 362                 nv_wr32(dev, 0x400bbc, 0xb7a7b540);
 363                 break;
 364         default:
 365                 break;
 366         }
 367
 368         /* Turn all the tiling regions off. */
 369         for (i = 0; i < pfb->num_tiles; i++)
 370                 nv40_graph_set_tile_region(dev, i);
 371
 372         /* begin RAM config */
 373         vramsz = pci_resource_len(dev->pdev, 0) - 1;
 374         switch (dev_priv->chipset) {
 375         case 0x40:
 376                 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
 377                 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
 378                 nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
 379                 nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
 380                 nv_wr32(dev, 0x400820, 0);
 381                 nv_wr32(dev, 0x400824, 0);
 382                 nv_wr32(dev, 0x400864, vramsz);
 383                 nv_wr32(dev, 0x400868, vramsz);
 384                 break;
 385         default:
 386                 switch (dev_priv->chipset) {
 387                 case 0x46:
 388                 case 0x47:
 389                 case 0x49:
 390                 case 0x4b:
 391                         nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
 392                         nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
 393                         break;
 394                 default:
 395                         nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
 396                         nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
 397                         break;
 398                 }
 399                 nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
 400                 nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
 401                 nv_wr32(dev, 0x400840, 0);
 402                 nv_wr32(dev, 0x400844, 0);
 403                 nv_wr32(dev, 0x4008A0, vramsz);
 404                 nv_wr32(dev, 0x4008A4, vramsz);
 405                 break;
 406         }
 407
 408         return 0;
 409 }
 410
 411 void nv40_graph_takedown(struct drm_device *dev)
 412 {
 413         nouveau_irq_unregister(dev, 12);
 414 }
 415
 416 static int
 417 nv40_graph_register(struct drm_device *dev)
 418 {
 419         struct drm_nouveau_private *dev_priv = dev->dev_private;
 420
 421         if (dev_priv->engine.graph.registered)
 422                 return 0;
 423
 424         NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
 425         NVOBJ_CLASS(dev, 0x0030, GR); /* null */
 426         NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
 427         NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
 428         NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
 429         NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
 430         NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
 431         NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
 432         NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
 433         NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
 434         NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
 435         NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
 436         NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
 437         NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
 438         NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
 439         NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */
 440
 441         /* curie */
 442         if (dev_priv->chipset >= 0x60 ||
 443             0x00005450 & (1 << (dev_priv->chipset & 0x0f)))
 444                 NVOBJ_CLASS(dev, 0x4497, GR);
 445         else
 446                 NVOBJ_CLASS(dev, 0x4097, GR);
 447
 448         /* nvsw */
 449         NVOBJ_CLASS(dev, 0x506e, SW);
 450         NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
 451
 452         dev_priv->engine.graph.registered = true;
 453         return 0;
 454 }
 455
 456 static int
 457 nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
 458 {
 459         struct drm_nouveau_private *dev_priv = dev->dev_private;
 460         struct nouveau_channel *chan;
 461         unsigned long flags;
 462         int i;
 463
 464         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 465         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 466                 chan = dev_priv->channels.ptr[i];
 467                 if (!chan || !chan->ramin_grctx)
 468                         continue;
 469
 470                 if (inst == chan->ramin_grctx->pinst)
 471                         break;
 472         }
 473         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 474         return i;
 475 }
 476
 477 static void
 478 nv40_graph_isr(struct drm_device *dev)
 479 {
 480         u32 stat;
 481
 482         while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
 483                 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
 484                 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
 485                 u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
 486                 u32 chid = nv40_graph_isr_chid(dev, inst);
 487                 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
 488                 u32 subc = (addr & 0x00070000) >> 16;
 489                 u32 mthd = (addr & 0x00001ffc);
 490                 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
 491                 u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
 492                 u32 show = stat;
 493
 494                 if (stat & NV_PGRAPH_INTR_ERROR) {
 495                         if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
 496                                 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
 497                                         show &= ~NV_PGRAPH_INTR_ERROR;
 498                         } else
 499                         if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
 500                                 nv_mask(dev, 0x402000, 0, 0);
 501                         }
 502                 }
 503
 504                 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
 505                 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
 506
 507                 if (show && nouveau_ratelimit()) {
 508                         NV_INFO(dev, "PGRAPH -");
 509                         nouveau_bitfield_print(nv10_graph_intr, show);
 510                         printk(" nsource:");
 511                         nouveau_bitfield_print(nv04_graph_nsource, nsource);
 512                         printk(" nstatus:");
 513                         nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
 514                         printk("\n");
 515                         NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
 516                                      "class 0x%04x mthd 0x%04x data 0x%08x\n",
 517                                 chid, inst, subc, class, mthd, data);
 518                 }
 519         }
 520 }