drivers/gpu/drm/i915/intel_i2c.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29 #include <linux/i2c.h>
  30 #include <linux/i2c-algo-bit.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36
  37 /* Intel GPIO access functions */
  38
  39 #define I2C_RISEFALL_TIME 20
  40
  41 static inline struct intel_gmbus *
  42 to_intel_gmbus(struct i2c_adapter *i2c)
  43 {
  44         return container_of(i2c, struct intel_gmbus, adapter);
  45 }
  46
  47 struct intel_gpio {
  48         struct i2c_adapter adapter;
  49         struct i2c_algo_bit_data algo;
  50         struct drm_i915_private *dev_priv;
  51         u32 reg;
  52 };
  53
  54 void
  55 intel_i2c_reset(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58         if (HAS_PCH_SPLIT(dev))
  59                 I915_WRITE(PCH_GMBUS0, 0);
  60         else
  61                 I915_WRITE(GMBUS0, 0);
  62 }
  63
  64 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
  65 {
  66         u32 val;
  67
  68         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  69         if (!IS_PINEVIEW(dev_priv->dev))
  70                 return;
  71
  72         val = I915_READ(DSPCLK_GATE_D);
  73         if (enable)
  74                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  75         else
  76                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  77         I915_WRITE(DSPCLK_GATE_D, val);
  78 }
  79
  80 static u32 get_reserved(struct intel_gpio *gpio)
  81 {
  82         struct drm_i915_private *dev_priv = gpio->dev_priv;
  83         struct drm_device *dev = dev_priv->dev;
  84         u32 reserved = 0;
  85
  86         /* On most chips, these bits must be preserved in software. */
  87         if (!IS_I830(dev) && !IS_845G(dev))
  88                 reserved = I915_READ(gpio->reg) & (GPIO_DATA_PULLUP_DISABLE |
  89                                                    GPIO_CLOCK_PULLUP_DISABLE);
  90
  91         return reserved;
  92 }
  93
  94 static int get_clock(void *data)
  95 {
  96         struct intel_gpio *gpio = data;
  97         struct drm_i915_private *dev_priv = gpio->dev_priv;
  98         u32 reserved = get_reserved(gpio);
  99         I915_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
 100         I915_WRITE(gpio->reg, reserved);
 101         return (I915_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
 102 }
 103
 104 static int get_data(void *data)
 105 {
 106         struct intel_gpio *gpio = data;
 107         struct drm_i915_private *dev_priv = gpio->dev_priv;
 108         u32 reserved = get_reserved(gpio);
 109         I915_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
 110         I915_WRITE(gpio->reg, reserved);
 111         return (I915_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
 112 }
 113
 114 static void set_clock(void *data, int state_high)
 115 {
 116         struct intel_gpio *gpio = data;
 117         struct drm_i915_private *dev_priv = gpio->dev_priv;
 118         u32 reserved = get_reserved(gpio);
 119         u32 clock_bits;
 120
 121         if (state_high)
 122                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 123         else
 124                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 125                         GPIO_CLOCK_VAL_MASK;
 126
 127         I915_WRITE(gpio->reg, reserved | clock_bits);
 128         POSTING_READ(gpio->reg);
 129 }
 130
 131 static void set_data(void *data, int state_high)
 132 {
 133         struct intel_gpio *gpio = data;
 134         struct drm_i915_private *dev_priv = gpio->dev_priv;
 135         u32 reserved = get_reserved(gpio);
 136         u32 data_bits;
 137
 138         if (state_high)
 139                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 140         else
 141                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 142                         GPIO_DATA_VAL_MASK;
 143
 144         I915_WRITE(gpio->reg, reserved | data_bits);
 145         POSTING_READ(gpio->reg);
 146 }
 147
 148 static struct i2c_adapter *
 149 intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
 150 {
 151         static const int map_pin_to_reg[] = {
 152                 0,
 153                 GPIOB,
 154                 GPIOA,
 155                 GPIOC,
 156                 GPIOD,
 157                 GPIOE,
 158                 0,
 159                 GPIOF,
 160         };
 161         struct intel_gpio *gpio;
 162
 163         if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
 164                 return NULL;
 165
 166         gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
 167         if (gpio == NULL)
 168                 return NULL;
 169
 170         gpio->reg = map_pin_to_reg[pin];
 171         if (HAS_PCH_SPLIT(dev_priv->dev))
 172                 gpio->reg += PCH_GPIOA - GPIOA;
 173         gpio->dev_priv = dev_priv;
 174
 175         snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
 176                  "i915 GPIO%c", "?BACDE?F"[pin]);
 177         gpio->adapter.owner = THIS_MODULE;
 178         gpio->adapter.algo_data = &gpio->algo;
 179         gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
 180         gpio->algo.setsda = set_data;
 181         gpio->algo.setscl = set_clock;
 182         gpio->algo.getsda = get_data;
 183         gpio->algo.getscl = get_clock;
 184         gpio->algo.udelay = I2C_RISEFALL_TIME;
 185         gpio->algo.timeout = usecs_to_jiffies(2200);
 186         gpio->algo.data = gpio;
 187
 188         if (i2c_bit_add_bus(&gpio->adapter))
 189                 goto out_free;
 190
 191         return &gpio->adapter;
 192
 193 out_free:
 194         kfree(gpio);
 195         return NULL;
 196 }
 197
 198 static int
 199 intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv,
 200                      struct i2c_adapter *adapter,
 201                      struct i2c_msg *msgs,
 202                      int num)
 203 {
 204         struct intel_gpio *gpio = container_of(adapter,
 205                                                struct intel_gpio,
 206                                                adapter);
 207         int ret;
 208
 209         intel_i2c_reset(dev_priv->dev);
 210
 211         intel_i2c_quirk_set(dev_priv, true);
 212         set_data(gpio, 1);
 213         set_clock(gpio, 1);
 214         udelay(I2C_RISEFALL_TIME);
 215
 216         ret = adapter->algo->master_xfer(adapter, msgs, num);
 217
 218         set_data(gpio, 1);
 219         set_clock(gpio, 1);
 220         intel_i2c_quirk_set(dev_priv, false);
 221
 222         return ret;
 223 }
 224
 225 static int
 226 gmbus_xfer(struct i2c_adapter *adapter,
 227            struct i2c_msg *msgs,
 228            int num)
 229 {
 230         struct intel_gmbus *bus = container_of(adapter,
 231                                                struct intel_gmbus,
 232                                                adapter);
 233         struct drm_i915_private *dev_priv = adapter->algo_data;
 234         int i, reg_offset;
 235
 236         if (bus->force_bit)
 237                 return intel_i2c_quirk_xfer(dev_priv,
 238                                             bus->force_bit, msgs, num);
 239
 240         reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
 241
 242         I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
 243
 244         for (i = 0; i < num; i++) {
 245                 u16 len = msgs[i].len;
 246                 u8 *buf = msgs[i].buf;
 247
 248                 if (msgs[i].flags & I2C_M_RD) {
 249                         I915_WRITE(GMBUS1 + reg_offset,
 250                                    GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
 251                                    (len << GMBUS_BYTE_COUNT_SHIFT) |
 252                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
 253                                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 254                         POSTING_READ(GMBUS2+reg_offset);
 255                         do {
 256                                 u32 val, loop = 0;
 257
 258                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
 259                                         goto timeout;
 260                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 261                                         return 0;
 262
 263                                 val = I915_READ(GMBUS3 + reg_offset);
 264                                 do {
 265                                         *buf++ = val & 0xff;
 266                                         val >>= 8;
 267                                 } while (--len && ++loop < 4);
 268                         } while (len);
 269                 } else {
 270                         u32 val, loop;
 271
 272                         val = loop = 0;
 273                         do {
 274                                 val |= *buf++ << (8 * loop);
 275                         } while (--len && ++loop < 4);
 276
 277                         I915_WRITE(GMBUS3 + reg_offset, val);
 278                         I915_WRITE(GMBUS1 + reg_offset,
 279                                    (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
 280                                    (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
 281                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
 282                                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 283                         POSTING_READ(GMBUS2+reg_offset);
 284
 285                         while (len) {
 286                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
 287                                         goto timeout;
 288                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 289                                         return 0;
 290
 291                                 val = loop = 0;
 292                                 do {
 293                                         val |= *buf++ << (8 * loop);
 294                                 } while (--len && ++loop < 4);
 295
 296                                 I915_WRITE(GMBUS3 + reg_offset, val);
 297                                 POSTING_READ(GMBUS2+reg_offset);
 298                         }
 299                 }
 300
 301                 if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
 302                         goto timeout;
 303                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 304                         return 0;
 305         }
 306
 307         return num;
 308
 309 timeout:
 310         DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
 311                  bus->reg0 & 0xff, bus->adapter.name);
 312         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
 313         bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
 314         if (!bus->force_bit)
 315                 return -ENOMEM;
 316
 317         return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
 318 }
 319
 320 static u32 gmbus_func(struct i2c_adapter *adapter)
 321 {
 322         struct intel_gmbus *bus = container_of(adapter,
 323                                                struct intel_gmbus,
 324                                                adapter);
 325
 326         if (bus->force_bit)
 327                 bus->force_bit->algo->functionality(bus->force_bit);
 328
 329         return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 330                 /* I2C_FUNC_10BIT_ADDR | */
 331                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 332                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 333 }
 334
 335 static const struct i2c_algorithm gmbus_algorithm = {
 336         .master_xfer    = gmbus_xfer,
 337         .functionality  = gmbus_func
 338 };
 339
 340 /**
 341  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 342  * @dev: DRM device
 343  */
 344 int intel_setup_gmbus(struct drm_device *dev)
 345 {
 346         static const char *names[GMBUS_NUM_PORTS] = {
 347                 "disabled",
 348                 "ssc",
 349                 "vga",
 350                 "panel",
 351                 "dpc",
 352                 "dpb",
 353                 "reserved",
 354                 "dpd",
 355         };
 356         struct drm_i915_private *dev_priv = dev->dev_private;
 357         int ret, i;
 358
 359         dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
 360                                   GFP_KERNEL);
 361         if (dev_priv->gmbus == NULL)
 362                 return -ENOMEM;
 363
 364         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 365                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 366
 367                 bus->adapter.owner = THIS_MODULE;
 368                 bus->adapter.class = I2C_CLASS_DDC;
 369                 snprintf(bus->adapter.name,
 370                          sizeof(bus->adapter.name),
 371                          "i915 gmbus %s",
 372                          names[i]);
 373
 374                 bus->adapter.dev.parent = &dev->pdev->dev;
 375                 bus->adapter.algo_data  = dev_priv;
 376
 377                 bus->adapter.algo = &gmbus_algorithm;
 378                 ret = i2c_add_adapter(&bus->adapter);
 379                 if (ret)
 380                         goto err;
 381
 382                 /* By default use a conservative clock rate */
 383                 bus->reg0 = i | GMBUS_RATE_100KHZ;
 384
 385                 /* XXX force bit banging until GMBUS is fully debugged */
 386                 bus->force_bit = intel_gpio_create(dev_priv, i);
 387         }
 388
 389         intel_i2c_reset(dev_priv->dev);
 390
 391         return 0;
 392
 393 err:
 394         while (--i) {
 395                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 396                 i2c_del_adapter(&bus->adapter);
 397         }
 398         kfree(dev_priv->gmbus);
 399         dev_priv->gmbus = NULL;
 400         return ret;
 401 }
 402
 403 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 404 {
 405         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 406
 407         /* speed:
 408          * 0x0 = 100 KHz
 409          * 0x1 = 50 KHz
 410          * 0x2 = 400 KHz
 411          * 0x3 = 1000 Khz
 412          */
 413         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
 414 }
 415
 416 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 417 {
 418         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 419
 420         if (force_bit) {
 421                 if (bus->force_bit == NULL) {
 422                         struct drm_i915_private *dev_priv = adapter->algo_data;
 423                         bus->force_bit = intel_gpio_create(dev_priv,
 424                                                            bus->reg0 & 0xff);
 425                 }
 426         } else {
 427                 if (bus->force_bit) {
 428                         i2c_del_adapter(bus->force_bit);
 429                         kfree(bus->force_bit);
 430                         bus->force_bit = NULL;
 431                 }
 432         }
 433 }
 434
 435 void intel_teardown_gmbus(struct drm_device *dev)
 436 {
 437         struct drm_i915_private *dev_priv = dev->dev_private;
 438         int i;
 439
 440         if (dev_priv->gmbus == NULL)
 441                 return;
 442
 443         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 444                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 445                 if (bus->force_bit) {
 446                         i2c_del_adapter(bus->force_bit);
 447                         kfree(bus->force_bit);
 448                 }
 449                 i2c_del_adapter(&bus->adapter);
 450         }
 451
 452         kfree(dev_priv->gmbus);
 453         dev_priv->gmbus = NULL;
 454 }