drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_update_watermarks(struct drm_device *dev);
  48 static void intel_increase_pllclock(struct drm_crtc *crtc);
  49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50
  51 typedef struct {
  52         /* given values */
  53         int n;
  54         int m1, m2;
  55         int p1, p2;
  56         /* derived values */
  57         int     dot;
  58         int     vco;
  59         int     m;
  60         int     p;
  61 } intel_clock_t;
  62
  63 typedef struct {
  64         int     min, max;
  65 } intel_range_t;
  66
  67 typedef struct {
  68         int     dot_limit;
  69         int     p2_slow, p2_fast;
  70 } intel_p2_t;
  71
  72 #define INTEL_P2_NUM                  2
  73 typedef struct intel_limit intel_limit_t;
  74 struct intel_limit {
  75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  76         intel_p2_t          p2;
  77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  78                         int, int, intel_clock_t *);
  79 };
  80
  81 /* FDI */
  82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  83
  84 static bool
  85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86                     int target, int refclk, intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *best_clock);
  90
  91 static bool
  92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  93                       int target, int refclk, intel_clock_t *best_clock);
  94 static bool
  95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  96                            int target, int refclk, intel_clock_t *best_clock);
  97
  98 static inline u32 /* units of 100MHz */
  99 intel_fdi_link_freq(struct drm_device *dev)
 100 {
 101         if (IS_GEN5(dev)) {
 102                 struct drm_i915_private *dev_priv = dev->dev_private;
 103                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 104         } else
 105                 return 27;
 106 }
 107
 108 static const intel_limit_t intel_limits_i8xx_dvo = {
 109         .dot = { .min = 25000, .max = 350000 },
 110         .vco = { .min = 930000, .max = 1400000 },
 111         .n = { .min = 3, .max = 16 },
 112         .m = { .min = 96, .max = 140 },
 113         .m1 = { .min = 18, .max = 26 },
 114         .m2 = { .min = 6, .max = 16 },
 115         .p = { .min = 4, .max = 128 },
 116         .p1 = { .min = 2, .max = 33 },
 117         .p2 = { .dot_limit = 165000,
 118                 .p2_slow = 4, .p2_fast = 2 },
 119         .find_pll = intel_find_best_PLL,
 120 };
 121
 122 static const intel_limit_t intel_limits_i8xx_lvds = {
 123         .dot = { .min = 25000, .max = 350000 },
 124         .vco = { .min = 930000, .max = 1400000 },
 125         .n = { .min = 3, .max = 16 },
 126         .m = { .min = 96, .max = 140 },
 127         .m1 = { .min = 18, .max = 26 },
 128         .m2 = { .min = 6, .max = 16 },
 129         .p = { .min = 4, .max = 128 },
 130         .p1 = { .min = 1, .max = 6 },
 131         .p2 = { .dot_limit = 165000,
 132                 .p2_slow = 14, .p2_fast = 7 },
 133         .find_pll = intel_find_best_PLL,
 134 };
 135
 136 static const intel_limit_t intel_limits_i9xx_sdvo = {
 137         .dot = { .min = 20000, .max = 400000 },
 138         .vco = { .min = 1400000, .max = 2800000 },
 139         .n = { .min = 1, .max = 6 },
 140         .m = { .min = 70, .max = 120 },
 141         .m1 = { .min = 10, .max = 22 },
 142         .m2 = { .min = 5, .max = 9 },
 143         .p = { .min = 5, .max = 80 },
 144         .p1 = { .min = 1, .max = 8 },
 145         .p2 = { .dot_limit = 200000,
 146                 .p2_slow = 10, .p2_fast = 5 },
 147         .find_pll = intel_find_best_PLL,
 148 };
 149
 150 static const intel_limit_t intel_limits_i9xx_lvds = {
 151         .dot = { .min = 20000, .max = 400000 },
 152         .vco = { .min = 1400000, .max = 2800000 },
 153         .n = { .min = 1, .max = 6 },
 154         .m = { .min = 70, .max = 120 },
 155         .m1 = { .min = 10, .max = 22 },
 156         .m2 = { .min = 5, .max = 9 },
 157         .p = { .min = 7, .max = 98 },
 158         .p1 = { .min = 1, .max = 8 },
 159         .p2 = { .dot_limit = 112000,
 160                 .p2_slow = 14, .p2_fast = 7 },
 161         .find_pll = intel_find_best_PLL,
 162 };
 163
 164
 165 static const intel_limit_t intel_limits_g4x_sdvo = {
 166         .dot = { .min = 25000, .max = 270000 },
 167         .vco = { .min = 1750000, .max = 3500000},
 168         .n = { .min = 1, .max = 4 },
 169         .m = { .min = 104, .max = 138 },
 170         .m1 = { .min = 17, .max = 23 },
 171         .m2 = { .min = 5, .max = 11 },
 172         .p = { .min = 10, .max = 30 },
 173         .p1 = { .min = 1, .max = 3},
 174         .p2 = { .dot_limit = 270000,
 175                 .p2_slow = 10,
 176                 .p2_fast = 10
 177         },
 178         .find_pll = intel_g4x_find_best_PLL,
 179 };
 180
 181 static const intel_limit_t intel_limits_g4x_hdmi = {
 182         .dot = { .min = 22000, .max = 400000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 16, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 5, .max = 80 },
 189         .p1 = { .min = 1, .max = 8},
 190         .p2 = { .dot_limit = 165000,
 191                 .p2_slow = 10, .p2_fast = 5 },
 192         .find_pll = intel_g4x_find_best_PLL,
 193 };
 194
 195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 196         .dot = { .min = 20000, .max = 115000 },
 197         .vco = { .min = 1750000, .max = 3500000 },
 198         .n = { .min = 1, .max = 3 },
 199         .m = { .min = 104, .max = 138 },
 200         .m1 = { .min = 17, .max = 23 },
 201         .m2 = { .min = 5, .max = 11 },
 202         .p = { .min = 28, .max = 112 },
 203         .p1 = { .min = 2, .max = 8 },
 204         .p2 = { .dot_limit = 0,
 205                 .p2_slow = 14, .p2_fast = 14
 206         },
 207         .find_pll = intel_g4x_find_best_PLL,
 208 };
 209
 210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 211         .dot = { .min = 80000, .max = 224000 },
 212         .vco = { .min = 1750000, .max = 3500000 },
 213         .n = { .min = 1, .max = 3 },
 214         .m = { .min = 104, .max = 138 },
 215         .m1 = { .min = 17, .max = 23 },
 216         .m2 = { .min = 5, .max = 11 },
 217         .p = { .min = 14, .max = 42 },
 218         .p1 = { .min = 2, .max = 6 },
 219         .p2 = { .dot_limit = 0,
 220                 .p2_slow = 7, .p2_fast = 7
 221         },
 222         .find_pll = intel_g4x_find_best_PLL,
 223 };
 224
 225 static const intel_limit_t intel_limits_g4x_display_port = {
 226         .dot = { .min = 161670, .max = 227000 },
 227         .vco = { .min = 1750000, .max = 3500000},
 228         .n = { .min = 1, .max = 2 },
 229         .m = { .min = 97, .max = 108 },
 230         .m1 = { .min = 0x10, .max = 0x12 },
 231         .m2 = { .min = 0x05, .max = 0x06 },
 232         .p = { .min = 10, .max = 20 },
 233         .p1 = { .min = 1, .max = 2},
 234         .p2 = { .dot_limit = 0,
 235                 .p2_slow = 10, .p2_fast = 10 },
 236         .find_pll = intel_find_pll_g4x_dp,
 237 };
 238
 239 static const intel_limit_t intel_limits_pineview_sdvo = {
 240         .dot = { .min = 20000, .max = 400000},
 241         .vco = { .min = 1700000, .max = 3500000 },
 242         /* Pineview's Ncounter is a ring counter */
 243         .n = { .min = 3, .max = 6 },
 244         .m = { .min = 2, .max = 256 },
 245         /* Pineview only has one combined m divider, which we treat as m2. */
 246         .m1 = { .min = 0, .max = 0 },
 247         .m2 = { .min = 0, .max = 254 },
 248         .p = { .min = 5, .max = 80 },
 249         .p1 = { .min = 1, .max = 8 },
 250         .p2 = { .dot_limit = 200000,
 251                 .p2_slow = 10, .p2_fast = 5 },
 252         .find_pll = intel_find_best_PLL,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_lvds = {
 256         .dot = { .min = 20000, .max = 400000 },
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         .n = { .min = 3, .max = 6 },
 259         .m = { .min = 2, .max = 256 },
 260         .m1 = { .min = 0, .max = 0 },
 261         .m2 = { .min = 0, .max = 254 },
 262         .p = { .min = 7, .max = 112 },
 263         .p1 = { .min = 1, .max = 8 },
 264         .p2 = { .dot_limit = 112000,
 265                 .p2_slow = 14, .p2_fast = 14 },
 266         .find_pll = intel_find_best_PLL,
 267 };
 268
 269 /* Ironlake / Sandybridge
 270  *
 271  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 272  * the range value for them is (actual_value - 2).
 273  */
 274 static const intel_limit_t intel_limits_ironlake_dac = {
 275         .dot = { .min = 25000, .max = 350000 },
 276         .vco = { .min = 1760000, .max = 3510000 },
 277         .n = { .min = 1, .max = 5 },
 278         .m = { .min = 79, .max = 127 },
 279         .m1 = { .min = 12, .max = 22 },
 280         .m2 = { .min = 5, .max = 9 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 225000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285         .find_pll = intel_g4x_find_best_PLL,
 286 };
 287
 288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 289         .dot = { .min = 25000, .max = 350000 },
 290         .vco = { .min = 1760000, .max = 3510000 },
 291         .n = { .min = 1, .max = 3 },
 292         .m = { .min = 79, .max = 118 },
 293         .m1 = { .min = 12, .max = 22 },
 294         .m2 = { .min = 5, .max = 9 },
 295         .p = { .min = 28, .max = 112 },
 296         .p1 = { .min = 2, .max = 8 },
 297         .p2 = { .dot_limit = 225000,
 298                 .p2_slow = 14, .p2_fast = 14 },
 299         .find_pll = intel_g4x_find_best_PLL,
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 127 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 56 },
 310         .p1 = { .min = 2, .max = 8 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313         .find_pll = intel_g4x_find_best_PLL,
 314 };
 315
 316 /* LVDS 100mhz refclk limits. */
 317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 318         .dot = { .min = 25000, .max = 350000 },
 319         .vco = { .min = 1760000, .max = 3510000 },
 320         .n = { .min = 1, .max = 2 },
 321         .m = { .min = 79, .max = 126 },
 322         .m1 = { .min = 12, .max = 22 },
 323         .m2 = { .min = 5, .max = 9 },
 324         .p = { .min = 28, .max = 112 },
 325         .p1 = { .min = 2, .max = 8 },
 326         .p2 = { .dot_limit = 225000,
 327                 .p2_slow = 14, .p2_fast = 14 },
 328         .find_pll = intel_g4x_find_best_PLL,
 329 };
 330
 331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 332         .dot = { .min = 25000, .max = 350000 },
 333         .vco = { .min = 1760000, .max = 3510000 },
 334         .n = { .min = 1, .max = 3 },
 335         .m = { .min = 79, .max = 126 },
 336         .m1 = { .min = 12, .max = 22 },
 337         .m2 = { .min = 5, .max = 9 },
 338         .p = { .min = 14, .max = 42 },
 339         .p1 = { .min = 2, .max = 6 },
 340         .p2 = { .dot_limit = 225000,
 341                 .p2_slow = 7, .p2_fast = 7 },
 342         .find_pll = intel_g4x_find_best_PLL,
 343 };
 344
 345 static const intel_limit_t intel_limits_ironlake_display_port = {
 346         .dot = { .min = 25000, .max = 350000 },
 347         .vco = { .min = 1760000, .max = 3510000},
 348         .n = { .min = 1, .max = 2 },
 349         .m = { .min = 81, .max = 90 },
 350         .m1 = { .min = 12, .max = 22 },
 351         .m2 = { .min = 5, .max = 9 },
 352         .p = { .min = 10, .max = 20 },
 353         .p1 = { .min = 1, .max = 2},
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 10, .p2_fast = 10 },
 356         .find_pll = intel_find_pll_ironlake_dp,
 357 };
 358
 359 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 360                               unsigned int reg)
 361 {
 362         unsigned int val;
 363
 364         if (dev_priv->lvds_val)
 365                 val = dev_priv->lvds_val;
 366         else {
 367                 /* BIOS should set the proper LVDS register value at boot, but
 368                  * in reality, it doesn't set the value when the lid is closed;
 369                  * we need to check "the value to be set" in VBT when LVDS
 370                  * register is uninitialized.
 371                  */
 372                 val = I915_READ(reg);
 373                 if (!(val & ~LVDS_DETECTED))
 374                         val = dev_priv->bios_lvds_val;
 375                 dev_priv->lvds_val = val;
 376         }
 377         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 378 }
 379
 380 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 381                                                 int refclk)
 382 {
 383         struct drm_device *dev = crtc->dev;
 384         struct drm_i915_private *dev_priv = dev->dev_private;
 385         const intel_limit_t *limit;
 386
 387         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 388                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 389                         /* LVDS dual channel */
 390                         if (refclk == 100000)
 391                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 392                         else
 393                                 limit = &intel_limits_ironlake_dual_lvds;
 394                 } else {
 395                         if (refclk == 100000)
 396                                 limit = &intel_limits_ironlake_single_lvds_100m;
 397                         else
 398                                 limit = &intel_limits_ironlake_single_lvds;
 399                 }
 400         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 401                         HAS_eDP)
 402                 limit = &intel_limits_ironlake_display_port;
 403         else
 404                 limit = &intel_limits_ironlake_dac;
 405
 406         return limit;
 407 }
 408
 409 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 410 {
 411         struct drm_device *dev = crtc->dev;
 412         struct drm_i915_private *dev_priv = dev->dev_private;
 413         const intel_limit_t *limit;
 414
 415         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 416                 if (is_dual_link_lvds(dev_priv, LVDS))
 417                         /* LVDS with dual channel */
 418                         limit = &intel_limits_g4x_dual_channel_lvds;
 419                 else
 420                         /* LVDS with dual channel */
 421                         limit = &intel_limits_g4x_single_channel_lvds;
 422         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 423                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 424                 limit = &intel_limits_g4x_hdmi;
 425         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 426                 limit = &intel_limits_g4x_sdvo;
 427         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 428                 limit = &intel_limits_g4x_display_port;
 429         } else /* The option is for other outputs */
 430                 limit = &intel_limits_i9xx_sdvo;
 431
 432         return limit;
 433 }
 434
 435 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 436 {
 437         struct drm_device *dev = crtc->dev;
 438         const intel_limit_t *limit;
 439
 440         if (HAS_PCH_SPLIT(dev))
 441                 limit = intel_ironlake_limit(crtc, refclk);
 442         else if (IS_G4X(dev)) {
 443                 limit = intel_g4x_limit(crtc);
 444         } else if (IS_PINEVIEW(dev)) {
 445                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 446                         limit = &intel_limits_pineview_lvds;
 447                 else
 448                         limit = &intel_limits_pineview_sdvo;
 449         } else if (!IS_GEN2(dev)) {
 450                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 451                         limit = &intel_limits_i9xx_lvds;
 452                 else
 453                         limit = &intel_limits_i9xx_sdvo;
 454         } else {
 455                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 456                         limit = &intel_limits_i8xx_lvds;
 457                 else
 458                         limit = &intel_limits_i8xx_dvo;
 459         }
 460         return limit;
 461 }
 462
 463 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 464 static void pineview_clock(int refclk, intel_clock_t *clock)
 465 {
 466         clock->m = clock->m2 + 2;
 467         clock->p = clock->p1 * clock->p2;
 468         clock->vco = refclk * clock->m / clock->n;
 469         clock->dot = clock->vco / clock->p;
 470 }
 471
 472 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 473 {
 474         if (IS_PINEVIEW(dev)) {
 475                 pineview_clock(refclk, clock);
 476                 return;
 477         }
 478         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 479         clock->p = clock->p1 * clock->p2;
 480         clock->vco = refclk * clock->m / (clock->n + 2);
 481         clock->dot = clock->vco / clock->p;
 482 }
 483
 484 /**
 485  * Returns whether any output on the specified pipe is of the specified type
 486  */
 487 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 488 {
 489         struct drm_device *dev = crtc->dev;
 490         struct drm_mode_config *mode_config = &dev->mode_config;
 491         struct intel_encoder *encoder;
 492
 493         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 494                 if (encoder->base.crtc == crtc && encoder->type == type)
 495                         return true;
 496
 497         return false;
 498 }
 499
 500 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 501 /**
 502  * Returns whether the given set of divisors are valid for a given refclk with
 503  * the given connectors.
 504  */
 505
 506 static bool intel_PLL_is_valid(struct drm_device *dev,
 507                                const intel_limit_t *limit,
 508                                const intel_clock_t *clock)
 509 {
 510         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 511                 INTELPllInvalid("p1 out of range\n");
 512         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 513                 INTELPllInvalid("p out of range\n");
 514         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 515                 INTELPllInvalid("m2 out of range\n");
 516         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 517                 INTELPllInvalid("m1 out of range\n");
 518         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 519                 INTELPllInvalid("m1 <= m2\n");
 520         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 521                 INTELPllInvalid("m out of range\n");
 522         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 523                 INTELPllInvalid("n out of range\n");
 524         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 525                 INTELPllInvalid("vco out of range\n");
 526         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 527          * connector, etc., rather than just a single range.
 528          */
 529         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 530                 INTELPllInvalid("dot out of range\n");
 531
 532         return true;
 533 }
 534
 535 static bool
 536 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 537                     int target, int refclk, intel_clock_t *best_clock)
 538
 539 {
 540         struct drm_device *dev = crtc->dev;
 541         struct drm_i915_private *dev_priv = dev->dev_private;
 542         intel_clock_t clock;
 543         int err = target;
 544
 545         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 546             (I915_READ(LVDS)) != 0) {
 547                 /*
 548                  * For LVDS, if the panel is on, just rely on its current
 549                  * settings for dual-channel.  We haven't figured out how to
 550                  * reliably set up different single/dual channel state, if we
 551                  * even can.
 552                  */
 553                 if (is_dual_link_lvds(dev_priv, LVDS))
 554                         clock.p2 = limit->p2.p2_fast;
 555                 else
 556                         clock.p2 = limit->p2.p2_slow;
 557         } else {
 558                 if (target < limit->p2.dot_limit)
 559                         clock.p2 = limit->p2.p2_slow;
 560                 else
 561                         clock.p2 = limit->p2.p2_fast;
 562         }
 563
 564         memset(best_clock, 0, sizeof(*best_clock));
 565
 566         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 567              clock.m1++) {
 568                 for (clock.m2 = limit->m2.min;
 569                      clock.m2 <= limit->m2.max; clock.m2++) {
 570                         /* m1 is always 0 in Pineview */
 571                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 572                                 break;
 573                         for (clock.n = limit->n.min;
 574                              clock.n <= limit->n.max; clock.n++) {
 575                                 for (clock.p1 = limit->p1.min;
 576                                         clock.p1 <= limit->p1.max; clock.p1++) {
 577                                         int this_err;
 578
 579                                         intel_clock(dev, refclk, &clock);
 580                                         if (!intel_PLL_is_valid(dev, limit,
 581                                                                 &clock))
 582                                                 continue;
 583
 584                                         this_err = abs(clock.dot - target);
 585                                         if (this_err < err) {
 586                                                 *best_clock = clock;
 587                                                 err = this_err;
 588                                         }
 589                                 }
 590                         }
 591                 }
 592         }
 593
 594         return (err != target);
 595 }
 596
 597 static bool
 598 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 599                         int target, int refclk, intel_clock_t *best_clock)
 600 {
 601         struct drm_device *dev = crtc->dev;
 602         struct drm_i915_private *dev_priv = dev->dev_private;
 603         intel_clock_t clock;
 604         int max_n;
 605         bool found;
 606         /* approximately equals target * 0.00585 */
 607         int err_most = (target >> 8) + (target >> 9);
 608         found = false;
 609
 610         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 611                 int lvds_reg;
 612
 613                 if (HAS_PCH_SPLIT(dev))
 614                         lvds_reg = PCH_LVDS;
 615                 else
 616                         lvds_reg = LVDS;
 617                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 618                     LVDS_CLKB_POWER_UP)
 619                         clock.p2 = limit->p2.p2_fast;
 620                 else
 621                         clock.p2 = limit->p2.p2_slow;
 622         } else {
 623                 if (target < limit->p2.dot_limit)
 624                         clock.p2 = limit->p2.p2_slow;
 625                 else
 626                         clock.p2 = limit->p2.p2_fast;
 627         }
 628
 629         memset(best_clock, 0, sizeof(*best_clock));
 630         max_n = limit->n.max;
 631         /* based on hardware requirement, prefer smaller n to precision */
 632         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 633                 /* based on hardware requirement, prefere larger m1,m2 */
 634                 for (clock.m1 = limit->m1.max;
 635                      clock.m1 >= limit->m1.min; clock.m1--) {
 636                         for (clock.m2 = limit->m2.max;
 637                              clock.m2 >= limit->m2.min; clock.m2--) {
 638                                 for (clock.p1 = limit->p1.max;
 639                                      clock.p1 >= limit->p1.min; clock.p1--) {
 640                                         int this_err;
 641
 642                                         intel_clock(dev, refclk, &clock);
 643                                         if (!intel_PLL_is_valid(dev, limit,
 644                                                                 &clock))
 645                                                 continue;
 646
 647                                         this_err = abs(clock.dot - target);
 648                                         if (this_err < err_most) {
 649                                                 *best_clock = clock;
 650                                                 err_most = this_err;
 651                                                 max_n = clock.n;
 652                                                 found = true;
 653                                         }
 654                                 }
 655                         }
 656                 }
 657         }
 658         return found;
 659 }
 660
 661 static bool
 662 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 663                            int target, int refclk, intel_clock_t *best_clock)
 664 {
 665         struct drm_device *dev = crtc->dev;
 666         intel_clock_t clock;
 667
 668         if (target < 200000) {
 669                 clock.n = 1;
 670                 clock.p1 = 2;
 671                 clock.p2 = 10;
 672                 clock.m1 = 12;
 673                 clock.m2 = 9;
 674         } else {
 675                 clock.n = 2;
 676                 clock.p1 = 1;
 677                 clock.p2 = 10;
 678                 clock.m1 = 14;
 679                 clock.m2 = 8;
 680         }
 681         intel_clock(dev, refclk, &clock);
 682         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 683         return true;
 684 }
 685
 686 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 687 static bool
 688 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 689                       int target, int refclk, intel_clock_t *best_clock)
 690 {
 691         intel_clock_t clock;
 692         if (target < 200000) {
 693                 clock.p1 = 2;
 694                 clock.p2 = 10;
 695                 clock.n = 2;
 696                 clock.m1 = 23;
 697                 clock.m2 = 8;
 698         } else {
 699                 clock.p1 = 1;
 700                 clock.p2 = 10;
 701                 clock.n = 1;
 702                 clock.m1 = 14;
 703                 clock.m2 = 2;
 704         }
 705         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 706         clock.p = (clock.p1 * clock.p2);
 707         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 708         clock.vco = 0;
 709         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 710         return true;
 711 }
 712
 713 /**
 714  * intel_wait_for_vblank - wait for vblank on a given pipe
 715  * @dev: drm device
 716  * @pipe: pipe to wait for
 717  *
 718  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 719  * mode setting code.
 720  */
 721 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 722 {
 723         struct drm_i915_private *dev_priv = dev->dev_private;
 724         int pipestat_reg = PIPESTAT(pipe);
 725
 726         /* Clear existing vblank status. Note this will clear any other
 727          * sticky status fields as well.
 728          *
 729          * This races with i915_driver_irq_handler() with the result
 730          * that either function could miss a vblank event.  Here it is not
 731          * fatal, as we will either wait upon the next vblank interrupt or
 732          * timeout.  Generally speaking intel_wait_for_vblank() is only
 733          * called during modeset at which time the GPU should be idle and
 734          * should *not* be performing page flips and thus not waiting on
 735          * vblanks...
 736          * Currently, the result of us stealing a vblank from the irq
 737          * handler is that a single frame will be skipped during swapbuffers.
 738          */
 739         I915_WRITE(pipestat_reg,
 740                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 741
 742         /* Wait for vblank interrupt bit to set */
 743         if (wait_for(I915_READ(pipestat_reg) &
 744                      PIPE_VBLANK_INTERRUPT_STATUS,
 745                      50))
 746                 DRM_DEBUG_KMS("vblank wait timed out\n");
 747 }
 748
 749 /*
 750  * intel_wait_for_pipe_off - wait for pipe to turn off
 751  * @dev: drm device
 752  * @pipe: pipe to wait for
 753  *
 754  * After disabling a pipe, we can't wait for vblank in the usual way,
 755  * spinning on the vblank interrupt status bit, since we won't actually
 756  * see an interrupt when the pipe is disabled.
 757  *
 758  * On Gen4 and above:
 759  *   wait for the pipe register state bit to turn off
 760  *
 761  * Otherwise:
 762  *   wait for the display line value to settle (it usually
 763  *   ends up stopping at the start of the next frame).
 764  *
 765  */
 766 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 767 {
 768         struct drm_i915_private *dev_priv = dev->dev_private;
 769
 770         if (INTEL_INFO(dev)->gen >= 4) {
 771                 int reg = PIPECONF(pipe);
 772
 773                 /* Wait for the Pipe State to go off */
 774                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 775                              100))
 776                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 777         } else {
 778                 u32 last_line;
 779                 int reg = PIPEDSL(pipe);
 780                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 781
 782                 /* Wait for the display line to settle */
 783                 do {
 784                         last_line = I915_READ(reg) & DSL_LINEMASK;
 785                         mdelay(5);
 786                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 787                          time_after(timeout, jiffies));
 788                 if (time_after(jiffies, timeout))
 789                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 790         }
 791 }
 792
 793 static const char *state_string(bool enabled)
 794 {
 795         return enabled ? "on" : "off";
 796 }
 797
 798 /* Only for pre-ILK configs */
 799 static void assert_pll(struct drm_i915_private *dev_priv,
 800                        enum pipe pipe, bool state)
 801 {
 802         int reg;
 803         u32 val;
 804         bool cur_state;
 805
 806         reg = DPLL(pipe);
 807         val = I915_READ(reg);
 808         cur_state = !!(val & DPLL_VCO_ENABLE);
 809         WARN(cur_state != state,
 810              "PLL state assertion failure (expected %s, current %s)\n",
 811              state_string(state), state_string(cur_state));
 812 }
 813 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 814 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 815
 816 /* For ILK+ */
 817 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 818                            enum pipe pipe, bool state)
 819 {
 820         int reg;
 821         u32 val;
 822         bool cur_state;
 823
 824         if (HAS_PCH_CPT(dev_priv->dev)) {
 825                 u32 pch_dpll;
 826
 827                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 828
 829                 /* Make sure the selected PLL is enabled to the transcoder */
 830                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 831                      "transcoder %d PLL not enabled\n", pipe);
 832
 833                 /* Convert the transcoder pipe number to a pll pipe number */
 834                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 835         }
 836
 837         reg = PCH_DPLL(pipe);
 838         val = I915_READ(reg);
 839         cur_state = !!(val & DPLL_VCO_ENABLE);
 840         WARN(cur_state != state,
 841              "PCH PLL state assertion failure (expected %s, current %s)\n",
 842              state_string(state), state_string(cur_state));
 843 }
 844 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 845 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 846
 847 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 848                           enum pipe pipe, bool state)
 849 {
 850         int reg;
 851         u32 val;
 852         bool cur_state;
 853
 854         reg = FDI_TX_CTL(pipe);
 855         val = I915_READ(reg);
 856         cur_state = !!(val & FDI_TX_ENABLE);
 857         WARN(cur_state != state,
 858              "FDI TX state assertion failure (expected %s, current %s)\n",
 859              state_string(state), state_string(cur_state));
 860 }
 861 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 862 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 863
 864 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 865                           enum pipe pipe, bool state)
 866 {
 867         int reg;
 868         u32 val;
 869         bool cur_state;
 870
 871         reg = FDI_RX_CTL(pipe);
 872         val = I915_READ(reg);
 873         cur_state = !!(val & FDI_RX_ENABLE);
 874         WARN(cur_state != state,
 875              "FDI RX state assertion failure (expected %s, current %s)\n",
 876              state_string(state), state_string(cur_state));
 877 }
 878 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 879 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 880
 881 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 882                                       enum pipe pipe)
 883 {
 884         int reg;
 885         u32 val;
 886
 887         /* ILK FDI PLL is always enabled */
 888         if (dev_priv->info->gen == 5)
 889                 return;
 890
 891         reg = FDI_TX_CTL(pipe);
 892         val = I915_READ(reg);
 893         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 894 }
 895
 896 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 897                                       enum pipe pipe)
 898 {
 899         int reg;
 900         u32 val;
 901
 902         reg = FDI_RX_CTL(pipe);
 903         val = I915_READ(reg);
 904         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 905 }
 906
 907 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 908                                   enum pipe pipe)
 909 {
 910         int pp_reg, lvds_reg;
 911         u32 val;
 912         enum pipe panel_pipe = PIPE_A;
 913         bool locked = true;
 914
 915         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 916                 pp_reg = PCH_PP_CONTROL;
 917                 lvds_reg = PCH_LVDS;
 918         } else {
 919                 pp_reg = PP_CONTROL;
 920                 lvds_reg = LVDS;
 921         }
 922
 923         val = I915_READ(pp_reg);
 924         if (!(val & PANEL_POWER_ON) ||
 925             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 926                 locked = false;
 927
 928         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 929                 panel_pipe = PIPE_B;
 930
 931         WARN(panel_pipe == pipe && locked,
 932              "panel assertion failure, pipe %c regs locked\n",
 933              pipe_name(pipe));
 934 }
 935
 936 static void assert_pipe(struct drm_i915_private *dev_priv,
 937                         enum pipe pipe, bool state)
 938 {
 939         int reg;
 940         u32 val;
 941         bool cur_state;
 942
 943         reg = PIPECONF(pipe);
 944         val = I915_READ(reg);
 945         cur_state = !!(val & PIPECONF_ENABLE);
 946         WARN(cur_state != state,
 947              "pipe %c assertion failure (expected %s, current %s)\n",
 948              pipe_name(pipe), state_string(state), state_string(cur_state));
 949 }
 950 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 951 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 952
 953 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 954                                  enum plane plane)
 955 {
 956         int reg;
 957         u32 val;
 958
 959         reg = DSPCNTR(plane);
 960         val = I915_READ(reg);
 961         WARN(!(val & DISPLAY_PLANE_ENABLE),
 962              "plane %c assertion failure, should be active but is disabled\n",
 963              plane_name(plane));
 964 }
 965
 966 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 967                                    enum pipe pipe)
 968 {
 969         int reg, i;
 970         u32 val;
 971         int cur_pipe;
 972
 973         /* Planes are fixed to pipes on ILK+ */
 974         if (HAS_PCH_SPLIT(dev_priv->dev))
 975                 return;
 976
 977         /* Need to check both planes against the pipe */
 978         for (i = 0; i < 2; i++) {
 979                 reg = DSPCNTR(i);
 980                 val = I915_READ(reg);
 981                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 982                         DISPPLANE_SEL_PIPE_SHIFT;
 983                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 984                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 985                      plane_name(i), pipe_name(pipe));
 986         }
 987 }
 988
 989 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 990 {
 991         u32 val;
 992         bool enabled;
 993
 994         val = I915_READ(PCH_DREF_CONTROL);
 995         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 996                             DREF_SUPERSPREAD_SOURCE_MASK));
 997         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 998 }
 999
1000 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1001                                        enum pipe pipe)
1002 {
1003         int reg;
1004         u32 val;
1005         bool enabled;
1006
1007         reg = TRANSCONF(pipe);
1008         val = I915_READ(reg);
1009         enabled = !!(val & TRANS_ENABLE);
1010         WARN(enabled,
1011              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1012              pipe_name(pipe));
1013 }
1014
1015 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1016                             enum pipe pipe, u32 port_sel, u32 val)
1017 {
1018         if ((val & DP_PORT_EN) == 0)
1019                 return false;
1020
1021         if (HAS_PCH_CPT(dev_priv->dev)) {
1022                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1023                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1024                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1025                         return false;
1026         } else {
1027                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1028                         return false;
1029         }
1030         return true;
1031 }
1032
1033 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1034                               enum pipe pipe, u32 val)
1035 {
1036         if ((val & PORT_ENABLE) == 0)
1037                 return false;
1038
1039         if (HAS_PCH_CPT(dev_priv->dev)) {
1040                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1041                         return false;
1042         } else {
1043                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1044                         return false;
1045         }
1046         return true;
1047 }
1048
1049 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1050                               enum pipe pipe, u32 val)
1051 {
1052         if ((val & LVDS_PORT_EN) == 0)
1053                 return false;
1054
1055         if (HAS_PCH_CPT(dev_priv->dev)) {
1056                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1057                         return false;
1058         } else {
1059                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1060                         return false;
1061         }
1062         return true;
1063 }
1064
1065 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1066                               enum pipe pipe, u32 val)
1067 {
1068         if ((val & ADPA_DAC_ENABLE) == 0)
1069                 return false;
1070         if (HAS_PCH_CPT(dev_priv->dev)) {
1071                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1072                         return false;
1073         } else {
1074                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1075                         return false;
1076         }
1077         return true;
1078 }
1079
1080 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1081                                    enum pipe pipe, int reg, u32 port_sel)
1082 {
1083         u32 val = I915_READ(reg);
1084         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1085              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1086              reg, pipe_name(pipe));
1087 }
1088
1089 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1090                                      enum pipe pipe, int reg)
1091 {
1092         u32 val = I915_READ(reg);
1093         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1094              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1095              reg, pipe_name(pipe));
1096 }
1097
1098 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1099                                       enum pipe pipe)
1100 {
1101         int reg;
1102         u32 val;
1103
1104         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1105         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1106         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1107
1108         reg = PCH_ADPA;
1109         val = I915_READ(reg);
1110         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1111              "PCH VGA enabled on transcoder %c, should be disabled\n",
1112              pipe_name(pipe));
1113
1114         reg = PCH_LVDS;
1115         val = I915_READ(reg);
1116         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1117              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1118              pipe_name(pipe));
1119
1120         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1121         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1122         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1123 }
1124
1125 /**
1126  * intel_enable_pll - enable a PLL
1127  * @dev_priv: i915 private structure
1128  * @pipe: pipe PLL to enable
1129  *
1130  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1131  * make sure the PLL reg is writable first though, since the panel write
1132  * protect mechanism may be enabled.
1133  *
1134  * Note!  This is for pre-ILK only.
1135  */
1136 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1137 {
1138         int reg;
1139         u32 val;
1140
1141         /* No really, not for ILK+ */
1142         BUG_ON(dev_priv->info->gen >= 5);
1143
1144         /* PLL is protected by panel, make sure we can write it */
1145         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1146                 assert_panel_unlocked(dev_priv, pipe);
1147
1148         reg = DPLL(pipe);
1149         val = I915_READ(reg);
1150         val |= DPLL_VCO_ENABLE;
1151
1152         /* We do this three times for luck */
1153         I915_WRITE(reg, val);
1154         POSTING_READ(reg);
1155         udelay(150); /* wait for warmup */
1156         I915_WRITE(reg, val);
1157         POSTING_READ(reg);
1158         udelay(150); /* wait for warmup */
1159         I915_WRITE(reg, val);
1160         POSTING_READ(reg);
1161         udelay(150); /* wait for warmup */
1162 }
1163
1164 /**
1165  * intel_disable_pll - disable a PLL
1166  * @dev_priv: i915 private structure
1167  * @pipe: pipe PLL to disable
1168  *
1169  * Disable the PLL for @pipe, making sure the pipe is off first.
1170  *
1171  * Note!  This is for pre-ILK only.
1172  */
1173 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1174 {
1175         int reg;
1176         u32 val;
1177
1178         /* Don't disable pipe A or pipe A PLLs if needed */
1179         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1180                 return;
1181
1182         /* Make sure the pipe isn't still relying on us */
1183         assert_pipe_disabled(dev_priv, pipe);
1184
1185         reg = DPLL(pipe);
1186         val = I915_READ(reg);
1187         val &= ~DPLL_VCO_ENABLE;
1188         I915_WRITE(reg, val);
1189         POSTING_READ(reg);
1190 }
1191
1192 /**
1193  * intel_enable_pch_pll - enable PCH PLL
1194  * @dev_priv: i915 private structure
1195  * @pipe: pipe PLL to enable
1196  *
1197  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1198  * drives the transcoder clock.
1199  */
1200 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1201                                  enum pipe pipe)
1202 {
1203         int reg;
1204         u32 val;
1205
1206         if (pipe > 1)
1207                 return;
1208
1209         /* PCH only available on ILK+ */
1210         BUG_ON(dev_priv->info->gen < 5);
1211
1212         /* PCH refclock must be enabled first */
1213         assert_pch_refclk_enabled(dev_priv);
1214
1215         reg = PCH_DPLL(pipe);
1216         val = I915_READ(reg);
1217         val |= DPLL_VCO_ENABLE;
1218         I915_WRITE(reg, val);
1219         POSTING_READ(reg);
1220         udelay(200);
1221 }
1222
1223 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1224                                   enum pipe pipe)
1225 {
1226         int reg;
1227         u32 val;
1228
1229         if (pipe > 1)
1230                 return;
1231
1232         /* PCH only available on ILK+ */
1233         BUG_ON(dev_priv->info->gen < 5);
1234
1235         /* Make sure transcoder isn't still depending on us */
1236         assert_transcoder_disabled(dev_priv, pipe);
1237
1238         reg = PCH_DPLL(pipe);
1239         val = I915_READ(reg);
1240         val &= ~DPLL_VCO_ENABLE;
1241         I915_WRITE(reg, val);
1242         POSTING_READ(reg);
1243         udelay(200);
1244 }
1245
1246 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1247                                     enum pipe pipe)
1248 {
1249         int reg;
1250         u32 val;
1251
1252         /* PCH only available on ILK+ */
1253         BUG_ON(dev_priv->info->gen < 5);
1254
1255         /* Make sure PCH DPLL is enabled */
1256         assert_pch_pll_enabled(dev_priv, pipe);
1257
1258         /* FDI must be feeding us bits for PCH ports */
1259         assert_fdi_tx_enabled(dev_priv, pipe);
1260         assert_fdi_rx_enabled(dev_priv, pipe);
1261
1262         reg = TRANSCONF(pipe);
1263         val = I915_READ(reg);
1264
1265         if (HAS_PCH_IBX(dev_priv->dev)) {
1266                 /*
1267                  * make the BPC in transcoder be consistent with
1268                  * that in pipeconf reg.
1269                  */
1270                 val &= ~PIPE_BPC_MASK;
1271                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1272         }
1273         I915_WRITE(reg, val | TRANS_ENABLE);
1274         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1275                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1276 }
1277
1278 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1279                                      enum pipe pipe)
1280 {
1281         int reg;
1282         u32 val;
1283
1284         /* FDI relies on the transcoder */
1285         assert_fdi_tx_disabled(dev_priv, pipe);
1286         assert_fdi_rx_disabled(dev_priv, pipe);
1287
1288         /* Ports must be off as well */
1289         assert_pch_ports_disabled(dev_priv, pipe);
1290
1291         reg = TRANSCONF(pipe);
1292         val = I915_READ(reg);
1293         val &= ~TRANS_ENABLE;
1294         I915_WRITE(reg, val);
1295         /* wait for PCH transcoder off, transcoder state */
1296         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1297                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1298 }
1299
1300 /**
1301  * intel_enable_pipe - enable a pipe, asserting requirements
1302  * @dev_priv: i915 private structure
1303  * @pipe: pipe to enable
1304  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1305  *
1306  * Enable @pipe, making sure that various hardware specific requirements
1307  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1308  *
1309  * @pipe should be %PIPE_A or %PIPE_B.
1310  *
1311  * Will wait until the pipe is actually running (i.e. first vblank) before
1312  * returning.
1313  */
1314 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1315                               bool pch_port)
1316 {
1317         int reg;
1318         u32 val;
1319
1320         /*
1321          * A pipe without a PLL won't actually be able to drive bits from
1322          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1323          * need the check.
1324          */
1325         if (!HAS_PCH_SPLIT(dev_priv->dev))
1326                 assert_pll_enabled(dev_priv, pipe);
1327         else {
1328                 if (pch_port) {
1329                         /* if driving the PCH, we need FDI enabled */
1330                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1331                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1332                 }
1333                 /* FIXME: assert CPU port conditions for SNB+ */
1334         }
1335
1336         reg = PIPECONF(pipe);
1337         val = I915_READ(reg);
1338         if (val & PIPECONF_ENABLE)
1339                 return;
1340
1341         I915_WRITE(reg, val | PIPECONF_ENABLE);
1342         intel_wait_for_vblank(dev_priv->dev, pipe);
1343 }
1344
1345 /**
1346  * intel_disable_pipe - disable a pipe, asserting requirements
1347  * @dev_priv: i915 private structure
1348  * @pipe: pipe to disable
1349  *
1350  * Disable @pipe, making sure that various hardware specific requirements
1351  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1352  *
1353  * @pipe should be %PIPE_A or %PIPE_B.
1354  *
1355  * Will wait until the pipe has shut down before returning.
1356  */
1357 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1358                                enum pipe pipe)
1359 {
1360         int reg;
1361         u32 val;
1362
1363         /*
1364          * Make sure planes won't keep trying to pump pixels to us,
1365          * or we might hang the display.
1366          */
1367         assert_planes_disabled(dev_priv, pipe);
1368
1369         /* Don't disable pipe A or pipe A PLLs if needed */
1370         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1371                 return;
1372
1373         reg = PIPECONF(pipe);
1374         val = I915_READ(reg);
1375         if ((val & PIPECONF_ENABLE) == 0)
1376                 return;
1377
1378         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1379         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1380 }
1381
1382 /*
1383  * Plane regs are double buffered, going from enabled->disabled needs a
1384  * trigger in order to latch.  The display address reg provides this.
1385  */
1386 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1387                                       enum plane plane)
1388 {
1389         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1390         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1391 }
1392
1393 /**
1394  * intel_enable_plane - enable a display plane on a given pipe
1395  * @dev_priv: i915 private structure
1396  * @plane: plane to enable
1397  * @pipe: pipe being fed
1398  *
1399  * Enable @plane on @pipe, making sure that @pipe is running first.
1400  */
1401 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1402                                enum plane plane, enum pipe pipe)
1403 {
1404         int reg;
1405         u32 val;
1406
1407         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1408         assert_pipe_enabled(dev_priv, pipe);
1409
1410         reg = DSPCNTR(plane);
1411         val = I915_READ(reg);
1412         if (val & DISPLAY_PLANE_ENABLE)
1413                 return;
1414
1415         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1416         intel_flush_display_plane(dev_priv, plane);
1417         intel_wait_for_vblank(dev_priv->dev, pipe);
1418 }
1419
1420 /**
1421  * intel_disable_plane - disable a display plane
1422  * @dev_priv: i915 private structure
1423  * @plane: plane to disable
1424  * @pipe: pipe consuming the data
1425  *
1426  * Disable @plane; should be an independent operation.
1427  */
1428 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1429                                 enum plane plane, enum pipe pipe)
1430 {
1431         int reg;
1432         u32 val;
1433
1434         reg = DSPCNTR(plane);
1435         val = I915_READ(reg);
1436         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1437                 return;
1438
1439         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1440         intel_flush_display_plane(dev_priv, plane);
1441         intel_wait_for_vblank(dev_priv->dev, pipe);
1442 }
1443
1444 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1445                            enum pipe pipe, int reg, u32 port_sel)
1446 {
1447         u32 val = I915_READ(reg);
1448         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1449                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1450                 I915_WRITE(reg, val & ~DP_PORT_EN);
1451         }
1452 }
1453
1454 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1455                              enum pipe pipe, int reg)
1456 {
1457         u32 val = I915_READ(reg);
1458         if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1459                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1460                               reg, pipe);
1461                 I915_WRITE(reg, val & ~PORT_ENABLE);
1462         }
1463 }
1464
1465 /* Disable any ports connected to this transcoder */
1466 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1467                                     enum pipe pipe)
1468 {
1469         u32 reg, val;
1470
1471         val = I915_READ(PCH_PP_CONTROL);
1472         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1473
1474         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1477
1478         reg = PCH_ADPA;
1479         val = I915_READ(reg);
1480         if (adpa_pipe_enabled(dev_priv, pipe, val))
1481                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1482
1483         reg = PCH_LVDS;
1484         val = I915_READ(reg);
1485         if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1486                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1487                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1488                 POSTING_READ(reg);
1489                 udelay(100);
1490         }
1491
1492         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1493         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1494         disable_pch_hdmi(dev_priv, pipe, HDMID);
1495 }
1496
1497 static void i8xx_disable_fbc(struct drm_device *dev)
1498 {
1499         struct drm_i915_private *dev_priv = dev->dev_private;
1500         u32 fbc_ctl;
1501
1502         /* Disable compression */
1503         fbc_ctl = I915_READ(FBC_CONTROL);
1504         if ((fbc_ctl & FBC_CTL_EN) == 0)
1505                 return;
1506
1507         fbc_ctl &= ~FBC_CTL_EN;
1508         I915_WRITE(FBC_CONTROL, fbc_ctl);
1509
1510         /* Wait for compressing bit to clear */
1511         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1512                 DRM_DEBUG_KMS("FBC idle timed out\n");
1513                 return;
1514         }
1515
1516         DRM_DEBUG_KMS("disabled FBC\n");
1517 }
1518
1519 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1520 {
1521         struct drm_device *dev = crtc->dev;
1522         struct drm_i915_private *dev_priv = dev->dev_private;
1523         struct drm_framebuffer *fb = crtc->fb;
1524         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1525         struct drm_i915_gem_object *obj = intel_fb->obj;
1526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1527         int cfb_pitch;
1528         int plane, i;
1529         u32 fbc_ctl, fbc_ctl2;
1530
1531         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1532         if (fb->pitch < cfb_pitch)
1533                 cfb_pitch = fb->pitch;
1534
1535         /* FBC_CTL wants 64B units */
1536         cfb_pitch = (cfb_pitch / 64) - 1;
1537         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1538
1539         /* Clear old tags */
1540         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1541                 I915_WRITE(FBC_TAG + (i * 4), 0);
1542
1543         /* Set it up... */
1544         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1545         fbc_ctl2 |= plane;
1546         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1547         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1548
1549         /* enable it... */
1550         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1551         if (IS_I945GM(dev))
1552                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1553         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1554         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1555         fbc_ctl |= obj->fence_reg;
1556         I915_WRITE(FBC_CONTROL, fbc_ctl);
1557
1558         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1559                       cfb_pitch, crtc->y, intel_crtc->plane);
1560 }
1561
1562 static bool i8xx_fbc_enabled(struct drm_device *dev)
1563 {
1564         struct drm_i915_private *dev_priv = dev->dev_private;
1565
1566         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1567 }
1568
1569 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1570 {
1571         struct drm_device *dev = crtc->dev;
1572         struct drm_i915_private *dev_priv = dev->dev_private;
1573         struct drm_framebuffer *fb = crtc->fb;
1574         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1575         struct drm_i915_gem_object *obj = intel_fb->obj;
1576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1577         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1578         unsigned long stall_watermark = 200;
1579         u32 dpfc_ctl;
1580
1581         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1582         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1583         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1584
1585         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1586                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1587                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1588         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1589
1590         /* enable it... */
1591         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1592
1593         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1594 }
1595
1596 static void g4x_disable_fbc(struct drm_device *dev)
1597 {
1598         struct drm_i915_private *dev_priv = dev->dev_private;
1599         u32 dpfc_ctl;
1600
1601         /* Disable compression */
1602         dpfc_ctl = I915_READ(DPFC_CONTROL);
1603         if (dpfc_ctl & DPFC_CTL_EN) {
1604                 dpfc_ctl &= ~DPFC_CTL_EN;
1605                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1606
1607                 DRM_DEBUG_KMS("disabled FBC\n");
1608         }
1609 }
1610
1611 static bool g4x_fbc_enabled(struct drm_device *dev)
1612 {
1613         struct drm_i915_private *dev_priv = dev->dev_private;
1614
1615         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1616 }
1617
1618 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1619 {
1620         struct drm_i915_private *dev_priv = dev->dev_private;
1621         u32 blt_ecoskpd;
1622
1623         /* Make sure blitter notifies FBC of writes */
1624         gen6_gt_force_wake_get(dev_priv);
1625         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1626         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1627                 GEN6_BLITTER_LOCK_SHIFT;
1628         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1629         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1630         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1631         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1632                          GEN6_BLITTER_LOCK_SHIFT);
1633         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1634         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1635         gen6_gt_force_wake_put(dev_priv);
1636 }
1637
1638 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1639 {
1640         struct drm_device *dev = crtc->dev;
1641         struct drm_i915_private *dev_priv = dev->dev_private;
1642         struct drm_framebuffer *fb = crtc->fb;
1643         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1644         struct drm_i915_gem_object *obj = intel_fb->obj;
1645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1646         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1647         unsigned long stall_watermark = 200;
1648         u32 dpfc_ctl;
1649
1650         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1651         dpfc_ctl &= DPFC_RESERVED;
1652         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1653         /* Set persistent mode for front-buffer rendering, ala X. */
1654         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1655         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1656         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1657
1658         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1659                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1660                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1661         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1662         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1663         /* enable it... */
1664         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1665
1666         if (IS_GEN6(dev)) {
1667                 I915_WRITE(SNB_DPFC_CTL_SA,
1668                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1669                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1670                 sandybridge_blit_fbc_update(dev);
1671         }
1672
1673         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1674 }
1675
1676 static void ironlake_disable_fbc(struct drm_device *dev)
1677 {
1678         struct drm_i915_private *dev_priv = dev->dev_private;
1679         u32 dpfc_ctl;
1680
1681         /* Disable compression */
1682         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1683         if (dpfc_ctl & DPFC_CTL_EN) {
1684                 dpfc_ctl &= ~DPFC_CTL_EN;
1685                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1686
1687                 DRM_DEBUG_KMS("disabled FBC\n");
1688         }
1689 }
1690
1691 static bool ironlake_fbc_enabled(struct drm_device *dev)
1692 {
1693         struct drm_i915_private *dev_priv = dev->dev_private;
1694
1695         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1696 }
1697
1698 bool intel_fbc_enabled(struct drm_device *dev)
1699 {
1700         struct drm_i915_private *dev_priv = dev->dev_private;
1701
1702         if (!dev_priv->display.fbc_enabled)
1703                 return false;
1704
1705         return dev_priv->display.fbc_enabled(dev);
1706 }
1707
1708 static void intel_fbc_work_fn(struct work_struct *__work)
1709 {
1710         struct intel_fbc_work *work =
1711                 container_of(to_delayed_work(__work),
1712                              struct intel_fbc_work, work);
1713         struct drm_device *dev = work->crtc->dev;
1714         struct drm_i915_private *dev_priv = dev->dev_private;
1715
1716         mutex_lock(&dev->struct_mutex);
1717         if (work == dev_priv->fbc_work) {
1718                 /* Double check that we haven't switched fb without cancelling
1719                  * the prior work.
1720                  */
1721                 if (work->crtc->fb == work->fb) {
1722                         dev_priv->display.enable_fbc(work->crtc,
1723                                                      work->interval);
1724
1725                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1726                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1727                         dev_priv->cfb_y = work->crtc->y;
1728                 }
1729
1730                 dev_priv->fbc_work = NULL;
1731         }
1732         mutex_unlock(&dev->struct_mutex);
1733
1734         kfree(work);
1735 }
1736
1737 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1738 {
1739         if (dev_priv->fbc_work == NULL)
1740                 return;
1741
1742         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1743
1744         /* Synchronisation is provided by struct_mutex and checking of
1745          * dev_priv->fbc_work, so we can perform the cancellation
1746          * entirely asynchronously.
1747          */
1748         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1749                 /* tasklet was killed before being run, clean up */
1750                 kfree(dev_priv->fbc_work);
1751
1752         /* Mark the work as no longer wanted so that if it does
1753          * wake-up (because the work was already running and waiting
1754          * for our mutex), it will discover that is no longer
1755          * necessary to run.
1756          */
1757         dev_priv->fbc_work = NULL;
1758 }
1759
1760 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1761 {
1762         struct intel_fbc_work *work;
1763         struct drm_device *dev = crtc->dev;
1764         struct drm_i915_private *dev_priv = dev->dev_private;
1765
1766         if (!dev_priv->display.enable_fbc)
1767                 return;
1768
1769         intel_cancel_fbc_work(dev_priv);
1770
1771         work = kzalloc(sizeof *work, GFP_KERNEL);
1772         if (work == NULL) {
1773                 dev_priv->display.enable_fbc(crtc, interval);
1774                 return;
1775         }
1776
1777         work->crtc = crtc;
1778         work->fb = crtc->fb;
1779         work->interval = interval;
1780         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1781
1782         dev_priv->fbc_work = work;
1783
1784         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1785
1786         /* Delay the actual enabling to let pageflipping cease and the
1787          * display to settle before starting the compression. Note that
1788          * this delay also serves a second purpose: it allows for a
1789          * vblank to pass after disabling the FBC before we attempt
1790          * to modify the control registers.
1791          *
1792          * A more complicated solution would involve tracking vblanks
1793          * following the termination of the page-flipping sequence
1794          * and indeed performing the enable as a co-routine and not
1795          * waiting synchronously upon the vblank.
1796          */
1797         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1798 }
1799
1800 void intel_disable_fbc(struct drm_device *dev)
1801 {
1802         struct drm_i915_private *dev_priv = dev->dev_private;
1803
1804         intel_cancel_fbc_work(dev_priv);
1805
1806         if (!dev_priv->display.disable_fbc)
1807                 return;
1808
1809         dev_priv->display.disable_fbc(dev);
1810         dev_priv->cfb_plane = -1;
1811 }
1812
1813 /**
1814  * intel_update_fbc - enable/disable FBC as needed
1815  * @dev: the drm_device
1816  *
1817  * Set up the framebuffer compression hardware at mode set time.  We
1818  * enable it if possible:
1819  *   - plane A only (on pre-965)
1820  *   - no pixel mulitply/line duplication
1821  *   - no alpha buffer discard
1822  *   - no dual wide
1823  *   - framebuffer <= 2048 in width, 1536 in height
1824  *
1825  * We can't assume that any compression will take place (worst case),
1826  * so the compressed buffer has to be the same size as the uncompressed
1827  * one.  It also must reside (along with the line length buffer) in
1828  * stolen memory.
1829  *
1830  * We need to enable/disable FBC on a global basis.
1831  */
1832 static void intel_update_fbc(struct drm_device *dev)
1833 {
1834         struct drm_i915_private *dev_priv = dev->dev_private;
1835         struct drm_crtc *crtc = NULL, *tmp_crtc;
1836         struct intel_crtc *intel_crtc;
1837         struct drm_framebuffer *fb;
1838         struct intel_framebuffer *intel_fb;
1839         struct drm_i915_gem_object *obj;
1840         int enable_fbc;
1841
1842         DRM_DEBUG_KMS("\n");
1843
1844         if (!i915_powersave)
1845                 return;
1846
1847         if (!I915_HAS_FBC(dev))
1848                 return;
1849
1850         /*
1851          * If FBC is already on, we just have to verify that we can
1852          * keep it that way...
1853          * Need to disable if:
1854          *   - more than one pipe is active
1855          *   - changing FBC params (stride, fence, mode)
1856          *   - new fb is too large to fit in compressed buffer
1857          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1858          */
1859         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1860                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1861                         if (crtc) {
1862                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1863                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1864                                 goto out_disable;
1865                         }
1866                         crtc = tmp_crtc;
1867                 }
1868         }
1869
1870         if (!crtc || crtc->fb == NULL) {
1871                 DRM_DEBUG_KMS("no output, disabling\n");
1872                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1873                 goto out_disable;
1874         }
1875
1876         intel_crtc = to_intel_crtc(crtc);
1877         fb = crtc->fb;
1878         intel_fb = to_intel_framebuffer(fb);
1879         obj = intel_fb->obj;
1880
1881         enable_fbc = i915_enable_fbc;
1882         if (enable_fbc < 0) {
1883                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1884                 enable_fbc = 1;
1885                 if (INTEL_INFO(dev)->gen <= 6)
1886                         enable_fbc = 0;
1887         }
1888         if (!enable_fbc) {
1889                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1890                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1891                 goto out_disable;
1892         }
1893         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1894                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1895                               "compression\n");
1896                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1897                 goto out_disable;
1898         }
1899         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1900             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1901                 DRM_DEBUG_KMS("mode incompatible with compression, "
1902                               "disabling\n");
1903                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1904                 goto out_disable;
1905         }
1906         if ((crtc->mode.hdisplay > 2048) ||
1907             (crtc->mode.vdisplay > 1536)) {
1908                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1909                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1910                 goto out_disable;
1911         }
1912         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1913                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1914                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1915                 goto out_disable;
1916         }
1917
1918         /* The use of a CPU fence is mandatory in order to detect writes
1919          * by the CPU to the scanout and trigger updates to the FBC.
1920          */
1921         if (obj->tiling_mode != I915_TILING_X ||
1922             obj->fence_reg == I915_FENCE_REG_NONE) {
1923                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1924                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1925                 goto out_disable;
1926         }
1927
1928         /* If the kernel debugger is active, always disable compression */
1929         if (in_dbg_master())
1930                 goto out_disable;
1931
1932         /* If the scanout has not changed, don't modify the FBC settings.
1933          * Note that we make the fundamental assumption that the fb->obj
1934          * cannot be unpinned (and have its GTT offset and fence revoked)
1935          * without first being decoupled from the scanout and FBC disabled.
1936          */
1937         if (dev_priv->cfb_plane == intel_crtc->plane &&
1938             dev_priv->cfb_fb == fb->base.id &&
1939             dev_priv->cfb_y == crtc->y)
1940                 return;
1941
1942         if (intel_fbc_enabled(dev)) {
1943                 /* We update FBC along two paths, after changing fb/crtc
1944                  * configuration (modeswitching) and after page-flipping
1945                  * finishes. For the latter, we know that not only did
1946                  * we disable the FBC at the start of the page-flip
1947                  * sequence, but also more than one vblank has passed.
1948                  *
1949                  * For the former case of modeswitching, it is possible
1950                  * to switch between two FBC valid configurations
1951                  * instantaneously so we do need to disable the FBC
1952                  * before we can modify its control registers. We also
1953                  * have to wait for the next vblank for that to take
1954                  * effect. However, since we delay enabling FBC we can
1955                  * assume that a vblank has passed since disabling and
1956                  * that we can safely alter the registers in the deferred
1957                  * callback.
1958                  *
1959                  * In the scenario that we go from a valid to invalid
1960                  * and then back to valid FBC configuration we have
1961                  * no strict enforcement that a vblank occurred since
1962                  * disabling the FBC. However, along all current pipe
1963                  * disabling paths we do need to wait for a vblank at
1964                  * some point. And we wait before enabling FBC anyway.
1965                  */
1966                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1967                 intel_disable_fbc(dev);
1968         }
1969
1970         intel_enable_fbc(crtc, 500);
1971         return;
1972
1973 out_disable:
1974         /* Multiple disables should be harmless */
1975         if (intel_fbc_enabled(dev)) {
1976                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1977                 intel_disable_fbc(dev);
1978         }
1979 }
1980
1981 int
1982 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1983                            struct drm_i915_gem_object *obj,
1984                            struct intel_ring_buffer *pipelined)
1985 {
1986         struct drm_i915_private *dev_priv = dev->dev_private;
1987         u32 alignment;
1988         int ret;
1989
1990         switch (obj->tiling_mode) {
1991         case I915_TILING_NONE:
1992                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1993                         alignment = 128 * 1024;
1994                 else if (INTEL_INFO(dev)->gen >= 4)
1995                         alignment = 4 * 1024;
1996                 else
1997                         alignment = 64 * 1024;
1998                 break;
1999         case I915_TILING_X:
2000                 /* pin() will align the object as required by fence */
2001                 alignment = 0;
2002                 break;
2003         case I915_TILING_Y:
2004                 /* FIXME: Is this true? */
2005                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2006                 return -EINVAL;
2007         default:
2008                 BUG();
2009         }
2010
2011         dev_priv->mm.interruptible = false;
2012         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2013         if (ret)
2014                 goto err_interruptible;
2015
2016         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2017          * fence, whereas 965+ only requires a fence if using
2018          * framebuffer compression.  For simplicity, we always install
2019          * a fence as the cost is not that onerous.
2020          */
2021         if (obj->tiling_mode != I915_TILING_NONE) {
2022                 ret = i915_gem_object_get_fence(obj, pipelined);
2023                 if (ret)
2024                         goto err_unpin;
2025         }
2026
2027         dev_priv->mm.interruptible = true;
2028         return 0;
2029
2030 err_unpin:
2031         i915_gem_object_unpin(obj);
2032 err_interruptible:
2033         dev_priv->mm.interruptible = true;
2034         return ret;
2035 }
2036
2037 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2038                              int x, int y)
2039 {
2040         struct drm_device *dev = crtc->dev;
2041         struct drm_i915_private *dev_priv = dev->dev_private;
2042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2043         struct intel_framebuffer *intel_fb;
2044         struct drm_i915_gem_object *obj;
2045         int plane = intel_crtc->plane;
2046         unsigned long Start, Offset;
2047         u32 dspcntr;
2048         u32 reg;
2049
2050         switch (plane) {
2051         case 0:
2052         case 1:
2053                 break;
2054         default:
2055                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2056                 return -EINVAL;
2057         }
2058
2059         intel_fb = to_intel_framebuffer(fb);
2060         obj = intel_fb->obj;
2061
2062         reg = DSPCNTR(plane);
2063         dspcntr = I915_READ(reg);
2064         /* Mask out pixel format bits in case we change it */
2065         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2066         switch (fb->bits_per_pixel) {
2067         case 8:
2068                 dspcntr |= DISPPLANE_8BPP;
2069                 break;
2070         case 16:
2071                 if (fb->depth == 15)
2072                         dspcntr |= DISPPLANE_15_16BPP;
2073                 else
2074                         dspcntr |= DISPPLANE_16BPP;
2075                 break;
2076         case 24:
2077         case 32:
2078                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2079                 break;
2080         default:
2081                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2082                 return -EINVAL;
2083         }
2084         if (INTEL_INFO(dev)->gen >= 4) {
2085                 if (obj->tiling_mode != I915_TILING_NONE)
2086                         dspcntr |= DISPPLANE_TILED;
2087                 else
2088                         dspcntr &= ~DISPPLANE_TILED;
2089         }
2090
2091         I915_WRITE(reg, dspcntr);
2092
2093         Start = obj->gtt_offset;
2094         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2095
2096         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2097                       Start, Offset, x, y, fb->pitch);
2098         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2099         if (INTEL_INFO(dev)->gen >= 4) {
2100                 I915_WRITE(DSPSURF(plane), Start);
2101                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2102                 I915_WRITE(DSPADDR(plane), Offset);
2103         } else
2104                 I915_WRITE(DSPADDR(plane), Start + Offset);
2105         POSTING_READ(reg);
2106
2107         return 0;
2108 }
2109
2110 static int ironlake_update_plane(struct drm_crtc *crtc,
2111                                  struct drm_framebuffer *fb, int x, int y)
2112 {
2113         struct drm_device *dev = crtc->dev;
2114         struct drm_i915_private *dev_priv = dev->dev_private;
2115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2116         struct intel_framebuffer *intel_fb;
2117         struct drm_i915_gem_object *obj;
2118         int plane = intel_crtc->plane;
2119         unsigned long Start, Offset;
2120         u32 dspcntr;
2121         u32 reg;
2122
2123         switch (plane) {
2124         case 0:
2125         case 1:
2126         case 2:
2127                 break;
2128         default:
2129                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2130                 return -EINVAL;
2131         }
2132
2133         intel_fb = to_intel_framebuffer(fb);
2134         obj = intel_fb->obj;
2135
2136         reg = DSPCNTR(plane);
2137         dspcntr = I915_READ(reg);
2138         /* Mask out pixel format bits in case we change it */
2139         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2140         switch (fb->bits_per_pixel) {
2141         case 8:
2142                 dspcntr |= DISPPLANE_8BPP;
2143                 break;
2144         case 16:
2145                 if (fb->depth != 16)
2146                         return -EINVAL;
2147
2148                 dspcntr |= DISPPLANE_16BPP;
2149                 break;
2150         case 24:
2151         case 32:
2152                 if (fb->depth == 24)
2153                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2154                 else if (fb->depth == 30)
2155                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2156                 else
2157                         return -EINVAL;
2158                 break;
2159         default:
2160                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2161                 return -EINVAL;
2162         }
2163
2164         if (obj->tiling_mode != I915_TILING_NONE)
2165                 dspcntr |= DISPPLANE_TILED;
2166         else
2167                 dspcntr &= ~DISPPLANE_TILED;
2168
2169         /* must disable */
2170         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2171
2172         I915_WRITE(reg, dspcntr);
2173
2174         Start = obj->gtt_offset;
2175         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2176
2177         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2178                       Start, Offset, x, y, fb->pitch);
2179         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2180         I915_WRITE(DSPSURF(plane), Start);
2181         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2182         I915_WRITE(DSPADDR(plane), Offset);
2183         POSTING_READ(reg);
2184
2185         return 0;
2186 }
2187
2188 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2189 static int
2190 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2191                            int x, int y, enum mode_set_atomic state)
2192 {
2193         struct drm_device *dev = crtc->dev;
2194         struct drm_i915_private *dev_priv = dev->dev_private;
2195         int ret;
2196
2197         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2198         if (ret)
2199                 return ret;
2200
2201         intel_update_fbc(dev);
2202         intel_increase_pllclock(crtc);
2203
2204         return 0;
2205 }
2206
2207 static int
2208 intel_finish_fb(struct drm_framebuffer *old_fb)
2209 {
2210         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2211         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2212         bool was_interruptible = dev_priv->mm.interruptible;
2213         int ret;
2214
2215         wait_event(dev_priv->pending_flip_queue,
2216                    atomic_read(&dev_priv->mm.wedged) ||
2217                    atomic_read(&obj->pending_flip) == 0);
2218
2219         /* Big Hammer, we also need to ensure that any pending
2220          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2221          * current scanout is retired before unpinning the old
2222          * framebuffer.
2223          *
2224          * This should only fail upon a hung GPU, in which case we
2225          * can safely continue.
2226          */
2227         dev_priv->mm.interruptible = false;
2228         ret = i915_gem_object_finish_gpu(obj);
2229         dev_priv->mm.interruptible = was_interruptible;
2230
2231         return ret;
2232 }
2233
2234 static int
2235 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2236                     struct drm_framebuffer *old_fb)
2237 {
2238         struct drm_device *dev = crtc->dev;
2239         struct drm_i915_master_private *master_priv;
2240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2241         int ret;
2242
2243         /* no fb bound */
2244         if (!crtc->fb) {
2245                 DRM_ERROR("No FB bound\n");
2246                 return 0;
2247         }
2248
2249         switch (intel_crtc->plane) {
2250         case 0:
2251         case 1:
2252                 break;
2253         case 2:
2254                 if (IS_IVYBRIDGE(dev))
2255                         break;
2256                 /* fall through otherwise */
2257         default:
2258                 DRM_ERROR("no plane for crtc\n");
2259                 return -EINVAL;
2260         }
2261
2262         mutex_lock(&dev->struct_mutex);
2263         ret = intel_pin_and_fence_fb_obj(dev,
2264                                          to_intel_framebuffer(crtc->fb)->obj,
2265                                          NULL);
2266         if (ret != 0) {
2267                 mutex_unlock(&dev->struct_mutex);
2268                 DRM_ERROR("pin & fence failed\n");
2269                 return ret;
2270         }
2271
2272         if (old_fb)
2273                 intel_finish_fb(old_fb);
2274
2275         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2276                                          LEAVE_ATOMIC_MODE_SET);
2277         if (ret) {
2278                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2279                 mutex_unlock(&dev->struct_mutex);
2280                 DRM_ERROR("failed to update base address\n");
2281                 return ret;
2282         }
2283
2284         if (old_fb) {
2285                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2286                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2287         }
2288
2289         mutex_unlock(&dev->struct_mutex);
2290
2291         if (!dev->primary->master)
2292                 return 0;
2293
2294         master_priv = dev->primary->master->driver_priv;
2295         if (!master_priv->sarea_priv)
2296                 return 0;
2297
2298         if (intel_crtc->pipe) {
2299                 master_priv->sarea_priv->pipeB_x = x;
2300                 master_priv->sarea_priv->pipeB_y = y;
2301         } else {
2302                 master_priv->sarea_priv->pipeA_x = x;
2303                 master_priv->sarea_priv->pipeA_y = y;
2304         }
2305
2306         return 0;
2307 }
2308
2309 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2310 {
2311         struct drm_device *dev = crtc->dev;
2312         struct drm_i915_private *dev_priv = dev->dev_private;
2313         u32 dpa_ctl;
2314
2315         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2316         dpa_ctl = I915_READ(DP_A);
2317         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2318
2319         if (clock < 200000) {
2320                 u32 temp;
2321                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2322                 /* workaround for 160Mhz:
2323                    1) program 0x4600c bits 15:0 = 0x8124
2324                    2) program 0x46010 bit 0 = 1
2325                    3) program 0x46034 bit 24 = 1
2326                    4) program 0x64000 bit 14 = 1
2327                    */
2328                 temp = I915_READ(0x4600c);
2329                 temp &= 0xffff0000;
2330                 I915_WRITE(0x4600c, temp | 0x8124);
2331
2332                 temp = I915_READ(0x46010);
2333                 I915_WRITE(0x46010, temp | 1);
2334
2335                 temp = I915_READ(0x46034);
2336                 I915_WRITE(0x46034, temp | (1 << 24));
2337         } else {
2338                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2339         }
2340         I915_WRITE(DP_A, dpa_ctl);
2341
2342         POSTING_READ(DP_A);
2343         udelay(500);
2344 }
2345
2346 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2347 {
2348         struct drm_device *dev = crtc->dev;
2349         struct drm_i915_private *dev_priv = dev->dev_private;
2350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2351         int pipe = intel_crtc->pipe;
2352         u32 reg, temp;
2353
2354         /* enable normal train */
2355         reg = FDI_TX_CTL(pipe);
2356         temp = I915_READ(reg);
2357         if (IS_IVYBRIDGE(dev)) {
2358                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2359                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2360         } else {
2361                 temp &= ~FDI_LINK_TRAIN_NONE;
2362                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2363         }
2364         I915_WRITE(reg, temp);
2365
2366         reg = FDI_RX_CTL(pipe);
2367         temp = I915_READ(reg);
2368         if (HAS_PCH_CPT(dev)) {
2369                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2370                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2371         } else {
2372                 temp &= ~FDI_LINK_TRAIN_NONE;
2373                 temp |= FDI_LINK_TRAIN_NONE;
2374         }
2375         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2376
2377         /* wait one idle pattern time */
2378         POSTING_READ(reg);
2379         udelay(1000);
2380
2381         /* IVB wants error correction enabled */
2382         if (IS_IVYBRIDGE(dev))
2383                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2384                            FDI_FE_ERRC_ENABLE);
2385 }
2386
2387 /* The FDI link training functions for ILK/Ibexpeak. */
2388 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2389 {
2390         struct drm_device *dev = crtc->dev;
2391         struct drm_i915_private *dev_priv = dev->dev_private;
2392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393         int pipe = intel_crtc->pipe;
2394         int plane = intel_crtc->plane;
2395         u32 reg, temp, tries;
2396
2397         /* FDI needs bits from pipe & plane first */
2398         assert_pipe_enabled(dev_priv, pipe);
2399         assert_plane_enabled(dev_priv, plane);
2400
2401         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2402            for train result */
2403         reg = FDI_RX_IMR(pipe);
2404         temp = I915_READ(reg);
2405         temp &= ~FDI_RX_SYMBOL_LOCK;
2406         temp &= ~FDI_RX_BIT_LOCK;
2407         I915_WRITE(reg, temp);
2408         I915_READ(reg);
2409         udelay(150);
2410
2411         /* enable CPU FDI TX and PCH FDI RX */
2412         reg = FDI_TX_CTL(pipe);
2413         temp = I915_READ(reg);
2414         temp &= ~(7 << 19);
2415         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2416         temp &= ~FDI_LINK_TRAIN_NONE;
2417         temp |= FDI_LINK_TRAIN_PATTERN_1;
2418         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2419
2420         reg = FDI_RX_CTL(pipe);
2421         temp = I915_READ(reg);
2422         temp &= ~FDI_LINK_TRAIN_NONE;
2423         temp |= FDI_LINK_TRAIN_PATTERN_1;
2424         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2425
2426         POSTING_READ(reg);
2427         udelay(150);
2428
2429         /* Ironlake workaround, enable clock pointer after FDI enable*/
2430         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2431         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2432                    FDI_RX_PHASE_SYNC_POINTER_EN);
2433
2434         reg = FDI_RX_IIR(pipe);
2435         for (tries = 0; tries < 5; tries++) {
2436                 temp = I915_READ(reg);
2437                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2438
2439                 if ((temp & FDI_RX_BIT_LOCK)) {
2440                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2441                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2442                         break;
2443                 }
2444         }
2445         if (tries == 5)
2446                 DRM_ERROR("FDI train 1 fail!\n");
2447
2448         /* Train 2 */
2449         reg = FDI_TX_CTL(pipe);
2450         temp = I915_READ(reg);
2451         temp &= ~FDI_LINK_TRAIN_NONE;
2452         temp |= FDI_LINK_TRAIN_PATTERN_2;
2453         I915_WRITE(reg, temp);
2454
2455         reg = FDI_RX_CTL(pipe);
2456         temp = I915_READ(reg);
2457         temp &= ~FDI_LINK_TRAIN_NONE;
2458         temp |= FDI_LINK_TRAIN_PATTERN_2;
2459         I915_WRITE(reg, temp);
2460
2461         POSTING_READ(reg);
2462         udelay(150);
2463
2464         reg = FDI_RX_IIR(pipe);
2465         for (tries = 0; tries < 5; tries++) {
2466                 temp = I915_READ(reg);
2467                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2468
2469                 if (temp & FDI_RX_SYMBOL_LOCK) {
2470                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2471                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2472                         break;
2473                 }
2474         }
2475         if (tries == 5)
2476                 DRM_ERROR("FDI train 2 fail!\n");
2477
2478         DRM_DEBUG_KMS("FDI train done\n");
2479
2480 }
2481
2482 static const int snb_b_fdi_train_param[] = {
2483         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2484         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2485         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2486         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2487 };
2488
2489 /* The FDI link training functions for SNB/Cougarpoint. */
2490 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2491 {
2492         struct drm_device *dev = crtc->dev;
2493         struct drm_i915_private *dev_priv = dev->dev_private;
2494         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2495         int pipe = intel_crtc->pipe;
2496         u32 reg, temp, i;
2497
2498         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2499            for train result */
2500         reg = FDI_RX_IMR(pipe);
2501         temp = I915_READ(reg);
2502         temp &= ~FDI_RX_SYMBOL_LOCK;
2503         temp &= ~FDI_RX_BIT_LOCK;
2504         I915_WRITE(reg, temp);
2505
2506         POSTING_READ(reg);
2507         udelay(150);
2508
2509         /* enable CPU FDI TX and PCH FDI RX */
2510         reg = FDI_TX_CTL(pipe);
2511         temp = I915_READ(reg);
2512         temp &= ~(7 << 19);
2513         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2514         temp &= ~FDI_LINK_TRAIN_NONE;
2515         temp |= FDI_LINK_TRAIN_PATTERN_1;
2516         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2517         /* SNB-B */
2518         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2519         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2520
2521         reg = FDI_RX_CTL(pipe);
2522         temp = I915_READ(reg);
2523         if (HAS_PCH_CPT(dev)) {
2524                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2525                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2526         } else {
2527                 temp &= ~FDI_LINK_TRAIN_NONE;
2528                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2529         }
2530         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2531
2532         POSTING_READ(reg);
2533         udelay(150);
2534
2535         for (i = 0; i < 4; i++) {
2536                 reg = FDI_TX_CTL(pipe);
2537                 temp = I915_READ(reg);
2538                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2539                 temp |= snb_b_fdi_train_param[i];
2540                 I915_WRITE(reg, temp);
2541
2542                 POSTING_READ(reg);
2543                 udelay(500);
2544
2545                 reg = FDI_RX_IIR(pipe);
2546                 temp = I915_READ(reg);
2547                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2548
2549                 if (temp & FDI_RX_BIT_LOCK) {
2550                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2551                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2552                         break;
2553                 }
2554         }
2555         if (i == 4)
2556                 DRM_ERROR("FDI train 1 fail!\n");
2557
2558         /* Train 2 */
2559         reg = FDI_TX_CTL(pipe);
2560         temp = I915_READ(reg);
2561         temp &= ~FDI_LINK_TRAIN_NONE;
2562         temp |= FDI_LINK_TRAIN_PATTERN_2;
2563         if (IS_GEN6(dev)) {
2564                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2565                 /* SNB-B */
2566                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2567         }
2568         I915_WRITE(reg, temp);
2569
2570         reg = FDI_RX_CTL(pipe);
2571         temp = I915_READ(reg);
2572         if (HAS_PCH_CPT(dev)) {
2573                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2574                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2575         } else {
2576                 temp &= ~FDI_LINK_TRAIN_NONE;
2577                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2578         }
2579         I915_WRITE(reg, temp);
2580
2581         POSTING_READ(reg);
2582         udelay(150);
2583
2584         for (i = 0; i < 4; i++) {
2585                 reg = FDI_TX_CTL(pipe);
2586                 temp = I915_READ(reg);
2587                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588                 temp |= snb_b_fdi_train_param[i];
2589                 I915_WRITE(reg, temp);
2590
2591                 POSTING_READ(reg);
2592                 udelay(500);
2593
2594                 reg = FDI_RX_IIR(pipe);
2595                 temp = I915_READ(reg);
2596                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2597
2598                 if (temp & FDI_RX_SYMBOL_LOCK) {
2599                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2600                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2601                         break;
2602                 }
2603         }
2604         if (i == 4)
2605                 DRM_ERROR("FDI train 2 fail!\n");
2606
2607         DRM_DEBUG_KMS("FDI train done.\n");
2608 }
2609
2610 /* Manual link training for Ivy Bridge A0 parts */
2611 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2612 {
2613         struct drm_device *dev = crtc->dev;
2614         struct drm_i915_private *dev_priv = dev->dev_private;
2615         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2616         int pipe = intel_crtc->pipe;
2617         u32 reg, temp, i;
2618
2619         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2620            for train result */
2621         reg = FDI_RX_IMR(pipe);
2622         temp = I915_READ(reg);
2623         temp &= ~FDI_RX_SYMBOL_LOCK;
2624         temp &= ~FDI_RX_BIT_LOCK;
2625         I915_WRITE(reg, temp);
2626
2627         POSTING_READ(reg);
2628         udelay(150);
2629
2630         /* enable CPU FDI TX and PCH FDI RX */
2631         reg = FDI_TX_CTL(pipe);
2632         temp = I915_READ(reg);
2633         temp &= ~(7 << 19);
2634         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2635         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2636         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2637         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2638         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2639         temp |= FDI_COMPOSITE_SYNC;
2640         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2641
2642         reg = FDI_RX_CTL(pipe);
2643         temp = I915_READ(reg);
2644         temp &= ~FDI_LINK_TRAIN_AUTO;
2645         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2646         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2647         temp |= FDI_COMPOSITE_SYNC;
2648         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2649
2650         POSTING_READ(reg);
2651         udelay(150);
2652
2653         for (i = 0; i < 4; i++) {
2654                 reg = FDI_TX_CTL(pipe);
2655                 temp = I915_READ(reg);
2656                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2657                 temp |= snb_b_fdi_train_param[i];
2658                 I915_WRITE(reg, temp);
2659
2660                 POSTING_READ(reg);
2661                 udelay(500);
2662
2663                 reg = FDI_RX_IIR(pipe);
2664                 temp = I915_READ(reg);
2665                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2666
2667                 if (temp & FDI_RX_BIT_LOCK ||
2668                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2669                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2670                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2671                         break;
2672                 }
2673         }
2674         if (i == 4)
2675                 DRM_ERROR("FDI train 1 fail!\n");
2676
2677         /* Train 2 */
2678         reg = FDI_TX_CTL(pipe);
2679         temp = I915_READ(reg);
2680         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2681         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2682         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2684         I915_WRITE(reg, temp);
2685
2686         reg = FDI_RX_CTL(pipe);
2687         temp = I915_READ(reg);
2688         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2689         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2690         I915_WRITE(reg, temp);
2691
2692         POSTING_READ(reg);
2693         udelay(150);
2694
2695         for (i = 0; i < 4; i++) {
2696                 reg = FDI_TX_CTL(pipe);
2697                 temp = I915_READ(reg);
2698                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2699                 temp |= snb_b_fdi_train_param[i];
2700                 I915_WRITE(reg, temp);
2701
2702                 POSTING_READ(reg);
2703                 udelay(500);
2704
2705                 reg = FDI_RX_IIR(pipe);
2706                 temp = I915_READ(reg);
2707                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2708
2709                 if (temp & FDI_RX_SYMBOL_LOCK) {
2710                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2711                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2712                         break;
2713                 }
2714         }
2715         if (i == 4)
2716                 DRM_ERROR("FDI train 2 fail!\n");
2717
2718         DRM_DEBUG_KMS("FDI train done.\n");
2719 }
2720
2721 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2722 {
2723         struct drm_device *dev = crtc->dev;
2724         struct drm_i915_private *dev_priv = dev->dev_private;
2725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2726         int pipe = intel_crtc->pipe;
2727         u32 reg, temp;
2728
2729         /* Write the TU size bits so error detection works */
2730         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2731                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2732
2733         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2734         reg = FDI_RX_CTL(pipe);
2735         temp = I915_READ(reg);
2736         temp &= ~((0x7 << 19) | (0x7 << 16));
2737         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2738         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2739         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2740
2741         POSTING_READ(reg);
2742         udelay(200);
2743
2744         /* Switch from Rawclk to PCDclk */
2745         temp = I915_READ(reg);
2746         I915_WRITE(reg, temp | FDI_PCDCLK);
2747
2748         POSTING_READ(reg);
2749         udelay(200);
2750
2751         /* Enable CPU FDI TX PLL, always on for Ironlake */
2752         reg = FDI_TX_CTL(pipe);
2753         temp = I915_READ(reg);
2754         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2755                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2756
2757                 POSTING_READ(reg);
2758                 udelay(100);
2759         }
2760 }
2761
2762 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2763 {
2764         struct drm_device *dev = crtc->dev;
2765         struct drm_i915_private *dev_priv = dev->dev_private;
2766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2767         int pipe = intel_crtc->pipe;
2768         u32 reg, temp;
2769
2770         /* disable CPU FDI tx and PCH FDI rx */
2771         reg = FDI_TX_CTL(pipe);
2772         temp = I915_READ(reg);
2773         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2774         POSTING_READ(reg);
2775
2776         reg = FDI_RX_CTL(pipe);
2777         temp = I915_READ(reg);
2778         temp &= ~(0x7 << 16);
2779         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2780         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2781
2782         POSTING_READ(reg);
2783         udelay(100);
2784
2785         /* Ironlake workaround, disable clock pointer after downing FDI */
2786         if (HAS_PCH_IBX(dev)) {
2787                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2788                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2789                            I915_READ(FDI_RX_CHICKEN(pipe) &
2790                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2791         }
2792
2793         /* still set train pattern 1 */
2794         reg = FDI_TX_CTL(pipe);
2795         temp = I915_READ(reg);
2796         temp &= ~FDI_LINK_TRAIN_NONE;
2797         temp |= FDI_LINK_TRAIN_PATTERN_1;
2798         I915_WRITE(reg, temp);
2799
2800         reg = FDI_RX_CTL(pipe);
2801         temp = I915_READ(reg);
2802         if (HAS_PCH_CPT(dev)) {
2803                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2804                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2805         } else {
2806                 temp &= ~FDI_LINK_TRAIN_NONE;
2807                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2808         }
2809         /* BPC in FDI rx is consistent with that in PIPECONF */
2810         temp &= ~(0x07 << 16);
2811         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2812         I915_WRITE(reg, temp);
2813
2814         POSTING_READ(reg);
2815         udelay(100);
2816 }
2817
2818 /*
2819  * When we disable a pipe, we need to clear any pending scanline wait events
2820  * to avoid hanging the ring, which we assume we are waiting on.
2821  */
2822 static void intel_clear_scanline_wait(struct drm_device *dev)
2823 {
2824         struct drm_i915_private *dev_priv = dev->dev_private;
2825         struct intel_ring_buffer *ring;
2826         u32 tmp;
2827
2828         if (IS_GEN2(dev))
2829                 /* Can't break the hang on i8xx */
2830                 return;
2831
2832         ring = LP_RING(dev_priv);
2833         tmp = I915_READ_CTL(ring);
2834         if (tmp & RING_WAIT)
2835                 I915_WRITE_CTL(ring, tmp);
2836 }
2837
2838 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2839 {
2840         struct drm_device *dev = crtc->dev;
2841         struct drm_i915_private *dev_priv = dev->dev_private;
2842         unsigned long flags;
2843         bool pending;
2844
2845         if (atomic_read(&dev_priv->mm.wedged))
2846                 return false;
2847
2848         spin_lock_irqsave(&dev->event_lock, flags);
2849         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2850         spin_unlock_irqrestore(&dev->event_lock, flags);
2851
2852         return pending;
2853 }
2854
2855 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2856 {
2857         struct drm_device *dev = crtc->dev;
2858         struct drm_i915_private *dev_priv = dev->dev_private;
2859
2860         if (crtc->fb == NULL)
2861                 return;
2862
2863         wait_event(dev_priv->pending_flip_queue,
2864                    !intel_crtc_has_pending_flip(crtc));
2865
2866         mutex_lock(&dev->struct_mutex);
2867         intel_finish_fb(crtc->fb);
2868         mutex_unlock(&dev->struct_mutex);
2869 }
2870
2871 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2872 {
2873         struct drm_device *dev = crtc->dev;
2874         struct drm_mode_config *mode_config = &dev->mode_config;
2875         struct intel_encoder *encoder;
2876
2877         /*
2878          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2879          * must be driven by its own crtc; no sharing is possible.
2880          */
2881         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2882                 if (encoder->base.crtc != crtc)
2883                         continue;
2884
2885                 switch (encoder->type) {
2886                 case INTEL_OUTPUT_EDP:
2887                         if (!intel_encoder_is_pch_edp(&encoder->base))
2888                                 return false;
2889                         continue;
2890                 }
2891         }
2892
2893         return true;
2894 }
2895
2896 /*
2897  * Enable PCH resources required for PCH ports:
2898  *   - PCH PLLs
2899  *   - FDI training & RX/TX
2900  *   - update transcoder timings
2901  *   - DP transcoding bits
2902  *   - transcoder
2903  */
2904 static void ironlake_pch_enable(struct drm_crtc *crtc)
2905 {
2906         struct drm_device *dev = crtc->dev;
2907         struct drm_i915_private *dev_priv = dev->dev_private;
2908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2909         int pipe = intel_crtc->pipe;
2910         u32 reg, temp, transc_sel;
2911
2912         /* For PCH output, training FDI link */
2913         dev_priv->display.fdi_link_train(crtc);
2914
2915         intel_enable_pch_pll(dev_priv, pipe);
2916
2917         if (HAS_PCH_CPT(dev)) {
2918                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2919                         TRANSC_DPLLB_SEL;
2920
2921                 /* Be sure PCH DPLL SEL is set */
2922                 temp = I915_READ(PCH_DPLL_SEL);
2923                 if (pipe == 0) {
2924                         temp &= ~(TRANSA_DPLLB_SEL);
2925                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2926                 } else if (pipe == 1) {
2927                         temp &= ~(TRANSB_DPLLB_SEL);
2928                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2929                 } else if (pipe == 2) {
2930                         temp &= ~(TRANSC_DPLLB_SEL);
2931                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2932                 }
2933                 I915_WRITE(PCH_DPLL_SEL, temp);
2934         }
2935
2936         /* set transcoder timing, panel must allow it */
2937         assert_panel_unlocked(dev_priv, pipe);
2938         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2939         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2940         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2941
2942         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2943         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2944         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2945
2946         intel_fdi_normal_train(crtc);
2947
2948         /* For PCH DP, enable TRANS_DP_CTL */
2949         if (HAS_PCH_CPT(dev) &&
2950             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2951              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2952                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2953                 reg = TRANS_DP_CTL(pipe);
2954                 temp = I915_READ(reg);
2955                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2956                           TRANS_DP_SYNC_MASK |
2957                           TRANS_DP_BPC_MASK);
2958                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2959                          TRANS_DP_ENH_FRAMING);
2960                 temp |= bpc << 9; /* same format but at 11:9 */
2961
2962                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2963                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2964                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2965                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2966
2967                 switch (intel_trans_dp_port_sel(crtc)) {
2968                 case PCH_DP_B:
2969                         temp |= TRANS_DP_PORT_SEL_B;
2970                         break;
2971                 case PCH_DP_C:
2972                         temp |= TRANS_DP_PORT_SEL_C;
2973                         break;
2974                 case PCH_DP_D:
2975                         temp |= TRANS_DP_PORT_SEL_D;
2976                         break;
2977                 default:
2978                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2979                         temp |= TRANS_DP_PORT_SEL_B;
2980                         break;
2981                 }
2982
2983                 I915_WRITE(reg, temp);
2984         }
2985
2986         intel_enable_transcoder(dev_priv, pipe);
2987 }
2988
2989 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2990 {
2991         struct drm_i915_private *dev_priv = dev->dev_private;
2992         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2993         u32 temp;
2994
2995         temp = I915_READ(dslreg);
2996         udelay(500);
2997         if (wait_for(I915_READ(dslreg) != temp, 5)) {
2998                 /* Without this, mode sets may fail silently on FDI */
2999                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3000                 udelay(250);
3001                 I915_WRITE(tc2reg, 0);
3002                 if (wait_for(I915_READ(dslreg) != temp, 5))
3003                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3004         }
3005 }
3006
3007 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3008 {
3009         struct drm_device *dev = crtc->dev;
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3012         int pipe = intel_crtc->pipe;
3013         int plane = intel_crtc->plane;
3014         u32 temp;
3015         bool is_pch_port;
3016
3017         if (intel_crtc->active)
3018                 return;
3019
3020         intel_crtc->active = true;
3021         intel_update_watermarks(dev);
3022
3023         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3024                 temp = I915_READ(PCH_LVDS);
3025                 if ((temp & LVDS_PORT_EN) == 0)
3026                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3027         }
3028
3029         is_pch_port = intel_crtc_driving_pch(crtc);
3030
3031         if (is_pch_port)
3032                 ironlake_fdi_pll_enable(crtc);
3033         else
3034                 ironlake_fdi_disable(crtc);
3035
3036         /* Enable panel fitting for LVDS */
3037         if (dev_priv->pch_pf_size &&
3038             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3039                 /* Force use of hard-coded filter coefficients
3040                  * as some pre-programmed values are broken,
3041                  * e.g. x201.
3042                  */
3043                 if (IS_IVYBRIDGE(dev))
3044                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3045                                                  PF_PIPE_SEL_IVB(pipe));
3046                 else
3047                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3048                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3049                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3050         }
3051
3052         /*
3053          * On ILK+ LUT must be loaded before the pipe is running but with
3054          * clocks enabled
3055          */
3056         intel_crtc_load_lut(crtc);
3057
3058         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3059         intel_enable_plane(dev_priv, plane, pipe);
3060
3061         if (is_pch_port)
3062                 ironlake_pch_enable(crtc);
3063
3064         mutex_lock(&dev->struct_mutex);
3065         intel_update_fbc(dev);
3066         mutex_unlock(&dev->struct_mutex);
3067
3068         intel_crtc_update_cursor(crtc, true);
3069 }
3070
3071 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3072 {
3073         struct drm_device *dev = crtc->dev;
3074         struct drm_i915_private *dev_priv = dev->dev_private;
3075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3076         int pipe = intel_crtc->pipe;
3077         int plane = intel_crtc->plane;
3078         u32 reg, temp;
3079
3080         if (!intel_crtc->active)
3081                 return;
3082
3083         intel_crtc_wait_for_pending_flips(crtc);
3084         drm_vblank_off(dev, pipe);
3085         intel_crtc_update_cursor(crtc, false);
3086
3087         intel_disable_plane(dev_priv, plane, pipe);
3088
3089         if (dev_priv->cfb_plane == plane)
3090                 intel_disable_fbc(dev);
3091
3092         intel_disable_pipe(dev_priv, pipe);
3093
3094         /* Disable PF */
3095         I915_WRITE(PF_CTL(pipe), 0);
3096         I915_WRITE(PF_WIN_SZ(pipe), 0);
3097
3098         ironlake_fdi_disable(crtc);
3099
3100         /* This is a horrible layering violation; we should be doing this in
3101          * the connector/encoder ->prepare instead, but we don't always have
3102          * enough information there about the config to know whether it will
3103          * actually be necessary or just cause undesired flicker.
3104          */
3105         intel_disable_pch_ports(dev_priv, pipe);
3106
3107         intel_disable_transcoder(dev_priv, pipe);
3108
3109         if (HAS_PCH_CPT(dev)) {
3110                 /* disable TRANS_DP_CTL */
3111                 reg = TRANS_DP_CTL(pipe);
3112                 temp = I915_READ(reg);
3113                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3114                 temp |= TRANS_DP_PORT_SEL_NONE;
3115                 I915_WRITE(reg, temp);
3116
3117                 /* disable DPLL_SEL */
3118                 temp = I915_READ(PCH_DPLL_SEL);
3119                 switch (pipe) {
3120                 case 0:
3121                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3122                         break;
3123                 case 1:
3124                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3125                         break;
3126                 case 2:
3127                         /* C shares PLL A or B */
3128                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3129                         break;
3130                 default:
3131                         BUG(); /* wtf */
3132                 }
3133                 I915_WRITE(PCH_DPLL_SEL, temp);
3134         }
3135
3136         /* disable PCH DPLL */
3137         if (!intel_crtc->no_pll)
3138                 intel_disable_pch_pll(dev_priv, pipe);
3139
3140         /* Switch from PCDclk to Rawclk */
3141         reg = FDI_RX_CTL(pipe);
3142         temp = I915_READ(reg);
3143         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3144
3145         /* Disable CPU FDI TX PLL */
3146         reg = FDI_TX_CTL(pipe);
3147         temp = I915_READ(reg);
3148         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3149
3150         POSTING_READ(reg);
3151         udelay(100);
3152
3153         reg = FDI_RX_CTL(pipe);
3154         temp = I915_READ(reg);
3155         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3156
3157         /* Wait for the clocks to turn off. */
3158         POSTING_READ(reg);
3159         udelay(100);
3160
3161         intel_crtc->active = false;
3162         intel_update_watermarks(dev);
3163
3164         mutex_lock(&dev->struct_mutex);
3165         intel_update_fbc(dev);
3166         intel_clear_scanline_wait(dev);
3167         mutex_unlock(&dev->struct_mutex);
3168 }
3169
3170 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3171 {
3172         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3173         int pipe = intel_crtc->pipe;
3174         int plane = intel_crtc->plane;
3175
3176         /* XXX: When our outputs are all unaware of DPMS modes other than off
3177          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3178          */
3179         switch (mode) {
3180         case DRM_MODE_DPMS_ON:
3181         case DRM_MODE_DPMS_STANDBY:
3182         case DRM_MODE_DPMS_SUSPEND:
3183                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3184                 ironlake_crtc_enable(crtc);
3185                 break;
3186
3187         case DRM_MODE_DPMS_OFF:
3188                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3189                 ironlake_crtc_disable(crtc);
3190                 break;
3191         }
3192 }
3193
3194 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3195 {
3196         if (!enable && intel_crtc->overlay) {
3197                 struct drm_device *dev = intel_crtc->base.dev;
3198                 struct drm_i915_private *dev_priv = dev->dev_private;
3199
3200                 mutex_lock(&dev->struct_mutex);
3201                 dev_priv->mm.interruptible = false;
3202                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3203                 dev_priv->mm.interruptible = true;
3204                 mutex_unlock(&dev->struct_mutex);
3205         }
3206
3207         /* Let userspace switch the overlay on again. In most cases userspace
3208          * has to recompute where to put it anyway.
3209          */
3210 }
3211
3212 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3213 {
3214         struct drm_device *dev = crtc->dev;
3215         struct drm_i915_private *dev_priv = dev->dev_private;
3216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3217         int pipe = intel_crtc->pipe;
3218         int plane = intel_crtc->plane;
3219
3220         if (intel_crtc->active)
3221                 return;
3222
3223         intel_crtc->active = true;
3224         intel_update_watermarks(dev);
3225
3226         intel_enable_pll(dev_priv, pipe);
3227         intel_enable_pipe(dev_priv, pipe, false);
3228         intel_enable_plane(dev_priv, plane, pipe);
3229
3230         intel_crtc_load_lut(crtc);
3231         intel_update_fbc(dev);
3232
3233         /* Give the overlay scaler a chance to enable if it's on this pipe */
3234         intel_crtc_dpms_overlay(intel_crtc, true);
3235         intel_crtc_update_cursor(crtc, true);
3236 }
3237
3238 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3239 {
3240         struct drm_device *dev = crtc->dev;
3241         struct drm_i915_private *dev_priv = dev->dev_private;
3242         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243         int pipe = intel_crtc->pipe;
3244         int plane = intel_crtc->plane;
3245
3246         if (!intel_crtc->active)
3247                 return;
3248
3249         /* Give the overlay scaler a chance to disable if it's on this pipe */
3250         intel_crtc_wait_for_pending_flips(crtc);
3251         drm_vblank_off(dev, pipe);
3252         intel_crtc_dpms_overlay(intel_crtc, false);
3253         intel_crtc_update_cursor(crtc, false);
3254
3255         if (dev_priv->cfb_plane == plane)
3256                 intel_disable_fbc(dev);
3257
3258         intel_disable_plane(dev_priv, plane, pipe);
3259         intel_disable_pipe(dev_priv, pipe);
3260         intel_disable_pll(dev_priv, pipe);
3261
3262         intel_crtc->active = false;
3263         intel_update_fbc(dev);
3264         intel_update_watermarks(dev);
3265         intel_clear_scanline_wait(dev);
3266 }
3267
3268 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3269 {
3270         /* XXX: When our outputs are all unaware of DPMS modes other than off
3271          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3272          */
3273         switch (mode) {
3274         case DRM_MODE_DPMS_ON:
3275         case DRM_MODE_DPMS_STANDBY:
3276         case DRM_MODE_DPMS_SUSPEND:
3277                 i9xx_crtc_enable(crtc);
3278                 break;
3279         case DRM_MODE_DPMS_OFF:
3280                 i9xx_crtc_disable(crtc);
3281                 break;
3282         }
3283 }
3284
3285 /**
3286  * Sets the power management mode of the pipe and plane.
3287  */
3288 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3289 {
3290         struct drm_device *dev = crtc->dev;
3291         struct drm_i915_private *dev_priv = dev->dev_private;
3292         struct drm_i915_master_private *master_priv;
3293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3294         int pipe = intel_crtc->pipe;
3295         bool enabled;
3296
3297         if (intel_crtc->dpms_mode == mode)
3298                 return;
3299
3300         intel_crtc->dpms_mode = mode;
3301
3302         dev_priv->display.dpms(crtc, mode);
3303
3304         if (!dev->primary->master)
3305                 return;
3306
3307         master_priv = dev->primary->master->driver_priv;
3308         if (!master_priv->sarea_priv)
3309                 return;
3310
3311         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3312
3313         switch (pipe) {
3314         case 0:
3315                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3316                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3317                 break;
3318         case 1:
3319                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3320                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3321                 break;
3322         default:
3323                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3324                 break;
3325         }
3326 }
3327
3328 static void intel_crtc_disable(struct drm_crtc *crtc)
3329 {
3330         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3331         struct drm_device *dev = crtc->dev;
3332
3333         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3334
3335         if (crtc->fb) {
3336                 mutex_lock(&dev->struct_mutex);
3337                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3338                 mutex_unlock(&dev->struct_mutex);
3339         }
3340 }
3341
3342 /* Prepare for a mode set.
3343  *
3344  * Note we could be a lot smarter here.  We need to figure out which outputs
3345  * will be enabled, which disabled (in short, how the config will changes)
3346  * and perform the minimum necessary steps to accomplish that, e.g. updating
3347  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3348  * panel fitting is in the proper state, etc.
3349  */
3350 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3351 {
3352         i9xx_crtc_disable(crtc);
3353 }
3354
3355 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3356 {
3357         i9xx_crtc_enable(crtc);
3358 }
3359
3360 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3361 {
3362         ironlake_crtc_disable(crtc);
3363 }
3364
3365 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3366 {
3367         ironlake_crtc_enable(crtc);
3368 }
3369
3370 void intel_encoder_prepare(struct drm_encoder *encoder)
3371 {
3372         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3373         /* lvds has its own version of prepare see intel_lvds_prepare */
3374         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3375 }
3376
3377 void intel_encoder_commit(struct drm_encoder *encoder)
3378 {
3379         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3380         struct drm_device *dev = encoder->dev;
3381         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3382         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3383
3384         /* lvds has its own version of commit see intel_lvds_commit */
3385         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3386
3387         if (HAS_PCH_CPT(dev))
3388                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3389 }
3390
3391 void intel_encoder_destroy(struct drm_encoder *encoder)
3392 {
3393         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3394
3395         drm_encoder_cleanup(encoder);
3396         kfree(intel_encoder);
3397 }
3398
3399 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3400                                   struct drm_display_mode *mode,
3401                                   struct drm_display_mode *adjusted_mode)
3402 {
3403         struct drm_device *dev = crtc->dev;
3404
3405         if (HAS_PCH_SPLIT(dev)) {
3406                 /* FDI link clock is fixed at 2.7G */
3407                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3408                         return false;
3409         }
3410
3411         /* XXX some encoders set the crtcinfo, others don't.
3412          * Obviously we need some form of conflict resolution here...
3413          */
3414         if (adjusted_mode->crtc_htotal == 0)
3415                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3416
3417         return true;
3418 }
3419
3420 static int i945_get_display_clock_speed(struct drm_device *dev)
3421 {
3422         return 400000;
3423 }
3424
3425 static int i915_get_display_clock_speed(struct drm_device *dev)
3426 {
3427         return 333000;
3428 }
3429
3430 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3431 {
3432         return 200000;
3433 }
3434
3435 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3436 {
3437         u16 gcfgc = 0;
3438
3439         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3440
3441         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3442                 return 133000;
3443         else {
3444                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3445                 case GC_DISPLAY_CLOCK_333_MHZ:
3446                         return 333000;
3447                 default:
3448                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3449                         return 190000;
3450                 }
3451         }
3452 }
3453
3454 static int i865_get_display_clock_speed(struct drm_device *dev)
3455 {
3456         return 266000;
3457 }
3458
3459 static int i855_get_display_clock_speed(struct drm_device *dev)
3460 {
3461         u16 hpllcc = 0;
3462         /* Assume that the hardware is in the high speed state.  This
3463          * should be the default.
3464          */
3465         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3466         case GC_CLOCK_133_200:
3467         case GC_CLOCK_100_200:
3468                 return 200000;
3469         case GC_CLOCK_166_250:
3470                 return 250000;
3471         case GC_CLOCK_100_133:
3472                 return 133000;
3473         }
3474
3475         /* Shouldn't happen */
3476         return 0;
3477 }
3478
3479 static int i830_get_display_clock_speed(struct drm_device *dev)
3480 {
3481         return 133000;
3482 }
3483
3484 struct fdi_m_n {
3485         u32        tu;
3486         u32        gmch_m;
3487         u32        gmch_n;
3488         u32        link_m;
3489         u32        link_n;
3490 };
3491
3492 static void
3493 fdi_reduce_ratio(u32 *num, u32 *den)
3494 {
3495         while (*num > 0xffffff || *den > 0xffffff) {
3496                 *num >>= 1;
3497                 *den >>= 1;
3498         }
3499 }
3500
3501 static void
3502 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3503                      int link_clock, struct fdi_m_n *m_n)
3504 {
3505         m_n->tu = 64; /* default size */
3506
3507         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3508         m_n->gmch_m = bits_per_pixel * pixel_clock;
3509         m_n->gmch_n = link_clock * nlanes * 8;
3510         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3511
3512         m_n->link_m = pixel_clock;
3513         m_n->link_n = link_clock;
3514         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3515 }
3516
3517
3518 struct intel_watermark_params {
3519         unsigned long fifo_size;
3520         unsigned long max_wm;
3521         unsigned long default_wm;
3522         unsigned long guard_size;
3523         unsigned long cacheline_size;
3524 };
3525
3526 /* Pineview has different values for various configs */
3527 static const struct intel_watermark_params pineview_display_wm = {
3528         PINEVIEW_DISPLAY_FIFO,
3529         PINEVIEW_MAX_WM,
3530         PINEVIEW_DFT_WM,
3531         PINEVIEW_GUARD_WM,
3532         PINEVIEW_FIFO_LINE_SIZE
3533 };
3534 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3535         PINEVIEW_DISPLAY_FIFO,
3536         PINEVIEW_MAX_WM,
3537         PINEVIEW_DFT_HPLLOFF_WM,
3538         PINEVIEW_GUARD_WM,
3539         PINEVIEW_FIFO_LINE_SIZE
3540 };
3541 static const struct intel_watermark_params pineview_cursor_wm = {
3542         PINEVIEW_CURSOR_FIFO,
3543         PINEVIEW_CURSOR_MAX_WM,
3544         PINEVIEW_CURSOR_DFT_WM,
3545         PINEVIEW_CURSOR_GUARD_WM,
3546         PINEVIEW_FIFO_LINE_SIZE,
3547 };
3548 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3549         PINEVIEW_CURSOR_FIFO,
3550         PINEVIEW_CURSOR_MAX_WM,
3551         PINEVIEW_CURSOR_DFT_WM,
3552         PINEVIEW_CURSOR_GUARD_WM,
3553         PINEVIEW_FIFO_LINE_SIZE
3554 };
3555 static const struct intel_watermark_params g4x_wm_info = {
3556         G4X_FIFO_SIZE,
3557         G4X_MAX_WM,
3558         G4X_MAX_WM,
3559         2,
3560         G4X_FIFO_LINE_SIZE,
3561 };
3562 static const struct intel_watermark_params g4x_cursor_wm_info = {
3563         I965_CURSOR_FIFO,
3564         I965_CURSOR_MAX_WM,
3565         I965_CURSOR_DFT_WM,
3566         2,
3567         G4X_FIFO_LINE_SIZE,
3568 };
3569 static const struct intel_watermark_params i965_cursor_wm_info = {
3570         I965_CURSOR_FIFO,
3571         I965_CURSOR_MAX_WM,
3572         I965_CURSOR_DFT_WM,
3573         2,
3574         I915_FIFO_LINE_SIZE,
3575 };
3576 static const struct intel_watermark_params i945_wm_info = {
3577         I945_FIFO_SIZE,
3578         I915_MAX_WM,
3579         1,
3580         2,
3581         I915_FIFO_LINE_SIZE
3582 };
3583 static const struct intel_watermark_params i915_wm_info = {
3584         I915_FIFO_SIZE,
3585         I915_MAX_WM,
3586         1,
3587         2,
3588         I915_FIFO_LINE_SIZE
3589 };
3590 static const struct intel_watermark_params i855_wm_info = {
3591         I855GM_FIFO_SIZE,
3592         I915_MAX_WM,
3593         1,
3594         2,
3595         I830_FIFO_LINE_SIZE
3596 };
3597 static const struct intel_watermark_params i830_wm_info = {
3598         I830_FIFO_SIZE,
3599         I915_MAX_WM,
3600         1,
3601         2,
3602         I830_FIFO_LINE_SIZE
3603 };
3604
3605 static const struct intel_watermark_params ironlake_display_wm_info = {
3606         ILK_DISPLAY_FIFO,
3607         ILK_DISPLAY_MAXWM,
3608         ILK_DISPLAY_DFTWM,
3609         2,
3610         ILK_FIFO_LINE_SIZE
3611 };
3612 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3613         ILK_CURSOR_FIFO,
3614         ILK_CURSOR_MAXWM,
3615         ILK_CURSOR_DFTWM,
3616         2,
3617         ILK_FIFO_LINE_SIZE
3618 };
3619 static const struct intel_watermark_params ironlake_display_srwm_info = {
3620         ILK_DISPLAY_SR_FIFO,
3621         ILK_DISPLAY_MAX_SRWM,
3622         ILK_DISPLAY_DFT_SRWM,
3623         2,
3624         ILK_FIFO_LINE_SIZE
3625 };
3626 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3627         ILK_CURSOR_SR_FIFO,
3628         ILK_CURSOR_MAX_SRWM,
3629         ILK_CURSOR_DFT_SRWM,
3630         2,
3631         ILK_FIFO_LINE_SIZE
3632 };
3633
3634 static const struct intel_watermark_params sandybridge_display_wm_info = {
3635         SNB_DISPLAY_FIFO,
3636         SNB_DISPLAY_MAXWM,
3637         SNB_DISPLAY_DFTWM,
3638         2,
3639         SNB_FIFO_LINE_SIZE
3640 };
3641 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3642         SNB_CURSOR_FIFO,
3643         SNB_CURSOR_MAXWM,
3644         SNB_CURSOR_DFTWM,
3645         2,
3646         SNB_FIFO_LINE_SIZE
3647 };
3648 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3649         SNB_DISPLAY_SR_FIFO,
3650         SNB_DISPLAY_MAX_SRWM,
3651         SNB_DISPLAY_DFT_SRWM,
3652         2,
3653         SNB_FIFO_LINE_SIZE
3654 };
3655 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3656         SNB_CURSOR_SR_FIFO,
3657         SNB_CURSOR_MAX_SRWM,
3658         SNB_CURSOR_DFT_SRWM,
3659         2,
3660         SNB_FIFO_LINE_SIZE
3661 };
3662
3663
3664 /**
3665  * intel_calculate_wm - calculate watermark level
3666  * @clock_in_khz: pixel clock
3667  * @wm: chip FIFO params
3668  * @pixel_size: display pixel size
3669  * @latency_ns: memory latency for the platform
3670  *
3671  * Calculate the watermark level (the level at which the display plane will
3672  * start fetching from memory again).  Each chip has a different display
3673  * FIFO size and allocation, so the caller needs to figure that out and pass
3674  * in the correct intel_watermark_params structure.
3675  *
3676  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3677  * on the pixel size.  When it reaches the watermark level, it'll start
3678  * fetching FIFO line sized based chunks from memory until the FIFO fills
3679  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3680  * will occur, and a display engine hang could result.
3681  */
3682 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3683                                         const struct intel_watermark_params *wm,
3684                                         int fifo_size,
3685                                         int pixel_size,
3686                                         unsigned long latency_ns)
3687 {
3688         long entries_required, wm_size;
3689
3690         /*
3691          * Note: we need to make sure we don't overflow for various clock &
3692          * latency values.
3693          * clocks go from a few thousand to several hundred thousand.
3694          * latency is usually a few thousand
3695          */
3696         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3697                 1000;
3698         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3699
3700         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3701
3702         wm_size = fifo_size - (entries_required + wm->guard_size);
3703
3704         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3705
3706         /* Don't promote wm_size to unsigned... */
3707         if (wm_size > (long)wm->max_wm)
3708                 wm_size = wm->max_wm;
3709         if (wm_size <= 0)
3710                 wm_size = wm->default_wm;
3711         return wm_size;
3712 }
3713
3714 struct cxsr_latency {
3715         int is_desktop;
3716         int is_ddr3;
3717         unsigned long fsb_freq;
3718         unsigned long mem_freq;
3719         unsigned long display_sr;
3720         unsigned long display_hpll_disable;
3721         unsigned long cursor_sr;
3722         unsigned long cursor_hpll_disable;
3723 };
3724
3725 static const struct cxsr_latency cxsr_latency_table[] = {
3726         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3727         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3728         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3729         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3730         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3731
3732         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3733         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3734         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3735         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3736         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3737
3738         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3739         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3740         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3741         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3742         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3743
3744         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3745         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3746         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3747         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3748         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3749
3750         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3751         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3752         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3753         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3754         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3755
3756         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3757         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3758         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3759         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3760         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3761 };
3762
3763 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3764                                                          int is_ddr3,
3765                                                          int fsb,
3766                                                          int mem)
3767 {
3768         const struct cxsr_latency *latency;
3769         int i;
3770
3771         if (fsb == 0 || mem == 0)
3772                 return NULL;
3773
3774         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3775                 latency = &cxsr_latency_table[i];
3776                 if (is_desktop == latency->is_desktop &&
3777                     is_ddr3 == latency->is_ddr3 &&
3778                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3779                         return latency;
3780         }
3781
3782         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3783
3784         return NULL;
3785 }
3786
3787 static void pineview_disable_cxsr(struct drm_device *dev)
3788 {
3789         struct drm_i915_private *dev_priv = dev->dev_private;
3790
3791         /* deactivate cxsr */
3792         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3793 }
3794
3795 /*
3796  * Latency for FIFO fetches is dependent on several factors:
3797  *   - memory configuration (speed, channels)
3798  *   - chipset
3799  *   - current MCH state
3800  * It can be fairly high in some situations, so here we assume a fairly
3801  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3802  * set this value too high, the FIFO will fetch frequently to stay full)
3803  * and power consumption (set it too low to save power and we might see
3804  * FIFO underruns and display "flicker").
3805  *
3806  * A value of 5us seems to be a good balance; safe for very low end
3807  * platforms but not overly aggressive on lower latency configs.
3808  */
3809 static const int latency_ns = 5000;
3810
3811 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3812 {
3813         struct drm_i915_private *dev_priv = dev->dev_private;
3814         uint32_t dsparb = I915_READ(DSPARB);
3815         int size;
3816
3817         size = dsparb & 0x7f;
3818         if (plane)
3819                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3820
3821         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3822                       plane ? "B" : "A", size);
3823
3824         return size;
3825 }
3826
3827 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3828 {
3829         struct drm_i915_private *dev_priv = dev->dev_private;
3830         uint32_t dsparb = I915_READ(DSPARB);
3831         int size;
3832
3833         size = dsparb & 0x1ff;
3834         if (plane)
3835                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3836         size >>= 1; /* Convert to cachelines */
3837
3838         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3839                       plane ? "B" : "A", size);
3840
3841         return size;
3842 }
3843
3844 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3845 {
3846         struct drm_i915_private *dev_priv = dev->dev_private;
3847         uint32_t dsparb = I915_READ(DSPARB);
3848         int size;
3849
3850         size = dsparb & 0x7f;
3851         size >>= 2; /* Convert to cachelines */
3852
3853         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3854                       plane ? "B" : "A",
3855                       size);
3856
3857         return size;
3858 }
3859
3860 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3861 {
3862         struct drm_i915_private *dev_priv = dev->dev_private;
3863         uint32_t dsparb = I915_READ(DSPARB);
3864         int size;
3865
3866         size = dsparb & 0x7f;
3867         size >>= 1; /* Convert to cachelines */
3868
3869         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3870                       plane ? "B" : "A", size);
3871
3872         return size;
3873 }
3874
3875 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3876 {
3877         struct drm_crtc *crtc, *enabled = NULL;
3878
3879         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3880                 if (crtc->enabled && crtc->fb) {
3881                         if (enabled)
3882                                 return NULL;
3883                         enabled = crtc;
3884                 }
3885         }
3886
3887         return enabled;
3888 }
3889
3890 static void pineview_update_wm(struct drm_device *dev)
3891 {
3892         struct drm_i915_private *dev_priv = dev->dev_private;
3893         struct drm_crtc *crtc;
3894         const struct cxsr_latency *latency;
3895         u32 reg;
3896         unsigned long wm;
3897
3898         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3899                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3900         if (!latency) {
3901                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3902                 pineview_disable_cxsr(dev);
3903                 return;
3904         }
3905
3906         crtc = single_enabled_crtc(dev);
3907         if (crtc) {
3908                 int clock = crtc->mode.clock;
3909                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3910
3911                 /* Display SR */
3912                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3913                                         pineview_display_wm.fifo_size,
3914                                         pixel_size, latency->display_sr);
3915                 reg = I915_READ(DSPFW1);
3916                 reg &= ~DSPFW_SR_MASK;
3917                 reg |= wm << DSPFW_SR_SHIFT;
3918                 I915_WRITE(DSPFW1, reg);
3919                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3920
3921                 /* cursor SR */
3922                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3923                                         pineview_display_wm.fifo_size,
3924                                         pixel_size, latency->cursor_sr);
3925                 reg = I915_READ(DSPFW3);
3926                 reg &= ~DSPFW_CURSOR_SR_MASK;
3927                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3928                 I915_WRITE(DSPFW3, reg);
3929
3930                 /* Display HPLL off SR */
3931                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3932                                         pineview_display_hplloff_wm.fifo_size,
3933                                         pixel_size, latency->display_hpll_disable);
3934                 reg = I915_READ(DSPFW3);
3935                 reg &= ~DSPFW_HPLL_SR_MASK;
3936                 reg |= wm & DSPFW_HPLL_SR_MASK;
3937                 I915_WRITE(DSPFW3, reg);
3938
3939                 /* cursor HPLL off SR */
3940                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3941                                         pineview_display_hplloff_wm.fifo_size,
3942                                         pixel_size, latency->cursor_hpll_disable);
3943                 reg = I915_READ(DSPFW3);
3944                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3945                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3946                 I915_WRITE(DSPFW3, reg);
3947                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3948
3949                 /* activate cxsr */
3950                 I915_WRITE(DSPFW3,
3951                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3952                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3953         } else {
3954                 pineview_disable_cxsr(dev);
3955                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3956         }
3957 }
3958
3959 static bool g4x_compute_wm0(struct drm_device *dev,
3960                             int plane,
3961                             const struct intel_watermark_params *display,
3962                             int display_latency_ns,
3963                             const struct intel_watermark_params *cursor,
3964                             int cursor_latency_ns,
3965                             int *plane_wm,
3966                             int *cursor_wm)
3967 {
3968         struct drm_crtc *crtc;
3969         int htotal, hdisplay, clock, pixel_size;
3970         int line_time_us, line_count;
3971         int entries, tlb_miss;
3972
3973         crtc = intel_get_crtc_for_plane(dev, plane);
3974         if (crtc->fb == NULL || !crtc->enabled) {
3975                 *cursor_wm = cursor->guard_size;
3976                 *plane_wm = display->guard_size;
3977                 return false;
3978         }
3979
3980         htotal = crtc->mode.htotal;
3981         hdisplay = crtc->mode.hdisplay;
3982         clock = crtc->mode.clock;
3983         pixel_size = crtc->fb->bits_per_pixel / 8;
3984
3985         /* Use the small buffer method to calculate plane watermark */
3986         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3987         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3988         if (tlb_miss > 0)
3989                 entries += tlb_miss;
3990         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3991         *plane_wm = entries + display->guard_size;
3992         if (*plane_wm > (int)display->max_wm)
3993                 *plane_wm = display->max_wm;
3994
3995         /* Use the large buffer method to calculate cursor watermark */
3996         line_time_us = ((htotal * 1000) / clock);
3997         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3998         entries = line_count * 64 * pixel_size;
3999         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4000         if (tlb_miss > 0)
4001                 entries += tlb_miss;
4002         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4003         *cursor_wm = entries + cursor->guard_size;
4004         if (*cursor_wm > (int)cursor->max_wm)
4005                 *cursor_wm = (int)cursor->max_wm;
4006
4007         return true;
4008 }
4009
4010 /*
4011  * Check the wm result.
4012  *
4013  * If any calculated watermark values is larger than the maximum value that
4014  * can be programmed into the associated watermark register, that watermark
4015  * must be disabled.
4016  */
4017 static bool g4x_check_srwm(struct drm_device *dev,
4018                            int display_wm, int cursor_wm,
4019                            const struct intel_watermark_params *display,
4020                            const struct intel_watermark_params *cursor)
4021 {
4022         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4023                       display_wm, cursor_wm);
4024
4025         if (display_wm > display->max_wm) {
4026                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4027                               display_wm, display->max_wm);
4028                 return false;
4029         }
4030
4031         if (cursor_wm > cursor->max_wm) {
4032                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4033                               cursor_wm, cursor->max_wm);
4034                 return false;
4035         }
4036
4037         if (!(display_wm || cursor_wm)) {
4038                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4039                 return false;
4040         }
4041
4042         return true;
4043 }
4044
4045 static bool g4x_compute_srwm(struct drm_device *dev,
4046                              int plane,
4047                              int latency_ns,
4048                              const struct intel_watermark_params *display,
4049                              const struct intel_watermark_params *cursor,
4050                              int *display_wm, int *cursor_wm)
4051 {
4052         struct drm_crtc *crtc;
4053         int hdisplay, htotal, pixel_size, clock;
4054         unsigned long line_time_us;
4055         int line_count, line_size;
4056         int small, large;
4057         int entries;
4058
4059         if (!latency_ns) {
4060                 *display_wm = *cursor_wm = 0;
4061                 return false;
4062         }
4063
4064         crtc = intel_get_crtc_for_plane(dev, plane);
4065         hdisplay = crtc->mode.hdisplay;
4066         htotal = crtc->mode.htotal;
4067         clock = crtc->mode.clock;
4068         pixel_size = crtc->fb->bits_per_pixel / 8;
4069
4070         line_time_us = (htotal * 1000) / clock;
4071         line_count = (latency_ns / line_time_us + 1000) / 1000;
4072         line_size = hdisplay * pixel_size;
4073
4074         /* Use the minimum of the small and large buffer method for primary */
4075         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4076         large = line_count * line_size;
4077
4078         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4079         *display_wm = entries + display->guard_size;
4080
4081         /* calculate the self-refresh watermark for display cursor */
4082         entries = line_count * pixel_size * 64;
4083         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4084         *cursor_wm = entries + cursor->guard_size;
4085
4086         return g4x_check_srwm(dev,
4087                               *display_wm, *cursor_wm,
4088                               display, cursor);
4089 }
4090
4091 #define single_plane_enabled(mask) is_power_of_2(mask)
4092
4093 static void g4x_update_wm(struct drm_device *dev)
4094 {
4095         static const int sr_latency_ns = 12000;
4096         struct drm_i915_private *dev_priv = dev->dev_private;
4097         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4098         int plane_sr, cursor_sr;
4099         unsigned int enabled = 0;
4100
4101         if (g4x_compute_wm0(dev, 0,
4102                             &g4x_wm_info, latency_ns,
4103                             &g4x_cursor_wm_info, latency_ns,
4104                             &planea_wm, &cursora_wm))
4105                 enabled |= 1;
4106
4107         if (g4x_compute_wm0(dev, 1,
4108                             &g4x_wm_info, latency_ns,
4109                             &g4x_cursor_wm_info, latency_ns,
4110                             &planeb_wm, &cursorb_wm))
4111                 enabled |= 2;
4112
4113         plane_sr = cursor_sr = 0;
4114         if (single_plane_enabled(enabled) &&
4115             g4x_compute_srwm(dev, ffs(enabled) - 1,
4116                              sr_latency_ns,
4117                              &g4x_wm_info,
4118                              &g4x_cursor_wm_info,
4119                              &plane_sr, &cursor_sr))
4120                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4121         else
4122                 I915_WRITE(FW_BLC_SELF,
4123                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4124
4125         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4126                       planea_wm, cursora_wm,
4127                       planeb_wm, cursorb_wm,
4128                       plane_sr, cursor_sr);
4129
4130         I915_WRITE(DSPFW1,
4131                    (plane_sr << DSPFW_SR_SHIFT) |
4132                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4133                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4134                    planea_wm);
4135         I915_WRITE(DSPFW2,
4136                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4137                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4138         /* HPLL off in SR has some issues on G4x... disable it */
4139         I915_WRITE(DSPFW3,
4140                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4141                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4142 }
4143
4144 static void i965_update_wm(struct drm_device *dev)
4145 {
4146         struct drm_i915_private *dev_priv = dev->dev_private;
4147         struct drm_crtc *crtc;
4148         int srwm = 1;
4149         int cursor_sr = 16;
4150
4151         /* Calc sr entries for one plane configs */
4152         crtc = single_enabled_crtc(dev);
4153         if (crtc) {
4154                 /* self-refresh has much higher latency */
4155                 static const int sr_latency_ns = 12000;
4156                 int clock = crtc->mode.clock;
4157                 int htotal = crtc->mode.htotal;
4158                 int hdisplay = crtc->mode.hdisplay;
4159                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4160                 unsigned long line_time_us;
4161                 int entries;
4162
4163                 line_time_us = ((htotal * 1000) / clock);
4164
4165                 /* Use ns/us then divide to preserve precision */
4166                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4167                         pixel_size * hdisplay;
4168                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4169                 srwm = I965_FIFO_SIZE - entries;
4170                 if (srwm < 0)
4171                         srwm = 1;
4172                 srwm &= 0x1ff;
4173                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4174                               entries, srwm);
4175
4176                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4177                         pixel_size * 64;
4178                 entries = DIV_ROUND_UP(entries,
4179                                           i965_cursor_wm_info.cacheline_size);
4180                 cursor_sr = i965_cursor_wm_info.fifo_size -
4181                         (entries + i965_cursor_wm_info.guard_size);
4182
4183                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4184                         cursor_sr = i965_cursor_wm_info.max_wm;
4185
4186                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4187                               "cursor %d\n", srwm, cursor_sr);
4188
4189                 if (IS_CRESTLINE(dev))
4190                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4191         } else {
4192                 /* Turn off self refresh if both pipes are enabled */
4193                 if (IS_CRESTLINE(dev))
4194                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4195                                    & ~FW_BLC_SELF_EN);
4196         }
4197
4198         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4199                       srwm);
4200
4201         /* 965 has limitations... */
4202         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4203                    (8 << 16) | (8 << 8) | (8 << 0));
4204         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4205         /* update cursor SR watermark */
4206         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4207 }
4208
4209 static void i9xx_update_wm(struct drm_device *dev)
4210 {
4211         struct drm_i915_private *dev_priv = dev->dev_private;
4212         const struct intel_watermark_params *wm_info;
4213         uint32_t fwater_lo;
4214         uint32_t fwater_hi;
4215         int cwm, srwm = 1;
4216         int fifo_size;
4217         int planea_wm, planeb_wm;
4218         struct drm_crtc *crtc, *enabled = NULL;
4219
4220         if (IS_I945GM(dev))
4221                 wm_info = &i945_wm_info;
4222         else if (!IS_GEN2(dev))
4223                 wm_info = &i915_wm_info;
4224         else
4225                 wm_info = &i855_wm_info;
4226
4227         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4228         crtc = intel_get_crtc_for_plane(dev, 0);
4229         if (crtc->enabled && crtc->fb) {
4230                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4231                                                wm_info, fifo_size,
4232                                                crtc->fb->bits_per_pixel / 8,
4233                                                latency_ns);
4234                 enabled = crtc;
4235         } else
4236                 planea_wm = fifo_size - wm_info->guard_size;
4237
4238         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4239         crtc = intel_get_crtc_for_plane(dev, 1);
4240         if (crtc->enabled && crtc->fb) {
4241                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4242                                                wm_info, fifo_size,
4243                                                crtc->fb->bits_per_pixel / 8,
4244                                                latency_ns);
4245                 if (enabled == NULL)
4246                         enabled = crtc;
4247                 else
4248                         enabled = NULL;
4249         } else
4250                 planeb_wm = fifo_size - wm_info->guard_size;
4251
4252         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4253
4254         /*
4255          * Overlay gets an aggressive default since video jitter is bad.
4256          */
4257         cwm = 2;
4258
4259         /* Play safe and disable self-refresh before adjusting watermarks. */
4260         if (IS_I945G(dev) || IS_I945GM(dev))
4261                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4262         else if (IS_I915GM(dev))
4263                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4264
4265         /* Calc sr entries for one plane configs */
4266         if (HAS_FW_BLC(dev) && enabled) {
4267                 /* self-refresh has much higher latency */
4268                 static const int sr_latency_ns = 6000;
4269                 int clock = enabled->mode.clock;
4270                 int htotal = enabled->mode.htotal;
4271                 int hdisplay = enabled->mode.hdisplay;
4272                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4273                 unsigned long line_time_us;
4274                 int entries;
4275
4276                 line_time_us = (htotal * 1000) / clock;
4277
4278                 /* Use ns/us then divide to preserve precision */
4279                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4280                         pixel_size * hdisplay;
4281                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4282                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4283                 srwm = wm_info->fifo_size - entries;
4284                 if (srwm < 0)
4285                         srwm = 1;
4286
4287                 if (IS_I945G(dev) || IS_I945GM(dev))
4288                         I915_WRITE(FW_BLC_SELF,
4289                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4290                 else if (IS_I915GM(dev))
4291                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4292         }
4293
4294         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4295                       planea_wm, planeb_wm, cwm, srwm);
4296
4297         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4298         fwater_hi = (cwm & 0x1f);
4299
4300         /* Set request length to 8 cachelines per fetch */
4301         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4302         fwater_hi = fwater_hi | (1 << 8);
4303
4304         I915_WRITE(FW_BLC, fwater_lo);
4305         I915_WRITE(FW_BLC2, fwater_hi);
4306
4307         if (HAS_FW_BLC(dev)) {
4308                 if (enabled) {
4309                         if (IS_I945G(dev) || IS_I945GM(dev))
4310                                 I915_WRITE(FW_BLC_SELF,
4311                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4312                         else if (IS_I915GM(dev))
4313                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4314                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4315                 } else
4316                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4317         }
4318 }
4319
4320 static void i830_update_wm(struct drm_device *dev)
4321 {
4322         struct drm_i915_private *dev_priv = dev->dev_private;
4323         struct drm_crtc *crtc;
4324         uint32_t fwater_lo;
4325         int planea_wm;
4326
4327         crtc = single_enabled_crtc(dev);
4328         if (crtc == NULL)
4329                 return;
4330
4331         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4332                                        dev_priv->display.get_fifo_size(dev, 0),
4333                                        crtc->fb->bits_per_pixel / 8,
4334                                        latency_ns);
4335         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4336         fwater_lo |= (3<<8) | planea_wm;
4337
4338         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4339
4340         I915_WRITE(FW_BLC, fwater_lo);
4341 }
4342
4343 #define ILK_LP0_PLANE_LATENCY           700
4344 #define ILK_LP0_CURSOR_LATENCY          1300
4345
4346 /*
4347  * Check the wm result.
4348  *
4349  * If any calculated watermark values is larger than the maximum value that
4350  * can be programmed into the associated watermark register, that watermark
4351  * must be disabled.
4352  */
4353 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4354                                 int fbc_wm, int display_wm, int cursor_wm,
4355                                 const struct intel_watermark_params *display,
4356                                 const struct intel_watermark_params *cursor)
4357 {
4358         struct drm_i915_private *dev_priv = dev->dev_private;
4359
4360         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4361                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4362
4363         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4364                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4365                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4366
4367                 /* fbc has it's own way to disable FBC WM */
4368                 I915_WRITE(DISP_ARB_CTL,
4369                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4370                 return false;
4371         }
4372
4373         if (display_wm > display->max_wm) {
4374                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4375                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4376                 return false;
4377         }
4378
4379         if (cursor_wm > cursor->max_wm) {
4380                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4381                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4382                 return false;
4383         }
4384
4385         if (!(fbc_wm || display_wm || cursor_wm)) {
4386                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4387                 return false;
4388         }
4389
4390         return true;
4391 }
4392
4393 /*
4394  * Compute watermark values of WM[1-3],
4395  */
4396 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4397                                   int latency_ns,
4398                                   const struct intel_watermark_params *display,
4399                                   const struct intel_watermark_params *cursor,
4400                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4401 {
4402         struct drm_crtc *crtc;
4403         unsigned long line_time_us;
4404         int hdisplay, htotal, pixel_size, clock;
4405         int line_count, line_size;
4406         int small, large;
4407         int entries;
4408
4409         if (!latency_ns) {
4410                 *fbc_wm = *display_wm = *cursor_wm = 0;
4411                 return false;
4412         }
4413
4414         crtc = intel_get_crtc_for_plane(dev, plane);
4415         hdisplay = crtc->mode.hdisplay;
4416         htotal = crtc->mode.htotal;
4417         clock = crtc->mode.clock;
4418         pixel_size = crtc->fb->bits_per_pixel / 8;
4419
4420         line_time_us = (htotal * 1000) / clock;
4421         line_count = (latency_ns / line_time_us + 1000) / 1000;
4422         line_size = hdisplay * pixel_size;
4423
4424         /* Use the minimum of the small and large buffer method for primary */
4425         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4426         large = line_count * line_size;
4427
4428         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4429         *display_wm = entries + display->guard_size;
4430
4431         /*
4432          * Spec says:
4433          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4434          */
4435         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4436
4437         /* calculate the self-refresh watermark for display cursor */
4438         entries = line_count * pixel_size * 64;
4439         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4440         *cursor_wm = entries + cursor->guard_size;
4441
4442         return ironlake_check_srwm(dev, level,
4443                                    *fbc_wm, *display_wm, *cursor_wm,
4444                                    display, cursor);
4445 }
4446
4447 static void ironlake_update_wm(struct drm_device *dev)
4448 {
4449         struct drm_i915_private *dev_priv = dev->dev_private;
4450         int fbc_wm, plane_wm, cursor_wm;
4451         unsigned int enabled;
4452
4453         enabled = 0;
4454         if (g4x_compute_wm0(dev, 0,
4455                             &ironlake_display_wm_info,
4456                             ILK_LP0_PLANE_LATENCY,
4457                             &ironlake_cursor_wm_info,
4458                             ILK_LP0_CURSOR_LATENCY,
4459                             &plane_wm, &cursor_wm)) {
4460                 I915_WRITE(WM0_PIPEA_ILK,
4461                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4462                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4463                               " plane %d, " "cursor: %d\n",
4464                               plane_wm, cursor_wm);
4465                 enabled |= 1;
4466         }
4467
4468         if (g4x_compute_wm0(dev, 1,
4469                             &ironlake_display_wm_info,
4470                             ILK_LP0_PLANE_LATENCY,
4471                             &ironlake_cursor_wm_info,
4472                             ILK_LP0_CURSOR_LATENCY,
4473                             &plane_wm, &cursor_wm)) {
4474                 I915_WRITE(WM0_PIPEB_ILK,
4475                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4476                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4477                               " plane %d, cursor: %d\n",
4478                               plane_wm, cursor_wm);
4479                 enabled |= 2;
4480         }
4481
4482         /*
4483          * Calculate and update the self-refresh watermark only when one
4484          * display plane is used.
4485          */
4486         I915_WRITE(WM3_LP_ILK, 0);
4487         I915_WRITE(WM2_LP_ILK, 0);
4488         I915_WRITE(WM1_LP_ILK, 0);
4489
4490         if (!single_plane_enabled(enabled))
4491                 return;
4492         enabled = ffs(enabled) - 1;
4493
4494         /* WM1 */
4495         if (!ironlake_compute_srwm(dev, 1, enabled,
4496                                    ILK_READ_WM1_LATENCY() * 500,
4497                                    &ironlake_display_srwm_info,
4498                                    &ironlake_cursor_srwm_info,
4499                                    &fbc_wm, &plane_wm, &cursor_wm))
4500                 return;
4501
4502         I915_WRITE(WM1_LP_ILK,
4503                    WM1_LP_SR_EN |
4504                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4505                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4506                    (plane_wm << WM1_LP_SR_SHIFT) |
4507                    cursor_wm);
4508
4509         /* WM2 */
4510         if (!ironlake_compute_srwm(dev, 2, enabled,
4511                                    ILK_READ_WM2_LATENCY() * 500,
4512                                    &ironlake_display_srwm_info,
4513                                    &ironlake_cursor_srwm_info,
4514                                    &fbc_wm, &plane_wm, &cursor_wm))
4515                 return;
4516
4517         I915_WRITE(WM2_LP_ILK,
4518                    WM2_LP_EN |
4519                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4520                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4521                    (plane_wm << WM1_LP_SR_SHIFT) |
4522                    cursor_wm);
4523
4524         /*
4525          * WM3 is unsupported on ILK, probably because we don't have latency
4526          * data for that power state
4527          */
4528 }
4529
4530 static void sandybridge_update_wm(struct drm_device *dev)
4531 {
4532         struct drm_i915_private *dev_priv = dev->dev_private;
4533         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4534         int fbc_wm, plane_wm, cursor_wm;
4535         unsigned int enabled;
4536
4537         enabled = 0;
4538         if (g4x_compute_wm0(dev, 0,
4539                             &sandybridge_display_wm_info, latency,
4540                             &sandybridge_cursor_wm_info, latency,
4541                             &plane_wm, &cursor_wm)) {
4542                 I915_WRITE(WM0_PIPEA_ILK,
4543                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4544                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4545                               " plane %d, " "cursor: %d\n",
4546                               plane_wm, cursor_wm);
4547                 enabled |= 1;
4548         }
4549
4550         if (g4x_compute_wm0(dev, 1,
4551                             &sandybridge_display_wm_info, latency,
4552                             &sandybridge_cursor_wm_info, latency,
4553                             &plane_wm, &cursor_wm)) {
4554                 I915_WRITE(WM0_PIPEB_ILK,
4555                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4556                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4557                               " plane %d, cursor: %d\n",
4558                               plane_wm, cursor_wm);
4559                 enabled |= 2;
4560         }
4561
4562         /* IVB has 3 pipes */
4563         if (IS_IVYBRIDGE(dev) &&
4564             g4x_compute_wm0(dev, 2,
4565                             &sandybridge_display_wm_info, latency,
4566                             &sandybridge_cursor_wm_info, latency,
4567                             &plane_wm, &cursor_wm)) {
4568                 I915_WRITE(WM0_PIPEC_IVB,
4569                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4570                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4571                               " plane %d, cursor: %d\n",
4572                               plane_wm, cursor_wm);
4573                 enabled |= 3;
4574         }
4575
4576         /*
4577          * Calculate and update the self-refresh watermark only when one
4578          * display plane is used.
4579          *
4580          * SNB support 3 levels of watermark.
4581          *
4582          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4583          * and disabled in the descending order
4584          *
4585          */
4586         I915_WRITE(WM3_LP_ILK, 0);
4587         I915_WRITE(WM2_LP_ILK, 0);
4588         I915_WRITE(WM1_LP_ILK, 0);
4589
4590         if (!single_plane_enabled(enabled))
4591                 return;
4592         enabled = ffs(enabled) - 1;
4593
4594         /* WM1 */
4595         if (!ironlake_compute_srwm(dev, 1, enabled,
4596                                    SNB_READ_WM1_LATENCY() * 500,
4597                                    &sandybridge_display_srwm_info,
4598                                    &sandybridge_cursor_srwm_info,
4599                                    &fbc_wm, &plane_wm, &cursor_wm))
4600                 return;
4601
4602         I915_WRITE(WM1_LP_ILK,
4603                    WM1_LP_SR_EN |
4604                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4605                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4606                    (plane_wm << WM1_LP_SR_SHIFT) |
4607                    cursor_wm);
4608
4609         /* WM2 */
4610         if (!ironlake_compute_srwm(dev, 2, enabled,
4611                                    SNB_READ_WM2_LATENCY() * 500,
4612                                    &sandybridge_display_srwm_info,
4613                                    &sandybridge_cursor_srwm_info,
4614                                    &fbc_wm, &plane_wm, &cursor_wm))
4615                 return;
4616
4617         I915_WRITE(WM2_LP_ILK,
4618                    WM2_LP_EN |
4619                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4620                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4621                    (plane_wm << WM1_LP_SR_SHIFT) |
4622                    cursor_wm);
4623
4624         /* WM3 */
4625         if (!ironlake_compute_srwm(dev, 3, enabled,
4626                                    SNB_READ_WM3_LATENCY() * 500,
4627                                    &sandybridge_display_srwm_info,
4628                                    &sandybridge_cursor_srwm_info,
4629                                    &fbc_wm, &plane_wm, &cursor_wm))
4630                 return;
4631
4632         I915_WRITE(WM3_LP_ILK,
4633                    WM3_LP_EN |
4634                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4635                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4636                    (plane_wm << WM1_LP_SR_SHIFT) |
4637                    cursor_wm);
4638 }
4639
4640 /**
4641  * intel_update_watermarks - update FIFO watermark values based on current modes
4642  *
4643  * Calculate watermark values for the various WM regs based on current mode
4644  * and plane configuration.
4645  *
4646  * There are several cases to deal with here:
4647  *   - normal (i.e. non-self-refresh)
4648  *   - self-refresh (SR) mode
4649  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4650  *   - lines are small relative to FIFO size (buffer can hold more than 2
4651  *     lines), so need to account for TLB latency
4652  *
4653  *   The normal calculation is:
4654  *     watermark = dotclock * bytes per pixel * latency
4655  *   where latency is platform & configuration dependent (we assume pessimal
4656  *   values here).
4657  *
4658  *   The SR calculation is:
4659  *     watermark = (trunc(latency/line time)+1) * surface width *
4660  *       bytes per pixel
4661  *   where
4662  *     line time = htotal / dotclock
4663  *     surface width = hdisplay for normal plane and 64 for cursor
4664  *   and latency is assumed to be high, as above.
4665  *
4666  * The final value programmed to the register should always be rounded up,
4667  * and include an extra 2 entries to account for clock crossings.
4668  *
4669  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4670  * to set the non-SR watermarks to 8.
4671  */
4672 static void intel_update_watermarks(struct drm_device *dev)
4673 {
4674         struct drm_i915_private *dev_priv = dev->dev_private;
4675
4676         if (dev_priv->display.update_wm)
4677                 dev_priv->display.update_wm(dev);
4678 }
4679
4680 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4681 {
4682         if (i915_panel_use_ssc >= 0)
4683                 return i915_panel_use_ssc != 0;
4684         return dev_priv->lvds_use_ssc
4685                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4686 }
4687
4688 /**
4689  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4690  * @crtc: CRTC structure
4691  * @mode: requested mode
4692  *
4693  * A pipe may be connected to one or more outputs.  Based on the depth of the
4694  * attached framebuffer, choose a good color depth to use on the pipe.
4695  *
4696  * If possible, match the pipe depth to the fb depth.  In some cases, this
4697  * isn't ideal, because the connected output supports a lesser or restricted
4698  * set of depths.  Resolve that here:
4699  *    LVDS typically supports only 6bpc, so clamp down in that case
4700  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4701  *    Displays may support a restricted set as well, check EDID and clamp as
4702  *      appropriate.
4703  *    DP may want to dither down to 6bpc to fit larger modes
4704  *
4705  * RETURNS:
4706  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4707  * true if they don't match).
4708  */
4709 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4710                                          unsigned int *pipe_bpp,
4711                                          struct drm_display_mode *mode)
4712 {
4713         struct drm_device *dev = crtc->dev;
4714         struct drm_i915_private *dev_priv = dev->dev_private;
4715         struct drm_encoder *encoder;
4716         struct drm_connector *connector;
4717         unsigned int display_bpc = UINT_MAX, bpc;
4718
4719         /* Walk the encoders & connectors on this crtc, get min bpc */
4720         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4721                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4722
4723                 if (encoder->crtc != crtc)
4724                         continue;
4725
4726                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4727                         unsigned int lvds_bpc;
4728
4729                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4730                             LVDS_A3_POWER_UP)
4731                                 lvds_bpc = 8;
4732                         else
4733                                 lvds_bpc = 6;
4734
4735                         if (lvds_bpc < display_bpc) {
4736                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4737                                 display_bpc = lvds_bpc;
4738                         }
4739                         continue;
4740                 }
4741
4742                 /* Not one of the known troublemakers, check the EDID */
4743                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4744                                     head) {
4745                         if (connector->encoder != encoder)
4746                                 continue;
4747
4748                         /* Don't use an invalid EDID bpc value */
4749                         if (connector->display_info.bpc &&
4750                             connector->display_info.bpc < display_bpc) {
4751                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4752                                 display_bpc = connector->display_info.bpc;
4753                         }
4754                 }
4755
4756                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4757                         /* Use VBT settings if we have an eDP panel */
4758                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4759
4760                         if (edp_bpc && edp_bpc < display_bpc) {
4761                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4762                                 display_bpc = edp_bpc;
4763                         }
4764                         continue;
4765                 }
4766
4767                 /*
4768                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4769                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4770                  */
4771                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4772                         if (display_bpc > 8 && display_bpc < 12) {
4773                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4774                                 display_bpc = 12;
4775                         } else {
4776                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4777                                 display_bpc = 8;
4778                         }
4779                 }
4780         }
4781
4782         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4783                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4784                 display_bpc = 6;
4785         }
4786
4787         /*
4788          * We could just drive the pipe at the highest bpc all the time and
4789          * enable dithering as needed, but that costs bandwidth.  So choose
4790          * the minimum value that expresses the full color range of the fb but
4791          * also stays within the max display bpc discovered above.
4792          */
4793
4794         switch (crtc->fb->depth) {
4795         case 8:
4796                 bpc = 8; /* since we go through a colormap */
4797                 break;
4798         case 15:
4799         case 16:
4800                 bpc = 6; /* min is 18bpp */
4801                 break;
4802         case 24:
4803                 bpc = 8;
4804                 break;
4805         case 30:
4806                 bpc = 10;
4807                 break;
4808         case 48:
4809                 bpc = 12;
4810                 break;
4811         default:
4812                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4813                 bpc = min((unsigned int)8, display_bpc);
4814                 break;
4815         }
4816
4817         display_bpc = min(display_bpc, bpc);
4818
4819         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4820                       bpc, display_bpc);
4821
4822         *pipe_bpp = display_bpc * 3;
4823
4824         return display_bpc != bpc;
4825 }
4826
4827 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4828                               struct drm_display_mode *mode,
4829                               struct drm_display_mode *adjusted_mode,
4830                               int x, int y,
4831                               struct drm_framebuffer *old_fb)
4832 {
4833         struct drm_device *dev = crtc->dev;
4834         struct drm_i915_private *dev_priv = dev->dev_private;
4835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4836         int pipe = intel_crtc->pipe;
4837         int plane = intel_crtc->plane;
4838         int refclk, num_connectors = 0;
4839         intel_clock_t clock, reduced_clock;
4840         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4841         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4842         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4843         struct drm_mode_config *mode_config = &dev->mode_config;
4844         struct intel_encoder *encoder;
4845         const intel_limit_t *limit;
4846         int ret;
4847         u32 temp;
4848         u32 lvds_sync = 0;
4849
4850         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4851                 if (encoder->base.crtc != crtc)
4852                         continue;
4853
4854                 switch (encoder->type) {
4855                 case INTEL_OUTPUT_LVDS:
4856                         is_lvds = true;
4857                         break;
4858                 case INTEL_OUTPUT_SDVO:
4859                 case INTEL_OUTPUT_HDMI:
4860                         is_sdvo = true;
4861                         if (encoder->needs_tv_clock)
4862                                 is_tv = true;
4863                         break;
4864                 case INTEL_OUTPUT_DVO:
4865                         is_dvo = true;
4866                         break;
4867                 case INTEL_OUTPUT_TVOUT:
4868                         is_tv = true;
4869                         break;
4870                 case INTEL_OUTPUT_ANALOG:
4871                         is_crt = true;
4872                         break;
4873                 case INTEL_OUTPUT_DISPLAYPORT:
4874                         is_dp = true;
4875                         break;
4876                 }
4877
4878                 num_connectors++;
4879         }
4880
4881         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4882                 refclk = dev_priv->lvds_ssc_freq * 1000;
4883                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4884                               refclk / 1000);
4885         } else if (!IS_GEN2(dev)) {
4886                 refclk = 96000;
4887         } else {
4888                 refclk = 48000;
4889         }
4890
4891         /*
4892          * Returns a set of divisors for the desired target clock with the given
4893          * refclk, or FALSE.  The returned values represent the clock equation:
4894          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4895          */
4896         limit = intel_limit(crtc, refclk);
4897         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4898         if (!ok) {
4899                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4900                 return -EINVAL;
4901         }
4902
4903         /* Ensure that the cursor is valid for the new mode before changing... */
4904         intel_crtc_update_cursor(crtc, true);
4905
4906         if (is_lvds && dev_priv->lvds_downclock_avail) {
4907                 has_reduced_clock = limit->find_pll(limit, crtc,
4908                                                     dev_priv->lvds_downclock,
4909                                                     refclk,
4910                                                     &reduced_clock);
4911                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4912                         /*
4913                          * If the different P is found, it means that we can't
4914                          * switch the display clock by using the FP0/FP1.
4915                          * In such case we will disable the LVDS downclock
4916                          * feature.
4917                          */
4918                         DRM_DEBUG_KMS("Different P is found for "
4919                                       "LVDS clock/downclock\n");
4920                         has_reduced_clock = 0;
4921                 }
4922         }
4923         /* SDVO TV has fixed PLL values depend on its clock range,
4924            this mirrors vbios setting. */
4925         if (is_sdvo && is_tv) {
4926                 if (adjusted_mode->clock >= 100000
4927                     && adjusted_mode->clock < 140500) {
4928                         clock.p1 = 2;
4929                         clock.p2 = 10;
4930                         clock.n = 3;
4931                         clock.m1 = 16;
4932                         clock.m2 = 8;
4933                 } else if (adjusted_mode->clock >= 140500
4934                            && adjusted_mode->clock <= 200000) {
4935                         clock.p1 = 1;
4936                         clock.p2 = 10;
4937                         clock.n = 6;
4938                         clock.m1 = 12;
4939                         clock.m2 = 8;
4940                 }
4941         }
4942
4943         if (IS_PINEVIEW(dev)) {
4944                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4945                 if (has_reduced_clock)
4946                         fp2 = (1 << reduced_clock.n) << 16 |
4947                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4948         } else {
4949                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4950                 if (has_reduced_clock)
4951                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4952                                 reduced_clock.m2;
4953         }
4954
4955         dpll = DPLL_VGA_MODE_DIS;
4956
4957         if (!IS_GEN2(dev)) {
4958                 if (is_lvds)
4959                         dpll |= DPLLB_MODE_LVDS;
4960                 else
4961                         dpll |= DPLLB_MODE_DAC_SERIAL;
4962                 if (is_sdvo) {
4963                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4964                         if (pixel_multiplier > 1) {
4965                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4966                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4967                         }
4968                         dpll |= DPLL_DVO_HIGH_SPEED;
4969                 }
4970                 if (is_dp)
4971                         dpll |= DPLL_DVO_HIGH_SPEED;
4972
4973                 /* compute bitmask from p1 value */
4974                 if (IS_PINEVIEW(dev))
4975                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4976                 else {
4977                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4978                         if (IS_G4X(dev) && has_reduced_clock)
4979                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4980                 }
4981                 switch (clock.p2) {
4982                 case 5:
4983                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4984                         break;
4985                 case 7:
4986                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4987                         break;
4988                 case 10:
4989                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4990                         break;
4991                 case 14:
4992                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4993                         break;
4994                 }
4995                 if (INTEL_INFO(dev)->gen >= 4)
4996                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4997         } else {
4998                 if (is_lvds) {
4999                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5000                 } else {
5001                         if (clock.p1 == 2)
5002                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
5003                         else
5004                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5005                         if (clock.p2 == 4)
5006                                 dpll |= PLL_P2_DIVIDE_BY_4;
5007                 }
5008         }
5009
5010         if (is_sdvo && is_tv)
5011                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5012         else if (is_tv)
5013                 /* XXX: just matching BIOS for now */
5014                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5015                 dpll |= 3;
5016         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5017                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5018         else
5019                 dpll |= PLL_REF_INPUT_DREFCLK;
5020
5021         /* setup pipeconf */
5022         pipeconf = I915_READ(PIPECONF(pipe));
5023
5024         /* Set up the display plane register */
5025         dspcntr = DISPPLANE_GAMMA_ENABLE;
5026
5027         /* Ironlake's plane is forced to pipe, bit 24 is to
5028            enable color space conversion */
5029         if (pipe == 0)
5030                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5031         else
5032                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5033
5034         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5035                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5036                  * core speed.
5037                  *
5038                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5039                  * pipe == 0 check?
5040                  */
5041                 if (mode->clock >
5042                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5043                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5044                 else
5045                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5046         }
5047
5048         /* default to 8bpc */
5049         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5050         if (is_dp) {
5051                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5052                         pipeconf |= PIPECONF_BPP_6 |
5053                                     PIPECONF_DITHER_EN |
5054                                     PIPECONF_DITHER_TYPE_SP;
5055                 }
5056         }
5057
5058         dpll |= DPLL_VCO_ENABLE;
5059
5060         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5061         drm_mode_debug_printmodeline(mode);
5062
5063         I915_WRITE(FP0(pipe), fp);
5064         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5065
5066         POSTING_READ(DPLL(pipe));
5067         udelay(150);
5068
5069         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5070          * This is an exception to the general rule that mode_set doesn't turn
5071          * things on.
5072          */
5073         if (is_lvds) {
5074                 temp = I915_READ(LVDS);
5075                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5076                 if (pipe == 1) {
5077                         temp |= LVDS_PIPEB_SELECT;
5078                 } else {
5079                         temp &= ~LVDS_PIPEB_SELECT;
5080                 }
5081                 /* set the corresponsding LVDS_BORDER bit */
5082                 temp |= dev_priv->lvds_border_bits;
5083                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5084                  * set the DPLLs for dual-channel mode or not.
5085                  */
5086                 if (clock.p2 == 7)
5087                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5088                 else
5089                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5090
5091                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5092                  * appropriately here, but we need to look more thoroughly into how
5093                  * panels behave in the two modes.
5094                  */
5095                 /* set the dithering flag on LVDS as needed */
5096                 if (INTEL_INFO(dev)->gen >= 4) {
5097                         if (dev_priv->lvds_dither)
5098                                 temp |= LVDS_ENABLE_DITHER;
5099                         else
5100                                 temp &= ~LVDS_ENABLE_DITHER;
5101                 }
5102                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5103                         lvds_sync |= LVDS_HSYNC_POLARITY;
5104                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5105                         lvds_sync |= LVDS_VSYNC_POLARITY;
5106                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5107                     != lvds_sync) {
5108                         char flags[2] = "-+";
5109                         DRM_INFO("Changing LVDS panel from "
5110                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5111                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5112                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5113                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5114                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5115                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5116                         temp |= lvds_sync;
5117                 }
5118                 I915_WRITE(LVDS, temp);
5119         }
5120
5121         if (is_dp) {
5122                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5123         }
5124
5125         I915_WRITE(DPLL(pipe), dpll);
5126
5127         /* Wait for the clocks to stabilize. */
5128         POSTING_READ(DPLL(pipe));
5129         udelay(150);
5130
5131         if (INTEL_INFO(dev)->gen >= 4) {
5132                 temp = 0;
5133                 if (is_sdvo) {
5134                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5135                         if (temp > 1)
5136                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5137                         else
5138                                 temp = 0;
5139                 }
5140                 I915_WRITE(DPLL_MD(pipe), temp);
5141         } else {
5142                 /* The pixel multiplier can only be updated once the
5143                  * DPLL is enabled and the clocks are stable.
5144                  *
5145                  * So write it again.
5146                  */
5147                 I915_WRITE(DPLL(pipe), dpll);
5148         }
5149
5150         intel_crtc->lowfreq_avail = false;
5151         if (is_lvds && has_reduced_clock && i915_powersave) {
5152                 I915_WRITE(FP1(pipe), fp2);
5153                 intel_crtc->lowfreq_avail = true;
5154                 if (HAS_PIPE_CXSR(dev)) {
5155                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5156                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5157                 }
5158         } else {
5159                 I915_WRITE(FP1(pipe), fp);
5160                 if (HAS_PIPE_CXSR(dev)) {
5161                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5162                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5163                 }
5164         }
5165
5166         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5167                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5168                 /* the chip adds 2 halflines automatically */
5169                 adjusted_mode->crtc_vdisplay -= 1;
5170                 adjusted_mode->crtc_vtotal -= 1;
5171                 adjusted_mode->crtc_vblank_start -= 1;
5172                 adjusted_mode->crtc_vblank_end -= 1;
5173                 adjusted_mode->crtc_vsync_end -= 1;
5174                 adjusted_mode->crtc_vsync_start -= 1;
5175         } else
5176                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5177
5178         I915_WRITE(HTOTAL(pipe),
5179                    (adjusted_mode->crtc_hdisplay - 1) |
5180                    ((adjusted_mode->crtc_htotal - 1) << 16));
5181         I915_WRITE(HBLANK(pipe),
5182                    (adjusted_mode->crtc_hblank_start - 1) |
5183                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5184         I915_WRITE(HSYNC(pipe),
5185                    (adjusted_mode->crtc_hsync_start - 1) |
5186                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5187
5188         I915_WRITE(VTOTAL(pipe),
5189                    (adjusted_mode->crtc_vdisplay - 1) |
5190                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5191         I915_WRITE(VBLANK(pipe),
5192                    (adjusted_mode->crtc_vblank_start - 1) |
5193                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5194         I915_WRITE(VSYNC(pipe),
5195                    (adjusted_mode->crtc_vsync_start - 1) |
5196                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5197
5198         /* pipesrc and dspsize control the size that is scaled from,
5199          * which should always be the user's requested size.
5200          */
5201         I915_WRITE(DSPSIZE(plane),
5202                    ((mode->vdisplay - 1) << 16) |
5203                    (mode->hdisplay - 1));
5204         I915_WRITE(DSPPOS(plane), 0);
5205         I915_WRITE(PIPESRC(pipe),
5206                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5207
5208         I915_WRITE(PIPECONF(pipe), pipeconf);
5209         POSTING_READ(PIPECONF(pipe));
5210         intel_enable_pipe(dev_priv, pipe, false);
5211
5212         intel_wait_for_vblank(dev, pipe);
5213
5214         I915_WRITE(DSPCNTR(plane), dspcntr);
5215         POSTING_READ(DSPCNTR(plane));
5216         intel_enable_plane(dev_priv, plane, pipe);
5217
5218         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5219
5220         intel_update_watermarks(dev);
5221
5222         return ret;
5223 }
5224
5225 /*
5226  * Initialize reference clocks when the driver loads
5227  */
5228 void ironlake_init_pch_refclk(struct drm_device *dev)
5229 {
5230         struct drm_i915_private *dev_priv = dev->dev_private;
5231         struct drm_mode_config *mode_config = &dev->mode_config;
5232         struct intel_encoder *encoder;
5233         u32 temp;
5234         bool has_lvds = false;
5235         bool has_cpu_edp = false;
5236         bool has_pch_edp = false;
5237         bool has_panel = false;
5238         bool has_ck505 = false;
5239         bool can_ssc = false;
5240
5241         /* We need to take the global config into account */
5242         list_for_each_entry(encoder, &mode_config->encoder_list,
5243                             base.head) {
5244                 switch (encoder->type) {
5245                 case INTEL_OUTPUT_LVDS:
5246                         has_panel = true;
5247                         has_lvds = true;
5248                         break;
5249                 case INTEL_OUTPUT_EDP:
5250                         has_panel = true;
5251                         if (intel_encoder_is_pch_edp(&encoder->base))
5252                                 has_pch_edp = true;
5253                         else
5254                                 has_cpu_edp = true;
5255                         break;
5256                 }
5257         }
5258
5259         if (HAS_PCH_IBX(dev)) {
5260                 has_ck505 = dev_priv->display_clock_mode;
5261                 can_ssc = has_ck505;
5262         } else {
5263                 has_ck505 = false;
5264                 can_ssc = true;
5265         }
5266
5267         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5268                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5269                       has_ck505);
5270
5271         /* Ironlake: try to setup display ref clock before DPLL
5272          * enabling. This is only under driver's control after
5273          * PCH B stepping, previous chipset stepping should be
5274          * ignoring this setting.
5275          */
5276         temp = I915_READ(PCH_DREF_CONTROL);
5277         /* Always enable nonspread source */
5278         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5279
5280         if (has_ck505)
5281                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5282         else
5283                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5284
5285         if (has_panel) {
5286                 temp &= ~DREF_SSC_SOURCE_MASK;
5287                 temp |= DREF_SSC_SOURCE_ENABLE;
5288
5289                 /* SSC must be turned on before enabling the CPU output  */
5290                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5291                         DRM_DEBUG_KMS("Using SSC on panel\n");
5292                         temp |= DREF_SSC1_ENABLE;
5293                 }
5294
5295                 /* Get SSC going before enabling the outputs */
5296                 I915_WRITE(PCH_DREF_CONTROL, temp);
5297                 POSTING_READ(PCH_DREF_CONTROL);
5298                 udelay(200);
5299
5300                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5301
5302                 /* Enable CPU source on CPU attached eDP */
5303                 if (has_cpu_edp) {
5304                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5305                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5306                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5307                         }
5308                         else
5309                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5310                 } else
5311                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5312
5313                 I915_WRITE(PCH_DREF_CONTROL, temp);
5314                 POSTING_READ(PCH_DREF_CONTROL);
5315                 udelay(200);
5316         } else {
5317                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5318
5319                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5320
5321                 /* Turn off CPU output */
5322                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5323
5324                 I915_WRITE(PCH_DREF_CONTROL, temp);
5325                 POSTING_READ(PCH_DREF_CONTROL);
5326                 udelay(200);
5327
5328                 /* Turn off the SSC source */
5329                 temp &= ~DREF_SSC_SOURCE_MASK;
5330                 temp |= DREF_SSC_SOURCE_DISABLE;
5331
5332                 /* Turn off SSC1 */
5333                 temp &= ~ DREF_SSC1_ENABLE;
5334
5335                 I915_WRITE(PCH_DREF_CONTROL, temp);
5336                 POSTING_READ(PCH_DREF_CONTROL);
5337                 udelay(200);
5338         }
5339 }
5340
5341 static int ironlake_get_refclk(struct drm_crtc *crtc)
5342 {
5343         struct drm_device *dev = crtc->dev;
5344         struct drm_i915_private *dev_priv = dev->dev_private;
5345         struct intel_encoder *encoder;
5346         struct drm_mode_config *mode_config = &dev->mode_config;
5347         struct intel_encoder *edp_encoder = NULL;
5348         int num_connectors = 0;
5349         bool is_lvds = false;
5350
5351         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5352                 if (encoder->base.crtc != crtc)
5353                         continue;
5354
5355                 switch (encoder->type) {
5356                 case INTEL_OUTPUT_LVDS:
5357                         is_lvds = true;
5358                         break;
5359                 case INTEL_OUTPUT_EDP:
5360                         edp_encoder = encoder;
5361                         break;
5362                 }
5363                 num_connectors++;
5364         }
5365
5366         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5367                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5368                               dev_priv->lvds_ssc_freq);
5369                 return dev_priv->lvds_ssc_freq * 1000;
5370         }
5371
5372         return 120000;
5373 }
5374
5375 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5376                                   struct drm_display_mode *mode,
5377                                   struct drm_display_mode *adjusted_mode,
5378                                   int x, int y,
5379                                   struct drm_framebuffer *old_fb)
5380 {
5381         struct drm_device *dev = crtc->dev;
5382         struct drm_i915_private *dev_priv = dev->dev_private;
5383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5384         int pipe = intel_crtc->pipe;
5385         int plane = intel_crtc->plane;
5386         int refclk, num_connectors = 0;
5387         intel_clock_t clock, reduced_clock;
5388         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5389         bool ok, has_reduced_clock = false, is_sdvo = false;
5390         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5391         struct intel_encoder *has_edp_encoder = NULL;
5392         struct drm_mode_config *mode_config = &dev->mode_config;
5393         struct intel_encoder *encoder;
5394         const intel_limit_t *limit;
5395         int ret;
5396         struct fdi_m_n m_n = {0};
5397         u32 temp;
5398         u32 lvds_sync = 0;
5399         int target_clock, pixel_multiplier, lane, link_bw, factor;
5400         unsigned int pipe_bpp;
5401         bool dither;
5402
5403         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5404                 if (encoder->base.crtc != crtc)
5405                         continue;
5406
5407                 switch (encoder->type) {
5408                 case INTEL_OUTPUT_LVDS:
5409                         is_lvds = true;
5410                         break;
5411                 case INTEL_OUTPUT_SDVO:
5412                 case INTEL_OUTPUT_HDMI:
5413                         is_sdvo = true;
5414                         if (encoder->needs_tv_clock)
5415                                 is_tv = true;
5416                         break;
5417                 case INTEL_OUTPUT_TVOUT:
5418                         is_tv = true;
5419                         break;
5420                 case INTEL_OUTPUT_ANALOG:
5421                         is_crt = true;
5422                         break;
5423                 case INTEL_OUTPUT_DISPLAYPORT:
5424                         is_dp = true;
5425                         break;
5426                 case INTEL_OUTPUT_EDP:
5427                         has_edp_encoder = encoder;
5428                         break;
5429                 }
5430
5431                 num_connectors++;
5432         }
5433
5434         refclk = ironlake_get_refclk(crtc);
5435
5436         /*
5437          * Returns a set of divisors for the desired target clock with the given
5438          * refclk, or FALSE.  The returned values represent the clock equation:
5439          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5440          */
5441         limit = intel_limit(crtc, refclk);
5442         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5443         if (!ok) {
5444                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5445                 return -EINVAL;
5446         }
5447
5448         /* Ensure that the cursor is valid for the new mode before changing... */
5449         intel_crtc_update_cursor(crtc, true);
5450
5451         if (is_lvds && dev_priv->lvds_downclock_avail) {
5452                 has_reduced_clock = limit->find_pll(limit, crtc,
5453                                                     dev_priv->lvds_downclock,
5454                                                     refclk,
5455                                                     &reduced_clock);
5456                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5457                         /*
5458                          * If the different P is found, it means that we can't
5459                          * switch the display clock by using the FP0/FP1.
5460                          * In such case we will disable the LVDS downclock
5461                          * feature.
5462                          */
5463                         DRM_DEBUG_KMS("Different P is found for "
5464                                       "LVDS clock/downclock\n");
5465                         has_reduced_clock = 0;
5466                 }
5467         }
5468         /* SDVO TV has fixed PLL values depend on its clock range,
5469            this mirrors vbios setting. */
5470         if (is_sdvo && is_tv) {
5471                 if (adjusted_mode->clock >= 100000
5472                     && adjusted_mode->clock < 140500) {
5473                         clock.p1 = 2;
5474                         clock.p2 = 10;
5475                         clock.n = 3;
5476                         clock.m1 = 16;
5477                         clock.m2 = 8;
5478                 } else if (adjusted_mode->clock >= 140500
5479                            && adjusted_mode->clock <= 200000) {
5480                         clock.p1 = 1;
5481                         clock.p2 = 10;
5482                         clock.n = 6;
5483                         clock.m1 = 12;
5484                         clock.m2 = 8;
5485                 }
5486         }
5487
5488         /* FDI link */
5489         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5490         lane = 0;
5491         /* CPU eDP doesn't require FDI link, so just set DP M/N
5492            according to current link config */
5493         if (has_edp_encoder &&
5494             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5495                 target_clock = mode->clock;
5496                 intel_edp_link_config(has_edp_encoder,
5497                                       &lane, &link_bw);
5498         } else {
5499                 /* [e]DP over FDI requires target mode clock
5500                    instead of link clock */
5501                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5502                         target_clock = mode->clock;
5503                 else
5504                         target_clock = adjusted_mode->clock;
5505
5506                 /* FDI is a binary signal running at ~2.7GHz, encoding
5507                  * each output octet as 10 bits. The actual frequency
5508                  * is stored as a divider into a 100MHz clock, and the
5509                  * mode pixel clock is stored in units of 1KHz.
5510                  * Hence the bw of each lane in terms of the mode signal
5511                  * is:
5512                  */
5513                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5514         }
5515
5516         /* determine panel color depth */
5517         temp = I915_READ(PIPECONF(pipe));
5518         temp &= ~PIPE_BPC_MASK;
5519         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, adjusted_mode);
5520         switch (pipe_bpp) {
5521         case 18:
5522                 temp |= PIPE_6BPC;
5523                 break;
5524         case 24:
5525                 temp |= PIPE_8BPC;
5526                 break;
5527         case 30:
5528                 temp |= PIPE_10BPC;
5529                 break;
5530         case 36:
5531                 temp |= PIPE_12BPC;
5532                 break;
5533         default:
5534                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5535                         pipe_bpp);
5536                 temp |= PIPE_8BPC;
5537                 pipe_bpp = 24;
5538                 break;
5539         }
5540
5541         intel_crtc->bpp = pipe_bpp;
5542         I915_WRITE(PIPECONF(pipe), temp);
5543
5544         if (!lane) {
5545                 /*
5546                  * Account for spread spectrum to avoid
5547                  * oversubscribing the link. Max center spread
5548                  * is 2.5%; use 5% for safety's sake.
5549                  */
5550                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5551                 lane = bps / (link_bw * 8) + 1;
5552         }
5553
5554         intel_crtc->fdi_lanes = lane;
5555
5556         if (pixel_multiplier > 1)
5557                 link_bw *= pixel_multiplier;
5558         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5559                              &m_n);
5560
5561         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5562         if (has_reduced_clock)
5563                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5564                         reduced_clock.m2;
5565
5566         /* Enable autotuning of the PLL clock (if permissible) */
5567         factor = 21;
5568         if (is_lvds) {
5569                 if ((intel_panel_use_ssc(dev_priv) &&
5570                      dev_priv->lvds_ssc_freq == 100) ||
5571                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5572                         factor = 25;
5573         } else if (is_sdvo && is_tv)
5574                 factor = 20;
5575
5576         if (clock.m < factor * clock.n)
5577                 fp |= FP_CB_TUNE;
5578
5579         dpll = 0;
5580
5581         if (is_lvds)
5582                 dpll |= DPLLB_MODE_LVDS;
5583         else
5584                 dpll |= DPLLB_MODE_DAC_SERIAL;
5585         if (is_sdvo) {
5586                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5587                 if (pixel_multiplier > 1) {
5588                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5589                 }
5590                 dpll |= DPLL_DVO_HIGH_SPEED;
5591         }
5592         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5593                 dpll |= DPLL_DVO_HIGH_SPEED;
5594
5595         /* compute bitmask from p1 value */
5596         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5597         /* also FPA1 */
5598         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5599
5600         switch (clock.p2) {
5601         case 5:
5602                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5603                 break;
5604         case 7:
5605                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5606                 break;
5607         case 10:
5608                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5609                 break;
5610         case 14:
5611                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5612                 break;
5613         }
5614
5615         if (is_sdvo && is_tv)
5616                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5617         else if (is_tv)
5618                 /* XXX: just matching BIOS for now */
5619                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5620                 dpll |= 3;
5621         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5622                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5623         else
5624                 dpll |= PLL_REF_INPUT_DREFCLK;
5625
5626         /* setup pipeconf */
5627         pipeconf = I915_READ(PIPECONF(pipe));
5628
5629         /* Set up the display plane register */
5630         dspcntr = DISPPLANE_GAMMA_ENABLE;
5631
5632         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5633         drm_mode_debug_printmodeline(mode);
5634
5635         /* PCH eDP needs FDI, but CPU eDP does not */
5636         if (!intel_crtc->no_pll) {
5637                 if (!has_edp_encoder ||
5638                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5639                         I915_WRITE(PCH_FP0(pipe), fp);
5640                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5641
5642                         POSTING_READ(PCH_DPLL(pipe));
5643                         udelay(150);
5644                 }
5645         } else {
5646                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5647                     fp == I915_READ(PCH_FP0(0))) {
5648                         intel_crtc->use_pll_a = true;
5649                         DRM_DEBUG_KMS("using pipe a dpll\n");
5650                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5651                            fp == I915_READ(PCH_FP0(1))) {
5652                         intel_crtc->use_pll_a = false;
5653                         DRM_DEBUG_KMS("using pipe b dpll\n");
5654                 } else {
5655                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5656                         return -EINVAL;
5657                 }
5658         }
5659
5660         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5661          * This is an exception to the general rule that mode_set doesn't turn
5662          * things on.
5663          */
5664         if (is_lvds) {
5665                 temp = I915_READ(PCH_LVDS);
5666                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5667                 if (HAS_PCH_CPT(dev)) {
5668                         temp &= ~PORT_TRANS_SEL_MASK;
5669                         temp |= PORT_TRANS_SEL_CPT(pipe);
5670                 } else {
5671                         if (pipe == 1)
5672                                 temp |= LVDS_PIPEB_SELECT;
5673                         else
5674                                 temp &= ~LVDS_PIPEB_SELECT;
5675                 }
5676
5677                 /* set the corresponsding LVDS_BORDER bit */
5678                 temp |= dev_priv->lvds_border_bits;
5679                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5680                  * set the DPLLs for dual-channel mode or not.
5681                  */
5682                 if (clock.p2 == 7)
5683                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5684                 else
5685                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5686
5687                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5688                  * appropriately here, but we need to look more thoroughly into how
5689                  * panels behave in the two modes.
5690                  */
5691                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5692                         lvds_sync |= LVDS_HSYNC_POLARITY;
5693                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5694                         lvds_sync |= LVDS_VSYNC_POLARITY;
5695                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5696                     != lvds_sync) {
5697                         char flags[2] = "-+";
5698                         DRM_INFO("Changing LVDS panel from "
5699                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5700                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5701                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5702                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5703                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5704                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5705                         temp |= lvds_sync;
5706                 }
5707                 I915_WRITE(PCH_LVDS, temp);
5708         }
5709
5710         pipeconf &= ~PIPECONF_DITHER_EN;
5711         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5712         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5713                 pipeconf |= PIPECONF_DITHER_EN;
5714                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5715         }
5716         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5717                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5718         } else {
5719                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5720                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5721                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5722                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5723                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5724         }
5725
5726         if (!intel_crtc->no_pll &&
5727             (!has_edp_encoder ||
5728              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5729                 I915_WRITE(PCH_DPLL(pipe), dpll);
5730
5731                 /* Wait for the clocks to stabilize. */
5732                 POSTING_READ(PCH_DPLL(pipe));
5733                 udelay(150);
5734
5735                 /* The pixel multiplier can only be updated once the
5736                  * DPLL is enabled and the clocks are stable.
5737                  *
5738                  * So write it again.
5739                  */
5740                 I915_WRITE(PCH_DPLL(pipe), dpll);
5741         }
5742
5743         intel_crtc->lowfreq_avail = false;
5744         if (!intel_crtc->no_pll) {
5745                 if (is_lvds && has_reduced_clock && i915_powersave) {
5746                         I915_WRITE(PCH_FP1(pipe), fp2);
5747                         intel_crtc->lowfreq_avail = true;
5748                         if (HAS_PIPE_CXSR(dev)) {
5749                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5750                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5751                         }
5752                 } else {
5753                         I915_WRITE(PCH_FP1(pipe), fp);
5754                         if (HAS_PIPE_CXSR(dev)) {
5755                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5756                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5757                         }
5758                 }
5759         }
5760
5761         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5762                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5763                 /* the chip adds 2 halflines automatically */
5764                 adjusted_mode->crtc_vdisplay -= 1;
5765                 adjusted_mode->crtc_vtotal -= 1;
5766                 adjusted_mode->crtc_vblank_start -= 1;
5767                 adjusted_mode->crtc_vblank_end -= 1;
5768                 adjusted_mode->crtc_vsync_end -= 1;
5769                 adjusted_mode->crtc_vsync_start -= 1;
5770         } else
5771                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5772
5773         I915_WRITE(HTOTAL(pipe),
5774                    (adjusted_mode->crtc_hdisplay - 1) |
5775                    ((adjusted_mode->crtc_htotal - 1) << 16));
5776         I915_WRITE(HBLANK(pipe),
5777                    (adjusted_mode->crtc_hblank_start - 1) |
5778                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5779         I915_WRITE(HSYNC(pipe),
5780                    (adjusted_mode->crtc_hsync_start - 1) |
5781                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5782
5783         I915_WRITE(VTOTAL(pipe),
5784                    (adjusted_mode->crtc_vdisplay - 1) |
5785                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5786         I915_WRITE(VBLANK(pipe),
5787                    (adjusted_mode->crtc_vblank_start - 1) |
5788                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5789         I915_WRITE(VSYNC(pipe),
5790                    (adjusted_mode->crtc_vsync_start - 1) |
5791                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5792
5793         /* pipesrc controls the size that is scaled from, which should
5794          * always be the user's requested size.
5795          */
5796         I915_WRITE(PIPESRC(pipe),
5797                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5798
5799         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5800         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5801         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5802         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5803
5804         if (has_edp_encoder &&
5805             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5806                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5807         }
5808
5809         I915_WRITE(PIPECONF(pipe), pipeconf);
5810         POSTING_READ(PIPECONF(pipe));
5811
5812         intel_wait_for_vblank(dev, pipe);
5813
5814         if (IS_GEN5(dev)) {
5815                 /* enable address swizzle for tiling buffer */
5816                 temp = I915_READ(DISP_ARB_CTL);
5817                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5818         }
5819
5820         I915_WRITE(DSPCNTR(plane), dspcntr);
5821         POSTING_READ(DSPCNTR(plane));
5822
5823         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5824
5825         intel_update_watermarks(dev);
5826
5827         return ret;
5828 }
5829
5830 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5831                                struct drm_display_mode *mode,
5832                                struct drm_display_mode *adjusted_mode,
5833                                int x, int y,
5834                                struct drm_framebuffer *old_fb)
5835 {
5836         struct drm_device *dev = crtc->dev;
5837         struct drm_i915_private *dev_priv = dev->dev_private;
5838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5839         int pipe = intel_crtc->pipe;
5840         int ret;
5841
5842         drm_vblank_pre_modeset(dev, pipe);
5843
5844         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5845                                               x, y, old_fb);
5846
5847         drm_vblank_post_modeset(dev, pipe);
5848
5849         intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5850
5851         return ret;
5852 }
5853
5854 static void g4x_write_eld(struct drm_connector *connector,
5855                           struct drm_crtc *crtc)
5856 {
5857         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5858         uint8_t *eld = connector->eld;
5859         uint32_t eldv;
5860         uint32_t len;
5861         uint32_t i;
5862
5863         i = I915_READ(G4X_AUD_VID_DID);
5864
5865         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5866                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5867         else
5868                 eldv = G4X_ELDV_DEVCTG;
5869
5870         i = I915_READ(G4X_AUD_CNTL_ST);
5871         i &= ~(eldv | G4X_ELD_ADDR);
5872         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5873         I915_WRITE(G4X_AUD_CNTL_ST, i);
5874
5875         if (!eld[0])
5876                 return;
5877
5878         len = min_t(uint8_t, eld[2], len);
5879         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5880         for (i = 0; i < len; i++)
5881                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5882
5883         i = I915_READ(G4X_AUD_CNTL_ST);
5884         i |= eldv;
5885         I915_WRITE(G4X_AUD_CNTL_ST, i);
5886 }
5887
5888 static void ironlake_write_eld(struct drm_connector *connector,
5889                                      struct drm_crtc *crtc)
5890 {
5891         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5892         uint8_t *eld = connector->eld;
5893         uint32_t eldv;
5894         uint32_t i;
5895         int len;
5896         int hdmiw_hdmiedid;
5897         int aud_cntl_st;
5898         int aud_cntrl_st2;
5899
5900         if (HAS_PCH_IBX(connector->dev)) {
5901                 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5902                 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5903                 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5904         } else {
5905                 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5906                 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5907                 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5908         }
5909
5910         i = to_intel_crtc(crtc)->pipe;
5911         hdmiw_hdmiedid += i * 0x100;
5912         aud_cntl_st += i * 0x100;
5913
5914         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5915
5916         i = I915_READ(aud_cntl_st);
5917         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
5918         if (!i) {
5919                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5920                 /* operate blindly on all ports */
5921                 eldv = GEN5_ELD_VALIDB;
5922                 eldv |= GEN5_ELD_VALIDB << 4;
5923                 eldv |= GEN5_ELD_VALIDB << 8;
5924         } else {
5925                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5926                 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5927         }
5928
5929         i = I915_READ(aud_cntrl_st2);
5930         i &= ~eldv;
5931         I915_WRITE(aud_cntrl_st2, i);
5932
5933         if (!eld[0])
5934                 return;
5935
5936         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5937                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5938                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5939         }
5940
5941         i = I915_READ(aud_cntl_st);
5942         i &= ~GEN5_ELD_ADDRESS;
5943         I915_WRITE(aud_cntl_st, i);
5944
5945         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5946         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5947         for (i = 0; i < len; i++)
5948                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5949
5950         i = I915_READ(aud_cntrl_st2);
5951         i |= eldv;
5952         I915_WRITE(aud_cntrl_st2, i);
5953 }
5954
5955 void intel_write_eld(struct drm_encoder *encoder,
5956                      struct drm_display_mode *mode)
5957 {
5958         struct drm_crtc *crtc = encoder->crtc;
5959         struct drm_connector *connector;
5960         struct drm_device *dev = encoder->dev;
5961         struct drm_i915_private *dev_priv = dev->dev_private;
5962
5963         connector = drm_select_eld(encoder, mode);
5964         if (!connector)
5965                 return;
5966
5967         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5968                          connector->base.id,
5969                          drm_get_connector_name(connector),
5970                          connector->encoder->base.id,
5971                          drm_get_encoder_name(connector->encoder));
5972
5973         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5974
5975         if (dev_priv->display.write_eld)
5976                 dev_priv->display.write_eld(connector, crtc);
5977 }
5978
5979 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5980 void intel_crtc_load_lut(struct drm_crtc *crtc)
5981 {
5982         struct drm_device *dev = crtc->dev;
5983         struct drm_i915_private *dev_priv = dev->dev_private;
5984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5985         int palreg = PALETTE(intel_crtc->pipe);
5986         int i;
5987
5988         /* The clocks have to be on to load the palette. */
5989         if (!crtc->enabled || !intel_crtc->active)
5990                 return;
5991
5992         /* use legacy palette for Ironlake */
5993         if (HAS_PCH_SPLIT(dev))
5994                 palreg = LGC_PALETTE(intel_crtc->pipe);
5995
5996         for (i = 0; i < 256; i++) {
5997                 I915_WRITE(palreg + 4 * i,
5998                            (intel_crtc->lut_r[i] << 16) |
5999                            (intel_crtc->lut_g[i] << 8) |
6000                            intel_crtc->lut_b[i]);
6001         }
6002 }
6003
6004 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6005 {
6006         struct drm_device *dev = crtc->dev;
6007         struct drm_i915_private *dev_priv = dev->dev_private;
6008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6009         bool visible = base != 0;
6010         u32 cntl;
6011
6012         if (intel_crtc->cursor_visible == visible)
6013                 return;
6014
6015         cntl = I915_READ(_CURACNTR);
6016         if (visible) {
6017                 /* On these chipsets we can only modify the base whilst
6018                  * the cursor is disabled.
6019                  */
6020                 I915_WRITE(_CURABASE, base);
6021
6022                 cntl &= ~(CURSOR_FORMAT_MASK);
6023                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6024                 cntl |= CURSOR_ENABLE |
6025                         CURSOR_GAMMA_ENABLE |
6026                         CURSOR_FORMAT_ARGB;
6027         } else
6028                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6029         I915_WRITE(_CURACNTR, cntl);
6030
6031         intel_crtc->cursor_visible = visible;
6032 }
6033
6034 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6035 {
6036         struct drm_device *dev = crtc->dev;
6037         struct drm_i915_private *dev_priv = dev->dev_private;
6038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6039         int pipe = intel_crtc->pipe;
6040         bool visible = base != 0;
6041
6042         if (intel_crtc->cursor_visible != visible) {
6043                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6044                 if (base) {
6045                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6046                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6047                         cntl |= pipe << 28; /* Connect to correct pipe */
6048                 } else {
6049                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6050                         cntl |= CURSOR_MODE_DISABLE;
6051                 }
6052                 I915_WRITE(CURCNTR(pipe), cntl);
6053
6054                 intel_crtc->cursor_visible = visible;
6055         }
6056         /* and commit changes on next vblank */
6057         I915_WRITE(CURBASE(pipe), base);
6058 }
6059
6060 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6061 {
6062         struct drm_device *dev = crtc->dev;
6063         struct drm_i915_private *dev_priv = dev->dev_private;
6064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6065         int pipe = intel_crtc->pipe;
6066         bool visible = base != 0;
6067
6068         if (intel_crtc->cursor_visible != visible) {
6069                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6070                 if (base) {
6071                         cntl &= ~CURSOR_MODE;
6072                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6073                 } else {
6074                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6075                         cntl |= CURSOR_MODE_DISABLE;
6076                 }
6077                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6078
6079                 intel_crtc->cursor_visible = visible;
6080         }
6081         /* and commit changes on next vblank */
6082         I915_WRITE(CURBASE_IVB(pipe), base);
6083 }
6084
6085 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6086 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6087                                      bool on)
6088 {
6089         struct drm_device *dev = crtc->dev;
6090         struct drm_i915_private *dev_priv = dev->dev_private;
6091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6092         int pipe = intel_crtc->pipe;
6093         int x = intel_crtc->cursor_x;
6094         int y = intel_crtc->cursor_y;
6095         u32 base, pos;
6096         bool visible;
6097
6098         pos = 0;
6099
6100         if (on && crtc->enabled && crtc->fb) {
6101                 base = intel_crtc->cursor_addr;
6102                 if (x > (int) crtc->fb->width)
6103                         base = 0;
6104
6105                 if (y > (int) crtc->fb->height)
6106                         base = 0;
6107         } else
6108                 base = 0;
6109
6110         if (x < 0) {
6111                 if (x + intel_crtc->cursor_width < 0)
6112                         base = 0;
6113
6114                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6115                 x = -x;
6116         }
6117         pos |= x << CURSOR_X_SHIFT;
6118
6119         if (y < 0) {
6120                 if (y + intel_crtc->cursor_height < 0)
6121                         base = 0;
6122
6123                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6124                 y = -y;
6125         }
6126         pos |= y << CURSOR_Y_SHIFT;
6127
6128         visible = base != 0;
6129         if (!visible && !intel_crtc->cursor_visible)
6130                 return;
6131
6132         if (IS_IVYBRIDGE(dev)) {
6133                 I915_WRITE(CURPOS_IVB(pipe), pos);
6134                 ivb_update_cursor(crtc, base);
6135         } else {
6136                 I915_WRITE(CURPOS(pipe), pos);
6137                 if (IS_845G(dev) || IS_I865G(dev))
6138                         i845_update_cursor(crtc, base);
6139                 else
6140                         i9xx_update_cursor(crtc, base);
6141         }
6142
6143         if (visible)
6144                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6145 }
6146
6147 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6148                                  struct drm_file *file,
6149                                  uint32_t handle,
6150                                  uint32_t width, uint32_t height)
6151 {
6152         struct drm_device *dev = crtc->dev;
6153         struct drm_i915_private *dev_priv = dev->dev_private;
6154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6155         struct drm_i915_gem_object *obj;
6156         uint32_t addr;
6157         int ret;
6158
6159         DRM_DEBUG_KMS("\n");
6160
6161         /* if we want to turn off the cursor ignore width and height */
6162         if (!handle) {
6163                 DRM_DEBUG_KMS("cursor off\n");
6164                 addr = 0;
6165                 obj = NULL;
6166                 mutex_lock(&dev->struct_mutex);
6167                 goto finish;
6168         }
6169
6170         /* Currently we only support 64x64 cursors */
6171         if (width != 64 || height != 64) {
6172                 DRM_ERROR("we currently only support 64x64 cursors\n");
6173                 return -EINVAL;
6174         }
6175
6176         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6177         if (&obj->base == NULL)
6178                 return -ENOENT;
6179
6180         if (obj->base.size < width * height * 4) {
6181                 DRM_ERROR("buffer is to small\n");
6182                 ret = -ENOMEM;
6183                 goto fail;
6184         }
6185
6186         /* we only need to pin inside GTT if cursor is non-phy */
6187         mutex_lock(&dev->struct_mutex);
6188         if (!dev_priv->info->cursor_needs_physical) {
6189                 if (obj->tiling_mode) {
6190                         DRM_ERROR("cursor cannot be tiled\n");
6191                         ret = -EINVAL;
6192                         goto fail_locked;
6193                 }
6194
6195                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6196                 if (ret) {
6197                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6198                         goto fail_locked;
6199                 }
6200
6201                 ret = i915_gem_object_put_fence(obj);
6202                 if (ret) {
6203                         DRM_ERROR("failed to release fence for cursor");
6204                         goto fail_unpin;
6205                 }
6206
6207                 addr = obj->gtt_offset;
6208         } else {
6209                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6210                 ret = i915_gem_attach_phys_object(dev, obj,
6211                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6212                                                   align);
6213                 if (ret) {
6214                         DRM_ERROR("failed to attach phys object\n");
6215                         goto fail_locked;
6216                 }
6217                 addr = obj->phys_obj->handle->busaddr;
6218         }
6219
6220         if (IS_GEN2(dev))
6221                 I915_WRITE(CURSIZE, (height << 12) | width);
6222
6223  finish:
6224         if (intel_crtc->cursor_bo) {
6225                 if (dev_priv->info->cursor_needs_physical) {
6226                         if (intel_crtc->cursor_bo != obj)
6227                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6228                 } else
6229                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6230                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6231         }
6232
6233         mutex_unlock(&dev->struct_mutex);
6234
6235         intel_crtc->cursor_addr = addr;
6236         intel_crtc->cursor_bo = obj;
6237         intel_crtc->cursor_width = width;
6238         intel_crtc->cursor_height = height;
6239
6240         intel_crtc_update_cursor(crtc, true);
6241
6242         return 0;
6243 fail_unpin:
6244         i915_gem_object_unpin(obj);
6245 fail_locked:
6246         mutex_unlock(&dev->struct_mutex);
6247 fail:
6248         drm_gem_object_unreference_unlocked(&obj->base);
6249         return ret;
6250 }
6251
6252 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6253 {
6254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6255
6256         intel_crtc->cursor_x = x;
6257         intel_crtc->cursor_y = y;
6258
6259         intel_crtc_update_cursor(crtc, true);
6260
6261         return 0;
6262 }
6263
6264 /** Sets the color ramps on behalf of RandR */
6265 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6266                                  u16 blue, int regno)
6267 {
6268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6269
6270         intel_crtc->lut_r[regno] = red >> 8;
6271         intel_crtc->lut_g[regno] = green >> 8;
6272         intel_crtc->lut_b[regno] = blue >> 8;
6273 }
6274
6275 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6276                              u16 *blue, int regno)
6277 {
6278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6279
6280         *red = intel_crtc->lut_r[regno] << 8;
6281         *green = intel_crtc->lut_g[regno] << 8;
6282         *blue = intel_crtc->lut_b[regno] << 8;
6283 }
6284
6285 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6286                                  u16 *blue, uint32_t start, uint32_t size)
6287 {
6288         int end = (start + size > 256) ? 256 : start + size, i;
6289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6290
6291         for (i = start; i < end; i++) {
6292                 intel_crtc->lut_r[i] = red[i] >> 8;
6293                 intel_crtc->lut_g[i] = green[i] >> 8;
6294                 intel_crtc->lut_b[i] = blue[i] >> 8;
6295         }
6296
6297         intel_crtc_load_lut(crtc);
6298 }
6299
6300 /**
6301  * Get a pipe with a simple mode set on it for doing load-based monitor
6302  * detection.
6303  *
6304  * It will be up to the load-detect code to adjust the pipe as appropriate for
6305  * its requirements.  The pipe will be connected to no other encoders.
6306  *
6307  * Currently this code will only succeed if there is a pipe with no encoders
6308  * configured for it.  In the future, it could choose to temporarily disable
6309  * some outputs to free up a pipe for its use.
6310  *
6311  * \return crtc, or NULL if no pipes are available.
6312  */
6313
6314 /* VESA 640x480x72Hz mode to set on the pipe */
6315 static struct drm_display_mode load_detect_mode = {
6316         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6317                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6318 };
6319
6320 static struct drm_framebuffer *
6321 intel_framebuffer_create(struct drm_device *dev,
6322                          struct drm_mode_fb_cmd *mode_cmd,
6323                          struct drm_i915_gem_object *obj)
6324 {
6325         struct intel_framebuffer *intel_fb;
6326         int ret;
6327
6328         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6329         if (!intel_fb) {
6330                 drm_gem_object_unreference_unlocked(&obj->base);
6331                 return ERR_PTR(-ENOMEM);
6332         }
6333
6334         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6335         if (ret) {
6336                 drm_gem_object_unreference_unlocked(&obj->base);
6337                 kfree(intel_fb);
6338                 return ERR_PTR(ret);
6339         }
6340
6341         return &intel_fb->base;
6342 }
6343
6344 static u32
6345 intel_framebuffer_pitch_for_width(int width, int bpp)
6346 {
6347         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6348         return ALIGN(pitch, 64);
6349 }
6350
6351 static u32
6352 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6353 {
6354         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6355         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6356 }
6357
6358 static struct drm_framebuffer *
6359 intel_framebuffer_create_for_mode(struct drm_device *dev,
6360                                   struct drm_display_mode *mode,
6361                                   int depth, int bpp)
6362 {
6363         struct drm_i915_gem_object *obj;
6364         struct drm_mode_fb_cmd mode_cmd;
6365
6366         obj = i915_gem_alloc_object(dev,
6367                                     intel_framebuffer_size_for_mode(mode, bpp));
6368         if (obj == NULL)
6369                 return ERR_PTR(-ENOMEM);
6370
6371         mode_cmd.width = mode->hdisplay;
6372         mode_cmd.height = mode->vdisplay;
6373         mode_cmd.depth = depth;
6374         mode_cmd.bpp = bpp;
6375         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6376
6377         return intel_framebuffer_create(dev, &mode_cmd, obj);
6378 }
6379
6380 static struct drm_framebuffer *
6381 mode_fits_in_fbdev(struct drm_device *dev,
6382                    struct drm_display_mode *mode)
6383 {
6384         struct drm_i915_private *dev_priv = dev->dev_private;
6385         struct drm_i915_gem_object *obj;
6386         struct drm_framebuffer *fb;
6387
6388         if (dev_priv->fbdev == NULL)
6389                 return NULL;
6390
6391         obj = dev_priv->fbdev->ifb.obj;
6392         if (obj == NULL)
6393                 return NULL;
6394
6395         fb = &dev_priv->fbdev->ifb.base;
6396         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6397                                                           fb->bits_per_pixel))
6398                 return NULL;
6399
6400         if (obj->base.size < mode->vdisplay * fb->pitch)
6401                 return NULL;
6402
6403         return fb;
6404 }
6405
6406 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6407                                 struct drm_connector *connector,
6408                                 struct drm_display_mode *mode,
6409                                 struct intel_load_detect_pipe *old)
6410 {
6411         struct intel_crtc *intel_crtc;
6412         struct drm_crtc *possible_crtc;
6413         struct drm_encoder *encoder = &intel_encoder->base;
6414         struct drm_crtc *crtc = NULL;
6415         struct drm_device *dev = encoder->dev;
6416         struct drm_framebuffer *old_fb;
6417         int i = -1;
6418
6419         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6420                       connector->base.id, drm_get_connector_name(connector),
6421                       encoder->base.id, drm_get_encoder_name(encoder));
6422
6423         /*
6424          * Algorithm gets a little messy:
6425          *
6426          *   - if the connector already has an assigned crtc, use it (but make
6427          *     sure it's on first)
6428          *
6429          *   - try to find the first unused crtc that can drive this connector,
6430          *     and use that if we find one
6431          */
6432
6433         /* See if we already have a CRTC for this connector */
6434         if (encoder->crtc) {
6435                 crtc = encoder->crtc;
6436
6437                 intel_crtc = to_intel_crtc(crtc);
6438                 old->dpms_mode = intel_crtc->dpms_mode;
6439                 old->load_detect_temp = false;
6440
6441                 /* Make sure the crtc and connector are running */
6442                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6443                         struct drm_encoder_helper_funcs *encoder_funcs;
6444                         struct drm_crtc_helper_funcs *crtc_funcs;
6445
6446                         crtc_funcs = crtc->helper_private;
6447                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6448
6449                         encoder_funcs = encoder->helper_private;
6450                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6451                 }
6452
6453                 return true;
6454         }
6455
6456         /* Find an unused one (if possible) */
6457         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6458                 i++;
6459                 if (!(encoder->possible_crtcs & (1 << i)))
6460                         continue;
6461                 if (!possible_crtc->enabled) {
6462                         crtc = possible_crtc;
6463                         break;
6464                 }
6465         }
6466
6467         /*
6468          * If we didn't find an unused CRTC, don't use any.
6469          */
6470         if (!crtc) {
6471                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6472                 return false;
6473         }
6474
6475         encoder->crtc = crtc;
6476         connector->encoder = encoder;
6477
6478         intel_crtc = to_intel_crtc(crtc);
6479         old->dpms_mode = intel_crtc->dpms_mode;
6480         old->load_detect_temp = true;
6481         old->release_fb = NULL;
6482
6483         if (!mode)
6484                 mode = &load_detect_mode;
6485
6486         old_fb = crtc->fb;
6487
6488         /* We need a framebuffer large enough to accommodate all accesses
6489          * that the plane may generate whilst we perform load detection.
6490          * We can not rely on the fbcon either being present (we get called
6491          * during its initialisation to detect all boot displays, or it may
6492          * not even exist) or that it is large enough to satisfy the
6493          * requested mode.
6494          */
6495         crtc->fb = mode_fits_in_fbdev(dev, mode);
6496         if (crtc->fb == NULL) {
6497                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6498                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6499                 old->release_fb = crtc->fb;
6500         } else
6501                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6502         if (IS_ERR(crtc->fb)) {
6503                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6504                 crtc->fb = old_fb;
6505                 return false;
6506         }
6507
6508         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6509                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6510                 if (old->release_fb)
6511                         old->release_fb->funcs->destroy(old->release_fb);
6512                 crtc->fb = old_fb;
6513                 return false;
6514         }
6515
6516         /* let the connector get through one full cycle before testing */
6517         intel_wait_for_vblank(dev, intel_crtc->pipe);
6518
6519         return true;
6520 }
6521
6522 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6523                                     struct drm_connector *connector,
6524                                     struct intel_load_detect_pipe *old)
6525 {
6526         struct drm_encoder *encoder = &intel_encoder->base;
6527         struct drm_device *dev = encoder->dev;
6528         struct drm_crtc *crtc = encoder->crtc;
6529         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6530         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6531
6532         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6533                       connector->base.id, drm_get_connector_name(connector),
6534                       encoder->base.id, drm_get_encoder_name(encoder));
6535
6536         if (old->load_detect_temp) {
6537                 connector->encoder = NULL;
6538                 drm_helper_disable_unused_functions(dev);
6539
6540                 if (old->release_fb)
6541                         old->release_fb->funcs->destroy(old->release_fb);
6542
6543                 return;
6544         }
6545
6546         /* Switch crtc and encoder back off if necessary */
6547         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6548                 encoder_funcs->dpms(encoder, old->dpms_mode);
6549                 crtc_funcs->dpms(crtc, old->dpms_mode);
6550         }
6551 }
6552
6553 /* Returns the clock of the currently programmed mode of the given pipe. */
6554 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6555 {
6556         struct drm_i915_private *dev_priv = dev->dev_private;
6557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6558         int pipe = intel_crtc->pipe;
6559         u32 dpll = I915_READ(DPLL(pipe));
6560         u32 fp;
6561         intel_clock_t clock;
6562
6563         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6564                 fp = I915_READ(FP0(pipe));
6565         else
6566                 fp = I915_READ(FP1(pipe));
6567
6568         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6569         if (IS_PINEVIEW(dev)) {
6570                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6571                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6572         } else {
6573                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6574                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6575         }
6576
6577         if (!IS_GEN2(dev)) {
6578                 if (IS_PINEVIEW(dev))
6579                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6580                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6581                 else
6582                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6583                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6584
6585                 switch (dpll & DPLL_MODE_MASK) {
6586                 case DPLLB_MODE_DAC_SERIAL:
6587                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6588                                 5 : 10;
6589                         break;
6590                 case DPLLB_MODE_LVDS:
6591                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6592                                 7 : 14;
6593                         break;
6594                 default:
6595                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6596                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6597                         return 0;
6598                 }
6599
6600                 /* XXX: Handle the 100Mhz refclk */
6601                 intel_clock(dev, 96000, &clock);
6602         } else {
6603                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6604
6605                 if (is_lvds) {
6606                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6607                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6608                         clock.p2 = 14;
6609
6610                         if ((dpll & PLL_REF_INPUT_MASK) ==
6611                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6612                                 /* XXX: might not be 66MHz */
6613                                 intel_clock(dev, 66000, &clock);
6614                         } else
6615                                 intel_clock(dev, 48000, &clock);
6616                 } else {
6617                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6618                                 clock.p1 = 2;
6619                         else {
6620                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6621                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6622                         }
6623                         if (dpll & PLL_P2_DIVIDE_BY_4)
6624                                 clock.p2 = 4;
6625                         else
6626                                 clock.p2 = 2;
6627
6628                         intel_clock(dev, 48000, &clock);
6629                 }
6630         }
6631
6632         /* XXX: It would be nice to validate the clocks, but we can't reuse
6633          * i830PllIsValid() because it relies on the xf86_config connector
6634          * configuration being accurate, which it isn't necessarily.
6635          */
6636
6637         return clock.dot;
6638 }
6639
6640 /** Returns the currently programmed mode of the given pipe. */
6641 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6642                                              struct drm_crtc *crtc)
6643 {
6644         struct drm_i915_private *dev_priv = dev->dev_private;
6645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6646         int pipe = intel_crtc->pipe;
6647         struct drm_display_mode *mode;
6648         int htot = I915_READ(HTOTAL(pipe));
6649         int hsync = I915_READ(HSYNC(pipe));
6650         int vtot = I915_READ(VTOTAL(pipe));
6651         int vsync = I915_READ(VSYNC(pipe));
6652
6653         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6654         if (!mode)
6655                 return NULL;
6656
6657         mode->clock = intel_crtc_clock_get(dev, crtc);
6658         mode->hdisplay = (htot & 0xffff) + 1;
6659         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6660         mode->hsync_start = (hsync & 0xffff) + 1;
6661         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6662         mode->vdisplay = (vtot & 0xffff) + 1;
6663         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6664         mode->vsync_start = (vsync & 0xffff) + 1;
6665         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6666
6667         drm_mode_set_name(mode);
6668         drm_mode_set_crtcinfo(mode, 0);
6669
6670         return mode;
6671 }
6672
6673 #define GPU_IDLE_TIMEOUT 500 /* ms */
6674
6675 /* When this timer fires, we've been idle for awhile */
6676 static void intel_gpu_idle_timer(unsigned long arg)
6677 {
6678         struct drm_device *dev = (struct drm_device *)arg;
6679         drm_i915_private_t *dev_priv = dev->dev_private;
6680
6681         if (!list_empty(&dev_priv->mm.active_list)) {
6682                 /* Still processing requests, so just re-arm the timer. */
6683                 mod_timer(&dev_priv->idle_timer, jiffies +
6684                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6685                 return;
6686         }
6687
6688         dev_priv->busy = false;
6689         queue_work(dev_priv->wq, &dev_priv->idle_work);
6690 }
6691
6692 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6693
6694 static void intel_crtc_idle_timer(unsigned long arg)
6695 {
6696         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6697         struct drm_crtc *crtc = &intel_crtc->base;
6698         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6699         struct intel_framebuffer *intel_fb;
6700
6701         intel_fb = to_intel_framebuffer(crtc->fb);
6702         if (intel_fb && intel_fb->obj->active) {
6703                 /* The framebuffer is still being accessed by the GPU. */
6704                 mod_timer(&intel_crtc->idle_timer, jiffies +
6705                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6706                 return;
6707         }
6708
6709         intel_crtc->busy = false;
6710         queue_work(dev_priv->wq, &dev_priv->idle_work);
6711 }
6712
6713 static void intel_increase_pllclock(struct drm_crtc *crtc)
6714 {
6715         struct drm_device *dev = crtc->dev;
6716         drm_i915_private_t *dev_priv = dev->dev_private;
6717         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6718         int pipe = intel_crtc->pipe;
6719         int dpll_reg = DPLL(pipe);
6720         int dpll;
6721
6722         if (HAS_PCH_SPLIT(dev))
6723                 return;
6724
6725         if (!dev_priv->lvds_downclock_avail)
6726                 return;
6727
6728         dpll = I915_READ(dpll_reg);
6729         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6730                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6731
6732                 /* Unlock panel regs */
6733                 I915_WRITE(PP_CONTROL,
6734                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6735
6736                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6737                 I915_WRITE(dpll_reg, dpll);
6738                 intel_wait_for_vblank(dev, pipe);
6739
6740                 dpll = I915_READ(dpll_reg);
6741                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6742                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6743
6744                 /* ...and lock them again */
6745                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6746         }
6747
6748         /* Schedule downclock */
6749         mod_timer(&intel_crtc->idle_timer, jiffies +
6750                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6751 }
6752
6753 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6754 {
6755         struct drm_device *dev = crtc->dev;
6756         drm_i915_private_t *dev_priv = dev->dev_private;
6757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6758         int pipe = intel_crtc->pipe;
6759         int dpll_reg = DPLL(pipe);
6760         int dpll = I915_READ(dpll_reg);
6761
6762         if (HAS_PCH_SPLIT(dev))
6763                 return;
6764
6765         if (!dev_priv->lvds_downclock_avail)
6766                 return;
6767
6768         /*
6769          * Since this is called by a timer, we should never get here in
6770          * the manual case.
6771          */
6772         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6773                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6774
6775                 /* Unlock panel regs */
6776                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6777                            PANEL_UNLOCK_REGS);
6778
6779                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6780                 I915_WRITE(dpll_reg, dpll);
6781                 intel_wait_for_vblank(dev, pipe);
6782                 dpll = I915_READ(dpll_reg);
6783                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6784                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6785
6786                 /* ...and lock them again */
6787                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6788         }
6789
6790 }
6791
6792 /**
6793  * intel_idle_update - adjust clocks for idleness
6794  * @work: work struct
6795  *
6796  * Either the GPU or display (or both) went idle.  Check the busy status
6797  * here and adjust the CRTC and GPU clocks as necessary.
6798  */
6799 static void intel_idle_update(struct work_struct *work)
6800 {
6801         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6802                                                     idle_work);
6803         struct drm_device *dev = dev_priv->dev;
6804         struct drm_crtc *crtc;
6805         struct intel_crtc *intel_crtc;
6806
6807         if (!i915_powersave)
6808                 return;
6809
6810         mutex_lock(&dev->struct_mutex);
6811
6812         i915_update_gfx_val(dev_priv);
6813
6814         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6815                 /* Skip inactive CRTCs */
6816                 if (!crtc->fb)
6817                         continue;
6818
6819                 intel_crtc = to_intel_crtc(crtc);
6820                 if (!intel_crtc->busy)
6821                         intel_decrease_pllclock(crtc);
6822         }
6823
6824
6825         mutex_unlock(&dev->struct_mutex);
6826 }
6827
6828 /**
6829  * intel_mark_busy - mark the GPU and possibly the display busy
6830  * @dev: drm device
6831  * @obj: object we're operating on
6832  *
6833  * Callers can use this function to indicate that the GPU is busy processing
6834  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6835  * buffer), we'll also mark the display as busy, so we know to increase its
6836  * clock frequency.
6837  */
6838 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6839 {
6840         drm_i915_private_t *dev_priv = dev->dev_private;
6841         struct drm_crtc *crtc = NULL;
6842         struct intel_framebuffer *intel_fb;
6843         struct intel_crtc *intel_crtc;
6844
6845         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6846                 return;
6847
6848         if (!dev_priv->busy)
6849                 dev_priv->busy = true;
6850         else
6851                 mod_timer(&dev_priv->idle_timer, jiffies +
6852                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6853
6854         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6855                 if (!crtc->fb)
6856                         continue;
6857
6858                 intel_crtc = to_intel_crtc(crtc);
6859                 intel_fb = to_intel_framebuffer(crtc->fb);
6860                 if (intel_fb->obj == obj) {
6861                         if (!intel_crtc->busy) {
6862                                 /* Non-busy -> busy, upclock */
6863                                 intel_increase_pllclock(crtc);
6864                                 intel_crtc->busy = true;
6865                         } else {
6866                                 /* Busy -> busy, put off timer */
6867                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6868                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6869                         }
6870                 }
6871         }
6872 }
6873
6874 static void intel_crtc_destroy(struct drm_crtc *crtc)
6875 {
6876         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6877         struct drm_device *dev = crtc->dev;
6878         struct intel_unpin_work *work;
6879         unsigned long flags;
6880
6881         spin_lock_irqsave(&dev->event_lock, flags);
6882         work = intel_crtc->unpin_work;
6883         intel_crtc->unpin_work = NULL;
6884         spin_unlock_irqrestore(&dev->event_lock, flags);
6885
6886         if (work) {
6887                 cancel_work_sync(&work->work);
6888                 kfree(work);
6889         }
6890
6891         drm_crtc_cleanup(crtc);
6892
6893         kfree(intel_crtc);
6894 }
6895
6896 static void intel_unpin_work_fn(struct work_struct *__work)
6897 {
6898         struct intel_unpin_work *work =
6899                 container_of(__work, struct intel_unpin_work, work);
6900
6901         mutex_lock(&work->dev->struct_mutex);
6902         i915_gem_object_unpin(work->old_fb_obj);
6903         drm_gem_object_unreference(&work->pending_flip_obj->base);
6904         drm_gem_object_unreference(&work->old_fb_obj->base);
6905
6906         intel_update_fbc(work->dev);
6907         mutex_unlock(&work->dev->struct_mutex);
6908         kfree(work);
6909 }
6910
6911 static void do_intel_finish_page_flip(struct drm_device *dev,
6912                                       struct drm_crtc *crtc)
6913 {
6914         drm_i915_private_t *dev_priv = dev->dev_private;
6915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6916         struct intel_unpin_work *work;
6917         struct drm_i915_gem_object *obj;
6918         struct drm_pending_vblank_event *e;
6919         struct timeval tnow, tvbl;
6920         unsigned long flags;
6921
6922         /* Ignore early vblank irqs */
6923         if (intel_crtc == NULL)
6924                 return;
6925
6926         do_gettimeofday(&tnow);
6927
6928         spin_lock_irqsave(&dev->event_lock, flags);
6929         work = intel_crtc->unpin_work;
6930
6931         /* Ensure we don't miss a work->pending update ... */
6932         smp_rmb();
6933
6934         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6935                 spin_unlock_irqrestore(&dev->event_lock, flags);
6936                 return;
6937         }
6938
6939         /* and that the unpin work is consistent wrt ->pending. */
6940         smp_rmb();
6941
6942         intel_crtc->unpin_work = NULL;
6943
6944         if (work->event) {
6945                 e = work->event;
6946                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6947
6948                 /* Called before vblank count and timestamps have
6949                  * been updated for the vblank interval of flip
6950                  * completion? Need to increment vblank count and
6951                  * add one videorefresh duration to returned timestamp
6952                  * to account for this. We assume this happened if we
6953                  * get called over 0.9 frame durations after the last
6954                  * timestamped vblank.
6955                  *
6956                  * This calculation can not be used with vrefresh rates
6957                  * below 5Hz (10Hz to be on the safe side) without
6958                  * promoting to 64 integers.
6959                  */
6960                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6961                     9 * crtc->framedur_ns) {
6962                         e->event.sequence++;
6963                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6964                                              crtc->framedur_ns);
6965                 }
6966
6967                 e->event.tv_sec = tvbl.tv_sec;
6968                 e->event.tv_usec = tvbl.tv_usec;
6969
6970                 list_add_tail(&e->base.link,
6971                               &e->base.file_priv->event_list);
6972                 wake_up_interruptible(&e->base.file_priv->event_wait);
6973         }
6974
6975         drm_vblank_put(dev, intel_crtc->pipe);
6976
6977         spin_unlock_irqrestore(&dev->event_lock, flags);
6978
6979         obj = work->old_fb_obj;
6980
6981         atomic_clear_mask(1 << intel_crtc->plane,
6982                           &obj->pending_flip.counter);
6983
6984         wake_up(&dev_priv->pending_flip_queue);
6985         schedule_work(&work->work);
6986
6987         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6988 }
6989
6990 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6991 {
6992         drm_i915_private_t *dev_priv = dev->dev_private;
6993         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6994
6995         do_intel_finish_page_flip(dev, crtc);
6996 }
6997
6998 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6999 {
7000         drm_i915_private_t *dev_priv = dev->dev_private;
7001         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7002
7003         do_intel_finish_page_flip(dev, crtc);
7004 }
7005
7006 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7007 {
7008         drm_i915_private_t *dev_priv = dev->dev_private;
7009         struct intel_crtc *intel_crtc =
7010                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7011         unsigned long flags;
7012
7013         /* NB: An MMIO update of the plane base pointer will also
7014          * generate a page-flip completion irq, i.e. every modeset
7015          * is also accompanied by a spurious intel_prepare_page_flip().
7016          */
7017         spin_lock_irqsave(&dev->event_lock, flags);
7018         if (intel_crtc->unpin_work)
7019                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7020         spin_unlock_irqrestore(&dev->event_lock, flags);
7021 }
7022
7023 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7024 {
7025         /* Ensure that the work item is consistent when activating it ... */
7026         smp_wmb();
7027         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7028         /* and that it is marked active as soon as the irq could fire. */
7029         smp_wmb();
7030 }
7031
7032 static int intel_gen2_queue_flip(struct drm_device *dev,
7033                                  struct drm_crtc *crtc,
7034                                  struct drm_framebuffer *fb,
7035                                  struct drm_i915_gem_object *obj)
7036 {
7037         struct drm_i915_private *dev_priv = dev->dev_private;
7038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7039         unsigned long offset;
7040         u32 flip_mask;
7041         int ret;
7042
7043         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7044         if (ret)
7045                 goto err;
7046
7047         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7048         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7049
7050         ret = BEGIN_LP_RING(6);
7051         if (ret)
7052                 goto err_unpin;
7053
7054         /* Can't queue multiple flips, so wait for the previous
7055          * one to finish before executing the next.
7056          */
7057         if (intel_crtc->plane)
7058                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7059         else
7060                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7061         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7062         OUT_RING(MI_NOOP);
7063         OUT_RING(MI_DISPLAY_FLIP |
7064                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7065         OUT_RING(fb->pitch);
7066         OUT_RING(obj->gtt_offset + offset);
7067         OUT_RING(MI_NOOP);
7068
7069         intel_mark_page_flip_active(intel_crtc);
7070         ADVANCE_LP_RING();
7071         return 0;
7072
7073 err_unpin:
7074         i915_gem_object_unpin(obj);
7075 err:
7076         return ret;
7077 }
7078
7079 static int intel_gen3_queue_flip(struct drm_device *dev,
7080                                  struct drm_crtc *crtc,
7081                                  struct drm_framebuffer *fb,
7082                                  struct drm_i915_gem_object *obj)
7083 {
7084         struct drm_i915_private *dev_priv = dev->dev_private;
7085         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7086         unsigned long offset;
7087         u32 flip_mask;
7088         int ret;
7089
7090         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7091         if (ret)
7092                 goto err;
7093
7094         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7095         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7096
7097         ret = BEGIN_LP_RING(6);
7098         if (ret)
7099                 goto err_unpin;
7100
7101         if (intel_crtc->plane)
7102                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7103         else
7104                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7105         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7106         OUT_RING(MI_NOOP);
7107         OUT_RING(MI_DISPLAY_FLIP_I915 |
7108                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7109         OUT_RING(fb->pitch);
7110         OUT_RING(obj->gtt_offset + offset);
7111         OUT_RING(MI_NOOP);
7112
7113         intel_mark_page_flip_active(intel_crtc);
7114         ADVANCE_LP_RING();
7115         return 0;
7116
7117 err_unpin:
7118         i915_gem_object_unpin(obj);
7119 err:
7120         return ret;
7121 }
7122
7123 static int intel_gen4_queue_flip(struct drm_device *dev,
7124                                  struct drm_crtc *crtc,
7125                                  struct drm_framebuffer *fb,
7126                                  struct drm_i915_gem_object *obj)
7127 {
7128         struct drm_i915_private *dev_priv = dev->dev_private;
7129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7130         uint32_t pf, pipesrc;
7131         int ret;
7132
7133         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7134         if (ret)
7135                 goto err;
7136
7137         ret = BEGIN_LP_RING(4);
7138         if (ret)
7139                 goto err_unpin;
7140
7141         /* i965+ uses the linear or tiled offsets from the
7142          * Display Registers (which do not change across a page-flip)
7143          * so we need only reprogram the base address.
7144          */
7145         OUT_RING(MI_DISPLAY_FLIP |
7146                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7147         OUT_RING(fb->pitch);
7148         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7149
7150         /* XXX Enabling the panel-fitter across page-flip is so far
7151          * untested on non-native modes, so ignore it for now.
7152          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7153          */
7154         pf = 0;
7155         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7156         OUT_RING(pf | pipesrc);
7157
7158         intel_mark_page_flip_active(intel_crtc);
7159
7160         intel_mark_page_flip_active(intel_crtc);
7161         ADVANCE_LP_RING();
7162         return 0;
7163
7164 err_unpin:
7165         i915_gem_object_unpin(obj);
7166 err:
7167         return ret;
7168 }
7169
7170 static int intel_gen6_queue_flip(struct drm_device *dev,
7171                                  struct drm_crtc *crtc,
7172                                  struct drm_framebuffer *fb,
7173                                  struct drm_i915_gem_object *obj)
7174 {
7175         struct drm_i915_private *dev_priv = dev->dev_private;
7176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7177         uint32_t pf, pipesrc;
7178         int ret;
7179
7180         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7181         if (ret)
7182                 goto err;
7183
7184         ret = BEGIN_LP_RING(4);
7185         if (ret)
7186                 goto err_unpin;
7187
7188         OUT_RING(MI_DISPLAY_FLIP |
7189                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7190         OUT_RING(fb->pitch | obj->tiling_mode);
7191         OUT_RING(obj->gtt_offset);
7192
7193         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7194         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7195         OUT_RING(pf | pipesrc);
7196         ADVANCE_LP_RING();
7197         return 0;
7198
7199 err_unpin:
7200         i915_gem_object_unpin(obj);
7201 err:
7202         return ret;
7203 }
7204
7205 /*
7206  * On gen7 we currently use the blit ring because (in early silicon at least)
7207  * the render ring doesn't give us interrpts for page flip completion, which
7208  * means clients will hang after the first flip is queued.  Fortunately the
7209  * blit ring generates interrupts properly, so use it instead.
7210  */
7211 static int intel_gen7_queue_flip(struct drm_device *dev,
7212                                  struct drm_crtc *crtc,
7213                                  struct drm_framebuffer *fb,
7214                                  struct drm_i915_gem_object *obj)
7215 {
7216         struct drm_i915_private *dev_priv = dev->dev_private;
7217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7218         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7219         uint32_t plane_bit = 0;
7220         int ret;
7221
7222         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7223         if (ret)
7224                 goto err;
7225
7226         switch(intel_crtc->plane) {
7227         case PLANE_A:
7228                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7229                 break;
7230         case PLANE_B:
7231                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7232                 break;
7233         case PLANE_C:
7234                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7235                 break;
7236         default:
7237                 WARN_ONCE(1, "unknown plane in flip command\n");
7238                 ret = -ENODEV;
7239                 goto err_unpin;
7240         }
7241
7242         ret = intel_ring_begin(ring, 4);
7243         if (ret)
7244                 goto err_unpin;
7245
7246         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7247         intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
7248         intel_ring_emit(ring, (obj->gtt_offset));
7249         intel_ring_emit(ring, (MI_NOOP));
7250
7251         intel_mark_page_flip_active(intel_crtc);
7252         intel_ring_advance(ring);
7253         return 0;
7254
7255 err_unpin:
7256         i915_gem_object_unpin(obj);
7257 err:
7258         return ret;
7259 }
7260
7261 static int intel_default_queue_flip(struct drm_device *dev,
7262                                     struct drm_crtc *crtc,
7263                                     struct drm_framebuffer *fb,
7264                                     struct drm_i915_gem_object *obj)
7265 {
7266         return -ENODEV;
7267 }
7268
7269 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7270                                 struct drm_framebuffer *fb,
7271                                 struct drm_pending_vblank_event *event)
7272 {
7273         struct drm_device *dev = crtc->dev;
7274         struct drm_i915_private *dev_priv = dev->dev_private;
7275         struct intel_framebuffer *intel_fb;
7276         struct drm_i915_gem_object *obj;
7277         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7278         struct intel_unpin_work *work;
7279         unsigned long flags;
7280         int ret;
7281
7282         work = kzalloc(sizeof *work, GFP_KERNEL);
7283         if (work == NULL)
7284                 return -ENOMEM;
7285
7286         work->event = event;
7287         work->dev = crtc->dev;
7288         intel_fb = to_intel_framebuffer(crtc->fb);
7289         work->old_fb_obj = intel_fb->obj;
7290         INIT_WORK(&work->work, intel_unpin_work_fn);
7291
7292         ret = drm_vblank_get(dev, intel_crtc->pipe);
7293         if (ret)
7294                 goto free_work;
7295
7296         /* We borrow the event spin lock for protecting unpin_work */
7297         spin_lock_irqsave(&dev->event_lock, flags);
7298         if (intel_crtc->unpin_work) {
7299                 spin_unlock_irqrestore(&dev->event_lock, flags);
7300                 kfree(work);
7301                 drm_vblank_put(dev, intel_crtc->pipe);
7302
7303                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7304                 return -EBUSY;
7305         }
7306         intel_crtc->unpin_work = work;
7307         spin_unlock_irqrestore(&dev->event_lock, flags);
7308
7309         intel_fb = to_intel_framebuffer(fb);
7310         obj = intel_fb->obj;
7311
7312         mutex_lock(&dev->struct_mutex);
7313
7314         /* Reference the objects for the scheduled work. */
7315         drm_gem_object_reference(&work->old_fb_obj->base);
7316         drm_gem_object_reference(&obj->base);
7317
7318         crtc->fb = fb;
7319
7320         work->pending_flip_obj = obj;
7321
7322         work->enable_stall_check = true;
7323
7324         /* Block clients from rendering to the new back buffer until
7325          * the flip occurs and the object is no longer visible.
7326          */
7327         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7328
7329         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7330         if (ret)
7331                 goto cleanup_pending;
7332
7333         intel_disable_fbc(dev);
7334         mutex_unlock(&dev->struct_mutex);
7335
7336         trace_i915_flip_request(intel_crtc->plane, obj);
7337
7338         return 0;
7339
7340 cleanup_pending:
7341         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7342         drm_gem_object_unreference(&work->old_fb_obj->base);
7343         drm_gem_object_unreference(&obj->base);
7344         mutex_unlock(&dev->struct_mutex);
7345
7346         spin_lock_irqsave(&dev->event_lock, flags);
7347         intel_crtc->unpin_work = NULL;
7348         spin_unlock_irqrestore(&dev->event_lock, flags);
7349
7350         drm_vblank_put(dev, intel_crtc->pipe);
7351 free_work:
7352         kfree(work);
7353
7354         return ret;
7355 }
7356
7357 static void intel_sanitize_modesetting(struct drm_device *dev,
7358                                        int pipe, int plane)
7359 {
7360         struct drm_i915_private *dev_priv = dev->dev_private;
7361         u32 reg, val;
7362         int i;
7363
7364         /* Clear any frame start delays used for debugging left by the BIOS */
7365         for_each_pipe(i) {
7366                 reg = PIPECONF(i);
7367                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7368         }
7369
7370         if (HAS_PCH_SPLIT(dev))
7371                 return;
7372
7373         /* Who knows what state these registers were left in by the BIOS or
7374          * grub?
7375          *
7376          * If we leave the registers in a conflicting state (e.g. with the
7377          * display plane reading from the other pipe than the one we intend
7378          * to use) then when we attempt to teardown the active mode, we will
7379          * not disable the pipes and planes in the correct order -- leaving
7380          * a plane reading from a disabled pipe and possibly leading to
7381          * undefined behaviour.
7382          */
7383
7384         reg = DSPCNTR(plane);
7385         val = I915_READ(reg);
7386
7387         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7388                 return;
7389         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7390                 return;
7391
7392         /* This display plane is active and attached to the other CPU pipe. */
7393         pipe = !pipe;
7394
7395         /* Disable the plane and wait for it to stop reading from the pipe. */
7396         intel_disable_plane(dev_priv, plane, pipe);
7397         intel_disable_pipe(dev_priv, pipe);
7398 }
7399
7400 static void intel_crtc_reset(struct drm_crtc *crtc)
7401 {
7402         struct drm_device *dev = crtc->dev;
7403         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7404
7405         /* Reset flags back to the 'unknown' status so that they
7406          * will be correctly set on the initial modeset.
7407          */
7408         intel_crtc->dpms_mode = -1;
7409
7410         /* We need to fix up any BIOS configuration that conflicts with
7411          * our expectations.
7412          */
7413         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7414 }
7415
7416 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7417         .dpms = intel_crtc_dpms,
7418         .mode_fixup = intel_crtc_mode_fixup,
7419         .mode_set = intel_crtc_mode_set,
7420         .mode_set_base = intel_pipe_set_base,
7421         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7422         .load_lut = intel_crtc_load_lut,
7423         .disable = intel_crtc_disable,
7424 };
7425
7426 static const struct drm_crtc_funcs intel_crtc_funcs = {
7427         .reset = intel_crtc_reset,
7428         .cursor_set = intel_crtc_cursor_set,
7429         .cursor_move = intel_crtc_cursor_move,
7430         .gamma_set = intel_crtc_gamma_set,
7431         .set_config = drm_crtc_helper_set_config,
7432         .destroy = intel_crtc_destroy,
7433         .page_flip = intel_crtc_page_flip,
7434 };
7435
7436 static void intel_crtc_init(struct drm_device *dev, int pipe)
7437 {
7438         drm_i915_private_t *dev_priv = dev->dev_private;
7439         struct intel_crtc *intel_crtc;
7440         int i;
7441
7442         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7443         if (intel_crtc == NULL)
7444                 return;
7445
7446         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7447
7448         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7449         for (i = 0; i < 256; i++) {
7450                 intel_crtc->lut_r[i] = i;
7451                 intel_crtc->lut_g[i] = i;
7452                 intel_crtc->lut_b[i] = i;
7453         }
7454
7455         /* Swap pipes & planes for FBC on pre-965 */
7456         intel_crtc->pipe = pipe;
7457         intel_crtc->plane = pipe;
7458         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7459                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7460                 intel_crtc->plane = !pipe;
7461         }
7462
7463         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7464                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7465         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7466         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7467
7468         intel_crtc_reset(&intel_crtc->base);
7469         intel_crtc->active = true; /* force the pipe off on setup_init_config */
7470         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7471
7472         if (HAS_PCH_SPLIT(dev)) {
7473                 if (pipe == 2 && IS_IVYBRIDGE(dev))
7474                         intel_crtc->no_pll = true;
7475                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7476                 intel_helper_funcs.commit = ironlake_crtc_commit;
7477         } else {
7478                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7479                 intel_helper_funcs.commit = i9xx_crtc_commit;
7480         }
7481
7482         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7483
7484         intel_crtc->busy = false;
7485
7486         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7487                     (unsigned long)intel_crtc);
7488 }
7489
7490 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7491                                 struct drm_file *file)
7492 {
7493         drm_i915_private_t *dev_priv = dev->dev_private;
7494         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7495         struct drm_mode_object *drmmode_obj;
7496         struct intel_crtc *crtc;
7497
7498         if (!dev_priv) {
7499                 DRM_ERROR("called with no initialization\n");
7500                 return -EINVAL;
7501         }
7502
7503         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7504                         DRM_MODE_OBJECT_CRTC);
7505
7506         if (!drmmode_obj) {
7507                 DRM_ERROR("no such CRTC id\n");
7508                 return -EINVAL;
7509         }
7510
7511         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7512         pipe_from_crtc_id->pipe = crtc->pipe;
7513
7514         return 0;
7515 }
7516
7517 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7518 {
7519         struct intel_encoder *encoder;
7520         int index_mask = 0;
7521         int entry = 0;
7522
7523         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7524                 if (type_mask & encoder->clone_mask)
7525                         index_mask |= (1 << entry);
7526                 entry++;
7527         }
7528
7529         return index_mask;
7530 }
7531
7532 static bool has_edp_a(struct drm_device *dev)
7533 {
7534         struct drm_i915_private *dev_priv = dev->dev_private;
7535
7536         if (!IS_MOBILE(dev))
7537                 return false;
7538
7539         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7540                 return false;
7541
7542         if (IS_GEN5(dev) &&
7543             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7544                 return false;
7545
7546         return true;
7547 }
7548
7549 static void intel_setup_outputs(struct drm_device *dev)
7550 {
7551         struct drm_i915_private *dev_priv = dev->dev_private;
7552         struct intel_encoder *encoder;
7553         bool dpd_is_edp = false;
7554         bool has_lvds = false;
7555
7556         if (IS_MOBILE(dev) && !IS_I830(dev))
7557                 has_lvds = intel_lvds_init(dev);
7558         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7559                 /* disable the panel fitter on everything but LVDS */
7560                 I915_WRITE(PFIT_CONTROL, 0);
7561         }
7562
7563         if (HAS_PCH_SPLIT(dev)) {
7564                 dpd_is_edp = intel_dpd_is_edp(dev);
7565
7566                 if (has_edp_a(dev))
7567                         intel_dp_init(dev, DP_A);
7568
7569                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7570                         intel_dp_init(dev, PCH_DP_D);
7571         }
7572
7573         intel_crt_init(dev);
7574
7575         if (HAS_PCH_SPLIT(dev)) {
7576                 int found;
7577
7578                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7579                         /* PCH SDVOB multiplex with HDMIB */
7580                         found = intel_sdvo_init(dev, PCH_SDVOB);
7581                         if (!found)
7582                                 intel_hdmi_init(dev, HDMIB);
7583                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7584                                 intel_dp_init(dev, PCH_DP_B);
7585                 }
7586
7587                 if (I915_READ(HDMIC) & PORT_DETECTED)
7588                         intel_hdmi_init(dev, HDMIC);
7589
7590                 if (I915_READ(HDMID) & PORT_DETECTED)
7591                         intel_hdmi_init(dev, HDMID);
7592
7593                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7594                         intel_dp_init(dev, PCH_DP_C);
7595
7596                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7597                         intel_dp_init(dev, PCH_DP_D);
7598
7599         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7600                 bool found = false;
7601
7602                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7603                         DRM_DEBUG_KMS("probing SDVOB\n");
7604                         found = intel_sdvo_init(dev, SDVOB);
7605                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7606                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7607                                 intel_hdmi_init(dev, SDVOB);
7608                         }
7609
7610                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7611                                 DRM_DEBUG_KMS("probing DP_B\n");
7612                                 intel_dp_init(dev, DP_B);
7613                         }
7614                 }
7615
7616                 /* Before G4X SDVOC doesn't have its own detect register */
7617
7618                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7619                         DRM_DEBUG_KMS("probing SDVOC\n");
7620                         found = intel_sdvo_init(dev, SDVOC);
7621                 }
7622
7623                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7624
7625                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7626                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7627                                 intel_hdmi_init(dev, SDVOC);
7628                         }
7629                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7630                                 DRM_DEBUG_KMS("probing DP_C\n");
7631                                 intel_dp_init(dev, DP_C);
7632                         }
7633                 }
7634
7635                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7636                     (I915_READ(DP_D) & DP_DETECTED)) {
7637                         DRM_DEBUG_KMS("probing DP_D\n");
7638                         intel_dp_init(dev, DP_D);
7639                 }
7640         } else if (IS_GEN2(dev))
7641                 intel_dvo_init(dev);
7642
7643         if (SUPPORTS_TV(dev))
7644                 intel_tv_init(dev);
7645
7646         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7647                 encoder->base.possible_crtcs = encoder->crtc_mask;
7648                 encoder->base.possible_clones =
7649                         intel_encoder_clones(dev, encoder->clone_mask);
7650         }
7651
7652         /* disable all the possible outputs/crtcs before entering KMS mode */
7653         drm_helper_disable_unused_functions(dev);
7654
7655         if (HAS_PCH_SPLIT(dev))
7656                 ironlake_init_pch_refclk(dev);
7657 }
7658
7659 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7660 {
7661         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7662
7663         drm_framebuffer_cleanup(fb);
7664         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7665
7666         kfree(intel_fb);
7667 }
7668
7669 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7670                                                 struct drm_file *file,
7671                                                 unsigned int *handle)
7672 {
7673         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7674         struct drm_i915_gem_object *obj = intel_fb->obj;
7675
7676         return drm_gem_handle_create(file, &obj->base, handle);
7677 }
7678
7679 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7680         .destroy = intel_user_framebuffer_destroy,
7681         .create_handle = intel_user_framebuffer_create_handle,
7682 };
7683
7684 int intel_framebuffer_init(struct drm_device *dev,
7685                            struct intel_framebuffer *intel_fb,
7686                            struct drm_mode_fb_cmd *mode_cmd,
7687                            struct drm_i915_gem_object *obj)
7688 {
7689         int ret;
7690
7691         if (obj->tiling_mode == I915_TILING_Y)
7692                 return -EINVAL;
7693
7694         if (mode_cmd->pitch & 63)
7695                 return -EINVAL;
7696
7697         switch (mode_cmd->bpp) {
7698         case 8:
7699         case 16:
7700                 /* Only pre-ILK can handle 5:5:5 */
7701                 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7702                         return -EINVAL;
7703                 break;
7704
7705         case 24:
7706         case 32:
7707                 break;
7708         default:
7709                 return -EINVAL;
7710         }
7711
7712         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7713         if (ret) {
7714                 DRM_ERROR("framebuffer init failed %d\n", ret);
7715                 return ret;
7716         }
7717
7718         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7719         intel_fb->obj = obj;
7720         return 0;
7721 }
7722
7723 static struct drm_framebuffer *
7724 intel_user_framebuffer_create(struct drm_device *dev,
7725                               struct drm_file *filp,
7726                               struct drm_mode_fb_cmd *mode_cmd)
7727 {
7728         struct drm_i915_gem_object *obj;
7729
7730         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7731         if (&obj->base == NULL)
7732                 return ERR_PTR(-ENOENT);
7733
7734         return intel_framebuffer_create(dev, mode_cmd, obj);
7735 }
7736
7737 static const struct drm_mode_config_funcs intel_mode_funcs = {
7738         .fb_create = intel_user_framebuffer_create,
7739         .output_poll_changed = intel_fb_output_poll_changed,
7740 };
7741
7742 static struct drm_i915_gem_object *
7743 intel_alloc_context_page(struct drm_device *dev)
7744 {
7745         struct drm_i915_gem_object *ctx;
7746         int ret;
7747
7748         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7749
7750         ctx = i915_gem_alloc_object(dev, 4096);
7751         if (!ctx) {
7752                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7753                 return NULL;
7754         }
7755
7756         ret = i915_gem_object_pin(ctx, 4096, true);
7757         if (ret) {
7758                 DRM_ERROR("failed to pin power context: %d\n", ret);
7759                 goto err_unref;
7760         }
7761
7762         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7763         if (ret) {
7764                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7765                 goto err_unpin;
7766         }
7767
7768         return ctx;
7769
7770 err_unpin:
7771         i915_gem_object_unpin(ctx);
7772 err_unref:
7773         drm_gem_object_unreference(&ctx->base);
7774         mutex_unlock(&dev->struct_mutex);
7775         return NULL;
7776 }
7777
7778 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7779 {
7780         struct drm_i915_private *dev_priv = dev->dev_private;
7781         u16 rgvswctl;
7782
7783         rgvswctl = I915_READ16(MEMSWCTL);
7784         if (rgvswctl & MEMCTL_CMD_STS) {
7785                 DRM_DEBUG("gpu busy, RCS change rejected\n");
7786                 return false; /* still busy with another command */
7787         }
7788
7789         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7790                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7791         I915_WRITE16(MEMSWCTL, rgvswctl);
7792         POSTING_READ16(MEMSWCTL);
7793
7794         rgvswctl |= MEMCTL_CMD_STS;
7795         I915_WRITE16(MEMSWCTL, rgvswctl);
7796
7797         return true;
7798 }
7799
7800 void ironlake_enable_drps(struct drm_device *dev)
7801 {
7802         struct drm_i915_private *dev_priv = dev->dev_private;
7803         u32 rgvmodectl = I915_READ(MEMMODECTL);
7804         u8 fmax, fmin, fstart, vstart;
7805
7806         /* Enable temp reporting */
7807         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7808         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7809
7810         /* 100ms RC evaluation intervals */
7811         I915_WRITE(RCUPEI, 100000);
7812         I915_WRITE(RCDNEI, 100000);
7813
7814         /* Set max/min thresholds to 90ms and 80ms respectively */
7815         I915_WRITE(RCBMAXAVG, 90000);
7816         I915_WRITE(RCBMINAVG, 80000);
7817
7818         I915_WRITE(MEMIHYST, 1);
7819
7820         /* Set up min, max, and cur for interrupt handling */
7821         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7822         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7823         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7824                 MEMMODE_FSTART_SHIFT;
7825
7826         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7827                 PXVFREQ_PX_SHIFT;
7828
7829         dev_priv->fmax = fmax; /* IPS callback will increase this */
7830         dev_priv->fstart = fstart;
7831
7832         dev_priv->max_delay = fstart;
7833         dev_priv->min_delay = fmin;
7834         dev_priv->cur_delay = fstart;
7835
7836         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7837                          fmax, fmin, fstart);
7838
7839         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7840
7841         /*
7842          * Interrupts will be enabled in ironlake_irq_postinstall
7843          */
7844
7845         I915_WRITE(VIDSTART, vstart);
7846         POSTING_READ(VIDSTART);
7847
7848         rgvmodectl |= MEMMODE_SWMODE_EN;
7849         I915_WRITE(MEMMODECTL, rgvmodectl);
7850
7851         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7852                 DRM_ERROR("stuck trying to change perf mode\n");
7853         msleep(1);
7854
7855         ironlake_set_drps(dev, fstart);
7856
7857         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7858                 I915_READ(0x112e0);
7859         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7860         dev_priv->last_count2 = I915_READ(0x112f4);
7861         getrawmonotonic(&dev_priv->last_time2);
7862 }
7863
7864 void ironlake_disable_drps(struct drm_device *dev)
7865 {
7866         struct drm_i915_private *dev_priv = dev->dev_private;
7867         u16 rgvswctl = I915_READ16(MEMSWCTL);
7868
7869         /* Ack interrupts, disable EFC interrupt */
7870         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7871         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7872         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7873         I915_WRITE(DEIIR, DE_PCU_EVENT);
7874         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7875
7876         /* Go back to the starting frequency */
7877         ironlake_set_drps(dev, dev_priv->fstart);
7878         msleep(1);
7879         rgvswctl |= MEMCTL_CMD_STS;
7880         I915_WRITE(MEMSWCTL, rgvswctl);
7881         msleep(1);
7882
7883 }
7884
7885 void gen6_set_rps(struct drm_device *dev, u8 val)
7886 {
7887         struct drm_i915_private *dev_priv = dev->dev_private;
7888         u32 swreq;
7889
7890         swreq = (val & 0x3ff) << 25;
7891         I915_WRITE(GEN6_RPNSWREQ, swreq);
7892 }
7893
7894 void gen6_disable_rps(struct drm_device *dev)
7895 {
7896         struct drm_i915_private *dev_priv = dev->dev_private;
7897
7898         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7899         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7900         I915_WRITE(GEN6_PMIER, 0);
7901         /* Complete PM interrupt masking here doesn't race with the rps work
7902          * item again unmasking PM interrupts because that is using a different
7903          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
7904          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
7905
7906         spin_lock_irq(&dev_priv->rps_lock);
7907         dev_priv->pm_iir = 0;
7908         spin_unlock_irq(&dev_priv->rps_lock);
7909
7910         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7911 }
7912
7913 static unsigned long intel_pxfreq(u32 vidfreq)
7914 {
7915         unsigned long freq;
7916         int div = (vidfreq & 0x3f0000) >> 16;
7917         int post = (vidfreq & 0x3000) >> 12;
7918         int pre = (vidfreq & 0x7);
7919
7920         if (!pre)
7921                 return 0;
7922
7923         freq = ((div * 133333) / ((1<<post) * pre));
7924
7925         return freq;
7926 }
7927
7928 void intel_init_emon(struct drm_device *dev)
7929 {
7930         struct drm_i915_private *dev_priv = dev->dev_private;
7931         u32 lcfuse;
7932         u8 pxw[16];
7933         int i;
7934
7935         /* Disable to program */
7936         I915_WRITE(ECR, 0);
7937         POSTING_READ(ECR);
7938
7939         /* Program energy weights for various events */
7940         I915_WRITE(SDEW, 0x15040d00);
7941         I915_WRITE(CSIEW0, 0x007f0000);
7942         I915_WRITE(CSIEW1, 0x1e220004);
7943         I915_WRITE(CSIEW2, 0x04000004);
7944
7945         for (i = 0; i < 5; i++)
7946                 I915_WRITE(PEW + (i * 4), 0);
7947         for (i = 0; i < 3; i++)
7948                 I915_WRITE(DEW + (i * 4), 0);
7949
7950         /* Program P-state weights to account for frequency power adjustment */
7951         for (i = 0; i < 16; i++) {
7952                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7953                 unsigned long freq = intel_pxfreq(pxvidfreq);
7954                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7955                         PXVFREQ_PX_SHIFT;
7956                 unsigned long val;
7957
7958                 val = vid * vid;
7959                 val *= (freq / 1000);
7960                 val *= 255;
7961                 val /= (127*127*900);
7962                 if (val > 0xff)
7963                         DRM_ERROR("bad pxval: %ld\n", val);
7964                 pxw[i] = val;
7965         }
7966         /* Render standby states get 0 weight */
7967         pxw[14] = 0;
7968         pxw[15] = 0;
7969
7970         for (i = 0; i < 4; i++) {
7971                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7972                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7973                 I915_WRITE(PXW + (i * 4), val);
7974         }
7975
7976         /* Adjust magic regs to magic values (more experimental results) */
7977         I915_WRITE(OGW0, 0);
7978         I915_WRITE(OGW1, 0);
7979         I915_WRITE(EG0, 0x00007f00);
7980         I915_WRITE(EG1, 0x0000000e);
7981         I915_WRITE(EG2, 0x000e0000);
7982         I915_WRITE(EG3, 0x68000300);
7983         I915_WRITE(EG4, 0x42000000);
7984         I915_WRITE(EG5, 0x00140031);
7985         I915_WRITE(EG6, 0);
7986         I915_WRITE(EG7, 0);
7987
7988         for (i = 0; i < 8; i++)
7989                 I915_WRITE(PXWL + (i * 4), 0);
7990
7991         /* Enable PMON + select events */
7992         I915_WRITE(ECR, 0x80000019);
7993
7994         lcfuse = I915_READ(LCFUSE02);
7995
7996         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7997 }
7998
7999 static bool intel_enable_rc6(struct drm_device *dev)
8000 {
8001         /*
8002          * Respect the kernel parameter if it is set
8003          */
8004         if (i915_enable_rc6 >= 0)
8005                 return i915_enable_rc6;
8006
8007         /*
8008          * Disable RC6 on Ironlake
8009          */
8010         if (INTEL_INFO(dev)->gen == 5)
8011                 return 0;
8012
8013         /*
8014          * Disable rc6 on Sandybridge
8015          */
8016         if (INTEL_INFO(dev)->gen == 6) {
8017                 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8018                 return 0;
8019         }
8020         DRM_DEBUG_DRIVER("RC6 enabled\n");
8021         return 1;
8022 }
8023
8024 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8025 {
8026         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8027         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8028         u32 pcu_mbox, rc6_mask = 0;
8029         int cur_freq, min_freq, max_freq;
8030         int i;
8031
8032         /* Here begins a magic sequence of register writes to enable
8033          * auto-downclocking.
8034          *
8035          * Perhaps there might be some value in exposing these to
8036          * userspace...
8037          */
8038         I915_WRITE(GEN6_RC_STATE, 0);
8039         mutex_lock(&dev_priv->dev->struct_mutex);
8040         gen6_gt_force_wake_get(dev_priv);
8041
8042         /* disable the counters and set deterministic thresholds */
8043         I915_WRITE(GEN6_RC_CONTROL, 0);
8044
8045         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8046         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8047         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8048         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8049         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8050
8051         for (i = 0; i < I915_NUM_RINGS; i++)
8052                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8053
8054         I915_WRITE(GEN6_RC_SLEEP, 0);
8055         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8056         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8057         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8058         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8059
8060         if (intel_enable_rc6(dev_priv->dev))
8061                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
8062                         ((IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0);
8063
8064         I915_WRITE(GEN6_RC_CONTROL,
8065                    rc6_mask |
8066                    GEN6_RC_CTL_EI_MODE(1) |
8067                    GEN6_RC_CTL_HW_ENABLE);
8068
8069         I915_WRITE(GEN6_RPNSWREQ,
8070                    GEN6_FREQUENCY(10) |
8071                    GEN6_OFFSET(0) |
8072                    GEN6_AGGRESSIVE_TURBO);
8073         I915_WRITE(GEN6_RC_VIDEO_FREQ,
8074                    GEN6_FREQUENCY(12));
8075
8076         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8077         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8078                    18 << 24 |
8079                    6 << 16);
8080         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8081         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8082         I915_WRITE(GEN6_RP_UP_EI, 100000);
8083         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8084         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8085         I915_WRITE(GEN6_RP_CONTROL,
8086                    GEN6_RP_MEDIA_TURBO |
8087                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
8088                    GEN6_RP_MEDIA_IS_GFX |
8089                    GEN6_RP_ENABLE |
8090                    GEN6_RP_UP_BUSY_AVG |
8091                    GEN6_RP_DOWN_IDLE_CONT);
8092
8093         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8094                      500))
8095                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8096
8097         I915_WRITE(GEN6_PCODE_DATA, 0);
8098         I915_WRITE(GEN6_PCODE_MAILBOX,
8099                    GEN6_PCODE_READY |
8100                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8101         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8102                      500))
8103                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8104
8105         min_freq = (rp_state_cap & 0xff0000) >> 16;
8106         max_freq = rp_state_cap & 0xff;
8107         cur_freq = (gt_perf_status & 0xff00) >> 8;
8108
8109         /* Check for overclock support */
8110         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8111                      500))
8112                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8113         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8114         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8115         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8116                      500))
8117                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8118         if (pcu_mbox & (1<<31)) { /* OC supported */
8119                 max_freq = pcu_mbox & 0xff;
8120                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8121         }
8122
8123         /* In units of 100MHz */
8124         dev_priv->max_delay = max_freq;
8125         dev_priv->min_delay = min_freq;
8126         dev_priv->cur_delay = cur_freq;
8127
8128         /* requires MSI enabled */
8129         I915_WRITE(GEN6_PMIER,
8130                    GEN6_PM_MBOX_EVENT |
8131                    GEN6_PM_THERMAL_EVENT |
8132                    GEN6_PM_RP_DOWN_TIMEOUT |
8133                    GEN6_PM_RP_UP_THRESHOLD |
8134                    GEN6_PM_RP_DOWN_THRESHOLD |
8135                    GEN6_PM_RP_UP_EI_EXPIRED |
8136                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8137         spin_lock_irq(&dev_priv->rps_lock);
8138         WARN_ON(dev_priv->pm_iir != 0);
8139         I915_WRITE(GEN6_PMIMR, 0);
8140         spin_unlock_irq(&dev_priv->rps_lock);
8141         /* enable all PM interrupts */
8142         I915_WRITE(GEN6_PMINTRMSK, 0);
8143
8144         gen6_gt_force_wake_put(dev_priv);
8145         mutex_unlock(&dev_priv->dev->struct_mutex);
8146 }
8147
8148 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8149 {
8150         int min_freq = 15;
8151         int gpu_freq, ia_freq, max_ia_freq;
8152         int scaling_factor = 180;
8153
8154         max_ia_freq = cpufreq_quick_get_max(0);
8155         /*
8156          * Default to measured freq if none found, PCU will ensure we don't go
8157          * over
8158          */
8159         if (!max_ia_freq)
8160                 max_ia_freq = tsc_khz;
8161
8162         /* Convert from kHz to MHz */
8163         max_ia_freq /= 1000;
8164
8165         mutex_lock(&dev_priv->dev->struct_mutex);
8166
8167         /*
8168          * For each potential GPU frequency, load a ring frequency we'd like
8169          * to use for memory access.  We do this by specifying the IA frequency
8170          * the PCU should use as a reference to determine the ring frequency.
8171          */
8172         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8173              gpu_freq--) {
8174                 int diff = dev_priv->max_delay - gpu_freq;
8175
8176                 /*
8177                  * For GPU frequencies less than 750MHz, just use the lowest
8178                  * ring freq.
8179                  */
8180                 if (gpu_freq < min_freq)
8181                         ia_freq = 800;
8182                 else
8183                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8184                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8185
8186                 I915_WRITE(GEN6_PCODE_DATA,
8187                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8188                            gpu_freq);
8189                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8190                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8191                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8192                               GEN6_PCODE_READY) == 0, 10)) {
8193                         DRM_ERROR("pcode write of freq table timed out\n");
8194                         continue;
8195                 }
8196         }
8197
8198         mutex_unlock(&dev_priv->dev->struct_mutex);
8199 }
8200
8201 static void ironlake_init_clock_gating(struct drm_device *dev)
8202 {
8203         struct drm_i915_private *dev_priv = dev->dev_private;
8204         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8205
8206         /* Required for FBC */
8207         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8208                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8209                 DPFDUNIT_CLOCK_GATE_DISABLE;
8210         /* Required for CxSR */
8211         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8212
8213         I915_WRITE(PCH_3DCGDIS0,
8214                    MARIUNIT_CLOCK_GATE_DISABLE |
8215                    SVSMUNIT_CLOCK_GATE_DISABLE);
8216         I915_WRITE(PCH_3DCGDIS1,
8217                    VFMUNIT_CLOCK_GATE_DISABLE);
8218
8219         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8220
8221         /*
8222          * According to the spec the following bits should be set in
8223          * order to enable memory self-refresh
8224          * The bit 22/21 of 0x42004
8225          * The bit 5 of 0x42020
8226          * The bit 15 of 0x45000
8227          */
8228         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8229                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8230                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8231         I915_WRITE(ILK_DSPCLK_GATE,
8232                    (I915_READ(ILK_DSPCLK_GATE) |
8233                     ILK_DPARB_CLK_GATE));
8234         I915_WRITE(DISP_ARB_CTL,
8235                    (I915_READ(DISP_ARB_CTL) |
8236                     DISP_FBC_WM_DIS));
8237         I915_WRITE(WM3_LP_ILK, 0);
8238         I915_WRITE(WM2_LP_ILK, 0);
8239         I915_WRITE(WM1_LP_ILK, 0);
8240
8241         /*
8242          * Based on the document from hardware guys the following bits
8243          * should be set unconditionally in order to enable FBC.
8244          * The bit 22 of 0x42000
8245          * The bit 22 of 0x42004
8246          * The bit 7,8,9 of 0x42020.
8247          */
8248         if (IS_IRONLAKE_M(dev)) {
8249                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8250                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8251                            ILK_FBCQ_DIS);
8252                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8253                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8254                            ILK_DPARB_GATE);
8255                 I915_WRITE(ILK_DSPCLK_GATE,
8256                            I915_READ(ILK_DSPCLK_GATE) |
8257                            ILK_DPFC_DIS1 |
8258                            ILK_DPFC_DIS2 |
8259                            ILK_CLK_FBC);
8260         }
8261
8262         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8263                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8264                    ILK_ELPIN_409_SELECT);
8265         I915_WRITE(_3D_CHICKEN2,
8266                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8267                    _3D_CHICKEN2_WM_READ_PIPELINED);
8268 }
8269
8270 static void gen6_init_clock_gating(struct drm_device *dev)
8271 {
8272         struct drm_i915_private *dev_priv = dev->dev_private;
8273         int pipe;
8274         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8275
8276         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8277
8278         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8279                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8280                    ILK_ELPIN_409_SELECT);
8281
8282         /* WaDisableHiZPlanesWhenMSAAEnabled */
8283         I915_WRITE(_3D_CHICKEN,
8284                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
8285
8286         I915_WRITE(WM3_LP_ILK, 0);
8287         I915_WRITE(WM2_LP_ILK, 0);
8288         I915_WRITE(WM1_LP_ILK, 0);
8289
8290         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8291          * gating disable must be set.  Failure to set it results in
8292          * flickering pixels due to Z write ordering failures after
8293          * some amount of runtime in the Mesa "fire" demo, and Unigine
8294          * Sanctuary and Tropics, and apparently anything else with
8295          * alpha test or pixel discard.
8296          *
8297          * According to the spec, bit 11 (RCCUNIT) must also be set,
8298          * but we didn't debug actual testcases to find it out.
8299          */
8300         I915_WRITE(GEN6_UCGCTL2,
8301                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8302                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8303
8304         /*
8305          * According to the spec the following bits should be
8306          * set in order to enable memory self-refresh and fbc:
8307          * The bit21 and bit22 of 0x42000
8308          * The bit21 and bit22 of 0x42004
8309          * The bit5 and bit7 of 0x42020
8310          * The bit14 of 0x70180
8311          * The bit14 of 0x71180
8312          */
8313         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8314                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8315                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8316         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8317                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8318                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8319         I915_WRITE(ILK_DSPCLK_GATE,
8320                    I915_READ(ILK_DSPCLK_GATE) |
8321                    ILK_DPARB_CLK_GATE  |
8322                    ILK_DPFD_CLK_GATE);
8323
8324         for_each_pipe(pipe) {
8325                 I915_WRITE(DSPCNTR(pipe),
8326                            I915_READ(DSPCNTR(pipe)) |
8327                            DISPPLANE_TRICKLE_FEED_DISABLE);
8328                 intel_flush_display_plane(dev_priv, pipe);
8329         }
8330
8331         /* The default value should be 0x200 according to docs, but the two
8332          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
8333         I915_WRITE(GEN6_GT_MODE, 0xffff << 16);
8334         I915_WRITE(GEN6_GT_MODE, GEN6_GT_MODE_HI << 16 | GEN6_GT_MODE_HI);
8335 }
8336
8337 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8338 {
8339         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8340
8341         reg &= ~GEN7_FF_SCHED_MASK;
8342         reg |= GEN7_FF_TS_SCHED_HW;
8343         reg |= GEN7_FF_VS_SCHED_HW;
8344         reg |= GEN7_FF_DS_SCHED_HW;
8345
8346         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8347 }
8348
8349 static void ivybridge_init_clock_gating(struct drm_device *dev)
8350 {
8351         struct drm_i915_private *dev_priv = dev->dev_private;
8352         int pipe;
8353         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8354
8355         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8356
8357         I915_WRITE(WM3_LP_ILK, 0);
8358         I915_WRITE(WM2_LP_ILK, 0);
8359         I915_WRITE(WM1_LP_ILK, 0);
8360
8361         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8362          * This implements the WaDisableRCZUnitClockGating workaround.
8363          */
8364         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8365
8366         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8367
8368         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8369         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8370                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8371
8372         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8373         I915_WRITE(GEN7_L3CNTLREG1,
8374                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8375         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8376                         GEN7_WA_L3_CHICKEN_MODE);
8377
8378         /* This is required by WaCatErrorRejectionIssue */
8379         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8380                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8381                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8382
8383         for_each_pipe(pipe) {
8384                 I915_WRITE(DSPCNTR(pipe),
8385                            I915_READ(DSPCNTR(pipe)) |
8386                            DISPPLANE_TRICKLE_FEED_DISABLE);
8387                 intel_flush_display_plane(dev_priv, pipe);
8388         }
8389
8390         gen7_setup_fixed_func_scheduler(dev_priv);
8391 }
8392
8393 static void g4x_init_clock_gating(struct drm_device *dev)
8394 {
8395         struct drm_i915_private *dev_priv = dev->dev_private;
8396         uint32_t dspclk_gate;
8397
8398         I915_WRITE(RENCLK_GATE_D1, 0);
8399         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8400                    GS_UNIT_CLOCK_GATE_DISABLE |
8401                    CL_UNIT_CLOCK_GATE_DISABLE);
8402         I915_WRITE(RAMCLK_GATE_D, 0);
8403         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8404                 OVRUNIT_CLOCK_GATE_DISABLE |
8405                 OVCUNIT_CLOCK_GATE_DISABLE;
8406         if (IS_GM45(dev))
8407                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8408         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8409 }
8410
8411 static void crestline_init_clock_gating(struct drm_device *dev)
8412 {
8413         struct drm_i915_private *dev_priv = dev->dev_private;
8414
8415         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8416         I915_WRITE(RENCLK_GATE_D2, 0);
8417         I915_WRITE(DSPCLK_GATE_D, 0);
8418         I915_WRITE(RAMCLK_GATE_D, 0);
8419         I915_WRITE16(DEUC, 0);
8420 }
8421
8422 static void broadwater_init_clock_gating(struct drm_device *dev)
8423 {
8424         struct drm_i915_private *dev_priv = dev->dev_private;
8425
8426         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8427                    I965_RCC_CLOCK_GATE_DISABLE |
8428                    I965_RCPB_CLOCK_GATE_DISABLE |
8429                    I965_ISC_CLOCK_GATE_DISABLE |
8430                    I965_FBC_CLOCK_GATE_DISABLE);
8431         I915_WRITE(RENCLK_GATE_D2, 0);
8432 }
8433
8434 static void gen3_init_clock_gating(struct drm_device *dev)
8435 {
8436         struct drm_i915_private *dev_priv = dev->dev_private;
8437         u32 dstate = I915_READ(D_STATE);
8438
8439         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8440                 DSTATE_DOT_CLOCK_GATING;
8441         I915_WRITE(D_STATE, dstate);
8442 }
8443
8444 static void i85x_init_clock_gating(struct drm_device *dev)
8445 {
8446         struct drm_i915_private *dev_priv = dev->dev_private;
8447
8448         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8449 }
8450
8451 static void i830_init_clock_gating(struct drm_device *dev)
8452 {
8453         struct drm_i915_private *dev_priv = dev->dev_private;
8454
8455         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8456 }
8457
8458 static void ibx_init_clock_gating(struct drm_device *dev)
8459 {
8460         struct drm_i915_private *dev_priv = dev->dev_private;
8461
8462         /*
8463          * On Ibex Peak and Cougar Point, we need to disable clock
8464          * gating for the panel power sequencer or it will fail to
8465          * start up when no ports are active.
8466          */
8467         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8468 }
8469
8470 static void cpt_init_clock_gating(struct drm_device *dev)
8471 {
8472         struct drm_i915_private *dev_priv = dev->dev_private;
8473         int pipe;
8474
8475         /*
8476          * On Ibex Peak and Cougar Point, we need to disable clock
8477          * gating for the panel power sequencer or it will fail to
8478          * start up when no ports are active.
8479          */
8480         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8481         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8482                    DPLS_EDP_PPS_FIX_DIS);
8483         /* Without this, mode sets may fail silently on FDI */
8484         for_each_pipe(pipe)
8485                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8486 }
8487
8488 static void ironlake_teardown_rc6(struct drm_device *dev)
8489 {
8490         struct drm_i915_private *dev_priv = dev->dev_private;
8491
8492         if (dev_priv->renderctx) {
8493                 i915_gem_object_unpin(dev_priv->renderctx);
8494                 drm_gem_object_unreference(&dev_priv->renderctx->base);
8495                 dev_priv->renderctx = NULL;
8496         }
8497
8498         if (dev_priv->pwrctx) {
8499                 i915_gem_object_unpin(dev_priv->pwrctx);
8500                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8501                 dev_priv->pwrctx = NULL;
8502         }
8503 }
8504
8505 static void ironlake_disable_rc6(struct drm_device *dev)
8506 {
8507         struct drm_i915_private *dev_priv = dev->dev_private;
8508
8509         if (I915_READ(PWRCTXA)) {
8510                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8511                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8512                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8513                          50);
8514
8515                 I915_WRITE(PWRCTXA, 0);
8516                 POSTING_READ(PWRCTXA);
8517
8518                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8519                 POSTING_READ(RSTDBYCTL);
8520         }
8521
8522         ironlake_teardown_rc6(dev);
8523 }
8524
8525 static int ironlake_setup_rc6(struct drm_device *dev)
8526 {
8527         struct drm_i915_private *dev_priv = dev->dev_private;
8528
8529         if (dev_priv->renderctx == NULL)
8530                 dev_priv->renderctx = intel_alloc_context_page(dev);
8531         if (!dev_priv->renderctx)
8532                 return -ENOMEM;
8533
8534         if (dev_priv->pwrctx == NULL)
8535                 dev_priv->pwrctx = intel_alloc_context_page(dev);
8536         if (!dev_priv->pwrctx) {
8537                 ironlake_teardown_rc6(dev);
8538                 return -ENOMEM;
8539         }
8540
8541         return 0;
8542 }
8543
8544 void ironlake_enable_rc6(struct drm_device *dev)
8545 {
8546         struct drm_i915_private *dev_priv = dev->dev_private;
8547         int ret;
8548
8549         /* rc6 disabled by default due to repeated reports of hanging during
8550          * boot and resume.
8551          */
8552         if (!intel_enable_rc6(dev))
8553                 return;
8554
8555         mutex_lock(&dev->struct_mutex);
8556         ret = ironlake_setup_rc6(dev);
8557         if (ret) {
8558                 mutex_unlock(&dev->struct_mutex);
8559                 return;
8560         }
8561
8562         /*
8563          * GPU can automatically power down the render unit if given a page
8564          * to save state.
8565          */
8566         ret = BEGIN_LP_RING(6);
8567         if (ret) {
8568                 ironlake_teardown_rc6(dev);
8569                 mutex_unlock(&dev->struct_mutex);
8570                 return;
8571         }
8572
8573         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8574         OUT_RING(MI_SET_CONTEXT);
8575         OUT_RING(dev_priv->renderctx->gtt_offset |
8576                  MI_MM_SPACE_GTT |
8577                  MI_SAVE_EXT_STATE_EN |
8578                  MI_RESTORE_EXT_STATE_EN |
8579                  MI_RESTORE_INHIBIT);
8580         OUT_RING(MI_SUSPEND_FLUSH);
8581         OUT_RING(MI_NOOP);
8582         OUT_RING(MI_FLUSH);
8583         ADVANCE_LP_RING();
8584
8585         /*
8586          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8587          * does an implicit flush, combined with MI_FLUSH above, it should be
8588          * safe to assume that renderctx is valid
8589          */
8590         ret = intel_wait_ring_idle(LP_RING(dev_priv));
8591         if (ret) {
8592                 DRM_ERROR("failed to enable ironlake power power savings\n");
8593                 ironlake_teardown_rc6(dev);
8594                 mutex_unlock(&dev->struct_mutex);
8595                 return;
8596         }
8597
8598         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8599         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8600         mutex_unlock(&dev->struct_mutex);
8601 }
8602
8603 void intel_init_clock_gating(struct drm_device *dev)
8604 {
8605         struct drm_i915_private *dev_priv = dev->dev_private;
8606
8607         dev_priv->display.init_clock_gating(dev);
8608
8609         if (dev_priv->display.init_pch_clock_gating)
8610                 dev_priv->display.init_pch_clock_gating(dev);
8611 }
8612
8613 /* Set up chip specific display functions */
8614 static void intel_init_display(struct drm_device *dev)
8615 {
8616         struct drm_i915_private *dev_priv = dev->dev_private;
8617
8618         /* We always want a DPMS function */
8619         if (HAS_PCH_SPLIT(dev)) {
8620                 dev_priv->display.dpms = ironlake_crtc_dpms;
8621                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8622                 dev_priv->display.update_plane = ironlake_update_plane;
8623         } else {
8624                 dev_priv->display.dpms = i9xx_crtc_dpms;
8625                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8626                 dev_priv->display.update_plane = i9xx_update_plane;
8627         }
8628
8629         if (I915_HAS_FBC(dev)) {
8630                 if (HAS_PCH_SPLIT(dev)) {
8631                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8632                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
8633                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
8634                 } else if (IS_GM45(dev)) {
8635                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8636                         dev_priv->display.enable_fbc = g4x_enable_fbc;
8637                         dev_priv->display.disable_fbc = g4x_disable_fbc;
8638                 } else if (IS_CRESTLINE(dev)) {
8639                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8640                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
8641                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
8642                 }
8643                 /* 855GM needs testing */
8644         }
8645
8646         /* Returns the core display clock speed */
8647         if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8648                 dev_priv->display.get_display_clock_speed =
8649                         i945_get_display_clock_speed;
8650         else if (IS_I915G(dev))
8651                 dev_priv->display.get_display_clock_speed =
8652                         i915_get_display_clock_speed;
8653         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8654                 dev_priv->display.get_display_clock_speed =
8655                         i9xx_misc_get_display_clock_speed;
8656         else if (IS_I915GM(dev))
8657                 dev_priv->display.get_display_clock_speed =
8658                         i915gm_get_display_clock_speed;
8659         else if (IS_I865G(dev))
8660                 dev_priv->display.get_display_clock_speed =
8661                         i865_get_display_clock_speed;
8662         else if (IS_I85X(dev))
8663                 dev_priv->display.get_display_clock_speed =
8664                         i855_get_display_clock_speed;
8665         else /* 852, 830 */
8666                 dev_priv->display.get_display_clock_speed =
8667                         i830_get_display_clock_speed;
8668
8669         /* For FIFO watermark updates */
8670         if (HAS_PCH_SPLIT(dev)) {
8671                 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8672                 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8673
8674                 /* IVB configs may use multi-threaded forcewake */
8675                 if (IS_IVYBRIDGE(dev)) {
8676                         u32     ecobus;
8677
8678                         mutex_lock(&dev->struct_mutex);
8679                         __gen6_gt_force_wake_mt_get(dev_priv);
8680                         ecobus = I915_READ(ECOBUS);
8681                         __gen6_gt_force_wake_mt_put(dev_priv);
8682                         mutex_unlock(&dev->struct_mutex);
8683
8684                         if (ecobus & FORCEWAKE_MT_ENABLE) {
8685                                 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8686                                 dev_priv->display.force_wake_get =
8687                                         __gen6_gt_force_wake_mt_get;
8688                                 dev_priv->display.force_wake_put =
8689                                         __gen6_gt_force_wake_mt_put;
8690                         }
8691                 }
8692
8693                 if (HAS_PCH_IBX(dev))
8694                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8695                 else if (HAS_PCH_CPT(dev))
8696                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8697
8698                 if (IS_GEN5(dev)) {
8699                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8700                                 dev_priv->display.update_wm = ironlake_update_wm;
8701                         else {
8702                                 DRM_DEBUG_KMS("Failed to get proper latency. "
8703                                               "Disable CxSR\n");
8704                                 dev_priv->display.update_wm = NULL;
8705                         }
8706                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8707                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8708                         dev_priv->display.write_eld = ironlake_write_eld;
8709                 } else if (IS_GEN6(dev)) {
8710                         if (SNB_READ_WM0_LATENCY()) {
8711                                 dev_priv->display.update_wm = sandybridge_update_wm;
8712                         } else {
8713                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8714                                               "Disable CxSR\n");
8715                                 dev_priv->display.update_wm = NULL;
8716                         }
8717                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8718                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8719                         dev_priv->display.write_eld = ironlake_write_eld;
8720                 } else if (IS_IVYBRIDGE(dev)) {
8721                         /* FIXME: detect B0+ stepping and use auto training */
8722                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8723                         if (SNB_READ_WM0_LATENCY()) {
8724                                 dev_priv->display.update_wm = sandybridge_update_wm;
8725                         } else {
8726                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8727                                               "Disable CxSR\n");
8728                                 dev_priv->display.update_wm = NULL;
8729                         }
8730                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8731                         dev_priv->display.write_eld = ironlake_write_eld;
8732                 } else
8733                         dev_priv->display.update_wm = NULL;
8734         } else if (IS_PINEVIEW(dev)) {
8735                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8736                                             dev_priv->is_ddr3,
8737                                             dev_priv->fsb_freq,
8738                                             dev_priv->mem_freq)) {
8739                         DRM_INFO("failed to find known CxSR latency "
8740                                  "(found ddr%s fsb freq %d, mem freq %d), "
8741                                  "disabling CxSR\n",
8742                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
8743                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8744                         /* Disable CxSR and never update its watermark again */
8745                         pineview_disable_cxsr(dev);
8746                         dev_priv->display.update_wm = NULL;
8747                 } else
8748                         dev_priv->display.update_wm = pineview_update_wm;
8749                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8750         } else if (IS_G4X(dev)) {
8751                 dev_priv->display.write_eld = g4x_write_eld;
8752                 dev_priv->display.update_wm = g4x_update_wm;
8753                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8754         } else if (IS_GEN4(dev)) {
8755                 dev_priv->display.update_wm = i965_update_wm;
8756                 if (IS_CRESTLINE(dev))
8757                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8758                 else if (IS_BROADWATER(dev))
8759                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8760         } else if (IS_GEN3(dev)) {
8761                 dev_priv->display.update_wm = i9xx_update_wm;
8762                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8763                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8764         } else if (IS_I865G(dev)) {
8765                 dev_priv->display.update_wm = i830_update_wm;
8766                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8767                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8768         } else if (IS_I85X(dev)) {
8769                 dev_priv->display.update_wm = i9xx_update_wm;
8770                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8771                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8772         } else {
8773                 dev_priv->display.update_wm = i830_update_wm;
8774                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8775                 if (IS_845G(dev))
8776                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8777                 else
8778                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8779         }
8780
8781         /* Default just returns -ENODEV to indicate unsupported */
8782         dev_priv->display.queue_flip = intel_default_queue_flip;
8783
8784         switch (INTEL_INFO(dev)->gen) {
8785         case 2:
8786                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8787                 break;
8788
8789         case 3:
8790                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8791                 break;
8792
8793         case 4:
8794         case 5:
8795                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8796                 break;
8797
8798         case 6:
8799                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8800                 break;
8801         case 7:
8802                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8803                 break;
8804         }
8805 }
8806
8807 /*
8808  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8809  * resume, or other times.  This quirk makes sure that's the case for
8810  * affected systems.
8811  */
8812 static void quirk_pipea_force(struct drm_device *dev)
8813 {
8814         struct drm_i915_private *dev_priv = dev->dev_private;
8815
8816         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8817         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8818 }
8819
8820 /*
8821  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8822  */
8823 static void quirk_ssc_force_disable(struct drm_device *dev)
8824 {
8825         struct drm_i915_private *dev_priv = dev->dev_private;
8826         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8827 }
8828
8829 struct intel_quirk {
8830         int device;
8831         int subsystem_vendor;
8832         int subsystem_device;
8833         void (*hook)(struct drm_device *dev);
8834 };
8835
8836 struct intel_quirk intel_quirks[] = {
8837         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8838         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8839         /* HP Mini needs pipe A force quirk (LP: #322104) */
8840         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8841
8842         /* Thinkpad R31 needs pipe A force quirk */
8843         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8844         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8845         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8846
8847         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8848         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
8849         /* ThinkPad X40 needs pipe A force quirk */
8850
8851         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8852         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8853
8854         /* 855 & before need to leave pipe A & dpll A up */
8855         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8856         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8857
8858         /* Lenovo U160 cannot use SSC on LVDS */
8859         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8860
8861         /* Sony Vaio Y cannot use SSC on LVDS */
8862         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8863 };
8864
8865 static void intel_init_quirks(struct drm_device *dev)
8866 {
8867         struct pci_dev *d = dev->pdev;
8868         int i;
8869
8870         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8871                 struct intel_quirk *q = &intel_quirks[i];
8872
8873                 if (d->device == q->device &&
8874                     (d->subsystem_vendor == q->subsystem_vendor ||
8875                      q->subsystem_vendor == PCI_ANY_ID) &&
8876                     (d->subsystem_device == q->subsystem_device ||
8877                      q->subsystem_device == PCI_ANY_ID))
8878                         q->hook(dev);
8879         }
8880 }
8881
8882 /* Disable the VGA plane that we never use */
8883 static void i915_disable_vga(struct drm_device *dev)
8884 {
8885         struct drm_i915_private *dev_priv = dev->dev_private;
8886         u8 sr1;
8887         u32 vga_reg;
8888
8889         if (HAS_PCH_SPLIT(dev))
8890                 vga_reg = CPU_VGACNTRL;
8891         else
8892                 vga_reg = VGACNTRL;
8893
8894         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8895         outb(1, VGA_SR_INDEX);
8896         sr1 = inb(VGA_SR_DATA);
8897         outb(sr1 | 1<<5, VGA_SR_DATA);
8898         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8899         udelay(300);
8900
8901         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8902         POSTING_READ(vga_reg);
8903 }
8904
8905 void i915_redisable_vga(struct drm_device *dev)
8906 {
8907         struct drm_i915_private *dev_priv = dev->dev_private;
8908         u32 vga_reg;
8909
8910         if (HAS_PCH_SPLIT(dev))
8911                 vga_reg = CPU_VGACNTRL;
8912         else
8913                 vga_reg = VGACNTRL;
8914
8915         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
8916                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
8917                 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8918                 POSTING_READ(vga_reg);
8919         }
8920 }
8921
8922 void intel_modeset_init(struct drm_device *dev)
8923 {
8924         struct drm_i915_private *dev_priv = dev->dev_private;
8925         int i;
8926
8927         drm_mode_config_init(dev);
8928
8929         dev->mode_config.min_width = 0;
8930         dev->mode_config.min_height = 0;
8931
8932         dev->mode_config.funcs = (void *)&intel_mode_funcs;
8933
8934         intel_init_quirks(dev);
8935
8936         intel_init_display(dev);
8937
8938         if (IS_GEN2(dev)) {
8939                 dev->mode_config.max_width = 2048;
8940                 dev->mode_config.max_height = 2048;
8941         } else if (IS_GEN3(dev)) {
8942                 dev->mode_config.max_width = 4096;
8943                 dev->mode_config.max_height = 4096;
8944         } else {
8945                 dev->mode_config.max_width = 8192;
8946                 dev->mode_config.max_height = 8192;
8947         }
8948         dev->mode_config.fb_base = dev->agp->base;
8949
8950         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8951                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8952
8953         for (i = 0; i < dev_priv->num_pipe; i++) {
8954                 intel_crtc_init(dev, i);
8955         }
8956
8957         /* Just disable it once at startup */
8958         i915_disable_vga(dev);
8959         intel_setup_outputs(dev);
8960
8961         intel_init_clock_gating(dev);
8962
8963         if (IS_IRONLAKE_M(dev)) {
8964                 ironlake_enable_drps(dev);
8965                 intel_init_emon(dev);
8966         }
8967
8968         if (IS_GEN6(dev) || IS_GEN7(dev)) {
8969                 gen6_enable_rps(dev_priv);
8970                 gen6_update_ring_freq(dev_priv);
8971         }
8972
8973         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8974         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8975                     (unsigned long)dev);
8976 }
8977
8978 void intel_modeset_gem_init(struct drm_device *dev)
8979 {
8980         if (IS_IRONLAKE_M(dev))
8981                 ironlake_enable_rc6(dev);
8982
8983         intel_setup_overlay(dev);
8984 }
8985
8986 void intel_modeset_cleanup(struct drm_device *dev)
8987 {
8988         struct drm_i915_private *dev_priv = dev->dev_private;
8989         struct drm_crtc *crtc;
8990         struct intel_crtc *intel_crtc;
8991
8992         drm_kms_helper_poll_fini(dev);
8993         mutex_lock(&dev->struct_mutex);
8994
8995         intel_unregister_dsm_handler();
8996
8997
8998         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8999                 /* Skip inactive CRTCs */
9000                 if (!crtc->fb)
9001                         continue;
9002
9003                 intel_crtc = to_intel_crtc(crtc);
9004                 intel_increase_pllclock(crtc);
9005         }
9006
9007         intel_disable_fbc(dev);
9008
9009         if (IS_IRONLAKE_M(dev))
9010                 ironlake_disable_drps(dev);
9011         if (IS_GEN6(dev) || IS_GEN7(dev))
9012                 gen6_disable_rps(dev);
9013
9014         if (IS_IRONLAKE_M(dev))
9015                 ironlake_disable_rc6(dev);
9016
9017         mutex_unlock(&dev->struct_mutex);
9018
9019         /* Disable the irq before mode object teardown, for the irq might
9020          * enqueue unpin/hotplug work. */
9021         drm_irq_uninstall(dev);
9022         cancel_work_sync(&dev_priv->hotplug_work);
9023         cancel_work_sync(&dev_priv->rps_work);
9024
9025         /* flush any delayed tasks or pending work */
9026         flush_scheduled_work();
9027
9028         /* Shut off idle work before the crtcs get freed. */
9029         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9030                 intel_crtc = to_intel_crtc(crtc);
9031                 del_timer_sync(&intel_crtc->idle_timer);
9032         }
9033         del_timer_sync(&dev_priv->idle_timer);
9034         cancel_work_sync(&dev_priv->idle_work);
9035
9036         drm_mode_config_cleanup(dev);
9037 }
9038
9039 /*
9040  * Return which encoder is currently attached for connector.
9041  */
9042 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9043 {
9044         return &intel_attached_encoder(connector)->base;
9045 }
9046
9047 void intel_connector_attach_encoder(struct intel_connector *connector,
9048                                     struct intel_encoder *encoder)
9049 {
9050         connector->encoder = encoder;
9051         drm_mode_connector_attach_encoder(&connector->base,
9052                                           &encoder->base);
9053 }
9054
9055 /*
9056  * set vga decode state - true == enable VGA decode
9057  */
9058 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9059 {
9060         struct drm_i915_private *dev_priv = dev->dev_private;
9061         u16 gmch_ctrl;
9062
9063         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9064         if (state)
9065                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9066         else
9067                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9068         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9069         return 0;
9070 }
9071
9072 #ifdef CONFIG_DEBUG_FS
9073 #include <linux/seq_file.h>
9074
9075 struct intel_display_error_state {
9076         struct intel_cursor_error_state {
9077                 u32 control;
9078                 u32 position;
9079                 u32 base;
9080                 u32 size;
9081         } cursor[2];
9082
9083         struct intel_pipe_error_state {
9084                 u32 conf;
9085                 u32 source;
9086
9087                 u32 htotal;
9088                 u32 hblank;
9089                 u32 hsync;
9090                 u32 vtotal;
9091                 u32 vblank;
9092                 u32 vsync;
9093         } pipe[2];
9094
9095         struct intel_plane_error_state {
9096                 u32 control;
9097                 u32 stride;
9098                 u32 size;
9099                 u32 pos;
9100                 u32 addr;
9101                 u32 surface;
9102                 u32 tile_offset;
9103         } plane[2];
9104 };
9105
9106 struct intel_display_error_state *
9107 intel_display_capture_error_state(struct drm_device *dev)
9108 {
9109         drm_i915_private_t *dev_priv = dev->dev_private;
9110         struct intel_display_error_state *error;
9111         int i;
9112
9113         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9114         if (error == NULL)
9115                 return NULL;
9116
9117         for (i = 0; i < 2; i++) {
9118                 error->cursor[i].control = I915_READ(CURCNTR(i));
9119                 error->cursor[i].position = I915_READ(CURPOS(i));
9120                 error->cursor[i].base = I915_READ(CURBASE(i));
9121
9122                 error->plane[i].control = I915_READ(DSPCNTR(i));
9123                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9124                 error->plane[i].size = I915_READ(DSPSIZE(i));
9125                 error->plane[i].pos = I915_READ(DSPPOS(i));
9126                 error->plane[i].addr = I915_READ(DSPADDR(i));
9127                 if (INTEL_INFO(dev)->gen >= 4) {
9128                         error->plane[i].surface = I915_READ(DSPSURF(i));
9129                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9130                 }
9131
9132                 error->pipe[i].conf = I915_READ(PIPECONF(i));
9133                 error->pipe[i].source = I915_READ(PIPESRC(i));
9134                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9135                 error->pipe[i].hblank = I915_READ(HBLANK(i));
9136                 error->pipe[i].hsync = I915_READ(HSYNC(i));
9137                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9138                 error->pipe[i].vblank = I915_READ(VBLANK(i));
9139                 error->pipe[i].vsync = I915_READ(VSYNC(i));
9140         }
9141
9142         return error;
9143 }
9144
9145 void
9146 intel_display_print_error_state(struct seq_file *m,
9147                                 struct drm_device *dev,
9148                                 struct intel_display_error_state *error)
9149 {
9150         int i;
9151
9152         for (i = 0; i < 2; i++) {
9153                 seq_printf(m, "Pipe [%d]:\n", i);
9154                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9155                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9156                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9157                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9158                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9159                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9160                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9161                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9162
9163                 seq_printf(m, "Plane [%d]:\n", i);
9164                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9165                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9166                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9167                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9168                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9169                 if (INTEL_INFO(dev)->gen >= 4) {
9170                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9171                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9172                 }
9173
9174                 seq_printf(m, "Cursor [%d]:\n", i);
9175                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9176                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9177                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9178         }
9179 }
9180 #endif