drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         if (IS_GEN5(dev)) {
 349                 struct drm_i915_private *dev_priv = dev->dev_private;
 350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 351         } else
 352                 return 27;
 353 }
 354
 355 static const intel_limit_t intel_limits_i8xx_dvo = {
 356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 366         .find_pll = intel_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_i8xx_lvds = {
 370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 380         .find_pll = intel_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_i9xx_sdvo = {
 384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397 static const intel_limit_t intel_limits_i9xx_lvds = {
 398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 406         /* The single-channel range is 25-112Mhz, and dual-channel
 407          * is 80-224Mhz.  Prefer single channel as much as possible.
 408          */
 409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 411         .find_pll = intel_find_best_PLL,
 412 };
 413
 414     /* below parameter and function is for G4X Chipset Family*/
 415 static const intel_limit_t intel_limits_g4x_sdvo = {
 416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 425                  .p2_slow = G4X_P2_SDVO_SLOW,
 426                  .p2_fast = G4X_P2_SDVO_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_hdmi = {
 432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 443         },
 444         .find_pll = intel_g4x_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 450         .vco = { .min = G4X_VCO_MIN,
 451                  .max = G4X_VCO_MAX },
 452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 467         },
 468         .find_pll = intel_g4x_find_best_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 474         .vco = { .min = G4X_VCO_MIN,
 475                  .max = G4X_VCO_MAX },
 476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 491         },
 492         .find_pll = intel_g4x_find_best_PLL,
 493 };
 494
 495 static const intel_limit_t intel_limits_g4x_display_port = {
 496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 498         .vco = { .min = G4X_VCO_MIN,
 499                  .max = G4X_VCO_MAX},
 500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 501                  .max = G4X_N_DISPLAY_PORT_MAX },
 502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 503                  .max = G4X_M_DISPLAY_PORT_MAX },
 504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 505                  .max = G4X_M1_DISPLAY_PORT_MAX },
 506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 507                  .max = G4X_M2_DISPLAY_PORT_MAX },
 508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 509                  .max = G4X_P_DISPLAY_PORT_MAX },
 510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 511                  .max = G4X_P1_DISPLAY_PORT_MAX},
 512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 515         .find_pll = intel_find_pll_g4x_dp,
 516 };
 517
 518 static const intel_limit_t intel_limits_pineview_sdvo = {
 519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_pineview_lvds = {
 533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 541         /* Pineview only supports single-channel mode. */
 542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 544         .find_pll = intel_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_dac = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 619         .find_pll = intel_g4x_find_best_PLL,
 620 };
 621
 622 static const intel_limit_t intel_limits_ironlake_display_port = {
 623         .dot = { .min = IRONLAKE_DOT_MIN,
 624                  .max = IRONLAKE_DOT_MAX },
 625         .vco = { .min = IRONLAKE_VCO_MIN,
 626                  .max = IRONLAKE_VCO_MAX},
 627         .n   = { .min = IRONLAKE_DP_N_MIN,
 628                  .max = IRONLAKE_DP_N_MAX },
 629         .m   = { .min = IRONLAKE_DP_M_MIN,
 630                  .max = IRONLAKE_DP_M_MAX },
 631         .m1  = { .min = IRONLAKE_M1_MIN,
 632                  .max = IRONLAKE_M1_MAX },
 633         .m2  = { .min = IRONLAKE_M2_MIN,
 634                  .max = IRONLAKE_M2_MAX },
 635         .p   = { .min = IRONLAKE_DP_P_MIN,
 636                  .max = IRONLAKE_DP_P_MAX },
 637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 638                  .max = IRONLAKE_DP_P1_MAX},
 639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 641                  .p2_fast = IRONLAKE_DP_P2_FAST },
 642         .find_pll = intel_find_pll_ironlake_dp,
 643 };
 644
 645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 646                                                 int refclk)
 647 {
 648         struct drm_device *dev = crtc->dev;
 649         struct drm_i915_private *dev_priv = dev->dev_private;
 650         const intel_limit_t *limit;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 654                     LVDS_CLKB_POWER_UP) {
 655                         /* LVDS dual channel */
 656                         if (refclk == 100000)
 657                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 658                         else
 659                                 limit = &intel_limits_ironlake_dual_lvds;
 660                 } else {
 661                         if (refclk == 100000)
 662                                 limit = &intel_limits_ironlake_single_lvds_100m;
 663                         else
 664                                 limit = &intel_limits_ironlake_single_lvds;
 665                 }
 666         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 667                         HAS_eDP)
 668                 limit = &intel_limits_ironlake_display_port;
 669         else
 670                 limit = &intel_limits_ironlake_dac;
 671
 672         return limit;
 673 }
 674
 675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 676 {
 677         struct drm_device *dev = crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         const intel_limit_t *limit;
 680
 681         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 682                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 683                     LVDS_CLKB_POWER_UP)
 684                         /* LVDS with dual channel */
 685                         limit = &intel_limits_g4x_dual_channel_lvds;
 686                 else
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_single_channel_lvds;
 689         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 690                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 691                 limit = &intel_limits_g4x_hdmi;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 693                 limit = &intel_limits_g4x_sdvo;
 694         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 695                 limit = &intel_limits_g4x_display_port;
 696         } else /* The option is for other outputs */
 697                 limit = &intel_limits_i9xx_sdvo;
 698
 699         return limit;
 700 }
 701
 702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 703 {
 704         struct drm_device *dev = crtc->dev;
 705         const intel_limit_t *limit;
 706
 707         if (HAS_PCH_SPLIT(dev))
 708                 limit = intel_ironlake_limit(crtc, refclk);
 709         else if (IS_G4X(dev)) {
 710                 limit = intel_g4x_limit(crtc);
 711         } else if (IS_PINEVIEW(dev)) {
 712                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 713                         limit = &intel_limits_pineview_lvds;
 714                 else
 715                         limit = &intel_limits_pineview_sdvo;
 716         } else if (!IS_GEN2(dev)) {
 717                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 718                         limit = &intel_limits_i9xx_lvds;
 719                 else
 720                         limit = &intel_limits_i9xx_sdvo;
 721         } else {
 722                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 723                         limit = &intel_limits_i8xx_lvds;
 724                 else
 725                         limit = &intel_limits_i8xx_dvo;
 726         }
 727         return limit;
 728 }
 729
 730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 731 static void pineview_clock(int refclk, intel_clock_t *clock)
 732 {
 733         clock->m = clock->m2 + 2;
 734         clock->p = clock->p1 * clock->p2;
 735         clock->vco = refclk * clock->m / clock->n;
 736         clock->dot = clock->vco / clock->p;
 737 }
 738
 739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 740 {
 741         if (IS_PINEVIEW(dev)) {
 742                 pineview_clock(refclk, clock);
 743                 return;
 744         }
 745         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 746         clock->p = clock->p1 * clock->p2;
 747         clock->vco = refclk * clock->m / (clock->n + 2);
 748         clock->dot = clock->vco / clock->p;
 749 }
 750
 751 /**
 752  * Returns whether any output on the specified pipe is of the specified type
 753  */
 754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct drm_mode_config *mode_config = &dev->mode_config;
 758         struct intel_encoder *encoder;
 759
 760         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 761                 if (encoder->base.crtc == crtc && encoder->type == type)
 762                         return true;
 763
 764         return false;
 765 }
 766
 767 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 768 /**
 769  * Returns whether the given set of divisors are valid for a given refclk with
 770  * the given connectors.
 771  */
 772
 773 static bool intel_PLL_is_valid(struct drm_device *dev,
 774                                const intel_limit_t *limit,
 775                                const intel_clock_t *clock)
 776 {
 777         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 778                 INTELPllInvalid ("p1 out of range\n");
 779         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 780                 INTELPllInvalid ("p out of range\n");
 781         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 782                 INTELPllInvalid ("m2 out of range\n");
 783         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 784                 INTELPllInvalid ("m1 out of range\n");
 785         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 786                 INTELPllInvalid ("m1 <= m2\n");
 787         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 788                 INTELPllInvalid ("m out of range\n");
 789         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 790                 INTELPllInvalid ("n out of range\n");
 791         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 792                 INTELPllInvalid ("vco out of range\n");
 793         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 794          * connector, etc., rather than just a single range.
 795          */
 796         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 797                 INTELPllInvalid ("dot out of range\n");
 798
 799         return true;
 800 }
 801
 802 static bool
 803 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 804                     int target, int refclk, intel_clock_t *best_clock)
 805
 806 {
 807         struct drm_device *dev = crtc->dev;
 808         struct drm_i915_private *dev_priv = dev->dev_private;
 809         intel_clock_t clock;
 810         int err = target;
 811
 812         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 813             (I915_READ(LVDS)) != 0) {
 814                 /*
 815                  * For LVDS, if the panel is on, just rely on its current
 816                  * settings for dual-channel.  We haven't figured out how to
 817                  * reliably set up different single/dual channel state, if we
 818                  * even can.
 819                  */
 820                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 821                     LVDS_CLKB_POWER_UP)
 822                         clock.p2 = limit->p2.p2_fast;
 823                 else
 824                         clock.p2 = limit->p2.p2_slow;
 825         } else {
 826                 if (target < limit->p2.dot_limit)
 827                         clock.p2 = limit->p2.p2_slow;
 828                 else
 829                         clock.p2 = limit->p2.p2_fast;
 830         }
 831
 832         memset (best_clock, 0, sizeof (*best_clock));
 833
 834         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 835              clock.m1++) {
 836                 for (clock.m2 = limit->m2.min;
 837                      clock.m2 <= limit->m2.max; clock.m2++) {
 838                         /* m1 is always 0 in Pineview */
 839                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 840                                 break;
 841                         for (clock.n = limit->n.min;
 842                              clock.n <= limit->n.max; clock.n++) {
 843                                 for (clock.p1 = limit->p1.min;
 844                                         clock.p1 <= limit->p1.max; clock.p1++) {
 845                                         int this_err;
 846
 847                                         intel_clock(dev, refclk, &clock);
 848                                         if (!intel_PLL_is_valid(dev, limit,
 849                                                                 &clock))
 850                                                 continue;
 851
 852                                         this_err = abs(clock.dot - target);
 853                                         if (this_err < err) {
 854                                                 *best_clock = clock;
 855                                                 err = this_err;
 856                                         }
 857                                 }
 858                         }
 859                 }
 860         }
 861
 862         return (err != target);
 863 }
 864
 865 static bool
 866 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 867                         int target, int refclk, intel_clock_t *best_clock)
 868 {
 869         struct drm_device *dev = crtc->dev;
 870         struct drm_i915_private *dev_priv = dev->dev_private;
 871         intel_clock_t clock;
 872         int max_n;
 873         bool found;
 874         /* approximately equals target * 0.00585 */
 875         int err_most = (target >> 8) + (target >> 9);
 876         found = false;
 877
 878         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 879                 int lvds_reg;
 880
 881                 if (HAS_PCH_SPLIT(dev))
 882                         lvds_reg = PCH_LVDS;
 883                 else
 884                         lvds_reg = LVDS;
 885                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 886                     LVDS_CLKB_POWER_UP)
 887                         clock.p2 = limit->p2.p2_fast;
 888                 else
 889                         clock.p2 = limit->p2.p2_slow;
 890         } else {
 891                 if (target < limit->p2.dot_limit)
 892                         clock.p2 = limit->p2.p2_slow;
 893                 else
 894                         clock.p2 = limit->p2.p2_fast;
 895         }
 896
 897         memset(best_clock, 0, sizeof(*best_clock));
 898         max_n = limit->n.max;
 899         /* based on hardware requirement, prefer smaller n to precision */
 900         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 901                 /* based on hardware requirement, prefere larger m1,m2 */
 902                 for (clock.m1 = limit->m1.max;
 903                      clock.m1 >= limit->m1.min; clock.m1--) {
 904                         for (clock.m2 = limit->m2.max;
 905                              clock.m2 >= limit->m2.min; clock.m2--) {
 906                                 for (clock.p1 = limit->p1.max;
 907                                      clock.p1 >= limit->p1.min; clock.p1--) {
 908                                         int this_err;
 909
 910                                         intel_clock(dev, refclk, &clock);
 911                                         if (!intel_PLL_is_valid(dev, limit,
 912                                                                 &clock))
 913                                                 continue;
 914
 915                                         this_err = abs(clock.dot - target);
 916                                         if (this_err < err_most) {
 917                                                 *best_clock = clock;
 918                                                 err_most = this_err;
 919                                                 max_n = clock.n;
 920                                                 found = true;
 921                                         }
 922                                 }
 923                         }
 924                 }
 925         }
 926         return found;
 927 }
 928
 929 static bool
 930 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 931                            int target, int refclk, intel_clock_t *best_clock)
 932 {
 933         struct drm_device *dev = crtc->dev;
 934         intel_clock_t clock;
 935
 936         if (target < 200000) {
 937                 clock.n = 1;
 938                 clock.p1 = 2;
 939                 clock.p2 = 10;
 940                 clock.m1 = 12;
 941                 clock.m2 = 9;
 942         } else {
 943                 clock.n = 2;
 944                 clock.p1 = 1;
 945                 clock.p2 = 10;
 946                 clock.m1 = 14;
 947                 clock.m2 = 8;
 948         }
 949         intel_clock(dev, refclk, &clock);
 950         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 951         return true;
 952 }
 953
 954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 955 static bool
 956 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 957                       int target, int refclk, intel_clock_t *best_clock)
 958 {
 959         intel_clock_t clock;
 960         if (target < 200000) {
 961                 clock.p1 = 2;
 962                 clock.p2 = 10;
 963                 clock.n = 2;
 964                 clock.m1 = 23;
 965                 clock.m2 = 8;
 966         } else {
 967                 clock.p1 = 1;
 968                 clock.p2 = 10;
 969                 clock.n = 1;
 970                 clock.m1 = 14;
 971                 clock.m2 = 2;
 972         }
 973         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 974         clock.p = (clock.p1 * clock.p2);
 975         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 976         clock.vco = 0;
 977         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 978         return true;
 979 }
 980
 981 /**
 982  * intel_wait_for_vblank - wait for vblank on a given pipe
 983  * @dev: drm device
 984  * @pipe: pipe to wait for
 985  *
 986  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 987  * mode setting code.
 988  */
 989 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 990 {
 991         struct drm_i915_private *dev_priv = dev->dev_private;
 992         int pipestat_reg = PIPESTAT(pipe);
 993
 994         /* Clear existing vblank status. Note this will clear any other
 995          * sticky status fields as well.
 996          *
 997          * This races with i915_driver_irq_handler() with the result
 998          * that either function could miss a vblank event.  Here it is not
 999          * fatal, as we will either wait upon the next vblank interrupt or
1000          * timeout.  Generally speaking intel_wait_for_vblank() is only
1001          * called during modeset at which time the GPU should be idle and
1002          * should *not* be performing page flips and thus not waiting on
1003          * vblanks...
1004          * Currently, the result of us stealing a vblank from the irq
1005          * handler is that a single frame will be skipped during swapbuffers.
1006          */
1007         I915_WRITE(pipestat_reg,
1008                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1009
1010         /* Wait for vblank interrupt bit to set */
1011         if (wait_for(I915_READ(pipestat_reg) &
1012                      PIPE_VBLANK_INTERRUPT_STATUS,
1013                      50))
1014                 DRM_DEBUG_KMS("vblank wait timed out\n");
1015 }
1016
1017 /*
1018  * intel_wait_for_pipe_off - wait for pipe to turn off
1019  * @dev: drm device
1020  * @pipe: pipe to wait for
1021  *
1022  * After disabling a pipe, we can't wait for vblank in the usual way,
1023  * spinning on the vblank interrupt status bit, since we won't actually
1024  * see an interrupt when the pipe is disabled.
1025  *
1026  * On Gen4 and above:
1027  *   wait for the pipe register state bit to turn off
1028  *
1029  * Otherwise:
1030  *   wait for the display line value to settle (it usually
1031  *   ends up stopping at the start of the next frame).
1032  *
1033  */
1034 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1035 {
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037
1038         if (INTEL_INFO(dev)->gen >= 4) {
1039                 int reg = PIPECONF(pipe);
1040
1041                 /* Wait for the Pipe State to go off */
1042                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043                              100))
1044                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045         } else {
1046                 u32 last_line;
1047                 int reg = PIPEDSL(pipe);
1048                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049
1050                 /* Wait for the display line to settle */
1051                 do {
1052                         last_line = I915_READ(reg) & DSL_LINEMASK;
1053                         mdelay(5);
1054                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1055                          time_after(timeout, jiffies));
1056                 if (time_after(jiffies, timeout))
1057                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058         }
1059 }
1060
1061 static const char *state_string(bool enabled)
1062 {
1063         return enabled ? "on" : "off";
1064 }
1065
1066 /* Only for pre-ILK configs */
1067 static void assert_pll(struct drm_i915_private *dev_priv,
1068                        enum pipe pipe, bool state)
1069 {
1070         int reg;
1071         u32 val;
1072         bool cur_state;
1073
1074         reg = DPLL(pipe);
1075         val = I915_READ(reg);
1076         cur_state = !!(val & DPLL_VCO_ENABLE);
1077         WARN(cur_state != state,
1078              "PLL state assertion failure (expected %s, current %s)\n",
1079              state_string(state), state_string(cur_state));
1080 }
1081 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1082 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1083
1084 /* For ILK+ */
1085 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1086                            enum pipe pipe, bool state)
1087 {
1088         int reg;
1089         u32 val;
1090         bool cur_state;
1091
1092         reg = PCH_DPLL(pipe);
1093         val = I915_READ(reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state assertion failure (expected %s, current %s)\n",
1097              state_string(state), state_string(cur_state));
1098 }
1099 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
1100 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
1101
1102 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103                           enum pipe pipe, bool state)
1104 {
1105         int reg;
1106         u32 val;
1107         bool cur_state;
1108
1109         reg = FDI_TX_CTL(pipe);
1110         val = I915_READ(reg);
1111         cur_state = !!(val & FDI_TX_ENABLE);
1112         WARN(cur_state != state,
1113              "FDI TX state assertion failure (expected %s, current %s)\n",
1114              state_string(state), state_string(cur_state));
1115 }
1116 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1117 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1118
1119 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1120                           enum pipe pipe, bool state)
1121 {
1122         int reg;
1123         u32 val;
1124         bool cur_state;
1125
1126         reg = FDI_RX_CTL(pipe);
1127         val = I915_READ(reg);
1128         cur_state = !!(val & FDI_RX_ENABLE);
1129         WARN(cur_state != state,
1130              "FDI RX state assertion failure (expected %s, current %s)\n",
1131              state_string(state), state_string(cur_state));
1132 }
1133 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1134 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1135
1136 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1137                                       enum pipe pipe)
1138 {
1139         int reg;
1140         u32 val;
1141
1142         /* ILK FDI PLL is always enabled */
1143         if (dev_priv->info->gen == 5)
1144                 return;
1145
1146         reg = FDI_TX_CTL(pipe);
1147         val = I915_READ(reg);
1148         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1149 }
1150
1151 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1152                                       enum pipe pipe)
1153 {
1154         int reg;
1155         u32 val;
1156
1157         reg = FDI_RX_CTL(pipe);
1158         val = I915_READ(reg);
1159         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1160 }
1161
1162 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1163                                   enum pipe pipe)
1164 {
1165         int pp_reg, lvds_reg;
1166         u32 val;
1167         enum pipe panel_pipe = PIPE_A;
1168         bool locked = locked;
1169
1170         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1171                 pp_reg = PCH_PP_CONTROL;
1172                 lvds_reg = PCH_LVDS;
1173         } else {
1174                 pp_reg = PP_CONTROL;
1175                 lvds_reg = LVDS;
1176         }
1177
1178         val = I915_READ(pp_reg);
1179         if (!(val & PANEL_POWER_ON) ||
1180             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1181                 locked = false;
1182
1183         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1184                 panel_pipe = PIPE_B;
1185
1186         WARN(panel_pipe == pipe && locked,
1187              "panel assertion failure, pipe %c regs locked\n",
1188              pipe_name(pipe));
1189 }
1190
1191 static void assert_pipe(struct drm_i915_private *dev_priv,
1192                         enum pipe pipe, bool state)
1193 {
1194         int reg;
1195         u32 val;
1196         bool cur_state;
1197
1198         reg = PIPECONF(pipe);
1199         val = I915_READ(reg);
1200         cur_state = !!(val & PIPECONF_ENABLE);
1201         WARN(cur_state != state,
1202              "pipe %c assertion failure (expected %s, current %s)\n",
1203              pipe_name(pipe), state_string(state), state_string(cur_state));
1204 }
1205 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1206 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1207
1208 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
1209                                  enum plane plane)
1210 {
1211         int reg;
1212         u32 val;
1213
1214         reg = DSPCNTR(plane);
1215         val = I915_READ(reg);
1216         WARN(!(val & DISPLAY_PLANE_ENABLE),
1217              "plane %c assertion failure, should be active but is disabled\n",
1218              plane_name(plane));
1219 }
1220
1221 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1222                                    enum pipe pipe)
1223 {
1224         int reg, i;
1225         u32 val;
1226         int cur_pipe;
1227
1228         /* Planes are fixed to pipes on ILK+ */
1229         if (HAS_PCH_SPLIT(dev_priv->dev))
1230                 return;
1231
1232         /* Need to check both planes against the pipe */
1233         for (i = 0; i < 2; i++) {
1234                 reg = DSPCNTR(i);
1235                 val = I915_READ(reg);
1236                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1237                         DISPPLANE_SEL_PIPE_SHIFT;
1238                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1239                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1240                      plane_name(i), pipe_name(pipe));
1241         }
1242 }
1243
1244 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1245 {
1246         u32 val;
1247         bool enabled;
1248
1249         val = I915_READ(PCH_DREF_CONTROL);
1250         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1251                             DREF_SUPERSPREAD_SOURCE_MASK));
1252         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1253 }
1254
1255 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1256                                        enum pipe pipe)
1257 {
1258         int reg;
1259         u32 val;
1260         bool enabled;
1261
1262         reg = TRANSCONF(pipe);
1263         val = I915_READ(reg);
1264         enabled = !!(val & TRANS_ENABLE);
1265         WARN(enabled,
1266              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1267              pipe_name(pipe));
1268 }
1269
1270 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1271                                    enum pipe pipe, int reg)
1272 {
1273         u32 val = I915_READ(reg);
1274         WARN(DP_PIPE_ENABLED(val, pipe),
1275              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1276              reg, pipe_name(pipe));
1277 }
1278
1279 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1280                                      enum pipe pipe, int reg)
1281 {
1282         u32 val = I915_READ(reg);
1283         WARN(HDMI_PIPE_ENABLED(val, pipe),
1284              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1285              reg, pipe_name(pipe));
1286 }
1287
1288 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1289                                       enum pipe pipe)
1290 {
1291         int reg;
1292         u32 val;
1293
1294         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1295         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1296         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1297
1298         reg = PCH_ADPA;
1299         val = I915_READ(reg);
1300         WARN(ADPA_PIPE_ENABLED(val, pipe),
1301              "PCH VGA enabled on transcoder %c, should be disabled\n",
1302              pipe_name(pipe));
1303
1304         reg = PCH_LVDS;
1305         val = I915_READ(reg);
1306         WARN(LVDS_PIPE_ENABLED(val, pipe),
1307              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1308              pipe_name(pipe));
1309
1310         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1311         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1312         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1313 }
1314
1315 /**
1316  * intel_enable_pll - enable a PLL
1317  * @dev_priv: i915 private structure
1318  * @pipe: pipe PLL to enable
1319  *
1320  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1321  * make sure the PLL reg is writable first though, since the panel write
1322  * protect mechanism may be enabled.
1323  *
1324  * Note!  This is for pre-ILK only.
1325  */
1326 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1327 {
1328         int reg;
1329         u32 val;
1330
1331         /* No really, not for ILK+ */
1332         BUG_ON(dev_priv->info->gen >= 5);
1333
1334         /* PLL is protected by panel, make sure we can write it */
1335         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1336                 assert_panel_unlocked(dev_priv, pipe);
1337
1338         reg = DPLL(pipe);
1339         val = I915_READ(reg);
1340         val |= DPLL_VCO_ENABLE;
1341
1342         /* We do this three times for luck */
1343         I915_WRITE(reg, val);
1344         POSTING_READ(reg);
1345         udelay(150); /* wait for warmup */
1346         I915_WRITE(reg, val);
1347         POSTING_READ(reg);
1348         udelay(150); /* wait for warmup */
1349         I915_WRITE(reg, val);
1350         POSTING_READ(reg);
1351         udelay(150); /* wait for warmup */
1352 }
1353
1354 /**
1355  * intel_disable_pll - disable a PLL
1356  * @dev_priv: i915 private structure
1357  * @pipe: pipe PLL to disable
1358  *
1359  * Disable the PLL for @pipe, making sure the pipe is off first.
1360  *
1361  * Note!  This is for pre-ILK only.
1362  */
1363 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1364 {
1365         int reg;
1366         u32 val;
1367
1368         /* Don't disable pipe A or pipe A PLLs if needed */
1369         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1370                 return;
1371
1372         /* Make sure the pipe isn't still relying on us */
1373         assert_pipe_disabled(dev_priv, pipe);
1374
1375         reg = DPLL(pipe);
1376         val = I915_READ(reg);
1377         val &= ~DPLL_VCO_ENABLE;
1378         I915_WRITE(reg, val);
1379         POSTING_READ(reg);
1380 }
1381
1382 /**
1383  * intel_enable_pch_pll - enable PCH PLL
1384  * @dev_priv: i915 private structure
1385  * @pipe: pipe PLL to enable
1386  *
1387  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1388  * drives the transcoder clock.
1389  */
1390 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1391                                  enum pipe pipe)
1392 {
1393         int reg;
1394         u32 val;
1395
1396         /* PCH only available on ILK+ */
1397         BUG_ON(dev_priv->info->gen < 5);
1398
1399         /* PCH refclock must be enabled first */
1400         assert_pch_refclk_enabled(dev_priv);
1401
1402         reg = PCH_DPLL(pipe);
1403         val = I915_READ(reg);
1404         val |= DPLL_VCO_ENABLE;
1405         I915_WRITE(reg, val);
1406         POSTING_READ(reg);
1407         udelay(200);
1408 }
1409
1410 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1411                                   enum pipe pipe)
1412 {
1413         int reg;
1414         u32 val;
1415
1416         /* PCH only available on ILK+ */
1417         BUG_ON(dev_priv->info->gen < 5);
1418
1419         /* Make sure transcoder isn't still depending on us */
1420         assert_transcoder_disabled(dev_priv, pipe);
1421
1422         reg = PCH_DPLL(pipe);
1423         val = I915_READ(reg);
1424         val &= ~DPLL_VCO_ENABLE;
1425         I915_WRITE(reg, val);
1426         POSTING_READ(reg);
1427         udelay(200);
1428 }
1429
1430 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1431                                     enum pipe pipe)
1432 {
1433         int reg;
1434         u32 val;
1435
1436         /* PCH only available on ILK+ */
1437         BUG_ON(dev_priv->info->gen < 5);
1438
1439         /* Make sure PCH DPLL is enabled */
1440         assert_pch_pll_enabled(dev_priv, pipe);
1441
1442         /* FDI must be feeding us bits for PCH ports */
1443         assert_fdi_tx_enabled(dev_priv, pipe);
1444         assert_fdi_rx_enabled(dev_priv, pipe);
1445
1446         reg = TRANSCONF(pipe);
1447         val = I915_READ(reg);
1448         /*
1449          * make the BPC in transcoder be consistent with
1450          * that in pipeconf reg.
1451          */
1452         val &= ~PIPE_BPC_MASK;
1453         val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1454         I915_WRITE(reg, val | TRANS_ENABLE);
1455         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1456                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1457 }
1458
1459 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1460                                      enum pipe pipe)
1461 {
1462         int reg;
1463         u32 val;
1464
1465         /* FDI relies on the transcoder */
1466         assert_fdi_tx_disabled(dev_priv, pipe);
1467         assert_fdi_rx_disabled(dev_priv, pipe);
1468
1469         /* Ports must be off as well */
1470         assert_pch_ports_disabled(dev_priv, pipe);
1471
1472         reg = TRANSCONF(pipe);
1473         val = I915_READ(reg);
1474         val &= ~TRANS_ENABLE;
1475         I915_WRITE(reg, val);
1476         /* wait for PCH transcoder off, transcoder state */
1477         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1478                 DRM_ERROR("failed to disable transcoder\n");
1479 }
1480
1481 /**
1482  * intel_enable_pipe - enable a pipe, asserting requirements
1483  * @dev_priv: i915 private structure
1484  * @pipe: pipe to enable
1485  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1486  *
1487  * Enable @pipe, making sure that various hardware specific requirements
1488  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1489  *
1490  * @pipe should be %PIPE_A or %PIPE_B.
1491  *
1492  * Will wait until the pipe is actually running (i.e. first vblank) before
1493  * returning.
1494  */
1495 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1496                               bool pch_port)
1497 {
1498         int reg;
1499         u32 val;
1500
1501         /*
1502          * A pipe without a PLL won't actually be able to drive bits from
1503          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1504          * need the check.
1505          */
1506         if (!HAS_PCH_SPLIT(dev_priv->dev))
1507                 assert_pll_enabled(dev_priv, pipe);
1508         else {
1509                 if (pch_port) {
1510                         /* if driving the PCH, we need FDI enabled */
1511                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1512                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1513                 }
1514                 /* FIXME: assert CPU port conditions for SNB+ */
1515         }
1516
1517         reg = PIPECONF(pipe);
1518         val = I915_READ(reg);
1519         val |= PIPECONF_ENABLE;
1520         I915_WRITE(reg, val);
1521         POSTING_READ(reg);
1522         intel_wait_for_vblank(dev_priv->dev, pipe);
1523 }
1524
1525 /**
1526  * intel_disable_pipe - disable a pipe, asserting requirements
1527  * @dev_priv: i915 private structure
1528  * @pipe: pipe to disable
1529  *
1530  * Disable @pipe, making sure that various hardware specific requirements
1531  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1532  *
1533  * @pipe should be %PIPE_A or %PIPE_B.
1534  *
1535  * Will wait until the pipe has shut down before returning.
1536  */
1537 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1538                                enum pipe pipe)
1539 {
1540         int reg;
1541         u32 val;
1542
1543         /*
1544          * Make sure planes won't keep trying to pump pixels to us,
1545          * or we might hang the display.
1546          */
1547         assert_planes_disabled(dev_priv, pipe);
1548
1549         /* Don't disable pipe A or pipe A PLLs if needed */
1550         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1551                 return;
1552
1553         reg = PIPECONF(pipe);
1554         val = I915_READ(reg);
1555         val &= ~PIPECONF_ENABLE;
1556         I915_WRITE(reg, val);
1557         POSTING_READ(reg);
1558         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1559 }
1560
1561 /**
1562  * intel_enable_plane - enable a display plane on a given pipe
1563  * @dev_priv: i915 private structure
1564  * @plane: plane to enable
1565  * @pipe: pipe being fed
1566  *
1567  * Enable @plane on @pipe, making sure that @pipe is running first.
1568  */
1569 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1570                                enum plane plane, enum pipe pipe)
1571 {
1572         int reg;
1573         u32 val;
1574
1575         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1576         assert_pipe_enabled(dev_priv, pipe);
1577
1578         reg = DSPCNTR(plane);
1579         val = I915_READ(reg);
1580         val |= DISPLAY_PLANE_ENABLE;
1581         I915_WRITE(reg, val);
1582         POSTING_READ(reg);
1583         intel_wait_for_vblank(dev_priv->dev, pipe);
1584 }
1585
1586 /*
1587  * Plane regs are double buffered, going from enabled->disabled needs a
1588  * trigger in order to latch.  The display address reg provides this.
1589  */
1590 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1591                                       enum plane plane)
1592 {
1593         u32 reg = DSPADDR(plane);
1594         I915_WRITE(reg, I915_READ(reg));
1595 }
1596
1597 /**
1598  * intel_disable_plane - disable a display plane
1599  * @dev_priv: i915 private structure
1600  * @plane: plane to disable
1601  * @pipe: pipe consuming the data
1602  *
1603  * Disable @plane; should be an independent operation.
1604  */
1605 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1606                                 enum plane plane, enum pipe pipe)
1607 {
1608         int reg;
1609         u32 val;
1610
1611         reg = DSPCNTR(plane);
1612         val = I915_READ(reg);
1613         val &= ~DISPLAY_PLANE_ENABLE;
1614         I915_WRITE(reg, val);
1615         POSTING_READ(reg);
1616         intel_flush_display_plane(dev_priv, plane);
1617         intel_wait_for_vblank(dev_priv->dev, pipe);
1618 }
1619
1620 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1621                            enum pipe pipe, int reg)
1622 {
1623         u32 val = I915_READ(reg);
1624         if (DP_PIPE_ENABLED(val, pipe))
1625                 I915_WRITE(reg, val & ~DP_PORT_EN);
1626 }
1627
1628 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1629                              enum pipe pipe, int reg)
1630 {
1631         u32 val = I915_READ(reg);
1632         if (HDMI_PIPE_ENABLED(val, pipe))
1633                 I915_WRITE(reg, val & ~PORT_ENABLE);
1634 }
1635
1636 /* Disable any ports connected to this transcoder */
1637 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1638                                     enum pipe pipe)
1639 {
1640         u32 reg, val;
1641
1642         val = I915_READ(PCH_PP_CONTROL);
1643         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1644
1645         disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1646         disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1647         disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1648
1649         reg = PCH_ADPA;
1650         val = I915_READ(reg);
1651         if (ADPA_PIPE_ENABLED(val, pipe))
1652                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1653
1654         reg = PCH_LVDS;
1655         val = I915_READ(reg);
1656         if (LVDS_PIPE_ENABLED(val, pipe)) {
1657                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1658                 POSTING_READ(reg);
1659                 udelay(100);
1660         }
1661
1662         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1663         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1664         disable_pch_hdmi(dev_priv, pipe, HDMID);
1665 }
1666
1667 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1668 {
1669         struct drm_device *dev = crtc->dev;
1670         struct drm_i915_private *dev_priv = dev->dev_private;
1671         struct drm_framebuffer *fb = crtc->fb;
1672         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1673         struct drm_i915_gem_object *obj = intel_fb->obj;
1674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1675         int plane, i;
1676         u32 fbc_ctl, fbc_ctl2;
1677
1678         if (fb->pitch == dev_priv->cfb_pitch &&
1679             obj->fence_reg == dev_priv->cfb_fence &&
1680             intel_crtc->plane == dev_priv->cfb_plane &&
1681             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1682                 return;
1683
1684         i8xx_disable_fbc(dev);
1685
1686         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1687
1688         if (fb->pitch < dev_priv->cfb_pitch)
1689                 dev_priv->cfb_pitch = fb->pitch;
1690
1691         /* FBC_CTL wants 64B units */
1692         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1693         dev_priv->cfb_fence = obj->fence_reg;
1694         dev_priv->cfb_plane = intel_crtc->plane;
1695         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1696
1697         /* Clear old tags */
1698         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1699                 I915_WRITE(FBC_TAG + (i * 4), 0);
1700
1701         /* Set it up... */
1702         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1703         if (obj->tiling_mode != I915_TILING_NONE)
1704                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1705         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1706         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1707
1708         /* enable it... */
1709         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1710         if (IS_I945GM(dev))
1711                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1712         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1713         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1714         if (obj->tiling_mode != I915_TILING_NONE)
1715                 fbc_ctl |= dev_priv->cfb_fence;
1716         I915_WRITE(FBC_CONTROL, fbc_ctl);
1717
1718         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1719                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1720 }
1721
1722 void i8xx_disable_fbc(struct drm_device *dev)
1723 {
1724         struct drm_i915_private *dev_priv = dev->dev_private;
1725         u32 fbc_ctl;
1726
1727         /* Disable compression */
1728         fbc_ctl = I915_READ(FBC_CONTROL);
1729         if ((fbc_ctl & FBC_CTL_EN) == 0)
1730                 return;
1731
1732         fbc_ctl &= ~FBC_CTL_EN;
1733         I915_WRITE(FBC_CONTROL, fbc_ctl);
1734
1735         /* Wait for compressing bit to clear */
1736         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1737                 DRM_DEBUG_KMS("FBC idle timed out\n");
1738                 return;
1739         }
1740
1741         DRM_DEBUG_KMS("disabled FBC\n");
1742 }
1743
1744 static bool i8xx_fbc_enabled(struct drm_device *dev)
1745 {
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1749 }
1750
1751 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1752 {
1753         struct drm_device *dev = crtc->dev;
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755         struct drm_framebuffer *fb = crtc->fb;
1756         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1757         struct drm_i915_gem_object *obj = intel_fb->obj;
1758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1759         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1760         unsigned long stall_watermark = 200;
1761         u32 dpfc_ctl;
1762
1763         dpfc_ctl = I915_READ(DPFC_CONTROL);
1764         if (dpfc_ctl & DPFC_CTL_EN) {
1765                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1766                     dev_priv->cfb_fence == obj->fence_reg &&
1767                     dev_priv->cfb_plane == intel_crtc->plane &&
1768                     dev_priv->cfb_y == crtc->y)
1769                         return;
1770
1771                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1772                 POSTING_READ(DPFC_CONTROL);
1773                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1774         }
1775
1776         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1777         dev_priv->cfb_fence = obj->fence_reg;
1778         dev_priv->cfb_plane = intel_crtc->plane;
1779         dev_priv->cfb_y = crtc->y;
1780
1781         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1782         if (obj->tiling_mode != I915_TILING_NONE) {
1783                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1784                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1785         } else {
1786                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1787         }
1788
1789         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1790                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1791                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1792         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1793
1794         /* enable it... */
1795         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1796
1797         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1798 }
1799
1800 void g4x_disable_fbc(struct drm_device *dev)
1801 {
1802         struct drm_i915_private *dev_priv = dev->dev_private;
1803         u32 dpfc_ctl;
1804
1805         /* Disable compression */
1806         dpfc_ctl = I915_READ(DPFC_CONTROL);
1807         if (dpfc_ctl & DPFC_CTL_EN) {
1808                 dpfc_ctl &= ~DPFC_CTL_EN;
1809                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1810
1811                 DRM_DEBUG_KMS("disabled FBC\n");
1812         }
1813 }
1814
1815 static bool g4x_fbc_enabled(struct drm_device *dev)
1816 {
1817         struct drm_i915_private *dev_priv = dev->dev_private;
1818
1819         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1820 }
1821
1822 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1823 {
1824         struct drm_i915_private *dev_priv = dev->dev_private;
1825         u32 blt_ecoskpd;
1826
1827         /* Make sure blitter notifies FBC of writes */
1828         __gen6_force_wake_get(dev_priv);
1829         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1830         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1831                 GEN6_BLITTER_LOCK_SHIFT;
1832         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1833         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1834         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1835         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1836                          GEN6_BLITTER_LOCK_SHIFT);
1837         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1838         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1839         __gen6_force_wake_put(dev_priv);
1840 }
1841
1842 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1843 {
1844         struct drm_device *dev = crtc->dev;
1845         struct drm_i915_private *dev_priv = dev->dev_private;
1846         struct drm_framebuffer *fb = crtc->fb;
1847         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1848         struct drm_i915_gem_object *obj = intel_fb->obj;
1849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1850         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1851         unsigned long stall_watermark = 200;
1852         u32 dpfc_ctl;
1853
1854         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1855         if (dpfc_ctl & DPFC_CTL_EN) {
1856                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1857                     dev_priv->cfb_fence == obj->fence_reg &&
1858                     dev_priv->cfb_plane == intel_crtc->plane &&
1859                     dev_priv->cfb_offset == obj->gtt_offset &&
1860                     dev_priv->cfb_y == crtc->y)
1861                         return;
1862
1863                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1864                 POSTING_READ(ILK_DPFC_CONTROL);
1865                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1866         }
1867
1868         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1869         dev_priv->cfb_fence = obj->fence_reg;
1870         dev_priv->cfb_plane = intel_crtc->plane;
1871         dev_priv->cfb_offset = obj->gtt_offset;
1872         dev_priv->cfb_y = crtc->y;
1873
1874         dpfc_ctl &= DPFC_RESERVED;
1875         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1876         if (obj->tiling_mode != I915_TILING_NONE) {
1877                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1878                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1879         } else {
1880                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1881         }
1882
1883         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1884                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1885                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1886         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1887         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1888         /* enable it... */
1889         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1890
1891         if (IS_GEN6(dev)) {
1892                 I915_WRITE(SNB_DPFC_CTL_SA,
1893                            SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1894                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1895                 sandybridge_blit_fbc_update(dev);
1896         }
1897
1898         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1899 }
1900
1901 void ironlake_disable_fbc(struct drm_device *dev)
1902 {
1903         struct drm_i915_private *dev_priv = dev->dev_private;
1904         u32 dpfc_ctl;
1905
1906         /* Disable compression */
1907         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1908         if (dpfc_ctl & DPFC_CTL_EN) {
1909                 dpfc_ctl &= ~DPFC_CTL_EN;
1910                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1911
1912                 DRM_DEBUG_KMS("disabled FBC\n");
1913         }
1914 }
1915
1916 static bool ironlake_fbc_enabled(struct drm_device *dev)
1917 {
1918         struct drm_i915_private *dev_priv = dev->dev_private;
1919
1920         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1921 }
1922
1923 bool intel_fbc_enabled(struct drm_device *dev)
1924 {
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926
1927         if (!dev_priv->display.fbc_enabled)
1928                 return false;
1929
1930         return dev_priv->display.fbc_enabled(dev);
1931 }
1932
1933 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1934 {
1935         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1936
1937         if (!dev_priv->display.enable_fbc)
1938                 return;
1939
1940         dev_priv->display.enable_fbc(crtc, interval);
1941 }
1942
1943 void intel_disable_fbc(struct drm_device *dev)
1944 {
1945         struct drm_i915_private *dev_priv = dev->dev_private;
1946
1947         if (!dev_priv->display.disable_fbc)
1948                 return;
1949
1950         dev_priv->display.disable_fbc(dev);
1951 }
1952
1953 /**
1954  * intel_update_fbc - enable/disable FBC as needed
1955  * @dev: the drm_device
1956  *
1957  * Set up the framebuffer compression hardware at mode set time.  We
1958  * enable it if possible:
1959  *   - plane A only (on pre-965)
1960  *   - no pixel mulitply/line duplication
1961  *   - no alpha buffer discard
1962  *   - no dual wide
1963  *   - framebuffer <= 2048 in width, 1536 in height
1964  *
1965  * We can't assume that any compression will take place (worst case),
1966  * so the compressed buffer has to be the same size as the uncompressed
1967  * one.  It also must reside (along with the line length buffer) in
1968  * stolen memory.
1969  *
1970  * We need to enable/disable FBC on a global basis.
1971  */
1972 static void intel_update_fbc(struct drm_device *dev)
1973 {
1974         struct drm_i915_private *dev_priv = dev->dev_private;
1975         struct drm_crtc *crtc = NULL, *tmp_crtc;
1976         struct intel_crtc *intel_crtc;
1977         struct drm_framebuffer *fb;
1978         struct intel_framebuffer *intel_fb;
1979         struct drm_i915_gem_object *obj;
1980
1981         DRM_DEBUG_KMS("\n");
1982
1983         if (!i915_powersave)
1984                 return;
1985
1986         if (!I915_HAS_FBC(dev))
1987                 return;
1988
1989         /*
1990          * If FBC is already on, we just have to verify that we can
1991          * keep it that way...
1992          * Need to disable if:
1993          *   - more than one pipe is active
1994          *   - changing FBC params (stride, fence, mode)
1995          *   - new fb is too large to fit in compressed buffer
1996          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1997          */
1998         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1999                 if (tmp_crtc->enabled && tmp_crtc->fb) {
2000                         if (crtc) {
2001                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
2002                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
2003                                 goto out_disable;
2004                         }
2005                         crtc = tmp_crtc;
2006                 }
2007         }
2008
2009         if (!crtc || crtc->fb == NULL) {
2010                 DRM_DEBUG_KMS("no output, disabling\n");
2011                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
2012                 goto out_disable;
2013         }
2014
2015         intel_crtc = to_intel_crtc(crtc);
2016         fb = crtc->fb;
2017         intel_fb = to_intel_framebuffer(fb);
2018         obj = intel_fb->obj;
2019
2020         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
2021                 DRM_DEBUG_KMS("framebuffer too large, disabling "
2022                               "compression\n");
2023                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
2024                 goto out_disable;
2025         }
2026         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
2027             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
2028                 DRM_DEBUG_KMS("mode incompatible with compression, "
2029                               "disabling\n");
2030                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
2031                 goto out_disable;
2032         }
2033         if ((crtc->mode.hdisplay > 2048) ||
2034             (crtc->mode.vdisplay > 1536)) {
2035                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
2036                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
2037                 goto out_disable;
2038         }
2039         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
2040                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
2041                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
2042                 goto out_disable;
2043         }
2044         if (obj->tiling_mode != I915_TILING_X) {
2045                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
2046                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
2047                 goto out_disable;
2048         }
2049
2050         /* If the kernel debugger is active, always disable compression */
2051         if (in_dbg_master())
2052                 goto out_disable;
2053
2054         intel_enable_fbc(crtc, 500);
2055         return;
2056
2057 out_disable:
2058         /* Multiple disables should be harmless */
2059         if (intel_fbc_enabled(dev)) {
2060                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2061                 intel_disable_fbc(dev);
2062         }
2063 }
2064
2065 int
2066 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2067                            struct drm_i915_gem_object *obj,
2068                            struct intel_ring_buffer *pipelined)
2069 {
2070         u32 alignment;
2071         int ret;
2072
2073         switch (obj->tiling_mode) {
2074         case I915_TILING_NONE:
2075                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2076                         alignment = 128 * 1024;
2077                 else if (INTEL_INFO(dev)->gen >= 4)
2078                         alignment = 4 * 1024;
2079                 else
2080                         alignment = 64 * 1024;
2081                 break;
2082         case I915_TILING_X:
2083                 /* pin() will align the object as required by fence */
2084                 alignment = 0;
2085                 break;
2086         case I915_TILING_Y:
2087                 /* FIXME: Is this true? */
2088                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2089                 return -EINVAL;
2090         default:
2091                 BUG();
2092         }
2093
2094         ret = i915_gem_object_pin(obj, alignment, true);
2095         if (ret)
2096                 return ret;
2097
2098         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
2099         if (ret)
2100                 goto err_unpin;
2101
2102         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2103          * fence, whereas 965+ only requires a fence if using
2104          * framebuffer compression.  For simplicity, we always install
2105          * a fence as the cost is not that onerous.
2106          */
2107         if (obj->tiling_mode != I915_TILING_NONE) {
2108                 ret = i915_gem_object_get_fence(obj, pipelined, false);
2109                 if (ret)
2110                         goto err_unpin;
2111         }
2112
2113         return 0;
2114
2115 err_unpin:
2116         i915_gem_object_unpin(obj);
2117         return ret;
2118 }
2119
2120 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2121 static int
2122 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2123                            int x, int y, enum mode_set_atomic state)
2124 {
2125         struct drm_device *dev = crtc->dev;
2126         struct drm_i915_private *dev_priv = dev->dev_private;
2127         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2128         struct intel_framebuffer *intel_fb;
2129         struct drm_i915_gem_object *obj;
2130         int plane = intel_crtc->plane;
2131         unsigned long Start, Offset;
2132         u32 dspcntr;
2133         u32 reg;
2134
2135         switch (plane) {
2136         case 0:
2137         case 1:
2138                 break;
2139         default:
2140                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2141                 return -EINVAL;
2142         }
2143
2144         intel_fb = to_intel_framebuffer(fb);
2145         obj = intel_fb->obj;
2146
2147         reg = DSPCNTR(plane);
2148         dspcntr = I915_READ(reg);
2149         /* Mask out pixel format bits in case we change it */
2150         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2151         switch (fb->bits_per_pixel) {
2152         case 8:
2153                 dspcntr |= DISPPLANE_8BPP;
2154                 break;
2155         case 16:
2156                 if (fb->depth == 15)
2157                         dspcntr |= DISPPLANE_15_16BPP;
2158                 else
2159                         dspcntr |= DISPPLANE_16BPP;
2160                 break;
2161         case 24:
2162         case 32:
2163                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2164                 break;
2165         default:
2166                 DRM_ERROR("Unknown color depth\n");
2167                 return -EINVAL;
2168         }
2169         if (INTEL_INFO(dev)->gen >= 4) {
2170                 if (obj->tiling_mode != I915_TILING_NONE)
2171                         dspcntr |= DISPPLANE_TILED;
2172                 else
2173                         dspcntr &= ~DISPPLANE_TILED;
2174         }
2175
2176         if (HAS_PCH_SPLIT(dev))
2177                 /* must disable */
2178                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2179
2180         I915_WRITE(reg, dspcntr);
2181
2182         Start = obj->gtt_offset;
2183         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2184
2185         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2186                       Start, Offset, x, y, fb->pitch);
2187         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2188         if (INTEL_INFO(dev)->gen >= 4) {
2189                 I915_WRITE(DSPSURF(plane), Start);
2190                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2191                 I915_WRITE(DSPADDR(plane), Offset);
2192         } else
2193                 I915_WRITE(DSPADDR(plane), Start + Offset);
2194         POSTING_READ(reg);
2195
2196         intel_update_fbc(dev);
2197         intel_increase_pllclock(crtc);
2198
2199         return 0;
2200 }
2201
2202 static int
2203 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204                     struct drm_framebuffer *old_fb)
2205 {
2206         struct drm_device *dev = crtc->dev;
2207         struct drm_i915_master_private *master_priv;
2208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2209         int ret;
2210
2211         /* no fb bound */
2212         if (!crtc->fb) {
2213                 DRM_DEBUG_KMS("No FB bound\n");
2214                 return 0;
2215         }
2216
2217         switch (intel_crtc->plane) {
2218         case 0:
2219         case 1:
2220                 break;
2221         default:
2222                 return -EINVAL;
2223         }
2224
2225         mutex_lock(&dev->struct_mutex);
2226         ret = intel_pin_and_fence_fb_obj(dev,
2227                                          to_intel_framebuffer(crtc->fb)->obj,
2228                                          NULL);
2229         if (ret != 0) {
2230                 mutex_unlock(&dev->struct_mutex);
2231                 return ret;
2232         }
2233
2234         if (old_fb) {
2235                 struct drm_i915_private *dev_priv = dev->dev_private;
2236                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2237
2238                 wait_event(dev_priv->pending_flip_queue,
2239                            atomic_read(&dev_priv->mm.wedged) ||
2240                            atomic_read(&obj->pending_flip) == 0);
2241
2242                 /* Big Hammer, we also need to ensure that any pending
2243                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2244                  * current scanout is retired before unpinning the old
2245                  * framebuffer.
2246                  *
2247                  * This should only fail upon a hung GPU, in which case we
2248                  * can safely continue.
2249                  */
2250                 ret = i915_gem_object_flush_gpu(obj, false);
2251                 (void) ret;
2252         }
2253
2254         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2255                                          LEAVE_ATOMIC_MODE_SET);
2256         if (ret) {
2257                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2258                 mutex_unlock(&dev->struct_mutex);
2259                 return ret;
2260         }
2261
2262         if (old_fb) {
2263                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2264                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2265         }
2266
2267         mutex_unlock(&dev->struct_mutex);
2268
2269         if (!dev->primary->master)
2270                 return 0;
2271
2272         master_priv = dev->primary->master->driver_priv;
2273         if (!master_priv->sarea_priv)
2274                 return 0;
2275
2276         if (intel_crtc->pipe) {
2277                 master_priv->sarea_priv->pipeB_x = x;
2278                 master_priv->sarea_priv->pipeB_y = y;
2279         } else {
2280                 master_priv->sarea_priv->pipeA_x = x;
2281                 master_priv->sarea_priv->pipeA_y = y;
2282         }
2283
2284         return 0;
2285 }
2286
2287 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2288 {
2289         struct drm_device *dev = crtc->dev;
2290         struct drm_i915_private *dev_priv = dev->dev_private;
2291         u32 dpa_ctl;
2292
2293         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2294         dpa_ctl = I915_READ(DP_A);
2295         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2296
2297         if (clock < 200000) {
2298                 u32 temp;
2299                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2300                 /* workaround for 160Mhz:
2301                    1) program 0x4600c bits 15:0 = 0x8124
2302                    2) program 0x46010 bit 0 = 1
2303                    3) program 0x46034 bit 24 = 1
2304                    4) program 0x64000 bit 14 = 1
2305                    */
2306                 temp = I915_READ(0x4600c);
2307                 temp &= 0xffff0000;
2308                 I915_WRITE(0x4600c, temp | 0x8124);
2309
2310                 temp = I915_READ(0x46010);
2311                 I915_WRITE(0x46010, temp | 1);
2312
2313                 temp = I915_READ(0x46034);
2314                 I915_WRITE(0x46034, temp | (1 << 24));
2315         } else {
2316                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2317         }
2318         I915_WRITE(DP_A, dpa_ctl);
2319
2320         POSTING_READ(DP_A);
2321         udelay(500);
2322 }
2323
2324 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2325 {
2326         struct drm_device *dev = crtc->dev;
2327         struct drm_i915_private *dev_priv = dev->dev_private;
2328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2329         int pipe = intel_crtc->pipe;
2330         u32 reg, temp;
2331
2332         /* enable normal train */
2333         reg = FDI_TX_CTL(pipe);
2334         temp = I915_READ(reg);
2335         temp &= ~FDI_LINK_TRAIN_NONE;
2336         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2337         I915_WRITE(reg, temp);
2338
2339         reg = FDI_RX_CTL(pipe);
2340         temp = I915_READ(reg);
2341         if (HAS_PCH_CPT(dev)) {
2342                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2343                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2344         } else {
2345                 temp &= ~FDI_LINK_TRAIN_NONE;
2346                 temp |= FDI_LINK_TRAIN_NONE;
2347         }
2348         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2349
2350         /* wait one idle pattern time */
2351         POSTING_READ(reg);
2352         udelay(1000);
2353 }
2354
2355 /* The FDI link training functions for ILK/Ibexpeak. */
2356 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2357 {
2358         struct drm_device *dev = crtc->dev;
2359         struct drm_i915_private *dev_priv = dev->dev_private;
2360         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2361         int pipe = intel_crtc->pipe;
2362         int plane = intel_crtc->plane;
2363         u32 reg, temp, tries;
2364
2365         /* FDI needs bits from pipe & plane first */
2366         assert_pipe_enabled(dev_priv, pipe);
2367         assert_plane_enabled(dev_priv, plane);
2368
2369         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2370            for train result */
2371         reg = FDI_RX_IMR(pipe);
2372         temp = I915_READ(reg);
2373         temp &= ~FDI_RX_SYMBOL_LOCK;
2374         temp &= ~FDI_RX_BIT_LOCK;
2375         I915_WRITE(reg, temp);
2376         I915_READ(reg);
2377         udelay(150);
2378
2379         /* enable CPU FDI TX and PCH FDI RX */
2380         reg = FDI_TX_CTL(pipe);
2381         temp = I915_READ(reg);
2382         temp &= ~(7 << 19);
2383         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2384         temp &= ~FDI_LINK_TRAIN_NONE;
2385         temp |= FDI_LINK_TRAIN_PATTERN_1;
2386         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2387
2388         reg = FDI_RX_CTL(pipe);
2389         temp = I915_READ(reg);
2390         temp &= ~FDI_LINK_TRAIN_NONE;
2391         temp |= FDI_LINK_TRAIN_PATTERN_1;
2392         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2393
2394         POSTING_READ(reg);
2395         udelay(150);
2396
2397         /* Ironlake workaround, enable clock pointer after FDI enable*/
2398         if (HAS_PCH_IBX(dev)) {
2399                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2400                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2401                            FDI_RX_PHASE_SYNC_POINTER_EN);
2402         }
2403
2404         reg = FDI_RX_IIR(pipe);
2405         for (tries = 0; tries < 5; tries++) {
2406                 temp = I915_READ(reg);
2407                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2408
2409                 if ((temp & FDI_RX_BIT_LOCK)) {
2410                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2411                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2412                         break;
2413                 }
2414         }
2415         if (tries == 5)
2416                 DRM_ERROR("FDI train 1 fail!\n");
2417
2418         /* Train 2 */
2419         reg = FDI_TX_CTL(pipe);
2420         temp = I915_READ(reg);
2421         temp &= ~FDI_LINK_TRAIN_NONE;
2422         temp |= FDI_LINK_TRAIN_PATTERN_2;
2423         I915_WRITE(reg, temp);
2424
2425         reg = FDI_RX_CTL(pipe);
2426         temp = I915_READ(reg);
2427         temp &= ~FDI_LINK_TRAIN_NONE;
2428         temp |= FDI_LINK_TRAIN_PATTERN_2;
2429         I915_WRITE(reg, temp);
2430
2431         POSTING_READ(reg);
2432         udelay(150);
2433
2434         reg = FDI_RX_IIR(pipe);
2435         for (tries = 0; tries < 5; tries++) {
2436                 temp = I915_READ(reg);
2437                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2438
2439                 if (temp & FDI_RX_SYMBOL_LOCK) {
2440                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2441                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2442                         break;
2443                 }
2444         }
2445         if (tries == 5)
2446                 DRM_ERROR("FDI train 2 fail!\n");
2447
2448         DRM_DEBUG_KMS("FDI train done\n");
2449
2450 }
2451
2452 static const int snb_b_fdi_train_param [] = {
2453         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2454         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2455         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2456         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2457 };
2458
2459 /* The FDI link training functions for SNB/Cougarpoint. */
2460 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2461 {
2462         struct drm_device *dev = crtc->dev;
2463         struct drm_i915_private *dev_priv = dev->dev_private;
2464         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2465         int pipe = intel_crtc->pipe;
2466         u32 reg, temp, i;
2467
2468         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2469            for train result */
2470         reg = FDI_RX_IMR(pipe);
2471         temp = I915_READ(reg);
2472         temp &= ~FDI_RX_SYMBOL_LOCK;
2473         temp &= ~FDI_RX_BIT_LOCK;
2474         I915_WRITE(reg, temp);
2475
2476         POSTING_READ(reg);
2477         udelay(150);
2478
2479         /* enable CPU FDI TX and PCH FDI RX */
2480         reg = FDI_TX_CTL(pipe);
2481         temp = I915_READ(reg);
2482         temp &= ~(7 << 19);
2483         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2484         temp &= ~FDI_LINK_TRAIN_NONE;
2485         temp |= FDI_LINK_TRAIN_PATTERN_1;
2486         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2487         /* SNB-B */
2488         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2489         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2490
2491         reg = FDI_RX_CTL(pipe);
2492         temp = I915_READ(reg);
2493         if (HAS_PCH_CPT(dev)) {
2494                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2495                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2496         } else {
2497                 temp &= ~FDI_LINK_TRAIN_NONE;
2498                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2499         }
2500         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2501
2502         POSTING_READ(reg);
2503         udelay(150);
2504
2505         for (i = 0; i < 4; i++ ) {
2506                 reg = FDI_TX_CTL(pipe);
2507                 temp = I915_READ(reg);
2508                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2509                 temp |= snb_b_fdi_train_param[i];
2510                 I915_WRITE(reg, temp);
2511
2512                 POSTING_READ(reg);
2513                 udelay(500);
2514
2515                 reg = FDI_RX_IIR(pipe);
2516                 temp = I915_READ(reg);
2517                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2518
2519                 if (temp & FDI_RX_BIT_LOCK) {
2520                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2521                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2522                         break;
2523                 }
2524         }
2525         if (i == 4)
2526                 DRM_ERROR("FDI train 1 fail!\n");
2527
2528         /* Train 2 */
2529         reg = FDI_TX_CTL(pipe);
2530         temp = I915_READ(reg);
2531         temp &= ~FDI_LINK_TRAIN_NONE;
2532         temp |= FDI_LINK_TRAIN_PATTERN_2;
2533         if (IS_GEN6(dev)) {
2534                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2535                 /* SNB-B */
2536                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2537         }
2538         I915_WRITE(reg, temp);
2539
2540         reg = FDI_RX_CTL(pipe);
2541         temp = I915_READ(reg);
2542         if (HAS_PCH_CPT(dev)) {
2543                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2545         } else {
2546                 temp &= ~FDI_LINK_TRAIN_NONE;
2547                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2548         }
2549         I915_WRITE(reg, temp);
2550
2551         POSTING_READ(reg);
2552         udelay(150);
2553
2554         for (i = 0; i < 4; i++ ) {
2555                 reg = FDI_TX_CTL(pipe);
2556                 temp = I915_READ(reg);
2557                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558                 temp |= snb_b_fdi_train_param[i];
2559                 I915_WRITE(reg, temp);
2560
2561                 POSTING_READ(reg);
2562                 udelay(500);
2563
2564                 reg = FDI_RX_IIR(pipe);
2565                 temp = I915_READ(reg);
2566                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2567
2568                 if (temp & FDI_RX_SYMBOL_LOCK) {
2569                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2570                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2571                         break;
2572                 }
2573         }
2574         if (i == 4)
2575                 DRM_ERROR("FDI train 2 fail!\n");
2576
2577         DRM_DEBUG_KMS("FDI train done.\n");
2578 }
2579
2580 static void ironlake_fdi_enable(struct drm_crtc *crtc)
2581 {
2582         struct drm_device *dev = crtc->dev;
2583         struct drm_i915_private *dev_priv = dev->dev_private;
2584         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2585         int pipe = intel_crtc->pipe;
2586         u32 reg, temp;
2587
2588         /* Write the TU size bits so error detection works */
2589         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2590                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2591
2592         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2593         reg = FDI_RX_CTL(pipe);
2594         temp = I915_READ(reg);
2595         temp &= ~((0x7 << 19) | (0x7 << 16));
2596         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2597         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2598         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2599
2600         POSTING_READ(reg);
2601         udelay(200);
2602
2603         /* Switch from Rawclk to PCDclk */
2604         temp = I915_READ(reg);
2605         I915_WRITE(reg, temp | FDI_PCDCLK);
2606
2607         POSTING_READ(reg);
2608         udelay(200);
2609
2610         /* Enable CPU FDI TX PLL, always on for Ironlake */
2611         reg = FDI_TX_CTL(pipe);
2612         temp = I915_READ(reg);
2613         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2614                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2615
2616                 POSTING_READ(reg);
2617                 udelay(100);
2618         }
2619 }
2620
2621 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2622 {
2623         struct drm_device *dev = crtc->dev;
2624         struct drm_i915_private *dev_priv = dev->dev_private;
2625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2626         int pipe = intel_crtc->pipe;
2627         u32 reg, temp;
2628
2629         /* disable CPU FDI tx and PCH FDI rx */
2630         reg = FDI_TX_CTL(pipe);
2631         temp = I915_READ(reg);
2632         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2633         POSTING_READ(reg);
2634
2635         reg = FDI_RX_CTL(pipe);
2636         temp = I915_READ(reg);
2637         temp &= ~(0x7 << 16);
2638         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2639         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2640
2641         POSTING_READ(reg);
2642         udelay(100);
2643
2644         /* Ironlake workaround, disable clock pointer after downing FDI */
2645         if (HAS_PCH_IBX(dev)) {
2646                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2647                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2648                            I915_READ(FDI_RX_CHICKEN(pipe) &
2649                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2650         }
2651
2652         /* still set train pattern 1 */
2653         reg = FDI_TX_CTL(pipe);
2654         temp = I915_READ(reg);
2655         temp &= ~FDI_LINK_TRAIN_NONE;
2656         temp |= FDI_LINK_TRAIN_PATTERN_1;
2657         I915_WRITE(reg, temp);
2658
2659         reg = FDI_RX_CTL(pipe);
2660         temp = I915_READ(reg);
2661         if (HAS_PCH_CPT(dev)) {
2662                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2663                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2664         } else {
2665                 temp &= ~FDI_LINK_TRAIN_NONE;
2666                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2667         }
2668         /* BPC in FDI rx is consistent with that in PIPECONF */
2669         temp &= ~(0x07 << 16);
2670         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2671         I915_WRITE(reg, temp);
2672
2673         POSTING_READ(reg);
2674         udelay(100);
2675 }
2676
2677 /*
2678  * When we disable a pipe, we need to clear any pending scanline wait events
2679  * to avoid hanging the ring, which we assume we are waiting on.
2680  */
2681 static void intel_clear_scanline_wait(struct drm_device *dev)
2682 {
2683         struct drm_i915_private *dev_priv = dev->dev_private;
2684         struct intel_ring_buffer *ring;
2685         u32 tmp;
2686
2687         if (IS_GEN2(dev))
2688                 /* Can't break the hang on i8xx */
2689                 return;
2690
2691         ring = LP_RING(dev_priv);
2692         tmp = I915_READ_CTL(ring);
2693         if (tmp & RING_WAIT)
2694                 I915_WRITE_CTL(ring, tmp);
2695 }
2696
2697 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2698 {
2699         struct drm_i915_gem_object *obj;
2700         struct drm_i915_private *dev_priv;
2701
2702         if (crtc->fb == NULL)
2703                 return;
2704
2705         obj = to_intel_framebuffer(crtc->fb)->obj;
2706         dev_priv = crtc->dev->dev_private;
2707         wait_event(dev_priv->pending_flip_queue,
2708                    atomic_read(&obj->pending_flip) == 0);
2709 }
2710
2711 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2712 {
2713         struct drm_device *dev = crtc->dev;
2714         struct drm_mode_config *mode_config = &dev->mode_config;
2715         struct intel_encoder *encoder;
2716
2717         /*
2718          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2719          * must be driven by its own crtc; no sharing is possible.
2720          */
2721         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2722                 if (encoder->base.crtc != crtc)
2723                         continue;
2724
2725                 switch (encoder->type) {
2726                 case INTEL_OUTPUT_EDP:
2727                         if (!intel_encoder_is_pch_edp(&encoder->base))
2728                                 return false;
2729                         continue;
2730                 }
2731         }
2732
2733         return true;
2734 }
2735
2736 /*
2737  * Enable PCH resources required for PCH ports:
2738  *   - PCH PLLs
2739  *   - FDI training & RX/TX
2740  *   - update transcoder timings
2741  *   - DP transcoding bits
2742  *   - transcoder
2743  */
2744 static void ironlake_pch_enable(struct drm_crtc *crtc)
2745 {
2746         struct drm_device *dev = crtc->dev;
2747         struct drm_i915_private *dev_priv = dev->dev_private;
2748         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2749         int pipe = intel_crtc->pipe;
2750         u32 reg, temp;
2751
2752         /* For PCH output, training FDI link */
2753         if (IS_GEN6(dev))
2754                 gen6_fdi_link_train(crtc);
2755         else
2756                 ironlake_fdi_link_train(crtc);
2757
2758         intel_enable_pch_pll(dev_priv, pipe);
2759
2760         if (HAS_PCH_CPT(dev)) {
2761                 /* Be sure PCH DPLL SEL is set */
2762                 temp = I915_READ(PCH_DPLL_SEL);
2763                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2764                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2765                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2766                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2767                 I915_WRITE(PCH_DPLL_SEL, temp);
2768         }
2769
2770         /* set transcoder timing, panel must allow it */
2771         assert_panel_unlocked(dev_priv, pipe);
2772         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2773         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2774         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2775
2776         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2777         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2778         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2779
2780         intel_fdi_normal_train(crtc);
2781
2782         /* For PCH DP, enable TRANS_DP_CTL */
2783         if (HAS_PCH_CPT(dev) &&
2784             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2785                 reg = TRANS_DP_CTL(pipe);
2786                 temp = I915_READ(reg);
2787                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2788                           TRANS_DP_SYNC_MASK |
2789                           TRANS_DP_BPC_MASK);
2790                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2791                          TRANS_DP_ENH_FRAMING);
2792                 temp |= TRANS_DP_8BPC;
2793
2794                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2795                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2796                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2797                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2798
2799                 switch (intel_trans_dp_port_sel(crtc)) {
2800                 case PCH_DP_B:
2801                         temp |= TRANS_DP_PORT_SEL_B;
2802                         break;
2803                 case PCH_DP_C:
2804                         temp |= TRANS_DP_PORT_SEL_C;
2805                         break;
2806                 case PCH_DP_D:
2807                         temp |= TRANS_DP_PORT_SEL_D;
2808                         break;
2809                 default:
2810                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2811                         temp |= TRANS_DP_PORT_SEL_B;
2812                         break;
2813                 }
2814
2815                 I915_WRITE(reg, temp);
2816         }
2817
2818         intel_enable_transcoder(dev_priv, pipe);
2819 }
2820
2821 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2822 {
2823         struct drm_device *dev = crtc->dev;
2824         struct drm_i915_private *dev_priv = dev->dev_private;
2825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2826         int pipe = intel_crtc->pipe;
2827         int plane = intel_crtc->plane;
2828         u32 temp;
2829         bool is_pch_port;
2830
2831         if (intel_crtc->active)
2832                 return;
2833
2834         intel_crtc->active = true;
2835         intel_update_watermarks(dev);
2836
2837         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2838                 temp = I915_READ(PCH_LVDS);
2839                 if ((temp & LVDS_PORT_EN) == 0)
2840                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2841         }
2842
2843         is_pch_port = intel_crtc_driving_pch(crtc);
2844
2845         if (is_pch_port)
2846                 ironlake_fdi_enable(crtc);
2847         else
2848                 ironlake_fdi_disable(crtc);
2849
2850         /* Enable panel fitting for LVDS */
2851         if (dev_priv->pch_pf_size &&
2852             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2853                 /* Force use of hard-coded filter coefficients
2854                  * as some pre-programmed values are broken,
2855                  * e.g. x201.
2856                  */
2857                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2858                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2859                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2860         }
2861
2862         intel_enable_pipe(dev_priv, pipe, is_pch_port);
2863         intel_enable_plane(dev_priv, plane, pipe);
2864
2865         if (is_pch_port)
2866                 ironlake_pch_enable(crtc);
2867
2868         intel_crtc_load_lut(crtc);
2869         intel_update_fbc(dev);
2870         intel_crtc_update_cursor(crtc, true);
2871 }
2872
2873 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2874 {
2875         struct drm_device *dev = crtc->dev;
2876         struct drm_i915_private *dev_priv = dev->dev_private;
2877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2878         int pipe = intel_crtc->pipe;
2879         int plane = intel_crtc->plane;
2880         u32 reg, temp;
2881
2882         if (!intel_crtc->active)
2883                 return;
2884
2885         intel_crtc_wait_for_pending_flips(crtc);
2886         drm_vblank_off(dev, pipe);
2887         intel_crtc_update_cursor(crtc, false);
2888
2889         intel_disable_plane(dev_priv, plane, pipe);
2890
2891         if (dev_priv->cfb_plane == plane &&
2892             dev_priv->display.disable_fbc)
2893                 dev_priv->display.disable_fbc(dev);
2894
2895         intel_disable_pipe(dev_priv, pipe);
2896
2897         /* Disable PF */
2898         I915_WRITE(PF_CTL(pipe), 0);
2899         I915_WRITE(PF_WIN_SZ(pipe), 0);
2900
2901         ironlake_fdi_disable(crtc);
2902
2903         /* This is a horrible layering violation; we should be doing this in
2904          * the connector/encoder ->prepare instead, but we don't always have
2905          * enough information there about the config to know whether it will
2906          * actually be necessary or just cause undesired flicker.
2907          */
2908         intel_disable_pch_ports(dev_priv, pipe);
2909
2910         intel_disable_transcoder(dev_priv, pipe);
2911
2912         if (HAS_PCH_CPT(dev)) {
2913                 /* disable TRANS_DP_CTL */
2914                 reg = TRANS_DP_CTL(pipe);
2915                 temp = I915_READ(reg);
2916                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2917                 temp |= TRANS_DP_PORT_SEL_NONE;
2918                 I915_WRITE(reg, temp);
2919
2920                 /* disable DPLL_SEL */
2921                 temp = I915_READ(PCH_DPLL_SEL);
2922                 switch (pipe) {
2923                 case 0:
2924                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2925                         break;
2926                 case 1:
2927                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2928                         break;
2929                 case 2:
2930                         /* FIXME: manage transcoder PLLs? */
2931                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2932                         break;
2933                 default:
2934                         BUG(); /* wtf */
2935                 }
2936                 I915_WRITE(PCH_DPLL_SEL, temp);
2937         }
2938
2939         /* disable PCH DPLL */
2940         intel_disable_pch_pll(dev_priv, pipe);
2941
2942         /* Switch from PCDclk to Rawclk */
2943         reg = FDI_RX_CTL(pipe);
2944         temp = I915_READ(reg);
2945         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2946
2947         /* Disable CPU FDI TX PLL */
2948         reg = FDI_TX_CTL(pipe);
2949         temp = I915_READ(reg);
2950         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2951
2952         POSTING_READ(reg);
2953         udelay(100);
2954
2955         reg = FDI_RX_CTL(pipe);
2956         temp = I915_READ(reg);
2957         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2958
2959         /* Wait for the clocks to turn off. */
2960         POSTING_READ(reg);
2961         udelay(100);
2962
2963         intel_crtc->active = false;
2964         intel_update_watermarks(dev);
2965         intel_update_fbc(dev);
2966         intel_clear_scanline_wait(dev);
2967 }
2968
2969 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2970 {
2971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2972         int pipe = intel_crtc->pipe;
2973         int plane = intel_crtc->plane;
2974
2975         /* XXX: When our outputs are all unaware of DPMS modes other than off
2976          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2977          */
2978         switch (mode) {
2979         case DRM_MODE_DPMS_ON:
2980         case DRM_MODE_DPMS_STANDBY:
2981         case DRM_MODE_DPMS_SUSPEND:
2982                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2983                 ironlake_crtc_enable(crtc);
2984                 break;
2985
2986         case DRM_MODE_DPMS_OFF:
2987                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2988                 ironlake_crtc_disable(crtc);
2989                 break;
2990         }
2991 }
2992
2993 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2994 {
2995         if (!enable && intel_crtc->overlay) {
2996                 struct drm_device *dev = intel_crtc->base.dev;
2997
2998                 mutex_lock(&dev->struct_mutex);
2999                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
3000                 mutex_unlock(&dev->struct_mutex);
3001         }
3002
3003         /* Let userspace switch the overlay on again. In most cases userspace
3004          * has to recompute where to put it anyway.
3005          */
3006 }
3007
3008 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3009 {
3010         struct drm_device *dev = crtc->dev;
3011         struct drm_i915_private *dev_priv = dev->dev_private;
3012         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3013         int pipe = intel_crtc->pipe;
3014         int plane = intel_crtc->plane;
3015
3016         if (intel_crtc->active)
3017                 return;
3018
3019         intel_crtc->active = true;
3020         intel_update_watermarks(dev);
3021
3022         intel_enable_pll(dev_priv, pipe);
3023         intel_enable_pipe(dev_priv, pipe, false);
3024         intel_enable_plane(dev_priv, plane, pipe);
3025
3026         intel_crtc_load_lut(crtc);
3027         intel_update_fbc(dev);
3028
3029         /* Give the overlay scaler a chance to enable if it's on this pipe */
3030         intel_crtc_dpms_overlay(intel_crtc, true);
3031         intel_crtc_update_cursor(crtc, true);
3032 }
3033
3034 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3035 {
3036         struct drm_device *dev = crtc->dev;
3037         struct drm_i915_private *dev_priv = dev->dev_private;
3038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3039         int pipe = intel_crtc->pipe;
3040         int plane = intel_crtc->plane;
3041
3042         if (!intel_crtc->active)
3043                 return;
3044
3045         /* Give the overlay scaler a chance to disable if it's on this pipe */
3046         intel_crtc_wait_for_pending_flips(crtc);
3047         drm_vblank_off(dev, pipe);
3048         intel_crtc_dpms_overlay(intel_crtc, false);
3049         intel_crtc_update_cursor(crtc, false);
3050
3051         if (dev_priv->cfb_plane == plane &&
3052             dev_priv->display.disable_fbc)
3053                 dev_priv->display.disable_fbc(dev);
3054
3055         intel_disable_plane(dev_priv, plane, pipe);
3056         intel_disable_pipe(dev_priv, pipe);
3057         intel_disable_pll(dev_priv, pipe);
3058
3059         intel_crtc->active = false;
3060         intel_update_fbc(dev);
3061         intel_update_watermarks(dev);
3062         intel_clear_scanline_wait(dev);
3063 }
3064
3065 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3066 {
3067         /* XXX: When our outputs are all unaware of DPMS modes other than off
3068          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3069          */
3070         switch (mode) {
3071         case DRM_MODE_DPMS_ON:
3072         case DRM_MODE_DPMS_STANDBY:
3073         case DRM_MODE_DPMS_SUSPEND:
3074                 i9xx_crtc_enable(crtc);
3075                 break;
3076         case DRM_MODE_DPMS_OFF:
3077                 i9xx_crtc_disable(crtc);
3078                 break;
3079         }
3080 }
3081
3082 /**
3083  * Sets the power management mode of the pipe and plane.
3084  */
3085 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3086 {
3087         struct drm_device *dev = crtc->dev;
3088         struct drm_i915_private *dev_priv = dev->dev_private;
3089         struct drm_i915_master_private *master_priv;
3090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3091         int pipe = intel_crtc->pipe;
3092         bool enabled;
3093
3094         if (intel_crtc->dpms_mode == mode)
3095                 return;
3096
3097         intel_crtc->dpms_mode = mode;
3098
3099         dev_priv->display.dpms(crtc, mode);
3100
3101         if (!dev->primary->master)
3102                 return;
3103
3104         master_priv = dev->primary->master->driver_priv;
3105         if (!master_priv->sarea_priv)
3106                 return;
3107
3108         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3109
3110         switch (pipe) {
3111         case 0:
3112                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3113                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3114                 break;
3115         case 1:
3116                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3117                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3118                 break;
3119         default:
3120                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3121                 break;
3122         }
3123 }
3124
3125 static void intel_crtc_disable(struct drm_crtc *crtc)
3126 {
3127         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3128         struct drm_device *dev = crtc->dev;
3129
3130         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3131
3132         if (crtc->fb) {
3133                 mutex_lock(&dev->struct_mutex);
3134                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3135                 mutex_unlock(&dev->struct_mutex);
3136         }
3137 }
3138
3139 /* Prepare for a mode set.
3140  *
3141  * Note we could be a lot smarter here.  We need to figure out which outputs
3142  * will be enabled, which disabled (in short, how the config will changes)
3143  * and perform the minimum necessary steps to accomplish that, e.g. updating
3144  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3145  * panel fitting is in the proper state, etc.
3146  */
3147 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3148 {
3149         i9xx_crtc_disable(crtc);
3150 }
3151
3152 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3153 {
3154         i9xx_crtc_enable(crtc);
3155 }
3156
3157 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3158 {
3159         ironlake_crtc_disable(crtc);
3160 }
3161
3162 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3163 {
3164         ironlake_crtc_enable(crtc);
3165 }
3166
3167 void intel_encoder_prepare (struct drm_encoder *encoder)
3168 {
3169         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3170         /* lvds has its own version of prepare see intel_lvds_prepare */
3171         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3172 }
3173
3174 void intel_encoder_commit (struct drm_encoder *encoder)
3175 {
3176         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3177         /* lvds has its own version of commit see intel_lvds_commit */
3178         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3179 }
3180
3181 void intel_encoder_destroy(struct drm_encoder *encoder)
3182 {
3183         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3184
3185         drm_encoder_cleanup(encoder);
3186         kfree(intel_encoder);
3187 }
3188
3189 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3190                                   struct drm_display_mode *mode,
3191                                   struct drm_display_mode *adjusted_mode)
3192 {
3193         struct drm_device *dev = crtc->dev;
3194
3195         if (HAS_PCH_SPLIT(dev)) {
3196                 /* FDI link clock is fixed at 2.7G */
3197                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3198                         return false;
3199         }
3200
3201         /* XXX some encoders set the crtcinfo, others don't.
3202          * Obviously we need some form of conflict resolution here...
3203          */
3204         if (adjusted_mode->crtc_htotal == 0)
3205                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3206
3207         return true;
3208 }
3209
3210 static int i945_get_display_clock_speed(struct drm_device *dev)
3211 {
3212         return 400000;
3213 }
3214
3215 static int i915_get_display_clock_speed(struct drm_device *dev)
3216 {
3217         return 333000;
3218 }
3219
3220 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3221 {
3222         return 200000;
3223 }
3224
3225 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3226 {
3227         u16 gcfgc = 0;
3228
3229         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3230
3231         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3232                 return 133000;
3233         else {
3234                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3235                 case GC_DISPLAY_CLOCK_333_MHZ:
3236                         return 333000;
3237                 default:
3238                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3239                         return 190000;
3240                 }
3241         }
3242 }
3243
3244 static int i865_get_display_clock_speed(struct drm_device *dev)
3245 {
3246         return 266000;
3247 }
3248
3249 static int i855_get_display_clock_speed(struct drm_device *dev)
3250 {
3251         u16 hpllcc = 0;
3252         /* Assume that the hardware is in the high speed state.  This
3253          * should be the default.
3254          */
3255         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3256         case GC_CLOCK_133_200:
3257         case GC_CLOCK_100_200:
3258                 return 200000;
3259         case GC_CLOCK_166_250:
3260                 return 250000;
3261         case GC_CLOCK_100_133:
3262                 return 133000;
3263         }
3264
3265         /* Shouldn't happen */
3266         return 0;
3267 }
3268
3269 static int i830_get_display_clock_speed(struct drm_device *dev)
3270 {
3271         return 133000;
3272 }
3273
3274 struct fdi_m_n {
3275         u32        tu;
3276         u32        gmch_m;
3277         u32        gmch_n;
3278         u32        link_m;
3279         u32        link_n;
3280 };
3281
3282 static void
3283 fdi_reduce_ratio(u32 *num, u32 *den)
3284 {
3285         while (*num > 0xffffff || *den > 0xffffff) {
3286                 *num >>= 1;
3287                 *den >>= 1;
3288         }
3289 }
3290
3291 static void
3292 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3293                      int link_clock, struct fdi_m_n *m_n)
3294 {
3295         m_n->tu = 64; /* default size */
3296
3297         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3298         m_n->gmch_m = bits_per_pixel * pixel_clock;
3299         m_n->gmch_n = link_clock * nlanes * 8;
3300         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3301
3302         m_n->link_m = pixel_clock;
3303         m_n->link_n = link_clock;
3304         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3305 }
3306
3307
3308 struct intel_watermark_params {
3309         unsigned long fifo_size;
3310         unsigned long max_wm;
3311         unsigned long default_wm;
3312         unsigned long guard_size;
3313         unsigned long cacheline_size;
3314 };
3315
3316 /* Pineview has different values for various configs */
3317 static const struct intel_watermark_params pineview_display_wm = {
3318         PINEVIEW_DISPLAY_FIFO,
3319         PINEVIEW_MAX_WM,
3320         PINEVIEW_DFT_WM,
3321         PINEVIEW_GUARD_WM,
3322         PINEVIEW_FIFO_LINE_SIZE
3323 };
3324 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3325         PINEVIEW_DISPLAY_FIFO,
3326         PINEVIEW_MAX_WM,
3327         PINEVIEW_DFT_HPLLOFF_WM,
3328         PINEVIEW_GUARD_WM,
3329         PINEVIEW_FIFO_LINE_SIZE
3330 };
3331 static const struct intel_watermark_params pineview_cursor_wm = {
3332         PINEVIEW_CURSOR_FIFO,
3333         PINEVIEW_CURSOR_MAX_WM,
3334         PINEVIEW_CURSOR_DFT_WM,
3335         PINEVIEW_CURSOR_GUARD_WM,
3336         PINEVIEW_FIFO_LINE_SIZE,
3337 };
3338 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3339         PINEVIEW_CURSOR_FIFO,
3340         PINEVIEW_CURSOR_MAX_WM,
3341         PINEVIEW_CURSOR_DFT_WM,
3342         PINEVIEW_CURSOR_GUARD_WM,
3343         PINEVIEW_FIFO_LINE_SIZE
3344 };
3345 static const struct intel_watermark_params g4x_wm_info = {
3346         G4X_FIFO_SIZE,
3347         G4X_MAX_WM,
3348         G4X_MAX_WM,
3349         2,
3350         G4X_FIFO_LINE_SIZE,
3351 };
3352 static const struct intel_watermark_params g4x_cursor_wm_info = {
3353         I965_CURSOR_FIFO,
3354         I965_CURSOR_MAX_WM,
3355         I965_CURSOR_DFT_WM,
3356         2,
3357         G4X_FIFO_LINE_SIZE,
3358 };
3359 static const struct intel_watermark_params i965_cursor_wm_info = {
3360         I965_CURSOR_FIFO,
3361         I965_CURSOR_MAX_WM,
3362         I965_CURSOR_DFT_WM,
3363         2,
3364         I915_FIFO_LINE_SIZE,
3365 };
3366 static const struct intel_watermark_params i945_wm_info = {
3367         I945_FIFO_SIZE,
3368         I915_MAX_WM,
3369         1,
3370         2,
3371         I915_FIFO_LINE_SIZE
3372 };
3373 static const struct intel_watermark_params i915_wm_info = {
3374         I915_FIFO_SIZE,
3375         I915_MAX_WM,
3376         1,
3377         2,
3378         I915_FIFO_LINE_SIZE
3379 };
3380 static const struct intel_watermark_params i855_wm_info = {
3381         I855GM_FIFO_SIZE,
3382         I915_MAX_WM,
3383         1,
3384         2,
3385         I830_FIFO_LINE_SIZE
3386 };
3387 static const struct intel_watermark_params i830_wm_info = {
3388         I830_FIFO_SIZE,
3389         I915_MAX_WM,
3390         1,
3391         2,
3392         I830_FIFO_LINE_SIZE
3393 };
3394
3395 static const struct intel_watermark_params ironlake_display_wm_info = {
3396         ILK_DISPLAY_FIFO,
3397         ILK_DISPLAY_MAXWM,
3398         ILK_DISPLAY_DFTWM,
3399         2,
3400         ILK_FIFO_LINE_SIZE
3401 };
3402 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3403         ILK_CURSOR_FIFO,
3404         ILK_CURSOR_MAXWM,
3405         ILK_CURSOR_DFTWM,
3406         2,
3407         ILK_FIFO_LINE_SIZE
3408 };
3409 static const struct intel_watermark_params ironlake_display_srwm_info = {
3410         ILK_DISPLAY_SR_FIFO,
3411         ILK_DISPLAY_MAX_SRWM,
3412         ILK_DISPLAY_DFT_SRWM,
3413         2,
3414         ILK_FIFO_LINE_SIZE
3415 };
3416 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3417         ILK_CURSOR_SR_FIFO,
3418         ILK_CURSOR_MAX_SRWM,
3419         ILK_CURSOR_DFT_SRWM,
3420         2,
3421         ILK_FIFO_LINE_SIZE
3422 };
3423
3424 static const struct intel_watermark_params sandybridge_display_wm_info = {
3425         SNB_DISPLAY_FIFO,
3426         SNB_DISPLAY_MAXWM,
3427         SNB_DISPLAY_DFTWM,
3428         2,
3429         SNB_FIFO_LINE_SIZE
3430 };
3431 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3432         SNB_CURSOR_FIFO,
3433         SNB_CURSOR_MAXWM,
3434         SNB_CURSOR_DFTWM,
3435         2,
3436         SNB_FIFO_LINE_SIZE
3437 };
3438 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3439         SNB_DISPLAY_SR_FIFO,
3440         SNB_DISPLAY_MAX_SRWM,
3441         SNB_DISPLAY_DFT_SRWM,
3442         2,
3443         SNB_FIFO_LINE_SIZE
3444 };
3445 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3446         SNB_CURSOR_SR_FIFO,
3447         SNB_CURSOR_MAX_SRWM,
3448         SNB_CURSOR_DFT_SRWM,
3449         2,
3450         SNB_FIFO_LINE_SIZE
3451 };
3452
3453
3454 /**
3455  * intel_calculate_wm - calculate watermark level
3456  * @clock_in_khz: pixel clock
3457  * @wm: chip FIFO params
3458  * @pixel_size: display pixel size
3459  * @latency_ns: memory latency for the platform
3460  *
3461  * Calculate the watermark level (the level at which the display plane will
3462  * start fetching from memory again).  Each chip has a different display
3463  * FIFO size and allocation, so the caller needs to figure that out and pass
3464  * in the correct intel_watermark_params structure.
3465  *
3466  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3467  * on the pixel size.  When it reaches the watermark level, it'll start
3468  * fetching FIFO line sized based chunks from memory until the FIFO fills
3469  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3470  * will occur, and a display engine hang could result.
3471  */
3472 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3473                                         const struct intel_watermark_params *wm,
3474                                         int fifo_size,
3475                                         int pixel_size,
3476                                         unsigned long latency_ns)
3477 {
3478         long entries_required, wm_size;
3479
3480         /*
3481          * Note: we need to make sure we don't overflow for various clock &
3482          * latency values.
3483          * clocks go from a few thousand to several hundred thousand.
3484          * latency is usually a few thousand
3485          */
3486         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3487                 1000;
3488         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3489
3490         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
3491
3492         wm_size = fifo_size - (entries_required + wm->guard_size);
3493
3494         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
3495
3496         /* Don't promote wm_size to unsigned... */
3497         if (wm_size > (long)wm->max_wm)
3498                 wm_size = wm->max_wm;
3499         if (wm_size <= 0)
3500                 wm_size = wm->default_wm;
3501         return wm_size;
3502 }
3503
3504 struct cxsr_latency {
3505         int is_desktop;
3506         int is_ddr3;
3507         unsigned long fsb_freq;
3508         unsigned long mem_freq;
3509         unsigned long display_sr;
3510         unsigned long display_hpll_disable;
3511         unsigned long cursor_sr;
3512         unsigned long cursor_hpll_disable;
3513 };
3514
3515 static const struct cxsr_latency cxsr_latency_table[] = {
3516         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3517         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3518         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3519         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3520         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3521
3522         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3523         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3524         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3525         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3526         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3527
3528         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3529         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3530         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3531         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3532         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3533
3534         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3535         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3536         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3537         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3538         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3539
3540         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3541         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3542         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3543         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3544         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3545
3546         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3547         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3548         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3549         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3550         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3551 };
3552
3553 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3554                                                          int is_ddr3,
3555                                                          int fsb,
3556                                                          int mem)
3557 {
3558         const struct cxsr_latency *latency;
3559         int i;
3560
3561         if (fsb == 0 || mem == 0)
3562                 return NULL;
3563
3564         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3565                 latency = &cxsr_latency_table[i];
3566                 if (is_desktop == latency->is_desktop &&
3567                     is_ddr3 == latency->is_ddr3 &&
3568                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3569                         return latency;
3570         }
3571
3572         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3573
3574         return NULL;
3575 }
3576
3577 static void pineview_disable_cxsr(struct drm_device *dev)
3578 {
3579         struct drm_i915_private *dev_priv = dev->dev_private;
3580
3581         /* deactivate cxsr */
3582         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3583 }
3584
3585 /*
3586  * Latency for FIFO fetches is dependent on several factors:
3587  *   - memory configuration (speed, channels)
3588  *   - chipset
3589  *   - current MCH state
3590  * It can be fairly high in some situations, so here we assume a fairly
3591  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3592  * set this value too high, the FIFO will fetch frequently to stay full)
3593  * and power consumption (set it too low to save power and we might see
3594  * FIFO underruns and display "flicker").
3595  *
3596  * A value of 5us seems to be a good balance; safe for very low end
3597  * platforms but not overly aggressive on lower latency configs.
3598  */
3599 static const int latency_ns = 5000;
3600
3601 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3602 {
3603         struct drm_i915_private *dev_priv = dev->dev_private;
3604         uint32_t dsparb = I915_READ(DSPARB);
3605         int size;
3606
3607         size = dsparb & 0x7f;
3608         if (plane)
3609                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3610
3611         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3612                       plane ? "B" : "A", size);
3613
3614         return size;
3615 }
3616
3617 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3618 {
3619         struct drm_i915_private *dev_priv = dev->dev_private;
3620         uint32_t dsparb = I915_READ(DSPARB);
3621         int size;
3622
3623         size = dsparb & 0x1ff;
3624         if (plane)
3625                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3626         size >>= 1; /* Convert to cachelines */
3627
3628         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3629                       plane ? "B" : "A", size);
3630
3631         return size;
3632 }
3633
3634 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3635 {
3636         struct drm_i915_private *dev_priv = dev->dev_private;
3637         uint32_t dsparb = I915_READ(DSPARB);
3638         int size;
3639
3640         size = dsparb & 0x7f;
3641         size >>= 2; /* Convert to cachelines */
3642
3643         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3644                       plane ? "B" : "A",
3645                       size);
3646
3647         return size;
3648 }
3649
3650 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3651 {
3652         struct drm_i915_private *dev_priv = dev->dev_private;
3653         uint32_t dsparb = I915_READ(DSPARB);
3654         int size;
3655
3656         size = dsparb & 0x7f;
3657         size >>= 1; /* Convert to cachelines */
3658
3659         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3660                       plane ? "B" : "A", size);
3661
3662         return size;
3663 }
3664
3665 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3666 {
3667         struct drm_crtc *crtc, *enabled = NULL;
3668
3669         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3670                 if (crtc->enabled && crtc->fb) {
3671                         if (enabled)
3672                                 return NULL;
3673                         enabled = crtc;
3674                 }
3675         }
3676
3677         return enabled;
3678 }
3679
3680 static void pineview_update_wm(struct drm_device *dev)
3681 {
3682         struct drm_i915_private *dev_priv = dev->dev_private;
3683         struct drm_crtc *crtc;
3684         const struct cxsr_latency *latency;
3685         u32 reg;
3686         unsigned long wm;
3687
3688         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3689                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3690         if (!latency) {
3691                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3692                 pineview_disable_cxsr(dev);
3693                 return;
3694         }
3695
3696         crtc = single_enabled_crtc(dev);
3697         if (crtc) {
3698                 int clock = crtc->mode.clock;
3699                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3700
3701                 /* Display SR */
3702                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3703                                         pineview_display_wm.fifo_size,
3704                                         pixel_size, latency->display_sr);
3705                 reg = I915_READ(DSPFW1);
3706                 reg &= ~DSPFW_SR_MASK;
3707                 reg |= wm << DSPFW_SR_SHIFT;
3708                 I915_WRITE(DSPFW1, reg);
3709                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3710
3711                 /* cursor SR */
3712                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3713                                         pineview_display_wm.fifo_size,
3714                                         pixel_size, latency->cursor_sr);
3715                 reg = I915_READ(DSPFW3);
3716                 reg &= ~DSPFW_CURSOR_SR_MASK;
3717                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3718                 I915_WRITE(DSPFW3, reg);
3719
3720                 /* Display HPLL off SR */
3721                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3722                                         pineview_display_hplloff_wm.fifo_size,
3723                                         pixel_size, latency->display_hpll_disable);
3724                 reg = I915_READ(DSPFW3);
3725                 reg &= ~DSPFW_HPLL_SR_MASK;
3726                 reg |= wm & DSPFW_HPLL_SR_MASK;
3727                 I915_WRITE(DSPFW3, reg);
3728
3729                 /* cursor HPLL off SR */
3730                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3731                                         pineview_display_hplloff_wm.fifo_size,
3732                                         pixel_size, latency->cursor_hpll_disable);
3733                 reg = I915_READ(DSPFW3);
3734                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3735                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3736                 I915_WRITE(DSPFW3, reg);
3737                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3738
3739                 /* activate cxsr */
3740                 I915_WRITE(DSPFW3,
3741                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3742                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3743         } else {
3744                 pineview_disable_cxsr(dev);
3745                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3746         }
3747 }
3748
3749 static bool g4x_compute_wm0(struct drm_device *dev,
3750                             int plane,
3751                             const struct intel_watermark_params *display,
3752                             int display_latency_ns,
3753                             const struct intel_watermark_params *cursor,
3754                             int cursor_latency_ns,
3755                             int *plane_wm,
3756                             int *cursor_wm)
3757 {
3758         struct drm_crtc *crtc;
3759         int htotal, hdisplay, clock, pixel_size;
3760         int line_time_us, line_count;
3761         int entries, tlb_miss;
3762
3763         crtc = intel_get_crtc_for_plane(dev, plane);
3764         if (crtc->fb == NULL || !crtc->enabled)
3765                 return false;
3766
3767         htotal = crtc->mode.htotal;
3768         hdisplay = crtc->mode.hdisplay;
3769         clock = crtc->mode.clock;
3770         pixel_size = crtc->fb->bits_per_pixel / 8;
3771
3772         /* Use the small buffer method to calculate plane watermark */
3773         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3774         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3775         if (tlb_miss > 0)
3776                 entries += tlb_miss;
3777         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3778         *plane_wm = entries + display->guard_size;
3779         if (*plane_wm > (int)display->max_wm)
3780                 *plane_wm = display->max_wm;
3781
3782         /* Use the large buffer method to calculate cursor watermark */
3783         line_time_us = ((htotal * 1000) / clock);
3784         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3785         entries = line_count * 64 * pixel_size;
3786         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3787         if (tlb_miss > 0)
3788                 entries += tlb_miss;
3789         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3790         *cursor_wm = entries + cursor->guard_size;
3791         if (*cursor_wm > (int)cursor->max_wm)
3792                 *cursor_wm = (int)cursor->max_wm;
3793
3794         return true;
3795 }
3796
3797 /*
3798  * Check the wm result.
3799  *
3800  * If any calculated watermark values is larger than the maximum value that
3801  * can be programmed into the associated watermark register, that watermark
3802  * must be disabled.
3803  */
3804 static bool g4x_check_srwm(struct drm_device *dev,
3805                            int display_wm, int cursor_wm,
3806                            const struct intel_watermark_params *display,
3807                            const struct intel_watermark_params *cursor)
3808 {
3809         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3810                       display_wm, cursor_wm);
3811
3812         if (display_wm > display->max_wm) {
3813                 DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",
3814                               display_wm, display->max_wm);
3815                 return false;
3816         }
3817
3818         if (cursor_wm > cursor->max_wm) {
3819                 DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",
3820                               cursor_wm, cursor->max_wm);
3821                 return false;
3822         }
3823
3824         if (!(display_wm || cursor_wm)) {
3825                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3826                 return false;
3827         }
3828
3829         return true;
3830 }
3831
3832 static bool g4x_compute_srwm(struct drm_device *dev,
3833                              int plane,
3834                              int latency_ns,
3835                              const struct intel_watermark_params *display,
3836                              const struct intel_watermark_params *cursor,
3837                              int *display_wm, int *cursor_wm)
3838 {
3839         struct drm_crtc *crtc;
3840         int hdisplay, htotal, pixel_size, clock;
3841         unsigned long line_time_us;
3842         int line_count, line_size;
3843         int small, large;
3844         int entries;
3845
3846         if (!latency_ns) {
3847                 *display_wm = *cursor_wm = 0;
3848                 return false;
3849         }
3850
3851         crtc = intel_get_crtc_for_plane(dev, plane);
3852         hdisplay = crtc->mode.hdisplay;
3853         htotal = crtc->mode.htotal;
3854         clock = crtc->mode.clock;
3855         pixel_size = crtc->fb->bits_per_pixel / 8;
3856
3857         line_time_us = (htotal * 1000) / clock;
3858         line_count = (latency_ns / line_time_us + 1000) / 1000;
3859         line_size = hdisplay * pixel_size;
3860
3861         /* Use the minimum of the small and large buffer method for primary */
3862         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3863         large = line_count * line_size;
3864
3865         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3866         *display_wm = entries + display->guard_size;
3867
3868         /* calculate the self-refresh watermark for display cursor */
3869         entries = line_count * pixel_size * 64;
3870         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3871         *cursor_wm = entries + cursor->guard_size;
3872
3873         return g4x_check_srwm(dev,
3874                               *display_wm, *cursor_wm,
3875                               display, cursor);
3876 }
3877
3878 static inline bool single_plane_enabled(unsigned int mask)
3879 {
3880         return mask && (mask & -mask) == 0;
3881 }
3882
3883 static void g4x_update_wm(struct drm_device *dev)
3884 {
3885         static const int sr_latency_ns = 12000;
3886         struct drm_i915_private *dev_priv = dev->dev_private;
3887         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3888         int plane_sr, cursor_sr;
3889         unsigned int enabled = 0;
3890
3891         if (g4x_compute_wm0(dev, 0,
3892                             &g4x_wm_info, latency_ns,
3893                             &g4x_cursor_wm_info, latency_ns,
3894                             &planea_wm, &cursora_wm))
3895                 enabled |= 1;
3896
3897         if (g4x_compute_wm0(dev, 1,
3898                             &g4x_wm_info, latency_ns,
3899                             &g4x_cursor_wm_info, latency_ns,
3900                             &planeb_wm, &cursorb_wm))
3901                 enabled |= 2;
3902
3903         plane_sr = cursor_sr = 0;
3904         if (single_plane_enabled(enabled) &&
3905             g4x_compute_srwm(dev, ffs(enabled) - 1,
3906                              sr_latency_ns,
3907                              &g4x_wm_info,
3908                              &g4x_cursor_wm_info,
3909                              &plane_sr, &cursor_sr))
3910                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3911         else
3912                 I915_WRITE(FW_BLC_SELF,
3913                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3914
3915         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3916                       planea_wm, cursora_wm,
3917                       planeb_wm, cursorb_wm,
3918                       plane_sr, cursor_sr);
3919
3920         I915_WRITE(DSPFW1,
3921                    (plane_sr << DSPFW_SR_SHIFT) |
3922                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3923                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
3924                    planea_wm);
3925         I915_WRITE(DSPFW2,
3926                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3927                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3928         /* HPLL off in SR has some issues on G4x... disable it */
3929         I915_WRITE(DSPFW3,
3930                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3931                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3932 }
3933
3934 static void i965_update_wm(struct drm_device *dev)
3935 {
3936         struct drm_i915_private *dev_priv = dev->dev_private;
3937         struct drm_crtc *crtc;
3938         int srwm = 1;
3939         int cursor_sr = 16;
3940
3941         /* Calc sr entries for one plane configs */
3942         crtc = single_enabled_crtc(dev);
3943         if (crtc) {
3944                 /* self-refresh has much higher latency */
3945                 static const int sr_latency_ns = 12000;
3946                 int clock = crtc->mode.clock;
3947                 int htotal = crtc->mode.htotal;
3948                 int hdisplay = crtc->mode.hdisplay;
3949                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3950                 unsigned long line_time_us;
3951                 int entries;
3952
3953                 line_time_us = ((htotal * 1000) / clock);
3954
3955                 /* Use ns/us then divide to preserve precision */
3956                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3957                         pixel_size * hdisplay;
3958                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3959                 srwm = I965_FIFO_SIZE - entries;
3960                 if (srwm < 0)
3961                         srwm = 1;
3962                 srwm &= 0x1ff;
3963                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3964                               entries, srwm);
3965
3966                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3967                         pixel_size * 64;
3968                 entries = DIV_ROUND_UP(entries,
3969                                           i965_cursor_wm_info.cacheline_size);
3970                 cursor_sr = i965_cursor_wm_info.fifo_size -
3971                         (entries + i965_cursor_wm_info.guard_size);
3972
3973                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3974                         cursor_sr = i965_cursor_wm_info.max_wm;
3975
3976                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3977                               "cursor %d\n", srwm, cursor_sr);
3978
3979                 if (IS_CRESTLINE(dev))
3980                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3981         } else {
3982                 /* Turn off self refresh if both pipes are enabled */
3983                 if (IS_CRESTLINE(dev))
3984                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3985                                    & ~FW_BLC_SELF_EN);
3986         }
3987
3988         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3989                       srwm);
3990
3991         /* 965 has limitations... */
3992         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3993                    (8 << 16) | (8 << 8) | (8 << 0));
3994         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3995         /* update cursor SR watermark */
3996         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3997 }
3998
3999 static void i9xx_update_wm(struct drm_device *dev)
4000 {
4001         struct drm_i915_private *dev_priv = dev->dev_private;
4002         const struct intel_watermark_params *wm_info;
4003         uint32_t fwater_lo;
4004         uint32_t fwater_hi;
4005         int cwm, srwm = 1;
4006         int fifo_size;
4007         int planea_wm, planeb_wm;
4008         struct drm_crtc *crtc, *enabled = NULL;
4009
4010         if (IS_I945GM(dev))
4011                 wm_info = &i945_wm_info;
4012         else if (!IS_GEN2(dev))
4013                 wm_info = &i915_wm_info;
4014         else
4015                 wm_info = &i855_wm_info;
4016
4017         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4018         crtc = intel_get_crtc_for_plane(dev, 0);
4019         if (crtc->enabled && crtc->fb) {
4020                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4021                                                wm_info, fifo_size,
4022                                                crtc->fb->bits_per_pixel / 8,
4023                                                latency_ns);
4024                 enabled = crtc;
4025         } else
4026                 planea_wm = fifo_size - wm_info->guard_size;
4027
4028         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4029         crtc = intel_get_crtc_for_plane(dev, 1);
4030         if (crtc->enabled && crtc->fb) {
4031                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4032                                                wm_info, fifo_size,
4033                                                crtc->fb->bits_per_pixel / 8,
4034                                                latency_ns);
4035                 if (enabled == NULL)
4036                         enabled = crtc;
4037                 else
4038                         enabled = NULL;
4039         } else
4040                 planeb_wm = fifo_size - wm_info->guard_size;
4041
4042         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4043
4044         /*
4045          * Overlay gets an aggressive default since video jitter is bad.
4046          */
4047         cwm = 2;
4048
4049         /* Play safe and disable self-refresh before adjusting watermarks. */
4050         if (IS_I945G(dev) || IS_I945GM(dev))
4051                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4052         else if (IS_I915GM(dev))
4053                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4054
4055         /* Calc sr entries for one plane configs */
4056         if (HAS_FW_BLC(dev) && enabled) {
4057                 /* self-refresh has much higher latency */
4058                 static const int sr_latency_ns = 6000;
4059                 int clock = enabled->mode.clock;
4060                 int htotal = enabled->mode.htotal;
4061                 int hdisplay = enabled->mode.hdisplay;
4062                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4063                 unsigned long line_time_us;
4064                 int entries;
4065
4066                 line_time_us = (htotal * 1000) / clock;
4067
4068                 /* Use ns/us then divide to preserve precision */
4069                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4070                         pixel_size * hdisplay;
4071                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4072                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4073                 srwm = wm_info->fifo_size - entries;
4074                 if (srwm < 0)
4075                         srwm = 1;
4076
4077                 if (IS_I945G(dev) || IS_I945GM(dev))
4078                         I915_WRITE(FW_BLC_SELF,
4079                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4080                 else if (IS_I915GM(dev))
4081                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4082         }
4083
4084         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4085                       planea_wm, planeb_wm, cwm, srwm);
4086
4087         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4088         fwater_hi = (cwm & 0x1f);
4089
4090         /* Set request length to 8 cachelines per fetch */
4091         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4092         fwater_hi = fwater_hi | (1 << 8);
4093
4094         I915_WRITE(FW_BLC, fwater_lo);
4095         I915_WRITE(FW_BLC2, fwater_hi);
4096
4097         if (HAS_FW_BLC(dev)) {
4098                 if (enabled) {
4099                         if (IS_I945G(dev) || IS_I945GM(dev))
4100                                 I915_WRITE(FW_BLC_SELF,
4101                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4102                         else if (IS_I915GM(dev))
4103                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4104                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4105                 } else
4106                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4107         }
4108 }
4109
4110 static void i830_update_wm(struct drm_device *dev)
4111 {
4112         struct drm_i915_private *dev_priv = dev->dev_private;
4113         struct drm_crtc *crtc;
4114         uint32_t fwater_lo;
4115         int planea_wm;
4116
4117         crtc = single_enabled_crtc(dev);
4118         if (crtc == NULL)
4119                 return;
4120
4121         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4122                                        dev_priv->display.get_fifo_size(dev, 0),
4123                                        crtc->fb->bits_per_pixel / 8,
4124                                        latency_ns);
4125         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4126         fwater_lo |= (3<<8) | planea_wm;
4127
4128         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4129
4130         I915_WRITE(FW_BLC, fwater_lo);
4131 }
4132
4133 #define ILK_LP0_PLANE_LATENCY           700
4134 #define ILK_LP0_CURSOR_LATENCY          1300
4135
4136 static bool ironlake_compute_wm0(struct drm_device *dev,
4137                                  int pipe,
4138                                  const struct intel_watermark_params *display,
4139                                  int display_latency_ns,
4140                                  const struct intel_watermark_params *cursor,
4141                                  int cursor_latency_ns,
4142                                  int *plane_wm,
4143                                  int *cursor_wm)
4144 {
4145         struct drm_crtc *crtc;
4146         int htotal, hdisplay, clock, pixel_size;
4147         int line_time_us, line_count;
4148         int entries, tlb_miss;
4149
4150         crtc = intel_get_crtc_for_pipe(dev, pipe);
4151         if (crtc->fb == NULL || !crtc->enabled)
4152                 return false;
4153
4154         htotal = crtc->mode.htotal;
4155         hdisplay = crtc->mode.hdisplay;
4156         clock = crtc->mode.clock;
4157         pixel_size = crtc->fb->bits_per_pixel / 8;
4158
4159         /* Use the small buffer method to calculate plane watermark */
4160         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4161         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4162         if (tlb_miss > 0)
4163                 entries += tlb_miss;
4164         entries = DIV_ROUND_UP(entries, display->cacheline_size);
4165         *plane_wm = entries + display->guard_size;
4166         if (*plane_wm > (int)display->max_wm)
4167                 *plane_wm = display->max_wm;
4168
4169         /* Use the large buffer method to calculate cursor watermark */
4170         line_time_us = ((htotal * 1000) / clock);
4171         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4172         entries = line_count * 64 * pixel_size;
4173         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4174         if (tlb_miss > 0)
4175                 entries += tlb_miss;
4176         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4177         *cursor_wm = entries + cursor->guard_size;
4178         if (*cursor_wm > (int)cursor->max_wm)
4179                 *cursor_wm = (int)cursor->max_wm;
4180
4181         return true;
4182 }
4183
4184 /*
4185  * Check the wm result.
4186  *
4187  * If any calculated watermark values is larger than the maximum value that
4188  * can be programmed into the associated watermark register, that watermark
4189  * must be disabled.
4190  */
4191 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4192                                 int fbc_wm, int display_wm, int cursor_wm,
4193                                 const struct intel_watermark_params *display,
4194                                 const struct intel_watermark_params *cursor)
4195 {
4196         struct drm_i915_private *dev_priv = dev->dev_private;
4197
4198         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4199                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4200
4201         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4202                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4203                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4204
4205                 /* fbc has it's own way to disable FBC WM */
4206                 I915_WRITE(DISP_ARB_CTL,
4207                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4208                 return false;
4209         }
4210
4211         if (display_wm > display->max_wm) {
4212                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4213                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4214                 return false;
4215         }
4216
4217         if (cursor_wm > cursor->max_wm) {
4218                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4219                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4220                 return false;
4221         }
4222
4223         if (!(fbc_wm || display_wm || cursor_wm)) {
4224                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4225                 return false;
4226         }
4227
4228         return true;
4229 }
4230
4231 /*
4232  * Compute watermark values of WM[1-3],
4233  */
4234 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4235                                   int latency_ns,
4236                                   const struct intel_watermark_params *display,
4237                                   const struct intel_watermark_params *cursor,
4238                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4239 {
4240         struct drm_crtc *crtc;
4241         unsigned long line_time_us;
4242         int hdisplay, htotal, pixel_size, clock;
4243         int line_count, line_size;
4244         int small, large;
4245         int entries;
4246
4247         if (!latency_ns) {
4248                 *fbc_wm = *display_wm = *cursor_wm = 0;
4249                 return false;
4250         }
4251
4252         crtc = intel_get_crtc_for_plane(dev, plane);
4253         hdisplay = crtc->mode.hdisplay;
4254         htotal = crtc->mode.htotal;
4255         clock = crtc->mode.clock;
4256         pixel_size = crtc->fb->bits_per_pixel / 8;
4257
4258         line_time_us = (htotal * 1000) / clock;
4259         line_count = (latency_ns / line_time_us + 1000) / 1000;
4260         line_size = hdisplay * pixel_size;
4261
4262         /* Use the minimum of the small and large buffer method for primary */
4263         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4264         large = line_count * line_size;
4265
4266         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4267         *display_wm = entries + display->guard_size;
4268
4269         /*
4270          * Spec says:
4271          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4272          */
4273         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4274
4275         /* calculate the self-refresh watermark for display cursor */
4276         entries = line_count * pixel_size * 64;
4277         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4278         *cursor_wm = entries + cursor->guard_size;
4279
4280         return ironlake_check_srwm(dev, level,
4281                                    *fbc_wm, *display_wm, *cursor_wm,
4282                                    display, cursor);
4283 }
4284
4285 static void ironlake_update_wm(struct drm_device *dev)
4286 {
4287         struct drm_i915_private *dev_priv = dev->dev_private;
4288         int fbc_wm, plane_wm, cursor_wm;
4289         unsigned int enabled;
4290
4291         enabled = 0;
4292         if (ironlake_compute_wm0(dev, 0,
4293                                  &ironlake_display_wm_info,
4294                                  ILK_LP0_PLANE_LATENCY,
4295                                  &ironlake_cursor_wm_info,
4296                                  ILK_LP0_CURSOR_LATENCY,
4297                                  &plane_wm, &cursor_wm)) {
4298                 I915_WRITE(WM0_PIPEA_ILK,
4299                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4300                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4301                               " plane %d, " "cursor: %d\n",
4302                               plane_wm, cursor_wm);
4303                 enabled |= 1;
4304         }
4305
4306         if (ironlake_compute_wm0(dev, 1,
4307                                  &ironlake_display_wm_info,
4308                                  ILK_LP0_PLANE_LATENCY,
4309                                  &ironlake_cursor_wm_info,
4310                                  ILK_LP0_CURSOR_LATENCY,
4311                                  &plane_wm, &cursor_wm)) {
4312                 I915_WRITE(WM0_PIPEB_ILK,
4313                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4314                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4315                               " plane %d, cursor: %d\n",
4316                               plane_wm, cursor_wm);
4317                 enabled |= 2;
4318         }
4319
4320         /*
4321          * Calculate and update the self-refresh watermark only when one
4322          * display plane is used.
4323          */
4324         I915_WRITE(WM3_LP_ILK, 0);
4325         I915_WRITE(WM2_LP_ILK, 0);
4326         I915_WRITE(WM1_LP_ILK, 0);
4327
4328         if (!single_plane_enabled(enabled))
4329                 return;
4330         enabled = ffs(enabled) - 1;
4331
4332         /* WM1 */
4333         if (!ironlake_compute_srwm(dev, 1, enabled,
4334                                    ILK_READ_WM1_LATENCY() * 500,
4335                                    &ironlake_display_srwm_info,
4336                                    &ironlake_cursor_srwm_info,
4337                                    &fbc_wm, &plane_wm, &cursor_wm))
4338                 return;
4339
4340         I915_WRITE(WM1_LP_ILK,
4341                    WM1_LP_SR_EN |
4342                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4343                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4344                    (plane_wm << WM1_LP_SR_SHIFT) |
4345                    cursor_wm);
4346
4347         /* WM2 */
4348         if (!ironlake_compute_srwm(dev, 2, enabled,
4349                                    ILK_READ_WM2_LATENCY() * 500,
4350                                    &ironlake_display_srwm_info,
4351                                    &ironlake_cursor_srwm_info,
4352                                    &fbc_wm, &plane_wm, &cursor_wm))
4353                 return;
4354
4355         I915_WRITE(WM2_LP_ILK,
4356                    WM2_LP_EN |
4357                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4358                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4359                    (plane_wm << WM1_LP_SR_SHIFT) |
4360                    cursor_wm);
4361
4362         /*
4363          * WM3 is unsupported on ILK, probably because we don't have latency
4364          * data for that power state
4365          */
4366 }
4367
4368 static void sandybridge_update_wm(struct drm_device *dev)
4369 {
4370         struct drm_i915_private *dev_priv = dev->dev_private;
4371         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4372         int fbc_wm, plane_wm, cursor_wm;
4373         unsigned int enabled;
4374
4375         enabled = 0;
4376         if (ironlake_compute_wm0(dev, 0,
4377                                  &sandybridge_display_wm_info, latency,
4378                                  &sandybridge_cursor_wm_info, latency,
4379                                  &plane_wm, &cursor_wm)) {
4380                 I915_WRITE(WM0_PIPEA_ILK,
4381                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4382                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4383                               " plane %d, " "cursor: %d\n",
4384                               plane_wm, cursor_wm);
4385                 enabled |= 1;
4386         }
4387
4388         if (ironlake_compute_wm0(dev, 1,
4389                                  &sandybridge_display_wm_info, latency,
4390                                  &sandybridge_cursor_wm_info, latency,
4391                                  &plane_wm, &cursor_wm)) {
4392                 I915_WRITE(WM0_PIPEB_ILK,
4393                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4394                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4395                               " plane %d, cursor: %d\n",
4396                               plane_wm, cursor_wm);
4397                 enabled |= 2;
4398         }
4399
4400         /*
4401          * Calculate and update the self-refresh watermark only when one
4402          * display plane is used.
4403          *
4404          * SNB support 3 levels of watermark.
4405          *
4406          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4407          * and disabled in the descending order
4408          *
4409          */
4410         I915_WRITE(WM3_LP_ILK, 0);
4411         I915_WRITE(WM2_LP_ILK, 0);
4412         I915_WRITE(WM1_LP_ILK, 0);
4413
4414         if (!single_plane_enabled(enabled))
4415                 return;
4416         enabled = ffs(enabled) - 1;
4417
4418         /* WM1 */
4419         if (!ironlake_compute_srwm(dev, 1, enabled,
4420                                    SNB_READ_WM1_LATENCY() * 500,
4421                                    &sandybridge_display_srwm_info,
4422                                    &sandybridge_cursor_srwm_info,
4423                                    &fbc_wm, &plane_wm, &cursor_wm))
4424                 return;
4425
4426         I915_WRITE(WM1_LP_ILK,
4427                    WM1_LP_SR_EN |
4428                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4429                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4430                    (plane_wm << WM1_LP_SR_SHIFT) |
4431                    cursor_wm);
4432
4433         /* WM2 */
4434         if (!ironlake_compute_srwm(dev, 2, enabled,
4435                                    SNB_READ_WM2_LATENCY() * 500,
4436                                    &sandybridge_display_srwm_info,
4437                                    &sandybridge_cursor_srwm_info,
4438                                    &fbc_wm, &plane_wm, &cursor_wm))
4439                 return;
4440
4441         I915_WRITE(WM2_LP_ILK,
4442                    WM2_LP_EN |
4443                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4444                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4445                    (plane_wm << WM1_LP_SR_SHIFT) |
4446                    cursor_wm);
4447
4448         /* WM3 */
4449         if (!ironlake_compute_srwm(dev, 3, enabled,
4450                                    SNB_READ_WM3_LATENCY() * 500,
4451                                    &sandybridge_display_srwm_info,
4452                                    &sandybridge_cursor_srwm_info,
4453                                    &fbc_wm, &plane_wm, &cursor_wm))
4454                 return;
4455
4456         I915_WRITE(WM3_LP_ILK,
4457                    WM3_LP_EN |
4458                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4459                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4460                    (plane_wm << WM1_LP_SR_SHIFT) |
4461                    cursor_wm);
4462 }
4463
4464 /**
4465  * intel_update_watermarks - update FIFO watermark values based on current modes
4466  *
4467  * Calculate watermark values for the various WM regs based on current mode
4468  * and plane configuration.
4469  *
4470  * There are several cases to deal with here:
4471  *   - normal (i.e. non-self-refresh)
4472  *   - self-refresh (SR) mode
4473  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4474  *   - lines are small relative to FIFO size (buffer can hold more than 2
4475  *     lines), so need to account for TLB latency
4476  *
4477  *   The normal calculation is:
4478  *     watermark = dotclock * bytes per pixel * latency
4479  *   where latency is platform & configuration dependent (we assume pessimal
4480  *   values here).
4481  *
4482  *   The SR calculation is:
4483  *     watermark = (trunc(latency/line time)+1) * surface width *
4484  *       bytes per pixel
4485  *   where
4486  *     line time = htotal / dotclock
4487  *     surface width = hdisplay for normal plane and 64 for cursor
4488  *   and latency is assumed to be high, as above.
4489  *
4490  * The final value programmed to the register should always be rounded up,
4491  * and include an extra 2 entries to account for clock crossings.
4492  *
4493  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4494  * to set the non-SR watermarks to 8.
4495  */
4496 static void intel_update_watermarks(struct drm_device *dev)
4497 {
4498         struct drm_i915_private *dev_priv = dev->dev_private;
4499
4500         if (dev_priv->display.update_wm)
4501                 dev_priv->display.update_wm(dev);
4502 }
4503
4504 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4505 {
4506         return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4507 }
4508
4509 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4510                                struct drm_display_mode *mode,
4511                                struct drm_display_mode *adjusted_mode,
4512                                int x, int y,
4513                                struct drm_framebuffer *old_fb)
4514 {
4515         struct drm_device *dev = crtc->dev;
4516         struct drm_i915_private *dev_priv = dev->dev_private;
4517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4518         int pipe = intel_crtc->pipe;
4519         int plane = intel_crtc->plane;
4520         u32 fp_reg, dpll_reg;
4521         int refclk, num_connectors = 0;
4522         intel_clock_t clock, reduced_clock;
4523         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4524         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4525         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4526         struct intel_encoder *has_edp_encoder = NULL;
4527         struct drm_mode_config *mode_config = &dev->mode_config;
4528         struct intel_encoder *encoder;
4529         const intel_limit_t *limit;
4530         int ret;
4531         struct fdi_m_n m_n = {0};
4532         u32 reg, temp;
4533         u32 lvds_sync = 0;
4534         int target_clock;
4535
4536         drm_vblank_pre_modeset(dev, pipe);
4537
4538         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4539                 if (encoder->base.crtc != crtc)
4540                         continue;
4541
4542                 switch (encoder->type) {
4543                 case INTEL_OUTPUT_LVDS:
4544                         is_lvds = true;
4545                         break;
4546                 case INTEL_OUTPUT_SDVO:
4547                 case INTEL_OUTPUT_HDMI:
4548                         is_sdvo = true;
4549                         if (encoder->needs_tv_clock)
4550                                 is_tv = true;
4551                         break;
4552                 case INTEL_OUTPUT_DVO:
4553                         is_dvo = true;
4554                         break;
4555                 case INTEL_OUTPUT_TVOUT:
4556                         is_tv = true;
4557                         break;
4558                 case INTEL_OUTPUT_ANALOG:
4559                         is_crt = true;
4560                         break;
4561                 case INTEL_OUTPUT_DISPLAYPORT:
4562                         is_dp = true;
4563                         break;
4564                 case INTEL_OUTPUT_EDP:
4565                         has_edp_encoder = encoder;
4566                         break;
4567                 }
4568
4569                 num_connectors++;
4570         }
4571
4572         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4573                 refclk = dev_priv->lvds_ssc_freq * 1000;
4574                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4575                               refclk / 1000);
4576         } else if (!IS_GEN2(dev)) {
4577                 refclk = 96000;
4578                 if (HAS_PCH_SPLIT(dev) &&
4579                     (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
4580                         refclk = 120000; /* 120Mhz refclk */
4581         } else {
4582                 refclk = 48000;
4583         }
4584
4585         /*
4586          * Returns a set of divisors for the desired target clock with the given
4587          * refclk, or FALSE.  The returned values represent the clock equation:
4588          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4589          */
4590         limit = intel_limit(crtc, refclk);
4591         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4592         if (!ok) {
4593                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4594                 drm_vblank_post_modeset(dev, pipe);
4595                 return -EINVAL;
4596         }
4597
4598         /* Ensure that the cursor is valid for the new mode before changing... */
4599         intel_crtc_update_cursor(crtc, true);
4600
4601         if (is_lvds && dev_priv->lvds_downclock_avail) {
4602                 has_reduced_clock = limit->find_pll(limit, crtc,
4603                                                     dev_priv->lvds_downclock,
4604                                                     refclk,
4605                                                     &reduced_clock);
4606                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4607                         /*
4608                          * If the different P is found, it means that we can't
4609                          * switch the display clock by using the FP0/FP1.
4610                          * In such case we will disable the LVDS downclock
4611                          * feature.
4612                          */
4613                         DRM_DEBUG_KMS("Different P is found for "
4614                                       "LVDS clock/downclock\n");
4615                         has_reduced_clock = 0;
4616                 }
4617         }
4618         /* SDVO TV has fixed PLL values depend on its clock range,
4619            this mirrors vbios setting. */
4620         if (is_sdvo && is_tv) {
4621                 if (adjusted_mode->clock >= 100000
4622                     && adjusted_mode->clock < 140500) {
4623                         clock.p1 = 2;
4624                         clock.p2 = 10;
4625                         clock.n = 3;
4626                         clock.m1 = 16;
4627                         clock.m2 = 8;
4628                 } else if (adjusted_mode->clock >= 140500
4629                            && adjusted_mode->clock <= 200000) {
4630                         clock.p1 = 1;
4631                         clock.p2 = 10;
4632                         clock.n = 6;
4633                         clock.m1 = 12;
4634                         clock.m2 = 8;
4635                 }
4636         }
4637
4638         /* FDI link */
4639         if (HAS_PCH_SPLIT(dev)) {
4640                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4641                 int lane = 0, link_bw, bpp;
4642                 /* CPU eDP doesn't require FDI link, so just set DP M/N
4643                    according to current link config */
4644                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4645                         target_clock = mode->clock;
4646                         intel_edp_link_config(has_edp_encoder,
4647                                               &lane, &link_bw);
4648                 } else {
4649                         /* [e]DP over FDI requires target mode clock
4650                            instead of link clock */
4651                         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4652                                 target_clock = mode->clock;
4653                         else
4654                                 target_clock = adjusted_mode->clock;
4655
4656                         /* FDI is a binary signal running at ~2.7GHz, encoding
4657                          * each output octet as 10 bits. The actual frequency
4658                          * is stored as a divider into a 100MHz clock, and the
4659                          * mode pixel clock is stored in units of 1KHz.
4660                          * Hence the bw of each lane in terms of the mode signal
4661                          * is:
4662                          */
4663                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4664                 }
4665
4666                 /* determine panel color depth */
4667                 temp = I915_READ(PIPECONF(pipe));
4668                 temp &= ~PIPE_BPC_MASK;
4669                 if (is_lvds) {
4670                         /* the BPC will be 6 if it is 18-bit LVDS panel */
4671                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4672                                 temp |= PIPE_8BPC;
4673                         else
4674                                 temp |= PIPE_6BPC;
4675                 } else if (has_edp_encoder) {
4676                         switch (dev_priv->edp.bpp/3) {
4677                         case 8:
4678                                 temp |= PIPE_8BPC;
4679                                 break;
4680                         case 10:
4681                                 temp |= PIPE_10BPC;
4682                                 break;
4683                         case 6:
4684                                 temp |= PIPE_6BPC;
4685                                 break;
4686                         case 12:
4687                                 temp |= PIPE_12BPC;
4688                                 break;
4689                         }
4690                 } else
4691                         temp |= PIPE_8BPC;
4692                 I915_WRITE(PIPECONF(pipe), temp);
4693
4694                 switch (temp & PIPE_BPC_MASK) {
4695                 case PIPE_8BPC:
4696                         bpp = 24;
4697                         break;
4698                 case PIPE_10BPC:
4699                         bpp = 30;
4700                         break;
4701                 case PIPE_6BPC:
4702                         bpp = 18;
4703                         break;
4704                 case PIPE_12BPC:
4705                         bpp = 36;
4706                         break;
4707                 default:
4708                         DRM_ERROR("unknown pipe bpc value\n");
4709                         bpp = 24;
4710                 }
4711
4712                 if (!lane) {
4713                         /*
4714                          * Account for spread spectrum to avoid
4715                          * oversubscribing the link. Max center spread
4716                          * is 2.5%; use 5% for safety's sake.
4717                          */
4718                         u32 bps = target_clock * bpp * 21 / 20;
4719                         lane = bps / (link_bw * 8) + 1;
4720                 }
4721
4722                 intel_crtc->fdi_lanes = lane;
4723
4724                 if (pixel_multiplier > 1)
4725                         link_bw *= pixel_multiplier;
4726                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4727         }
4728
4729         /* Ironlake: try to setup display ref clock before DPLL
4730          * enabling. This is only under driver's control after
4731          * PCH B stepping, previous chipset stepping should be
4732          * ignoring this setting.
4733          */
4734         if (HAS_PCH_SPLIT(dev)) {
4735                 temp = I915_READ(PCH_DREF_CONTROL);
4736                 /* Always enable nonspread source */
4737                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4738                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4739                 temp &= ~DREF_SSC_SOURCE_MASK;
4740                 temp |= DREF_SSC_SOURCE_ENABLE;
4741                 I915_WRITE(PCH_DREF_CONTROL, temp);
4742
4743                 POSTING_READ(PCH_DREF_CONTROL);
4744                 udelay(200);
4745
4746                 if (has_edp_encoder) {
4747                         if (intel_panel_use_ssc(dev_priv)) {
4748                                 temp |= DREF_SSC1_ENABLE;
4749                                 I915_WRITE(PCH_DREF_CONTROL, temp);
4750
4751                                 POSTING_READ(PCH_DREF_CONTROL);
4752                                 udelay(200);
4753                         }
4754                         temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4755
4756                         /* Enable CPU source on CPU attached eDP */
4757                         if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4758                                 if (intel_panel_use_ssc(dev_priv))
4759                                         temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4760                                 else
4761                                         temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4762                         } else {
4763                                 /* Enable SSC on PCH eDP if needed */
4764                                 if (intel_panel_use_ssc(dev_priv)) {
4765                                         DRM_ERROR("enabling SSC on PCH\n");
4766                                         temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4767                                 }
4768                         }
4769                         I915_WRITE(PCH_DREF_CONTROL, temp);
4770                         POSTING_READ(PCH_DREF_CONTROL);
4771                         udelay(200);
4772                 }
4773         }
4774
4775         if (IS_PINEVIEW(dev)) {
4776                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4777                 if (has_reduced_clock)
4778                         fp2 = (1 << reduced_clock.n) << 16 |
4779                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4780         } else {
4781                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4782                 if (has_reduced_clock)
4783                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4784                                 reduced_clock.m2;
4785         }
4786
4787         /* Enable autotuning of the PLL clock (if permissible) */
4788         if (HAS_PCH_SPLIT(dev)) {
4789                 int factor = 21;
4790
4791                 if (is_lvds) {
4792                         if ((intel_panel_use_ssc(dev_priv) &&
4793                              dev_priv->lvds_ssc_freq == 100) ||
4794                             (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4795                                 factor = 25;
4796                 } else if (is_sdvo && is_tv)
4797                         factor = 20;
4798
4799                 if (clock.m1 < factor * clock.n)
4800                         fp |= FP_CB_TUNE;
4801         }
4802
4803         dpll = 0;
4804         if (!HAS_PCH_SPLIT(dev))
4805                 dpll = DPLL_VGA_MODE_DIS;
4806
4807         if (!IS_GEN2(dev)) {
4808                 if (is_lvds)
4809                         dpll |= DPLLB_MODE_LVDS;
4810                 else
4811                         dpll |= DPLLB_MODE_DAC_SERIAL;
4812                 if (is_sdvo) {
4813                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4814                         if (pixel_multiplier > 1) {
4815                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4816                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4817                                 else if (HAS_PCH_SPLIT(dev))
4818                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4819                         }
4820                         dpll |= DPLL_DVO_HIGH_SPEED;
4821                 }
4822                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4823                         dpll |= DPLL_DVO_HIGH_SPEED;
4824
4825                 /* compute bitmask from p1 value */
4826                 if (IS_PINEVIEW(dev))
4827                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4828                 else {
4829                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4830                         /* also FPA1 */
4831                         if (HAS_PCH_SPLIT(dev))
4832                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4833                         if (IS_G4X(dev) && has_reduced_clock)
4834                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4835                 }
4836                 switch (clock.p2) {
4837                 case 5:
4838                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4839                         break;
4840                 case 7:
4841                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4842                         break;
4843                 case 10:
4844                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4845                         break;
4846                 case 14:
4847                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4848                         break;
4849                 }
4850                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
4851                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4852         } else {
4853                 if (is_lvds) {
4854                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4855                 } else {
4856                         if (clock.p1 == 2)
4857                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4858                         else
4859                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4860                         if (clock.p2 == 4)
4861                                 dpll |= PLL_P2_DIVIDE_BY_4;
4862                 }
4863         }
4864
4865         if (is_sdvo && is_tv)
4866                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4867         else if (is_tv)
4868                 /* XXX: just matching BIOS for now */
4869                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4870                 dpll |= 3;
4871         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4872                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4873         else
4874                 dpll |= PLL_REF_INPUT_DREFCLK;
4875
4876         /* setup pipeconf */
4877         pipeconf = I915_READ(PIPECONF(pipe));
4878
4879         /* Set up the display plane register */
4880         dspcntr = DISPPLANE_GAMMA_ENABLE;
4881
4882         /* Ironlake's plane is forced to pipe, bit 24 is to
4883            enable color space conversion */
4884         if (!HAS_PCH_SPLIT(dev)) {
4885                 if (pipe == 0)
4886                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4887                 else
4888                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4889         }
4890
4891         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4892                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4893                  * core speed.
4894                  *
4895                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4896                  * pipe == 0 check?
4897                  */
4898                 if (mode->clock >
4899                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4900                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4901                 else
4902                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4903         }
4904
4905         if (!HAS_PCH_SPLIT(dev))
4906                 dpll |= DPLL_VCO_ENABLE;
4907
4908         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4909         drm_mode_debug_printmodeline(mode);
4910
4911         /* assign to Ironlake registers */
4912         if (HAS_PCH_SPLIT(dev)) {
4913                 fp_reg = PCH_FP0(pipe);
4914                 dpll_reg = PCH_DPLL(pipe);
4915         } else {
4916                 fp_reg = FP0(pipe);
4917                 dpll_reg = DPLL(pipe);
4918         }
4919
4920         /* PCH eDP needs FDI, but CPU eDP does not */
4921         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4922                 I915_WRITE(fp_reg, fp);
4923                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4924
4925                 POSTING_READ(dpll_reg);
4926                 udelay(150);
4927         }
4928
4929         /* enable transcoder DPLL */
4930         if (HAS_PCH_CPT(dev)) {
4931                 temp = I915_READ(PCH_DPLL_SEL);
4932                 switch (pipe) {
4933                 case 0:
4934                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4935                         break;
4936                 case 1:
4937                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4938                         break;
4939                 case 2:
4940                         /* FIXME: manage transcoder PLLs? */
4941                         temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
4942                         break;
4943                 default:
4944                         BUG();
4945                 }
4946                 I915_WRITE(PCH_DPLL_SEL, temp);
4947
4948                 POSTING_READ(PCH_DPLL_SEL);
4949                 udelay(150);
4950         }
4951
4952         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4953          * This is an exception to the general rule that mode_set doesn't turn
4954          * things on.
4955          */
4956         if (is_lvds) {
4957                 reg = LVDS;
4958                 if (HAS_PCH_SPLIT(dev))
4959                         reg = PCH_LVDS;
4960
4961                 temp = I915_READ(reg);
4962                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4963                 if (pipe == 1) {
4964                         if (HAS_PCH_CPT(dev))
4965                                 temp |= PORT_TRANS_B_SEL_CPT;
4966                         else
4967                                 temp |= LVDS_PIPEB_SELECT;
4968                 } else {
4969                         if (HAS_PCH_CPT(dev))
4970                                 temp &= ~PORT_TRANS_SEL_MASK;
4971                         else
4972                                 temp &= ~LVDS_PIPEB_SELECT;
4973                 }
4974                 /* set the corresponsding LVDS_BORDER bit */
4975                 temp |= dev_priv->lvds_border_bits;
4976                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4977                  * set the DPLLs for dual-channel mode or not.
4978                  */
4979                 if (clock.p2 == 7)
4980                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4981                 else
4982                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4983
4984                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4985                  * appropriately here, but we need to look more thoroughly into how
4986                  * panels behave in the two modes.
4987                  */
4988                 /* set the dithering flag on non-PCH LVDS as needed */
4989                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4990                         if (dev_priv->lvds_dither)
4991                                 temp |= LVDS_ENABLE_DITHER;
4992                         else
4993                                 temp &= ~LVDS_ENABLE_DITHER;
4994                 }
4995                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4996                         lvds_sync |= LVDS_HSYNC_POLARITY;
4997                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4998                         lvds_sync |= LVDS_VSYNC_POLARITY;
4999                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5000                     != lvds_sync) {
5001                         char flags[2] = "-+";
5002                         DRM_INFO("Changing LVDS panel from "
5003                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5004                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5005                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5006                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5007                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5008                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5009                         temp |= lvds_sync;
5010                 }
5011                 I915_WRITE(reg, temp);
5012         }
5013
5014         /* set the dithering flag and clear for anything other than a panel. */
5015         if (HAS_PCH_SPLIT(dev)) {
5016                 pipeconf &= ~PIPECONF_DITHER_EN;
5017                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5018                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5019                         pipeconf |= PIPECONF_DITHER_EN;
5020                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5021                 }
5022         }
5023
5024         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5025                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5026         } else if (HAS_PCH_SPLIT(dev)) {
5027                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5028                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5029                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5030                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5031                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5032         }
5033
5034         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5035                 I915_WRITE(dpll_reg, dpll);
5036
5037                 /* Wait for the clocks to stabilize. */
5038                 POSTING_READ(dpll_reg);
5039                 udelay(150);
5040
5041                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
5042                         temp = 0;
5043                         if (is_sdvo) {
5044                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5045                                 if (temp > 1)
5046                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5047                                 else
5048                                         temp = 0;
5049                         }
5050                         I915_WRITE(DPLL_MD(pipe), temp);
5051                 } else {
5052                         /* The pixel multiplier can only be updated once the
5053                          * DPLL is enabled and the clocks are stable.
5054                          *
5055                          * So write it again.
5056                          */
5057                         I915_WRITE(dpll_reg, dpll);
5058                 }
5059         }
5060
5061         intel_crtc->lowfreq_avail = false;
5062         if (is_lvds && has_reduced_clock && i915_powersave) {
5063                 I915_WRITE(fp_reg + 4, fp2);
5064                 intel_crtc->lowfreq_avail = true;
5065                 if (HAS_PIPE_CXSR(dev)) {
5066                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5067                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5068                 }
5069         } else {
5070                 I915_WRITE(fp_reg + 4, fp);
5071                 if (HAS_PIPE_CXSR(dev)) {
5072                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5073                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5074                 }
5075         }
5076
5077         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5078                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5079                 /* the chip adds 2 halflines automatically */
5080                 adjusted_mode->crtc_vdisplay -= 1;
5081                 adjusted_mode->crtc_vtotal -= 1;
5082                 adjusted_mode->crtc_vblank_start -= 1;
5083                 adjusted_mode->crtc_vblank_end -= 1;
5084                 adjusted_mode->crtc_vsync_end -= 1;
5085                 adjusted_mode->crtc_vsync_start -= 1;
5086         } else
5087                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5088
5089         I915_WRITE(HTOTAL(pipe),
5090                    (adjusted_mode->crtc_hdisplay - 1) |
5091                    ((adjusted_mode->crtc_htotal - 1) << 16));
5092         I915_WRITE(HBLANK(pipe),
5093                    (adjusted_mode->crtc_hblank_start - 1) |
5094                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5095         I915_WRITE(HSYNC(pipe),
5096                    (adjusted_mode->crtc_hsync_start - 1) |
5097                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5098
5099         I915_WRITE(VTOTAL(pipe),
5100                    (adjusted_mode->crtc_vdisplay - 1) |
5101                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5102         I915_WRITE(VBLANK(pipe),
5103                    (adjusted_mode->crtc_vblank_start - 1) |
5104                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5105         I915_WRITE(VSYNC(pipe),
5106                    (adjusted_mode->crtc_vsync_start - 1) |
5107                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5108
5109         /* pipesrc and dspsize control the size that is scaled from,
5110          * which should always be the user's requested size.
5111          */
5112         if (!HAS_PCH_SPLIT(dev)) {
5113                 I915_WRITE(DSPSIZE(plane),
5114                            ((mode->vdisplay - 1) << 16) |
5115                            (mode->hdisplay - 1));
5116                 I915_WRITE(DSPPOS(plane), 0);
5117         }
5118         I915_WRITE(PIPESRC(pipe),
5119                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5120
5121         if (HAS_PCH_SPLIT(dev)) {
5122                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5123                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5124                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5125                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5126
5127                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5128                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5129                 }
5130         }
5131
5132         I915_WRITE(PIPECONF(pipe), pipeconf);
5133         POSTING_READ(PIPECONF(pipe));
5134         if (!HAS_PCH_SPLIT(dev))
5135                 intel_enable_pipe(dev_priv, pipe, false);
5136
5137         intel_wait_for_vblank(dev, pipe);
5138
5139         if (IS_GEN5(dev)) {
5140                 /* enable address swizzle for tiling buffer */
5141                 temp = I915_READ(DISP_ARB_CTL);
5142                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5143         }
5144
5145         I915_WRITE(DSPCNTR(plane), dspcntr);
5146         POSTING_READ(DSPCNTR(plane));
5147         if (!HAS_PCH_SPLIT(dev))
5148                 intel_enable_plane(dev_priv, plane, pipe);
5149
5150         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5151
5152         intel_update_watermarks(dev);
5153
5154         drm_vblank_post_modeset(dev, pipe);
5155
5156         return ret;
5157 }
5158
5159 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5160 void intel_crtc_load_lut(struct drm_crtc *crtc)
5161 {
5162         struct drm_device *dev = crtc->dev;
5163         struct drm_i915_private *dev_priv = dev->dev_private;
5164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5165         int palreg = PALETTE(intel_crtc->pipe);
5166         int i;
5167
5168         /* The clocks have to be on to load the palette. */
5169         if (!crtc->enabled)
5170                 return;
5171
5172         /* use legacy palette for Ironlake */
5173         if (HAS_PCH_SPLIT(dev))
5174                 palreg = LGC_PALETTE(intel_crtc->pipe);
5175
5176         for (i = 0; i < 256; i++) {
5177                 I915_WRITE(palreg + 4 * i,
5178                            (intel_crtc->lut_r[i] << 16) |
5179                            (intel_crtc->lut_g[i] << 8) |
5180                            intel_crtc->lut_b[i]);
5181         }
5182 }
5183
5184 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5185 {
5186         struct drm_device *dev = crtc->dev;
5187         struct drm_i915_private *dev_priv = dev->dev_private;
5188         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5189         bool visible = base != 0;
5190         u32 cntl;
5191
5192         if (intel_crtc->cursor_visible == visible)
5193                 return;
5194
5195         cntl = I915_READ(_CURACNTR);
5196         if (visible) {
5197                 /* On these chipsets we can only modify the base whilst
5198                  * the cursor is disabled.
5199                  */
5200                 I915_WRITE(_CURABASE, base);
5201
5202                 cntl &= ~(CURSOR_FORMAT_MASK);
5203                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5204                 cntl |= CURSOR_ENABLE |
5205                         CURSOR_GAMMA_ENABLE |
5206                         CURSOR_FORMAT_ARGB;
5207         } else
5208                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5209         I915_WRITE(_CURACNTR, cntl);
5210
5211         intel_crtc->cursor_visible = visible;
5212 }
5213
5214 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5215 {
5216         struct drm_device *dev = crtc->dev;
5217         struct drm_i915_private *dev_priv = dev->dev_private;
5218         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5219         int pipe = intel_crtc->pipe;
5220         bool visible = base != 0;
5221
5222         if (intel_crtc->cursor_visible != visible) {
5223                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5224                 if (base) {
5225                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5226                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5227                         cntl |= pipe << 28; /* Connect to correct pipe */
5228                 } else {
5229                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5230                         cntl |= CURSOR_MODE_DISABLE;
5231                 }
5232                 I915_WRITE(CURCNTR(pipe), cntl);
5233
5234                 intel_crtc->cursor_visible = visible;
5235         }
5236         /* and commit changes on next vblank */
5237         I915_WRITE(CURBASE(pipe), base);
5238 }
5239
5240 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5241 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5242                                      bool on)
5243 {
5244         struct drm_device *dev = crtc->dev;
5245         struct drm_i915_private *dev_priv = dev->dev_private;
5246         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5247         int pipe = intel_crtc->pipe;
5248         int x = intel_crtc->cursor_x;
5249         int y = intel_crtc->cursor_y;
5250         u32 base, pos;
5251         bool visible;
5252
5253         pos = 0;
5254
5255         if (on && crtc->enabled && crtc->fb) {
5256                 base = intel_crtc->cursor_addr;
5257                 if (x > (int) crtc->fb->width)
5258                         base = 0;
5259
5260                 if (y > (int) crtc->fb->height)
5261                         base = 0;
5262         } else
5263                 base = 0;
5264
5265         if (x < 0) {
5266                 if (x + intel_crtc->cursor_width < 0)
5267                         base = 0;
5268
5269                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5270                 x = -x;
5271         }
5272         pos |= x << CURSOR_X_SHIFT;
5273
5274         if (y < 0) {
5275                 if (y + intel_crtc->cursor_height < 0)
5276                         base = 0;
5277
5278                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5279                 y = -y;
5280         }
5281         pos |= y << CURSOR_Y_SHIFT;
5282
5283         visible = base != 0;
5284         if (!visible && !intel_crtc->cursor_visible)
5285                 return;
5286
5287         I915_WRITE(CURPOS(pipe), pos);
5288         if (IS_845G(dev) || IS_I865G(dev))
5289                 i845_update_cursor(crtc, base);
5290         else
5291                 i9xx_update_cursor(crtc, base);
5292
5293         if (visible)
5294                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5295 }
5296
5297 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5298                                  struct drm_file *file,
5299                                  uint32_t handle,
5300                                  uint32_t width, uint32_t height)
5301 {
5302         struct drm_device *dev = crtc->dev;
5303         struct drm_i915_private *dev_priv = dev->dev_private;
5304         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5305         struct drm_i915_gem_object *obj;
5306         uint32_t addr;
5307         int ret;
5308
5309         DRM_DEBUG_KMS("\n");
5310
5311         /* if we want to turn off the cursor ignore width and height */
5312         if (!handle) {
5313                 DRM_DEBUG_KMS("cursor off\n");
5314                 addr = 0;
5315                 obj = NULL;
5316                 mutex_lock(&dev->struct_mutex);
5317                 goto finish;
5318         }
5319
5320         /* Currently we only support 64x64 cursors */
5321         if (width != 64 || height != 64) {
5322                 DRM_ERROR("we currently only support 64x64 cursors\n");
5323                 return -EINVAL;
5324         }
5325
5326         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5327         if (&obj->base == NULL)
5328                 return -ENOENT;
5329
5330         if (obj->base.size < width * height * 4) {
5331                 DRM_ERROR("buffer is to small\n");
5332                 ret = -ENOMEM;
5333                 goto fail;
5334         }
5335
5336         /* we only need to pin inside GTT if cursor is non-phy */
5337         mutex_lock(&dev->struct_mutex);
5338         if (!dev_priv->info->cursor_needs_physical) {
5339                 if (obj->tiling_mode) {
5340                         DRM_ERROR("cursor cannot be tiled\n");
5341                         ret = -EINVAL;
5342                         goto fail_locked;
5343                 }
5344
5345                 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
5346                 if (ret) {
5347                         DRM_ERROR("failed to pin cursor bo\n");
5348                         goto fail_locked;
5349                 }
5350
5351                 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
5352                 if (ret) {
5353                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5354                         goto fail_unpin;
5355                 }
5356
5357                 ret = i915_gem_object_put_fence(obj);
5358                 if (ret) {
5359                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5360                         goto fail_unpin;
5361                 }
5362
5363                 addr = obj->gtt_offset;
5364         } else {
5365                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5366                 ret = i915_gem_attach_phys_object(dev, obj,
5367                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5368                                                   align);
5369                 if (ret) {
5370                         DRM_ERROR("failed to attach phys object\n");
5371                         goto fail_locked;
5372                 }
5373                 addr = obj->phys_obj->handle->busaddr;
5374         }
5375
5376         if (IS_GEN2(dev))
5377                 I915_WRITE(CURSIZE, (height << 12) | width);
5378
5379  finish:
5380         if (intel_crtc->cursor_bo) {
5381                 if (dev_priv->info->cursor_needs_physical) {
5382                         if (intel_crtc->cursor_bo != obj)
5383                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5384                 } else
5385                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5386                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5387         }
5388
5389         mutex_unlock(&dev->struct_mutex);
5390
5391         intel_crtc->cursor_addr = addr;
5392         intel_crtc->cursor_bo = obj;
5393         intel_crtc->cursor_width = width;
5394         intel_crtc->cursor_height = height;
5395
5396         intel_crtc_update_cursor(crtc, true);
5397
5398         return 0;
5399 fail_unpin:
5400         i915_gem_object_unpin(obj);
5401 fail_locked:
5402         mutex_unlock(&dev->struct_mutex);
5403 fail:
5404         drm_gem_object_unreference_unlocked(&obj->base);
5405         return ret;
5406 }
5407
5408 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5409 {
5410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5411
5412         intel_crtc->cursor_x = x;
5413         intel_crtc->cursor_y = y;
5414
5415         intel_crtc_update_cursor(crtc, true);
5416
5417         return 0;
5418 }
5419
5420 /** Sets the color ramps on behalf of RandR */
5421 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5422                                  u16 blue, int regno)
5423 {
5424         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5425
5426         intel_crtc->lut_r[regno] = red >> 8;
5427         intel_crtc->lut_g[regno] = green >> 8;
5428         intel_crtc->lut_b[regno] = blue >> 8;
5429 }
5430
5431 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5432                              u16 *blue, int regno)
5433 {
5434         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5435
5436         *red = intel_crtc->lut_r[regno] << 8;
5437         *green = intel_crtc->lut_g[regno] << 8;
5438         *blue = intel_crtc->lut_b[regno] << 8;
5439 }
5440
5441 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5442                                  u16 *blue, uint32_t start, uint32_t size)
5443 {
5444         int end = (start + size > 256) ? 256 : start + size, i;
5445         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5446
5447         for (i = start; i < end; i++) {
5448                 intel_crtc->lut_r[i] = red[i] >> 8;
5449                 intel_crtc->lut_g[i] = green[i] >> 8;
5450                 intel_crtc->lut_b[i] = blue[i] >> 8;
5451         }
5452
5453         intel_crtc_load_lut(crtc);
5454 }
5455
5456 /**
5457  * Get a pipe with a simple mode set on it for doing load-based monitor
5458  * detection.
5459  *
5460  * It will be up to the load-detect code to adjust the pipe as appropriate for
5461  * its requirements.  The pipe will be connected to no other encoders.
5462  *
5463  * Currently this code will only succeed if there is a pipe with no encoders
5464  * configured for it.  In the future, it could choose to temporarily disable
5465  * some outputs to free up a pipe for its use.
5466  *
5467  * \return crtc, or NULL if no pipes are available.
5468  */
5469
5470 /* VESA 640x480x72Hz mode to set on the pipe */
5471 static struct drm_display_mode load_detect_mode = {
5472         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5473                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5474 };
5475
5476 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5477                                             struct drm_connector *connector,
5478                                             struct drm_display_mode *mode,
5479                                             int *dpms_mode)
5480 {
5481         struct intel_crtc *intel_crtc;
5482         struct drm_crtc *possible_crtc;
5483         struct drm_crtc *supported_crtc =NULL;
5484         struct drm_encoder *encoder = &intel_encoder->base;
5485         struct drm_crtc *crtc = NULL;
5486         struct drm_device *dev = encoder->dev;
5487         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5488         struct drm_crtc_helper_funcs *crtc_funcs;
5489         int i = -1;
5490
5491         /*
5492          * Algorithm gets a little messy:
5493          *   - if the connector already has an assigned crtc, use it (but make
5494          *     sure it's on first)
5495          *   - try to find the first unused crtc that can drive this connector,
5496          *     and use that if we find one
5497          *   - if there are no unused crtcs available, try to use the first
5498          *     one we found that supports the connector
5499          */
5500
5501         /* See if we already have a CRTC for this connector */
5502         if (encoder->crtc) {
5503                 crtc = encoder->crtc;
5504                 /* Make sure the crtc and connector are running */
5505                 intel_crtc = to_intel_crtc(crtc);
5506                 *dpms_mode = intel_crtc->dpms_mode;
5507                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5508                         crtc_funcs = crtc->helper_private;
5509                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5510                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5511                 }
5512                 return crtc;
5513         }
5514
5515         /* Find an unused one (if possible) */
5516         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5517                 i++;
5518                 if (!(encoder->possible_crtcs & (1 << i)))
5519                         continue;
5520                 if (!possible_crtc->enabled) {
5521                         crtc = possible_crtc;
5522                         break;
5523                 }
5524                 if (!supported_crtc)
5525                         supported_crtc = possible_crtc;
5526         }
5527
5528         /*
5529          * If we didn't find an unused CRTC, don't use any.
5530          */
5531         if (!crtc) {
5532                 return NULL;
5533         }
5534
5535         encoder->crtc = crtc;
5536         connector->encoder = encoder;
5537         intel_encoder->load_detect_temp = true;
5538
5539         intel_crtc = to_intel_crtc(crtc);
5540         *dpms_mode = intel_crtc->dpms_mode;
5541
5542         if (!crtc->enabled) {
5543                 if (!mode)
5544                         mode = &load_detect_mode;
5545                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
5546         } else {
5547                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5548                         crtc_funcs = crtc->helper_private;
5549                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5550                 }
5551
5552                 /* Add this connector to the crtc */
5553                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
5554                 encoder_funcs->commit(encoder);
5555         }
5556         /* let the connector get through one full cycle before testing */
5557         intel_wait_for_vblank(dev, intel_crtc->pipe);
5558
5559         return crtc;
5560 }
5561
5562 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5563                                     struct drm_connector *connector, int dpms_mode)
5564 {
5565         struct drm_encoder *encoder = &intel_encoder->base;
5566         struct drm_device *dev = encoder->dev;
5567         struct drm_crtc *crtc = encoder->crtc;
5568         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5569         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5570
5571         if (intel_encoder->load_detect_temp) {
5572                 encoder->crtc = NULL;
5573                 connector->encoder = NULL;
5574                 intel_encoder->load_detect_temp = false;
5575                 crtc->enabled = drm_helper_crtc_in_use(crtc);
5576                 drm_helper_disable_unused_functions(dev);
5577         }
5578
5579         /* Switch crtc and encoder back off if necessary */
5580         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
5581                 if (encoder->crtc == crtc)
5582                         encoder_funcs->dpms(encoder, dpms_mode);
5583                 crtc_funcs->dpms(crtc, dpms_mode);
5584         }
5585 }
5586
5587 /* Returns the clock of the currently programmed mode of the given pipe. */
5588 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5589 {
5590         struct drm_i915_private *dev_priv = dev->dev_private;
5591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5592         int pipe = intel_crtc->pipe;
5593         u32 dpll = I915_READ(DPLL(pipe));
5594         u32 fp;
5595         intel_clock_t clock;
5596
5597         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5598                 fp = FP0(pipe);
5599         else
5600                 fp = FP1(pipe);
5601
5602         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5603         if (IS_PINEVIEW(dev)) {
5604                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5605                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5606         } else {
5607                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5608                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5609         }
5610
5611         if (!IS_GEN2(dev)) {
5612                 if (IS_PINEVIEW(dev))
5613                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5614                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5615                 else
5616                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5617                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5618
5619                 switch (dpll & DPLL_MODE_MASK) {
5620                 case DPLLB_MODE_DAC_SERIAL:
5621                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5622                                 5 : 10;
5623                         break;
5624                 case DPLLB_MODE_LVDS:
5625                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5626                                 7 : 14;
5627                         break;
5628                 default:
5629                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5630                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5631                         return 0;
5632                 }
5633
5634                 /* XXX: Handle the 100Mhz refclk */
5635                 intel_clock(dev, 96000, &clock);
5636         } else {
5637                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5638
5639                 if (is_lvds) {
5640                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5641                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5642                         clock.p2 = 14;
5643
5644                         if ((dpll & PLL_REF_INPUT_MASK) ==
5645                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5646                                 /* XXX: might not be 66MHz */
5647                                 intel_clock(dev, 66000, &clock);
5648                         } else
5649                                 intel_clock(dev, 48000, &clock);
5650                 } else {
5651                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5652                                 clock.p1 = 2;
5653                         else {
5654                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5655                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5656                         }
5657                         if (dpll & PLL_P2_DIVIDE_BY_4)
5658                                 clock.p2 = 4;
5659                         else
5660                                 clock.p2 = 2;
5661
5662                         intel_clock(dev, 48000, &clock);
5663                 }
5664         }
5665
5666         /* XXX: It would be nice to validate the clocks, but we can't reuse
5667          * i830PllIsValid() because it relies on the xf86_config connector
5668          * configuration being accurate, which it isn't necessarily.
5669          */
5670
5671         return clock.dot;
5672 }
5673
5674 /** Returns the currently programmed mode of the given pipe. */
5675 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5676                                              struct drm_crtc *crtc)
5677 {
5678         struct drm_i915_private *dev_priv = dev->dev_private;
5679         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5680         int pipe = intel_crtc->pipe;
5681         struct drm_display_mode *mode;
5682         int htot = I915_READ(HTOTAL(pipe));
5683         int hsync = I915_READ(HSYNC(pipe));
5684         int vtot = I915_READ(VTOTAL(pipe));
5685         int vsync = I915_READ(VSYNC(pipe));
5686
5687         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5688         if (!mode)
5689                 return NULL;
5690
5691         mode->clock = intel_crtc_clock_get(dev, crtc);
5692         mode->hdisplay = (htot & 0xffff) + 1;
5693         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5694         mode->hsync_start = (hsync & 0xffff) + 1;
5695         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5696         mode->vdisplay = (vtot & 0xffff) + 1;
5697         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5698         mode->vsync_start = (vsync & 0xffff) + 1;
5699         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5700
5701         drm_mode_set_name(mode);
5702         drm_mode_set_crtcinfo(mode, 0);
5703
5704         return mode;
5705 }
5706
5707 #define GPU_IDLE_TIMEOUT 500 /* ms */
5708
5709 /* When this timer fires, we've been idle for awhile */
5710 static void intel_gpu_idle_timer(unsigned long arg)
5711 {
5712         struct drm_device *dev = (struct drm_device *)arg;
5713         drm_i915_private_t *dev_priv = dev->dev_private;
5714
5715         if (!list_empty(&dev_priv->mm.active_list)) {
5716                 /* Still processing requests, so just re-arm the timer. */
5717                 mod_timer(&dev_priv->idle_timer, jiffies +
5718                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5719                 return;
5720         }
5721
5722         dev_priv->busy = false;
5723         queue_work(dev_priv->wq, &dev_priv->idle_work);
5724 }
5725
5726 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5727
5728 static void intel_crtc_idle_timer(unsigned long arg)
5729 {
5730         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5731         struct drm_crtc *crtc = &intel_crtc->base;
5732         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5733         struct intel_framebuffer *intel_fb;
5734
5735         intel_fb = to_intel_framebuffer(crtc->fb);
5736         if (intel_fb && intel_fb->obj->active) {
5737                 /* The framebuffer is still being accessed by the GPU. */
5738                 mod_timer(&intel_crtc->idle_timer, jiffies +
5739                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5740                 return;
5741         }
5742
5743         intel_crtc->busy = false;
5744         queue_work(dev_priv->wq, &dev_priv->idle_work);
5745 }
5746
5747 static void intel_increase_pllclock(struct drm_crtc *crtc)
5748 {
5749         struct drm_device *dev = crtc->dev;
5750         drm_i915_private_t *dev_priv = dev->dev_private;
5751         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5752         int pipe = intel_crtc->pipe;
5753         int dpll_reg = DPLL(pipe);
5754         int dpll;
5755
5756         if (HAS_PCH_SPLIT(dev))
5757                 return;
5758
5759         if (!dev_priv->lvds_downclock_avail)
5760                 return;
5761
5762         dpll = I915_READ(dpll_reg);
5763         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5764                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5765
5766                 /* Unlock panel regs */
5767                 I915_WRITE(PP_CONTROL,
5768                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
5769
5770                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5771                 I915_WRITE(dpll_reg, dpll);
5772                 POSTING_READ(dpll_reg);
5773                 intel_wait_for_vblank(dev, pipe);
5774
5775                 dpll = I915_READ(dpll_reg);
5776                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5777                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5778
5779                 /* ...and lock them again */
5780                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5781         }
5782
5783         /* Schedule downclock */
5784         mod_timer(&intel_crtc->idle_timer, jiffies +
5785                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5786 }
5787
5788 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5789 {
5790         struct drm_device *dev = crtc->dev;
5791         drm_i915_private_t *dev_priv = dev->dev_private;
5792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5793         int pipe = intel_crtc->pipe;
5794         int dpll_reg = DPLL(pipe);
5795         int dpll = I915_READ(dpll_reg);
5796
5797         if (HAS_PCH_SPLIT(dev))
5798                 return;
5799
5800         if (!dev_priv->lvds_downclock_avail)
5801                 return;
5802
5803         /*
5804          * Since this is called by a timer, we should never get here in
5805          * the manual case.
5806          */
5807         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5808                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5809
5810                 /* Unlock panel regs */
5811                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5812                            PANEL_UNLOCK_REGS);
5813
5814                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5815                 I915_WRITE(dpll_reg, dpll);
5816                 dpll = I915_READ(dpll_reg);
5817                 intel_wait_for_vblank(dev, pipe);
5818                 dpll = I915_READ(dpll_reg);
5819                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5820                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5821
5822                 /* ...and lock them again */
5823                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5824         }
5825
5826 }
5827
5828 /**
5829  * intel_idle_update - adjust clocks for idleness
5830  * @work: work struct
5831  *
5832  * Either the GPU or display (or both) went idle.  Check the busy status
5833  * here and adjust the CRTC and GPU clocks as necessary.
5834  */
5835 static void intel_idle_update(struct work_struct *work)
5836 {
5837         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5838                                                     idle_work);
5839         struct drm_device *dev = dev_priv->dev;
5840         struct drm_crtc *crtc;
5841         struct intel_crtc *intel_crtc;
5842
5843         if (!i915_powersave)
5844                 return;
5845
5846         mutex_lock(&dev->struct_mutex);
5847
5848         i915_update_gfx_val(dev_priv);
5849
5850         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5851                 /* Skip inactive CRTCs */
5852                 if (!crtc->fb)
5853                         continue;
5854
5855                 intel_crtc = to_intel_crtc(crtc);
5856                 if (!intel_crtc->busy)
5857                         intel_decrease_pllclock(crtc);
5858         }
5859
5860
5861         mutex_unlock(&dev->struct_mutex);
5862 }
5863
5864 /**
5865  * intel_mark_busy - mark the GPU and possibly the display busy
5866  * @dev: drm device
5867  * @obj: object we're operating on
5868  *
5869  * Callers can use this function to indicate that the GPU is busy processing
5870  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
5871  * buffer), we'll also mark the display as busy, so we know to increase its
5872  * clock frequency.
5873  */
5874 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5875 {
5876         drm_i915_private_t *dev_priv = dev->dev_private;
5877         struct drm_crtc *crtc = NULL;
5878         struct intel_framebuffer *intel_fb;
5879         struct intel_crtc *intel_crtc;
5880
5881         if (!drm_core_check_feature(dev, DRIVER_MODESET))
5882                 return;
5883
5884         if (!dev_priv->busy)
5885                 dev_priv->busy = true;
5886         else
5887                 mod_timer(&dev_priv->idle_timer, jiffies +
5888                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5889
5890         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5891                 if (!crtc->fb)
5892                         continue;
5893
5894                 intel_crtc = to_intel_crtc(crtc);
5895                 intel_fb = to_intel_framebuffer(crtc->fb);
5896                 if (intel_fb->obj == obj) {
5897                         if (!intel_crtc->busy) {
5898                                 /* Non-busy -> busy, upclock */
5899                                 intel_increase_pllclock(crtc);
5900                                 intel_crtc->busy = true;
5901                         } else {
5902                                 /* Busy -> busy, put off timer */
5903                                 mod_timer(&intel_crtc->idle_timer, jiffies +
5904                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5905                         }
5906                 }
5907         }
5908 }
5909
5910 static void intel_crtc_destroy(struct drm_crtc *crtc)
5911 {
5912         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5913         struct drm_device *dev = crtc->dev;
5914         struct intel_unpin_work *work;
5915         unsigned long flags;
5916
5917         spin_lock_irqsave(&dev->event_lock, flags);
5918         work = intel_crtc->unpin_work;
5919         intel_crtc->unpin_work = NULL;
5920         spin_unlock_irqrestore(&dev->event_lock, flags);
5921
5922         if (work) {
5923                 cancel_work_sync(&work->work);
5924                 kfree(work);
5925         }
5926
5927         drm_crtc_cleanup(crtc);
5928
5929         kfree(intel_crtc);
5930 }
5931
5932 static void intel_unpin_work_fn(struct work_struct *__work)
5933 {
5934         struct intel_unpin_work *work =
5935                 container_of(__work, struct intel_unpin_work, work);
5936
5937         mutex_lock(&work->dev->struct_mutex);
5938         i915_gem_object_unpin(work->old_fb_obj);
5939         drm_gem_object_unreference(&work->pending_flip_obj->base);
5940         drm_gem_object_unreference(&work->old_fb_obj->base);
5941
5942         mutex_unlock(&work->dev->struct_mutex);
5943         kfree(work);
5944 }
5945
5946 static void do_intel_finish_page_flip(struct drm_device *dev,
5947                                       struct drm_crtc *crtc)
5948 {
5949         drm_i915_private_t *dev_priv = dev->dev_private;
5950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5951         struct intel_unpin_work *work;
5952         struct drm_i915_gem_object *obj;
5953         struct drm_pending_vblank_event *e;
5954         struct timeval tnow, tvbl;
5955         unsigned long flags;
5956
5957         /* Ignore early vblank irqs */
5958         if (intel_crtc == NULL)
5959                 return;
5960
5961         do_gettimeofday(&tnow);
5962
5963         spin_lock_irqsave(&dev->event_lock, flags);
5964         work = intel_crtc->unpin_work;
5965         if (work == NULL || !work->pending) {
5966                 spin_unlock_irqrestore(&dev->event_lock, flags);
5967                 return;
5968         }
5969
5970         intel_crtc->unpin_work = NULL;
5971
5972         if (work->event) {
5973                 e = work->event;
5974                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5975
5976                 /* Called before vblank count and timestamps have
5977                  * been updated for the vblank interval of flip
5978                  * completion? Need to increment vblank count and
5979                  * add one videorefresh duration to returned timestamp
5980                  * to account for this. We assume this happened if we
5981                  * get called over 0.9 frame durations after the last
5982                  * timestamped vblank.
5983                  *
5984                  * This calculation can not be used with vrefresh rates
5985                  * below 5Hz (10Hz to be on the safe side) without
5986                  * promoting to 64 integers.
5987                  */
5988                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5989                     9 * crtc->framedur_ns) {
5990                         e->event.sequence++;
5991                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5992                                              crtc->framedur_ns);
5993                 }
5994
5995                 e->event.tv_sec = tvbl.tv_sec;
5996                 e->event.tv_usec = tvbl.tv_usec;
5997
5998                 list_add_tail(&e->base.link,
5999                               &e->base.file_priv->event_list);
6000                 wake_up_interruptible(&e->base.file_priv->event_wait);
6001         }
6002
6003         drm_vblank_put(dev, intel_crtc->pipe);
6004
6005         spin_unlock_irqrestore(&dev->event_lock, flags);
6006
6007         obj = work->old_fb_obj;
6008
6009         atomic_clear_mask(1 << intel_crtc->plane,
6010                           &obj->pending_flip.counter);
6011         if (atomic_read(&obj->pending_flip) == 0)
6012                 wake_up(&dev_priv->pending_flip_queue);
6013
6014         schedule_work(&work->work);
6015
6016         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6017 }
6018
6019 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6020 {
6021         drm_i915_private_t *dev_priv = dev->dev_private;
6022         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6023
6024         do_intel_finish_page_flip(dev, crtc);
6025 }
6026
6027 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6028 {
6029         drm_i915_private_t *dev_priv = dev->dev_private;
6030         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6031
6032         do_intel_finish_page_flip(dev, crtc);
6033 }
6034
6035 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6036 {
6037         drm_i915_private_t *dev_priv = dev->dev_private;
6038         struct intel_crtc *intel_crtc =
6039                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6040         unsigned long flags;
6041
6042         spin_lock_irqsave(&dev->event_lock, flags);
6043         if (intel_crtc->unpin_work) {
6044                 if ((++intel_crtc->unpin_work->pending) > 1)
6045                         DRM_ERROR("Prepared flip multiple times\n");
6046         } else {
6047                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6048         }
6049         spin_unlock_irqrestore(&dev->event_lock, flags);
6050 }
6051
6052 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6053                                 struct drm_framebuffer *fb,
6054                                 struct drm_pending_vblank_event *event)
6055 {
6056         struct drm_device *dev = crtc->dev;
6057         struct drm_i915_private *dev_priv = dev->dev_private;
6058         struct intel_framebuffer *intel_fb;
6059         struct drm_i915_gem_object *obj;
6060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6061         struct intel_unpin_work *work;
6062         unsigned long flags, offset;
6063         int pipe = intel_crtc->pipe;
6064         u32 pf, pipesrc;
6065         int ret;
6066
6067         work = kzalloc(sizeof *work, GFP_KERNEL);
6068         if (work == NULL)
6069                 return -ENOMEM;
6070
6071         work->event = event;
6072         work->dev = crtc->dev;
6073         intel_fb = to_intel_framebuffer(crtc->fb);
6074         work->old_fb_obj = intel_fb->obj;
6075         INIT_WORK(&work->work, intel_unpin_work_fn);
6076
6077         /* We borrow the event spin lock for protecting unpin_work */
6078         spin_lock_irqsave(&dev->event_lock, flags);
6079         if (intel_crtc->unpin_work) {
6080                 spin_unlock_irqrestore(&dev->event_lock, flags);
6081                 kfree(work);
6082
6083                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6084                 return -EBUSY;
6085         }
6086         intel_crtc->unpin_work = work;
6087         spin_unlock_irqrestore(&dev->event_lock, flags);
6088
6089         intel_fb = to_intel_framebuffer(fb);
6090         obj = intel_fb->obj;
6091
6092         mutex_lock(&dev->struct_mutex);
6093         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6094         if (ret)
6095                 goto cleanup_work;
6096
6097         /* Reference the objects for the scheduled work. */
6098         drm_gem_object_reference(&work->old_fb_obj->base);
6099         drm_gem_object_reference(&obj->base);
6100
6101         crtc->fb = fb;
6102
6103         ret = drm_vblank_get(dev, intel_crtc->pipe);
6104         if (ret)
6105                 goto cleanup_objs;
6106
6107         if (IS_GEN3(dev) || IS_GEN2(dev)) {
6108                 u32 flip_mask;
6109
6110                 /* Can't queue multiple flips, so wait for the previous
6111                  * one to finish before executing the next.
6112                  */
6113                 ret = BEGIN_LP_RING(2);
6114                 if (ret)
6115                         goto cleanup_objs;
6116
6117                 if (intel_crtc->plane)
6118                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6119                 else
6120                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6121                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6122                 OUT_RING(MI_NOOP);
6123                 ADVANCE_LP_RING();
6124         }
6125
6126         work->pending_flip_obj = obj;
6127
6128         work->enable_stall_check = true;
6129
6130         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6131         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6132
6133         ret = BEGIN_LP_RING(4);
6134         if (ret)
6135                 goto cleanup_objs;
6136
6137         /* Block clients from rendering to the new back buffer until
6138          * the flip occurs and the object is no longer visible.
6139          */
6140         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6141
6142         switch (INTEL_INFO(dev)->gen) {
6143         case 2:
6144                 OUT_RING(MI_DISPLAY_FLIP |
6145                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6146                 OUT_RING(fb->pitch);
6147                 OUT_RING(obj->gtt_offset + offset);
6148                 OUT_RING(MI_NOOP);
6149                 break;
6150
6151         case 3:
6152                 OUT_RING(MI_DISPLAY_FLIP_I915 |
6153                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6154                 OUT_RING(fb->pitch);
6155                 OUT_RING(obj->gtt_offset + offset);
6156                 OUT_RING(MI_NOOP);
6157                 break;
6158
6159         case 4:
6160         case 5:
6161                 /* i965+ uses the linear or tiled offsets from the
6162                  * Display Registers (which do not change across a page-flip)
6163                  * so we need only reprogram the base address.
6164                  */
6165                 OUT_RING(MI_DISPLAY_FLIP |
6166                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6167                 OUT_RING(fb->pitch);
6168                 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6169
6170                 /* XXX Enabling the panel-fitter across page-flip is so far
6171                  * untested on non-native modes, so ignore it for now.
6172                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6173                  */
6174                 pf = 0;
6175                 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6176                 OUT_RING(pf | pipesrc);
6177                 break;
6178
6179         case 6:
6180                 OUT_RING(MI_DISPLAY_FLIP |
6181                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6182                 OUT_RING(fb->pitch | obj->tiling_mode);
6183                 OUT_RING(obj->gtt_offset);
6184
6185                 pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
6186                 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6187                 OUT_RING(pf | pipesrc);
6188                 break;
6189         }
6190         ADVANCE_LP_RING();
6191
6192         mutex_unlock(&dev->struct_mutex);
6193
6194         trace_i915_flip_request(intel_crtc->plane, obj);
6195
6196         return 0;
6197
6198 cleanup_objs:
6199         drm_gem_object_unreference(&work->old_fb_obj->base);
6200         drm_gem_object_unreference(&obj->base);
6201 cleanup_work:
6202         mutex_unlock(&dev->struct_mutex);
6203
6204         spin_lock_irqsave(&dev->event_lock, flags);
6205         intel_crtc->unpin_work = NULL;
6206         spin_unlock_irqrestore(&dev->event_lock, flags);
6207
6208         kfree(work);
6209
6210         return ret;
6211 }
6212
6213 static void intel_crtc_reset(struct drm_crtc *crtc)
6214 {
6215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6216
6217         /* Reset flags back to the 'unknown' status so that they
6218          * will be correctly set on the initial modeset.
6219          */
6220         intel_crtc->dpms_mode = -1;
6221 }
6222
6223 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6224         .dpms = intel_crtc_dpms,
6225         .mode_fixup = intel_crtc_mode_fixup,
6226         .mode_set = intel_crtc_mode_set,
6227         .mode_set_base = intel_pipe_set_base,
6228         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6229         .load_lut = intel_crtc_load_lut,
6230         .disable = intel_crtc_disable,
6231 };
6232
6233 static const struct drm_crtc_funcs intel_crtc_funcs = {
6234         .reset = intel_crtc_reset,
6235         .cursor_set = intel_crtc_cursor_set,
6236         .cursor_move = intel_crtc_cursor_move,
6237         .gamma_set = intel_crtc_gamma_set,
6238         .set_config = drm_crtc_helper_set_config,
6239         .destroy = intel_crtc_destroy,
6240         .page_flip = intel_crtc_page_flip,
6241 };
6242
6243 static void intel_sanitize_modesetting(struct drm_device *dev,
6244                                        int pipe, int plane)
6245 {
6246         struct drm_i915_private *dev_priv = dev->dev_private;
6247         u32 reg, val;
6248
6249         if (HAS_PCH_SPLIT(dev))
6250                 return;
6251
6252         /* Who knows what state these registers were left in by the BIOS or
6253          * grub?
6254          *
6255          * If we leave the registers in a conflicting state (e.g. with the
6256          * display plane reading from the other pipe than the one we intend
6257          * to use) then when we attempt to teardown the active mode, we will
6258          * not disable the pipes and planes in the correct order -- leaving
6259          * a plane reading from a disabled pipe and possibly leading to
6260          * undefined behaviour.
6261          */
6262
6263         reg = DSPCNTR(plane);
6264         val = I915_READ(reg);
6265
6266         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6267                 return;
6268         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6269                 return;
6270
6271         /* This display plane is active and attached to the other CPU pipe. */
6272         pipe = !pipe;
6273
6274         /* Disable the plane and wait for it to stop reading from the pipe. */
6275         intel_disable_plane(dev_priv, plane, pipe);
6276         intel_disable_pipe(dev_priv, pipe);
6277 }
6278
6279 static void intel_crtc_init(struct drm_device *dev, int pipe)
6280 {
6281         drm_i915_private_t *dev_priv = dev->dev_private;
6282         struct intel_crtc *intel_crtc;
6283         int i;
6284
6285         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6286         if (intel_crtc == NULL)
6287                 return;
6288
6289         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6290
6291         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6292         for (i = 0; i < 256; i++) {
6293                 intel_crtc->lut_r[i] = i;
6294                 intel_crtc->lut_g[i] = i;
6295                 intel_crtc->lut_b[i] = i;
6296         }
6297
6298         /* Swap pipes & planes for FBC on pre-965 */
6299         intel_crtc->pipe = pipe;
6300         intel_crtc->plane = pipe;
6301         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6302                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6303                 intel_crtc->plane = !pipe;
6304         }
6305
6306         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6307                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6308         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6309         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6310
6311         intel_crtc_reset(&intel_crtc->base);
6312         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6313
6314         if (HAS_PCH_SPLIT(dev)) {
6315                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6316                 intel_helper_funcs.commit = ironlake_crtc_commit;
6317         } else {
6318                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6319                 intel_helper_funcs.commit = i9xx_crtc_commit;
6320         }
6321
6322         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6323
6324         intel_crtc->busy = false;
6325
6326         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6327                     (unsigned long)intel_crtc);
6328
6329         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6330 }
6331
6332 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6333                                 struct drm_file *file)
6334 {
6335         drm_i915_private_t *dev_priv = dev->dev_private;
6336         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6337         struct drm_mode_object *drmmode_obj;
6338         struct intel_crtc *crtc;
6339
6340         if (!dev_priv) {
6341                 DRM_ERROR("called with no initialization\n");
6342                 return -EINVAL;
6343         }
6344
6345         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6346                         DRM_MODE_OBJECT_CRTC);
6347
6348         if (!drmmode_obj) {
6349                 DRM_ERROR("no such CRTC id\n");
6350                 return -EINVAL;
6351         }
6352
6353         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6354         pipe_from_crtc_id->pipe = crtc->pipe;
6355
6356         return 0;
6357 }
6358
6359 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6360 {
6361         struct intel_encoder *encoder;
6362         int index_mask = 0;
6363         int entry = 0;
6364
6365         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6366                 if (type_mask & encoder->clone_mask)
6367                         index_mask |= (1 << entry);
6368                 entry++;
6369         }
6370
6371         return index_mask;
6372 }
6373
6374 static bool has_edp_a(struct drm_device *dev)
6375 {
6376         struct drm_i915_private *dev_priv = dev->dev_private;
6377
6378         if (!IS_MOBILE(dev))
6379                 return false;
6380
6381         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6382                 return false;
6383
6384         if (IS_GEN5(dev) &&
6385             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6386                 return false;
6387
6388         return true;
6389 }
6390
6391 static void intel_setup_outputs(struct drm_device *dev)
6392 {
6393         struct drm_i915_private *dev_priv = dev->dev_private;
6394         struct intel_encoder *encoder;
6395         bool dpd_is_edp = false;
6396         bool has_lvds = false;
6397
6398         if (IS_MOBILE(dev) && !IS_I830(dev))
6399                 has_lvds = intel_lvds_init(dev);
6400         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6401                 /* disable the panel fitter on everything but LVDS */
6402                 I915_WRITE(PFIT_CONTROL, 0);
6403         }
6404
6405         if (HAS_PCH_SPLIT(dev)) {
6406                 dpd_is_edp = intel_dpd_is_edp(dev);
6407
6408                 if (has_edp_a(dev))
6409                         intel_dp_init(dev, DP_A);
6410
6411                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6412                         intel_dp_init(dev, PCH_DP_D);
6413         }
6414
6415         intel_crt_init(dev);
6416
6417         if (HAS_PCH_SPLIT(dev)) {
6418                 int found;
6419
6420                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6421                         /* PCH SDVOB multiplex with HDMIB */
6422                         found = intel_sdvo_init(dev, PCH_SDVOB);
6423                         if (!found)
6424                                 intel_hdmi_init(dev, HDMIB);
6425                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6426                                 intel_dp_init(dev, PCH_DP_B);
6427                 }
6428
6429                 if (I915_READ(HDMIC) & PORT_DETECTED)
6430                         intel_hdmi_init(dev, HDMIC);
6431
6432                 if (I915_READ(HDMID) & PORT_DETECTED)
6433                         intel_hdmi_init(dev, HDMID);
6434
6435                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6436                         intel_dp_init(dev, PCH_DP_C);
6437
6438                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6439                         intel_dp_init(dev, PCH_DP_D);
6440
6441         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6442                 bool found = false;
6443
6444                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6445                         DRM_DEBUG_KMS("probing SDVOB\n");
6446                         found = intel_sdvo_init(dev, SDVOB);
6447                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6448                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6449                                 intel_hdmi_init(dev, SDVOB);
6450                         }
6451
6452                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6453                                 DRM_DEBUG_KMS("probing DP_B\n");
6454                                 intel_dp_init(dev, DP_B);
6455                         }
6456                 }
6457
6458                 /* Before G4X SDVOC doesn't have its own detect register */
6459
6460                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6461                         DRM_DEBUG_KMS("probing SDVOC\n");
6462                         found = intel_sdvo_init(dev, SDVOC);
6463                 }
6464
6465                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6466
6467                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6468                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6469                                 intel_hdmi_init(dev, SDVOC);
6470                         }
6471                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6472                                 DRM_DEBUG_KMS("probing DP_C\n");
6473                                 intel_dp_init(dev, DP_C);
6474                         }
6475                 }
6476
6477                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6478                     (I915_READ(DP_D) & DP_DETECTED)) {
6479                         DRM_DEBUG_KMS("probing DP_D\n");
6480                         intel_dp_init(dev, DP_D);
6481                 }
6482         } else if (IS_GEN2(dev))
6483                 intel_dvo_init(dev);
6484
6485         if (SUPPORTS_TV(dev))
6486                 intel_tv_init(dev);
6487
6488         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6489                 encoder->base.possible_crtcs = encoder->crtc_mask;
6490                 encoder->base.possible_clones =
6491                         intel_encoder_clones(dev, encoder->clone_mask);
6492         }
6493
6494         intel_panel_setup_backlight(dev);
6495 }
6496
6497 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6498 {
6499         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6500
6501         drm_framebuffer_cleanup(fb);
6502         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6503
6504         kfree(intel_fb);
6505 }
6506
6507 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6508                                                 struct drm_file *file,
6509                                                 unsigned int *handle)
6510 {
6511         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6512         struct drm_i915_gem_object *obj = intel_fb->obj;
6513
6514         return drm_gem_handle_create(file, &obj->base, handle);
6515 }
6516
6517 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6518         .destroy = intel_user_framebuffer_destroy,
6519         .create_handle = intel_user_framebuffer_create_handle,
6520 };
6521
6522 int intel_framebuffer_init(struct drm_device *dev,
6523                            struct intel_framebuffer *intel_fb,
6524                            struct drm_mode_fb_cmd *mode_cmd,
6525                            struct drm_i915_gem_object *obj)
6526 {
6527         int ret;
6528
6529         if (obj->tiling_mode == I915_TILING_Y)
6530                 return -EINVAL;
6531
6532         if (mode_cmd->pitch & 63)
6533                 return -EINVAL;
6534
6535         switch (mode_cmd->bpp) {
6536         case 8:
6537         case 16:
6538         case 24:
6539         case 32:
6540                 break;
6541         default:
6542                 return -EINVAL;
6543         }
6544
6545         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6546         if (ret) {
6547                 DRM_ERROR("framebuffer init failed %d\n", ret);
6548                 return ret;
6549         }
6550
6551         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6552         intel_fb->obj = obj;
6553         return 0;
6554 }
6555
6556 static struct drm_framebuffer *
6557 intel_user_framebuffer_create(struct drm_device *dev,
6558                               struct drm_file *filp,
6559                               struct drm_mode_fb_cmd *mode_cmd)
6560 {
6561         struct drm_i915_gem_object *obj;
6562         struct intel_framebuffer *intel_fb;
6563         int ret;
6564
6565         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6566         if (&obj->base == NULL)
6567                 return ERR_PTR(-ENOENT);
6568
6569         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6570         if (!intel_fb)
6571                 return ERR_PTR(-ENOMEM);
6572
6573         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6574         if (ret) {
6575                 drm_gem_object_unreference_unlocked(&obj->base);
6576                 kfree(intel_fb);
6577                 return ERR_PTR(ret);
6578         }
6579
6580         return &intel_fb->base;
6581 }
6582
6583 static const struct drm_mode_config_funcs intel_mode_funcs = {
6584         .fb_create = intel_user_framebuffer_create,
6585         .output_poll_changed = intel_fb_output_poll_changed,
6586 };
6587
6588 static struct drm_i915_gem_object *
6589 intel_alloc_context_page(struct drm_device *dev)
6590 {
6591         struct drm_i915_gem_object *ctx;
6592         int ret;
6593
6594         ctx = i915_gem_alloc_object(dev, 4096);
6595         if (!ctx) {
6596                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6597                 return NULL;
6598         }
6599
6600         mutex_lock(&dev->struct_mutex);
6601         ret = i915_gem_object_pin(ctx, 4096, true);
6602         if (ret) {
6603                 DRM_ERROR("failed to pin power context: %d\n", ret);
6604                 goto err_unref;
6605         }
6606
6607         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6608         if (ret) {
6609                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6610                 goto err_unpin;
6611         }
6612         mutex_unlock(&dev->struct_mutex);
6613
6614         return ctx;
6615
6616 err_unpin:
6617         i915_gem_object_unpin(ctx);
6618 err_unref:
6619         drm_gem_object_unreference(&ctx->base);
6620         mutex_unlock(&dev->struct_mutex);
6621         return NULL;
6622 }
6623
6624 bool ironlake_set_drps(struct drm_device *dev, u8 val)
6625 {
6626         struct drm_i915_private *dev_priv = dev->dev_private;
6627         u16 rgvswctl;
6628
6629         rgvswctl = I915_READ16(MEMSWCTL);
6630         if (rgvswctl & MEMCTL_CMD_STS) {
6631                 DRM_DEBUG("gpu busy, RCS change rejected\n");
6632                 return false; /* still busy with another command */
6633         }
6634
6635         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6636                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6637         I915_WRITE16(MEMSWCTL, rgvswctl);
6638         POSTING_READ16(MEMSWCTL);
6639
6640         rgvswctl |= MEMCTL_CMD_STS;
6641         I915_WRITE16(MEMSWCTL, rgvswctl);
6642
6643         return true;
6644 }
6645
6646 void ironlake_enable_drps(struct drm_device *dev)
6647 {
6648         struct drm_i915_private *dev_priv = dev->dev_private;
6649         u32 rgvmodectl = I915_READ(MEMMODECTL);
6650         u8 fmax, fmin, fstart, vstart;
6651
6652         /* Enable temp reporting */
6653         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6654         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6655
6656         /* 100ms RC evaluation intervals */
6657         I915_WRITE(RCUPEI, 100000);
6658         I915_WRITE(RCDNEI, 100000);
6659
6660         /* Set max/min thresholds to 90ms and 80ms respectively */
6661         I915_WRITE(RCBMAXAVG, 90000);
6662         I915_WRITE(RCBMINAVG, 80000);
6663
6664         I915_WRITE(MEMIHYST, 1);
6665
6666         /* Set up min, max, and cur for interrupt handling */
6667         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6668         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6669         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6670                 MEMMODE_FSTART_SHIFT;
6671
6672         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6673                 PXVFREQ_PX_SHIFT;
6674
6675         dev_priv->fmax = fmax; /* IPS callback will increase this */
6676         dev_priv->fstart = fstart;
6677
6678         dev_priv->max_delay = fstart;
6679         dev_priv->min_delay = fmin;
6680         dev_priv->cur_delay = fstart;
6681
6682         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6683                          fmax, fmin, fstart);
6684
6685         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6686
6687         /*
6688          * Interrupts will be enabled in ironlake_irq_postinstall
6689          */
6690
6691         I915_WRITE(VIDSTART, vstart);
6692         POSTING_READ(VIDSTART);
6693
6694         rgvmodectl |= MEMMODE_SWMODE_EN;
6695         I915_WRITE(MEMMODECTL, rgvmodectl);
6696
6697         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6698                 DRM_ERROR("stuck trying to change perf mode\n");
6699         msleep(1);
6700
6701         ironlake_set_drps(dev, fstart);
6702
6703         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6704                 I915_READ(0x112e0);
6705         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6706         dev_priv->last_count2 = I915_READ(0x112f4);
6707         getrawmonotonic(&dev_priv->last_time2);
6708 }
6709
6710 void ironlake_disable_drps(struct drm_device *dev)
6711 {
6712         struct drm_i915_private *dev_priv = dev->dev_private;
6713         u16 rgvswctl = I915_READ16(MEMSWCTL);
6714
6715         /* Ack interrupts, disable EFC interrupt */
6716         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6717         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6718         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6719         I915_WRITE(DEIIR, DE_PCU_EVENT);
6720         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6721
6722         /* Go back to the starting frequency */
6723         ironlake_set_drps(dev, dev_priv->fstart);
6724         msleep(1);
6725         rgvswctl |= MEMCTL_CMD_STS;
6726         I915_WRITE(MEMSWCTL, rgvswctl);
6727         msleep(1);
6728
6729 }
6730
6731 void gen6_set_rps(struct drm_device *dev, u8 val)
6732 {
6733         struct drm_i915_private *dev_priv = dev->dev_private;
6734         u32 swreq;
6735
6736         swreq = (val & 0x3ff) << 25;
6737         I915_WRITE(GEN6_RPNSWREQ, swreq);
6738 }
6739
6740 void gen6_disable_rps(struct drm_device *dev)
6741 {
6742         struct drm_i915_private *dev_priv = dev->dev_private;
6743
6744         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6745         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6746         I915_WRITE(GEN6_PMIER, 0);
6747         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6748 }
6749
6750 static unsigned long intel_pxfreq(u32 vidfreq)
6751 {
6752         unsigned long freq;
6753         int div = (vidfreq & 0x3f0000) >> 16;
6754         int post = (vidfreq & 0x3000) >> 12;
6755         int pre = (vidfreq & 0x7);
6756
6757         if (!pre)
6758                 return 0;
6759
6760         freq = ((div * 133333) / ((1<<post) * pre));
6761
6762         return freq;
6763 }
6764
6765 void intel_init_emon(struct drm_device *dev)
6766 {
6767         struct drm_i915_private *dev_priv = dev->dev_private;
6768         u32 lcfuse;
6769         u8 pxw[16];
6770         int i;
6771
6772         /* Disable to program */
6773         I915_WRITE(ECR, 0);
6774         POSTING_READ(ECR);
6775
6776         /* Program energy weights for various events */
6777         I915_WRITE(SDEW, 0x15040d00);
6778         I915_WRITE(CSIEW0, 0x007f0000);
6779         I915_WRITE(CSIEW1, 0x1e220004);
6780         I915_WRITE(CSIEW2, 0x04000004);
6781
6782         for (i = 0; i < 5; i++)
6783                 I915_WRITE(PEW + (i * 4), 0);
6784         for (i = 0; i < 3; i++)
6785                 I915_WRITE(DEW + (i * 4), 0);
6786
6787         /* Program P-state weights to account for frequency power adjustment */
6788         for (i = 0; i < 16; i++) {
6789                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6790                 unsigned long freq = intel_pxfreq(pxvidfreq);
6791                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6792                         PXVFREQ_PX_SHIFT;
6793                 unsigned long val;
6794
6795                 val = vid * vid;
6796                 val *= (freq / 1000);
6797                 val *= 255;
6798                 val /= (127*127*900);
6799                 if (val > 0xff)
6800                         DRM_ERROR("bad pxval: %ld\n", val);
6801                 pxw[i] = val;
6802         }
6803         /* Render standby states get 0 weight */
6804         pxw[14] = 0;
6805         pxw[15] = 0;
6806
6807         for (i = 0; i < 4; i++) {
6808                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6809                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6810                 I915_WRITE(PXW + (i * 4), val);
6811         }
6812
6813         /* Adjust magic regs to magic values (more experimental results) */
6814         I915_WRITE(OGW0, 0);
6815         I915_WRITE(OGW1, 0);
6816         I915_WRITE(EG0, 0x00007f00);
6817         I915_WRITE(EG1, 0x0000000e);
6818         I915_WRITE(EG2, 0x000e0000);
6819         I915_WRITE(EG3, 0x68000300);
6820         I915_WRITE(EG4, 0x42000000);
6821         I915_WRITE(EG5, 0x00140031);
6822         I915_WRITE(EG6, 0);
6823         I915_WRITE(EG7, 0);
6824
6825         for (i = 0; i < 8; i++)
6826                 I915_WRITE(PXWL + (i * 4), 0);
6827
6828         /* Enable PMON + select events */
6829         I915_WRITE(ECR, 0x80000019);
6830
6831         lcfuse = I915_READ(LCFUSE02);
6832
6833         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6834 }
6835
6836 void gen6_enable_rps(struct drm_i915_private *dev_priv)
6837 {
6838         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6839         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6840         u32 pcu_mbox;
6841         int cur_freq, min_freq, max_freq;
6842         int i;
6843
6844         /* Here begins a magic sequence of register writes to enable
6845          * auto-downclocking.
6846          *
6847          * Perhaps there might be some value in exposing these to
6848          * userspace...
6849          */
6850         I915_WRITE(GEN6_RC_STATE, 0);
6851         __gen6_force_wake_get(dev_priv);
6852
6853         /* disable the counters and set deterministic thresholds */
6854         I915_WRITE(GEN6_RC_CONTROL, 0);
6855
6856         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6857         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6858         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6859         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6860         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6861
6862         for (i = 0; i < I915_NUM_RINGS; i++)
6863                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6864
6865         I915_WRITE(GEN6_RC_SLEEP, 0);
6866         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6867         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6868         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6869         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6870
6871         I915_WRITE(GEN6_RC_CONTROL,
6872                    GEN6_RC_CTL_RC6p_ENABLE |
6873                    GEN6_RC_CTL_RC6_ENABLE |
6874                    GEN6_RC_CTL_EI_MODE(1) |
6875                    GEN6_RC_CTL_HW_ENABLE);
6876
6877         I915_WRITE(GEN6_RPNSWREQ,
6878                    GEN6_FREQUENCY(10) |
6879                    GEN6_OFFSET(0) |
6880                    GEN6_AGGRESSIVE_TURBO);
6881         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6882                    GEN6_FREQUENCY(12));
6883
6884         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6885         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6886                    18 << 24 |
6887                    6 << 16);
6888         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
6889         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
6890         I915_WRITE(GEN6_RP_UP_EI, 100000);
6891         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
6892         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6893         I915_WRITE(GEN6_RP_CONTROL,
6894                    GEN6_RP_MEDIA_TURBO |
6895                    GEN6_RP_USE_NORMAL_FREQ |
6896                    GEN6_RP_MEDIA_IS_GFX |
6897                    GEN6_RP_ENABLE |
6898                    GEN6_RP_UP_BUSY_AVG |
6899                    GEN6_RP_DOWN_IDLE_CONT);
6900
6901         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6902                      500))
6903                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6904
6905         I915_WRITE(GEN6_PCODE_DATA, 0);
6906         I915_WRITE(GEN6_PCODE_MAILBOX,
6907                    GEN6_PCODE_READY |
6908                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6909         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6910                      500))
6911                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6912
6913         min_freq = (rp_state_cap & 0xff0000) >> 16;
6914         max_freq = rp_state_cap & 0xff;
6915         cur_freq = (gt_perf_status & 0xff00) >> 8;
6916
6917         /* Check for overclock support */
6918         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6919                      500))
6920                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6921         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6922         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6923         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6924                      500))
6925                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6926         if (pcu_mbox & (1<<31)) { /* OC supported */
6927                 max_freq = pcu_mbox & 0xff;
6928                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
6929         }
6930
6931         /* In units of 100MHz */
6932         dev_priv->max_delay = max_freq;
6933         dev_priv->min_delay = min_freq;
6934         dev_priv->cur_delay = cur_freq;
6935
6936         /* requires MSI enabled */
6937         I915_WRITE(GEN6_PMIER,
6938                    GEN6_PM_MBOX_EVENT |
6939                    GEN6_PM_THERMAL_EVENT |
6940                    GEN6_PM_RP_DOWN_TIMEOUT |
6941                    GEN6_PM_RP_UP_THRESHOLD |
6942                    GEN6_PM_RP_DOWN_THRESHOLD |
6943                    GEN6_PM_RP_UP_EI_EXPIRED |
6944                    GEN6_PM_RP_DOWN_EI_EXPIRED);
6945         I915_WRITE(GEN6_PMIMR, 0);
6946         /* enable all PM interrupts */
6947         I915_WRITE(GEN6_PMINTRMSK, 0);
6948
6949         __gen6_force_wake_put(dev_priv);
6950 }
6951
6952 void intel_enable_clock_gating(struct drm_device *dev)
6953 {
6954         struct drm_i915_private *dev_priv = dev->dev_private;
6955         int pipe;
6956
6957         /*
6958          * Disable clock gating reported to work incorrectly according to the
6959          * specs, but enable as much else as we can.
6960          */
6961         if (HAS_PCH_SPLIT(dev)) {
6962                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6963
6964                 if (IS_GEN5(dev)) {
6965                         /* Required for FBC */
6966                         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
6967                                 DPFCRUNIT_CLOCK_GATE_DISABLE |
6968                                 DPFDUNIT_CLOCK_GATE_DISABLE;
6969                         /* Required for CxSR */
6970                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6971
6972                         I915_WRITE(PCH_3DCGDIS0,
6973                                    MARIUNIT_CLOCK_GATE_DISABLE |
6974                                    SVSMUNIT_CLOCK_GATE_DISABLE);
6975                         I915_WRITE(PCH_3DCGDIS1,
6976                                    VFMUNIT_CLOCK_GATE_DISABLE);
6977                 }
6978
6979                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6980
6981                 /*
6982                  * On Ibex Peak and Cougar Point, we need to disable clock
6983                  * gating for the panel power sequencer or it will fail to
6984                  * start up when no ports are active.
6985                  */
6986                 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6987
6988                 /*
6989                  * According to the spec the following bits should be set in
6990                  * order to enable memory self-refresh
6991                  * The bit 22/21 of 0x42004
6992                  * The bit 5 of 0x42020
6993                  * The bit 15 of 0x45000
6994                  */
6995                 if (IS_GEN5(dev)) {
6996                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6997                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
6998                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6999                         I915_WRITE(ILK_DSPCLK_GATE,
7000                                         (I915_READ(ILK_DSPCLK_GATE) |
7001                                                 ILK_DPARB_CLK_GATE));
7002                         I915_WRITE(DISP_ARB_CTL,
7003                                         (I915_READ(DISP_ARB_CTL) |
7004                                                 DISP_FBC_WM_DIS));
7005                         I915_WRITE(WM3_LP_ILK, 0);
7006                         I915_WRITE(WM2_LP_ILK, 0);
7007                         I915_WRITE(WM1_LP_ILK, 0);
7008                 }
7009                 /*
7010                  * Based on the document from hardware guys the following bits
7011                  * should be set unconditionally in order to enable FBC.
7012                  * The bit 22 of 0x42000
7013                  * The bit 22 of 0x42004
7014                  * The bit 7,8,9 of 0x42020.
7015                  */
7016                 if (IS_IRONLAKE_M(dev)) {
7017                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7018                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7019                                    ILK_FBCQ_DIS);
7020                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7021                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7022                                    ILK_DPARB_GATE);
7023                         I915_WRITE(ILK_DSPCLK_GATE,
7024                                    I915_READ(ILK_DSPCLK_GATE) |
7025                                    ILK_DPFC_DIS1 |
7026                                    ILK_DPFC_DIS2 |
7027                                    ILK_CLK_FBC);
7028                 }
7029
7030                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7031                            I915_READ(ILK_DISPLAY_CHICKEN2) |
7032                            ILK_ELPIN_409_SELECT);
7033
7034                 if (IS_GEN5(dev)) {
7035                         I915_WRITE(_3D_CHICKEN2,
7036                                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7037                                    _3D_CHICKEN2_WM_READ_PIPELINED);
7038                 }
7039
7040                 if (IS_GEN6(dev)) {
7041                         I915_WRITE(WM3_LP_ILK, 0);
7042                         I915_WRITE(WM2_LP_ILK, 0);
7043                         I915_WRITE(WM1_LP_ILK, 0);
7044
7045                         /*
7046                          * According to the spec the following bits should be
7047                          * set in order to enable memory self-refresh and fbc:
7048                          * The bit21 and bit22 of 0x42000
7049                          * The bit21 and bit22 of 0x42004
7050                          * The bit5 and bit7 of 0x42020
7051                          * The bit14 of 0x70180
7052                          * The bit14 of 0x71180
7053                          */
7054                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7055                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7056                                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7057                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7058                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7059                                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7060                         I915_WRITE(ILK_DSPCLK_GATE,
7061                                    I915_READ(ILK_DSPCLK_GATE) |
7062                                    ILK_DPARB_CLK_GATE  |
7063                                    ILK_DPFD_CLK_GATE);
7064
7065                         for_each_pipe(pipe)
7066                                 I915_WRITE(DSPCNTR(pipe),
7067                                            I915_READ(DSPCNTR(pipe)) |
7068                                            DISPPLANE_TRICKLE_FEED_DISABLE);
7069                 }
7070         } else if (IS_G4X(dev)) {
7071                 uint32_t dspclk_gate;
7072                 I915_WRITE(RENCLK_GATE_D1, 0);
7073                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7074                        GS_UNIT_CLOCK_GATE_DISABLE |
7075                        CL_UNIT_CLOCK_GATE_DISABLE);
7076                 I915_WRITE(RAMCLK_GATE_D, 0);
7077                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7078                         OVRUNIT_CLOCK_GATE_DISABLE |
7079                         OVCUNIT_CLOCK_GATE_DISABLE;
7080                 if (IS_GM45(dev))
7081                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7082                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7083         } else if (IS_CRESTLINE(dev)) {
7084                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7085                 I915_WRITE(RENCLK_GATE_D2, 0);
7086                 I915_WRITE(DSPCLK_GATE_D, 0);
7087                 I915_WRITE(RAMCLK_GATE_D, 0);
7088                 I915_WRITE16(DEUC, 0);
7089         } else if (IS_BROADWATER(dev)) {
7090                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7091                        I965_RCC_CLOCK_GATE_DISABLE |
7092                        I965_RCPB_CLOCK_GATE_DISABLE |
7093                        I965_ISC_CLOCK_GATE_DISABLE |
7094                        I965_FBC_CLOCK_GATE_DISABLE);
7095                 I915_WRITE(RENCLK_GATE_D2, 0);
7096         } else if (IS_GEN3(dev)) {
7097                 u32 dstate = I915_READ(D_STATE);
7098
7099                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7100                         DSTATE_DOT_CLOCK_GATING;
7101                 I915_WRITE(D_STATE, dstate);
7102         } else if (IS_I85X(dev) || IS_I865G(dev)) {
7103                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7104         } else if (IS_I830(dev)) {
7105                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7106         }
7107 }
7108
7109 static void ironlake_teardown_rc6(struct drm_device *dev)
7110 {
7111         struct drm_i915_private *dev_priv = dev->dev_private;
7112
7113         if (dev_priv->renderctx) {
7114                 i915_gem_object_unpin(dev_priv->renderctx);
7115                 drm_gem_object_unreference(&dev_priv->renderctx->base);
7116                 dev_priv->renderctx = NULL;
7117         }
7118
7119         if (dev_priv->pwrctx) {
7120                 i915_gem_object_unpin(dev_priv->pwrctx);
7121                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7122                 dev_priv->pwrctx = NULL;
7123         }
7124 }
7125
7126 static void ironlake_disable_rc6(struct drm_device *dev)
7127 {
7128         struct drm_i915_private *dev_priv = dev->dev_private;
7129
7130         if (I915_READ(PWRCTXA)) {
7131                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7132                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7133                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7134                          50);
7135
7136                 I915_WRITE(PWRCTXA, 0);
7137                 POSTING_READ(PWRCTXA);
7138
7139                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7140                 POSTING_READ(RSTDBYCTL);
7141         }
7142
7143         ironlake_disable_rc6(dev);
7144 }
7145
7146 static int ironlake_setup_rc6(struct drm_device *dev)
7147 {
7148         struct drm_i915_private *dev_priv = dev->dev_private;
7149
7150         if (dev_priv->renderctx == NULL)
7151                 dev_priv->renderctx = intel_alloc_context_page(dev);
7152         if (!dev_priv->renderctx)
7153                 return -ENOMEM;
7154
7155         if (dev_priv->pwrctx == NULL)
7156                 dev_priv->pwrctx = intel_alloc_context_page(dev);
7157         if (!dev_priv->pwrctx) {
7158                 ironlake_teardown_rc6(dev);
7159                 return -ENOMEM;
7160         }
7161
7162         return 0;
7163 }
7164
7165 void ironlake_enable_rc6(struct drm_device *dev)
7166 {
7167         struct drm_i915_private *dev_priv = dev->dev_private;
7168         int ret;
7169
7170         /* rc6 disabled by default due to repeated reports of hanging during
7171          * boot and resume.
7172          */
7173         if (!i915_enable_rc6)
7174                 return;
7175
7176         ret = ironlake_setup_rc6(dev);
7177         if (ret)
7178                 return;
7179
7180         /*
7181          * GPU can automatically power down the render unit if given a page
7182          * to save state.
7183          */
7184         ret = BEGIN_LP_RING(6);
7185         if (ret) {
7186                 ironlake_teardown_rc6(dev);
7187                 return;
7188         }
7189
7190         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7191         OUT_RING(MI_SET_CONTEXT);
7192         OUT_RING(dev_priv->renderctx->gtt_offset |
7193                  MI_MM_SPACE_GTT |
7194                  MI_SAVE_EXT_STATE_EN |
7195                  MI_RESTORE_EXT_STATE_EN |
7196                  MI_RESTORE_INHIBIT);
7197         OUT_RING(MI_SUSPEND_FLUSH);
7198         OUT_RING(MI_NOOP);
7199         OUT_RING(MI_FLUSH);
7200         ADVANCE_LP_RING();
7201
7202         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7203         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7204 }
7205
7206
7207 /* Set up chip specific display functions */
7208 static void intel_init_display(struct drm_device *dev)
7209 {
7210         struct drm_i915_private *dev_priv = dev->dev_private;
7211
7212         /* We always want a DPMS function */
7213         if (HAS_PCH_SPLIT(dev))
7214                 dev_priv->display.dpms = ironlake_crtc_dpms;
7215         else
7216                 dev_priv->display.dpms = i9xx_crtc_dpms;
7217
7218         if (I915_HAS_FBC(dev)) {
7219                 if (HAS_PCH_SPLIT(dev)) {
7220                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7221                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
7222                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
7223                 } else if (IS_GM45(dev)) {
7224                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7225                         dev_priv->display.enable_fbc = g4x_enable_fbc;
7226                         dev_priv->display.disable_fbc = g4x_disable_fbc;
7227                 } else if (IS_CRESTLINE(dev)) {
7228                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7229                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
7230                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
7231                 }
7232                 /* 855GM needs testing */
7233         }
7234
7235         /* Returns the core display clock speed */
7236         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7237                 dev_priv->display.get_display_clock_speed =
7238                         i945_get_display_clock_speed;
7239         else if (IS_I915G(dev))
7240                 dev_priv->display.get_display_clock_speed =
7241                         i915_get_display_clock_speed;
7242         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7243                 dev_priv->display.get_display_clock_speed =
7244                         i9xx_misc_get_display_clock_speed;
7245         else if (IS_I915GM(dev))
7246                 dev_priv->display.get_display_clock_speed =
7247                         i915gm_get_display_clock_speed;
7248         else if (IS_I865G(dev))
7249                 dev_priv->display.get_display_clock_speed =
7250                         i865_get_display_clock_speed;
7251         else if (IS_I85X(dev))
7252                 dev_priv->display.get_display_clock_speed =
7253                         i855_get_display_clock_speed;
7254         else /* 852, 830 */
7255                 dev_priv->display.get_display_clock_speed =
7256                         i830_get_display_clock_speed;
7257
7258         /* For FIFO watermark updates */
7259         if (HAS_PCH_SPLIT(dev)) {
7260                 if (IS_GEN5(dev)) {
7261                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7262                                 dev_priv->display.update_wm = ironlake_update_wm;
7263                         else {
7264                                 DRM_DEBUG_KMS("Failed to get proper latency. "
7265                                               "Disable CxSR\n");
7266                                 dev_priv->display.update_wm = NULL;
7267                         }
7268                 } else if (IS_GEN6(dev)) {
7269                         if (SNB_READ_WM0_LATENCY()) {
7270                                 dev_priv->display.update_wm = sandybridge_update_wm;
7271                         } else {
7272                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
7273                                               "Disable CxSR\n");
7274                                 dev_priv->display.update_wm = NULL;
7275                         }
7276                 } else
7277                         dev_priv->display.update_wm = NULL;
7278         } else if (IS_PINEVIEW(dev)) {
7279                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7280                                             dev_priv->is_ddr3,
7281                                             dev_priv->fsb_freq,
7282                                             dev_priv->mem_freq)) {
7283                         DRM_INFO("failed to find known CxSR latency "
7284                                  "(found ddr%s fsb freq %d, mem freq %d), "
7285                                  "disabling CxSR\n",
7286                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
7287                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7288                         /* Disable CxSR and never update its watermark again */
7289                         pineview_disable_cxsr(dev);
7290                         dev_priv->display.update_wm = NULL;
7291                 } else
7292                         dev_priv->display.update_wm = pineview_update_wm;
7293         } else if (IS_G4X(dev))
7294                 dev_priv->display.update_wm = g4x_update_wm;
7295         else if (IS_GEN4(dev))
7296                 dev_priv->display.update_wm = i965_update_wm;
7297         else if (IS_GEN3(dev)) {
7298                 dev_priv->display.update_wm = i9xx_update_wm;
7299                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7300         } else if (IS_I85X(dev)) {
7301                 dev_priv->display.update_wm = i9xx_update_wm;
7302                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7303         } else {
7304                 dev_priv->display.update_wm = i830_update_wm;
7305                 if (IS_845G(dev))
7306                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7307                 else
7308                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7309         }
7310 }
7311
7312 /*
7313  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7314  * resume, or other times.  This quirk makes sure that's the case for
7315  * affected systems.
7316  */
7317 static void quirk_pipea_force (struct drm_device *dev)
7318 {
7319         struct drm_i915_private *dev_priv = dev->dev_private;
7320
7321         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7322         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7323 }
7324
7325 struct intel_quirk {
7326         int device;
7327         int subsystem_vendor;
7328         int subsystem_device;
7329         void (*hook)(struct drm_device *dev);
7330 };
7331
7332 struct intel_quirk intel_quirks[] = {
7333         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7334         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7335         /* HP Mini needs pipe A force quirk (LP: #322104) */
7336         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7337
7338         /* Thinkpad R31 needs pipe A force quirk */
7339         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7340         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7341         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7342
7343         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7344         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
7345         /* ThinkPad X40 needs pipe A force quirk */
7346
7347         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7348         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7349
7350         /* 855 & before need to leave pipe A & dpll A up */
7351         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7352         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7353 };
7354
7355 static void intel_init_quirks(struct drm_device *dev)
7356 {
7357         struct pci_dev *d = dev->pdev;
7358         int i;
7359
7360         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7361                 struct intel_quirk *q = &intel_quirks[i];
7362
7363                 if (d->device == q->device &&
7364                     (d->subsystem_vendor == q->subsystem_vendor ||
7365                      q->subsystem_vendor == PCI_ANY_ID) &&
7366                     (d->subsystem_device == q->subsystem_device ||
7367                      q->subsystem_device == PCI_ANY_ID))
7368                         q->hook(dev);
7369         }
7370 }
7371
7372 /* Disable the VGA plane that we never use */
7373 static void i915_disable_vga(struct drm_device *dev)
7374 {
7375         struct drm_i915_private *dev_priv = dev->dev_private;
7376         u8 sr1;
7377         u32 vga_reg;
7378
7379         if (HAS_PCH_SPLIT(dev))
7380                 vga_reg = CPU_VGACNTRL;
7381         else
7382                 vga_reg = VGACNTRL;
7383
7384         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7385         outb(1, VGA_SR_INDEX);
7386         sr1 = inb(VGA_SR_DATA);
7387         outb(sr1 | 1<<5, VGA_SR_DATA);
7388         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7389         udelay(300);
7390
7391         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7392         POSTING_READ(vga_reg);
7393 }
7394
7395 void intel_modeset_init(struct drm_device *dev)
7396 {
7397         struct drm_i915_private *dev_priv = dev->dev_private;
7398         int i;
7399
7400         drm_mode_config_init(dev);
7401
7402         dev->mode_config.min_width = 0;
7403         dev->mode_config.min_height = 0;
7404
7405         dev->mode_config.funcs = (void *)&intel_mode_funcs;
7406
7407         intel_init_quirks(dev);
7408
7409         intel_init_display(dev);
7410
7411         if (IS_GEN2(dev)) {
7412                 dev->mode_config.max_width = 2048;
7413                 dev->mode_config.max_height = 2048;
7414         } else if (IS_GEN3(dev)) {
7415                 dev->mode_config.max_width = 4096;
7416                 dev->mode_config.max_height = 4096;
7417         } else {
7418                 dev->mode_config.max_width = 8192;
7419                 dev->mode_config.max_height = 8192;
7420         }
7421         dev->mode_config.fb_base = dev->agp->base;
7422
7423         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7424                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7425
7426         for (i = 0; i < dev_priv->num_pipe; i++) {
7427                 intel_crtc_init(dev, i);
7428         }
7429
7430         intel_setup_outputs(dev);
7431
7432         intel_enable_clock_gating(dev);
7433
7434         /* Just disable it once at startup */
7435         i915_disable_vga(dev);
7436
7437         if (IS_IRONLAKE_M(dev)) {
7438                 ironlake_enable_drps(dev);
7439                 intel_init_emon(dev);
7440         }
7441
7442         if (IS_GEN6(dev))
7443                 gen6_enable_rps(dev_priv);
7444
7445         if (IS_IRONLAKE_M(dev))
7446                 ironlake_enable_rc6(dev);
7447
7448         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7449         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7450                     (unsigned long)dev);
7451
7452         intel_setup_overlay(dev);
7453 }
7454
7455 void intel_modeset_cleanup(struct drm_device *dev)
7456 {
7457         struct drm_i915_private *dev_priv = dev->dev_private;
7458         struct drm_crtc *crtc;
7459         struct intel_crtc *intel_crtc;
7460
7461         drm_kms_helper_poll_fini(dev);
7462         mutex_lock(&dev->struct_mutex);
7463
7464         intel_unregister_dsm_handler();
7465
7466
7467         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7468                 /* Skip inactive CRTCs */
7469                 if (!crtc->fb)
7470                         continue;
7471
7472                 intel_crtc = to_intel_crtc(crtc);
7473                 intel_increase_pllclock(crtc);
7474         }
7475
7476         if (dev_priv->display.disable_fbc)
7477                 dev_priv->display.disable_fbc(dev);
7478
7479         if (IS_IRONLAKE_M(dev))
7480                 ironlake_disable_drps(dev);
7481         if (IS_GEN6(dev))
7482                 gen6_disable_rps(dev);
7483
7484         if (IS_IRONLAKE_M(dev))
7485                 ironlake_disable_rc6(dev);
7486
7487         mutex_unlock(&dev->struct_mutex);
7488
7489         /* Disable the irq before mode object teardown, for the irq might
7490          * enqueue unpin/hotplug work. */
7491         drm_irq_uninstall(dev);
7492         cancel_work_sync(&dev_priv->hotplug_work);
7493
7494         /* Shut off idle work before the crtcs get freed. */
7495         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7496                 intel_crtc = to_intel_crtc(crtc);
7497                 del_timer_sync(&intel_crtc->idle_timer);
7498         }
7499         del_timer_sync(&dev_priv->idle_timer);
7500         cancel_work_sync(&dev_priv->idle_work);
7501
7502         drm_mode_config_cleanup(dev);
7503 }
7504
7505 /*
7506  * Return which encoder is currently attached for connector.
7507  */
7508 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7509 {
7510         return &intel_attached_encoder(connector)->base;
7511 }
7512
7513 void intel_connector_attach_encoder(struct intel_connector *connector,
7514                                     struct intel_encoder *encoder)
7515 {
7516         connector->encoder = encoder;
7517         drm_mode_connector_attach_encoder(&connector->base,
7518                                           &encoder->base);
7519 }
7520
7521 /*
7522  * set vga decode state - true == enable VGA decode
7523  */
7524 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7525 {
7526         struct drm_i915_private *dev_priv = dev->dev_private;
7527         u16 gmch_ctrl;
7528
7529         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7530         if (state)
7531                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7532         else
7533                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7534         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7535         return 0;
7536 }
7537
7538 #ifdef CONFIG_DEBUG_FS
7539 #include <linux/seq_file.h>
7540
7541 struct intel_display_error_state {
7542         struct intel_cursor_error_state {
7543                 u32 control;
7544                 u32 position;
7545                 u32 base;
7546                 u32 size;
7547         } cursor[2];
7548
7549         struct intel_pipe_error_state {
7550                 u32 conf;
7551                 u32 source;
7552
7553                 u32 htotal;
7554                 u32 hblank;
7555                 u32 hsync;
7556                 u32 vtotal;
7557                 u32 vblank;
7558                 u32 vsync;
7559         } pipe[2];
7560
7561         struct intel_plane_error_state {
7562                 u32 control;
7563                 u32 stride;
7564                 u32 size;
7565                 u32 pos;
7566                 u32 addr;
7567                 u32 surface;
7568                 u32 tile_offset;
7569         } plane[2];
7570 };
7571
7572 struct intel_display_error_state *
7573 intel_display_capture_error_state(struct drm_device *dev)
7574 {
7575         drm_i915_private_t *dev_priv = dev->dev_private;
7576         struct intel_display_error_state *error;
7577         int i;
7578
7579         error = kmalloc(sizeof(*error), GFP_ATOMIC);
7580         if (error == NULL)
7581                 return NULL;
7582
7583         for (i = 0; i < 2; i++) {
7584                 error->cursor[i].control = I915_READ(CURCNTR(i));
7585                 error->cursor[i].position = I915_READ(CURPOS(i));
7586                 error->cursor[i].base = I915_READ(CURBASE(i));
7587
7588                 error->plane[i].control = I915_READ(DSPCNTR(i));
7589                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7590                 error->plane[i].size = I915_READ(DSPSIZE(i));
7591                 error->plane[i].pos= I915_READ(DSPPOS(i));
7592                 error->plane[i].addr = I915_READ(DSPADDR(i));
7593                 if (INTEL_INFO(dev)->gen >= 4) {
7594                         error->plane[i].surface = I915_READ(DSPSURF(i));
7595                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7596                 }
7597
7598                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7599                 error->pipe[i].source = I915_READ(PIPESRC(i));
7600                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7601                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7602                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7603                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7604                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7605                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7606         }
7607
7608         return error;
7609 }
7610
7611 void
7612 intel_display_print_error_state(struct seq_file *m,
7613                                 struct drm_device *dev,
7614                                 struct intel_display_error_state *error)
7615 {
7616         int i;
7617
7618         for (i = 0; i < 2; i++) {
7619                 seq_printf(m, "Pipe [%d]:\n", i);
7620                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7621                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7622                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7623                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7624                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7625                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7626                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7627                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7628
7629                 seq_printf(m, "Plane [%d]:\n", i);
7630                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7631                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7632                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7633                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
7634                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7635                 if (INTEL_INFO(dev)->gen >= 4) {
7636                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7637                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7638                 }
7639
7640                 seq_printf(m, "Cursor [%d]:\n", i);
7641                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7642                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
7643                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7644         }
7645 }
7646 #endif