drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define MAX_NOPID ((u32)~0)
  35
  36 /** These are the interrupts used by the driver */
  37 #define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT |               \
  38                                     I915_ASLE_INTERRUPT |               \
  39                                     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
  40                                     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
  41
  42 void
  43 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
  44 {
  45         if ((dev_priv->irq_mask_reg & mask) != 0) {
  46                 dev_priv->irq_mask_reg &= ~mask;
  47                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  48                 (void) I915_READ(IMR);
  49         }
  50 }
  51
  52 static inline void
  53 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
  54 {
  55         if ((dev_priv->irq_mask_reg & mask) != mask) {
  56                 dev_priv->irq_mask_reg |= mask;
  57                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  58                 (void) I915_READ(IMR);
  59         }
  60 }
  61
  62 /**
  63  * i915_get_pipe - return the the pipe associated with a given plane
  64  * @dev: DRM device
  65  * @plane: plane to look for
  66  *
  67  * The Intel Mesa & 2D drivers call the vblank routines with a plane number
  68  * rather than a pipe number, since they may not always be equal.  This routine
  69  * maps the given @plane back to a pipe number.
  70  */
  71 static int
  72 i915_get_pipe(struct drm_device *dev, int plane)
  73 {
  74         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  75         u32 dspcntr;
  76
  77         dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
  78
  79         return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
  80 }
  81
  82 /**
  83  * i915_get_plane - return the the plane associated with a given pipe
  84  * @dev: DRM device
  85  * @pipe: pipe to look for
  86  *
  87  * The Intel Mesa & 2D drivers call the vblank routines with a plane number
  88  * rather than a plane number, since they may not always be equal.  This routine
  89  * maps the given @pipe back to a plane number.
  90  */
  91 static int
  92 i915_get_plane(struct drm_device *dev, int pipe)
  93 {
  94         if (i915_get_pipe(dev, 0) == pipe)
  95                 return 0;
  96         return 1;
  97 }
  98
  99 /**
 100  * i915_pipe_enabled - check if a pipe is enabled
 101  * @dev: DRM device
 102  * @pipe: pipe to check
 103  *
 104  * Reading certain registers when the pipe is disabled can hang the chip.
 105  * Use this routine to make sure the PLL is running and the pipe is active
 106  * before reading such registers if unsure.
 107  */
 108 static int
 109 i915_pipe_enabled(struct drm_device *dev, int pipe)
 110 {
 111         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 112         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 113
 114         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 115                 return 1;
 116
 117         return 0;
 118 }
 119
 120 /**
 121  * Emit blits for scheduled buffer swaps.
 122  *
 123  * This function will be called with the HW lock held.
 124  */
 125 static void i915_vblank_tasklet(struct drm_device *dev)
 126 {
 127         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 128         unsigned long irqflags;
 129         struct list_head *list, *tmp, hits, *hit;
 130         int nhits, nrects, slice[2], upper[2], lower[2], i;
 131         unsigned counter[2];
 132         struct drm_drawable_info *drw;
 133         drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
 134         u32 cpp = dev_priv->cpp;
 135         u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
 136                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
 137                                 XY_SRC_COPY_BLT_WRITE_RGB)
 138                              : XY_SRC_COPY_BLT_CMD;
 139         u32 src_pitch = sarea_priv->pitch * cpp;
 140         u32 dst_pitch = sarea_priv->pitch * cpp;
 141         u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
 142         RING_LOCALS;
 143
 144         if (IS_I965G(dev) && sarea_priv->front_tiled) {
 145                 cmd |= XY_SRC_COPY_BLT_DST_TILED;
 146                 dst_pitch >>= 2;
 147         }
 148         if (IS_I965G(dev) && sarea_priv->back_tiled) {
 149                 cmd |= XY_SRC_COPY_BLT_SRC_TILED;
 150                 src_pitch >>= 2;
 151         }
 152
 153         counter[0] = drm_vblank_count(dev, 0);
 154         counter[1] = drm_vblank_count(dev, 1);
 155
 156         DRM_DEBUG("\n");
 157
 158         INIT_LIST_HEAD(&hits);
 159
 160         nhits = nrects = 0;
 161
 162         spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
 163
 164         /* Find buffer swaps scheduled for this vertical blank */
 165         list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
 166                 drm_i915_vbl_swap_t *vbl_swap =
 167                         list_entry(list, drm_i915_vbl_swap_t, head);
 168                 int pipe = i915_get_pipe(dev, vbl_swap->plane);
 169
 170                 if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
 171                         continue;
 172
 173                 list_del(list);
 174                 dev_priv->swaps_pending--;
 175                 drm_vblank_put(dev, pipe);
 176
 177                 spin_unlock(&dev_priv->swaps_lock);
 178                 spin_lock(&dev->drw_lock);
 179
 180                 drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
 181
 182                 if (!drw) {
 183                         spin_unlock(&dev->drw_lock);
 184                         drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
 185                         spin_lock(&dev_priv->swaps_lock);
 186                         continue;
 187                 }
 188
 189                 list_for_each(hit, &hits) {
 190                         drm_i915_vbl_swap_t *swap_cmp =
 191                                 list_entry(hit, drm_i915_vbl_swap_t, head);
 192                         struct drm_drawable_info *drw_cmp =
 193                                 drm_get_drawable_info(dev, swap_cmp->drw_id);
 194
 195                         if (drw_cmp &&
 196                             drw_cmp->rects[0].y1 > drw->rects[0].y1) {
 197                                 list_add_tail(list, hit);
 198                                 break;
 199                         }
 200                 }
 201
 202                 spin_unlock(&dev->drw_lock);
 203
 204                 /* List of hits was empty, or we reached the end of it */
 205                 if (hit == &hits)
 206                         list_add_tail(list, hits.prev);
 207
 208                 nhits++;
 209
 210                 spin_lock(&dev_priv->swaps_lock);
 211         }
 212
 213         if (nhits == 0) {
 214                 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
 215                 return;
 216         }
 217
 218         spin_unlock(&dev_priv->swaps_lock);
 219
 220         i915_kernel_lost_context(dev);
 221
 222         if (IS_I965G(dev)) {
 223                 BEGIN_LP_RING(4);
 224
 225                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 226                 OUT_RING(0);
 227                 OUT_RING(((sarea_priv->width - 1) & 0xffff) | ((sarea_priv->height - 1) << 16));
 228                 OUT_RING(0);
 229                 ADVANCE_LP_RING();
 230         } else {
 231                 BEGIN_LP_RING(6);
 232
 233                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 234                 OUT_RING(0);
 235                 OUT_RING(0);
 236                 OUT_RING(sarea_priv->width | sarea_priv->height << 16);
 237                 OUT_RING(sarea_priv->width | sarea_priv->height << 16);
 238                 OUT_RING(0);
 239
 240                 ADVANCE_LP_RING();
 241         }
 242
 243         sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
 244
 245         upper[0] = upper[1] = 0;
 246         slice[0] = max(sarea_priv->pipeA_h / nhits, 1);
 247         slice[1] = max(sarea_priv->pipeB_h / nhits, 1);
 248         lower[0] = sarea_priv->pipeA_y + slice[0];
 249         lower[1] = sarea_priv->pipeB_y + slice[0];
 250
 251         spin_lock(&dev->drw_lock);
 252
 253         /* Emit blits for buffer swaps, partitioning both outputs into as many
 254          * slices as there are buffer swaps scheduled in order to avoid tearing
 255          * (based on the assumption that a single buffer swap would always
 256          * complete before scanout starts).
 257          */
 258         for (i = 0; i++ < nhits;
 259              upper[0] = lower[0], lower[0] += slice[0],
 260              upper[1] = lower[1], lower[1] += slice[1]) {
 261                 if (i == nhits)
 262                         lower[0] = lower[1] = sarea_priv->height;
 263
 264                 list_for_each(hit, &hits) {
 265                         drm_i915_vbl_swap_t *swap_hit =
 266                                 list_entry(hit, drm_i915_vbl_swap_t, head);
 267                         struct drm_clip_rect *rect;
 268                         int num_rects, plane;
 269                         unsigned short top, bottom;
 270
 271                         drw = drm_get_drawable_info(dev, swap_hit->drw_id);
 272
 273                         if (!drw)
 274                                 continue;
 275
 276                         rect = drw->rects;
 277                         plane = swap_hit->plane;
 278                         top = upper[plane];
 279                         bottom = lower[plane];
 280
 281                         for (num_rects = drw->num_rects; num_rects--; rect++) {
 282                                 int y1 = max(rect->y1, top);
 283                                 int y2 = min(rect->y2, bottom);
 284
 285                                 if (y1 >= y2)
 286                                         continue;
 287
 288                                 BEGIN_LP_RING(8);
 289
 290                                 OUT_RING(cmd);
 291                                 OUT_RING(ropcpp | dst_pitch);
 292                                 OUT_RING((y1 << 16) | rect->x1);
 293                                 OUT_RING((y2 << 16) | rect->x2);
 294                                 OUT_RING(sarea_priv->front_offset);
 295                                 OUT_RING((y1 << 16) | rect->x1);
 296                                 OUT_RING(src_pitch);
 297                                 OUT_RING(sarea_priv->back_offset);
 298
 299                                 ADVANCE_LP_RING();
 300                         }
 301                 }
 302         }
 303
 304         spin_unlock_irqrestore(&dev->drw_lock, irqflags);
 305
 306         list_for_each_safe(hit, tmp, &hits) {
 307                 drm_i915_vbl_swap_t *swap_hit =
 308                         list_entry(hit, drm_i915_vbl_swap_t, head);
 309
 310                 list_del(hit);
 311
 312                 drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
 313         }
 314 }
 315
 316 u32 i915_get_vblank_counter(struct drm_device *dev, int plane)
 317 {
 318         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 319         unsigned long high_frame;
 320         unsigned long low_frame;
 321         u32 high1, high2, low, count;
 322         int pipe;
 323
 324         pipe = i915_get_pipe(dev, plane);
 325         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 326         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 327
 328         if (!i915_pipe_enabled(dev, pipe)) {
 329                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
 330                 return 0;
 331         }
 332
 333         /*
 334          * High & low register fields aren't synchronized, so make sure
 335          * we get a low value that's stable across two reads of the high
 336          * register.
 337          */
 338         do {
 339                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 340                          PIPE_FRAME_HIGH_SHIFT);
 341                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 342                         PIPE_FRAME_LOW_SHIFT);
 343                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 344                          PIPE_FRAME_HIGH_SHIFT);
 345         } while (high1 != high2);
 346
 347         count = (high1 << 8) | low;
 348
 349         return count;
 350 }
 351
 352 void
 353 i915_gem_vblank_work_handler(struct work_struct *work)
 354 {
 355         drm_i915_private_t *dev_priv;
 356         struct drm_device *dev;
 357
 358         dev_priv = container_of(work, drm_i915_private_t,
 359                                 mm.vblank_work);
 360         dev = dev_priv->dev;
 361
 362         mutex_lock(&dev->struct_mutex);
 363         i915_vblank_tasklet(dev);
 364         mutex_unlock(&dev->struct_mutex);
 365 }
 366
 367 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 368 {
 369         struct drm_device *dev = (struct drm_device *) arg;
 370         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 371         u32 iir;
 372         u32 pipea_stats, pipeb_stats;
 373         int vblank = 0;
 374
 375         atomic_inc(&dev_priv->irq_received);
 376
 377         if (dev->pdev->msi_enabled)
 378                 I915_WRITE(IMR, ~0);
 379         iir = I915_READ(IIR);
 380
 381         if (iir == 0) {
 382                 if (dev->pdev->msi_enabled) {
 383                         I915_WRITE(IMR, dev_priv->irq_mask_reg);
 384                         (void) I915_READ(IMR);
 385                 }
 386                 return IRQ_NONE;
 387         }
 388
 389         /*
 390          * Clear the PIPE(A|B)STAT regs before the IIR otherwise
 391          * we may get extra interrupts.
 392          */
 393         if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
 394                 pipea_stats = I915_READ(PIPEASTAT);
 395                 if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A))
 396                         pipea_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
 397                                          PIPE_VBLANK_INTERRUPT_ENABLE);
 398                 else if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
 399                                         PIPE_VBLANK_INTERRUPT_STATUS)) {
 400                         vblank++;
 401                         drm_handle_vblank(dev, i915_get_plane(dev, 0));
 402                 }
 403
 404                 I915_WRITE(PIPEASTAT, pipea_stats);
 405         }
 406         if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
 407                 pipeb_stats = I915_READ(PIPEBSTAT);
 408                 /* Ack the event */
 409                 I915_WRITE(PIPEBSTAT, pipeb_stats);
 410
 411                 /* The vblank interrupt gets enabled even if we didn't ask for
 412                    it, so make sure it's shut down again */
 413                 if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B))
 414                         pipeb_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
 415                                          PIPE_VBLANK_INTERRUPT_ENABLE);
 416                 else if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
 417                                         PIPE_VBLANK_INTERRUPT_STATUS)) {
 418                         vblank++;
 419                         drm_handle_vblank(dev, i915_get_plane(dev, 1));
 420                 }
 421
 422                 if (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS)
 423                         opregion_asle_intr(dev);
 424                 I915_WRITE(PIPEBSTAT, pipeb_stats);
 425         }
 426
 427         I915_WRITE(IIR, iir);
 428         if (dev->pdev->msi_enabled)
 429                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 430         (void) I915_READ(IIR); /* Flush posted writes */
 431
 432         if (dev_priv->sarea_priv)
 433                 dev_priv->sarea_priv->last_dispatch =
 434                         READ_BREADCRUMB(dev_priv);
 435
 436         if (iir & I915_USER_INTERRUPT) {
 437                 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
 438                 DRM_WAKEUP(&dev_priv->irq_queue);
 439         }
 440
 441         if (iir & I915_ASLE_INTERRUPT)
 442                 opregion_asle_intr(dev);
 443
 444         if (vblank && dev_priv->swaps_pending > 0) {
 445                 if (dev_priv->ring.ring_obj == NULL)
 446                         drm_locked_tasklet(dev, i915_vblank_tasklet);
 447                 else
 448                         schedule_work(&dev_priv->mm.vblank_work);
 449         }
 450
 451         return IRQ_HANDLED;
 452 }
 453
 454 static int i915_emit_irq(struct drm_device * dev)
 455 {
 456         drm_i915_private_t *dev_priv = dev->dev_private;
 457         RING_LOCALS;
 458
 459         i915_kernel_lost_context(dev);
 460
 461         DRM_DEBUG("\n");
 462
 463         dev_priv->counter++;
 464         if (dev_priv->counter > 0x7FFFFFFFUL)
 465                 dev_priv->counter = 1;
 466         if (dev_priv->sarea_priv)
 467                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 468
 469         BEGIN_LP_RING(6);
 470         OUT_RING(MI_STORE_DWORD_INDEX);
 471         OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
 472         OUT_RING(dev_priv->counter);
 473         OUT_RING(0);
 474         OUT_RING(0);
 475         OUT_RING(MI_USER_INTERRUPT);
 476         ADVANCE_LP_RING();
 477
 478         return dev_priv->counter;
 479 }
 480
 481 void i915_user_irq_get(struct drm_device *dev)
 482 {
 483         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 484         unsigned long irqflags;
 485
 486         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 487         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
 488                 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 489         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 490 }
 491
 492 void i915_user_irq_put(struct drm_device *dev)
 493 {
 494         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 495         unsigned long irqflags;
 496
 497         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 498         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
 499         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
 500                 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 501         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 502 }
 503
 504 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 505 {
 506         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 507         int ret = 0;
 508
 509         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
 510                   READ_BREADCRUMB(dev_priv));
 511
 512         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 513                 if (dev_priv->sarea_priv) {
 514                         dev_priv->sarea_priv->last_dispatch =
 515                                 READ_BREADCRUMB(dev_priv);
 516                 }
 517                 return 0;
 518         }
 519
 520         if (dev_priv->sarea_priv)
 521                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 522
 523         i915_user_irq_get(dev);
 524         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 525                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 526         i915_user_irq_put(dev);
 527
 528         if (ret == -EBUSY) {
 529                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 530                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 531         }
 532
 533         if (dev_priv->sarea_priv)
 534                 dev_priv->sarea_priv->last_dispatch =
 535                         READ_BREADCRUMB(dev_priv);
 536
 537         return ret;
 538 }
 539
 540 /* Needs the lock as it touches the ring.
 541  */
 542 int i915_irq_emit(struct drm_device *dev, void *data,
 543                          struct drm_file *file_priv)
 544 {
 545         drm_i915_private_t *dev_priv = dev->dev_private;
 546         drm_i915_irq_emit_t *emit = data;
 547         int result;
 548
 549         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 550
 551         if (!dev_priv) {
 552                 DRM_ERROR("called with no initialization\n");
 553                 return -EINVAL;
 554         }
 555         mutex_lock(&dev->struct_mutex);
 556         result = i915_emit_irq(dev);
 557         mutex_unlock(&dev->struct_mutex);
 558
 559         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 560                 DRM_ERROR("copy_to_user\n");
 561                 return -EFAULT;
 562         }
 563
 564         return 0;
 565 }
 566
 567 /* Doesn't need the hardware lock.
 568  */
 569 int i915_irq_wait(struct drm_device *dev, void *data,
 570                          struct drm_file *file_priv)
 571 {
 572         drm_i915_private_t *dev_priv = dev->dev_private;
 573         drm_i915_irq_wait_t *irqwait = data;
 574
 575         if (!dev_priv) {
 576                 DRM_ERROR("called with no initialization\n");
 577                 return -EINVAL;
 578         }
 579
 580         return i915_wait_irq(dev, irqwait->irq_seq);
 581 }
 582
 583 int i915_enable_vblank(struct drm_device *dev, int plane)
 584 {
 585         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 586         int pipe = i915_get_pipe(dev, plane);
 587         u32     pipestat_reg = 0;
 588         u32     pipestat;
 589         u32     interrupt = 0;
 590         unsigned long irqflags;
 591
 592         switch (pipe) {
 593         case 0:
 594                 pipestat_reg = PIPEASTAT;
 595                 interrupt = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
 596                 break;
 597         case 1:
 598                 pipestat_reg = PIPEBSTAT;
 599                 interrupt = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
 600                 break;
 601         default:
 602                 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
 603                           pipe);
 604                 return 0;
 605         }
 606
 607         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 608         /* Enabling vblank events in IMR comes before PIPESTAT write, or
 609          * there's a race where the PIPESTAT vblank bit gets set to 1, so
 610          * the OR of enabled PIPESTAT bits goes to 1, so the PIPExEVENT in
 611          * ISR flashes to 1, but the IIR bit doesn't get set to 1 because
 612          * IMR masks it.  It doesn't ever get set after we clear the masking
 613          * in IMR because the ISR bit is edge, not level-triggered, on the
 614          * OR of PIPESTAT bits.
 615          */
 616         i915_enable_irq(dev_priv, interrupt);
 617         pipestat = I915_READ(pipestat_reg);
 618         if (IS_I965G(dev))
 619                 pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE;
 620         else
 621                 pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE;
 622         /* Clear any stale interrupt status */
 623         pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
 624                      PIPE_VBLANK_INTERRUPT_STATUS);
 625         I915_WRITE(pipestat_reg, pipestat);
 626         (void) I915_READ(pipestat_reg); /* Posting read */
 627         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 628
 629         return 0;
 630 }
 631
 632 void i915_disable_vblank(struct drm_device *dev, int plane)
 633 {
 634         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 635         int pipe = i915_get_pipe(dev, plane);
 636         u32     pipestat_reg = 0;
 637         u32     pipestat;
 638         u32     interrupt = 0;
 639         unsigned long irqflags;
 640
 641         switch (pipe) {
 642         case 0:
 643                 pipestat_reg = PIPEASTAT;
 644                 interrupt = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
 645                 break;
 646         case 1:
 647                 pipestat_reg = PIPEBSTAT;
 648                 interrupt = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
 649                 break;
 650         default:
 651                 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
 652                           pipe);
 653                 return;
 654                 break;
 655         }
 656
 657         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 658         i915_disable_irq(dev_priv, interrupt);
 659         pipestat = I915_READ(pipestat_reg);
 660         pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
 661                       PIPE_VBLANK_INTERRUPT_ENABLE);
 662         /* Clear any stale interrupt status */
 663         pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
 664                      PIPE_VBLANK_INTERRUPT_STATUS);
 665         I915_WRITE(pipestat_reg, pipestat);
 666         (void) I915_READ(pipestat_reg); /* Posting read */
 667         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 668 }
 669
 670 /* Set the vblank monitor pipe
 671  */
 672 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 673                          struct drm_file *file_priv)
 674 {
 675         drm_i915_private_t *dev_priv = dev->dev_private;
 676
 677         if (!dev_priv) {
 678                 DRM_ERROR("called with no initialization\n");
 679                 return -EINVAL;
 680         }
 681
 682         return 0;
 683 }
 684
 685 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 686                          struct drm_file *file_priv)
 687 {
 688         drm_i915_private_t *dev_priv = dev->dev_private;
 689         drm_i915_vblank_pipe_t *pipe = data;
 690
 691         if (!dev_priv) {
 692                 DRM_ERROR("called with no initialization\n");
 693                 return -EINVAL;
 694         }
 695
 696         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 697
 698         return 0;
 699 }
 700
 701 /**
 702  * Schedule buffer swap at given vertical blank.
 703  */
 704 int i915_vblank_swap(struct drm_device *dev, void *data,
 705                      struct drm_file *file_priv)
 706 {
 707         drm_i915_private_t *dev_priv = dev->dev_private;
 708         drm_i915_vblank_swap_t *swap = data;
 709         drm_i915_vbl_swap_t *vbl_swap;
 710         unsigned int pipe, seqtype, curseq, plane;
 711         unsigned long irqflags;
 712         struct list_head *list;
 713         int ret;
 714
 715         if (!dev_priv || !dev_priv->sarea_priv) {
 716                 DRM_ERROR("%s called with no initialization\n", __func__);
 717                 return -EINVAL;
 718         }
 719
 720         if (dev_priv->sarea_priv->rotation) {
 721                 DRM_DEBUG("Rotation not supported\n");
 722                 return -EINVAL;
 723         }
 724
 725         if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
 726                              _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)) {
 727                 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
 728                 return -EINVAL;
 729         }
 730
 731         plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
 732         pipe = i915_get_pipe(dev, plane);
 733
 734         seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
 735
 736         if (!(dev_priv->vblank_pipe & (1 << pipe))) {
 737                 DRM_ERROR("Invalid pipe %d\n", pipe);
 738                 return -EINVAL;
 739         }
 740
 741         spin_lock_irqsave(&dev->drw_lock, irqflags);
 742
 743         if (!drm_get_drawable_info(dev, swap->drawable)) {
 744                 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
 745                 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
 746                 return -EINVAL;
 747         }
 748
 749         spin_unlock_irqrestore(&dev->drw_lock, irqflags);
 750
 751         /*
 752          * We take the ref here and put it when the swap actually completes
 753          * in the tasklet.
 754          */
 755         ret = drm_vblank_get(dev, pipe);
 756         if (ret)
 757                 return ret;
 758         curseq = drm_vblank_count(dev, pipe);
 759
 760         if (seqtype == _DRM_VBLANK_RELATIVE)
 761                 swap->sequence += curseq;
 762
 763         if ((curseq - swap->sequence) <= (1<<23)) {
 764                 if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
 765                         swap->sequence = curseq + 1;
 766                 } else {
 767                         DRM_DEBUG("Missed target sequence\n");
 768                         drm_vblank_put(dev, pipe);
 769                         return -EINVAL;
 770                 }
 771         }
 772
 773         spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
 774
 775         list_for_each(list, &dev_priv->vbl_swaps.head) {
 776                 vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
 777
 778                 if (vbl_swap->drw_id == swap->drawable &&
 779                     vbl_swap->plane == plane &&
 780                     vbl_swap->sequence == swap->sequence) {
 781                         spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
 782                         drm_vblank_put(dev, pipe);
 783                         DRM_DEBUG("Already scheduled\n");
 784                         return 0;
 785                 }
 786         }
 787
 788         spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
 789
 790         if (dev_priv->swaps_pending >= 100) {
 791                 DRM_DEBUG("Too many swaps queued\n");
 792                 drm_vblank_put(dev, pipe);
 793                 return -EBUSY;
 794         }
 795
 796         vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);
 797
 798         if (!vbl_swap) {
 799                 DRM_ERROR("Failed to allocate memory to queue swap\n");
 800                 drm_vblank_put(dev, pipe);
 801                 return -ENOMEM;
 802         }
 803
 804         DRM_DEBUG("\n");
 805
 806         vbl_swap->drw_id = swap->drawable;
 807         vbl_swap->plane = plane;
 808         vbl_swap->sequence = swap->sequence;
 809
 810         spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
 811
 812         list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);
 813         dev_priv->swaps_pending++;
 814
 815         spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
 816
 817         return 0;
 818 }
 819
 820 /* drm_dma.h hooks
 821 */
 822 void i915_driver_irq_preinstall(struct drm_device * dev)
 823 {
 824         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 825
 826         I915_WRITE(HWSTAM, 0xeffe);
 827         I915_WRITE(IMR, 0xffffffff);
 828         I915_WRITE(IER, 0x0);
 829 }
 830
 831 int i915_driver_irq_postinstall(struct drm_device *dev)
 832 {
 833         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 834         int ret, num_pipes = 2;
 835
 836         spin_lock_init(&dev_priv->swaps_lock);
 837         INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
 838         dev_priv->swaps_pending = 0;
 839
 840         /* Set initial unmasked IRQs to just the selected vblank pipes. */
 841         dev_priv->irq_mask_reg = ~0;
 842
 843         ret = drm_vblank_init(dev, num_pipes);
 844         if (ret)
 845                 return ret;
 846
 847         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 848         dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
 849         dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 850
 851         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 852
 853         dev_priv->irq_mask_reg &= I915_INTERRUPT_ENABLE_MASK;
 854
 855         I915_WRITE(IMR, dev_priv->irq_mask_reg);
 856         I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
 857         (void) I915_READ(IER);
 858
 859         opregion_enable_asle(dev);
 860         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
 861
 862         return 0;
 863 }
 864
 865 void i915_driver_irq_uninstall(struct drm_device * dev)
 866 {
 867         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 868         u32 temp;
 869
 870         if (!dev_priv)
 871                 return;
 872
 873         dev_priv->vblank_pipe = 0;
 874
 875         I915_WRITE(HWSTAM, 0xffffffff);
 876         I915_WRITE(IMR, 0xffffffff);
 877         I915_WRITE(IER, 0x0);
 878
 879         temp = I915_READ(PIPEASTAT);
 880         I915_WRITE(PIPEASTAT, temp);
 881         temp = I915_READ(PIPEBSTAT);
 882         I915_WRITE(PIPEBSTAT, temp);
 883         temp = I915_READ(IIR);
 884         I915_WRITE(IIR, temp);
 885 }