drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/intel-gtt.h>
  38
  39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
  40
  41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
  42                                                   bool pipelined);
  43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  46                                              int write);
  47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  48                                                      uint64_t offset,
  49                                                      uint64_t size);
  50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  51 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
  52                                           bool interruptible);
  53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  54                                            unsigned alignment);
  55 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  56 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  57                                 struct drm_i915_gem_pwrite *args,
  58                                 struct drm_file *file_priv);
  59 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
  60
  61 static int
  62 i915_gem_object_get_pages(struct drm_gem_object *obj,
  63                           gfp_t gfpmask);
  64
  65 static void
  66 i915_gem_object_put_pages(struct drm_gem_object *obj);
  67
  68 static LIST_HEAD(shrink_list);
  69 static DEFINE_SPINLOCK(shrink_list_lock);
  70
  71 /* some bookkeeping */
  72 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  73                                   size_t size)
  74 {
  75         dev_priv->mm.object_count++;
  76         dev_priv->mm.object_memory += size;
  77 }
  78
  79 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  80                                      size_t size)
  81 {
  82         dev_priv->mm.object_count--;
  83         dev_priv->mm.object_memory -= size;
  84 }
  85
  86 static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv,
  87                                   size_t size)
  88 {
  89         dev_priv->mm.gtt_count++;
  90         dev_priv->mm.gtt_memory += size;
  91 }
  92
  93 static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv,
  94                                      size_t size)
  95 {
  96         dev_priv->mm.gtt_count--;
  97         dev_priv->mm.gtt_memory -= size;
  98 }
  99
 100 static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv,
 101                                   size_t size)
 102 {
 103         dev_priv->mm.pin_count++;
 104         dev_priv->mm.pin_memory += size;
 105 }
 106
 107 static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv,
 108                                      size_t size)
 109 {
 110         dev_priv->mm.pin_count--;
 111         dev_priv->mm.pin_memory -= size;
 112 }
 113
 114 int
 115 i915_gem_check_is_wedged(struct drm_device *dev)
 116 {
 117         struct drm_i915_private *dev_priv = dev->dev_private;
 118         struct completion *x = &dev_priv->error_completion;
 119         unsigned long flags;
 120         int ret;
 121
 122         if (!atomic_read(&dev_priv->mm.wedged))
 123                 return 0;
 124
 125         ret = wait_for_completion_interruptible(x);
 126         if (ret)
 127                 return ret;
 128
 129         /* Success, we reset the GPU! */
 130         if (!atomic_read(&dev_priv->mm.wedged))
 131                 return 0;
 132
 133         /* GPU is hung, bump the completion count to account for
 134          * the token we just consumed so that we never hit zero and
 135          * end up waiting upon a subsequent completion event that
 136          * will never happen.
 137          */
 138         spin_lock_irqsave(&x->wait.lock, flags);
 139         x->done++;
 140         spin_unlock_irqrestore(&x->wait.lock, flags);
 141         return -EIO;
 142 }
 143
 144 static int i915_mutex_lock_interruptible(struct drm_device *dev)
 145 {
 146         struct drm_i915_private *dev_priv = dev->dev_private;
 147         int ret;
 148
 149         ret = i915_gem_check_is_wedged(dev);
 150         if (ret)
 151                 return ret;
 152
 153         ret = mutex_lock_interruptible(&dev->struct_mutex);
 154         if (ret)
 155                 return ret;
 156
 157         if (atomic_read(&dev_priv->mm.wedged)) {
 158                 mutex_unlock(&dev->struct_mutex);
 159                 return -EAGAIN;
 160         }
 161
 162         WARN_ON(i915_verify_lists(dev));
 163         return 0;
 164 }
 165
 166 static inline bool
 167 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
 168 {
 169         return obj_priv->gtt_space &&
 170                 !obj_priv->active &&
 171                 obj_priv->pin_count == 0;
 172 }
 173
 174 int i915_gem_do_init(struct drm_device *dev,
 175                      unsigned long start,
 176                      unsigned long end)
 177 {
 178         drm_i915_private_t *dev_priv = dev->dev_private;
 179
 180         if (start >= end ||
 181             (start & (PAGE_SIZE - 1)) != 0 ||
 182             (end & (PAGE_SIZE - 1)) != 0) {
 183                 return -EINVAL;
 184         }
 185
 186         drm_mm_init(&dev_priv->mm.gtt_space, start,
 187                     end - start);
 188
 189         dev_priv->mm.gtt_total = end - start;
 190
 191         return 0;
 192 }
 193
 194 int
 195 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 196                     struct drm_file *file_priv)
 197 {
 198         struct drm_i915_gem_init *args = data;
 199         int ret;
 200
 201         mutex_lock(&dev->struct_mutex);
 202         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
 203         mutex_unlock(&dev->struct_mutex);
 204
 205         return ret;
 206 }
 207
 208 int
 209 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 210                             struct drm_file *file_priv)
 211 {
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213         struct drm_i915_gem_get_aperture *args = data;
 214
 215         if (!(dev->driver->driver_features & DRIVER_GEM))
 216                 return -ENODEV;
 217
 218         mutex_lock(&dev->struct_mutex);
 219         args->aper_size = dev_priv->mm.gtt_total;
 220         args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory;
 221         mutex_unlock(&dev->struct_mutex);
 222
 223         return 0;
 224 }
 225
 226
 227 /**
 228  * Creates a new mm object and returns a handle to it.
 229  */
 230 int
 231 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 232                       struct drm_file *file_priv)
 233 {
 234         struct drm_i915_gem_create *args = data;
 235         struct drm_gem_object *obj;
 236         int ret;
 237         u32 handle;
 238
 239         args->size = roundup(args->size, PAGE_SIZE);
 240
 241         /* Allocate the new object */
 242         obj = i915_gem_alloc_object(dev, args->size);
 243         if (obj == NULL)
 244                 return -ENOMEM;
 245
 246         ret = drm_gem_handle_create(file_priv, obj, &handle);
 247         if (ret) {
 248                 drm_gem_object_release(obj);
 249                 i915_gem_info_remove_obj(dev->dev_private, obj->size);
 250                 kfree(obj);
 251                 return ret;
 252         }
 253
 254         /* drop reference from allocate - handle holds it now */
 255         drm_gem_object_unreference(obj);
 256         trace_i915_gem_object_create(obj);
 257
 258         args->handle = handle;
 259         return 0;
 260 }
 261
 262 static inline int
 263 fast_shmem_read(struct page **pages,
 264                 loff_t page_base, int page_offset,
 265                 char __user *data,
 266                 int length)
 267 {
 268         char *vaddr;
 269         int ret;
 270
 271         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 272         ret = __copy_to_user_inatomic(data, vaddr + page_offset, length);
 273         kunmap_atomic(vaddr, KM_USER0);
 274
 275         return ret;
 276 }
 277
 278 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
 279 {
 280         drm_i915_private_t *dev_priv = obj->dev->dev_private;
 281         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 282
 283         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 284                 obj_priv->tiling_mode != I915_TILING_NONE;
 285 }
 286
 287 static inline void
 288 slow_shmem_copy(struct page *dst_page,
 289                 int dst_offset,
 290                 struct page *src_page,
 291                 int src_offset,
 292                 int length)
 293 {
 294         char *dst_vaddr, *src_vaddr;
 295
 296         dst_vaddr = kmap(dst_page);
 297         src_vaddr = kmap(src_page);
 298
 299         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 300
 301         kunmap(src_page);
 302         kunmap(dst_page);
 303 }
 304
 305 static inline void
 306 slow_shmem_bit17_copy(struct page *gpu_page,
 307                       int gpu_offset,
 308                       struct page *cpu_page,
 309                       int cpu_offset,
 310                       int length,
 311                       int is_read)
 312 {
 313         char *gpu_vaddr, *cpu_vaddr;
 314
 315         /* Use the unswizzled path if this page isn't affected. */
 316         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 317                 if (is_read)
 318                         return slow_shmem_copy(cpu_page, cpu_offset,
 319                                                gpu_page, gpu_offset, length);
 320                 else
 321                         return slow_shmem_copy(gpu_page, gpu_offset,
 322                                                cpu_page, cpu_offset, length);
 323         }
 324
 325         gpu_vaddr = kmap(gpu_page);
 326         cpu_vaddr = kmap(cpu_page);
 327
 328         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 329          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 330          */
 331         while (length > 0) {
 332                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 333                 int this_length = min(cacheline_end - gpu_offset, length);
 334                 int swizzled_gpu_offset = gpu_offset ^ 64;
 335
 336                 if (is_read) {
 337                         memcpy(cpu_vaddr + cpu_offset,
 338                                gpu_vaddr + swizzled_gpu_offset,
 339                                this_length);
 340                 } else {
 341                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 342                                cpu_vaddr + cpu_offset,
 343                                this_length);
 344                 }
 345                 cpu_offset += this_length;
 346                 gpu_offset += this_length;
 347                 length -= this_length;
 348         }
 349
 350         kunmap(cpu_page);
 351         kunmap(gpu_page);
 352 }
 353
 354 /**
 355  * This is the fast shmem pread path, which attempts to copy_from_user directly
 356  * from the backing pages of the object to the user's address space.  On a
 357  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 358  */
 359 static int
 360 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
 361                           struct drm_i915_gem_pread *args,
 362                           struct drm_file *file_priv)
 363 {
 364         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 365         ssize_t remain;
 366         loff_t offset, page_base;
 367         char __user *user_data;
 368         int page_offset, page_length;
 369
 370         user_data = (char __user *) (uintptr_t) args->data_ptr;
 371         remain = args->size;
 372
 373         obj_priv = to_intel_bo(obj);
 374         offset = args->offset;
 375
 376         while (remain > 0) {
 377                 /* Operation in this page
 378                  *
 379                  * page_base = page offset within aperture
 380                  * page_offset = offset within page
 381                  * page_length = bytes to copy for this page
 382                  */
 383                 page_base = (offset & ~(PAGE_SIZE-1));
 384                 page_offset = offset & (PAGE_SIZE-1);
 385                 page_length = remain;
 386                 if ((page_offset + remain) > PAGE_SIZE)
 387                         page_length = PAGE_SIZE - page_offset;
 388
 389                 if (fast_shmem_read(obj_priv->pages,
 390                                     page_base, page_offset,
 391                                     user_data, page_length))
 392                         return -EFAULT;
 393
 394                 remain -= page_length;
 395                 user_data += page_length;
 396                 offset += page_length;
 397         }
 398
 399         return 0;
 400 }
 401
 402 static int
 403 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
 404 {
 405         int ret;
 406
 407         ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
 408
 409         /* If we've insufficient memory to map in the pages, attempt
 410          * to make some space by throwing out some old buffers.
 411          */
 412         if (ret == -ENOMEM) {
 413                 struct drm_device *dev = obj->dev;
 414
 415                 ret = i915_gem_evict_something(dev, obj->size,
 416                                                i915_gem_get_gtt_alignment(obj));
 417                 if (ret)
 418                         return ret;
 419
 420                 ret = i915_gem_object_get_pages(obj, 0);
 421         }
 422
 423         return ret;
 424 }
 425
 426 /**
 427  * This is the fallback shmem pread path, which allocates temporary storage
 428  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 429  * can copy out of the object's backing pages while holding the struct mutex
 430  * and not take page faults.
 431  */
 432 static int
 433 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
 434                           struct drm_i915_gem_pread *args,
 435                           struct drm_file *file_priv)
 436 {
 437         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 438         struct mm_struct *mm = current->mm;
 439         struct page **user_pages;
 440         ssize_t remain;
 441         loff_t offset, pinned_pages, i;
 442         loff_t first_data_page, last_data_page, num_pages;
 443         int shmem_page_index, shmem_page_offset;
 444         int data_page_index,  data_page_offset;
 445         int page_length;
 446         int ret;
 447         uint64_t data_ptr = args->data_ptr;
 448         int do_bit17_swizzling;
 449
 450         remain = args->size;
 451
 452         /* Pin the user pages containing the data.  We can't fault while
 453          * holding the struct mutex, yet we want to hold it while
 454          * dereferencing the user data.
 455          */
 456         first_data_page = data_ptr / PAGE_SIZE;
 457         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 458         num_pages = last_data_page - first_data_page + 1;
 459
 460         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 461         if (user_pages == NULL)
 462                 return -ENOMEM;
 463
 464         mutex_unlock(&dev->struct_mutex);
 465         down_read(&mm->mmap_sem);
 466         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 467                                       num_pages, 1, 0, user_pages, NULL);
 468         up_read(&mm->mmap_sem);
 469         mutex_lock(&dev->struct_mutex);
 470         if (pinned_pages < num_pages) {
 471                 ret = -EFAULT;
 472                 goto out;
 473         }
 474
 475         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 476                                                         args->offset,
 477                                                         args->size);
 478         if (ret)
 479                 goto out;
 480
 481         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 482
 483         obj_priv = to_intel_bo(obj);
 484         offset = args->offset;
 485
 486         while (remain > 0) {
 487                 /* Operation in this page
 488                  *
 489                  * shmem_page_index = page number within shmem file
 490                  * shmem_page_offset = offset within page in shmem file
 491                  * data_page_index = page number in get_user_pages return
 492                  * data_page_offset = offset with data_page_index page.
 493                  * page_length = bytes to copy for this page
 494                  */
 495                 shmem_page_index = offset / PAGE_SIZE;
 496                 shmem_page_offset = offset & ~PAGE_MASK;
 497                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 498                 data_page_offset = data_ptr & ~PAGE_MASK;
 499
 500                 page_length = remain;
 501                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 502                         page_length = PAGE_SIZE - shmem_page_offset;
 503                 if ((data_page_offset + page_length) > PAGE_SIZE)
 504                         page_length = PAGE_SIZE - data_page_offset;
 505
 506                 if (do_bit17_swizzling) {
 507                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 508                                               shmem_page_offset,
 509                                               user_pages[data_page_index],
 510                                               data_page_offset,
 511                                               page_length,
 512                                               1);
 513                 } else {
 514                         slow_shmem_copy(user_pages[data_page_index],
 515                                         data_page_offset,
 516                                         obj_priv->pages[shmem_page_index],
 517                                         shmem_page_offset,
 518                                         page_length);
 519                 }
 520
 521                 remain -= page_length;
 522                 data_ptr += page_length;
 523                 offset += page_length;
 524         }
 525
 526 out:
 527         for (i = 0; i < pinned_pages; i++) {
 528                 SetPageDirty(user_pages[i]);
 529                 page_cache_release(user_pages[i]);
 530         }
 531         drm_free_large(user_pages);
 532
 533         return ret;
 534 }
 535
 536 /**
 537  * Reads data from the object referenced by handle.
 538  *
 539  * On error, the contents of *data are undefined.
 540  */
 541 int
 542 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 543                      struct drm_file *file_priv)
 544 {
 545         struct drm_i915_gem_pread *args = data;
 546         struct drm_gem_object *obj;
 547         struct drm_i915_gem_object *obj_priv;
 548         int ret = 0;
 549
 550         ret = i915_mutex_lock_interruptible(dev);
 551         if (ret)
 552                 return ret;
 553
 554         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 555         if (obj == NULL) {
 556                 ret = -ENOENT;
 557                 goto unlock;
 558         }
 559         obj_priv = to_intel_bo(obj);
 560
 561         /* Bounds check source.  */
 562         if (args->offset > obj->size || args->size > obj->size - args->offset) {
 563                 ret = -EINVAL;
 564                 goto out;
 565         }
 566
 567         if (args->size == 0)
 568                 goto out;
 569
 570         if (!access_ok(VERIFY_WRITE,
 571                        (char __user *)(uintptr_t)args->data_ptr,
 572                        args->size)) {
 573                 ret = -EFAULT;
 574                 goto out;
 575         }
 576
 577         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 578                                        args->size);
 579         if (ret) {
 580                 ret = -EFAULT;
 581                 goto out;
 582         }
 583
 584         ret = i915_gem_object_get_pages_or_evict(obj);
 585         if (ret)
 586                 goto out;
 587
 588         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 589                                                         args->offset,
 590                                                         args->size);
 591         if (ret)
 592                 goto out_put;
 593
 594         ret = -EFAULT;
 595         if (!i915_gem_object_needs_bit17_swizzle(obj))
 596                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
 597         if (ret == -EFAULT)
 598                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
 599
 600 out_put:
 601         i915_gem_object_put_pages(obj);
 602 out:
 603         drm_gem_object_unreference(obj);
 604 unlock:
 605         mutex_unlock(&dev->struct_mutex);
 606         return ret;
 607 }
 608
 609 /* This is the fast write path which cannot handle
 610  * page faults in the source data
 611  */
 612
 613 static inline int
 614 fast_user_write(struct io_mapping *mapping,
 615                 loff_t page_base, int page_offset,
 616                 char __user *user_data,
 617                 int length)
 618 {
 619         char *vaddr_atomic;
 620         unsigned long unwritten;
 621
 622         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
 623         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 624                                                       user_data, length);
 625         io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
 626         return unwritten;
 627 }
 628
 629 /* Here's the write path which can sleep for
 630  * page faults
 631  */
 632
 633 static inline void
 634 slow_kernel_write(struct io_mapping *mapping,
 635                   loff_t gtt_base, int gtt_offset,
 636                   struct page *user_page, int user_offset,
 637                   int length)
 638 {
 639         char __iomem *dst_vaddr;
 640         char *src_vaddr;
 641
 642         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 643         src_vaddr = kmap(user_page);
 644
 645         memcpy_toio(dst_vaddr + gtt_offset,
 646                     src_vaddr + user_offset,
 647                     length);
 648
 649         kunmap(user_page);
 650         io_mapping_unmap(dst_vaddr);
 651 }
 652
 653 static inline int
 654 fast_shmem_write(struct page **pages,
 655                  loff_t page_base, int page_offset,
 656                  char __user *data,
 657                  int length)
 658 {
 659         char *vaddr;
 660         int ret;
 661
 662         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 663         ret = __copy_from_user_inatomic(vaddr + page_offset, data, length);
 664         kunmap_atomic(vaddr, KM_USER0);
 665
 666         return ret;
 667 }
 668
 669 /**
 670  * This is the fast pwrite path, where we copy the data directly from the
 671  * user into the GTT, uncached.
 672  */
 673 static int
 674 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 675                          struct drm_i915_gem_pwrite *args,
 676                          struct drm_file *file_priv)
 677 {
 678         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 679         drm_i915_private_t *dev_priv = dev->dev_private;
 680         ssize_t remain;
 681         loff_t offset, page_base;
 682         char __user *user_data;
 683         int page_offset, page_length;
 684
 685         user_data = (char __user *) (uintptr_t) args->data_ptr;
 686         remain = args->size;
 687
 688         obj_priv = to_intel_bo(obj);
 689         offset = obj_priv->gtt_offset + args->offset;
 690
 691         while (remain > 0) {
 692                 /* Operation in this page
 693                  *
 694                  * page_base = page offset within aperture
 695                  * page_offset = offset within page
 696                  * page_length = bytes to copy for this page
 697                  */
 698                 page_base = (offset & ~(PAGE_SIZE-1));
 699                 page_offset = offset & (PAGE_SIZE-1);
 700                 page_length = remain;
 701                 if ((page_offset + remain) > PAGE_SIZE)
 702                         page_length = PAGE_SIZE - page_offset;
 703
 704                 /* If we get a fault while copying data, then (presumably) our
 705                  * source page isn't available.  Return the error and we'll
 706                  * retry in the slow path.
 707                  */
 708                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 709                                     page_offset, user_data, page_length))
 710
 711                         return -EFAULT;
 712
 713                 remain -= page_length;
 714                 user_data += page_length;
 715                 offset += page_length;
 716         }
 717
 718         return 0;
 719 }
 720
 721 /**
 722  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 723  * the memory and maps it using kmap_atomic for copying.
 724  *
 725  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 726  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 727  */
 728 static int
 729 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 730                          struct drm_i915_gem_pwrite *args,
 731                          struct drm_file *file_priv)
 732 {
 733         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 734         drm_i915_private_t *dev_priv = dev->dev_private;
 735         ssize_t remain;
 736         loff_t gtt_page_base, offset;
 737         loff_t first_data_page, last_data_page, num_pages;
 738         loff_t pinned_pages, i;
 739         struct page **user_pages;
 740         struct mm_struct *mm = current->mm;
 741         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 742         int ret;
 743         uint64_t data_ptr = args->data_ptr;
 744
 745         remain = args->size;
 746
 747         /* Pin the user pages containing the data.  We can't fault while
 748          * holding the struct mutex, and all of the pwrite implementations
 749          * want to hold it while dereferencing the user data.
 750          */
 751         first_data_page = data_ptr / PAGE_SIZE;
 752         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 753         num_pages = last_data_page - first_data_page + 1;
 754
 755         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 756         if (user_pages == NULL)
 757                 return -ENOMEM;
 758
 759         mutex_unlock(&dev->struct_mutex);
 760         down_read(&mm->mmap_sem);
 761         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 762                                       num_pages, 0, 0, user_pages, NULL);
 763         up_read(&mm->mmap_sem);
 764         mutex_lock(&dev->struct_mutex);
 765         if (pinned_pages < num_pages) {
 766                 ret = -EFAULT;
 767                 goto out_unpin_pages;
 768         }
 769
 770         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 771         if (ret)
 772                 goto out_unpin_pages;
 773
 774         obj_priv = to_intel_bo(obj);
 775         offset = obj_priv->gtt_offset + args->offset;
 776
 777         while (remain > 0) {
 778                 /* Operation in this page
 779                  *
 780                  * gtt_page_base = page offset within aperture
 781                  * gtt_page_offset = offset within page in aperture
 782                  * data_page_index = page number in get_user_pages return
 783                  * data_page_offset = offset with data_page_index page.
 784                  * page_length = bytes to copy for this page
 785                  */
 786                 gtt_page_base = offset & PAGE_MASK;
 787                 gtt_page_offset = offset & ~PAGE_MASK;
 788                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 789                 data_page_offset = data_ptr & ~PAGE_MASK;
 790
 791                 page_length = remain;
 792                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 793                         page_length = PAGE_SIZE - gtt_page_offset;
 794                 if ((data_page_offset + page_length) > PAGE_SIZE)
 795                         page_length = PAGE_SIZE - data_page_offset;
 796
 797                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 798                                   gtt_page_base, gtt_page_offset,
 799                                   user_pages[data_page_index],
 800                                   data_page_offset,
 801                                   page_length);
 802
 803                 remain -= page_length;
 804                 offset += page_length;
 805                 data_ptr += page_length;
 806         }
 807
 808 out_unpin_pages:
 809         for (i = 0; i < pinned_pages; i++)
 810                 page_cache_release(user_pages[i]);
 811         drm_free_large(user_pages);
 812
 813         return ret;
 814 }
 815
 816 /**
 817  * This is the fast shmem pwrite path, which attempts to directly
 818  * copy_from_user into the kmapped pages backing the object.
 819  */
 820 static int
 821 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 822                            struct drm_i915_gem_pwrite *args,
 823                            struct drm_file *file_priv)
 824 {
 825         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 826         ssize_t remain;
 827         loff_t offset, page_base;
 828         char __user *user_data;
 829         int page_offset, page_length;
 830
 831         user_data = (char __user *) (uintptr_t) args->data_ptr;
 832         remain = args->size;
 833
 834         obj_priv = to_intel_bo(obj);
 835         offset = args->offset;
 836         obj_priv->dirty = 1;
 837
 838         while (remain > 0) {
 839                 /* Operation in this page
 840                  *
 841                  * page_base = page offset within aperture
 842                  * page_offset = offset within page
 843                  * page_length = bytes to copy for this page
 844                  */
 845                 page_base = (offset & ~(PAGE_SIZE-1));
 846                 page_offset = offset & (PAGE_SIZE-1);
 847                 page_length = remain;
 848                 if ((page_offset + remain) > PAGE_SIZE)
 849                         page_length = PAGE_SIZE - page_offset;
 850
 851                 if (fast_shmem_write(obj_priv->pages,
 852                                        page_base, page_offset,
 853                                        user_data, page_length))
 854                         return -EFAULT;
 855
 856                 remain -= page_length;
 857                 user_data += page_length;
 858                 offset += page_length;
 859         }
 860
 861         return 0;
 862 }
 863
 864 /**
 865  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 866  * the memory and maps it using kmap_atomic for copying.
 867  *
 868  * This avoids taking mmap_sem for faulting on the user's address while the
 869  * struct_mutex is held.
 870  */
 871 static int
 872 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 873                            struct drm_i915_gem_pwrite *args,
 874                            struct drm_file *file_priv)
 875 {
 876         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 877         struct mm_struct *mm = current->mm;
 878         struct page **user_pages;
 879         ssize_t remain;
 880         loff_t offset, pinned_pages, i;
 881         loff_t first_data_page, last_data_page, num_pages;
 882         int shmem_page_index, shmem_page_offset;
 883         int data_page_index,  data_page_offset;
 884         int page_length;
 885         int ret;
 886         uint64_t data_ptr = args->data_ptr;
 887         int do_bit17_swizzling;
 888
 889         remain = args->size;
 890
 891         /* Pin the user pages containing the data.  We can't fault while
 892          * holding the struct mutex, and all of the pwrite implementations
 893          * want to hold it while dereferencing the user data.
 894          */
 895         first_data_page = data_ptr / PAGE_SIZE;
 896         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 897         num_pages = last_data_page - first_data_page + 1;
 898
 899         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 900         if (user_pages == NULL)
 901                 return -ENOMEM;
 902
 903         mutex_unlock(&dev->struct_mutex);
 904         down_read(&mm->mmap_sem);
 905         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 906                                       num_pages, 0, 0, user_pages, NULL);
 907         up_read(&mm->mmap_sem);
 908         mutex_lock(&dev->struct_mutex);
 909         if (pinned_pages < num_pages) {
 910                 ret = -EFAULT;
 911                 goto out;
 912         }
 913
 914         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 915         if (ret)
 916                 goto out;
 917
 918         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 919
 920         obj_priv = to_intel_bo(obj);
 921         offset = args->offset;
 922         obj_priv->dirty = 1;
 923
 924         while (remain > 0) {
 925                 /* Operation in this page
 926                  *
 927                  * shmem_page_index = page number within shmem file
 928                  * shmem_page_offset = offset within page in shmem file
 929                  * data_page_index = page number in get_user_pages return
 930                  * data_page_offset = offset with data_page_index page.
 931                  * page_length = bytes to copy for this page
 932                  */
 933                 shmem_page_index = offset / PAGE_SIZE;
 934                 shmem_page_offset = offset & ~PAGE_MASK;
 935                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 936                 data_page_offset = data_ptr & ~PAGE_MASK;
 937
 938                 page_length = remain;
 939                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 940                         page_length = PAGE_SIZE - shmem_page_offset;
 941                 if ((data_page_offset + page_length) > PAGE_SIZE)
 942                         page_length = PAGE_SIZE - data_page_offset;
 943
 944                 if (do_bit17_swizzling) {
 945                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 946                                               shmem_page_offset,
 947                                               user_pages[data_page_index],
 948                                               data_page_offset,
 949                                               page_length,
 950                                               0);
 951                 } else {
 952                         slow_shmem_copy(obj_priv->pages[shmem_page_index],
 953                                         shmem_page_offset,
 954                                         user_pages[data_page_index],
 955                                         data_page_offset,
 956                                         page_length);
 957                 }
 958
 959                 remain -= page_length;
 960                 data_ptr += page_length;
 961                 offset += page_length;
 962         }
 963
 964 out:
 965         for (i = 0; i < pinned_pages; i++)
 966                 page_cache_release(user_pages[i]);
 967         drm_free_large(user_pages);
 968
 969         return ret;
 970 }
 971
 972 /**
 973  * Writes data to the object referenced by handle.
 974  *
 975  * On error, the contents of the buffer that were to be modified are undefined.
 976  */
 977 int
 978 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 979                       struct drm_file *file)
 980 {
 981         struct drm_i915_gem_pwrite *args = data;
 982         struct drm_gem_object *obj;
 983         struct drm_i915_gem_object *obj_priv;
 984         int ret = 0;
 985
 986         ret = i915_mutex_lock_interruptible(dev);
 987         if (ret)
 988                 return ret;
 989
 990         obj = drm_gem_object_lookup(dev, file, args->handle);
 991         if (obj == NULL) {
 992                 ret = -ENOENT;
 993                 goto unlock;
 994         }
 995         obj_priv = to_intel_bo(obj);
 996
 997
 998         /* Bounds check destination. */
 999         if (args->offset > obj->size || args->size > obj->size - args->offset) {
1000                 ret = -EINVAL;
1001                 goto out;
1002         }
1003
1004         if (args->size == 0)
1005                 goto out;
1006
1007         if (!access_ok(VERIFY_READ,
1008                        (char __user *)(uintptr_t)args->data_ptr,
1009                        args->size)) {
1010                 ret = -EFAULT;
1011                 goto out;
1012         }
1013
1014         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
1015                                       args->size);
1016         if (ret) {
1017                 ret = -EFAULT;
1018                 goto out;
1019         }
1020
1021         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1022          * it would end up going through the fenced access, and we'll get
1023          * different detiling behavior between reading and writing.
1024          * pread/pwrite currently are reading and writing from the CPU
1025          * perspective, requiring manual detiling by the client.
1026          */
1027         if (obj_priv->phys_obj)
1028                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1029         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
1030                  obj_priv->gtt_space &&
1031                  obj->write_domain != I915_GEM_DOMAIN_CPU) {
1032                 ret = i915_gem_object_pin(obj, 0);
1033                 if (ret)
1034                         goto out;
1035
1036                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1037                 if (ret)
1038                         goto out_unpin;
1039
1040                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1041                 if (ret == -EFAULT)
1042                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1043
1044 out_unpin:
1045                 i915_gem_object_unpin(obj);
1046         } else {
1047                 ret = i915_gem_object_get_pages_or_evict(obj);
1048                 if (ret)
1049                         goto out;
1050
1051                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1052                 if (ret)
1053                         goto out_put;
1054
1055                 ret = -EFAULT;
1056                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1057                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1058                 if (ret == -EFAULT)
1059                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1060
1061 out_put:
1062                 i915_gem_object_put_pages(obj);
1063         }
1064
1065 out:
1066         drm_gem_object_unreference(obj);
1067 unlock:
1068         mutex_unlock(&dev->struct_mutex);
1069         return ret;
1070 }
1071
1072 /**
1073  * Called when user space prepares to use an object with the CPU, either
1074  * through the mmap ioctl's mapping or a GTT mapping.
1075  */
1076 int
1077 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1078                           struct drm_file *file_priv)
1079 {
1080         struct drm_i915_private *dev_priv = dev->dev_private;
1081         struct drm_i915_gem_set_domain *args = data;
1082         struct drm_gem_object *obj;
1083         struct drm_i915_gem_object *obj_priv;
1084         uint32_t read_domains = args->read_domains;
1085         uint32_t write_domain = args->write_domain;
1086         int ret;
1087
1088         if (!(dev->driver->driver_features & DRIVER_GEM))
1089                 return -ENODEV;
1090
1091         /* Only handle setting domains to types used by the CPU. */
1092         if (write_domain & I915_GEM_GPU_DOMAINS)
1093                 return -EINVAL;
1094
1095         if (read_domains & I915_GEM_GPU_DOMAINS)
1096                 return -EINVAL;
1097
1098         /* Having something in the write domain implies it's in the read
1099          * domain, and only that read domain.  Enforce that in the request.
1100          */
1101         if (write_domain != 0 && read_domains != write_domain)
1102                 return -EINVAL;
1103
1104         ret = i915_mutex_lock_interruptible(dev);
1105         if (ret)
1106                 return ret;
1107
1108         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1109         if (obj == NULL) {
1110                 ret = -ENOENT;
1111                 goto unlock;
1112         }
1113         obj_priv = to_intel_bo(obj);
1114
1115         intel_mark_busy(dev, obj);
1116
1117         if (read_domains & I915_GEM_DOMAIN_GTT) {
1118                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1119
1120                 /* Update the LRU on the fence for the CPU access that's
1121                  * about to occur.
1122                  */
1123                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1124                         struct drm_i915_fence_reg *reg =
1125                                 &dev_priv->fence_regs[obj_priv->fence_reg];
1126                         list_move_tail(&reg->lru_list,
1127                                        &dev_priv->mm.fence_list);
1128                 }
1129
1130                 /* Silently promote "you're not bound, there was nothing to do"
1131                  * to success, since the client was just asking us to
1132                  * make sure everything was done.
1133                  */
1134                 if (ret == -EINVAL)
1135                         ret = 0;
1136         } else {
1137                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1138         }
1139
1140         /* Maintain LRU order of "inactive" objects */
1141         if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1142                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1143
1144         drm_gem_object_unreference(obj);
1145 unlock:
1146         mutex_unlock(&dev->struct_mutex);
1147         return ret;
1148 }
1149
1150 /**
1151  * Called when user space has done writes to this buffer
1152  */
1153 int
1154 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1155                       struct drm_file *file_priv)
1156 {
1157         struct drm_i915_gem_sw_finish *args = data;
1158         struct drm_gem_object *obj;
1159         int ret = 0;
1160
1161         if (!(dev->driver->driver_features & DRIVER_GEM))
1162                 return -ENODEV;
1163
1164         ret = i915_mutex_lock_interruptible(dev);
1165         if (ret)
1166                 return ret;
1167
1168         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1169         if (obj == NULL) {
1170                 ret = -ENOENT;
1171                 goto unlock;
1172         }
1173
1174         /* Pinned buffers may be scanout, so flush the cache */
1175         if (to_intel_bo(obj)->pin_count)
1176                 i915_gem_object_flush_cpu_write_domain(obj);
1177
1178         drm_gem_object_unreference(obj);
1179 unlock:
1180         mutex_unlock(&dev->struct_mutex);
1181         return ret;
1182 }
1183
1184 /**
1185  * Maps the contents of an object, returning the address it is mapped
1186  * into.
1187  *
1188  * While the mapping holds a reference on the contents of the object, it doesn't
1189  * imply a ref on the object itself.
1190  */
1191 int
1192 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1193                    struct drm_file *file_priv)
1194 {
1195         struct drm_i915_gem_mmap *args = data;
1196         struct drm_gem_object *obj;
1197         loff_t offset;
1198         unsigned long addr;
1199
1200         if (!(dev->driver->driver_features & DRIVER_GEM))
1201                 return -ENODEV;
1202
1203         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1204         if (obj == NULL)
1205                 return -ENOENT;
1206
1207         offset = args->offset;
1208
1209         down_write(&current->mm->mmap_sem);
1210         addr = do_mmap(obj->filp, 0, args->size,
1211                        PROT_READ | PROT_WRITE, MAP_SHARED,
1212                        args->offset);
1213         up_write(&current->mm->mmap_sem);
1214         drm_gem_object_unreference_unlocked(obj);
1215         if (IS_ERR((void *)addr))
1216                 return addr;
1217
1218         args->addr_ptr = (uint64_t) addr;
1219
1220         return 0;
1221 }
1222
1223 /**
1224  * i915_gem_fault - fault a page into the GTT
1225  * vma: VMA in question
1226  * vmf: fault info
1227  *
1228  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1229  * from userspace.  The fault handler takes care of binding the object to
1230  * the GTT (if needed), allocating and programming a fence register (again,
1231  * only if needed based on whether the old reg is still valid or the object
1232  * is tiled) and inserting a new PTE into the faulting process.
1233  *
1234  * Note that the faulting process may involve evicting existing objects
1235  * from the GTT and/or fence registers to make room.  So performance may
1236  * suffer if the GTT working set is large or there are few fence registers
1237  * left.
1238  */
1239 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1240 {
1241         struct drm_gem_object *obj = vma->vm_private_data;
1242         struct drm_device *dev = obj->dev;
1243         drm_i915_private_t *dev_priv = dev->dev_private;
1244         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1245         pgoff_t page_offset;
1246         unsigned long pfn;
1247         int ret = 0;
1248         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1249
1250         /* We don't use vmf->pgoff since that has the fake offset */
1251         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1252                 PAGE_SHIFT;
1253
1254         /* Now bind it into the GTT if needed */
1255         mutex_lock(&dev->struct_mutex);
1256         if (!obj_priv->gtt_space) {
1257                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1258                 if (ret)
1259                         goto unlock;
1260
1261                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1262                 if (ret)
1263                         goto unlock;
1264         }
1265
1266         /* Need a new fence register? */
1267         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1268                 ret = i915_gem_object_get_fence_reg(obj, true);
1269                 if (ret)
1270                         goto unlock;
1271         }
1272
1273         if (i915_gem_object_is_inactive(obj_priv))
1274                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1275
1276         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1277                 page_offset;
1278
1279         /* Finally, remap it using the new GTT offset */
1280         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1281 unlock:
1282         mutex_unlock(&dev->struct_mutex);
1283
1284         switch (ret) {
1285         case 0:
1286         case -ERESTARTSYS:
1287                 return VM_FAULT_NOPAGE;
1288         case -ENOMEM:
1289         case -EAGAIN:
1290                 return VM_FAULT_OOM;
1291         default:
1292                 return VM_FAULT_SIGBUS;
1293         }
1294 }
1295
1296 /**
1297  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1298  * @obj: obj in question
1299  *
1300  * GEM memory mapping works by handing back to userspace a fake mmap offset
1301  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1302  * up the object based on the offset and sets up the various memory mapping
1303  * structures.
1304  *
1305  * This routine allocates and attaches a fake offset for @obj.
1306  */
1307 static int
1308 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1309 {
1310         struct drm_device *dev = obj->dev;
1311         struct drm_gem_mm *mm = dev->mm_private;
1312         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1313         struct drm_map_list *list;
1314         struct drm_local_map *map;
1315         int ret = 0;
1316
1317         /* Set the object up for mmap'ing */
1318         list = &obj->map_list;
1319         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1320         if (!list->map)
1321                 return -ENOMEM;
1322
1323         map = list->map;
1324         map->type = _DRM_GEM;
1325         map->size = obj->size;
1326         map->handle = obj;
1327
1328         /* Get a DRM GEM mmap offset allocated... */
1329         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1330                                                     obj->size / PAGE_SIZE, 0, 0);
1331         if (!list->file_offset_node) {
1332                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1333                 ret = -ENOSPC;
1334                 goto out_free_list;
1335         }
1336
1337         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1338                                                   obj->size / PAGE_SIZE, 0);
1339         if (!list->file_offset_node) {
1340                 ret = -ENOMEM;
1341                 goto out_free_list;
1342         }
1343
1344         list->hash.key = list->file_offset_node->start;
1345         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1346         if (ret) {
1347                 DRM_ERROR("failed to add to map hash\n");
1348                 goto out_free_mm;
1349         }
1350
1351         /* By now we should be all set, any drm_mmap request on the offset
1352          * below will get to our mmap & fault handler */
1353         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1354
1355         return 0;
1356
1357 out_free_mm:
1358         drm_mm_put_block(list->file_offset_node);
1359 out_free_list:
1360         kfree(list->map);
1361
1362         return ret;
1363 }
1364
1365 /**
1366  * i915_gem_release_mmap - remove physical page mappings
1367  * @obj: obj in question
1368  *
1369  * Preserve the reservation of the mmapping with the DRM core code, but
1370  * relinquish ownership of the pages back to the system.
1371  *
1372  * It is vital that we remove the page mapping if we have mapped a tiled
1373  * object through the GTT and then lose the fence register due to
1374  * resource pressure. Similarly if the object has been moved out of the
1375  * aperture, than pages mapped into userspace must be revoked. Removing the
1376  * mapping will then trigger a page fault on the next user access, allowing
1377  * fixup by i915_gem_fault().
1378  */
1379 void
1380 i915_gem_release_mmap(struct drm_gem_object *obj)
1381 {
1382         struct drm_device *dev = obj->dev;
1383         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1384
1385         if (dev->dev_mapping)
1386                 unmap_mapping_range(dev->dev_mapping,
1387                                     obj_priv->mmap_offset, obj->size, 1);
1388 }
1389
1390 static void
1391 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1392 {
1393         struct drm_device *dev = obj->dev;
1394         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1395         struct drm_gem_mm *mm = dev->mm_private;
1396         struct drm_map_list *list;
1397
1398         list = &obj->map_list;
1399         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1400
1401         if (list->file_offset_node) {
1402                 drm_mm_put_block(list->file_offset_node);
1403                 list->file_offset_node = NULL;
1404         }
1405
1406         if (list->map) {
1407                 kfree(list->map);
1408                 list->map = NULL;
1409         }
1410
1411         obj_priv->mmap_offset = 0;
1412 }
1413
1414 /**
1415  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1416  * @obj: object to check
1417  *
1418  * Return the required GTT alignment for an object, taking into account
1419  * potential fence register mapping if needed.
1420  */
1421 static uint32_t
1422 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1423 {
1424         struct drm_device *dev = obj->dev;
1425         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1426         int start, i;
1427
1428         /*
1429          * Minimum alignment is 4k (GTT page size), but might be greater
1430          * if a fence register is needed for the object.
1431          */
1432         if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE)
1433                 return 4096;
1434
1435         /*
1436          * Previous chips need to be aligned to the size of the smallest
1437          * fence register that can contain the object.
1438          */
1439         if (INTEL_INFO(dev)->gen == 3)
1440                 start = 1024*1024;
1441         else
1442                 start = 512*1024;
1443
1444         for (i = start; i < obj->size; i <<= 1)
1445                 ;
1446
1447         return i;
1448 }
1449
1450 /**
1451  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1452  * @dev: DRM device
1453  * @data: GTT mapping ioctl data
1454  * @file_priv: GEM object info
1455  *
1456  * Simply returns the fake offset to userspace so it can mmap it.
1457  * The mmap call will end up in drm_gem_mmap(), which will set things
1458  * up so we can get faults in the handler above.
1459  *
1460  * The fault handler will take care of binding the object into the GTT
1461  * (since it may have been evicted to make room for something), allocating
1462  * a fence register, and mapping the appropriate aperture address into
1463  * userspace.
1464  */
1465 int
1466 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1467                         struct drm_file *file_priv)
1468 {
1469         struct drm_i915_gem_mmap_gtt *args = data;
1470         struct drm_gem_object *obj;
1471         struct drm_i915_gem_object *obj_priv;
1472         int ret;
1473
1474         if (!(dev->driver->driver_features & DRIVER_GEM))
1475                 return -ENODEV;
1476
1477         ret = i915_mutex_lock_interruptible(dev);
1478         if (ret)
1479                 return ret;
1480
1481         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1482         if (obj == NULL) {
1483                 ret = -ENOENT;
1484                 goto unlock;
1485         }
1486         obj_priv = to_intel_bo(obj);
1487
1488         if (obj_priv->madv != I915_MADV_WILLNEED) {
1489                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1490                 ret = -EINVAL;
1491                 goto out;
1492         }
1493
1494         if (!obj_priv->mmap_offset) {
1495                 ret = i915_gem_create_mmap_offset(obj);
1496                 if (ret)
1497                         goto out;
1498         }
1499
1500         args->offset = obj_priv->mmap_offset;
1501
1502         /*
1503          * Pull it into the GTT so that we have a page list (makes the
1504          * initial fault faster and any subsequent flushing possible).
1505          */
1506         if (!obj_priv->agp_mem) {
1507                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1508                 if (ret)
1509                         goto out;
1510         }
1511
1512 out:
1513         drm_gem_object_unreference(obj);
1514 unlock:
1515         mutex_unlock(&dev->struct_mutex);
1516         return ret;
1517 }
1518
1519 static void
1520 i915_gem_object_put_pages(struct drm_gem_object *obj)
1521 {
1522         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1523         int page_count = obj->size / PAGE_SIZE;
1524         int i;
1525
1526         BUG_ON(obj_priv->pages_refcount == 0);
1527         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1528
1529         if (--obj_priv->pages_refcount != 0)
1530                 return;
1531
1532         if (obj_priv->tiling_mode != I915_TILING_NONE)
1533                 i915_gem_object_save_bit_17_swizzle(obj);
1534
1535         if (obj_priv->madv == I915_MADV_DONTNEED)
1536                 obj_priv->dirty = 0;
1537
1538         for (i = 0; i < page_count; i++) {
1539                 if (obj_priv->dirty)
1540                         set_page_dirty(obj_priv->pages[i]);
1541
1542                 if (obj_priv->madv == I915_MADV_WILLNEED)
1543                         mark_page_accessed(obj_priv->pages[i]);
1544
1545                 page_cache_release(obj_priv->pages[i]);
1546         }
1547         obj_priv->dirty = 0;
1548
1549         drm_free_large(obj_priv->pages);
1550         obj_priv->pages = NULL;
1551 }
1552
1553 static uint32_t
1554 i915_gem_next_request_seqno(struct drm_device *dev,
1555                             struct intel_ring_buffer *ring)
1556 {
1557         drm_i915_private_t *dev_priv = dev->dev_private;
1558
1559         ring->outstanding_lazy_request = true;
1560         return dev_priv->next_seqno;
1561 }
1562
1563 static void
1564 i915_gem_object_move_to_active(struct drm_gem_object *obj,
1565                                struct intel_ring_buffer *ring)
1566 {
1567         struct drm_device *dev = obj->dev;
1568         struct drm_i915_private *dev_priv = dev->dev_private;
1569         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1570         uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
1571
1572         BUG_ON(ring == NULL);
1573         obj_priv->ring = ring;
1574
1575         /* Add a reference if we're newly entering the active list. */
1576         if (!obj_priv->active) {
1577                 drm_gem_object_reference(obj);
1578                 obj_priv->active = 1;
1579         }
1580
1581         /* Move from whatever list we were on to the tail of execution. */
1582         list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list);
1583         list_move_tail(&obj_priv->ring_list, &ring->active_list);
1584         obj_priv->last_rendering_seqno = seqno;
1585 }
1586
1587 static void
1588 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1589 {
1590         struct drm_device *dev = obj->dev;
1591         drm_i915_private_t *dev_priv = dev->dev_private;
1592         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1593
1594         BUG_ON(!obj_priv->active);
1595         list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list);
1596         list_del_init(&obj_priv->ring_list);
1597         obj_priv->last_rendering_seqno = 0;
1598 }
1599
1600 /* Immediately discard the backing storage */
1601 static void
1602 i915_gem_object_truncate(struct drm_gem_object *obj)
1603 {
1604         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1605         struct inode *inode;
1606
1607         /* Our goal here is to return as much of the memory as
1608          * is possible back to the system as we are called from OOM.
1609          * To do this we must instruct the shmfs to drop all of its
1610          * backing pages, *now*. Here we mirror the actions taken
1611          * when by shmem_delete_inode() to release the backing store.
1612          */
1613         inode = obj->filp->f_path.dentry->d_inode;
1614         truncate_inode_pages(inode->i_mapping, 0);
1615         if (inode->i_op->truncate_range)
1616                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1617
1618         obj_priv->madv = __I915_MADV_PURGED;
1619 }
1620
1621 static inline int
1622 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1623 {
1624         return obj_priv->madv == I915_MADV_DONTNEED;
1625 }
1626
1627 static void
1628 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1629 {
1630         struct drm_device *dev = obj->dev;
1631         drm_i915_private_t *dev_priv = dev->dev_private;
1632         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1633
1634         if (obj_priv->pin_count != 0)
1635                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list);
1636         else
1637                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1638         list_del_init(&obj_priv->ring_list);
1639
1640         BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1641
1642         obj_priv->last_rendering_seqno = 0;
1643         obj_priv->ring = NULL;
1644         if (obj_priv->active) {
1645                 obj_priv->active = 0;
1646                 drm_gem_object_unreference(obj);
1647         }
1648         WARN_ON(i915_verify_lists(dev));
1649 }
1650
1651 static void
1652 i915_gem_process_flushing_list(struct drm_device *dev,
1653                                uint32_t flush_domains,
1654                                struct intel_ring_buffer *ring)
1655 {
1656         drm_i915_private_t *dev_priv = dev->dev_private;
1657         struct drm_i915_gem_object *obj_priv, *next;
1658
1659         list_for_each_entry_safe(obj_priv, next,
1660                                  &dev_priv->mm.gpu_write_list,
1661                                  gpu_write_list) {
1662                 struct drm_gem_object *obj = &obj_priv->base;
1663
1664                 if (obj->write_domain & flush_domains &&
1665                     obj_priv->ring == ring) {
1666                         uint32_t old_write_domain = obj->write_domain;
1667
1668                         obj->write_domain = 0;
1669                         list_del_init(&obj_priv->gpu_write_list);
1670                         i915_gem_object_move_to_active(obj, ring);
1671
1672                         /* update the fence lru list */
1673                         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1674                                 struct drm_i915_fence_reg *reg =
1675                                         &dev_priv->fence_regs[obj_priv->fence_reg];
1676                                 list_move_tail(&reg->lru_list,
1677                                                 &dev_priv->mm.fence_list);
1678                         }
1679
1680                         trace_i915_gem_object_change_domain(obj,
1681                                                             obj->read_domains,
1682                                                             old_write_domain);
1683                 }
1684         }
1685 }
1686
1687 uint32_t
1688 i915_add_request(struct drm_device *dev,
1689                  struct drm_file *file,
1690                  struct drm_i915_gem_request *request,
1691                  struct intel_ring_buffer *ring)
1692 {
1693         drm_i915_private_t *dev_priv = dev->dev_private;
1694         struct drm_i915_file_private *file_priv = NULL;
1695         uint32_t seqno;
1696         int was_empty;
1697
1698         if (file != NULL)
1699                 file_priv = file->driver_priv;
1700
1701         if (request == NULL) {
1702                 request = kzalloc(sizeof(*request), GFP_KERNEL);
1703                 if (request == NULL)
1704                         return 0;
1705         }
1706
1707         seqno = ring->add_request(dev, ring, 0);
1708         ring->outstanding_lazy_request = false;
1709
1710         request->seqno = seqno;
1711         request->ring = ring;
1712         request->emitted_jiffies = jiffies;
1713         was_empty = list_empty(&ring->request_list);
1714         list_add_tail(&request->list, &ring->request_list);
1715
1716         if (file_priv) {
1717                 spin_lock(&file_priv->mm.lock);
1718                 request->file_priv = file_priv;
1719                 list_add_tail(&request->client_list,
1720                               &file_priv->mm.request_list);
1721                 spin_unlock(&file_priv->mm.lock);
1722         }
1723
1724         if (!dev_priv->mm.suspended) {
1725                 mod_timer(&dev_priv->hangcheck_timer,
1726                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1727                 if (was_empty)
1728                         queue_delayed_work(dev_priv->wq,
1729                                            &dev_priv->mm.retire_work, HZ);
1730         }
1731         return seqno;
1732 }
1733
1734 /**
1735  * Command execution barrier
1736  *
1737  * Ensures that all commands in the ring are finished
1738  * before signalling the CPU
1739  */
1740 static void
1741 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1742 {
1743         uint32_t flush_domains = 0;
1744
1745         /* The sampler always gets flushed on i965 (sigh) */
1746         if (INTEL_INFO(dev)->gen >= 4)
1747                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1748
1749         ring->flush(dev, ring,
1750                         I915_GEM_DOMAIN_COMMAND, flush_domains);
1751 }
1752
1753 static inline void
1754 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1755 {
1756         struct drm_i915_file_private *file_priv = request->file_priv;
1757
1758         if (!file_priv)
1759                 return;
1760
1761         spin_lock(&file_priv->mm.lock);
1762         list_del(&request->client_list);
1763         request->file_priv = NULL;
1764         spin_unlock(&file_priv->mm.lock);
1765 }
1766
1767 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1768                                       struct intel_ring_buffer *ring)
1769 {
1770         while (!list_empty(&ring->request_list)) {
1771                 struct drm_i915_gem_request *request;
1772
1773                 request = list_first_entry(&ring->request_list,
1774                                            struct drm_i915_gem_request,
1775                                            list);
1776
1777                 list_del(&request->list);
1778                 i915_gem_request_remove_from_client(request);
1779                 kfree(request);
1780         }
1781
1782         while (!list_empty(&ring->active_list)) {
1783                 struct drm_i915_gem_object *obj_priv;
1784
1785                 obj_priv = list_first_entry(&ring->active_list,
1786                                             struct drm_i915_gem_object,
1787                                             ring_list);
1788
1789                 obj_priv->base.write_domain = 0;
1790                 list_del_init(&obj_priv->gpu_write_list);
1791                 i915_gem_object_move_to_inactive(&obj_priv->base);
1792         }
1793 }
1794
1795 void i915_gem_reset(struct drm_device *dev)
1796 {
1797         struct drm_i915_private *dev_priv = dev->dev_private;
1798         struct drm_i915_gem_object *obj_priv;
1799         int i;
1800
1801         i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring);
1802         i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring);
1803
1804         /* Remove anything from the flushing lists. The GPU cache is likely
1805          * to be lost on reset along with the data, so simply move the
1806          * lost bo to the inactive list.
1807          */
1808         while (!list_empty(&dev_priv->mm.flushing_list)) {
1809                 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1810                                             struct drm_i915_gem_object,
1811                                             mm_list);
1812
1813                 obj_priv->base.write_domain = 0;
1814                 list_del_init(&obj_priv->gpu_write_list);
1815                 i915_gem_object_move_to_inactive(&obj_priv->base);
1816         }
1817
1818         /* Move everything out of the GPU domains to ensure we do any
1819          * necessary invalidation upon reuse.
1820          */
1821         list_for_each_entry(obj_priv,
1822                             &dev_priv->mm.inactive_list,
1823                             mm_list)
1824         {
1825                 obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1826         }
1827
1828         /* The fence registers are invalidated so clear them out */
1829         for (i = 0; i < 16; i++) {
1830                 struct drm_i915_fence_reg *reg;
1831
1832                 reg = &dev_priv->fence_regs[i];
1833                 if (!reg->obj)
1834                         continue;
1835
1836                 i915_gem_clear_fence_reg(reg->obj);
1837         }
1838 }
1839
1840 /**
1841  * This function clears the request list as sequence numbers are passed.
1842  */
1843 static void
1844 i915_gem_retire_requests_ring(struct drm_device *dev,
1845                               struct intel_ring_buffer *ring)
1846 {
1847         drm_i915_private_t *dev_priv = dev->dev_private;
1848         uint32_t seqno;
1849
1850         if (!ring->status_page.page_addr ||
1851             list_empty(&ring->request_list))
1852                 return;
1853
1854         WARN_ON(i915_verify_lists(dev));
1855
1856         seqno = ring->get_seqno(dev, ring);
1857         while (!list_empty(&ring->request_list)) {
1858                 struct drm_i915_gem_request *request;
1859
1860                 request = list_first_entry(&ring->request_list,
1861                                            struct drm_i915_gem_request,
1862                                            list);
1863
1864                 if (!i915_seqno_passed(seqno, request->seqno))
1865                         break;
1866
1867                 trace_i915_gem_request_retire(dev, request->seqno);
1868
1869                 list_del(&request->list);
1870                 i915_gem_request_remove_from_client(request);
1871                 kfree(request);
1872         }
1873
1874         /* Move any buffers on the active list that are no longer referenced
1875          * by the ringbuffer to the flushing/inactive lists as appropriate.
1876          */
1877         while (!list_empty(&ring->active_list)) {
1878                 struct drm_gem_object *obj;
1879                 struct drm_i915_gem_object *obj_priv;
1880
1881                 obj_priv = list_first_entry(&ring->active_list,
1882                                             struct drm_i915_gem_object,
1883                                             ring_list);
1884
1885                 if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno))
1886                         break;
1887
1888                 obj = &obj_priv->base;
1889                 if (obj->write_domain != 0)
1890                         i915_gem_object_move_to_flushing(obj);
1891                 else
1892                         i915_gem_object_move_to_inactive(obj);
1893         }
1894
1895         if (unlikely (dev_priv->trace_irq_seqno &&
1896                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1897                 ring->user_irq_put(dev, ring);
1898                 dev_priv->trace_irq_seqno = 0;
1899         }
1900
1901         WARN_ON(i915_verify_lists(dev));
1902 }
1903
1904 void
1905 i915_gem_retire_requests(struct drm_device *dev)
1906 {
1907         drm_i915_private_t *dev_priv = dev->dev_private;
1908
1909         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1910             struct drm_i915_gem_object *obj_priv, *tmp;
1911
1912             /* We must be careful that during unbind() we do not
1913              * accidentally infinitely recurse into retire requests.
1914              * Currently:
1915              *   retire -> free -> unbind -> wait -> retire_ring
1916              */
1917             list_for_each_entry_safe(obj_priv, tmp,
1918                                      &dev_priv->mm.deferred_free_list,
1919                                      mm_list)
1920                     i915_gem_free_object_tail(&obj_priv->base);
1921         }
1922
1923         i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1924         i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1925 }
1926
1927 static void
1928 i915_gem_retire_work_handler(struct work_struct *work)
1929 {
1930         drm_i915_private_t *dev_priv;
1931         struct drm_device *dev;
1932
1933         dev_priv = container_of(work, drm_i915_private_t,
1934                                 mm.retire_work.work);
1935         dev = dev_priv->dev;
1936
1937         /* Come back later if the device is busy... */
1938         if (!mutex_trylock(&dev->struct_mutex)) {
1939                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1940                 return;
1941         }
1942
1943         i915_gem_retire_requests(dev);
1944
1945         if (!dev_priv->mm.suspended &&
1946                 (!list_empty(&dev_priv->render_ring.request_list) ||
1947                  !list_empty(&dev_priv->bsd_ring.request_list)))
1948                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1949         mutex_unlock(&dev->struct_mutex);
1950 }
1951
1952 int
1953 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1954                      bool interruptible, struct intel_ring_buffer *ring)
1955 {
1956         drm_i915_private_t *dev_priv = dev->dev_private;
1957         u32 ier;
1958         int ret = 0;
1959
1960         BUG_ON(seqno == 0);
1961
1962         if (atomic_read(&dev_priv->mm.wedged))
1963                 return -EAGAIN;
1964
1965         if (ring->outstanding_lazy_request) {
1966                 seqno = i915_add_request(dev, NULL, NULL, ring);
1967                 if (seqno == 0)
1968                         return -ENOMEM;
1969         }
1970         BUG_ON(seqno == dev_priv->next_seqno);
1971
1972         if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) {
1973                 if (HAS_PCH_SPLIT(dev))
1974                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1975                 else
1976                         ier = I915_READ(IER);
1977                 if (!ier) {
1978                         DRM_ERROR("something (likely vbetool) disabled "
1979                                   "interrupts, re-enabling\n");
1980                         i915_driver_irq_preinstall(dev);
1981                         i915_driver_irq_postinstall(dev);
1982                 }
1983
1984                 trace_i915_gem_request_wait_begin(dev, seqno);
1985
1986                 ring->waiting_gem_seqno = seqno;
1987                 ring->user_irq_get(dev, ring);
1988                 if (interruptible)
1989                         ret = wait_event_interruptible(ring->irq_queue,
1990                                 i915_seqno_passed(
1991                                         ring->get_seqno(dev, ring), seqno)
1992                                 || atomic_read(&dev_priv->mm.wedged));
1993                 else
1994                         wait_event(ring->irq_queue,
1995                                 i915_seqno_passed(
1996                                         ring->get_seqno(dev, ring), seqno)
1997                                 || atomic_read(&dev_priv->mm.wedged));
1998
1999                 ring->user_irq_put(dev, ring);
2000                 ring->waiting_gem_seqno = 0;
2001
2002                 trace_i915_gem_request_wait_end(dev, seqno);
2003         }
2004         if (atomic_read(&dev_priv->mm.wedged))
2005                 ret = -EAGAIN;
2006
2007         if (ret && ret != -ERESTARTSYS)
2008                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2009                           __func__, ret, seqno, ring->get_seqno(dev, ring),
2010                           dev_priv->next_seqno);
2011
2012         /* Directly dispatch request retiring.  While we have the work queue
2013          * to handle this, the waiter on a request often wants an associated
2014          * buffer to have made it to the inactive list, and we would need
2015          * a separate wait queue to handle that.
2016          */
2017         if (ret == 0)
2018                 i915_gem_retire_requests_ring(dev, ring);
2019
2020         return ret;
2021 }
2022
2023 /**
2024  * Waits for a sequence number to be signaled, and cleans up the
2025  * request and object lists appropriately for that event.
2026  */
2027 static int
2028 i915_wait_request(struct drm_device *dev, uint32_t seqno,
2029                   struct intel_ring_buffer *ring)
2030 {
2031         return i915_do_wait_request(dev, seqno, 1, ring);
2032 }
2033
2034 static void
2035 i915_gem_flush_ring(struct drm_device *dev,
2036                     struct drm_file *file_priv,
2037                     struct intel_ring_buffer *ring,
2038                     uint32_t invalidate_domains,
2039                     uint32_t flush_domains)
2040 {
2041         ring->flush(dev, ring, invalidate_domains, flush_domains);
2042         i915_gem_process_flushing_list(dev, flush_domains, ring);
2043 }
2044
2045 static void
2046 i915_gem_flush(struct drm_device *dev,
2047                struct drm_file *file_priv,
2048                uint32_t invalidate_domains,
2049                uint32_t flush_domains,
2050                uint32_t flush_rings)
2051 {
2052         drm_i915_private_t *dev_priv = dev->dev_private;
2053
2054         if (flush_domains & I915_GEM_DOMAIN_CPU)
2055                 drm_agp_chipset_flush(dev);
2056
2057         if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
2058                 if (flush_rings & RING_RENDER)
2059                         i915_gem_flush_ring(dev, file_priv,
2060                                             &dev_priv->render_ring,
2061                                             invalidate_domains, flush_domains);
2062                 if (flush_rings & RING_BSD)
2063                         i915_gem_flush_ring(dev, file_priv,
2064                                             &dev_priv->bsd_ring,
2065                                             invalidate_domains, flush_domains);
2066         }
2067 }
2068
2069 /**
2070  * Ensures that all rendering to the object has completed and the object is
2071  * safe to unbind from the GTT or access from the CPU.
2072  */
2073 static int
2074 i915_gem_object_wait_rendering(struct drm_gem_object *obj,
2075                                bool interruptible)
2076 {
2077         struct drm_device *dev = obj->dev;
2078         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2079         int ret;
2080
2081         /* This function only exists to support waiting for existing rendering,
2082          * not for emitting required flushes.
2083          */
2084         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
2085
2086         /* If there is rendering queued on the buffer being evicted, wait for
2087          * it.
2088          */
2089         if (obj_priv->active) {
2090                 ret = i915_do_wait_request(dev,
2091                                            obj_priv->last_rendering_seqno,
2092                                            interruptible,
2093                                            obj_priv->ring);
2094                 if (ret)
2095                         return ret;
2096         }
2097
2098         return 0;
2099 }
2100
2101 /**
2102  * Unbinds an object from the GTT aperture.
2103  */
2104 int
2105 i915_gem_object_unbind(struct drm_gem_object *obj)
2106 {
2107         struct drm_device *dev = obj->dev;
2108         struct drm_i915_private *dev_priv = dev->dev_private;
2109         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2110         int ret = 0;
2111
2112         if (obj_priv->gtt_space == NULL)
2113                 return 0;
2114
2115         if (obj_priv->pin_count != 0) {
2116                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2117                 return -EINVAL;
2118         }
2119
2120         /* blow away mappings if mapped through GTT */
2121         i915_gem_release_mmap(obj);
2122
2123         /* Move the object to the CPU domain to ensure that
2124          * any possible CPU writes while it's not in the GTT
2125          * are flushed when we go to remap it. This will
2126          * also ensure that all pending GPU writes are finished
2127          * before we unbind.
2128          */
2129         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2130         if (ret == -ERESTARTSYS)
2131                 return ret;
2132         /* Continue on if we fail due to EIO, the GPU is hung so we
2133          * should be safe and we need to cleanup or else we might
2134          * cause memory corruption through use-after-free.
2135          */
2136         if (ret) {
2137                 i915_gem_clflush_object(obj);
2138                 obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU;
2139         }
2140
2141         /* release the fence reg _after_ flushing */
2142         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2143                 i915_gem_clear_fence_reg(obj);
2144
2145         drm_unbind_agp(obj_priv->agp_mem);
2146         drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2147
2148         i915_gem_object_put_pages(obj);
2149         BUG_ON(obj_priv->pages_refcount);
2150
2151         i915_gem_info_remove_gtt(dev_priv, obj->size);
2152         list_del_init(&obj_priv->mm_list);
2153
2154         drm_mm_put_block(obj_priv->gtt_space);
2155         obj_priv->gtt_space = NULL;
2156         obj_priv->gtt_offset = 0;
2157
2158         if (i915_gem_object_is_purgeable(obj_priv))
2159                 i915_gem_object_truncate(obj);
2160
2161         trace_i915_gem_object_unbind(obj);
2162
2163         return ret;
2164 }
2165
2166 static int i915_ring_idle(struct drm_device *dev,
2167                           struct intel_ring_buffer *ring)
2168 {
2169         i915_gem_flush_ring(dev, NULL, ring,
2170                             I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2171         return i915_wait_request(dev,
2172                                  i915_gem_next_request_seqno(dev, ring),
2173                                  ring);
2174 }
2175
2176 int
2177 i915_gpu_idle(struct drm_device *dev)
2178 {
2179         drm_i915_private_t *dev_priv = dev->dev_private;
2180         bool lists_empty;
2181         int ret;
2182
2183         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2184                        list_empty(&dev_priv->render_ring.active_list) &&
2185                        list_empty(&dev_priv->bsd_ring.active_list));
2186         if (lists_empty)
2187                 return 0;
2188
2189         /* Flush everything onto the inactive list. */
2190         ret = i915_ring_idle(dev, &dev_priv->render_ring);
2191         if (ret)
2192                 return ret;
2193
2194         ret = i915_ring_idle(dev, &dev_priv->bsd_ring);
2195         if (ret)
2196                 return ret;
2197
2198         return 0;
2199 }
2200
2201 static int
2202 i915_gem_object_get_pages(struct drm_gem_object *obj,
2203                           gfp_t gfpmask)
2204 {
2205         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2206         int page_count, i;
2207         struct address_space *mapping;
2208         struct inode *inode;
2209         struct page *page;
2210
2211         BUG_ON(obj_priv->pages_refcount
2212                         == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2213
2214         if (obj_priv->pages_refcount++ != 0)
2215                 return 0;
2216
2217         /* Get the list of pages out of our struct file.  They'll be pinned
2218          * at this point until we release them.
2219          */
2220         page_count = obj->size / PAGE_SIZE;
2221         BUG_ON(obj_priv->pages != NULL);
2222         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2223         if (obj_priv->pages == NULL) {
2224                 obj_priv->pages_refcount--;
2225                 return -ENOMEM;
2226         }
2227
2228         inode = obj->filp->f_path.dentry->d_inode;
2229         mapping = inode->i_mapping;
2230         for (i = 0; i < page_count; i++) {
2231                 page = read_cache_page_gfp(mapping, i,
2232                                            GFP_HIGHUSER |
2233                                            __GFP_COLD |
2234                                            __GFP_RECLAIMABLE |
2235                                            gfpmask);
2236                 if (IS_ERR(page))
2237                         goto err_pages;
2238
2239                 obj_priv->pages[i] = page;
2240         }
2241
2242         if (obj_priv->tiling_mode != I915_TILING_NONE)
2243                 i915_gem_object_do_bit_17_swizzle(obj);
2244
2245         return 0;
2246
2247 err_pages:
2248         while (i--)
2249                 page_cache_release(obj_priv->pages[i]);
2250
2251         drm_free_large(obj_priv->pages);
2252         obj_priv->pages = NULL;
2253         obj_priv->pages_refcount--;
2254         return PTR_ERR(page);
2255 }
2256
2257 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2258 {
2259         struct drm_gem_object *obj = reg->obj;
2260         struct drm_device *dev = obj->dev;
2261         drm_i915_private_t *dev_priv = dev->dev_private;
2262         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2263         int regnum = obj_priv->fence_reg;
2264         uint64_t val;
2265
2266         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2267                     0xfffff000) << 32;
2268         val |= obj_priv->gtt_offset & 0xfffff000;
2269         val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2270                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2271
2272         if (obj_priv->tiling_mode == I915_TILING_Y)
2273                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2274         val |= I965_FENCE_REG_VALID;
2275
2276         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2277 }
2278
2279 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2280 {
2281         struct drm_gem_object *obj = reg->obj;
2282         struct drm_device *dev = obj->dev;
2283         drm_i915_private_t *dev_priv = dev->dev_private;
2284         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2285         int regnum = obj_priv->fence_reg;
2286         uint64_t val;
2287
2288         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2289                     0xfffff000) << 32;
2290         val |= obj_priv->gtt_offset & 0xfffff000;
2291         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2292         if (obj_priv->tiling_mode == I915_TILING_Y)
2293                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2294         val |= I965_FENCE_REG_VALID;
2295
2296         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2297 }
2298
2299 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2300 {
2301         struct drm_gem_object *obj = reg->obj;
2302         struct drm_device *dev = obj->dev;
2303         drm_i915_private_t *dev_priv = dev->dev_private;
2304         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2305         int regnum = obj_priv->fence_reg;
2306         int tile_width;
2307         uint32_t fence_reg, val;
2308         uint32_t pitch_val;
2309
2310         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2311             (obj_priv->gtt_offset & (obj->size - 1))) {
2312                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2313                      __func__, obj_priv->gtt_offset, obj->size);
2314                 return;
2315         }
2316
2317         if (obj_priv->tiling_mode == I915_TILING_Y &&
2318             HAS_128_BYTE_Y_TILING(dev))
2319                 tile_width = 128;
2320         else
2321                 tile_width = 512;
2322
2323         /* Note: pitch better be a power of two tile widths */
2324         pitch_val = obj_priv->stride / tile_width;
2325         pitch_val = ffs(pitch_val) - 1;
2326
2327         if (obj_priv->tiling_mode == I915_TILING_Y &&
2328             HAS_128_BYTE_Y_TILING(dev))
2329                 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2330         else
2331                 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2332
2333         val = obj_priv->gtt_offset;
2334         if (obj_priv->tiling_mode == I915_TILING_Y)
2335                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2336         val |= I915_FENCE_SIZE_BITS(obj->size);
2337         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2338         val |= I830_FENCE_REG_VALID;
2339
2340         if (regnum < 8)
2341                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2342         else
2343                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2344         I915_WRITE(fence_reg, val);
2345 }
2346
2347 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2348 {
2349         struct drm_gem_object *obj = reg->obj;
2350         struct drm_device *dev = obj->dev;
2351         drm_i915_private_t *dev_priv = dev->dev_private;
2352         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2353         int regnum = obj_priv->fence_reg;
2354         uint32_t val;
2355         uint32_t pitch_val;
2356         uint32_t fence_size_bits;
2357
2358         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2359             (obj_priv->gtt_offset & (obj->size - 1))) {
2360                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2361                      __func__, obj_priv->gtt_offset);
2362                 return;
2363         }
2364
2365         pitch_val = obj_priv->stride / 128;
2366         pitch_val = ffs(pitch_val) - 1;
2367         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2368
2369         val = obj_priv->gtt_offset;
2370         if (obj_priv->tiling_mode == I915_TILING_Y)
2371                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2372         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2373         WARN_ON(fence_size_bits & ~0x00000f00);
2374         val |= fence_size_bits;
2375         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2376         val |= I830_FENCE_REG_VALID;
2377
2378         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2379 }
2380
2381 static int i915_find_fence_reg(struct drm_device *dev,
2382                                bool interruptible)
2383 {
2384         struct drm_i915_fence_reg *reg = NULL;
2385         struct drm_i915_gem_object *obj_priv = NULL;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct drm_gem_object *obj = NULL;
2388         int i, avail, ret;
2389
2390         /* First try to find a free reg */
2391         avail = 0;
2392         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2393                 reg = &dev_priv->fence_regs[i];
2394                 if (!reg->obj)
2395                         return i;
2396
2397                 obj_priv = to_intel_bo(reg->obj);
2398                 if (!obj_priv->pin_count)
2399                     avail++;
2400         }
2401
2402         if (avail == 0)
2403                 return -ENOSPC;
2404
2405         /* None available, try to steal one or wait for a user to finish */
2406         i = I915_FENCE_REG_NONE;
2407         list_for_each_entry(reg, &dev_priv->mm.fence_list,
2408                             lru_list) {
2409                 obj = reg->obj;
2410                 obj_priv = to_intel_bo(obj);
2411
2412                 if (obj_priv->pin_count)
2413                         continue;
2414
2415                 /* found one! */
2416                 i = obj_priv->fence_reg;
2417                 break;
2418         }
2419
2420         BUG_ON(i == I915_FENCE_REG_NONE);
2421
2422         /* We only have a reference on obj from the active list. put_fence_reg
2423          * might drop that one, causing a use-after-free in it. So hold a
2424          * private reference to obj like the other callers of put_fence_reg
2425          * (set_tiling ioctl) do. */
2426         drm_gem_object_reference(obj);
2427         ret = i915_gem_object_put_fence_reg(obj, interruptible);
2428         drm_gem_object_unreference(obj);
2429         if (ret != 0)
2430                 return ret;
2431
2432         return i;
2433 }
2434
2435 /**
2436  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2437  * @obj: object to map through a fence reg
2438  *
2439  * When mapping objects through the GTT, userspace wants to be able to write
2440  * to them without having to worry about swizzling if the object is tiled.
2441  *
2442  * This function walks the fence regs looking for a free one for @obj,
2443  * stealing one if it can't find any.
2444  *
2445  * It then sets up the reg based on the object's properties: address, pitch
2446  * and tiling format.
2447  */
2448 int
2449 i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
2450                               bool interruptible)
2451 {
2452         struct drm_device *dev = obj->dev;
2453         struct drm_i915_private *dev_priv = dev->dev_private;
2454         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2455         struct drm_i915_fence_reg *reg = NULL;
2456         int ret;
2457
2458         /* Just update our place in the LRU if our fence is getting used. */
2459         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2460                 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2461                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2462                 return 0;
2463         }
2464
2465         switch (obj_priv->tiling_mode) {
2466         case I915_TILING_NONE:
2467                 WARN(1, "allocating a fence for non-tiled object?\n");
2468                 break;
2469         case I915_TILING_X:
2470                 if (!obj_priv->stride)
2471                         return -EINVAL;
2472                 WARN((obj_priv->stride & (512 - 1)),
2473                      "object 0x%08x is X tiled but has non-512B pitch\n",
2474                      obj_priv->gtt_offset);
2475                 break;
2476         case I915_TILING_Y:
2477                 if (!obj_priv->stride)
2478                         return -EINVAL;
2479                 WARN((obj_priv->stride & (128 - 1)),
2480                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2481                      obj_priv->gtt_offset);
2482                 break;
2483         }
2484
2485         ret = i915_find_fence_reg(dev, interruptible);
2486         if (ret < 0)
2487                 return ret;
2488
2489         obj_priv->fence_reg = ret;
2490         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2491         list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2492
2493         reg->obj = obj;
2494
2495         switch (INTEL_INFO(dev)->gen) {
2496         case 6:
2497                 sandybridge_write_fence_reg(reg);
2498                 break;
2499         case 5:
2500         case 4:
2501                 i965_write_fence_reg(reg);
2502                 break;
2503         case 3:
2504                 i915_write_fence_reg(reg);
2505                 break;
2506         case 2:
2507                 i830_write_fence_reg(reg);
2508                 break;
2509         }
2510
2511         trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2512                         obj_priv->tiling_mode);
2513
2514         return 0;
2515 }
2516
2517 /**
2518  * i915_gem_clear_fence_reg - clear out fence register info
2519  * @obj: object to clear
2520  *
2521  * Zeroes out the fence register itself and clears out the associated
2522  * data structures in dev_priv and obj_priv.
2523  */
2524 static void
2525 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2526 {
2527         struct drm_device *dev = obj->dev;
2528         drm_i915_private_t *dev_priv = dev->dev_private;
2529         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2530         struct drm_i915_fence_reg *reg =
2531                 &dev_priv->fence_regs[obj_priv->fence_reg];
2532         uint32_t fence_reg;
2533
2534         switch (INTEL_INFO(dev)->gen) {
2535         case 6:
2536                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2537                              (obj_priv->fence_reg * 8), 0);
2538                 break;
2539         case 5:
2540         case 4:
2541                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2542                 break;
2543         case 3:
2544                 if (obj_priv->fence_reg >= 8)
2545                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2546                 else
2547         case 2:
2548                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2549
2550                 I915_WRITE(fence_reg, 0);
2551                 break;
2552         }
2553
2554         reg->obj = NULL;
2555         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2556         list_del_init(&reg->lru_list);
2557 }
2558
2559 /**
2560  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2561  * to the buffer to finish, and then resets the fence register.
2562  * @obj: tiled object holding a fence register.
2563  * @bool: whether the wait upon the fence is interruptible
2564  *
2565  * Zeroes out the fence register itself and clears out the associated
2566  * data structures in dev_priv and obj_priv.
2567  */
2568 int
2569 i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2570                               bool interruptible)
2571 {
2572         struct drm_device *dev = obj->dev;
2573         struct drm_i915_private *dev_priv = dev->dev_private;
2574         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2575         struct drm_i915_fence_reg *reg;
2576
2577         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2578                 return 0;
2579
2580         /* If we've changed tiling, GTT-mappings of the object
2581          * need to re-fault to ensure that the correct fence register
2582          * setup is in place.
2583          */
2584         i915_gem_release_mmap(obj);
2585
2586         /* On the i915, GPU access to tiled buffers is via a fence,
2587          * therefore we must wait for any outstanding access to complete
2588          * before clearing the fence.
2589          */
2590         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2591         if (reg->gpu) {
2592                 int ret;
2593
2594                 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2595                 if (ret)
2596                         return ret;
2597
2598                 ret = i915_gem_object_wait_rendering(obj, interruptible);
2599                 if (ret)
2600                         return ret;
2601
2602                 reg->gpu = false;
2603         }
2604
2605         i915_gem_object_flush_gtt_write_domain(obj);
2606         i915_gem_clear_fence_reg(obj);
2607
2608         return 0;
2609 }
2610
2611 /**
2612  * Finds free space in the GTT aperture and binds the object there.
2613  */
2614 static int
2615 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2616 {
2617         struct drm_device *dev = obj->dev;
2618         drm_i915_private_t *dev_priv = dev->dev_private;
2619         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2620         struct drm_mm_node *free_space;
2621         gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
2622         int ret;
2623
2624         if (obj_priv->madv != I915_MADV_WILLNEED) {
2625                 DRM_ERROR("Attempting to bind a purgeable object\n");
2626                 return -EINVAL;
2627         }
2628
2629         if (alignment == 0)
2630                 alignment = i915_gem_get_gtt_alignment(obj);
2631         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2632                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2633                 return -EINVAL;
2634         }
2635
2636         /* If the object is bigger than the entire aperture, reject it early
2637          * before evicting everything in a vain attempt to find space.
2638          */
2639         if (obj->size > dev_priv->mm.gtt_total) {
2640                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2641                 return -E2BIG;
2642         }
2643
2644  search_free:
2645         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2646                                         obj->size, alignment, 0);
2647         if (free_space != NULL)
2648                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2649                                                        alignment);
2650         if (obj_priv->gtt_space == NULL) {
2651                 /* If the gtt is empty and we're still having trouble
2652                  * fitting our object in, we're out of memory.
2653                  */
2654                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2655                 if (ret)
2656                         return ret;
2657
2658                 goto search_free;
2659         }
2660
2661         ret = i915_gem_object_get_pages(obj, gfpmask);
2662         if (ret) {
2663                 drm_mm_put_block(obj_priv->gtt_space);
2664                 obj_priv->gtt_space = NULL;
2665
2666                 if (ret == -ENOMEM) {
2667                         /* first try to clear up some space from the GTT */
2668                         ret = i915_gem_evict_something(dev, obj->size,
2669                                                        alignment);
2670                         if (ret) {
2671                                 /* now try to shrink everyone else */
2672                                 if (gfpmask) {
2673                                         gfpmask = 0;
2674                                         goto search_free;
2675                                 }
2676
2677                                 return ret;
2678                         }
2679
2680                         goto search_free;
2681                 }
2682
2683                 return ret;
2684         }
2685
2686         /* Create an AGP memory structure pointing at our pages, and bind it
2687          * into the GTT.
2688          */
2689         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2690                                                obj_priv->pages,
2691                                                obj->size >> PAGE_SHIFT,
2692                                                obj_priv->gtt_space->start,
2693                                                obj_priv->agp_type);
2694         if (obj_priv->agp_mem == NULL) {
2695                 i915_gem_object_put_pages(obj);
2696                 drm_mm_put_block(obj_priv->gtt_space);
2697                 obj_priv->gtt_space = NULL;
2698
2699                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2700                 if (ret)
2701                         return ret;
2702
2703                 goto search_free;
2704         }
2705
2706         /* keep track of bounds object by adding it to the inactive list */
2707         list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
2708         i915_gem_info_add_gtt(dev_priv, obj->size);
2709
2710         /* Assert that the object is not currently in any GPU domain. As it
2711          * wasn't in the GTT, there shouldn't be any way it could have been in
2712          * a GPU cache
2713          */
2714         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2715         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2716
2717         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2718         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2719
2720         return 0;
2721 }
2722
2723 void
2724 i915_gem_clflush_object(struct drm_gem_object *obj)
2725 {
2726         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
2727
2728         /* If we don't have a page list set up, then we're not pinned
2729          * to GPU, and we can ignore the cache flush because it'll happen
2730          * again at bind time.
2731          */
2732         if (obj_priv->pages == NULL)
2733                 return;
2734
2735         trace_i915_gem_object_clflush(obj);
2736
2737         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2738 }
2739
2740 /** Flushes any GPU write domain for the object if it's dirty. */
2741 static int
2742 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
2743                                        bool pipelined)
2744 {
2745         struct drm_device *dev = obj->dev;
2746         uint32_t old_write_domain;
2747
2748         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2749                 return 0;
2750
2751         /* Queue the GPU write cache flushing we need. */
2752         old_write_domain = obj->write_domain;
2753         i915_gem_flush_ring(dev, NULL,
2754                             to_intel_bo(obj)->ring,
2755                             0, obj->write_domain);
2756         BUG_ON(obj->write_domain);
2757
2758         trace_i915_gem_object_change_domain(obj,
2759                                             obj->read_domains,
2760                                             old_write_domain);
2761
2762         if (pipelined)
2763                 return 0;
2764
2765         return i915_gem_object_wait_rendering(obj, true);
2766 }
2767
2768 /** Flushes the GTT write domain for the object if it's dirty. */
2769 static void
2770 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2771 {
2772         uint32_t old_write_domain;
2773
2774         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2775                 return;
2776
2777         /* No actual flushing is required for the GTT write domain.   Writes
2778          * to it immediately go to main memory as far as we know, so there's
2779          * no chipset flush.  It also doesn't land in render cache.
2780          */
2781         old_write_domain = obj->write_domain;
2782         obj->write_domain = 0;
2783
2784         trace_i915_gem_object_change_domain(obj,
2785                                             obj->read_domains,
2786                                             old_write_domain);
2787 }
2788
2789 /** Flushes the CPU write domain for the object if it's dirty. */
2790 static void
2791 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2792 {
2793         struct drm_device *dev = obj->dev;
2794         uint32_t old_write_domain;
2795
2796         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2797                 return;
2798
2799         i915_gem_clflush_object(obj);
2800         drm_agp_chipset_flush(dev);
2801         old_write_domain = obj->write_domain;
2802         obj->write_domain = 0;
2803
2804         trace_i915_gem_object_change_domain(obj,
2805                                             obj->read_domains,
2806                                             old_write_domain);
2807 }
2808
2809 /**
2810  * Moves a single object to the GTT read, and possibly write domain.
2811  *
2812  * This function returns when the move is complete, including waiting on
2813  * flushes to occur.
2814  */
2815 int
2816 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2817 {
2818         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2819         uint32_t old_write_domain, old_read_domains;
2820         int ret;
2821
2822         /* Not valid to be called on unbound objects. */
2823         if (obj_priv->gtt_space == NULL)
2824                 return -EINVAL;
2825
2826         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2827         if (ret != 0)
2828                 return ret;
2829
2830         i915_gem_object_flush_cpu_write_domain(obj);
2831
2832         if (write) {
2833                 ret = i915_gem_object_wait_rendering(obj, true);
2834                 if (ret)
2835                         return ret;
2836         }
2837
2838         old_write_domain = obj->write_domain;
2839         old_read_domains = obj->read_domains;
2840
2841         /* It should now be out of any other write domains, and we can update
2842          * the domain values for our changes.
2843          */
2844         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2845         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2846         if (write) {
2847                 obj->read_domains = I915_GEM_DOMAIN_GTT;
2848                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2849                 obj_priv->dirty = 1;
2850         }
2851
2852         trace_i915_gem_object_change_domain(obj,
2853                                             old_read_domains,
2854                                             old_write_domain);
2855
2856         return 0;
2857 }
2858
2859 /*
2860  * Prepare buffer for display plane. Use uninterruptible for possible flush
2861  * wait, as in modesetting process we're not supposed to be interrupted.
2862  */
2863 int
2864 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
2865                                      bool pipelined)
2866 {
2867         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2868         uint32_t old_read_domains;
2869         int ret;
2870
2871         /* Not valid to be called on unbound objects. */
2872         if (obj_priv->gtt_space == NULL)
2873                 return -EINVAL;
2874
2875         ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2876         if (ret)
2877                 return ret;
2878
2879         /* Currently, we are always called from an non-interruptible context. */
2880         if (!pipelined) {
2881                 ret = i915_gem_object_wait_rendering(obj, false);
2882                 if (ret)
2883                         return ret;
2884         }
2885
2886         i915_gem_object_flush_cpu_write_domain(obj);
2887
2888         old_read_domains = obj->read_domains;
2889         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2890
2891         trace_i915_gem_object_change_domain(obj,
2892                                             old_read_domains,
2893                                             obj->write_domain);
2894
2895         return 0;
2896 }
2897
2898 /**
2899  * Moves a single object to the CPU read, and possibly write domain.
2900  *
2901  * This function returns when the move is complete, including waiting on
2902  * flushes to occur.
2903  */
2904 static int
2905 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2906 {
2907         uint32_t old_write_domain, old_read_domains;
2908         int ret;
2909
2910         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2911         if (ret != 0)
2912                 return ret;
2913
2914         i915_gem_object_flush_gtt_write_domain(obj);
2915
2916         /* If we have a partially-valid cache of the object in the CPU,
2917          * finish invalidating it and free the per-page flags.
2918          */
2919         i915_gem_object_set_to_full_cpu_read_domain(obj);
2920
2921         if (write) {
2922                 ret = i915_gem_object_wait_rendering(obj, true);
2923                 if (ret)
2924                         return ret;
2925         }
2926
2927         old_write_domain = obj->write_domain;
2928         old_read_domains = obj->read_domains;
2929
2930         /* Flush the CPU cache if it's still invalid. */
2931         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2932                 i915_gem_clflush_object(obj);
2933
2934                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2935         }
2936
2937         /* It should now be out of any other write domains, and we can update
2938          * the domain values for our changes.
2939          */
2940         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2941
2942         /* If we're writing through the CPU, then the GPU read domains will
2943          * need to be invalidated at next use.
2944          */
2945         if (write) {
2946                 obj->read_domains = I915_GEM_DOMAIN_CPU;
2947                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2948         }
2949
2950         trace_i915_gem_object_change_domain(obj,
2951                                             old_read_domains,
2952                                             old_write_domain);
2953
2954         return 0;
2955 }
2956
2957 /*
2958  * Set the next domain for the specified object. This
2959  * may not actually perform the necessary flushing/invaliding though,
2960  * as that may want to be batched with other set_domain operations
2961  *
2962  * This is (we hope) the only really tricky part of gem. The goal
2963  * is fairly simple -- track which caches hold bits of the object
2964  * and make sure they remain coherent. A few concrete examples may
2965  * help to explain how it works. For shorthand, we use the notation
2966  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2967  * a pair of read and write domain masks.
2968  *
2969  * Case 1: the batch buffer
2970  *
2971  *      1. Allocated
2972  *      2. Written by CPU
2973  *      3. Mapped to GTT
2974  *      4. Read by GPU
2975  *      5. Unmapped from GTT
2976  *      6. Freed
2977  *
2978  *      Let's take these a step at a time
2979  *
2980  *      1. Allocated
2981  *              Pages allocated from the kernel may still have
2982  *              cache contents, so we set them to (CPU, CPU) always.
2983  *      2. Written by CPU (using pwrite)
2984  *              The pwrite function calls set_domain (CPU, CPU) and
2985  *              this function does nothing (as nothing changes)
2986  *      3. Mapped by GTT
2987  *              This function asserts that the object is not
2988  *              currently in any GPU-based read or write domains
2989  *      4. Read by GPU
2990  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
2991  *              As write_domain is zero, this function adds in the
2992  *              current read domains (CPU+COMMAND, 0).
2993  *              flush_domains is set to CPU.
2994  *              invalidate_domains is set to COMMAND
2995  *              clflush is run to get data out of the CPU caches
2996  *              then i915_dev_set_domain calls i915_gem_flush to
2997  *              emit an MI_FLUSH and drm_agp_chipset_flush
2998  *      5. Unmapped from GTT
2999  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
3000  *              flush_domains and invalidate_domains end up both zero
3001  *              so no flushing/invalidating happens
3002  *      6. Freed
3003  *              yay, done
3004  *
3005  * Case 2: The shared render buffer
3006  *
3007  *      1. Allocated
3008  *      2. Mapped to GTT
3009  *      3. Read/written by GPU
3010  *      4. set_domain to (CPU,CPU)
3011  *      5. Read/written by CPU
3012  *      6. Read/written by GPU
3013  *
3014  *      1. Allocated
3015  *              Same as last example, (CPU, CPU)
3016  *      2. Mapped to GTT
3017  *              Nothing changes (assertions find that it is not in the GPU)
3018  *      3. Read/written by GPU
3019  *              execbuffer calls set_domain (RENDER, RENDER)
3020  *              flush_domains gets CPU
3021  *              invalidate_domains gets GPU
3022  *              clflush (obj)
3023  *              MI_FLUSH and drm_agp_chipset_flush
3024  *      4. set_domain (CPU, CPU)
3025  *              flush_domains gets GPU
3026  *              invalidate_domains gets CPU
3027  *              wait_rendering (obj) to make sure all drawing is complete.
3028  *              This will include an MI_FLUSH to get the data from GPU
3029  *              to memory
3030  *              clflush (obj) to invalidate the CPU cache
3031  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3032  *      5. Read/written by CPU
3033  *              cache lines are loaded and dirtied
3034  *      6. Read written by GPU
3035  *              Same as last GPU access
3036  *
3037  * Case 3: The constant buffer
3038  *
3039  *      1. Allocated
3040  *      2. Written by CPU
3041  *      3. Read by GPU
3042  *      4. Updated (written) by CPU again
3043  *      5. Read by GPU
3044  *
3045  *      1. Allocated
3046  *              (CPU, CPU)
3047  *      2. Written by CPU
3048  *              (CPU, CPU)
3049  *      3. Read by GPU
3050  *              (CPU+RENDER, 0)
3051  *              flush_domains = CPU
3052  *              invalidate_domains = RENDER
3053  *              clflush (obj)
3054  *              MI_FLUSH
3055  *              drm_agp_chipset_flush
3056  *      4. Updated (written) by CPU again
3057  *              (CPU, CPU)
3058  *              flush_domains = 0 (no previous write domain)
3059  *              invalidate_domains = 0 (no new read domains)
3060  *      5. Read by GPU
3061  *              (CPU+RENDER, 0)
3062  *              flush_domains = CPU
3063  *              invalidate_domains = RENDER
3064  *              clflush (obj)
3065  *              MI_FLUSH
3066  *              drm_agp_chipset_flush
3067  */
3068 static void
3069 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3070 {
3071         struct drm_device               *dev = obj->dev;
3072         struct drm_i915_private         *dev_priv = dev->dev_private;
3073         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
3074         uint32_t                        invalidate_domains = 0;
3075         uint32_t                        flush_domains = 0;
3076         uint32_t                        old_read_domains;
3077
3078         intel_mark_busy(dev, obj);
3079
3080         /*
3081          * If the object isn't moving to a new write domain,
3082          * let the object stay in multiple read domains
3083          */
3084         if (obj->pending_write_domain == 0)
3085                 obj->pending_read_domains |= obj->read_domains;
3086         else
3087                 obj_priv->dirty = 1;
3088
3089         /*
3090          * Flush the current write domain if
3091          * the new read domains don't match. Invalidate
3092          * any read domains which differ from the old
3093          * write domain
3094          */
3095         if (obj->write_domain &&
3096             obj->write_domain != obj->pending_read_domains) {
3097                 flush_domains |= obj->write_domain;
3098                 invalidate_domains |=
3099                         obj->pending_read_domains & ~obj->write_domain;
3100         }
3101         /*
3102          * Invalidate any read caches which may have
3103          * stale data. That is, any new read domains.
3104          */
3105         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3106         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
3107                 i915_gem_clflush_object(obj);
3108
3109         old_read_domains = obj->read_domains;
3110
3111         /* The actual obj->write_domain will be updated with
3112          * pending_write_domain after we emit the accumulated flush for all
3113          * of our domain changes in execbuffers (which clears objects'
3114          * write_domains).  So if we have a current write domain that we
3115          * aren't changing, set pending_write_domain to that.
3116          */
3117         if (flush_domains == 0 && obj->pending_write_domain == 0)
3118                 obj->pending_write_domain = obj->write_domain;
3119         obj->read_domains = obj->pending_read_domains;
3120
3121         dev->invalidate_domains |= invalidate_domains;
3122         dev->flush_domains |= flush_domains;
3123         if (obj_priv->ring)
3124                 dev_priv->mm.flush_rings |= obj_priv->ring->id;
3125
3126         trace_i915_gem_object_change_domain(obj,
3127                                             old_read_domains,
3128                                             obj->write_domain);
3129 }
3130
3131 /**
3132  * Moves the object from a partially CPU read to a full one.
3133  *
3134  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3135  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3136  */
3137 static void
3138 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3139 {
3140         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3141
3142         if (!obj_priv->page_cpu_valid)
3143                 return;
3144
3145         /* If we're partially in the CPU read domain, finish moving it in.
3146          */
3147         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3148                 int i;
3149
3150                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3151                         if (obj_priv->page_cpu_valid[i])
3152                                 continue;
3153                         drm_clflush_pages(obj_priv->pages + i, 1);
3154                 }
3155         }
3156
3157         /* Free the page_cpu_valid mappings which are now stale, whether
3158          * or not we've got I915_GEM_DOMAIN_CPU.
3159          */
3160         kfree(obj_priv->page_cpu_valid);
3161         obj_priv->page_cpu_valid = NULL;
3162 }
3163
3164 /**
3165  * Set the CPU read domain on a range of the object.
3166  *
3167  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3168  * not entirely valid.  The page_cpu_valid member of the object flags which
3169  * pages have been flushed, and will be respected by
3170  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3171  * of the whole object.
3172  *
3173  * This function returns when the move is complete, including waiting on
3174  * flushes to occur.
3175  */
3176 static int
3177 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3178                                           uint64_t offset, uint64_t size)
3179 {
3180         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3181         uint32_t old_read_domains;
3182         int i, ret;
3183
3184         if (offset == 0 && size == obj->size)
3185                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3186
3187         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
3188         if (ret != 0)
3189                 return ret;
3190         i915_gem_object_flush_gtt_write_domain(obj);
3191
3192         /* If we're already fully in the CPU read domain, we're done. */
3193         if (obj_priv->page_cpu_valid == NULL &&
3194             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3195                 return 0;
3196
3197         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3198          * newly adding I915_GEM_DOMAIN_CPU
3199          */
3200         if (obj_priv->page_cpu_valid == NULL) {
3201                 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3202                                                    GFP_KERNEL);
3203                 if (obj_priv->page_cpu_valid == NULL)
3204                         return -ENOMEM;
3205         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3206                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3207
3208         /* Flush the cache on any pages that are still invalid from the CPU's
3209          * perspective.
3210          */
3211         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3212              i++) {
3213                 if (obj_priv->page_cpu_valid[i])
3214                         continue;
3215
3216                 drm_clflush_pages(obj_priv->pages + i, 1);
3217
3218                 obj_priv->page_cpu_valid[i] = 1;
3219         }
3220
3221         /* It should now be out of any other write domains, and we can update
3222          * the domain values for our changes.
3223          */
3224         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3225
3226         old_read_domains = obj->read_domains;
3227         obj->read_domains |= I915_GEM_DOMAIN_CPU;
3228
3229         trace_i915_gem_object_change_domain(obj,
3230                                             old_read_domains,
3231                                             obj->write_domain);
3232
3233         return 0;
3234 }
3235
3236 /**
3237  * Pin an object to the GTT and evaluate the relocations landing in it.
3238  */
3239 static int
3240 i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj,
3241                              struct drm_file *file_priv,
3242                              struct drm_i915_gem_exec_object2 *entry)
3243 {
3244         struct drm_device *dev = obj->base.dev;
3245         drm_i915_private_t *dev_priv = dev->dev_private;
3246         struct drm_i915_gem_relocation_entry __user *user_relocs;
3247         struct drm_gem_object *target_obj = NULL;
3248         uint32_t target_handle = 0;
3249         int i, ret = 0;
3250
3251         user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
3252         for (i = 0; i < entry->relocation_count; i++) {
3253                 struct drm_i915_gem_relocation_entry reloc;
3254                 uint32_t target_offset;
3255
3256                 if (__copy_from_user_inatomic(&reloc,
3257                                               user_relocs+i,
3258                                               sizeof(reloc))) {
3259                         ret = -EFAULT;
3260                         break;
3261                 }
3262
3263                 if (reloc.target_handle != target_handle) {
3264                         drm_gem_object_unreference(target_obj);
3265
3266                         target_obj = drm_gem_object_lookup(dev, file_priv,
3267                                                            reloc.target_handle);
3268                         if (target_obj == NULL) {
3269                                 ret = -ENOENT;
3270                                 break;
3271                         }
3272
3273                         target_handle = reloc.target_handle;
3274                 }
3275                 target_offset = to_intel_bo(target_obj)->gtt_offset;
3276
3277 #if WATCH_RELOC
3278                 DRM_INFO("%s: obj %p offset %08x target %d "
3279                          "read %08x write %08x gtt %08x "
3280                          "presumed %08x delta %08x\n",
3281                          __func__,
3282                          obj,
3283                          (int) reloc.offset,
3284                          (int) reloc.target_handle,
3285                          (int) reloc.read_domains,
3286                          (int) reloc.write_domain,
3287                          (int) target_offset,
3288                          (int) reloc.presumed_offset,
3289                          reloc.delta);
3290 #endif
3291
3292                 /* The target buffer should have appeared before us in the
3293                  * exec_object list, so it should have a GTT space bound by now.
3294                  */
3295                 if (target_offset == 0) {
3296                         DRM_ERROR("No GTT space found for object %d\n",
3297                                   reloc.target_handle);
3298                         ret = -EINVAL;
3299                         break;
3300                 }
3301
3302                 /* Validate that the target is in a valid r/w GPU domain */
3303                 if (reloc.write_domain & (reloc.write_domain - 1)) {
3304                         DRM_ERROR("reloc with multiple write domains: "
3305                                   "obj %p target %d offset %d "
3306                                   "read %08x write %08x",
3307                                   obj, reloc.target_handle,
3308                                   (int) reloc.offset,
3309                                   reloc.read_domains,
3310                                   reloc.write_domain);
3311                         ret = -EINVAL;
3312                         break;
3313                 }
3314                 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
3315                     reloc.read_domains & I915_GEM_DOMAIN_CPU) {
3316                         DRM_ERROR("reloc with read/write CPU domains: "
3317                                   "obj %p target %d offset %d "
3318                                   "read %08x write %08x",
3319                                   obj, reloc.target_handle,
3320                                   (int) reloc.offset,
3321                                   reloc.read_domains,
3322                                   reloc.write_domain);
3323                         ret = -EINVAL;
3324                         break;
3325                 }
3326                 if (reloc.write_domain && target_obj->pending_write_domain &&
3327                     reloc.write_domain != target_obj->pending_write_domain) {
3328                         DRM_ERROR("Write domain conflict: "
3329                                   "obj %p target %d offset %d "
3330                                   "new %08x old %08x\n",
3331                                   obj, reloc.target_handle,
3332                                   (int) reloc.offset,
3333                                   reloc.write_domain,
3334                                   target_obj->pending_write_domain);
3335                         ret = -EINVAL;
3336                         break;
3337                 }
3338
3339                 target_obj->pending_read_domains |= reloc.read_domains;
3340                 target_obj->pending_write_domain = reloc.write_domain;
3341
3342                 /* If the relocation already has the right value in it, no
3343                  * more work needs to be done.
3344                  */
3345                 if (target_offset == reloc.presumed_offset)
3346                         continue;
3347
3348                 /* Check that the relocation address is valid... */
3349                 if (reloc.offset > obj->base.size - 4) {
3350                         DRM_ERROR("Relocation beyond object bounds: "
3351                                   "obj %p target %d offset %d size %d.\n",
3352                                   obj, reloc.target_handle,
3353                                   (int) reloc.offset, (int) obj->base.size);
3354                         ret = -EINVAL;
3355                         break;
3356                 }
3357                 if (reloc.offset & 3) {
3358                         DRM_ERROR("Relocation not 4-byte aligned: "
3359                                   "obj %p target %d offset %d.\n",
3360                                   obj, reloc.target_handle,
3361                                   (int) reloc.offset);
3362                         ret = -EINVAL;
3363                         break;
3364                 }
3365
3366                 /* and points to somewhere within the target object. */
3367                 if (reloc.delta >= target_obj->size) {
3368                         DRM_ERROR("Relocation beyond target object bounds: "
3369                                   "obj %p target %d delta %d size %d.\n",
3370                                   obj, reloc.target_handle,
3371                                   (int) reloc.delta, (int) target_obj->size);
3372                         ret = -EINVAL;
3373                         break;
3374                 }
3375
3376                 reloc.delta += target_offset;
3377                 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
3378                         uint32_t page_offset = reloc.offset & ~PAGE_MASK;
3379                         char *vaddr;
3380
3381                         vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT], KM_USER0);
3382                         *(uint32_t *)(vaddr + page_offset) = reloc.delta;
3383                         kunmap_atomic(vaddr, KM_USER0);
3384                 } else {
3385                         uint32_t __iomem *reloc_entry;
3386                         void __iomem *reloc_page;
3387
3388                         ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1);
3389                         if (ret)
3390                                 break;
3391
3392                         /* Map the page containing the relocation we're going to perform.  */
3393                         reloc.offset += obj->gtt_offset;
3394                         reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3395                                                               reloc.offset & PAGE_MASK,
3396                                                               KM_USER0);
3397                         reloc_entry = (uint32_t __iomem *)
3398                                 (reloc_page + (reloc.offset & ~PAGE_MASK));
3399                         iowrite32(reloc.delta, reloc_entry);
3400                         io_mapping_unmap_atomic(reloc_page, KM_USER0);
3401                 }
3402         }
3403
3404         drm_gem_object_unreference(target_obj);
3405         return ret;
3406 }
3407
3408 static int
3409 i915_gem_execbuffer_pin(struct drm_device *dev,
3410                         struct drm_file *file,
3411                         struct drm_gem_object **object_list,
3412                         struct drm_i915_gem_exec_object2 *exec_list,
3413                         int count)
3414 {
3415         struct drm_i915_private *dev_priv = dev->dev_private;
3416         int ret, i, retry;
3417
3418         /* attempt to pin all of the buffers into the GTT */
3419         for (retry = 0; retry < 2; retry++) {
3420                 ret = 0;
3421                 for (i = 0; i < count; i++) {
3422                         struct drm_i915_gem_exec_object2 *entry = &exec_list[i];
3423                         struct drm_i915_gem_object *obj= to_intel_bo(object_list[i]);
3424                         bool need_fence =
3425                                 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3426                                 obj->tiling_mode != I915_TILING_NONE;
3427
3428                         /* Check fence reg constraints and rebind if necessary */
3429                         if (need_fence &&
3430                             !i915_gem_object_fence_offset_ok(&obj->base,
3431                                                              obj->tiling_mode)) {
3432                                 ret = i915_gem_object_unbind(&obj->base);
3433                                 if (ret)
3434                                         break;
3435                         }
3436
3437                         ret = i915_gem_object_pin(&obj->base, entry->alignment);
3438                         if (ret)
3439                                 break;
3440
3441                         /*
3442                          * Pre-965 chips need a fence register set up in order
3443                          * to properly handle blits to/from tiled surfaces.
3444                          */
3445                         if (need_fence) {
3446                                 ret = i915_gem_object_get_fence_reg(&obj->base, true);
3447                                 if (ret) {
3448                                         i915_gem_object_unpin(&obj->base);
3449                                         break;
3450                                 }
3451
3452                                 dev_priv->fence_regs[obj->fence_reg].gpu = true;
3453                         }
3454
3455                         entry->offset = obj->gtt_offset;
3456                 }
3457
3458                 while (i--)
3459                         i915_gem_object_unpin(object_list[i]);
3460
3461                 if (ret == 0)
3462                         break;
3463
3464                 if (ret != -ENOSPC || retry)
3465                         return ret;
3466
3467                 ret = i915_gem_evict_everything(dev);
3468                 if (ret)
3469                         return ret;
3470         }
3471
3472         return 0;
3473 }
3474
3475 /* Throttle our rendering by waiting until the ring has completed our requests
3476  * emitted over 20 msec ago.
3477  *
3478  * Note that if we were to use the current jiffies each time around the loop,
3479  * we wouldn't escape the function with any frames outstanding if the time to
3480  * render a frame was over 20ms.
3481  *
3482  * This should get us reasonable parallelism between CPU and GPU but also
3483  * relatively low latency when blocking on a particular request to finish.
3484  */
3485 static int
3486 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3487 {
3488         struct drm_i915_private *dev_priv = dev->dev_private;
3489         struct drm_i915_file_private *file_priv = file->driver_priv;
3490         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3491         struct drm_i915_gem_request *request;
3492         struct intel_ring_buffer *ring = NULL;
3493         u32 seqno = 0;
3494         int ret;
3495
3496         spin_lock(&file_priv->mm.lock);
3497         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3498                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3499                         break;
3500
3501                 ring = request->ring;
3502                 seqno = request->seqno;
3503         }
3504         spin_unlock(&file_priv->mm.lock);
3505
3506         if (seqno == 0)
3507                 return 0;
3508
3509         ret = 0;
3510         if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) {
3511                 /* And wait for the seqno passing without holding any locks and
3512                  * causing extra latency for others. This is safe as the irq
3513                  * generation is designed to be run atomically and so is
3514                  * lockless.
3515                  */
3516                 ring->user_irq_get(dev, ring);
3517                 ret = wait_event_interruptible(ring->irq_queue,
3518                                                i915_seqno_passed(ring->get_seqno(dev, ring), seqno)
3519                                                || atomic_read(&dev_priv->mm.wedged));
3520                 ring->user_irq_put(dev, ring);
3521
3522                 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3523                         ret = -EIO;
3524         }
3525
3526         if (ret == 0)
3527                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3528
3529         return ret;
3530 }
3531
3532 static int
3533 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec,
3534                           uint64_t exec_offset)
3535 {
3536         uint32_t exec_start, exec_len;
3537
3538         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3539         exec_len = (uint32_t) exec->batch_len;
3540
3541         if ((exec_start | exec_len) & 0x7)
3542                 return -EINVAL;
3543
3544         if (!exec_start)
3545                 return -EINVAL;
3546
3547         return 0;
3548 }
3549
3550 static int
3551 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
3552                    int count)
3553 {
3554         int i;
3555
3556         for (i = 0; i < count; i++) {
3557                 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
3558                 size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry);
3559
3560                 if (!access_ok(VERIFY_READ, ptr, length))
3561                         return -EFAULT;
3562
3563                 if (fault_in_pages_readable(ptr, length))
3564                         return -EFAULT;
3565         }
3566
3567         return 0;
3568 }
3569
3570 static int
3571 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3572                        struct drm_file *file,
3573                        struct drm_i915_gem_execbuffer2 *args,
3574                        struct drm_i915_gem_exec_object2 *exec_list)
3575 {
3576         drm_i915_private_t *dev_priv = dev->dev_private;
3577         struct drm_gem_object **object_list = NULL;
3578         struct drm_gem_object *batch_obj;
3579         struct drm_i915_gem_object *obj_priv;
3580         struct drm_clip_rect *cliprects = NULL;
3581         struct drm_i915_gem_request *request = NULL;
3582         int ret, i, flips;
3583         uint64_t exec_offset;
3584
3585         struct intel_ring_buffer *ring = NULL;
3586
3587         ret = i915_gem_check_is_wedged(dev);
3588         if (ret)
3589                 return ret;
3590
3591         ret = validate_exec_list(exec_list, args->buffer_count);
3592         if (ret)
3593                 return ret;
3594
3595 #if WATCH_EXEC
3596         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3597                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3598 #endif
3599         if (args->flags & I915_EXEC_BSD) {
3600                 if (!HAS_BSD(dev)) {
3601                         DRM_ERROR("execbuf with wrong flag\n");
3602                         return -EINVAL;
3603                 }
3604                 ring = &dev_priv->bsd_ring;
3605         } else {
3606                 ring = &dev_priv->render_ring;
3607         }
3608
3609         if (args->buffer_count < 1) {
3610                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3611                 return -EINVAL;
3612         }
3613         object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3614         if (object_list == NULL) {
3615                 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3616                           args->buffer_count);
3617                 ret = -ENOMEM;
3618                 goto pre_mutex_err;
3619         }
3620
3621         if (args->num_cliprects != 0) {
3622                 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3623                                     GFP_KERNEL);
3624                 if (cliprects == NULL) {
3625                         ret = -ENOMEM;
3626                         goto pre_mutex_err;
3627                 }
3628
3629                 ret = copy_from_user(cliprects,
3630                                      (struct drm_clip_rect __user *)
3631                                      (uintptr_t) args->cliprects_ptr,
3632                                      sizeof(*cliprects) * args->num_cliprects);
3633                 if (ret != 0) {
3634                         DRM_ERROR("copy %d cliprects failed: %d\n",
3635                                   args->num_cliprects, ret);
3636                         ret = -EFAULT;
3637                         goto pre_mutex_err;
3638                 }
3639         }
3640
3641         request = kzalloc(sizeof(*request), GFP_KERNEL);
3642         if (request == NULL) {
3643                 ret = -ENOMEM;
3644                 goto pre_mutex_err;
3645         }
3646
3647         ret = i915_mutex_lock_interruptible(dev);
3648         if (ret)
3649                 goto pre_mutex_err;
3650
3651         if (dev_priv->mm.suspended) {
3652                 mutex_unlock(&dev->struct_mutex);
3653                 ret = -EBUSY;
3654                 goto pre_mutex_err;
3655         }
3656
3657         /* Look up object handles */
3658         for (i = 0; i < args->buffer_count; i++) {
3659                 object_list[i] = drm_gem_object_lookup(dev, file,
3660                                                        exec_list[i].handle);
3661                 if (object_list[i] == NULL) {
3662                         DRM_ERROR("Invalid object handle %d at index %d\n",
3663                                    exec_list[i].handle, i);
3664                         /* prevent error path from reading uninitialized data */
3665                         args->buffer_count = i + 1;
3666                         ret = -ENOENT;
3667                         goto err;
3668                 }
3669
3670                 obj_priv = to_intel_bo(object_list[i]);
3671                 if (obj_priv->in_execbuffer) {
3672                         DRM_ERROR("Object %p appears more than once in object list\n",
3673                                    object_list[i]);
3674                         /* prevent error path from reading uninitialized data */
3675                         args->buffer_count = i + 1;
3676                         ret = -EINVAL;
3677                         goto err;
3678                 }
3679                 obj_priv->in_execbuffer = true;
3680         }
3681
3682         /* Move the objects en-masse into the GTT, evicting if necessary. */
3683         ret = i915_gem_execbuffer_pin(dev, file,
3684                                       object_list, exec_list,
3685                                       args->buffer_count);
3686         if (ret)
3687                 goto err;
3688
3689         /* The objects are in their final locations, apply the relocations. */
3690         for (i = 0; i < args->buffer_count; i++) {
3691                 struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]);
3692                 obj->base.pending_read_domains = 0;
3693                 obj->base.pending_write_domain = 0;
3694                 ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]);
3695                 if (ret)
3696                         goto err;
3697         }
3698
3699         /* Set the pending read domains for the batch buffer to COMMAND */
3700         batch_obj = object_list[args->buffer_count-1];
3701         if (batch_obj->pending_write_domain) {
3702                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3703                 ret = -EINVAL;
3704                 goto err;
3705         }
3706         batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3707
3708         /* Sanity check the batch buffer */
3709         exec_offset = to_intel_bo(batch_obj)->gtt_offset;
3710         ret = i915_gem_check_execbuffer(args, exec_offset);
3711         if (ret != 0) {
3712                 DRM_ERROR("execbuf with invalid offset/length\n");
3713                 goto err;
3714         }
3715
3716         /* Zero the global flush/invalidate flags. These
3717          * will be modified as new domains are computed
3718          * for each object
3719          */
3720         dev->invalidate_domains = 0;
3721         dev->flush_domains = 0;
3722         dev_priv->mm.flush_rings = 0;
3723
3724         for (i = 0; i < args->buffer_count; i++) {
3725                 struct drm_gem_object *obj = object_list[i];
3726
3727                 /* Compute new gpu domains and update invalidate/flush */
3728                 i915_gem_object_set_to_gpu_domain(obj);
3729         }
3730
3731         if (dev->invalidate_domains | dev->flush_domains) {
3732 #if WATCH_EXEC
3733                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3734                           __func__,
3735                          dev->invalidate_domains,
3736                          dev->flush_domains);
3737 #endif
3738                 i915_gem_flush(dev, file,
3739                                dev->invalidate_domains,
3740                                dev->flush_domains,
3741                                dev_priv->mm.flush_rings);
3742         }
3743
3744         for (i = 0; i < args->buffer_count; i++) {
3745                 struct drm_gem_object *obj = object_list[i];
3746                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3747                 uint32_t old_write_domain = obj->write_domain;
3748
3749                 obj->write_domain = obj->pending_write_domain;
3750                 if (obj->write_domain)
3751                         list_move_tail(&obj_priv->gpu_write_list,
3752                                        &dev_priv->mm.gpu_write_list);
3753
3754                 trace_i915_gem_object_change_domain(obj,
3755                                                     obj->read_domains,
3756                                                     old_write_domain);
3757         }
3758
3759 #if WATCH_COHERENCY
3760         for (i = 0; i < args->buffer_count; i++) {
3761                 i915_gem_object_check_coherency(object_list[i],
3762                                                 exec_list[i].handle);
3763         }
3764 #endif
3765
3766 #if WATCH_EXEC
3767         i915_gem_dump_object(batch_obj,
3768                               args->batch_len,
3769                               __func__,
3770                               ~0);
3771 #endif
3772
3773         /* Check for any pending flips. As we only maintain a flip queue depth
3774          * of 1, we can simply insert a WAIT for the next display flip prior
3775          * to executing the batch and avoid stalling the CPU.
3776          */
3777         flips = 0;
3778         for (i = 0; i < args->buffer_count; i++) {
3779                 if (object_list[i]->write_domain)
3780                         flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip);
3781         }
3782         if (flips) {
3783                 int plane, flip_mask;
3784
3785                 for (plane = 0; flips >> plane; plane++) {
3786                         if (((flips >> plane) & 1) == 0)
3787                                 continue;
3788
3789                         if (plane)
3790                                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
3791                         else
3792                                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
3793
3794                         intel_ring_begin(dev, ring, 2);
3795                         intel_ring_emit(dev, ring,
3796                                         MI_WAIT_FOR_EVENT | flip_mask);
3797                         intel_ring_emit(dev, ring, MI_NOOP);
3798                         intel_ring_advance(dev, ring);
3799                 }
3800         }
3801
3802         /* Exec the batchbuffer */
3803         ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3804                                             cliprects, exec_offset);
3805         if (ret) {
3806                 DRM_ERROR("dispatch failed %d\n", ret);
3807                 goto err;
3808         }
3809
3810         /*
3811          * Ensure that the commands in the batch buffer are
3812          * finished before the interrupt fires
3813          */
3814         i915_retire_commands(dev, ring);
3815
3816         for (i = 0; i < args->buffer_count; i++) {
3817                 struct drm_gem_object *obj = object_list[i];
3818                 obj_priv = to_intel_bo(obj);
3819
3820                 i915_gem_object_move_to_active(obj, ring);
3821         }
3822
3823         i915_add_request(dev, file, request, ring);
3824         request = NULL;
3825
3826 err:
3827         for (i = 0; i < args->buffer_count; i++) {
3828                 if (object_list[i]) {
3829                         obj_priv = to_intel_bo(object_list[i]);
3830                         obj_priv->in_execbuffer = false;
3831                 }
3832                 drm_gem_object_unreference(object_list[i]);
3833         }
3834
3835         mutex_unlock(&dev->struct_mutex);
3836
3837 pre_mutex_err:
3838         drm_free_large(object_list);
3839         kfree(cliprects);
3840         kfree(request);
3841
3842         return ret;
3843 }
3844
3845 /*
3846  * Legacy execbuffer just creates an exec2 list from the original exec object
3847  * list array and passes it to the real function.
3848  */
3849 int
3850 i915_gem_execbuffer(struct drm_device *dev, void *data,
3851                     struct drm_file *file_priv)
3852 {
3853         struct drm_i915_gem_execbuffer *args = data;
3854         struct drm_i915_gem_execbuffer2 exec2;
3855         struct drm_i915_gem_exec_object *exec_list = NULL;
3856         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3857         int ret, i;
3858
3859 #if WATCH_EXEC
3860         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3861                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3862 #endif
3863
3864         if (args->buffer_count < 1) {
3865                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3866                 return -EINVAL;
3867         }
3868
3869         /* Copy in the exec list from userland */
3870         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3871         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3872         if (exec_list == NULL || exec2_list == NULL) {
3873                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3874                           args->buffer_count);
3875                 drm_free_large(exec_list);
3876                 drm_free_large(exec2_list);
3877                 return -ENOMEM;
3878         }
3879         ret = copy_from_user(exec_list,
3880                              (struct drm_i915_relocation_entry __user *)
3881                              (uintptr_t) args->buffers_ptr,
3882                              sizeof(*exec_list) * args->buffer_count);
3883         if (ret != 0) {
3884                 DRM_ERROR("copy %d exec entries failed %d\n",
3885                           args->buffer_count, ret);
3886                 drm_free_large(exec_list);
3887                 drm_free_large(exec2_list);
3888                 return -EFAULT;
3889         }
3890
3891         for (i = 0; i < args->buffer_count; i++) {
3892                 exec2_list[i].handle = exec_list[i].handle;
3893                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3894                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3895                 exec2_list[i].alignment = exec_list[i].alignment;
3896                 exec2_list[i].offset = exec_list[i].offset;
3897                 if (INTEL_INFO(dev)->gen < 4)
3898                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3899                 else
3900                         exec2_list[i].flags = 0;
3901         }
3902
3903         exec2.buffers_ptr = args->buffers_ptr;
3904         exec2.buffer_count = args->buffer_count;
3905         exec2.batch_start_offset = args->batch_start_offset;
3906         exec2.batch_len = args->batch_len;
3907         exec2.DR1 = args->DR1;
3908         exec2.DR4 = args->DR4;
3909         exec2.num_cliprects = args->num_cliprects;
3910         exec2.cliprects_ptr = args->cliprects_ptr;
3911         exec2.flags = I915_EXEC_RENDER;
3912
3913         ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3914         if (!ret) {
3915                 /* Copy the new buffer offsets back to the user's exec list. */
3916                 for (i = 0; i < args->buffer_count; i++)
3917                         exec_list[i].offset = exec2_list[i].offset;
3918                 /* ... and back out to userspace */
3919                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3920                                    (uintptr_t) args->buffers_ptr,
3921                                    exec_list,
3922                                    sizeof(*exec_list) * args->buffer_count);
3923                 if (ret) {
3924                         ret = -EFAULT;
3925                         DRM_ERROR("failed to copy %d exec entries "
3926                                   "back to user (%d)\n",
3927                                   args->buffer_count, ret);
3928                 }
3929         }
3930
3931         drm_free_large(exec_list);
3932         drm_free_large(exec2_list);
3933         return ret;
3934 }
3935
3936 int
3937 i915_gem_execbuffer2(struct drm_device *dev, void *data,
3938                      struct drm_file *file_priv)
3939 {
3940         struct drm_i915_gem_execbuffer2 *args = data;
3941         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3942         int ret;
3943
3944 #if WATCH_EXEC
3945         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3946                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3947 #endif
3948
3949         if (args->buffer_count < 1) {
3950                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
3951                 return -EINVAL;
3952         }
3953
3954         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3955         if (exec2_list == NULL) {
3956                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3957                           args->buffer_count);
3958                 return -ENOMEM;
3959         }
3960         ret = copy_from_user(exec2_list,
3961                              (struct drm_i915_relocation_entry __user *)
3962                              (uintptr_t) args->buffers_ptr,
3963                              sizeof(*exec2_list) * args->buffer_count);
3964         if (ret != 0) {
3965                 DRM_ERROR("copy %d exec entries failed %d\n",
3966                           args->buffer_count, ret);
3967                 drm_free_large(exec2_list);
3968                 return -EFAULT;
3969         }
3970
3971         ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
3972         if (!ret) {
3973                 /* Copy the new buffer offsets back to the user's exec list. */
3974                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3975                                    (uintptr_t) args->buffers_ptr,
3976                                    exec2_list,
3977                                    sizeof(*exec2_list) * args->buffer_count);
3978                 if (ret) {
3979                         ret = -EFAULT;
3980                         DRM_ERROR("failed to copy %d exec entries "
3981                                   "back to user (%d)\n",
3982                                   args->buffer_count, ret);
3983                 }
3984         }
3985
3986         drm_free_large(exec2_list);
3987         return ret;
3988 }
3989
3990 int
3991 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3992 {
3993         struct drm_device *dev = obj->dev;
3994         struct drm_i915_private *dev_priv = dev->dev_private;
3995         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3996         int ret;
3997
3998         BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3999         WARN_ON(i915_verify_lists(dev));
4000
4001         if (obj_priv->gtt_space != NULL) {
4002                 if (alignment == 0)
4003                         alignment = i915_gem_get_gtt_alignment(obj);
4004                 if (obj_priv->gtt_offset & (alignment - 1)) {
4005                         WARN(obj_priv->pin_count,
4006                              "bo is already pinned with incorrect alignment:"
4007                              " offset=%x, req.alignment=%x\n",
4008                              obj_priv->gtt_offset, alignment);
4009                         ret = i915_gem_object_unbind(obj);
4010                         if (ret)
4011                                 return ret;
4012                 }
4013         }
4014
4015         if (obj_priv->gtt_space == NULL) {
4016                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4017                 if (ret)
4018                         return ret;
4019         }
4020
4021         obj_priv->pin_count++;
4022
4023         /* If the object is not active and not pending a flush,
4024          * remove it from the inactive list
4025          */
4026         if (obj_priv->pin_count == 1) {
4027                 i915_gem_info_add_pin(dev_priv, obj->size);
4028                 if (!obj_priv->active)
4029                         list_move_tail(&obj_priv->mm_list,
4030                                        &dev_priv->mm.pinned_list);
4031         }
4032
4033         WARN_ON(i915_verify_lists(dev));
4034         return 0;
4035 }
4036
4037 void
4038 i915_gem_object_unpin(struct drm_gem_object *obj)
4039 {
4040         struct drm_device *dev = obj->dev;
4041         drm_i915_private_t *dev_priv = dev->dev_private;
4042         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4043
4044         WARN_ON(i915_verify_lists(dev));
4045         obj_priv->pin_count--;
4046         BUG_ON(obj_priv->pin_count < 0);
4047         BUG_ON(obj_priv->gtt_space == NULL);
4048
4049         /* If the object is no longer pinned, and is
4050          * neither active nor being flushed, then stick it on
4051          * the inactive list
4052          */
4053         if (obj_priv->pin_count == 0) {
4054                 if (!obj_priv->active)
4055                         list_move_tail(&obj_priv->mm_list,
4056                                        &dev_priv->mm.inactive_list);
4057                 i915_gem_info_remove_pin(dev_priv, obj->size);
4058         }
4059         WARN_ON(i915_verify_lists(dev));
4060 }
4061
4062 int
4063 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4064                    struct drm_file *file_priv)
4065 {
4066         struct drm_i915_gem_pin *args = data;
4067         struct drm_gem_object *obj;
4068         struct drm_i915_gem_object *obj_priv;
4069         int ret;
4070
4071         ret = i915_mutex_lock_interruptible(dev);
4072         if (ret)
4073                 return ret;
4074
4075         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4076         if (obj == NULL) {
4077                 ret = -ENOENT;
4078                 goto unlock;
4079         }
4080         obj_priv = to_intel_bo(obj);
4081
4082         if (obj_priv->madv != I915_MADV_WILLNEED) {
4083                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4084                 ret = -EINVAL;
4085                 goto out;
4086         }
4087
4088         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4089                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4090                           args->handle);
4091                 ret = -EINVAL;
4092                 goto out;
4093         }
4094
4095         obj_priv->user_pin_count++;
4096         obj_priv->pin_filp = file_priv;
4097         if (obj_priv->user_pin_count == 1) {
4098                 ret = i915_gem_object_pin(obj, args->alignment);
4099                 if (ret)
4100                         goto out;
4101         }
4102
4103         /* XXX - flush the CPU caches for pinned objects
4104          * as the X server doesn't manage domains yet
4105          */
4106         i915_gem_object_flush_cpu_write_domain(obj);
4107         args->offset = obj_priv->gtt_offset;
4108 out:
4109         drm_gem_object_unreference(obj);
4110 unlock:
4111         mutex_unlock(&dev->struct_mutex);
4112         return ret;
4113 }
4114
4115 int
4116 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4117                      struct drm_file *file_priv)
4118 {
4119         struct drm_i915_gem_pin *args = data;
4120         struct drm_gem_object *obj;
4121         struct drm_i915_gem_object *obj_priv;
4122         int ret;
4123
4124         ret = i915_mutex_lock_interruptible(dev);
4125         if (ret)
4126                 return ret;
4127
4128         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4129         if (obj == NULL) {
4130                 ret = -ENOENT;
4131                 goto unlock;
4132         }
4133         obj_priv = to_intel_bo(obj);
4134
4135         if (obj_priv->pin_filp != file_priv) {
4136                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4137                           args->handle);
4138                 ret = -EINVAL;
4139                 goto out;
4140         }
4141         obj_priv->user_pin_count--;
4142         if (obj_priv->user_pin_count == 0) {
4143                 obj_priv->pin_filp = NULL;
4144                 i915_gem_object_unpin(obj);
4145         }
4146
4147 out:
4148         drm_gem_object_unreference(obj);
4149 unlock:
4150         mutex_unlock(&dev->struct_mutex);
4151         return ret;
4152 }
4153
4154 int
4155 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4156                     struct drm_file *file_priv)
4157 {
4158         struct drm_i915_gem_busy *args = data;
4159         struct drm_gem_object *obj;
4160         struct drm_i915_gem_object *obj_priv;
4161         int ret;
4162
4163         ret = i915_mutex_lock_interruptible(dev);
4164         if (ret)
4165                 return ret;
4166
4167         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4168         if (obj == NULL) {
4169                 ret = -ENOENT;
4170                 goto unlock;
4171         }
4172         obj_priv = to_intel_bo(obj);
4173
4174         /* Count all active objects as busy, even if they are currently not used
4175          * by the gpu. Users of this interface expect objects to eventually
4176          * become non-busy without any further actions, therefore emit any
4177          * necessary flushes here.
4178          */
4179         args->busy = obj_priv->active;
4180         if (args->busy) {
4181                 /* Unconditionally flush objects, even when the gpu still uses this
4182                  * object. Userspace calling this function indicates that it wants to
4183                  * use this buffer rather sooner than later, so issuing the required
4184                  * flush earlier is beneficial.
4185                  */
4186                 if (obj->write_domain & I915_GEM_GPU_DOMAINS)
4187                         i915_gem_flush_ring(dev, file_priv,
4188                                             obj_priv->ring,
4189                                             0, obj->write_domain);
4190
4191                 /* Update the active list for the hardware's current position.
4192                  * Otherwise this only updates on a delayed timer or when irqs
4193                  * are actually unmasked, and our working set ends up being
4194                  * larger than required.
4195                  */
4196                 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4197
4198                 args->busy = obj_priv->active;
4199         }
4200
4201         drm_gem_object_unreference(obj);
4202 unlock:
4203         mutex_unlock(&dev->struct_mutex);
4204         return ret;
4205 }
4206
4207 int
4208 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4209                         struct drm_file *file_priv)
4210 {
4211     return i915_gem_ring_throttle(dev, file_priv);
4212 }
4213
4214 int
4215 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4216                        struct drm_file *file_priv)
4217 {
4218         struct drm_i915_gem_madvise *args = data;
4219         struct drm_gem_object *obj;
4220         struct drm_i915_gem_object *obj_priv;
4221         int ret;
4222
4223         switch (args->madv) {
4224         case I915_MADV_DONTNEED:
4225         case I915_MADV_WILLNEED:
4226             break;
4227         default:
4228             return -EINVAL;
4229         }
4230
4231         ret = i915_mutex_lock_interruptible(dev);
4232         if (ret)
4233                 return ret;
4234
4235         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4236         if (obj == NULL) {
4237                 ret = -ENOENT;
4238                 goto unlock;
4239         }
4240         obj_priv = to_intel_bo(obj);
4241
4242         if (obj_priv->pin_count) {
4243                 ret = -EINVAL;
4244                 goto out;
4245         }
4246
4247         if (obj_priv->madv != __I915_MADV_PURGED)
4248                 obj_priv->madv = args->madv;
4249
4250         /* if the object is no longer bound, discard its backing storage */
4251         if (i915_gem_object_is_purgeable(obj_priv) &&
4252             obj_priv->gtt_space == NULL)
4253                 i915_gem_object_truncate(obj);
4254
4255         args->retained = obj_priv->madv != __I915_MADV_PURGED;
4256
4257 out:
4258         drm_gem_object_unreference(obj);
4259 unlock:
4260         mutex_unlock(&dev->struct_mutex);
4261         return ret;
4262 }
4263
4264 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4265                                               size_t size)
4266 {
4267         struct drm_i915_private *dev_priv = dev->dev_private;
4268         struct drm_i915_gem_object *obj;
4269
4270         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4271         if (obj == NULL)
4272                 return NULL;
4273
4274         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4275                 kfree(obj);
4276                 return NULL;
4277         }
4278
4279         i915_gem_info_add_obj(dev_priv, size);
4280
4281         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4282         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4283
4284         obj->agp_type = AGP_USER_MEMORY;
4285         obj->base.driver_private = NULL;
4286         obj->fence_reg = I915_FENCE_REG_NONE;
4287         INIT_LIST_HEAD(&obj->mm_list);
4288         INIT_LIST_HEAD(&obj->ring_list);
4289         INIT_LIST_HEAD(&obj->gpu_write_list);
4290         obj->madv = I915_MADV_WILLNEED;
4291
4292         return &obj->base;
4293 }
4294
4295 int i915_gem_init_object(struct drm_gem_object *obj)
4296 {
4297         BUG();
4298
4299         return 0;
4300 }
4301
4302 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4303 {
4304         struct drm_device *dev = obj->dev;
4305         drm_i915_private_t *dev_priv = dev->dev_private;
4306         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4307         int ret;
4308
4309         ret = i915_gem_object_unbind(obj);
4310         if (ret == -ERESTARTSYS) {
4311                 list_move(&obj_priv->mm_list,
4312                           &dev_priv->mm.deferred_free_list);
4313                 return;
4314         }
4315
4316         if (obj_priv->mmap_offset)
4317                 i915_gem_free_mmap_offset(obj);
4318
4319         drm_gem_object_release(obj);
4320         i915_gem_info_remove_obj(dev_priv, obj->size);
4321
4322         kfree(obj_priv->page_cpu_valid);
4323         kfree(obj_priv->bit_17);
4324         kfree(obj_priv);
4325 }
4326
4327 void i915_gem_free_object(struct drm_gem_object *obj)
4328 {
4329         struct drm_device *dev = obj->dev;
4330         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4331
4332         trace_i915_gem_object_destroy(obj);
4333
4334         while (obj_priv->pin_count > 0)
4335                 i915_gem_object_unpin(obj);
4336
4337         if (obj_priv->phys_obj)
4338                 i915_gem_detach_phys_object(dev, obj);
4339
4340         i915_gem_free_object_tail(obj);
4341 }
4342
4343 int
4344 i915_gem_idle(struct drm_device *dev)
4345 {
4346         drm_i915_private_t *dev_priv = dev->dev_private;
4347         int ret;
4348
4349         mutex_lock(&dev->struct_mutex);
4350
4351         if (dev_priv->mm.suspended) {
4352                 mutex_unlock(&dev->struct_mutex);
4353                 return 0;
4354         }
4355
4356         ret = i915_gpu_idle(dev);
4357         if (ret) {
4358                 mutex_unlock(&dev->struct_mutex);
4359                 return ret;
4360         }
4361
4362         /* Under UMS, be paranoid and evict. */
4363         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4364                 ret = i915_gem_evict_inactive(dev);
4365                 if (ret) {
4366                         mutex_unlock(&dev->struct_mutex);
4367                         return ret;
4368                 }
4369         }
4370
4371         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4372          * We need to replace this with a semaphore, or something.
4373          * And not confound mm.suspended!
4374          */
4375         dev_priv->mm.suspended = 1;
4376         del_timer_sync(&dev_priv->hangcheck_timer);
4377
4378         i915_kernel_lost_context(dev);
4379         i915_gem_cleanup_ringbuffer(dev);
4380
4381         mutex_unlock(&dev->struct_mutex);
4382
4383         /* Cancel the retire work handler, which should be idle now. */
4384         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4385
4386         return 0;
4387 }
4388
4389 /*
4390  * 965+ support PIPE_CONTROL commands, which provide finer grained control
4391  * over cache flushing.
4392  */
4393 static int
4394 i915_gem_init_pipe_control(struct drm_device *dev)
4395 {
4396         drm_i915_private_t *dev_priv = dev->dev_private;
4397         struct drm_gem_object *obj;
4398         struct drm_i915_gem_object *obj_priv;
4399         int ret;
4400
4401         obj = i915_gem_alloc_object(dev, 4096);
4402         if (obj == NULL) {
4403                 DRM_ERROR("Failed to allocate seqno page\n");
4404                 ret = -ENOMEM;
4405                 goto err;
4406         }
4407         obj_priv = to_intel_bo(obj);
4408         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4409
4410         ret = i915_gem_object_pin(obj, 4096);
4411         if (ret)
4412                 goto err_unref;
4413
4414         dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4415         dev_priv->seqno_page =  kmap(obj_priv->pages[0]);
4416         if (dev_priv->seqno_page == NULL)
4417                 goto err_unpin;
4418
4419         dev_priv->seqno_obj = obj;
4420         memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4421
4422         return 0;
4423
4424 err_unpin:
4425         i915_gem_object_unpin(obj);
4426 err_unref:
4427         drm_gem_object_unreference(obj);
4428 err:
4429         return ret;
4430 }
4431
4432
4433 static void
4434 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4435 {
4436         drm_i915_private_t *dev_priv = dev->dev_private;
4437         struct drm_gem_object *obj;
4438         struct drm_i915_gem_object *obj_priv;
4439
4440         obj = dev_priv->seqno_obj;
4441         obj_priv = to_intel_bo(obj);
4442         kunmap(obj_priv->pages[0]);
4443         i915_gem_object_unpin(obj);
4444         drm_gem_object_unreference(obj);
4445         dev_priv->seqno_obj = NULL;
4446
4447         dev_priv->seqno_page = NULL;
4448 }
4449
4450 int
4451 i915_gem_init_ringbuffer(struct drm_device *dev)
4452 {
4453         drm_i915_private_t *dev_priv = dev->dev_private;
4454         int ret;
4455
4456         if (HAS_PIPE_CONTROL(dev)) {
4457                 ret = i915_gem_init_pipe_control(dev);
4458                 if (ret)
4459                         return ret;
4460         }
4461
4462         ret = intel_init_render_ring_buffer(dev);
4463         if (ret)
4464                 goto cleanup_pipe_control;
4465
4466         if (HAS_BSD(dev)) {
4467                 ret = intel_init_bsd_ring_buffer(dev);
4468                 if (ret)
4469                         goto cleanup_render_ring;
4470         }
4471
4472         dev_priv->next_seqno = 1;
4473
4474         return 0;
4475
4476 cleanup_render_ring:
4477         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4478 cleanup_pipe_control:
4479         if (HAS_PIPE_CONTROL(dev))
4480                 i915_gem_cleanup_pipe_control(dev);
4481         return ret;
4482 }
4483
4484 void
4485 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4486 {
4487         drm_i915_private_t *dev_priv = dev->dev_private;
4488
4489         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4490         intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4491         if (HAS_PIPE_CONTROL(dev))
4492                 i915_gem_cleanup_pipe_control(dev);
4493 }
4494
4495 int
4496 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4497                        struct drm_file *file_priv)
4498 {
4499         drm_i915_private_t *dev_priv = dev->dev_private;
4500         int ret;
4501
4502         if (drm_core_check_feature(dev, DRIVER_MODESET))
4503                 return 0;
4504
4505         if (atomic_read(&dev_priv->mm.wedged)) {
4506                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4507                 atomic_set(&dev_priv->mm.wedged, 0);
4508         }
4509
4510         mutex_lock(&dev->struct_mutex);
4511         dev_priv->mm.suspended = 0;
4512
4513         ret = i915_gem_init_ringbuffer(dev);
4514         if (ret != 0) {
4515                 mutex_unlock(&dev->struct_mutex);
4516                 return ret;
4517         }
4518
4519         BUG_ON(!list_empty(&dev_priv->mm.active_list));
4520         BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4521         BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list));
4522         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4523         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4524         BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4525         BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list));
4526         mutex_unlock(&dev->struct_mutex);
4527
4528         ret = drm_irq_install(dev);
4529         if (ret)
4530                 goto cleanup_ringbuffer;
4531
4532         return 0;
4533
4534 cleanup_ringbuffer:
4535         mutex_lock(&dev->struct_mutex);
4536         i915_gem_cleanup_ringbuffer(dev);
4537         dev_priv->mm.suspended = 1;
4538         mutex_unlock(&dev->struct_mutex);
4539
4540         return ret;
4541 }
4542
4543 int
4544 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4545                        struct drm_file *file_priv)
4546 {
4547         if (drm_core_check_feature(dev, DRIVER_MODESET))
4548                 return 0;
4549
4550         drm_irq_uninstall(dev);
4551         return i915_gem_idle(dev);
4552 }
4553
4554 void
4555 i915_gem_lastclose(struct drm_device *dev)
4556 {
4557         int ret;
4558
4559         if (drm_core_check_feature(dev, DRIVER_MODESET))
4560                 return;
4561
4562         ret = i915_gem_idle(dev);
4563         if (ret)
4564                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4565 }
4566
4567 void
4568 i915_gem_load(struct drm_device *dev)
4569 {
4570         int i;
4571         drm_i915_private_t *dev_priv = dev->dev_private;
4572
4573         INIT_LIST_HEAD(&dev_priv->mm.active_list);
4574         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4575         INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4576         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4577         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
4578         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4579         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4580         INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4581         INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4582         INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4583         INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4584         for (i = 0; i < 16; i++)
4585                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4586         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4587                           i915_gem_retire_work_handler);
4588         init_completion(&dev_priv->error_completion);
4589         spin_lock(&shrink_list_lock);
4590         list_add(&dev_priv->mm.shrink_list, &shrink_list);
4591         spin_unlock(&shrink_list_lock);
4592
4593         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4594         if (IS_GEN3(dev)) {
4595                 u32 tmp = I915_READ(MI_ARB_STATE);
4596                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4597                         /* arb state is a masked write, so set bit + bit in mask */
4598                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4599                         I915_WRITE(MI_ARB_STATE, tmp);
4600                 }
4601         }
4602
4603         /* Old X drivers will take 0-2 for front, back, depth buffers */
4604         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4605                 dev_priv->fence_reg_start = 3;
4606
4607         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4608                 dev_priv->num_fence_regs = 16;
4609         else
4610                 dev_priv->num_fence_regs = 8;
4611
4612         /* Initialize fence registers to zero */
4613         switch (INTEL_INFO(dev)->gen) {
4614         case 6:
4615                 for (i = 0; i < 16; i++)
4616                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
4617                 break;
4618         case 5:
4619         case 4:
4620                 for (i = 0; i < 16; i++)
4621                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4622                 break;
4623         case 3:
4624                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4625                         for (i = 0; i < 8; i++)
4626                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4627         case 2:
4628                 for (i = 0; i < 8; i++)
4629                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4630                 break;
4631         }
4632         i915_gem_detect_bit_6_swizzle(dev);
4633         init_waitqueue_head(&dev_priv->pending_flip_queue);
4634 }
4635
4636 /*
4637  * Create a physically contiguous memory object for this object
4638  * e.g. for cursor + overlay regs
4639  */
4640 static int i915_gem_init_phys_object(struct drm_device *dev,
4641                                      int id, int size, int align)
4642 {
4643         drm_i915_private_t *dev_priv = dev->dev_private;
4644         struct drm_i915_gem_phys_object *phys_obj;
4645         int ret;
4646
4647         if (dev_priv->mm.phys_objs[id - 1] || !size)
4648                 return 0;
4649
4650         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4651         if (!phys_obj)
4652                 return -ENOMEM;
4653
4654         phys_obj->id = id;
4655
4656         phys_obj->handle = drm_pci_alloc(dev, size, align);
4657         if (!phys_obj->handle) {
4658                 ret = -ENOMEM;
4659                 goto kfree_obj;
4660         }
4661 #ifdef CONFIG_X86
4662         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4663 #endif
4664
4665         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4666
4667         return 0;
4668 kfree_obj:
4669         kfree(phys_obj);
4670         return ret;
4671 }
4672
4673 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4674 {
4675         drm_i915_private_t *dev_priv = dev->dev_private;
4676         struct drm_i915_gem_phys_object *phys_obj;
4677
4678         if (!dev_priv->mm.phys_objs[id - 1])
4679                 return;
4680
4681         phys_obj = dev_priv->mm.phys_objs[id - 1];
4682         if (phys_obj->cur_obj) {
4683                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4684         }
4685
4686 #ifdef CONFIG_X86
4687         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4688 #endif
4689         drm_pci_free(dev, phys_obj->handle);
4690         kfree(phys_obj);
4691         dev_priv->mm.phys_objs[id - 1] = NULL;
4692 }
4693
4694 void i915_gem_free_all_phys_object(struct drm_device *dev)
4695 {
4696         int i;
4697
4698         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4699                 i915_gem_free_phys_object(dev, i);
4700 }
4701
4702 void i915_gem_detach_phys_object(struct drm_device *dev,
4703                                  struct drm_gem_object *obj)
4704 {
4705         struct drm_i915_gem_object *obj_priv;
4706         int i;
4707         int ret;
4708         int page_count;
4709
4710         obj_priv = to_intel_bo(obj);
4711         if (!obj_priv->phys_obj)
4712                 return;
4713
4714         ret = i915_gem_object_get_pages(obj, 0);
4715         if (ret)
4716                 goto out;
4717
4718         page_count = obj->size / PAGE_SIZE;
4719
4720         for (i = 0; i < page_count; i++) {
4721                 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4722                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4723
4724                 memcpy(dst, src, PAGE_SIZE);
4725                 kunmap_atomic(dst, KM_USER0);
4726         }
4727         drm_clflush_pages(obj_priv->pages, page_count);
4728         drm_agp_chipset_flush(dev);
4729
4730         i915_gem_object_put_pages(obj);
4731 out:
4732         obj_priv->phys_obj->cur_obj = NULL;
4733         obj_priv->phys_obj = NULL;
4734 }
4735
4736 int
4737 i915_gem_attach_phys_object(struct drm_device *dev,
4738                             struct drm_gem_object *obj,
4739                             int id,
4740                             int align)
4741 {
4742         drm_i915_private_t *dev_priv = dev->dev_private;
4743         struct drm_i915_gem_object *obj_priv;
4744         int ret = 0;
4745         int page_count;
4746         int i;
4747
4748         if (id > I915_MAX_PHYS_OBJECT)
4749                 return -EINVAL;
4750
4751         obj_priv = to_intel_bo(obj);
4752
4753         if (obj_priv->phys_obj) {
4754                 if (obj_priv->phys_obj->id == id)
4755                         return 0;
4756                 i915_gem_detach_phys_object(dev, obj);
4757         }
4758
4759         /* create a new object */
4760         if (!dev_priv->mm.phys_objs[id - 1]) {
4761                 ret = i915_gem_init_phys_object(dev, id,
4762                                                 obj->size, align);
4763                 if (ret) {
4764                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4765                         goto out;
4766                 }
4767         }
4768
4769         /* bind to the object */
4770         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4771         obj_priv->phys_obj->cur_obj = obj;
4772
4773         ret = i915_gem_object_get_pages(obj, 0);
4774         if (ret) {
4775                 DRM_ERROR("failed to get page list\n");
4776                 goto out;
4777         }
4778
4779         page_count = obj->size / PAGE_SIZE;
4780
4781         for (i = 0; i < page_count; i++) {
4782                 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4783                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4784
4785                 memcpy(dst, src, PAGE_SIZE);
4786                 kunmap_atomic(src, KM_USER0);
4787         }
4788
4789         i915_gem_object_put_pages(obj);
4790
4791         return 0;
4792 out:
4793         return ret;
4794 }
4795
4796 static int
4797 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4798                      struct drm_i915_gem_pwrite *args,
4799                      struct drm_file *file_priv)
4800 {
4801         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4802         void *obj_addr;
4803         int ret;
4804         char __user *user_data;
4805
4806         user_data = (char __user *) (uintptr_t) args->data_ptr;
4807         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4808
4809         DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4810         ret = copy_from_user(obj_addr, user_data, args->size);
4811         if (ret)
4812                 return -EFAULT;
4813
4814         drm_agp_chipset_flush(dev);
4815         return 0;
4816 }
4817
4818 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4819 {
4820         struct drm_i915_file_private *file_priv = file->driver_priv;
4821
4822         /* Clean up our request list when the client is going away, so that
4823          * later retire_requests won't dereference our soon-to-be-gone
4824          * file_priv.
4825          */
4826         spin_lock(&file_priv->mm.lock);
4827         while (!list_empty(&file_priv->mm.request_list)) {
4828                 struct drm_i915_gem_request *request;
4829
4830                 request = list_first_entry(&file_priv->mm.request_list,
4831                                            struct drm_i915_gem_request,
4832                                            client_list);
4833                 list_del(&request->client_list);
4834                 request->file_priv = NULL;
4835         }
4836         spin_unlock(&file_priv->mm.lock);
4837 }
4838
4839 static int
4840 i915_gpu_is_active(struct drm_device *dev)
4841 {
4842         drm_i915_private_t *dev_priv = dev->dev_private;
4843         int lists_empty;
4844
4845         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4846                       list_empty(&dev_priv->render_ring.active_list) &&
4847                       list_empty(&dev_priv->bsd_ring.active_list);
4848
4849         return !lists_empty;
4850 }
4851
4852 static int
4853 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
4854 {
4855         drm_i915_private_t *dev_priv, *next_dev;
4856         struct drm_i915_gem_object *obj_priv, *next_obj;
4857         int cnt = 0;
4858         int would_deadlock = 1;
4859
4860         /* "fast-path" to count number of available objects */
4861         if (nr_to_scan == 0) {
4862                 spin_lock(&shrink_list_lock);
4863                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4864                         struct drm_device *dev = dev_priv->dev;
4865
4866                         if (mutex_trylock(&dev->struct_mutex)) {
4867                                 list_for_each_entry(obj_priv,
4868                                                     &dev_priv->mm.inactive_list,
4869                                                     mm_list)
4870                                         cnt++;
4871                                 mutex_unlock(&dev->struct_mutex);
4872                         }
4873                 }
4874                 spin_unlock(&shrink_list_lock);
4875
4876                 return (cnt / 100) * sysctl_vfs_cache_pressure;
4877         }
4878
4879         spin_lock(&shrink_list_lock);
4880
4881 rescan:
4882         /* first scan for clean buffers */
4883         list_for_each_entry_safe(dev_priv, next_dev,
4884                                  &shrink_list, mm.shrink_list) {
4885                 struct drm_device *dev = dev_priv->dev;
4886
4887                 if (! mutex_trylock(&dev->struct_mutex))
4888                         continue;
4889
4890                 spin_unlock(&shrink_list_lock);
4891                 i915_gem_retire_requests(dev);
4892
4893                 list_for_each_entry_safe(obj_priv, next_obj,
4894                                          &dev_priv->mm.inactive_list,
4895                                          mm_list) {
4896                         if (i915_gem_object_is_purgeable(obj_priv)) {
4897                                 i915_gem_object_unbind(&obj_priv->base);
4898                                 if (--nr_to_scan <= 0)
4899                                         break;
4900                         }
4901                 }
4902
4903                 spin_lock(&shrink_list_lock);
4904                 mutex_unlock(&dev->struct_mutex);
4905
4906                 would_deadlock = 0;
4907
4908                 if (nr_to_scan <= 0)
4909                         break;
4910         }
4911
4912         /* second pass, evict/count anything still on the inactive list */
4913         list_for_each_entry_safe(dev_priv, next_dev,
4914                                  &shrink_list, mm.shrink_list) {
4915                 struct drm_device *dev = dev_priv->dev;
4916
4917                 if (! mutex_trylock(&dev->struct_mutex))
4918                         continue;
4919
4920                 spin_unlock(&shrink_list_lock);
4921
4922                 list_for_each_entry_safe(obj_priv, next_obj,
4923                                          &dev_priv->mm.inactive_list,
4924                                          mm_list) {
4925                         if (nr_to_scan > 0) {
4926                                 i915_gem_object_unbind(&obj_priv->base);
4927                                 nr_to_scan--;
4928                         } else
4929                                 cnt++;
4930                 }
4931
4932                 spin_lock(&shrink_list_lock);
4933                 mutex_unlock(&dev->struct_mutex);
4934
4935                 would_deadlock = 0;
4936         }
4937
4938         if (nr_to_scan) {
4939                 int active = 0;
4940
4941                 /*
4942                  * We are desperate for pages, so as a last resort, wait
4943                  * for the GPU to finish and discard whatever we can.
4944                  * This has a dramatic impact to reduce the number of
4945                  * OOM-killer events whilst running the GPU aggressively.
4946                  */
4947                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4948                         struct drm_device *dev = dev_priv->dev;
4949
4950                         if (!mutex_trylock(&dev->struct_mutex))
4951                                 continue;
4952
4953                         spin_unlock(&shrink_list_lock);
4954
4955                         if (i915_gpu_is_active(dev)) {
4956                                 i915_gpu_idle(dev);
4957                                 active++;
4958                         }
4959
4960                         spin_lock(&shrink_list_lock);
4961                         mutex_unlock(&dev->struct_mutex);
4962                 }
4963
4964                 if (active)
4965                         goto rescan;
4966         }
4967
4968         spin_unlock(&shrink_list_lock);
4969
4970         if (would_deadlock)
4971                 return -1;
4972         else if (cnt > 0)
4973                 return (cnt / 100) * sysctl_vfs_cache_pressure;
4974         else
4975                 return 0;
4976 }
4977
4978 static struct shrinker shrinker = {
4979         .shrink = i915_gem_shrink,
4980         .seeks = DEFAULT_SEEKS,
4981 };
4982
4983 __init void
4984 i915_gem_shrinker_init(void)
4985 {
4986     register_shrinker(&shrinker);
4987 }
4988
4989 __exit void
4990 i915_gem_shrinker_exit(void)
4991 {
4992     unregister_shrinker(&shrinker);
4993 }