drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 /* Really want an OS-independent resettable timer.  Would like to have
  35  * this loop run for (eg) 3 sec, but have the timer reset every time
  36  * the head pointer changes, so that EBUSY only happens if the ring
  37  * actually stalls for (eg) 3 seconds.
  38  */
  39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  40 {
  41         drm_i915_private_t *dev_priv = dev->dev_private;
  42         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  43         u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
  44         u32 last_acthd = I915_READ(acthd_reg);
  45         u32 acthd;
  46         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  47         int i;
  48
  49         for (i = 0; i < 100000; i++) {
  50                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  51                 acthd = I915_READ(acthd_reg);
  52                 ring->space = ring->head - (ring->tail + 8);
  53                 if (ring->space < 0)
  54                         ring->space += ring->Size;
  55                 if (ring->space >= n)
  56                         return 0;
  57
  58                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  59
  60                 if (ring->head != last_head)
  61                         i = 0;
  62                 if (acthd != last_acthd)
  63                         i = 0;
  64
  65                 last_head = ring->head;
  66                 last_acthd = acthd;
  67                 msleep_interruptible(10);
  68
  69         }
  70
  71         return -EBUSY;
  72 }
  73
  74 /**
  75  * Sets up the hardware status page for devices that need a physical address
  76  * in the register.
  77  */
  78 int i915_init_phys_hws(struct drm_device *dev)
  79 {
  80         drm_i915_private_t *dev_priv = dev->dev_private;
  81         /* Program Hardware Status Page */
  82         dev_priv->status_page_dmah =
  83                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  84
  85         if (!dev_priv->status_page_dmah) {
  86                 DRM_ERROR("Can not allocate hardware status page\n");
  87                 return -ENOMEM;
  88         }
  89         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
  90         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  91
  92         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  93
  94         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  95         DRM_DEBUG("Enabled hardware status page\n");
  96         return 0;
  97 }
  98
  99 /**
 100  * Frees the hardware status page, whether it's a physical address or a virtual
 101  * address set up by the X Server.
 102  */
 103 void i915_free_hws(struct drm_device *dev)
 104 {
 105         drm_i915_private_t *dev_priv = dev->dev_private;
 106         if (dev_priv->status_page_dmah) {
 107                 drm_pci_free(dev, dev_priv->status_page_dmah);
 108                 dev_priv->status_page_dmah = NULL;
 109         }
 110
 111         if (dev_priv->status_gfx_addr) {
 112                 dev_priv->status_gfx_addr = 0;
 113                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 114         }
 115
 116         /* Need to rewrite hardware status page */
 117         I915_WRITE(HWS_PGA, 0x1ffff000);
 118 }
 119
 120 void i915_kernel_lost_context(struct drm_device * dev)
 121 {
 122         drm_i915_private_t *dev_priv = dev->dev_private;
 123         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
 124
 125         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 126         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 127         ring->space = ring->head - (ring->tail + 8);
 128         if (ring->space < 0)
 129                 ring->space += ring->Size;
 130
 131         if (ring->head == ring->tail)
 132                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 133 }
 134
 135 static int i915_dma_cleanup(struct drm_device * dev)
 136 {
 137         drm_i915_private_t *dev_priv = dev->dev_private;
 138         /* Make sure interrupts are disabled here because the uninstall ioctl
 139          * may not have been called from userspace and after dev_private
 140          * is freed, it's too late.
 141          */
 142         if (dev->irq_enabled)
 143                 drm_irq_uninstall(dev);
 144
 145         if (dev_priv->ring.virtual_start) {
 146                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 147                 dev_priv->ring.virtual_start = 0;
 148                 dev_priv->ring.map.handle = 0;
 149                 dev_priv->ring.map.size = 0;
 150         }
 151
 152         /* Clear the HWS virtual address at teardown */
 153         if (I915_NEED_GFX_HWS(dev))
 154                 i915_free_hws(dev);
 155
 156         return 0;
 157 }
 158
 159 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 160 {
 161         drm_i915_private_t *dev_priv = dev->dev_private;
 162
 163         dev_priv->sarea = drm_getsarea(dev);
 164         if (!dev_priv->sarea) {
 165                 DRM_ERROR("can not find sarea!\n");
 166                 i915_dma_cleanup(dev);
 167                 return -EINVAL;
 168         }
 169
 170         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 171             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 172
 173         if (init->ring_size != 0) {
 174                 if (dev_priv->ring.ring_obj != NULL) {
 175                         i915_dma_cleanup(dev);
 176                         DRM_ERROR("Client tried to initialize ringbuffer in "
 177                                   "GEM mode\n");
 178                         return -EINVAL;
 179                 }
 180
 181                 dev_priv->ring.Size = init->ring_size;
 182                 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 183
 184                 dev_priv->ring.map.offset = init->ring_start;
 185                 dev_priv->ring.map.size = init->ring_size;
 186                 dev_priv->ring.map.type = 0;
 187                 dev_priv->ring.map.flags = 0;
 188                 dev_priv->ring.map.mtrr = 0;
 189
 190                 drm_core_ioremap(&dev_priv->ring.map, dev);
 191
 192                 if (dev_priv->ring.map.handle == NULL) {
 193                         i915_dma_cleanup(dev);
 194                         DRM_ERROR("can not ioremap virtual address for"
 195                                   " ring buffer\n");
 196                         return -ENOMEM;
 197                 }
 198         }
 199
 200         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 201
 202         dev_priv->cpp = init->cpp;
 203         dev_priv->back_offset = init->back_offset;
 204         dev_priv->front_offset = init->front_offset;
 205         dev_priv->current_page = 0;
 206         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 207
 208         /* Allow hardware batchbuffers unless told otherwise.
 209          */
 210         dev_priv->allow_batchbuffer = 1;
 211
 212         return 0;
 213 }
 214
 215 static int i915_dma_resume(struct drm_device * dev)
 216 {
 217         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 218
 219         DRM_DEBUG("%s\n", __func__);
 220
 221         if (!dev_priv->sarea) {
 222                 DRM_ERROR("can not find sarea!\n");
 223                 return -EINVAL;
 224         }
 225
 226         if (dev_priv->ring.map.handle == NULL) {
 227                 DRM_ERROR("can not ioremap virtual address for"
 228                           " ring buffer\n");
 229                 return -ENOMEM;
 230         }
 231
 232         /* Program Hardware Status Page */
 233         if (!dev_priv->hw_status_page) {
 234                 DRM_ERROR("Can not find hardware status page\n");
 235                 return -EINVAL;
 236         }
 237         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 238
 239         if (dev_priv->status_gfx_addr != 0)
 240                 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 241         else
 242                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 243         DRM_DEBUG("Enabled hardware status page\n");
 244
 245         return 0;
 246 }
 247
 248 static int i915_dma_init(struct drm_device *dev, void *data,
 249                          struct drm_file *file_priv)
 250 {
 251         drm_i915_init_t *init = data;
 252         int retcode = 0;
 253
 254         switch (init->func) {
 255         case I915_INIT_DMA:
 256                 retcode = i915_initialize(dev, init);
 257                 break;
 258         case I915_CLEANUP_DMA:
 259                 retcode = i915_dma_cleanup(dev);
 260                 break;
 261         case I915_RESUME_DMA:
 262                 retcode = i915_dma_resume(dev);
 263                 break;
 264         default:
 265                 retcode = -EINVAL;
 266                 break;
 267         }
 268
 269         return retcode;
 270 }
 271
 272 /* Implement basically the same security restrictions as hardware does
 273  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 274  *
 275  * Most of the calculations below involve calculating the size of a
 276  * particular instruction.  It's important to get the size right as
 277  * that tells us where the next instruction to check is.  Any illegal
 278  * instruction detected will be given a size of zero, which is a
 279  * signal to abort the rest of the buffer.
 280  */
 281 static int do_validate_cmd(int cmd)
 282 {
 283         switch (((cmd >> 29) & 0x7)) {
 284         case 0x0:
 285                 switch ((cmd >> 23) & 0x3f) {
 286                 case 0x0:
 287                         return 1;       /* MI_NOOP */
 288                 case 0x4:
 289                         return 1;       /* MI_FLUSH */
 290                 default:
 291                         return 0;       /* disallow everything else */
 292                 }
 293                 break;
 294         case 0x1:
 295                 return 0;       /* reserved */
 296         case 0x2:
 297                 return (cmd & 0xff) + 2;        /* 2d commands */
 298         case 0x3:
 299                 if (((cmd >> 24) & 0x1f) <= 0x18)
 300                         return 1;
 301
 302                 switch ((cmd >> 24) & 0x1f) {
 303                 case 0x1c:
 304                         return 1;
 305                 case 0x1d:
 306                         switch ((cmd >> 16) & 0xff) {
 307                         case 0x3:
 308                                 return (cmd & 0x1f) + 2;
 309                         case 0x4:
 310                                 return (cmd & 0xf) + 2;
 311                         default:
 312                                 return (cmd & 0xffff) + 2;
 313                         }
 314                 case 0x1e:
 315                         if (cmd & (1 << 23))
 316                                 return (cmd & 0xffff) + 1;
 317                         else
 318                                 return 1;
 319                 case 0x1f:
 320                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 321                                 return (cmd & 0x1ffff) + 2;
 322                         else if (cmd & (1 << 17))       /* indirect random */
 323                                 if ((cmd & 0xffff) == 0)
 324                                         return 0;       /* unknown length, too hard */
 325                                 else
 326                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 327                         else
 328                                 return 2;       /* indirect sequential */
 329                 default:
 330                         return 0;
 331                 }
 332         default:
 333                 return 0;
 334         }
 335
 336         return 0;
 337 }
 338
 339 static int validate_cmd(int cmd)
 340 {
 341         int ret = do_validate_cmd(cmd);
 342
 343 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 344
 345         return ret;
 346 }
 347
 348 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords)
 349 {
 350         drm_i915_private_t *dev_priv = dev->dev_private;
 351         int i;
 352         RING_LOCALS;
 353
 354         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 355                 return -EINVAL;
 356
 357         BEGIN_LP_RING((dwords+1)&~1);
 358
 359         for (i = 0; i < dwords;) {
 360                 int cmd, sz;
 361
 362                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 363                         return -EINVAL;
 364
 365                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 366                         return -EINVAL;
 367
 368                 OUT_RING(cmd);
 369
 370                 while (++i, --sz) {
 371                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 372                                                          sizeof(cmd))) {
 373                                 return -EINVAL;
 374                         }
 375                         OUT_RING(cmd);
 376                 }
 377         }
 378
 379         if (dwords & 1)
 380                 OUT_RING(0);
 381
 382         ADVANCE_LP_RING();
 383
 384         return 0;
 385 }
 386
 387 int
 388 i915_emit_box(struct drm_device *dev,
 389               struct drm_clip_rect __user *boxes,
 390               int i, int DR1, int DR4)
 391 {
 392         drm_i915_private_t *dev_priv = dev->dev_private;
 393         struct drm_clip_rect box;
 394         RING_LOCALS;
 395
 396         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 397                 return -EFAULT;
 398         }
 399
 400         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 401                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 402                           box.x1, box.y1, box.x2, box.y2);
 403                 return -EINVAL;
 404         }
 405
 406         if (IS_I965G(dev)) {
 407                 BEGIN_LP_RING(4);
 408                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 409                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 410                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 411                 OUT_RING(DR4);
 412                 ADVANCE_LP_RING();
 413         } else {
 414                 BEGIN_LP_RING(6);
 415                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 416                 OUT_RING(DR1);
 417                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 418                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 419                 OUT_RING(DR4);
 420                 OUT_RING(0);
 421                 ADVANCE_LP_RING();
 422         }
 423
 424         return 0;
 425 }
 426
 427 /* XXX: Emitting the counter should really be moved to part of the IRQ
 428  * emit. For now, do it in both places:
 429  */
 430
 431 static void i915_emit_breadcrumb(struct drm_device *dev)
 432 {
 433         drm_i915_private_t *dev_priv = dev->dev_private;
 434         RING_LOCALS;
 435
 436         dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
 437
 438         if (dev_priv->counter > 0x7FFFFFFFUL)
 439                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
 440
 441         BEGIN_LP_RING(4);
 442         OUT_RING(MI_STORE_DWORD_INDEX);
 443         OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
 444         OUT_RING(dev_priv->counter);
 445         OUT_RING(0);
 446         ADVANCE_LP_RING();
 447 }
 448
 449 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 450                                    drm_i915_cmdbuffer_t * cmd)
 451 {
 452         int nbox = cmd->num_cliprects;
 453         int i = 0, count, ret;
 454
 455         if (cmd->sz & 0x3) {
 456                 DRM_ERROR("alignment");
 457                 return -EINVAL;
 458         }
 459
 460         i915_kernel_lost_context(dev);
 461
 462         count = nbox ? nbox : 1;
 463
 464         for (i = 0; i < count; i++) {
 465                 if (i < nbox) {
 466                         ret = i915_emit_box(dev, cmd->cliprects, i,
 467                                             cmd->DR1, cmd->DR4);
 468                         if (ret)
 469                                 return ret;
 470                 }
 471
 472                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 473                 if (ret)
 474                         return ret;
 475         }
 476
 477         i915_emit_breadcrumb(dev);
 478         return 0;
 479 }
 480
 481 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 482                                      drm_i915_batchbuffer_t * batch)
 483 {
 484         drm_i915_private_t *dev_priv = dev->dev_private;
 485         struct drm_clip_rect __user *boxes = batch->cliprects;
 486         int nbox = batch->num_cliprects;
 487         int i = 0, count;
 488         RING_LOCALS;
 489
 490         if ((batch->start | batch->used) & 0x7) {
 491                 DRM_ERROR("alignment");
 492                 return -EINVAL;
 493         }
 494
 495         i915_kernel_lost_context(dev);
 496
 497         count = nbox ? nbox : 1;
 498
 499         for (i = 0; i < count; i++) {
 500                 if (i < nbox) {
 501                         int ret = i915_emit_box(dev, boxes, i,
 502                                                 batch->DR1, batch->DR4);
 503                         if (ret)
 504                                 return ret;
 505                 }
 506
 507                 if (!IS_I830(dev) && !IS_845G(dev)) {
 508                         BEGIN_LP_RING(2);
 509                         if (IS_I965G(dev)) {
 510                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 511                                 OUT_RING(batch->start);
 512                         } else {
 513                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 514                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 515                         }
 516                         ADVANCE_LP_RING();
 517                 } else {
 518                         BEGIN_LP_RING(4);
 519                         OUT_RING(MI_BATCH_BUFFER);
 520                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 521                         OUT_RING(batch->start + batch->used - 4);
 522                         OUT_RING(0);
 523                         ADVANCE_LP_RING();
 524                 }
 525         }
 526
 527         i915_emit_breadcrumb(dev);
 528
 529         return 0;
 530 }
 531
 532 static int i915_dispatch_flip(struct drm_device * dev)
 533 {
 534         drm_i915_private_t *dev_priv = dev->dev_private;
 535         RING_LOCALS;
 536
 537         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 538                   __func__,
 539                   dev_priv->current_page,
 540                   dev_priv->sarea_priv->pf_current_page);
 541
 542         i915_kernel_lost_context(dev);
 543
 544         BEGIN_LP_RING(2);
 545         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 546         OUT_RING(0);
 547         ADVANCE_LP_RING();
 548
 549         BEGIN_LP_RING(6);
 550         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 551         OUT_RING(0);
 552         if (dev_priv->current_page == 0) {
 553                 OUT_RING(dev_priv->back_offset);
 554                 dev_priv->current_page = 1;
 555         } else {
 556                 OUT_RING(dev_priv->front_offset);
 557                 dev_priv->current_page = 0;
 558         }
 559         OUT_RING(0);
 560         ADVANCE_LP_RING();
 561
 562         BEGIN_LP_RING(2);
 563         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 564         OUT_RING(0);
 565         ADVANCE_LP_RING();
 566
 567         dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 568
 569         BEGIN_LP_RING(4);
 570         OUT_RING(MI_STORE_DWORD_INDEX);
 571         OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
 572         OUT_RING(dev_priv->counter);
 573         OUT_RING(0);
 574         ADVANCE_LP_RING();
 575
 576         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 577         return 0;
 578 }
 579
 580 static int i915_quiescent(struct drm_device * dev)
 581 {
 582         drm_i915_private_t *dev_priv = dev->dev_private;
 583
 584         i915_kernel_lost_context(dev);
 585         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
 586 }
 587
 588 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 589                             struct drm_file *file_priv)
 590 {
 591         LOCK_TEST_WITH_RETURN(dev, file_priv);
 592
 593         return i915_quiescent(dev);
 594 }
 595
 596 static int i915_batchbuffer(struct drm_device *dev, void *data,
 597                             struct drm_file *file_priv)
 598 {
 599         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 600         u32 *hw_status = dev_priv->hw_status_page;
 601         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 602             dev_priv->sarea_priv;
 603         drm_i915_batchbuffer_t *batch = data;
 604         int ret;
 605
 606         if (!dev_priv->allow_batchbuffer) {
 607                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 608                 return -EINVAL;
 609         }
 610
 611         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 612                   batch->start, batch->used, batch->num_cliprects);
 613
 614         LOCK_TEST_WITH_RETURN(dev, file_priv);
 615
 616         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
 617                                                        batch->num_cliprects *
 618                                                        sizeof(struct drm_clip_rect)))
 619                 return -EFAULT;
 620
 621         ret = i915_dispatch_batchbuffer(dev, batch);
 622
 623         sarea_priv->last_dispatch = (int)hw_status[5];
 624         return ret;
 625 }
 626
 627 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 628                           struct drm_file *file_priv)
 629 {
 630         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 631         u32 *hw_status = dev_priv->hw_status_page;
 632         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 633             dev_priv->sarea_priv;
 634         drm_i915_cmdbuffer_t *cmdbuf = data;
 635         int ret;
 636
 637         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 638                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 639
 640         LOCK_TEST_WITH_RETURN(dev, file_priv);
 641
 642         if (cmdbuf->num_cliprects &&
 643             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
 644                                 cmdbuf->num_cliprects *
 645                                 sizeof(struct drm_clip_rect))) {
 646                 DRM_ERROR("Fault accessing cliprects\n");
 647                 return -EFAULT;
 648         }
 649
 650         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
 651         if (ret) {
 652                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 653                 return ret;
 654         }
 655
 656         sarea_priv->last_dispatch = (int)hw_status[5];
 657         return 0;
 658 }
 659
 660 static int i915_flip_bufs(struct drm_device *dev, void *data,
 661                           struct drm_file *file_priv)
 662 {
 663         DRM_DEBUG("%s\n", __func__);
 664
 665         LOCK_TEST_WITH_RETURN(dev, file_priv);
 666
 667         return i915_dispatch_flip(dev);
 668 }
 669
 670 static int i915_getparam(struct drm_device *dev, void *data,
 671                          struct drm_file *file_priv)
 672 {
 673         drm_i915_private_t *dev_priv = dev->dev_private;
 674         drm_i915_getparam_t *param = data;
 675         int value;
 676
 677         if (!dev_priv) {
 678                 DRM_ERROR("called with no initialization\n");
 679                 return -EINVAL;
 680         }
 681
 682         switch (param->param) {
 683         case I915_PARAM_IRQ_ACTIVE:
 684                 value = dev->pdev->irq ? 1 : 0;
 685                 break;
 686         case I915_PARAM_ALLOW_BATCHBUFFER:
 687                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 688                 break;
 689         case I915_PARAM_LAST_DISPATCH:
 690                 value = READ_BREADCRUMB(dev_priv);
 691                 break;
 692         case I915_PARAM_CHIPSET_ID:
 693                 value = dev->pci_device;
 694                 break;
 695         case I915_PARAM_HAS_GEM:
 696                 value = 1;
 697                 break;
 698         default:
 699                 DRM_ERROR("Unknown parameter %d\n", param->param);
 700                 return -EINVAL;
 701         }
 702
 703         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 704                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 705                 return -EFAULT;
 706         }
 707
 708         return 0;
 709 }
 710
 711 static int i915_setparam(struct drm_device *dev, void *data,
 712                          struct drm_file *file_priv)
 713 {
 714         drm_i915_private_t *dev_priv = dev->dev_private;
 715         drm_i915_setparam_t *param = data;
 716
 717         if (!dev_priv) {
 718                 DRM_ERROR("called with no initialization\n");
 719                 return -EINVAL;
 720         }
 721
 722         switch (param->param) {
 723         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 724                 break;
 725         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 726                 dev_priv->tex_lru_log_granularity = param->value;
 727                 break;
 728         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 729                 dev_priv->allow_batchbuffer = param->value;
 730                 break;
 731         default:
 732                 DRM_ERROR("unknown parameter %d\n", param->param);
 733                 return -EINVAL;
 734         }
 735
 736         return 0;
 737 }
 738
 739 static int i915_set_status_page(struct drm_device *dev, void *data,
 740                                 struct drm_file *file_priv)
 741 {
 742         drm_i915_private_t *dev_priv = dev->dev_private;
 743         drm_i915_hws_addr_t *hws = data;
 744
 745         if (!I915_NEED_GFX_HWS(dev))
 746                 return -EINVAL;
 747
 748         if (!dev_priv) {
 749                 DRM_ERROR("called with no initialization\n");
 750                 return -EINVAL;
 751         }
 752
 753         printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr);
 754
 755         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
 756
 757         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 758         dev_priv->hws_map.size = 4*1024;
 759         dev_priv->hws_map.type = 0;
 760         dev_priv->hws_map.flags = 0;
 761         dev_priv->hws_map.mtrr = 0;
 762
 763         drm_core_ioremap(&dev_priv->hws_map, dev);
 764         if (dev_priv->hws_map.handle == NULL) {
 765                 i915_dma_cleanup(dev);
 766                 dev_priv->status_gfx_addr = 0;
 767                 DRM_ERROR("can not ioremap virtual address for"
 768                                 " G33 hw status page\n");
 769                 return -ENOMEM;
 770         }
 771         dev_priv->hw_status_page = dev_priv->hws_map.handle;
 772
 773         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 774         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 775         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
 776                         dev_priv->status_gfx_addr);
 777         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
 778         return 0;
 779 }
 780
 781 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 782 {
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784         unsigned long base, size;
 785         int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
 786
 787         /* i915 has 4 more counters */
 788         dev->counters += 4;
 789         dev->types[6] = _DRM_STAT_IRQ;
 790         dev->types[7] = _DRM_STAT_PRIMARY;
 791         dev->types[8] = _DRM_STAT_SECONDARY;
 792         dev->types[9] = _DRM_STAT_DMA;
 793
 794         dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
 795         if (dev_priv == NULL)
 796                 return -ENOMEM;
 797
 798         memset(dev_priv, 0, sizeof(drm_i915_private_t));
 799
 800         dev->dev_private = (void *)dev_priv;
 801         dev_priv->dev = dev;
 802
 803         /* Add register map (needed for suspend/resume) */
 804         base = drm_get_resource_start(dev, mmio_bar);
 805         size = drm_get_resource_len(dev, mmio_bar);
 806
 807         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
 808                          _DRM_KERNEL | _DRM_DRIVER,
 809                          &dev_priv->mmio_map);
 810
 811         i915_gem_load(dev);
 812
 813         /* Init HWS */
 814         if (!I915_NEED_GFX_HWS(dev)) {
 815                 ret = i915_init_phys_hws(dev);
 816                 if (ret != 0)
 817                         return ret;
 818         }
 819
 820         /* On the 945G/GM, the chipset reports the MSI capability on the
 821          * integrated graphics even though the support isn't actually there
 822          * according to the published specs.  It doesn't appear to function
 823          * correctly in testing on 945G.
 824          * This may be a side effect of MSI having been made available for PEG
 825          * and the registers being closely associated.
 826          */
 827         if (!IS_I945G(dev) && !IS_I945GM(dev))
 828                 if (pci_enable_msi(dev->pdev))
 829                         DRM_ERROR("failed to enable MSI\n");
 830
 831         intel_opregion_init(dev);
 832
 833         spin_lock_init(&dev_priv->user_irq_lock);
 834
 835         return ret;
 836 }
 837
 838 int i915_driver_unload(struct drm_device *dev)
 839 {
 840         struct drm_i915_private *dev_priv = dev->dev_private;
 841
 842         if (dev->pdev->msi_enabled)
 843                 pci_disable_msi(dev->pdev);
 844
 845         i915_free_hws(dev);
 846
 847         if (dev_priv->mmio_map)
 848                 drm_rmmap(dev, dev_priv->mmio_map);
 849
 850         intel_opregion_free(dev);
 851
 852         drm_free(dev->dev_private, sizeof(drm_i915_private_t),
 853                  DRM_MEM_DRIVER);
 854
 855         return 0;
 856 }
 857
 858 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
 859 {
 860         struct drm_i915_file_private *i915_file_priv;
 861
 862         DRM_DEBUG("\n");
 863         i915_file_priv = (struct drm_i915_file_private *)
 864             drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
 865
 866         if (!i915_file_priv)
 867                 return -ENOMEM;
 868
 869         file_priv->driver_priv = i915_file_priv;
 870
 871         i915_file_priv->mm.last_gem_seqno = 0;
 872         i915_file_priv->mm.last_gem_throttle_seqno = 0;
 873
 874         return 0;
 875 }
 876
 877 void i915_driver_lastclose(struct drm_device * dev)
 878 {
 879         drm_i915_private_t *dev_priv = dev->dev_private;
 880
 881         if (!dev_priv)
 882                 return;
 883
 884         i915_gem_lastclose(dev);
 885
 886         if (dev_priv->agp_heap)
 887                 i915_mem_takedown(&(dev_priv->agp_heap));
 888
 889         i915_dma_cleanup(dev);
 890 }
 891
 892 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
 893 {
 894         drm_i915_private_t *dev_priv = dev->dev_private;
 895         i915_mem_release(dev, file_priv, dev_priv->agp_heap);
 896 }
 897
 898 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
 899 {
 900         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
 901
 902         drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
 903 }
 904
 905 struct drm_ioctl_desc i915_ioctls[] = {
 906         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 907         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
 908         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
 909         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
 910         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
 911         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
 912         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
 913         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 914         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
 915         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
 916         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 917         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
 918         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
 919         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
 920         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
 921         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
 922         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
 923         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH),
 924         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
 925         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
 926         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
 927         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
 928         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
 929         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH),
 930         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH),
 931         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
 932         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
 933         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
 934         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
 935         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
 936         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
 937         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
 938         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
 939 };
 940
 941 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 942
 943 /**
 944  * Determine if the device really is AGP or not.
 945  *
 946  * All Intel graphics chipsets are treated as AGP, even if they are really
 947  * PCI-e.
 948  *
 949  * \param dev   The device to be tested.
 950  *
 951  * \returns
 952  * A value of 1 is always retured to indictate every i9x5 is AGP.
 953  */
 954 int i915_driver_device_is_agp(struct drm_device * dev)
 955 {
 956         return 1;
 957 }