drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include <linux/vgaarb.h>
  38 #include <linux/acpi.h>
  39 #include <linux/pnp.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/slab.h>
  42
  43
  44 /**
  45  * Sets up the hardware status page for devices that need a physical address
  46  * in the register.
  47  */
  48 static int i915_init_phys_hws(struct drm_device *dev)
  49 {
  50         drm_i915_private_t *dev_priv = dev->dev_private;
  51         /* Program Hardware Status Page */
  52         dev_priv->status_page_dmah =
  53                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  54
  55         if (!dev_priv->status_page_dmah) {
  56                 DRM_ERROR("Can not allocate hardware status page\n");
  57                 return -ENOMEM;
  58         }
  59         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
  60         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  61
  62         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  63
  64         if (IS_I965G(dev))
  65                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
  66                                              0xf0;
  67
  68         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  69         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  70         return 0;
  71 }
  72
  73 /**
  74  * Frees the hardware status page, whether it's a physical address or a virtual
  75  * address set up by the X Server.
  76  */
  77 static void i915_free_hws(struct drm_device *dev)
  78 {
  79         drm_i915_private_t *dev_priv = dev->dev_private;
  80         if (dev_priv->status_page_dmah) {
  81                 drm_pci_free(dev, dev_priv->status_page_dmah);
  82                 dev_priv->status_page_dmah = NULL;
  83         }
  84
  85         if (dev_priv->status_gfx_addr) {
  86                 dev_priv->status_gfx_addr = 0;
  87                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
  88         }
  89
  90         /* Need to rewrite hardware status page */
  91         I915_WRITE(HWS_PGA, 0x1ffff000);
  92 }
  93
  94 void i915_kernel_lost_context(struct drm_device * dev)
  95 {
  96         drm_i915_private_t *dev_priv = dev->dev_private;
  97         struct drm_i915_master_private *master_priv;
  98         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  99
 100         /*
 101          * We should never lose context on the ring with modesetting
 102          * as we don't expose it to userspace
 103          */
 104         if (drm_core_check_feature(dev, DRIVER_MODESET))
 105                 return;
 106
 107         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 108         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 109         ring->space = ring->head - (ring->tail + 8);
 110         if (ring->space < 0)
 111                 ring->space += ring->Size;
 112
 113         if (!dev->primary->master)
 114                 return;
 115
 116         master_priv = dev->primary->master->driver_priv;
 117         if (ring->head == ring->tail && master_priv->sarea_priv)
 118                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 119 }
 120
 121 static int i915_dma_cleanup(struct drm_device * dev)
 122 {
 123         drm_i915_private_t *dev_priv = dev->dev_private;
 124         /* Make sure interrupts are disabled here because the uninstall ioctl
 125          * may not have been called from userspace and after dev_private
 126          * is freed, it's too late.
 127          */
 128         if (dev->irq_enabled)
 129                 drm_irq_uninstall(dev);
 130
 131         if (dev_priv->ring.virtual_start) {
 132                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 133                 dev_priv->ring.virtual_start = NULL;
 134                 dev_priv->ring.map.handle = NULL;
 135                 dev_priv->ring.map.size = 0;
 136         }
 137
 138         /* Clear the HWS virtual address at teardown */
 139         if (I915_NEED_GFX_HWS(dev))
 140                 i915_free_hws(dev);
 141
 142         return 0;
 143 }
 144
 145 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 146 {
 147         drm_i915_private_t *dev_priv = dev->dev_private;
 148         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 149
 150         master_priv->sarea = drm_getsarea(dev);
 151         if (master_priv->sarea) {
 152                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 153                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 154         } else {
 155                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 156         }
 157
 158         if (init->ring_size != 0) {
 159                 if (dev_priv->ring.ring_obj != NULL) {
 160                         i915_dma_cleanup(dev);
 161                         DRM_ERROR("Client tried to initialize ringbuffer in "
 162                                   "GEM mode\n");
 163                         return -EINVAL;
 164                 }
 165
 166                 dev_priv->ring.Size = init->ring_size;
 167
 168                 dev_priv->ring.map.offset = init->ring_start;
 169                 dev_priv->ring.map.size = init->ring_size;
 170                 dev_priv->ring.map.type = 0;
 171                 dev_priv->ring.map.flags = 0;
 172                 dev_priv->ring.map.mtrr = 0;
 173
 174                 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
 175
 176                 if (dev_priv->ring.map.handle == NULL) {
 177                         i915_dma_cleanup(dev);
 178                         DRM_ERROR("can not ioremap virtual address for"
 179                                   " ring buffer\n");
 180                         return -ENOMEM;
 181                 }
 182         }
 183
 184         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 185
 186         dev_priv->cpp = init->cpp;
 187         dev_priv->back_offset = init->back_offset;
 188         dev_priv->front_offset = init->front_offset;
 189         dev_priv->current_page = 0;
 190         if (master_priv->sarea_priv)
 191                 master_priv->sarea_priv->pf_current_page = 0;
 192
 193         /* Allow hardware batchbuffers unless told otherwise.
 194          */
 195         dev_priv->allow_batchbuffer = 1;
 196
 197         return 0;
 198 }
 199
 200 static int i915_dma_resume(struct drm_device * dev)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203
 204         DRM_DEBUG_DRIVER("%s\n", __func__);
 205
 206         if (dev_priv->ring.map.handle == NULL) {
 207                 DRM_ERROR("can not ioremap virtual address for"
 208                           " ring buffer\n");
 209                 return -ENOMEM;
 210         }
 211
 212         /* Program Hardware Status Page */
 213         if (!dev_priv->hw_status_page) {
 214                 DRM_ERROR("Can not find hardware status page\n");
 215                 return -EINVAL;
 216         }
 217         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 218                                 dev_priv->hw_status_page);
 219
 220         if (dev_priv->status_gfx_addr != 0)
 221                 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 222         else
 223                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 224         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 225
 226         return 0;
 227 }
 228
 229 static int i915_dma_init(struct drm_device *dev, void *data,
 230                          struct drm_file *file_priv)
 231 {
 232         drm_i915_init_t *init = data;
 233         int retcode = 0;
 234
 235         switch (init->func) {
 236         case I915_INIT_DMA:
 237                 retcode = i915_initialize(dev, init);
 238                 break;
 239         case I915_CLEANUP_DMA:
 240                 retcode = i915_dma_cleanup(dev);
 241                 break;
 242         case I915_RESUME_DMA:
 243                 retcode = i915_dma_resume(dev);
 244                 break;
 245         default:
 246                 retcode = -EINVAL;
 247                 break;
 248         }
 249
 250         return retcode;
 251 }
 252
 253 /* Implement basically the same security restrictions as hardware does
 254  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 255  *
 256  * Most of the calculations below involve calculating the size of a
 257  * particular instruction.  It's important to get the size right as
 258  * that tells us where the next instruction to check is.  Any illegal
 259  * instruction detected will be given a size of zero, which is a
 260  * signal to abort the rest of the buffer.
 261  */
 262 static int do_validate_cmd(int cmd)
 263 {
 264         switch (((cmd >> 29) & 0x7)) {
 265         case 0x0:
 266                 switch ((cmd >> 23) & 0x3f) {
 267                 case 0x0:
 268                         return 1;       /* MI_NOOP */
 269                 case 0x4:
 270                         return 1;       /* MI_FLUSH */
 271                 default:
 272                         return 0;       /* disallow everything else */
 273                 }
 274                 break;
 275         case 0x1:
 276                 return 0;       /* reserved */
 277         case 0x2:
 278                 return (cmd & 0xff) + 2;        /* 2d commands */
 279         case 0x3:
 280                 if (((cmd >> 24) & 0x1f) <= 0x18)
 281                         return 1;
 282
 283                 switch ((cmd >> 24) & 0x1f) {
 284                 case 0x1c:
 285                         return 1;
 286                 case 0x1d:
 287                         switch ((cmd >> 16) & 0xff) {
 288                         case 0x3:
 289                                 return (cmd & 0x1f) + 2;
 290                         case 0x4:
 291                                 return (cmd & 0xf) + 2;
 292                         default:
 293                                 return (cmd & 0xffff) + 2;
 294                         }
 295                 case 0x1e:
 296                         if (cmd & (1 << 23))
 297                                 return (cmd & 0xffff) + 1;
 298                         else
 299                                 return 1;
 300                 case 0x1f:
 301                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 302                                 return (cmd & 0x1ffff) + 2;
 303                         else if (cmd & (1 << 17))       /* indirect random */
 304                                 if ((cmd & 0xffff) == 0)
 305                                         return 0;       /* unknown length, too hard */
 306                                 else
 307                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 308                         else
 309                                 return 2;       /* indirect sequential */
 310                 default:
 311                         return 0;
 312                 }
 313         default:
 314                 return 0;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static int validate_cmd(int cmd)
 321 {
 322         int ret = do_validate_cmd(cmd);
 323
 324 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 325
 326         return ret;
 327 }
 328
 329 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 330 {
 331         drm_i915_private_t *dev_priv = dev->dev_private;
 332         int i;
 333         RING_LOCALS;
 334
 335         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 336                 return -EINVAL;
 337
 338         BEGIN_LP_RING((dwords+1)&~1);
 339
 340         for (i = 0; i < dwords;) {
 341                 int cmd, sz;
 342
 343                 cmd = buffer[i];
 344
 345                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 346                         return -EINVAL;
 347
 348                 OUT_RING(cmd);
 349
 350                 while (++i, --sz) {
 351                         OUT_RING(buffer[i]);
 352                 }
 353         }
 354
 355         if (dwords & 1)
 356                 OUT_RING(0);
 357
 358         ADVANCE_LP_RING();
 359
 360         return 0;
 361 }
 362
 363 int
 364 i915_emit_box(struct drm_device *dev,
 365               struct drm_clip_rect *boxes,
 366               int i, int DR1, int DR4)
 367 {
 368         drm_i915_private_t *dev_priv = dev->dev_private;
 369         struct drm_clip_rect box = boxes[i];
 370         RING_LOCALS;
 371
 372         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 373                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 374                           box.x1, box.y1, box.x2, box.y2);
 375                 return -EINVAL;
 376         }
 377
 378         if (IS_I965G(dev)) {
 379                 BEGIN_LP_RING(4);
 380                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 381                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 382                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 383                 OUT_RING(DR4);
 384                 ADVANCE_LP_RING();
 385         } else {
 386                 BEGIN_LP_RING(6);
 387                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 388                 OUT_RING(DR1);
 389                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 390                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 391                 OUT_RING(DR4);
 392                 OUT_RING(0);
 393                 ADVANCE_LP_RING();
 394         }
 395
 396         return 0;
 397 }
 398
 399 /* XXX: Emitting the counter should really be moved to part of the IRQ
 400  * emit. For now, do it in both places:
 401  */
 402
 403 static void i915_emit_breadcrumb(struct drm_device *dev)
 404 {
 405         drm_i915_private_t *dev_priv = dev->dev_private;
 406         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 407         RING_LOCALS;
 408
 409         dev_priv->counter++;
 410         if (dev_priv->counter > 0x7FFFFFFFUL)
 411                 dev_priv->counter = 0;
 412         if (master_priv->sarea_priv)
 413                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 414
 415         BEGIN_LP_RING(4);
 416         OUT_RING(MI_STORE_DWORD_INDEX);
 417         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 418         OUT_RING(dev_priv->counter);
 419         OUT_RING(0);
 420         ADVANCE_LP_RING();
 421 }
 422
 423 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 424                                    drm_i915_cmdbuffer_t *cmd,
 425                                    struct drm_clip_rect *cliprects,
 426                                    void *cmdbuf)
 427 {
 428         int nbox = cmd->num_cliprects;
 429         int i = 0, count, ret;
 430
 431         if (cmd->sz & 0x3) {
 432                 DRM_ERROR("alignment");
 433                 return -EINVAL;
 434         }
 435
 436         i915_kernel_lost_context(dev);
 437
 438         count = nbox ? nbox : 1;
 439
 440         for (i = 0; i < count; i++) {
 441                 if (i < nbox) {
 442                         ret = i915_emit_box(dev, cliprects, i,
 443                                             cmd->DR1, cmd->DR4);
 444                         if (ret)
 445                                 return ret;
 446                 }
 447
 448                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 449                 if (ret)
 450                         return ret;
 451         }
 452
 453         i915_emit_breadcrumb(dev);
 454         return 0;
 455 }
 456
 457 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 458                                      drm_i915_batchbuffer_t * batch,
 459                                      struct drm_clip_rect *cliprects)
 460 {
 461         drm_i915_private_t *dev_priv = dev->dev_private;
 462         int nbox = batch->num_cliprects;
 463         int i = 0, count;
 464         RING_LOCALS;
 465
 466         if ((batch->start | batch->used) & 0x7) {
 467                 DRM_ERROR("alignment");
 468                 return -EINVAL;
 469         }
 470
 471         i915_kernel_lost_context(dev);
 472
 473         count = nbox ? nbox : 1;
 474
 475         for (i = 0; i < count; i++) {
 476                 if (i < nbox) {
 477                         int ret = i915_emit_box(dev, cliprects, i,
 478                                                 batch->DR1, batch->DR4);
 479                         if (ret)
 480                                 return ret;
 481                 }
 482
 483                 if (!IS_I830(dev) && !IS_845G(dev)) {
 484                         BEGIN_LP_RING(2);
 485                         if (IS_I965G(dev)) {
 486                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 487                                 OUT_RING(batch->start);
 488                         } else {
 489                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 490                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 491                         }
 492                         ADVANCE_LP_RING();
 493                 } else {
 494                         BEGIN_LP_RING(4);
 495                         OUT_RING(MI_BATCH_BUFFER);
 496                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 497                         OUT_RING(batch->start + batch->used - 4);
 498                         OUT_RING(0);
 499                         ADVANCE_LP_RING();
 500                 }
 501         }
 502
 503         i915_emit_breadcrumb(dev);
 504
 505         return 0;
 506 }
 507
 508 static int i915_dispatch_flip(struct drm_device * dev)
 509 {
 510         drm_i915_private_t *dev_priv = dev->dev_private;
 511         struct drm_i915_master_private *master_priv =
 512                 dev->primary->master->driver_priv;
 513         RING_LOCALS;
 514
 515         if (!master_priv->sarea_priv)
 516                 return -EINVAL;
 517
 518         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 519                           __func__,
 520                          dev_priv->current_page,
 521                          master_priv->sarea_priv->pf_current_page);
 522
 523         i915_kernel_lost_context(dev);
 524
 525         BEGIN_LP_RING(2);
 526         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 527         OUT_RING(0);
 528         ADVANCE_LP_RING();
 529
 530         BEGIN_LP_RING(6);
 531         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 532         OUT_RING(0);
 533         if (dev_priv->current_page == 0) {
 534                 OUT_RING(dev_priv->back_offset);
 535                 dev_priv->current_page = 1;
 536         } else {
 537                 OUT_RING(dev_priv->front_offset);
 538                 dev_priv->current_page = 0;
 539         }
 540         OUT_RING(0);
 541         ADVANCE_LP_RING();
 542
 543         BEGIN_LP_RING(2);
 544         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 545         OUT_RING(0);
 546         ADVANCE_LP_RING();
 547
 548         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 549
 550         BEGIN_LP_RING(4);
 551         OUT_RING(MI_STORE_DWORD_INDEX);
 552         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 553         OUT_RING(dev_priv->counter);
 554         OUT_RING(0);
 555         ADVANCE_LP_RING();
 556
 557         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 558         return 0;
 559 }
 560
 561 static int i915_quiescent(struct drm_device * dev)
 562 {
 563         drm_i915_private_t *dev_priv = dev->dev_private;
 564
 565         i915_kernel_lost_context(dev);
 566         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
 567 }
 568
 569 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 570                             struct drm_file *file_priv)
 571 {
 572         int ret;
 573
 574         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 575
 576         mutex_lock(&dev->struct_mutex);
 577         ret = i915_quiescent(dev);
 578         mutex_unlock(&dev->struct_mutex);
 579
 580         return ret;
 581 }
 582
 583 static int i915_batchbuffer(struct drm_device *dev, void *data,
 584                             struct drm_file *file_priv)
 585 {
 586         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 587         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 588         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 589             master_priv->sarea_priv;
 590         drm_i915_batchbuffer_t *batch = data;
 591         int ret;
 592         struct drm_clip_rect *cliprects = NULL;
 593
 594         if (!dev_priv->allow_batchbuffer) {
 595                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 596                 return -EINVAL;
 597         }
 598
 599         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 600                         batch->start, batch->used, batch->num_cliprects);
 601
 602         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 603
 604         if (batch->num_cliprects < 0)
 605                 return -EINVAL;
 606
 607         if (batch->num_cliprects) {
 608                 cliprects = kcalloc(batch->num_cliprects,
 609                                     sizeof(struct drm_clip_rect),
 610                                     GFP_KERNEL);
 611                 if (cliprects == NULL)
 612                         return -ENOMEM;
 613
 614                 ret = copy_from_user(cliprects, batch->cliprects,
 615                                      batch->num_cliprects *
 616                                      sizeof(struct drm_clip_rect));
 617                 if (ret != 0)
 618                         goto fail_free;
 619         }
 620
 621         mutex_lock(&dev->struct_mutex);
 622         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 623         mutex_unlock(&dev->struct_mutex);
 624
 625         if (sarea_priv)
 626                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 627
 628 fail_free:
 629         kfree(cliprects);
 630
 631         return ret;
 632 }
 633
 634 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 635                           struct drm_file *file_priv)
 636 {
 637         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 638         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 639         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 640             master_priv->sarea_priv;
 641         drm_i915_cmdbuffer_t *cmdbuf = data;
 642         struct drm_clip_rect *cliprects = NULL;
 643         void *batch_data;
 644         int ret;
 645
 646         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 647                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 648
 649         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 650
 651         if (cmdbuf->num_cliprects < 0)
 652                 return -EINVAL;
 653
 654         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 655         if (batch_data == NULL)
 656                 return -ENOMEM;
 657
 658         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 659         if (ret != 0)
 660                 goto fail_batch_free;
 661
 662         if (cmdbuf->num_cliprects) {
 663                 cliprects = kcalloc(cmdbuf->num_cliprects,
 664                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 665                 if (cliprects == NULL) {
 666                         ret = -ENOMEM;
 667                         goto fail_batch_free;
 668                 }
 669
 670                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 671                                      cmdbuf->num_cliprects *
 672                                      sizeof(struct drm_clip_rect));
 673                 if (ret != 0)
 674                         goto fail_clip_free;
 675         }
 676
 677         mutex_lock(&dev->struct_mutex);
 678         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 679         mutex_unlock(&dev->struct_mutex);
 680         if (ret) {
 681                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 682                 goto fail_clip_free;
 683         }
 684
 685         if (sarea_priv)
 686                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 687
 688 fail_clip_free:
 689         kfree(cliprects);
 690 fail_batch_free:
 691         kfree(batch_data);
 692
 693         return ret;
 694 }
 695
 696 static int i915_flip_bufs(struct drm_device *dev, void *data,
 697                           struct drm_file *file_priv)
 698 {
 699         int ret;
 700
 701         DRM_DEBUG_DRIVER("%s\n", __func__);
 702
 703         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 704
 705         mutex_lock(&dev->struct_mutex);
 706         ret = i915_dispatch_flip(dev);
 707         mutex_unlock(&dev->struct_mutex);
 708
 709         return ret;
 710 }
 711
 712 static int i915_getparam(struct drm_device *dev, void *data,
 713                          struct drm_file *file_priv)
 714 {
 715         drm_i915_private_t *dev_priv = dev->dev_private;
 716         drm_i915_getparam_t *param = data;
 717         int value;
 718
 719         if (!dev_priv) {
 720                 DRM_ERROR("called with no initialization\n");
 721                 return -EINVAL;
 722         }
 723
 724         switch (param->param) {
 725         case I915_PARAM_IRQ_ACTIVE:
 726                 value = dev->pdev->irq ? 1 : 0;
 727                 break;
 728         case I915_PARAM_ALLOW_BATCHBUFFER:
 729                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 730                 break;
 731         case I915_PARAM_LAST_DISPATCH:
 732                 value = READ_BREADCRUMB(dev_priv);
 733                 break;
 734         case I915_PARAM_CHIPSET_ID:
 735                 value = dev->pci_device;
 736                 break;
 737         case I915_PARAM_HAS_GEM:
 738                 value = dev_priv->has_gem;
 739                 break;
 740         case I915_PARAM_NUM_FENCES_AVAIL:
 741                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 742                 break;
 743         case I915_PARAM_HAS_OVERLAY:
 744                 value = dev_priv->overlay ? 1 : 0;
 745                 break;
 746         case I915_PARAM_HAS_PAGEFLIPPING:
 747                 value = 1;
 748                 break;
 749         case I915_PARAM_HAS_EXECBUF2:
 750                 /* depends on GEM */
 751                 value = dev_priv->has_gem;
 752                 break;
 753         default:
 754                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 755                                  param->param);
 756                 return -EINVAL;
 757         }
 758
 759         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 760                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 761                 return -EFAULT;
 762         }
 763
 764         return 0;
 765 }
 766
 767 static int i915_setparam(struct drm_device *dev, void *data,
 768                          struct drm_file *file_priv)
 769 {
 770         drm_i915_private_t *dev_priv = dev->dev_private;
 771         drm_i915_setparam_t *param = data;
 772
 773         if (!dev_priv) {
 774                 DRM_ERROR("called with no initialization\n");
 775                 return -EINVAL;
 776         }
 777
 778         switch (param->param) {
 779         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 780                 break;
 781         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 782                 dev_priv->tex_lru_log_granularity = param->value;
 783                 break;
 784         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 785                 dev_priv->allow_batchbuffer = param->value;
 786                 break;
 787         case I915_SETPARAM_NUM_USED_FENCES:
 788                 if (param->value > dev_priv->num_fence_regs ||
 789                     param->value < 0)
 790                         return -EINVAL;
 791                 /* Userspace can use first N regs */
 792                 dev_priv->fence_reg_start = param->value;
 793                 break;
 794         default:
 795                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 796                                         param->param);
 797                 return -EINVAL;
 798         }
 799
 800         return 0;
 801 }
 802
 803 static int i915_set_status_page(struct drm_device *dev, void *data,
 804                                 struct drm_file *file_priv)
 805 {
 806         drm_i915_private_t *dev_priv = dev->dev_private;
 807         drm_i915_hws_addr_t *hws = data;
 808
 809         if (!I915_NEED_GFX_HWS(dev))
 810                 return -EINVAL;
 811
 812         if (!dev_priv) {
 813                 DRM_ERROR("called with no initialization\n");
 814                 return -EINVAL;
 815         }
 816
 817         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 818                 WARN(1, "tried to set status page when mode setting active\n");
 819                 return 0;
 820         }
 821
 822         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 823
 824         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
 825
 826         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 827         dev_priv->hws_map.size = 4*1024;
 828         dev_priv->hws_map.type = 0;
 829         dev_priv->hws_map.flags = 0;
 830         dev_priv->hws_map.mtrr = 0;
 831
 832         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 833         if (dev_priv->hws_map.handle == NULL) {
 834                 i915_dma_cleanup(dev);
 835                 dev_priv->status_gfx_addr = 0;
 836                 DRM_ERROR("can not ioremap virtual address for"
 837                                 " G33 hw status page\n");
 838                 return -ENOMEM;
 839         }
 840         dev_priv->hw_status_page = dev_priv->hws_map.handle;
 841
 842         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 843         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 844         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 845                                 dev_priv->status_gfx_addr);
 846         DRM_DEBUG_DRIVER("load hws at %p\n",
 847                                 dev_priv->hw_status_page);
 848         return 0;
 849 }
 850
 851 static int i915_get_bridge_dev(struct drm_device *dev)
 852 {
 853         struct drm_i915_private *dev_priv = dev->dev_private;
 854
 855         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 856         if (!dev_priv->bridge_dev) {
 857                 DRM_ERROR("bridge device not found\n");
 858                 return -1;
 859         }
 860         return 0;
 861 }
 862
 863 #define MCHBAR_I915 0x44
 864 #define MCHBAR_I965 0x48
 865 #define MCHBAR_SIZE (4*4096)
 866
 867 #define DEVEN_REG 0x54
 868 #define   DEVEN_MCHBAR_EN (1 << 28)
 869
 870 /* Allocate space for the MCH regs if needed, return nonzero on error */
 871 static int
 872 intel_alloc_mchbar_resource(struct drm_device *dev)
 873 {
 874         drm_i915_private_t *dev_priv = dev->dev_private;
 875         int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 876         u32 temp_lo, temp_hi = 0;
 877         u64 mchbar_addr;
 878         int ret = 0;
 879
 880         if (IS_I965G(dev))
 881                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 882         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 883         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 884
 885         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 886 #ifdef CONFIG_PNP
 887         if (mchbar_addr &&
 888             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
 889                 ret = 0;
 890                 goto out;
 891         }
 892 #endif
 893
 894         /* Get some space for it */
 895         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
 896                                      MCHBAR_SIZE, MCHBAR_SIZE,
 897                                      PCIBIOS_MIN_MEM,
 898                                      0,   pcibios_align_resource,
 899                                      dev_priv->bridge_dev);
 900         if (ret) {
 901                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 902                 dev_priv->mch_res.start = 0;
 903                 goto out;
 904         }
 905
 906         if (IS_I965G(dev))
 907                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 908                                        upper_32_bits(dev_priv->mch_res.start));
 909
 910         pci_write_config_dword(dev_priv->bridge_dev, reg,
 911                                lower_32_bits(dev_priv->mch_res.start));
 912 out:
 913         return ret;
 914 }
 915
 916 /* Setup MCHBAR if possible, return true if we should disable it again */
 917 static void
 918 intel_setup_mchbar(struct drm_device *dev)
 919 {
 920         drm_i915_private_t *dev_priv = dev->dev_private;
 921         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 922         u32 temp;
 923         bool enabled;
 924
 925         dev_priv->mchbar_need_disable = false;
 926
 927         if (IS_I915G(dev) || IS_I915GM(dev)) {
 928                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 929                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 930         } else {
 931                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 932                 enabled = temp & 1;
 933         }
 934
 935         /* If it's already enabled, don't have to do anything */
 936         if (enabled)
 937                 return;
 938
 939         if (intel_alloc_mchbar_resource(dev))
 940                 return;
 941
 942         dev_priv->mchbar_need_disable = true;
 943
 944         /* Space is allocated or reserved, so enable it. */
 945         if (IS_I915G(dev) || IS_I915GM(dev)) {
 946                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 947                                        temp | DEVEN_MCHBAR_EN);
 948         } else {
 949                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 950                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 951         }
 952 }
 953
 954 static void
 955 intel_teardown_mchbar(struct drm_device *dev)
 956 {
 957         drm_i915_private_t *dev_priv = dev->dev_private;
 958         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 959         u32 temp;
 960
 961         if (dev_priv->mchbar_need_disable) {
 962                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 963                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 964                         temp &= ~DEVEN_MCHBAR_EN;
 965                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 966                 } else {
 967                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 968                         temp &= ~1;
 969                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 970                 }
 971         }
 972
 973         if (dev_priv->mch_res.start)
 974                 release_resource(&dev_priv->mch_res);
 975 }
 976
 977 /**
 978  * i915_probe_agp - get AGP bootup configuration
 979  * @pdev: PCI device
 980  * @aperture_size: returns AGP aperture configured size
 981  * @preallocated_size: returns size of BIOS preallocated AGP space
 982  *
 983  * Since Intel integrated graphics are UMA, the BIOS has to set aside
 984  * some RAM for the framebuffer at early boot.  This code figures out
 985  * how much was set aside so we can use it for our own purposes.
 986  */
 987 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
 988                           uint32_t *preallocated_size,
 989                           uint32_t *start)
 990 {
 991         struct drm_i915_private *dev_priv = dev->dev_private;
 992         u16 tmp = 0;
 993         unsigned long overhead;
 994         unsigned long stolen;
 995
 996         /* Get the fb aperture size and "stolen" memory amount. */
 997         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
 998
 999         *aperture_size = 1024 * 1024;
1000         *preallocated_size = 1024 * 1024;
1001
1002         switch (dev->pdev->device) {
1003         case PCI_DEVICE_ID_INTEL_82830_CGC:
1004         case PCI_DEVICE_ID_INTEL_82845G_IG:
1005         case PCI_DEVICE_ID_INTEL_82855GM_IG:
1006         case PCI_DEVICE_ID_INTEL_82865_IG:
1007                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1008                         *aperture_size *= 64;
1009                 else
1010                         *aperture_size *= 128;
1011                 break;
1012         default:
1013                 /* 9xx supports large sizes, just look at the length */
1014                 *aperture_size = pci_resource_len(dev->pdev, 2);
1015                 break;
1016         }
1017
1018         /*
1019          * Some of the preallocated space is taken by the GTT
1020          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
1021          */
1022         if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1023                 overhead = 4096;
1024         else
1025                 overhead = (*aperture_size / 1024) + 4096;
1026
1027         if (IS_GEN6(dev)) {
1028                 /* SNB has memory control reg at 0x50.w */
1029                 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1030
1031                 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1032                 case INTEL_855_GMCH_GMS_DISABLED:
1033                         DRM_ERROR("video memory is disabled\n");
1034                         return -1;
1035                 case SNB_GMCH_GMS_STOLEN_32M:
1036                         stolen = 32 * 1024 * 1024;
1037                         break;
1038                 case SNB_GMCH_GMS_STOLEN_64M:
1039                         stolen = 64 * 1024 * 1024;
1040                         break;
1041                 case SNB_GMCH_GMS_STOLEN_96M:
1042                         stolen = 96 * 1024 * 1024;
1043                         break;
1044                 case SNB_GMCH_GMS_STOLEN_128M:
1045                         stolen = 128 * 1024 * 1024;
1046                         break;
1047                 case SNB_GMCH_GMS_STOLEN_160M:
1048                         stolen = 160 * 1024 * 1024;
1049                         break;
1050                 case SNB_GMCH_GMS_STOLEN_192M:
1051                         stolen = 192 * 1024 * 1024;
1052                         break;
1053                 case SNB_GMCH_GMS_STOLEN_224M:
1054                         stolen = 224 * 1024 * 1024;
1055                         break;
1056                 case SNB_GMCH_GMS_STOLEN_256M:
1057                         stolen = 256 * 1024 * 1024;
1058                         break;
1059                 case SNB_GMCH_GMS_STOLEN_288M:
1060                         stolen = 288 * 1024 * 1024;
1061                         break;
1062                 case SNB_GMCH_GMS_STOLEN_320M:
1063                         stolen = 320 * 1024 * 1024;
1064                         break;
1065                 case SNB_GMCH_GMS_STOLEN_352M:
1066                         stolen = 352 * 1024 * 1024;
1067                         break;
1068                 case SNB_GMCH_GMS_STOLEN_384M:
1069                         stolen = 384 * 1024 * 1024;
1070                         break;
1071                 case SNB_GMCH_GMS_STOLEN_416M:
1072                         stolen = 416 * 1024 * 1024;
1073                         break;
1074                 case SNB_GMCH_GMS_STOLEN_448M:
1075                         stolen = 448 * 1024 * 1024;
1076                         break;
1077                 case SNB_GMCH_GMS_STOLEN_480M:
1078                         stolen = 480 * 1024 * 1024;
1079                         break;
1080                 case SNB_GMCH_GMS_STOLEN_512M:
1081                         stolen = 512 * 1024 * 1024;
1082                         break;
1083                 default:
1084                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1085                                   tmp & SNB_GMCH_GMS_STOLEN_MASK);
1086                         return -1;
1087                 }
1088         } else {
1089                 switch (tmp & INTEL_GMCH_GMS_MASK) {
1090                 case INTEL_855_GMCH_GMS_DISABLED:
1091                         DRM_ERROR("video memory is disabled\n");
1092                         return -1;
1093                 case INTEL_855_GMCH_GMS_STOLEN_1M:
1094                         stolen = 1 * 1024 * 1024;
1095                         break;
1096                 case INTEL_855_GMCH_GMS_STOLEN_4M:
1097                         stolen = 4 * 1024 * 1024;
1098                         break;
1099                 case INTEL_855_GMCH_GMS_STOLEN_8M:
1100                         stolen = 8 * 1024 * 1024;
1101                         break;
1102                 case INTEL_855_GMCH_GMS_STOLEN_16M:
1103                         stolen = 16 * 1024 * 1024;
1104                         break;
1105                 case INTEL_855_GMCH_GMS_STOLEN_32M:
1106                         stolen = 32 * 1024 * 1024;
1107                         break;
1108                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1109                         stolen = 48 * 1024 * 1024;
1110                         break;
1111                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1112                         stolen = 64 * 1024 * 1024;
1113                         break;
1114                 case INTEL_GMCH_GMS_STOLEN_128M:
1115                         stolen = 128 * 1024 * 1024;
1116                         break;
1117                 case INTEL_GMCH_GMS_STOLEN_256M:
1118                         stolen = 256 * 1024 * 1024;
1119                         break;
1120                 case INTEL_GMCH_GMS_STOLEN_96M:
1121                         stolen = 96 * 1024 * 1024;
1122                         break;
1123                 case INTEL_GMCH_GMS_STOLEN_160M:
1124                         stolen = 160 * 1024 * 1024;
1125                         break;
1126                 case INTEL_GMCH_GMS_STOLEN_224M:
1127                         stolen = 224 * 1024 * 1024;
1128                         break;
1129                 case INTEL_GMCH_GMS_STOLEN_352M:
1130                         stolen = 352 * 1024 * 1024;
1131                         break;
1132                 default:
1133                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1134                                   tmp & INTEL_GMCH_GMS_MASK);
1135                         return -1;
1136                 }
1137         }
1138
1139         *preallocated_size = stolen - overhead;
1140         *start = overhead;
1141
1142         return 0;
1143 }
1144
1145 #define PTE_ADDRESS_MASK                0xfffff000
1146 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1147 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1148 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1149 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1150 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1151 #define PTE_VALID                       (1 << 0)
1152
1153 /**
1154  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1155  * @dev: drm device
1156  * @gtt_addr: address to translate
1157  *
1158  * Some chip functions require allocations from stolen space but need the
1159  * physical address of the memory in question.  We use this routine
1160  * to get a physical address suitable for register programming from a given
1161  * GTT address.
1162  */
1163 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1164                                       unsigned long gtt_addr)
1165 {
1166         unsigned long *gtt;
1167         unsigned long entry, phys;
1168         int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1169         int gtt_offset, gtt_size;
1170
1171         if (IS_I965G(dev)) {
1172                 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1173                         gtt_offset = 2*1024*1024;
1174                         gtt_size = 2*1024*1024;
1175                 } else {
1176                         gtt_offset = 512*1024;
1177                         gtt_size = 512*1024;
1178                 }
1179         } else {
1180                 gtt_bar = 3;
1181                 gtt_offset = 0;
1182                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1183         }
1184
1185         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1186                          gtt_size);
1187         if (!gtt) {
1188                 DRM_ERROR("ioremap of GTT failed\n");
1189                 return 0;
1190         }
1191
1192         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1193
1194         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1195
1196         /* Mask out these reserved bits on this hardware. */
1197         if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1198             IS_I945G(dev) || IS_I945GM(dev)) {
1199                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1200         }
1201
1202         /* If it's not a mapping type we know, then bail. */
1203         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1204             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1205                 iounmap(gtt);
1206                 return 0;
1207         }
1208
1209         if (!(entry & PTE_VALID)) {
1210                 DRM_ERROR("bad GTT entry in stolen space\n");
1211                 iounmap(gtt);
1212                 return 0;
1213         }
1214
1215         iounmap(gtt);
1216
1217         phys =(entry & PTE_ADDRESS_MASK) |
1218                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1219
1220         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1221
1222         return phys;
1223 }
1224
1225 static void i915_warn_stolen(struct drm_device *dev)
1226 {
1227         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1228         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1229 }
1230
1231 static void i915_setup_compression(struct drm_device *dev, int size)
1232 {
1233         struct drm_i915_private *dev_priv = dev->dev_private;
1234         struct drm_mm_node *compressed_fb, *compressed_llb;
1235         unsigned long cfb_base;
1236         unsigned long ll_base = 0;
1237
1238         /* Leave 1M for line length buffer & misc. */
1239         compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1240         if (!compressed_fb) {
1241                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1242                 i915_warn_stolen(dev);
1243                 return;
1244         }
1245
1246         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1247         if (!compressed_fb) {
1248                 i915_warn_stolen(dev);
1249                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1250                 return;
1251         }
1252
1253         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1254         if (!cfb_base) {
1255                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1256                 drm_mm_put_block(compressed_fb);
1257         }
1258
1259         if (!IS_GM45(dev)) {
1260                 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1261                                                     4096, 0);
1262                 if (!compressed_llb) {
1263                         i915_warn_stolen(dev);
1264                         return;
1265                 }
1266
1267                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1268                 if (!compressed_llb) {
1269                         i915_warn_stolen(dev);
1270                         return;
1271                 }
1272
1273                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1274                 if (!ll_base) {
1275                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1276                         drm_mm_put_block(compressed_fb);
1277                         drm_mm_put_block(compressed_llb);
1278                 }
1279         }
1280
1281         dev_priv->cfb_size = size;
1282
1283         intel_disable_fbc(dev);
1284         dev_priv->compressed_fb = compressed_fb;
1285
1286         if (IS_GM45(dev)) {
1287                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1288         } else {
1289                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1290                 I915_WRITE(FBC_LL_BASE, ll_base);
1291                 dev_priv->compressed_llb = compressed_llb;
1292         }
1293
1294         DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1295                   ll_base, size >> 20);
1296 }
1297
1298 static void i915_cleanup_compression(struct drm_device *dev)
1299 {
1300         struct drm_i915_private *dev_priv = dev->dev_private;
1301
1302         drm_mm_put_block(dev_priv->compressed_fb);
1303         if (!IS_GM45(dev))
1304                 drm_mm_put_block(dev_priv->compressed_llb);
1305 }
1306
1307 /* true = enable decode, false = disable decoder */
1308 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1309 {
1310         struct drm_device *dev = cookie;
1311
1312         intel_modeset_vga_set_state(dev, state);
1313         if (state)
1314                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1315                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1316         else
1317                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1318 }
1319
1320 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1321 {
1322         struct drm_device *dev = pci_get_drvdata(pdev);
1323         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1324         if (state == VGA_SWITCHEROO_ON) {
1325                 printk(KERN_INFO "i915: switched off\n");
1326                 /* i915 resume handler doesn't set to D0 */
1327                 pci_set_power_state(dev->pdev, PCI_D0);
1328                 i915_resume(dev);
1329         } else {
1330                 printk(KERN_ERR "i915: switched off\n");
1331                 i915_suspend(dev, pmm);
1332         }
1333 }
1334
1335 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1336 {
1337         struct drm_device *dev = pci_get_drvdata(pdev);
1338         bool can_switch;
1339
1340         spin_lock(&dev->count_lock);
1341         can_switch = (dev->open_count == 0);
1342         spin_unlock(&dev->count_lock);
1343         return can_switch;
1344 }
1345
1346 static int i915_load_modeset_init(struct drm_device *dev,
1347                                   unsigned long prealloc_start,
1348                                   unsigned long prealloc_size,
1349                                   unsigned long agp_size)
1350 {
1351         struct drm_i915_private *dev_priv = dev->dev_private;
1352         int fb_bar = IS_I9XX(dev) ? 2 : 0;
1353         int ret = 0;
1354
1355         dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1356                 0xff000000;
1357
1358         /* Basic memrange allocator for stolen space (aka vram) */
1359         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1360         DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1361
1362         /* We're off and running w/KMS */
1363         dev_priv->mm.suspended = 0;
1364
1365         /* Let GEM Manage from end of prealloc space to end of aperture.
1366          *
1367          * However, leave one page at the end still bound to the scratch page.
1368          * There are a number of places where the hardware apparently
1369          * prefetches past the end of the object, and we've seen multiple
1370          * hangs with the GPU head pointer stuck in a batchbuffer bound
1371          * at the last page of the aperture.  One page should be enough to
1372          * keep any prefetching inside of the aperture.
1373          */
1374         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1375
1376         mutex_lock(&dev->struct_mutex);
1377         ret = i915_gem_init_ringbuffer(dev);
1378         mutex_unlock(&dev->struct_mutex);
1379         if (ret)
1380                 goto out;
1381
1382         /* Try to set up FBC with a reasonable compressed buffer size */
1383         if (I915_HAS_FBC(dev) && i915_powersave) {
1384                 int cfb_size;
1385
1386                 /* Try to get an 8M buffer... */
1387                 if (prealloc_size > (9*1024*1024))
1388                         cfb_size = 8*1024*1024;
1389                 else /* fall back to 7/8 of the stolen space */
1390                         cfb_size = prealloc_size * 7 / 8;
1391                 i915_setup_compression(dev, cfb_size);
1392         }
1393
1394         /* Allow hardware batchbuffers unless told otherwise.
1395          */
1396         dev_priv->allow_batchbuffer = 1;
1397
1398         ret = intel_init_bios(dev);
1399         if (ret)
1400                 DRM_INFO("failed to find VBIOS tables\n");
1401
1402         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1403         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1404         if (ret)
1405                 goto destroy_ringbuffer;
1406
1407         ret = vga_switcheroo_register_client(dev->pdev,
1408                                              i915_switcheroo_set_state,
1409                                              i915_switcheroo_can_switch);
1410         if (ret)
1411                 goto destroy_ringbuffer;
1412
1413         intel_modeset_init(dev);
1414
1415         ret = drm_irq_install(dev);
1416         if (ret)
1417                 goto destroy_ringbuffer;
1418
1419         /* Always safe in the mode setting case. */
1420         /* FIXME: do pre/post-mode set stuff in core KMS code */
1421         dev->vblank_disable_allowed = 1;
1422
1423         /*
1424          * Initialize the hardware status page IRQ location.
1425          */
1426
1427         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1428
1429         intel_fbdev_init(dev);
1430         drm_kms_helper_poll_init(dev);
1431         return 0;
1432
1433 destroy_ringbuffer:
1434         mutex_lock(&dev->struct_mutex);
1435         i915_gem_cleanup_ringbuffer(dev);
1436         mutex_unlock(&dev->struct_mutex);
1437 out:
1438         return ret;
1439 }
1440
1441 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1442 {
1443         struct drm_i915_master_private *master_priv;
1444
1445         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1446         if (!master_priv)
1447                 return -ENOMEM;
1448
1449         master->driver_priv = master_priv;
1450         return 0;
1451 }
1452
1453 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1454 {
1455         struct drm_i915_master_private *master_priv = master->driver_priv;
1456
1457         if (!master_priv)
1458                 return;
1459
1460         kfree(master_priv);
1461
1462         master->driver_priv = NULL;
1463 }
1464
1465 static void i915_get_mem_freq(struct drm_device *dev)
1466 {
1467         drm_i915_private_t *dev_priv = dev->dev_private;
1468         u32 tmp;
1469
1470         if (!IS_PINEVIEW(dev))
1471                 return;
1472
1473         tmp = I915_READ(CLKCFG);
1474
1475         switch (tmp & CLKCFG_FSB_MASK) {
1476         case CLKCFG_FSB_533:
1477                 dev_priv->fsb_freq = 533; /* 133*4 */
1478                 break;
1479         case CLKCFG_FSB_800:
1480                 dev_priv->fsb_freq = 800; /* 200*4 */
1481                 break;
1482         case CLKCFG_FSB_667:
1483                 dev_priv->fsb_freq =  667; /* 167*4 */
1484                 break;
1485         case CLKCFG_FSB_400:
1486                 dev_priv->fsb_freq = 400; /* 100*4 */
1487                 break;
1488         }
1489
1490         switch (tmp & CLKCFG_MEM_MASK) {
1491         case CLKCFG_MEM_533:
1492                 dev_priv->mem_freq = 533;
1493                 break;
1494         case CLKCFG_MEM_667:
1495                 dev_priv->mem_freq = 667;
1496                 break;
1497         case CLKCFG_MEM_800:
1498                 dev_priv->mem_freq = 800;
1499                 break;
1500         }
1501 }
1502
1503 /**
1504  * i915_driver_load - setup chip and create an initial config
1505  * @dev: DRM device
1506  * @flags: startup flags
1507  *
1508  * The driver load routine has to do several things:
1509  *   - drive output discovery via intel_modeset_init()
1510  *   - initialize the memory manager
1511  *   - allocate initial config memory
1512  *   - setup the DRM framebuffer with the allocated memory
1513  */
1514 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1515 {
1516         struct drm_i915_private *dev_priv;
1517         resource_size_t base, size;
1518         int ret = 0, mmio_bar;
1519         uint32_t agp_size, prealloc_size, prealloc_start;
1520
1521         /* i915 has 4 more counters */
1522         dev->counters += 4;
1523         dev->types[6] = _DRM_STAT_IRQ;
1524         dev->types[7] = _DRM_STAT_PRIMARY;
1525         dev->types[8] = _DRM_STAT_SECONDARY;
1526         dev->types[9] = _DRM_STAT_DMA;
1527
1528         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1529         if (dev_priv == NULL)
1530                 return -ENOMEM;
1531
1532         dev->dev_private = (void *)dev_priv;
1533         dev_priv->dev = dev;
1534         dev_priv->info = (struct intel_device_info *) flags;
1535
1536         /* Add register map (needed for suspend/resume) */
1537         mmio_bar = IS_I9XX(dev) ? 0 : 1;
1538         base = drm_get_resource_start(dev, mmio_bar);
1539         size = drm_get_resource_len(dev, mmio_bar);
1540
1541         if (i915_get_bridge_dev(dev)) {
1542                 ret = -EIO;
1543                 goto free_priv;
1544         }
1545
1546         dev_priv->regs = ioremap(base, size);
1547         if (!dev_priv->regs) {
1548                 DRM_ERROR("failed to map registers\n");
1549                 ret = -EIO;
1550                 goto put_bridge;
1551         }
1552
1553         dev_priv->mm.gtt_mapping =
1554                 io_mapping_create_wc(dev->agp->base,
1555                                      dev->agp->agp_info.aper_size * 1024*1024);
1556         if (dev_priv->mm.gtt_mapping == NULL) {
1557                 ret = -EIO;
1558                 goto out_rmmap;
1559         }
1560
1561         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1562          * one would think, because the kernel disables PAT on first
1563          * generation Core chips because WC PAT gets overridden by a UC
1564          * MTRR if present.  Even if a UC MTRR isn't present.
1565          */
1566         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1567                                          dev->agp->agp_info.aper_size *
1568                                          1024 * 1024,
1569                                          MTRR_TYPE_WRCOMB, 1);
1570         if (dev_priv->mm.gtt_mtrr < 0) {
1571                 DRM_INFO("MTRR allocation failed.  Graphics "
1572                          "performance may suffer.\n");
1573         }
1574
1575         ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
1576         if (ret)
1577                 goto out_iomapfree;
1578
1579         dev_priv->wq = create_singlethread_workqueue("i915");
1580         if (dev_priv->wq == NULL) {
1581                 DRM_ERROR("Failed to create our workqueue.\n");
1582                 ret = -ENOMEM;
1583                 goto out_iomapfree;
1584         }
1585
1586         /* enable GEM by default */
1587         dev_priv->has_gem = 1;
1588
1589         if (prealloc_size > agp_size * 3 / 4) {
1590                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1591                           "memory stolen.\n",
1592                           prealloc_size / 1024, agp_size / 1024);
1593                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1594                           "updating the BIOS to fix).\n");
1595                 dev_priv->has_gem = 0;
1596         }
1597
1598         if (dev_priv->has_gem == 0 &&
1599             drm_core_check_feature(dev, DRIVER_MODESET)) {
1600                 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
1601                 ret = -ENODEV;
1602                 goto out_iomapfree;
1603         }
1604
1605         dev->driver->get_vblank_counter = i915_get_vblank_counter;
1606         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1607         if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1608                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1609                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1610         }
1611
1612         /* Try to make sure MCHBAR is enabled before poking at it */
1613         intel_setup_mchbar(dev);
1614
1615         i915_gem_load(dev);
1616
1617         /* Init HWS */
1618         if (!I915_NEED_GFX_HWS(dev)) {
1619                 ret = i915_init_phys_hws(dev);
1620                 if (ret != 0)
1621                         goto out_workqueue_free;
1622         }
1623
1624         i915_get_mem_freq(dev);
1625
1626         /* On the 945G/GM, the chipset reports the MSI capability on the
1627          * integrated graphics even though the support isn't actually there
1628          * according to the published specs.  It doesn't appear to function
1629          * correctly in testing on 945G.
1630          * This may be a side effect of MSI having been made available for PEG
1631          * and the registers being closely associated.
1632          *
1633          * According to chipset errata, on the 965GM, MSI interrupts may
1634          * be lost or delayed, but we use them anyways to avoid
1635          * stuck interrupts on some machines.
1636          */
1637         if (!IS_I945G(dev) && !IS_I945GM(dev))
1638                 pci_enable_msi(dev->pdev);
1639
1640         spin_lock_init(&dev_priv->user_irq_lock);
1641         spin_lock_init(&dev_priv->error_lock);
1642         dev_priv->user_irq_refcount = 0;
1643         dev_priv->trace_irq_seqno = 0;
1644
1645         ret = drm_vblank_init(dev, I915_NUM_PIPE);
1646
1647         if (ret) {
1648                 (void) i915_driver_unload(dev);
1649                 return ret;
1650         }
1651
1652         /* Start out suspended */
1653         dev_priv->mm.suspended = 1;
1654
1655         intel_detect_pch(dev);
1656
1657         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1658                 ret = i915_load_modeset_init(dev, prealloc_start,
1659                                              prealloc_size, agp_size);
1660                 if (ret < 0) {
1661                         DRM_ERROR("failed to init modeset\n");
1662                         goto out_workqueue_free;
1663                 }
1664         }
1665
1666         /* Must be done after probing outputs */
1667         intel_opregion_init(dev, 0);
1668
1669         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1670                     (unsigned long) dev);
1671         return 0;
1672
1673 out_workqueue_free:
1674         destroy_workqueue(dev_priv->wq);
1675 out_iomapfree:
1676         io_mapping_free(dev_priv->mm.gtt_mapping);
1677 out_rmmap:
1678         iounmap(dev_priv->regs);
1679 put_bridge:
1680         pci_dev_put(dev_priv->bridge_dev);
1681 free_priv:
1682         kfree(dev_priv);
1683         return ret;
1684 }
1685
1686 int i915_driver_unload(struct drm_device *dev)
1687 {
1688         struct drm_i915_private *dev_priv = dev->dev_private;
1689
1690         i915_destroy_error_state(dev);
1691
1692         destroy_workqueue(dev_priv->wq);
1693         del_timer_sync(&dev_priv->hangcheck_timer);
1694
1695         io_mapping_free(dev_priv->mm.gtt_mapping);
1696         if (dev_priv->mm.gtt_mtrr >= 0) {
1697                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1698                          dev->agp->agp_info.aper_size * 1024 * 1024);
1699                 dev_priv->mm.gtt_mtrr = -1;
1700         }
1701
1702         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1703                 intel_modeset_cleanup(dev);
1704
1705                 /*
1706                  * free the memory space allocated for the child device
1707                  * config parsed from VBT
1708                  */
1709                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1710                         kfree(dev_priv->child_dev);
1711                         dev_priv->child_dev = NULL;
1712                         dev_priv->child_dev_num = 0;
1713                 }
1714                 drm_irq_uninstall(dev);
1715                 vga_switcheroo_unregister_client(dev->pdev);
1716                 vga_client_register(dev->pdev, NULL, NULL, NULL);
1717         }
1718
1719         if (dev->pdev->msi_enabled)
1720                 pci_disable_msi(dev->pdev);
1721
1722         if (dev_priv->regs != NULL)
1723                 iounmap(dev_priv->regs);
1724
1725         intel_opregion_free(dev, 0);
1726
1727         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1728                 i915_gem_free_all_phys_object(dev);
1729
1730                 mutex_lock(&dev->struct_mutex);
1731                 i915_gem_cleanup_ringbuffer(dev);
1732                 mutex_unlock(&dev->struct_mutex);
1733                 if (I915_HAS_FBC(dev) && i915_powersave)
1734                         i915_cleanup_compression(dev);
1735                 drm_mm_takedown(&dev_priv->vram);
1736                 i915_gem_lastclose(dev);
1737
1738                 intel_cleanup_overlay(dev);
1739         }
1740
1741         intel_teardown_mchbar(dev);
1742
1743         pci_dev_put(dev_priv->bridge_dev);
1744         kfree(dev->dev_private);
1745
1746         return 0;
1747 }
1748
1749 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1750 {
1751         struct drm_i915_file_private *i915_file_priv;
1752
1753         DRM_DEBUG_DRIVER("\n");
1754         i915_file_priv = (struct drm_i915_file_private *)
1755             kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
1756
1757         if (!i915_file_priv)
1758                 return -ENOMEM;
1759
1760         file_priv->driver_priv = i915_file_priv;
1761
1762         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1763
1764         return 0;
1765 }
1766
1767 /**
1768  * i915_driver_lastclose - clean up after all DRM clients have exited
1769  * @dev: DRM device
1770  *
1771  * Take care of cleaning up after all DRM clients have exited.  In the
1772  * mode setting case, we want to restore the kernel's initial mode (just
1773  * in case the last client left us in a bad state).
1774  *
1775  * Additionally, in the non-mode setting case, we'll tear down the AGP
1776  * and DMA structures, since the kernel won't be using them, and clea
1777  * up any GEM state.
1778  */
1779 void i915_driver_lastclose(struct drm_device * dev)
1780 {
1781         drm_i915_private_t *dev_priv = dev->dev_private;
1782
1783         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1784                 drm_fb_helper_restore();
1785                 vga_switcheroo_process_delayed_switch();
1786                 return;
1787         }
1788
1789         i915_gem_lastclose(dev);
1790
1791         if (dev_priv->agp_heap)
1792                 i915_mem_takedown(&(dev_priv->agp_heap));
1793
1794         i915_dma_cleanup(dev);
1795 }
1796
1797 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1798 {
1799         drm_i915_private_t *dev_priv = dev->dev_private;
1800         i915_gem_release(dev, file_priv);
1801         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1802                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1803 }
1804
1805 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1806 {
1807         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1808
1809         kfree(i915_file_priv);
1810 }
1811
1812 struct drm_ioctl_desc i915_ioctls[] = {
1813         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1814         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1815         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1816         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1817         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1818         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1819         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1820         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1821         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1822         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1823         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1824         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1825         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1826         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1827         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1828         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1829         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1830         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1831         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1832         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1833         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1834         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1835         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1836         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1837         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1838         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1839         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1840         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1841         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1842         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1843         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1844         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1845         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1846         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1847         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1848         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1849         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1850         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1851         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1852         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1853 };
1854
1855 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1856
1857 /**
1858  * Determine if the device really is AGP or not.
1859  *
1860  * All Intel graphics chipsets are treated as AGP, even if they are really
1861  * PCI-e.
1862  *
1863  * \param dev   The device to be tested.
1864  *
1865  * \returns
1866  * A value of 1 is always retured to indictate every i9x5 is AGP.
1867  */
1868 int i915_driver_device_is_agp(struct drm_device * dev)
1869 {
1870         return 1;
1871 }