drivers/dma/shdma.c

   1 /*
   2  * Renesas SuperH DMA Engine support
   3  *
   4  * base is drivers/dma/flsdma.c
   5  *
   6  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   7  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
   8  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
   9  *
  10  * This is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * - DMA of SuperH does not have Hardware DMA chain mode.
  16  * - MAX DMA size is 16MB.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/slab.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/dmaengine.h>
  25 #include <linux/delay.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/sh_dma.h>
  30 #include <linux/notifier.h>
  31 #include <linux/kdebug.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/rculist.h>
  34 #include "shdma.h"
  35
  36 /* DMA descriptor control */
  37 enum sh_dmae_desc_status {
  38         DESC_IDLE,
  39         DESC_PREPARED,
  40         DESC_SUBMITTED,
  41         DESC_COMPLETED, /* completed, have to call callback */
  42         DESC_WAITING,   /* callback called, waiting for ack / re-submit */
  43 };
  44
  45 #define NR_DESCS_PER_CHANNEL 32
  46 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
  47 #define LOG2_DEFAULT_XFER_SIZE  2
  48
  49 /*
  50  * Used for write-side mutual exclusion for the global device list,
  51  * read-side synchronization by way of RCU, and per-controller data.
  52  */
  53 static DEFINE_SPINLOCK(sh_dmae_lock);
  54 static LIST_HEAD(sh_dmae_devices);
  55
  56 /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
  57 static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SH_DMA_SLAVE_NUMBER)];
  58
  59 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
  60
  61 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
  62 {
  63         __raw_writel(data, sh_dc->base + reg / sizeof(u32));
  64 }
  65
  66 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
  67 {
  68         return __raw_readl(sh_dc->base + reg / sizeof(u32));
  69 }
  70
  71 static u16 dmaor_read(struct sh_dmae_device *shdev)
  72 {
  73         return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32));
  74 }
  75
  76 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
  77 {
  78         __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32));
  79 }
  80
  81 /*
  82  * Reset DMA controller
  83  *
  84  * SH7780 has two DMAOR register
  85  */
  86 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
  87 {
  88         unsigned short dmaor;
  89         unsigned long flags;
  90
  91         spin_lock_irqsave(&sh_dmae_lock, flags);
  92
  93         dmaor = dmaor_read(shdev);
  94         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
  95
  96         spin_unlock_irqrestore(&sh_dmae_lock, flags);
  97 }
  98
  99 static int sh_dmae_rst(struct sh_dmae_device *shdev)
 100 {
 101         unsigned short dmaor;
 102         unsigned long flags;
 103
 104         spin_lock_irqsave(&sh_dmae_lock, flags);
 105
 106         dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
 107
 108         dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
 109
 110         dmaor = dmaor_read(shdev);
 111
 112         spin_unlock_irqrestore(&sh_dmae_lock, flags);
 113
 114         if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
 115                 dev_warn(shdev->common.dev, "Can't initialize DMAOR.\n");
 116                 return -EIO;
 117         }
 118         return 0;
 119 }
 120
 121 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
 122 {
 123         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 124
 125         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
 126                 return true; /* working */
 127
 128         return false; /* waiting */
 129 }
 130
 131 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
 132 {
 133         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 134         struct sh_dmae_pdata *pdata = shdev->pdata;
 135         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
 136                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
 137
 138         if (cnt >= pdata->ts_shift_num)
 139                 cnt = 0;
 140
 141         return pdata->ts_shift[cnt];
 142 }
 143
 144 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
 145 {
 146         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 147         struct sh_dmae_pdata *pdata = shdev->pdata;
 148         int i;
 149
 150         for (i = 0; i < pdata->ts_shift_num; i++)
 151                 if (pdata->ts_shift[i] == l2size)
 152                         break;
 153
 154         if (i == pdata->ts_shift_num)
 155                 i = 0;
 156
 157         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
 158                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
 159 }
 160
 161 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
 162 {
 163         sh_dmae_writel(sh_chan, hw->sar, SAR);
 164         sh_dmae_writel(sh_chan, hw->dar, DAR);
 165         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
 166 }
 167
 168 static void dmae_start(struct sh_dmae_chan *sh_chan)
 169 {
 170         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 171
 172         chcr |= CHCR_DE | CHCR_IE;
 173         sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR);
 174 }
 175
 176 static void dmae_halt(struct sh_dmae_chan *sh_chan)
 177 {
 178         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 179
 180         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
 181         sh_dmae_writel(sh_chan, chcr, CHCR);
 182 }
 183
 184 static void dmae_init(struct sh_dmae_chan *sh_chan)
 185 {
 186         /*
 187          * Default configuration for dual address memory-memory transfer.
 188          * 0x400 represents auto-request.
 189          */
 190         u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
 191                                                    LOG2_DEFAULT_XFER_SIZE);
 192         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
 193         sh_dmae_writel(sh_chan, chcr, CHCR);
 194 }
 195
 196 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
 197 {
 198         /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
 199         if (dmae_is_busy(sh_chan))
 200                 return -EBUSY;
 201
 202         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
 203         sh_dmae_writel(sh_chan, val, CHCR);
 204
 205         return 0;
 206 }
 207
 208 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
 209 {
 210         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 211         struct sh_dmae_pdata *pdata = shdev->pdata;
 212         const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
 213         u16 __iomem *addr = shdev->dmars;
 214         int shift = chan_pdata->dmars_bit;
 215
 216         if (dmae_is_busy(sh_chan))
 217                 return -EBUSY;
 218
 219         /* in the case of a missing DMARS resource use first memory window */
 220         if (!addr)
 221                 addr = (u16 __iomem *)shdev->chan_reg;
 222         addr += chan_pdata->dmars / sizeof(u16);
 223
 224         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
 225                      addr);
 226
 227         return 0;
 228 }
 229
 230 static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
 231 {
 232         struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
 233         struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
 234         dma_async_tx_callback callback = tx->callback;
 235         dma_cookie_t cookie;
 236
 237         spin_lock_bh(&sh_chan->desc_lock);
 238
 239         cookie = sh_chan->common.cookie;
 240         cookie++;
 241         if (cookie < 0)
 242                 cookie = 1;
 243
 244         sh_chan->common.cookie = cookie;
 245         tx->cookie = cookie;
 246
 247         /* Mark all chunks of this descriptor as submitted, move to the queue */
 248         list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
 249                 /*
 250                  * All chunks are on the global ld_free, so, we have to find
 251                  * the end of the chain ourselves
 252                  */
 253                 if (chunk != desc && (chunk->mark == DESC_IDLE ||
 254                                       chunk->async_tx.cookie > 0 ||
 255                                       chunk->async_tx.cookie == -EBUSY ||
 256                                       &chunk->node == &sh_chan->ld_free))
 257                         break;
 258                 chunk->mark = DESC_SUBMITTED;
 259                 /* Callback goes to the last chunk */
 260                 chunk->async_tx.callback = NULL;
 261                 chunk->cookie = cookie;
 262                 list_move_tail(&chunk->node, &sh_chan->ld_queue);
 263                 last = chunk;
 264         }
 265
 266         last->async_tx.callback = callback;
 267         last->async_tx.callback_param = tx->callback_param;
 268
 269         dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n",
 270                 tx->cookie, &last->async_tx, sh_chan->id,
 271                 desc->hw.sar, desc->hw.tcr, desc->hw.dar);
 272
 273         spin_unlock_bh(&sh_chan->desc_lock);
 274
 275         return cookie;
 276 }
 277
 278 /* Called with desc_lock held */
 279 static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
 280 {
 281         struct sh_desc *desc;
 282
 283         list_for_each_entry(desc, &sh_chan->ld_free, node)
 284                 if (desc->mark != DESC_PREPARED) {
 285                         BUG_ON(desc->mark != DESC_IDLE);
 286                         list_del(&desc->node);
 287                         return desc;
 288                 }
 289
 290         return NULL;
 291 }
 292
 293 static const struct sh_dmae_slave_config *sh_dmae_find_slave(
 294         struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param)
 295 {
 296         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 297         struct sh_dmae_pdata *pdata = shdev->pdata;
 298         int i;
 299
 300         if (param->slave_id >= SH_DMA_SLAVE_NUMBER)
 301                 return NULL;
 302
 303         for (i = 0; i < pdata->slave_num; i++)
 304                 if (pdata->slave[i].slave_id == param->slave_id)
 305                         return pdata->slave + i;
 306
 307         return NULL;
 308 }
 309
 310 static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
 311 {
 312         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 313         struct sh_desc *desc;
 314         struct sh_dmae_slave *param = chan->private;
 315         int ret;
 316
 317         pm_runtime_get_sync(sh_chan->dev);
 318
 319         /*
 320          * This relies on the guarantee from dmaengine that alloc_chan_resources
 321          * never runs concurrently with itself or free_chan_resources.
 322          */
 323         if (param) {
 324                 const struct sh_dmae_slave_config *cfg;
 325
 326                 cfg = sh_dmae_find_slave(sh_chan, param);
 327                 if (!cfg) {
 328                         ret = -EINVAL;
 329                         goto efindslave;
 330                 }
 331
 332                 if (test_and_set_bit(param->slave_id, sh_dmae_slave_used)) {
 333                         ret = -EBUSY;
 334                         goto etestused;
 335                 }
 336
 337                 param->config = cfg;
 338
 339                 dmae_set_dmars(sh_chan, cfg->mid_rid);
 340                 dmae_set_chcr(sh_chan, cfg->chcr);
 341         } else {
 342                 dmae_init(sh_chan);
 343         }
 344
 345         spin_lock_bh(&sh_chan->desc_lock);
 346         while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
 347                 spin_unlock_bh(&sh_chan->desc_lock);
 348                 desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
 349                 if (!desc) {
 350                         spin_lock_bh(&sh_chan->desc_lock);
 351                         break;
 352                 }
 353                 dma_async_tx_descriptor_init(&desc->async_tx,
 354                                         &sh_chan->common);
 355                 desc->async_tx.tx_submit = sh_dmae_tx_submit;
 356                 desc->mark = DESC_IDLE;
 357
 358                 spin_lock_bh(&sh_chan->desc_lock);
 359                 list_add(&desc->node, &sh_chan->ld_free);
 360                 sh_chan->descs_allocated++;
 361         }
 362         spin_unlock_bh(&sh_chan->desc_lock);
 363
 364         if (!sh_chan->descs_allocated) {
 365                 ret = -ENOMEM;
 366                 goto edescalloc;
 367         }
 368
 369         return sh_chan->descs_allocated;
 370
 371 edescalloc:
 372         if (param)
 373                 clear_bit(param->slave_id, sh_dmae_slave_used);
 374 etestused:
 375 efindslave:
 376         pm_runtime_put(sh_chan->dev);
 377         return ret;
 378 }
 379
 380 /*
 381  * sh_dma_free_chan_resources - Free all resources of the channel.
 382  */
 383 static void sh_dmae_free_chan_resources(struct dma_chan *chan)
 384 {
 385         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 386         struct sh_desc *desc, *_desc;
 387         LIST_HEAD(list);
 388         int descs = sh_chan->descs_allocated;
 389
 390         /* Protect against ISR */
 391         spin_lock_irq(&sh_chan->desc_lock);
 392         dmae_halt(sh_chan);
 393         spin_unlock_irq(&sh_chan->desc_lock);
 394
 395         /* Now no new interrupts will occur */
 396
 397         /* Prepared and not submitted descriptors can still be on the queue */
 398         if (!list_empty(&sh_chan->ld_queue))
 399                 sh_dmae_chan_ld_cleanup(sh_chan, true);
 400
 401         if (chan->private) {
 402                 /* The caller is holding dma_list_mutex */
 403                 struct sh_dmae_slave *param = chan->private;
 404                 clear_bit(param->slave_id, sh_dmae_slave_used);
 405                 chan->private = NULL;
 406         }
 407
 408         spin_lock_bh(&sh_chan->desc_lock);
 409
 410         list_splice_init(&sh_chan->ld_free, &list);
 411         sh_chan->descs_allocated = 0;
 412
 413         spin_unlock_bh(&sh_chan->desc_lock);
 414
 415         if (descs > 0)
 416                 pm_runtime_put(sh_chan->dev);
 417
 418         list_for_each_entry_safe(desc, _desc, &list, node)
 419                 kfree(desc);
 420 }
 421
 422 /**
 423  * sh_dmae_add_desc - get, set up and return one transfer descriptor
 424  * @sh_chan:    DMA channel
 425  * @flags:      DMA transfer flags
 426  * @dest:       destination DMA address, incremented when direction equals
 427  *              DMA_FROM_DEVICE or DMA_BIDIRECTIONAL
 428  * @src:        source DMA address, incremented when direction equals
 429  *              DMA_TO_DEVICE or DMA_BIDIRECTIONAL
 430  * @len:        DMA transfer length
 431  * @first:      if NULL, set to the current descriptor and cookie set to -EBUSY
 432  * @direction:  needed for slave DMA to decide which address to keep constant,
 433  *              equals DMA_BIDIRECTIONAL for MEMCPY
 434  * Returns 0 or an error
 435  * Locks: called with desc_lock held
 436  */
 437 static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
 438         unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
 439         struct sh_desc **first, enum dma_data_direction direction)
 440 {
 441         struct sh_desc *new;
 442         size_t copy_size;
 443
 444         if (!*len)
 445                 return NULL;
 446
 447         /* Allocate the link descriptor from the free list */
 448         new = sh_dmae_get_desc(sh_chan);
 449         if (!new) {
 450                 dev_err(sh_chan->dev, "No free link descriptor available\n");
 451                 return NULL;
 452         }
 453
 454         copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1);
 455
 456         new->hw.sar = *src;
 457         new->hw.dar = *dest;
 458         new->hw.tcr = copy_size;
 459
 460         if (!*first) {
 461                 /* First desc */
 462                 new->async_tx.cookie = -EBUSY;
 463                 *first = new;
 464         } else {
 465                 /* Other desc - invisible to the user */
 466                 new->async_tx.cookie = -EINVAL;
 467         }
 468
 469         dev_dbg(sh_chan->dev,
 470                 "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n",
 471                 copy_size, *len, *src, *dest, &new->async_tx,
 472                 new->async_tx.cookie, sh_chan->xmit_shift);
 473
 474         new->mark = DESC_PREPARED;
 475         new->async_tx.flags = flags;
 476         new->direction = direction;
 477
 478         *len -= copy_size;
 479         if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE)
 480                 *src += copy_size;
 481         if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE)
 482                 *dest += copy_size;
 483
 484         return new;
 485 }
 486
 487 /*
 488  * sh_dmae_prep_sg - prepare transfer descriptors from an SG list
 489  *
 490  * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
 491  * converted to scatter-gather to guarantee consistent locking and a correct
 492  * list manipulation. For slave DMA direction carries the usual meaning, and,
 493  * logically, the SG list is RAM and the addr variable contains slave address,
 494  * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL
 495  * and the SG list contains only one element and points at the source buffer.
 496  */
 497 static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
 498         struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
 499         enum dma_data_direction direction, unsigned long flags)
 500 {
 501         struct scatterlist *sg;
 502         struct sh_desc *first = NULL, *new = NULL /* compiler... */;
 503         LIST_HEAD(tx_list);
 504         int chunks = 0;
 505         int i;
 506
 507         if (!sg_len)
 508                 return NULL;
 509
 510         for_each_sg(sgl, sg, sg_len, i)
 511                 chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) /
 512                         (SH_DMA_TCR_MAX + 1);
 513
 514         /* Have to lock the whole loop to protect against concurrent release */
 515         spin_lock_bh(&sh_chan->desc_lock);
 516
 517         /*
 518          * Chaining:
 519          * first descriptor is what user is dealing with in all API calls, its
 520          *      cookie is at first set to -EBUSY, at tx-submit to a positive
 521          *      number
 522          * if more than one chunk is needed further chunks have cookie = -EINVAL
 523          * the last chunk, if not equal to the first, has cookie = -ENOSPC
 524          * all chunks are linked onto the tx_list head with their .node heads
 525          *      only during this function, then they are immediately spliced
 526          *      back onto the free list in form of a chain
 527          */
 528         for_each_sg(sgl, sg, sg_len, i) {
 529                 dma_addr_t sg_addr = sg_dma_address(sg);
 530                 size_t len = sg_dma_len(sg);
 531
 532                 if (!len)
 533                         goto err_get_desc;
 534
 535                 do {
 536                         dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
 537                                 i, sg, len, (unsigned long long)sg_addr);
 538
 539                         if (direction == DMA_FROM_DEVICE)
 540                                 new = sh_dmae_add_desc(sh_chan, flags,
 541                                                 &sg_addr, addr, &len, &first,
 542                                                 direction);
 543                         else
 544                                 new = sh_dmae_add_desc(sh_chan, flags,
 545                                                 addr, &sg_addr, &len, &first,
 546                                                 direction);
 547                         if (!new)
 548                                 goto err_get_desc;
 549
 550                         new->chunks = chunks--;
 551                         list_add_tail(&new->node, &tx_list);
 552                 } while (len);
 553         }
 554
 555         if (new != first)
 556                 new->async_tx.cookie = -ENOSPC;
 557
 558         /* Put them back on the free list, so, they don't get lost */
 559         list_splice_tail(&tx_list, &sh_chan->ld_free);
 560
 561         spin_unlock_bh(&sh_chan->desc_lock);
 562
 563         return &first->async_tx;
 564
 565 err_get_desc:
 566         list_for_each_entry(new, &tx_list, node)
 567                 new->mark = DESC_IDLE;
 568         list_splice(&tx_list, &sh_chan->ld_free);
 569
 570         spin_unlock_bh(&sh_chan->desc_lock);
 571
 572         return NULL;
 573 }
 574
 575 static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
 576         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
 577         size_t len, unsigned long flags)
 578 {
 579         struct sh_dmae_chan *sh_chan;
 580         struct scatterlist sg;
 581
 582         if (!chan || !len)
 583                 return NULL;
 584
 585         sh_chan = to_sh_chan(chan);
 586
 587         sg_init_table(&sg, 1);
 588         sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
 589                     offset_in_page(dma_src));
 590         sg_dma_address(&sg) = dma_src;
 591         sg_dma_len(&sg) = len;
 592
 593         return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL,
 594                                flags);
 595 }
 596
 597 static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
 598         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
 599         enum dma_data_direction direction, unsigned long flags)
 600 {
 601         struct sh_dmae_slave *param;
 602         struct sh_dmae_chan *sh_chan;
 603         dma_addr_t slave_addr;
 604
 605         if (!chan)
 606                 return NULL;
 607
 608         sh_chan = to_sh_chan(chan);
 609         param = chan->private;
 610
 611         /* Someone calling slave DMA on a public channel? */
 612         if (!param || !sg_len) {
 613                 dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n",
 614                          __func__, param, sg_len, param ? param->slave_id : -1);
 615                 return NULL;
 616         }
 617
 618         slave_addr = param->config->addr;
 619
 620         /*
 621          * if (param != NULL), this is a successfully requested slave channel,
 622          * therefore param->config != NULL too.
 623          */
 624         return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &slave_addr,
 625                                direction, flags);
 626 }
 627
 628 static int sh_dmae_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 629                            unsigned long arg)
 630 {
 631         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 632
 633         /* Only supports DMA_TERMINATE_ALL */
 634         if (cmd != DMA_TERMINATE_ALL)
 635                 return -ENXIO;
 636
 637         if (!chan)
 638                 return -EINVAL;
 639
 640         spin_lock_bh(&sh_chan->desc_lock);
 641         dmae_halt(sh_chan);
 642
 643         if (!list_empty(&sh_chan->ld_queue)) {
 644                 /* Record partial transfer */
 645                 struct sh_desc *desc = list_entry(sh_chan->ld_queue.next,
 646                                                   struct sh_desc, node);
 647                 desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
 648                         sh_chan->xmit_shift;
 649
 650         }
 651         spin_unlock_bh(&sh_chan->desc_lock);
 652
 653         sh_dmae_chan_ld_cleanup(sh_chan, true);
 654
 655         return 0;
 656 }
 657
 658 static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
 659 {
 660         struct sh_desc *desc, *_desc;
 661         /* Is the "exposed" head of a chain acked? */
 662         bool head_acked = false;
 663         dma_cookie_t cookie = 0;
 664         dma_async_tx_callback callback = NULL;
 665         void *param = NULL;
 666
 667         spin_lock_bh(&sh_chan->desc_lock);
 668         list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
 669                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
 670
 671                 BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
 672                 BUG_ON(desc->mark != DESC_SUBMITTED &&
 673                        desc->mark != DESC_COMPLETED &&
 674                        desc->mark != DESC_WAITING);
 675
 676                 /*
 677                  * queue is ordered, and we use this loop to (1) clean up all
 678                  * completed descriptors, and to (2) update descriptor flags of
 679                  * any chunks in a (partially) completed chain
 680                  */
 681                 if (!all && desc->mark == DESC_SUBMITTED &&
 682                     desc->cookie != cookie)
 683                         break;
 684
 685                 if (tx->cookie > 0)
 686                         cookie = tx->cookie;
 687
 688                 if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
 689                         if (sh_chan->completed_cookie != desc->cookie - 1)
 690                                 dev_dbg(sh_chan->dev,
 691                                         "Completing cookie %d, expected %d\n",
 692                                         desc->cookie,
 693                                         sh_chan->completed_cookie + 1);
 694                         sh_chan->completed_cookie = desc->cookie;
 695                 }
 696
 697                 /* Call callback on the last chunk */
 698                 if (desc->mark == DESC_COMPLETED && tx->callback) {
 699                         desc->mark = DESC_WAITING;
 700                         callback = tx->callback;
 701                         param = tx->callback_param;
 702                         dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n",
 703                                 tx->cookie, tx, sh_chan->id);
 704                         BUG_ON(desc->chunks != 1);
 705                         break;
 706                 }
 707
 708                 if (tx->cookie > 0 || tx->cookie == -EBUSY) {
 709                         if (desc->mark == DESC_COMPLETED) {
 710                                 BUG_ON(tx->cookie < 0);
 711                                 desc->mark = DESC_WAITING;
 712                         }
 713                         head_acked = async_tx_test_ack(tx);
 714                 } else {
 715                         switch (desc->mark) {
 716                         case DESC_COMPLETED:
 717                                 desc->mark = DESC_WAITING;
 718                                 /* Fall through */
 719                         case DESC_WAITING:
 720                                 if (head_acked)
 721                                         async_tx_ack(&desc->async_tx);
 722                         }
 723                 }
 724
 725                 dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n",
 726                         tx, tx->cookie);
 727
 728                 if (((desc->mark == DESC_COMPLETED ||
 729                       desc->mark == DESC_WAITING) &&
 730                      async_tx_test_ack(&desc->async_tx)) || all) {
 731                         /* Remove from ld_queue list */
 732                         desc->mark = DESC_IDLE;
 733                         list_move(&desc->node, &sh_chan->ld_free);
 734                 }
 735         }
 736
 737         if (all && !callback)
 738                 /*
 739                  * Terminating and the loop completed normally: forgive
 740                  * uncompleted cookies
 741                  */
 742                 sh_chan->completed_cookie = sh_chan->common.cookie;
 743
 744         spin_unlock_bh(&sh_chan->desc_lock);
 745
 746         if (callback)
 747                 callback(param);
 748
 749         return callback;
 750 }
 751
 752 /*
 753  * sh_chan_ld_cleanup - Clean up link descriptors
 754  *
 755  * This function cleans up the ld_queue of DMA channel.
 756  */
 757 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
 758 {
 759         while (__ld_cleanup(sh_chan, all))
 760                 ;
 761 }
 762
 763 static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
 764 {
 765         struct sh_desc *desc;
 766
 767         spin_lock_bh(&sh_chan->desc_lock);
 768         /* DMA work check */
 769         if (dmae_is_busy(sh_chan))
 770                 goto sh_chan_xfer_ld_queue_end;
 771
 772         /* Find the first not transferred descriptor */
 773         list_for_each_entry(desc, &sh_chan->ld_queue, node)
 774                 if (desc->mark == DESC_SUBMITTED) {
 775                         dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n",
 776                                 desc->async_tx.cookie, sh_chan->id,
 777                                 desc->hw.tcr, desc->hw.sar, desc->hw.dar);
 778                         /* Get the ld start address from ld_queue */
 779                         dmae_set_reg(sh_chan, &desc->hw);
 780                         dmae_start(sh_chan);
 781                         break;
 782                 }
 783
 784 sh_chan_xfer_ld_queue_end:
 785         spin_unlock_bh(&sh_chan->desc_lock);
 786 }
 787
 788 static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
 789 {
 790         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 791         sh_chan_xfer_ld_queue(sh_chan);
 792 }
 793
 794 static enum dma_status sh_dmae_tx_status(struct dma_chan *chan,
 795                                         dma_cookie_t cookie,
 796                                         struct dma_tx_state *txstate)
 797 {
 798         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 799         dma_cookie_t last_used;
 800         dma_cookie_t last_complete;
 801         enum dma_status status;
 802
 803         sh_dmae_chan_ld_cleanup(sh_chan, false);
 804
 805         /* First read completed cookie to avoid a skew */
 806         last_complete = sh_chan->completed_cookie;
 807         rmb();
 808         last_used = chan->cookie;
 809         BUG_ON(last_complete < 0);
 810         dma_set_tx_state(txstate, last_complete, last_used, 0);
 811
 812         spin_lock_bh(&sh_chan->desc_lock);
 813
 814         status = dma_async_is_complete(cookie, last_complete, last_used);
 815
 816         /*
 817          * If we don't find cookie on the queue, it has been aborted and we have
 818          * to report error
 819          */
 820         if (status != DMA_SUCCESS) {
 821                 struct sh_desc *desc;
 822                 status = DMA_ERROR;
 823                 list_for_each_entry(desc, &sh_chan->ld_queue, node)
 824                         if (desc->cookie == cookie) {
 825                                 status = DMA_IN_PROGRESS;
 826                                 break;
 827                         }
 828         }
 829
 830         spin_unlock_bh(&sh_chan->desc_lock);
 831
 832         return status;
 833 }
 834
 835 static irqreturn_t sh_dmae_interrupt(int irq, void *data)
 836 {
 837         irqreturn_t ret = IRQ_NONE;
 838         struct sh_dmae_chan *sh_chan = data;
 839         u32 chcr;
 840
 841         spin_lock(&sh_chan->desc_lock);
 842
 843         chcr = sh_dmae_readl(sh_chan, CHCR);
 844
 845         if (chcr & CHCR_TE) {
 846                 /* DMA stop */
 847                 dmae_halt(sh_chan);
 848
 849                 ret = IRQ_HANDLED;
 850                 tasklet_schedule(&sh_chan->tasklet);
 851         }
 852
 853         spin_unlock(&sh_chan->desc_lock);
 854
 855         return ret;
 856 }
 857
 858 /* Called from error IRQ or NMI */
 859 static bool sh_dmae_reset(struct sh_dmae_device *shdev)
 860 {
 861         unsigned int handled = 0;
 862         int i;
 863
 864         /* halt the dma controller */
 865         sh_dmae_ctl_stop(shdev);
 866
 867         /* We cannot detect, which channel caused the error, have to reset all */
 868         for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
 869                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
 870                 struct sh_desc *desc;
 871                 LIST_HEAD(dl);
 872
 873                 if (!sh_chan)
 874                         continue;
 875
 876                 spin_lock(&sh_chan->desc_lock);
 877
 878                 /* Stop the channel */
 879                 dmae_halt(sh_chan);
 880
 881                 list_splice_init(&sh_chan->ld_queue, &dl);
 882
 883                 spin_unlock(&sh_chan->desc_lock);
 884
 885                 /* Complete all  */
 886                 list_for_each_entry(desc, &dl, node) {
 887                         struct dma_async_tx_descriptor *tx = &desc->async_tx;
 888                         desc->mark = DESC_IDLE;
 889                         if (tx->callback)
 890                                 tx->callback(tx->callback_param);
 891                 }
 892
 893                 spin_lock(&sh_chan->desc_lock);
 894                 list_splice(&dl, &sh_chan->ld_free);
 895                 spin_unlock(&sh_chan->desc_lock);
 896
 897                 handled++;
 898         }
 899
 900         sh_dmae_rst(shdev);
 901
 902         return !!handled;
 903 }
 904
 905 static irqreturn_t sh_dmae_err(int irq, void *data)
 906 {
 907         struct sh_dmae_device *shdev = data;
 908
 909         if (!(dmaor_read(shdev) & DMAOR_AE))
 910                 return IRQ_NONE;
 911
 912         sh_dmae_reset(data);
 913         return IRQ_HANDLED;
 914 }
 915
 916 static void dmae_do_tasklet(unsigned long data)
 917 {
 918         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
 919         struct sh_desc *desc;
 920         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
 921         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
 922
 923         spin_lock(&sh_chan->desc_lock);
 924         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
 925                 if (desc->mark == DESC_SUBMITTED &&
 926                     ((desc->direction == DMA_FROM_DEVICE &&
 927                       (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
 928                      (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
 929                         dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
 930                                 desc->async_tx.cookie, &desc->async_tx,
 931                                 desc->hw.dar);
 932                         desc->mark = DESC_COMPLETED;
 933                         break;
 934                 }
 935         }
 936         spin_unlock(&sh_chan->desc_lock);
 937
 938         /* Next desc */
 939         sh_chan_xfer_ld_queue(sh_chan);
 940         sh_dmae_chan_ld_cleanup(sh_chan, false);
 941 }
 942
 943 static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
 944 {
 945         /* Fast path out if NMIF is not asserted for this controller */
 946         if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
 947                 return false;
 948
 949         return sh_dmae_reset(shdev);
 950 }
 951
 952 static int sh_dmae_nmi_handler(struct notifier_block *self,
 953                                unsigned long cmd, void *data)
 954 {
 955         struct sh_dmae_device *shdev;
 956         int ret = NOTIFY_DONE;
 957         bool triggered;
 958
 959         /*
 960          * Only concern ourselves with NMI events.
 961          *
 962          * Normally we would check the die chain value, but as this needs
 963          * to be architecture independent, check for NMI context instead.
 964          */
 965         if (!in_nmi())
 966                 return NOTIFY_DONE;
 967
 968         rcu_read_lock();
 969         list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) {
 970                 /*
 971                  * Only stop if one of the controllers has NMIF asserted,
 972                  * we do not want to interfere with regular address error
 973                  * handling or NMI events that don't concern the DMACs.
 974                  */
 975                 triggered = sh_dmae_nmi_notify(shdev);
 976                 if (triggered == true)
 977                         ret = NOTIFY_OK;
 978         }
 979         rcu_read_unlock();
 980
 981         return ret;
 982 }
 983
 984 static struct notifier_block sh_dmae_nmi_notifier __read_mostly = {
 985         .notifier_call  = sh_dmae_nmi_handler,
 986
 987         /* Run before NMI debug handler and KGDB */
 988         .priority       = 1,
 989 };
 990
 991 static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
 992                                         int irq, unsigned long flags)
 993 {
 994         int err;
 995         const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
 996         struct platform_device *pdev = to_platform_device(shdev->common.dev);
 997         struct sh_dmae_chan *new_sh_chan;
 998
 999         /* alloc channel */
1000         new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
1001         if (!new_sh_chan) {
1002                 dev_err(shdev->common.dev,
1003                         "No free memory for allocating dma channels!\n");
1004                 return -ENOMEM;
1005         }
1006
1007         /* copy struct dma_device */
1008         new_sh_chan->common.device = &shdev->common;
1009
1010         new_sh_chan->dev = shdev->common.dev;
1011         new_sh_chan->id = id;
1012         new_sh_chan->irq = irq;
1013         new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
1014
1015         /* Init DMA tasklet */
1016         tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
1017                         (unsigned long)new_sh_chan);
1018
1019         spin_lock_init(&new_sh_chan->desc_lock);
1020
1021         /* Init descripter manage list */
1022         INIT_LIST_HEAD(&new_sh_chan->ld_queue);
1023         INIT_LIST_HEAD(&new_sh_chan->ld_free);
1024
1025         /* Add the channel to DMA device channel list */
1026         list_add_tail(&new_sh_chan->common.device_node,
1027                         &shdev->common.channels);
1028         shdev->common.chancnt++;
1029
1030         if (pdev->id >= 0)
1031                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
1032                          "sh-dmae%d.%d", pdev->id, new_sh_chan->id);
1033         else
1034                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
1035                          "sh-dma%d", new_sh_chan->id);
1036
1037         /* set up channel irq */
1038         err = request_irq(irq, &sh_dmae_interrupt, flags,
1039                           new_sh_chan->dev_id, new_sh_chan);
1040         if (err) {
1041                 dev_err(shdev->common.dev, "DMA channel %d request_irq error "
1042                         "with return %d\n", id, err);
1043                 goto err_no_irq;
1044         }
1045
1046         shdev->chan[id] = new_sh_chan;
1047         return 0;
1048
1049 err_no_irq:
1050         /* remove from dmaengine device node */
1051         list_del(&new_sh_chan->common.device_node);
1052         kfree(new_sh_chan);
1053         return err;
1054 }
1055
1056 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
1057 {
1058         int i;
1059
1060         for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
1061                 if (shdev->chan[i]) {
1062                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
1063
1064                         free_irq(sh_chan->irq, sh_chan);
1065
1066                         list_del(&sh_chan->common.device_node);
1067                         kfree(sh_chan);
1068                         shdev->chan[i] = NULL;
1069                 }
1070         }
1071         shdev->common.chancnt = 0;
1072 }
1073
1074 static int __init sh_dmae_probe(struct platform_device *pdev)
1075 {
1076         struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
1077         unsigned long irqflags = IRQF_DISABLED,
1078                 chan_flag[SH_DMAC_MAX_CHANNELS] = {};
1079         int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
1080         int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
1081         struct sh_dmae_device *shdev;
1082         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
1083
1084         /* get platform data */
1085         if (!pdata || !pdata->channel_num)
1086                 return -ENODEV;
1087
1088         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1089         /* DMARS area is optional */
1090         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1091         /*
1092          * IRQ resources:
1093          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
1094          *    the error IRQ, in which case it is the only IRQ in this resource:
1095          *    start == end. If it is the only IRQ resource, all channels also
1096          *    use the same IRQ.
1097          * 2. DMA channel IRQ resources can be specified one per resource or in
1098          *    ranges (start != end)
1099          * 3. iff all events (channels and, optionally, error) on this
1100          *    controller use the same IRQ, only one IRQ resource can be
1101          *    specified, otherwise there must be one IRQ per channel, even if
1102          *    some of them are equal
1103          * 4. if all IRQs on this controller are equal or if some specific IRQs
1104          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
1105          *    requested with the IRQF_SHARED flag
1106          */
1107         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1108         if (!chan || !errirq_res)
1109                 return -ENODEV;
1110
1111         if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
1112                 dev_err(&pdev->dev, "DMAC register region already claimed\n");
1113                 return -EBUSY;
1114         }
1115
1116         if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
1117                 dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
1118                 err = -EBUSY;
1119                 goto ermrdmars;
1120         }
1121
1122         err = -ENOMEM;
1123         shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
1124         if (!shdev) {
1125                 dev_err(&pdev->dev, "Not enough memory\n");
1126                 goto ealloc;
1127         }
1128
1129         shdev->chan_reg = ioremap(chan->start, resource_size(chan));
1130         if (!shdev->chan_reg)
1131                 goto emapchan;
1132         if (dmars) {
1133                 shdev->dmars = ioremap(dmars->start, resource_size(dmars));
1134                 if (!shdev->dmars)
1135                         goto emapdmars;
1136         }
1137
1138         /* platform data */
1139         shdev->pdata = pdata;
1140
1141         platform_set_drvdata(pdev, shdev);
1142
1143         pm_runtime_enable(&pdev->dev);
1144         pm_runtime_get_sync(&pdev->dev);
1145
1146         spin_lock_irq(&sh_dmae_lock);
1147         list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
1148         spin_unlock_irq(&sh_dmae_lock);
1149
1150         /* reset dma controller - only needed as a test */
1151         err = sh_dmae_rst(shdev);
1152         if (err)
1153                 goto rst_err;
1154
1155         INIT_LIST_HEAD(&shdev->common.channels);
1156
1157         dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
1158         if (pdata->slave && pdata->slave_num)
1159                 dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
1160
1161         shdev->common.device_alloc_chan_resources
1162                 = sh_dmae_alloc_chan_resources;
1163         shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
1164         shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
1165         shdev->common.device_tx_status = sh_dmae_tx_status;
1166         shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
1167
1168         /* Compulsory for DMA_SLAVE fields */
1169         shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg;
1170         shdev->common.device_control = sh_dmae_control;
1171
1172         shdev->common.dev = &pdev->dev;
1173         /* Default transfer size of 32 bytes requires 32-byte alignment */
1174         shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1175
1176 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1177         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1178
1179         if (!chanirq_res)
1180                 chanirq_res = errirq_res;
1181         else
1182                 irqres++;
1183
1184         if (chanirq_res == errirq_res ||
1185             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
1186                 irqflags = IRQF_SHARED;
1187
1188         errirq = errirq_res->start;
1189
1190         err = request_irq(errirq, sh_dmae_err, irqflags,
1191                           "DMAC Address Error", shdev);
1192         if (err) {
1193                 dev_err(&pdev->dev,
1194                         "DMA failed requesting irq #%d, error %d\n",
1195                         errirq, err);
1196                 goto eirq_err;
1197         }
1198
1199 #else
1200         chanirq_res = errirq_res;
1201 #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
1202
1203         if (chanirq_res->start == chanirq_res->end &&
1204             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
1205                 /* Special case - all multiplexed */
1206                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
1207                         if (irq_cnt < SH_DMAC_MAX_CHANNELS) {
1208                                 chan_irq[irq_cnt] = chanirq_res->start;
1209                                 chan_flag[irq_cnt] = IRQF_SHARED;
1210                         } else {
1211                                 irq_cap = 1;
1212                                 break;
1213                         }
1214                 }
1215         } else {
1216                 do {
1217                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
1218                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
1219                                     IORESOURCE_IRQ_SHAREABLE)
1220                                         chan_flag[irq_cnt] = IRQF_SHARED;
1221                                 else
1222                                         chan_flag[irq_cnt] = IRQF_DISABLED;
1223                                 dev_dbg(&pdev->dev,
1224                                         "Found IRQ %d for channel %d\n",
1225                                         i, irq_cnt);
1226                                 chan_irq[irq_cnt++] = i;
1227
1228                                 if (irq_cnt >= SH_DMAC_MAX_CHANNELS)
1229                                         break;
1230                         }
1231
1232                         if (irq_cnt >= SH_DMAC_MAX_CHANNELS) {
1233                                 irq_cap = 1;
1234                                 break;
1235                         }
1236                         chanirq_res = platform_get_resource(pdev,
1237                                                 IORESOURCE_IRQ, ++irqres);
1238                 } while (irq_cnt < pdata->channel_num && chanirq_res);
1239         }
1240
1241         /* Create DMA Channel */
1242         for (i = 0; i < irq_cnt; i++) {
1243                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
1244                 if (err)
1245                         goto chan_probe_err;
1246         }
1247
1248         if (irq_cap)
1249                 dev_notice(&pdev->dev, "Attempting to register %d DMA "
1250                            "channels when a maximum of %d are supported.\n",
1251                            pdata->channel_num, SH_DMAC_MAX_CHANNELS);
1252
1253         pm_runtime_put(&pdev->dev);
1254
1255         dma_async_device_register(&shdev->common);
1256
1257         return err;
1258
1259 chan_probe_err:
1260         sh_dmae_chan_remove(shdev);
1261
1262 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1263         free_irq(errirq, shdev);
1264 eirq_err:
1265 #endif
1266 rst_err:
1267         spin_lock_irq(&sh_dmae_lock);
1268         list_del_rcu(&shdev->node);
1269         spin_unlock_irq(&sh_dmae_lock);
1270
1271         pm_runtime_put(&pdev->dev);
1272         pm_runtime_disable(&pdev->dev);
1273
1274         if (dmars)
1275                 iounmap(shdev->dmars);
1276
1277         platform_set_drvdata(pdev, NULL);
1278 emapdmars:
1279         iounmap(shdev->chan_reg);
1280         synchronize_rcu();
1281 emapchan:
1282         kfree(shdev);
1283 ealloc:
1284         if (dmars)
1285                 release_mem_region(dmars->start, resource_size(dmars));
1286 ermrdmars:
1287         release_mem_region(chan->start, resource_size(chan));
1288
1289         return err;
1290 }
1291
1292 static int __exit sh_dmae_remove(struct platform_device *pdev)
1293 {
1294         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1295         struct resource *res;
1296         int errirq = platform_get_irq(pdev, 0);
1297
1298         dma_async_device_unregister(&shdev->common);
1299
1300         if (errirq > 0)
1301                 free_irq(errirq, shdev);
1302
1303         spin_lock_irq(&sh_dmae_lock);
1304         list_del_rcu(&shdev->node);
1305         spin_unlock_irq(&sh_dmae_lock);
1306
1307         /* channel data remove */
1308         sh_dmae_chan_remove(shdev);
1309
1310         pm_runtime_disable(&pdev->dev);
1311
1312         if (shdev->dmars)
1313                 iounmap(shdev->dmars);
1314         iounmap(shdev->chan_reg);
1315
1316         platform_set_drvdata(pdev, NULL);
1317
1318         synchronize_rcu();
1319         kfree(shdev);
1320
1321         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1322         if (res)
1323                 release_mem_region(res->start, resource_size(res));
1324         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1325         if (res)
1326                 release_mem_region(res->start, resource_size(res));
1327
1328         return 0;
1329 }
1330
1331 static void sh_dmae_shutdown(struct platform_device *pdev)
1332 {
1333         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1334         sh_dmae_ctl_stop(shdev);
1335 }
1336
1337 static int sh_dmae_runtime_suspend(struct device *dev)
1338 {
1339         return 0;
1340 }
1341
1342 static int sh_dmae_runtime_resume(struct device *dev)
1343 {
1344         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
1345
1346         return sh_dmae_rst(shdev);
1347 }
1348
1349 #ifdef CONFIG_PM
1350 static int sh_dmae_suspend(struct device *dev)
1351 {
1352         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
1353         int i;
1354
1355         for (i = 0; i < shdev->pdata->channel_num; i++) {
1356                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
1357                 if (sh_chan->descs_allocated)
1358                         sh_chan->pm_error = pm_runtime_put_sync(dev);
1359         }
1360
1361         return 0;
1362 }
1363
1364 static int sh_dmae_resume(struct device *dev)
1365 {
1366         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
1367         int i;
1368
1369         for (i = 0; i < shdev->pdata->channel_num; i++) {
1370                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
1371                 struct sh_dmae_slave *param = sh_chan->common.private;
1372
1373                 if (!sh_chan->descs_allocated)
1374                         continue;
1375
1376                 if (!sh_chan->pm_error)
1377                         pm_runtime_get_sync(dev);
1378
1379                 if (param) {
1380                         const struct sh_dmae_slave_config *cfg = param->config;
1381                         dmae_set_dmars(sh_chan, cfg->mid_rid);
1382                         dmae_set_chcr(sh_chan, cfg->chcr);
1383                 } else {
1384                         dmae_init(sh_chan);
1385                 }
1386         }
1387
1388         return 0;
1389 }
1390 #else
1391 #define sh_dmae_suspend NULL
1392 #define sh_dmae_resume NULL
1393 #endif
1394
1395 const struct dev_pm_ops sh_dmae_pm = {
1396         .suspend                = sh_dmae_suspend,
1397         .resume                 = sh_dmae_resume,
1398         .runtime_suspend        = sh_dmae_runtime_suspend,
1399         .runtime_resume         = sh_dmae_runtime_resume,
1400 };
1401
1402 static struct platform_driver sh_dmae_driver = {
1403         .remove         = __exit_p(sh_dmae_remove),
1404         .shutdown       = sh_dmae_shutdown,
1405         .driver = {
1406                 .owner  = THIS_MODULE,
1407                 .name   = "sh-dma-engine",
1408                 .pm     = &sh_dmae_pm,
1409         },
1410 };
1411
1412 static int __init sh_dmae_init(void)
1413 {
1414         /* Wire up NMI handling */
1415         int err = register_die_notifier(&sh_dmae_nmi_notifier);
1416         if (err)
1417                 return err;
1418
1419         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
1420 }
1421 module_init(sh_dmae_init);
1422
1423 static void __exit sh_dmae_exit(void)
1424 {
1425         platform_driver_unregister(&sh_dmae_driver);
1426
1427         unregister_die_notifier(&sh_dmae_nmi_notifier);
1428 }
1429 module_exit(sh_dmae_exit);
1430
1431 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
1432 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
1433 MODULE_LICENSE("GPL");
1434 MODULE_ALIAS("platform:sh-dma-engine");