2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
70 * - Break out common code from arch/arm/mach-s3c64xx and share
72 #include <linux/amba/bus.h>
73 #include <linux/amba/pl08x.h>
74 #include <linux/debugfs.h>
75 #include <linux/delay.h>
76 #include <linux/device.h>
77 #include <linux/dmaengine.h>
78 #include <linux/dmapool.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/interrupt.h>
82 #include <linux/module.h>
83 #include <linux/pm_runtime.h>
84 #include <linux/seq_file.h>
85 #include <linux/slab.h>
86 #include <asm/hardware/pl080.h>
88 #include "dmaengine.h"
91 #define DRIVER_NAME "pl08xdmac"
93 static struct amba_driver pl08x_amba_driver;
94 struct pl08x_driver_data;
97 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
98 * @channels: the number of channels available in this variant
99 * @dualmaster: whether this version supports dual AHB masters or not.
100 * @nomadik: whether the channels have Nomadik security extension bits
101 * that need to be checked for permission before use and some registers are
111 * PL08X private data structures
112 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
113 * start & end do not - their bus bit info is in cctl. Also note that these
114 * are fixed 32-bit quantities.
124 * struct pl08x_bus_data - information of source or destination
125 * busses for a transfer
126 * @addr: current address
127 * @maxwidth: the maximum width of a transfer on this bus
128 * @buswidth: the width of this bus in bytes: 1, 2 or 4
130 struct pl08x_bus_data {
137 * struct pl08x_phy_chan - holder for the physical channels
138 * @id: physical index to this channel
139 * @lock: a lock to use when altering an instance of this struct
140 * @serving: the virtual channel currently being served by this physical
142 * @locked: channel unavailable for the system, e.g. dedicated to secure
145 struct pl08x_phy_chan {
149 struct pl08x_dma_chan *serving;
154 * struct pl08x_sg - structure containing data per sg
155 * @src_addr: src address of sg
156 * @dst_addr: dst address of sg
157 * @len: transfer len in bytes
158 * @node: node for txd's dsg_list
164 struct list_head node;
168 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
169 * @vd: virtual DMA descriptor
170 * @dsg_list: list of children sg's
171 * @llis_bus: DMA memory address (physical) start for the LLIs
172 * @llis_va: virtual memory address start for the LLIs
173 * @cctl: control reg values for current txd
174 * @ccfg: config reg values for current txd
175 * @done: this marks completed descriptors, which should not have their
179 struct virt_dma_desc vd;
180 struct list_head dsg_list;
182 struct pl08x_lli *llis_va;
183 /* Default cctl value for LLIs */
186 * Settings to be put into the physical channel when we
187 * trigger this txd. Other registers are in llis_va[0].
194 * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
196 * @PL08X_CHAN_IDLE: the channel is idle
197 * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
198 * channel and is running a transfer on it
199 * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
200 * channel, but the transfer is currently paused
201 * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
202 * channel to become available (only pertains to memcpy channels)
204 enum pl08x_dma_chan_state {
212 * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
213 * @vc: wrappped virtual channel
214 * @phychan: the physical channel utilized by this channel, if there is one
215 * @name: name of channel
216 * @cd: channel platform data
217 * @runtime_addr: address for RX/TX according to the runtime config
218 * @at: active transaction on this channel
219 * @lock: a lock for this channel data
220 * @host: a pointer to the host (internal use)
221 * @state: whether the channel is idle, paused, running etc
222 * @slave: whether this channel is a device (slave) or for memcpy
223 * @signal: the physical DMA request signal which this channel is using
224 * @mux_use: count of descriptors using this DMA request signal setting
226 struct pl08x_dma_chan {
227 struct virt_dma_chan vc;
228 struct pl08x_phy_chan *phychan;
230 const struct pl08x_channel_data *cd;
231 struct dma_slave_config cfg;
232 struct pl08x_txd *at;
233 struct pl08x_driver_data *host;
234 enum pl08x_dma_chan_state state;
241 * struct pl08x_driver_data - the local state holder for the PL08x
242 * @slave: slave engine for this instance
243 * @memcpy: memcpy engine for this instance
244 * @base: virtual memory base (remapped) for the PL08x
245 * @adev: the corresponding AMBA (PrimeCell) bus entry
246 * @vd: vendor data for this PL08x variant
247 * @pd: platform data passed in from the platform/machine
248 * @phy_chans: array of data for the physical channels
249 * @pool: a pool for the LLI descriptors
250 * @pool_ctr: counter of LLIs in the pool
251 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
253 * @mem_buses: set to indicate memory transfers on AHB2.
254 * @lock: a spinlock for this struct
256 struct pl08x_driver_data {
257 struct dma_device slave;
258 struct dma_device memcpy;
260 struct amba_device *adev;
261 const struct vendor_data *vd;
262 struct pl08x_platform_data *pd;
263 struct pl08x_phy_chan *phy_chans;
264 struct dma_pool *pool;
271 * PL08X specific defines
274 /* Size (bytes) of each LLI buffer allocated for one transfer */
275 # define PL08X_LLI_TSFR_SIZE 0x2000
277 /* Maximum times we call dma_pool_alloc on this pool without freeing */
278 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
279 #define PL08X_ALIGN 8
281 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
283 return container_of(chan, struct pl08x_dma_chan, vc.chan);
286 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
288 return container_of(tx, struct pl08x_txd, vd.tx);
294 * This gives us the DMA request input to the PL08x primecell which the
295 * peripheral described by the channel data will be routed to, possibly
296 * via a board/SoC specific external MUX. One important point to note
297 * here is that this does not depend on the physical channel.
299 static int pl08x_request_mux(struct pl08x_dma_chan *plchan)
301 const struct pl08x_platform_data *pd = plchan->host->pd;
304 if (plchan->mux_use++ == 0 && pd->get_signal) {
305 ret = pd->get_signal(plchan->cd);
311 plchan->signal = ret;
316 static void pl08x_release_mux(struct pl08x_dma_chan *plchan)
318 const struct pl08x_platform_data *pd = plchan->host->pd;
320 if (plchan->signal >= 0) {
321 WARN_ON(plchan->mux_use == 0);
323 if (--plchan->mux_use == 0 && pd->put_signal) {
324 pd->put_signal(plchan->cd, plchan->signal);
331 * Physical channel handling
334 /* Whether a certain channel is busy or not */
335 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
339 val = readl(ch->base + PL080_CH_CONFIG);
340 return val & PL080_CONFIG_ACTIVE;
344 * Set the initial DMA register values i.e. those for the first LLI
345 * The next LLI pointer and the configuration interrupt bit have
346 * been set when the LLIs were constructed. Poke them into the hardware
347 * and start the transfer.
349 static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
351 struct pl08x_driver_data *pl08x = plchan->host;
352 struct pl08x_phy_chan *phychan = plchan->phychan;
353 struct virt_dma_desc *vd = vchan_next_desc(&plchan->vc);
354 struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
355 struct pl08x_lli *lli;
358 list_del(&txd->vd.node);
362 /* Wait for channel inactive */
363 while (pl08x_phy_channel_busy(phychan))
366 lli = &txd->llis_va[0];
368 dev_vdbg(&pl08x->adev->dev,
369 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
370 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
371 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
374 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
375 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
376 writel(lli->lli, phychan->base + PL080_CH_LLI);
377 writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
378 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
380 /* Enable the DMA channel */
381 /* Do not access config register until channel shows as disabled */
382 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
385 /* Do not access config register until channel shows as inactive */
386 val = readl(phychan->base + PL080_CH_CONFIG);
387 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
388 val = readl(phychan->base + PL080_CH_CONFIG);
390 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
394 * Pause the channel by setting the HALT bit.
396 * For M->P transfers, pause the DMAC first and then stop the peripheral -
397 * the FIFO can only drain if the peripheral is still requesting data.
398 * (note: this can still timeout if the DMAC FIFO never drains of data.)
400 * For P->M transfers, disable the peripheral first to stop it filling
401 * the DMAC FIFO, and then pause the DMAC.
403 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
408 /* Set the HALT bit and wait for the FIFO to drain */
409 val = readl(ch->base + PL080_CH_CONFIG);
410 val |= PL080_CONFIG_HALT;
411 writel(val, ch->base + PL080_CH_CONFIG);
413 /* Wait for channel inactive */
414 for (timeout = 1000; timeout; timeout--) {
415 if (!pl08x_phy_channel_busy(ch))
419 if (pl08x_phy_channel_busy(ch))
420 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
423 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
427 /* Clear the HALT bit */
428 val = readl(ch->base + PL080_CH_CONFIG);
429 val &= ~PL080_CONFIG_HALT;
430 writel(val, ch->base + PL080_CH_CONFIG);
434 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
435 * clears any pending interrupt status. This should not be used for
436 * an on-going transfer, but as a method of shutting down a channel
437 * (eg, when it's no longer used) or terminating a transfer.
439 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
440 struct pl08x_phy_chan *ch)
442 u32 val = readl(ch->base + PL080_CH_CONFIG);
444 val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
445 PL080_CONFIG_TC_IRQ_MASK);
447 writel(val, ch->base + PL080_CH_CONFIG);
449 writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
450 writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
453 static inline u32 get_bytes_in_cctl(u32 cctl)
455 /* The source width defines the number of bytes */
456 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
458 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
459 case PL080_WIDTH_8BIT:
461 case PL080_WIDTH_16BIT:
464 case PL080_WIDTH_32BIT:
471 /* The channel should be paused when calling this */
472 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
474 struct pl08x_phy_chan *ch;
475 struct pl08x_txd *txd;
478 ch = plchan->phychan;
482 * Follow the LLIs to get the number of remaining
483 * bytes in the currently active transaction.
486 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
488 /* First get the remaining bytes in the active transfer */
489 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
492 struct pl08x_lli *llis_va = txd->llis_va;
493 dma_addr_t llis_bus = txd->llis_bus;
496 BUG_ON(clli < llis_bus || clli >= llis_bus +
497 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
500 * Locate the next LLI - as this is an array,
501 * it's simple maths to find.
503 index = (clli - llis_bus) / sizeof(struct pl08x_lli);
505 for (; index < MAX_NUM_TSFR_LLIS; index++) {
506 bytes += get_bytes_in_cctl(llis_va[index].cctl);
509 * A LLI pointer of 0 terminates the LLI list
511 if (!llis_va[index].lli)
521 * Allocate a physical channel for a virtual channel
523 * Try to locate a physical channel to be used for this transfer. If all
524 * are taken return NULL and the requester will have to cope by using
525 * some fallback PIO mode or retrying later.
527 static struct pl08x_phy_chan *
528 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
529 struct pl08x_dma_chan *virt_chan)
531 struct pl08x_phy_chan *ch = NULL;
535 for (i = 0; i < pl08x->vd->channels; i++) {
536 ch = &pl08x->phy_chans[i];
538 spin_lock_irqsave(&ch->lock, flags);
540 if (!ch->locked && !ch->serving) {
541 ch->serving = virt_chan;
542 spin_unlock_irqrestore(&ch->lock, flags);
546 spin_unlock_irqrestore(&ch->lock, flags);
549 if (i == pl08x->vd->channels) {
550 /* No physical channel available, cope with it */
557 /* Mark the physical channel as free. Note, this write is atomic. */
558 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
559 struct pl08x_phy_chan *ch)
565 * Try to allocate a physical channel. When successful, assign it to
566 * this virtual channel, and initiate the next descriptor. The
567 * virtual channel lock must be held at this point.
569 static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan)
571 struct pl08x_driver_data *pl08x = plchan->host;
572 struct pl08x_phy_chan *ch;
574 ch = pl08x_get_phy_channel(pl08x, plchan);
576 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
577 plchan->state = PL08X_CHAN_WAITING;
581 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n",
582 ch->id, plchan->name);
584 plchan->phychan = ch;
585 plchan->state = PL08X_CHAN_RUNNING;
586 pl08x_start_next_txd(plchan);
589 static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch,
590 struct pl08x_dma_chan *plchan)
592 struct pl08x_driver_data *pl08x = plchan->host;
594 dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n",
595 ch->id, plchan->name);
598 * We do this without taking the lock; we're really only concerned
599 * about whether this pointer is NULL or not, and we're guaranteed
600 * that this will only be called when it _already_ is non-NULL.
602 ch->serving = plchan;
603 plchan->phychan = ch;
604 plchan->state = PL08X_CHAN_RUNNING;
605 pl08x_start_next_txd(plchan);
609 * Free a physical DMA channel, potentially reallocating it to another
610 * virtual channel if we have any pending.
612 static void pl08x_phy_free(struct pl08x_dma_chan *plchan)
614 struct pl08x_driver_data *pl08x = plchan->host;
615 struct pl08x_dma_chan *p, *next;
620 /* Find a waiting virtual channel for the next transfer. */
621 list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node)
622 if (p->state == PL08X_CHAN_WAITING) {
628 list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node)
629 if (p->state == PL08X_CHAN_WAITING) {
635 /* Ensure that the physical channel is stopped */
636 pl08x_terminate_phy_chan(pl08x, plchan->phychan);
642 * Eww. We know this isn't going to deadlock
643 * but lockdep probably doesn't.
645 spin_lock(&next->vc.lock);
646 /* Re-check the state now that we have the lock */
647 success = next->state == PL08X_CHAN_WAITING;
649 pl08x_phy_reassign_start(plchan->phychan, next);
650 spin_unlock(&next->vc.lock);
652 /* If the state changed, try to find another channel */
656 /* No more jobs, so free up the physical channel */
657 pl08x_put_phy_channel(pl08x, plchan->phychan);
660 plchan->phychan = NULL;
661 plchan->state = PL08X_CHAN_IDLE;
668 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
671 case PL080_WIDTH_8BIT:
673 case PL080_WIDTH_16BIT:
675 case PL080_WIDTH_32BIT:
684 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
689 /* Remove all src, dst and transfer size bits */
690 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
691 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
692 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
694 /* Then set the bits according to the parameters */
697 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
700 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
703 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
712 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
715 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
718 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
725 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
729 struct pl08x_lli_build_data {
730 struct pl08x_txd *txd;
731 struct pl08x_bus_data srcbus;
732 struct pl08x_bus_data dstbus;
738 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
739 * victim in case src & dest are not similarly aligned. i.e. If after aligning
740 * masters address with width requirements of transfer (by sending few byte by
741 * byte data), slave is still not aligned, then its width will be reduced to
743 * - prefers the destination bus if both available
744 * - prefers bus with fixed address (i.e. peripheral)
746 static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
747 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
749 if (!(cctl & PL080_CONTROL_DST_INCR)) {
752 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
756 if (bd->dstbus.buswidth >= bd->srcbus.buswidth) {
767 * Fills in one LLI for a certain transfer descriptor and advance the counter
769 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
770 int num_llis, int len, u32 cctl)
772 struct pl08x_lli *llis_va = bd->txd->llis_va;
773 dma_addr_t llis_bus = bd->txd->llis_bus;
775 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
777 llis_va[num_llis].cctl = cctl;
778 llis_va[num_llis].src = bd->srcbus.addr;
779 llis_va[num_llis].dst = bd->dstbus.addr;
780 llis_va[num_llis].lli = llis_bus + (num_llis + 1) *
781 sizeof(struct pl08x_lli);
782 llis_va[num_llis].lli |= bd->lli_bus;
784 if (cctl & PL080_CONTROL_SRC_INCR)
785 bd->srcbus.addr += len;
786 if (cctl & PL080_CONTROL_DST_INCR)
787 bd->dstbus.addr += len;
789 BUG_ON(bd->remainder < len);
791 bd->remainder -= len;
794 static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd,
795 u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
797 *cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
798 pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl);
799 (*total_bytes) += len;
803 * This fills in the table of LLIs for the transfer descriptor
804 * Note that we assume we never have to change the burst sizes
807 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
808 struct pl08x_txd *txd)
810 struct pl08x_bus_data *mbus, *sbus;
811 struct pl08x_lli_build_data bd;
813 u32 cctl, early_bytes = 0;
814 size_t max_bytes_per_lli, total_bytes;
815 struct pl08x_lli *llis_va;
816 struct pl08x_sg *dsg;
818 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
820 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
827 bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
830 /* Find maximum width of the source bus */
832 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
833 PL080_CONTROL_SWIDTH_SHIFT);
835 /* Find maximum width of the destination bus */
837 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
838 PL080_CONTROL_DWIDTH_SHIFT);
840 list_for_each_entry(dsg, &txd->dsg_list, node) {
844 bd.srcbus.addr = dsg->src_addr;
845 bd.dstbus.addr = dsg->dst_addr;
846 bd.remainder = dsg->len;
847 bd.srcbus.buswidth = bd.srcbus.maxwidth;
848 bd.dstbus.buswidth = bd.dstbus.maxwidth;
850 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
852 dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
853 bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
855 bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "",
858 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
859 mbus == &bd.srcbus ? "src" : "dst",
860 sbus == &bd.srcbus ? "src" : "dst");
863 * Zero length is only allowed if all these requirements are
865 * - flow controller is peripheral.
866 * - src.addr is aligned to src.width
867 * - dst.addr is aligned to dst.width
869 * sg_len == 1 should be true, as there can be two cases here:
871 * - Memory addresses are contiguous and are not scattered.
872 * Here, Only one sg will be passed by user driver, with
873 * memory address and zero length. We pass this to controller
874 * and after the transfer it will receive the last burst
875 * request from peripheral and so transfer finishes.
877 * - Memory addresses are scattered and are not contiguous.
878 * Here, Obviously as DMA controller doesn't know when a lli's
879 * transfer gets over, it can't load next lli. So in this
880 * case, there has to be an assumption that only one lli is
881 * supported. Thus, we can't have scattered addresses.
884 u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >>
885 PL080_CONFIG_FLOW_CONTROL_SHIFT;
886 if (!((fc >= PL080_FLOW_SRC2DST_DST) &&
887 (fc <= PL080_FLOW_SRC2DST_SRC))) {
888 dev_err(&pl08x->adev->dev, "%s sg len can't be zero",
893 if ((bd.srcbus.addr % bd.srcbus.buswidth) ||
894 (bd.dstbus.addr % bd.dstbus.buswidth)) {
895 dev_err(&pl08x->adev->dev,
896 "%s src & dst address must be aligned to src"
897 " & dst width if peripheral is flow controller",
902 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
903 bd.dstbus.buswidth, 0);
904 pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl);
909 * Send byte by byte for following cases
910 * - Less than a bus width available
911 * - until master bus is aligned
913 if (bd.remainder < mbus->buswidth)
914 early_bytes = bd.remainder;
915 else if ((mbus->addr) % (mbus->buswidth)) {
916 early_bytes = mbus->buswidth - (mbus->addr) %
918 if ((bd.remainder - early_bytes) < mbus->buswidth)
919 early_bytes = bd.remainder;
923 dev_vdbg(&pl08x->adev->dev,
924 "%s byte width LLIs (remain 0x%08x)\n",
925 __func__, bd.remainder);
926 prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++,
933 * - if slave is not then we must set its width down
935 if (sbus->addr % sbus->buswidth) {
936 dev_dbg(&pl08x->adev->dev,
937 "%s set down bus width to one byte\n",
944 * Bytes transferred = tsize * src width, not
947 max_bytes_per_lli = bd.srcbus.buswidth *
948 PL080_CONTROL_TRANSFER_SIZE_MASK;
949 dev_vdbg(&pl08x->adev->dev,
950 "%s max bytes per lli = %zu\n",
951 __func__, max_bytes_per_lli);
954 * Make largest possible LLIs until less than one bus
957 while (bd.remainder > (mbus->buswidth - 1)) {
958 size_t lli_len, tsize, width;
961 * If enough left try to send max possible,
962 * otherwise try to send the remainder
964 lli_len = min(bd.remainder, max_bytes_per_lli);
967 * Check against maximum bus alignment:
968 * Calculate actual transfer size in relation to
969 * bus width an get a maximum remainder of the
970 * highest bus width - 1
972 width = max(mbus->buswidth, sbus->buswidth);
973 lli_len = (lli_len / width) * width;
974 tsize = lli_len / bd.srcbus.buswidth;
976 dev_vdbg(&pl08x->adev->dev,
977 "%s fill lli with single lli chunk of "
978 "size 0x%08zx (remainder 0x%08zx)\n",
979 __func__, lli_len, bd.remainder);
981 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
982 bd.dstbus.buswidth, tsize);
983 pl08x_fill_lli_for_desc(&bd, num_llis++,
985 total_bytes += lli_len;
992 dev_vdbg(&pl08x->adev->dev,
993 "%s align with boundary, send odd bytes (remain %zu)\n",
994 __func__, bd.remainder);
995 prep_byte_width_lli(&bd, &cctl, bd.remainder,
996 num_llis++, &total_bytes);
1000 if (total_bytes != dsg->len) {
1001 dev_err(&pl08x->adev->dev,
1002 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
1003 __func__, total_bytes, dsg->len);
1007 if (num_llis >= MAX_NUM_TSFR_LLIS) {
1008 dev_err(&pl08x->adev->dev,
1009 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
1010 __func__, (u32) MAX_NUM_TSFR_LLIS);
1015 llis_va = txd->llis_va;
1016 /* The final LLI terminates the LLI. */
1017 llis_va[num_llis - 1].lli = 0;
1018 /* The final LLI element shall also fire an interrupt. */
1019 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
1021 #ifdef VERBOSE_DEBUG
1025 dev_vdbg(&pl08x->adev->dev,
1026 "%-3s %-9s %-10s %-10s %-10s %s\n",
1027 "lli", "", "csrc", "cdst", "clli", "cctl");
1028 for (i = 0; i < num_llis; i++) {
1029 dev_vdbg(&pl08x->adev->dev,
1030 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1031 i, &llis_va[i], llis_va[i].src,
1032 llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl
1041 /* You should call this with the struct pl08x lock held */
1042 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
1043 struct pl08x_txd *txd)
1045 struct pl08x_sg *dsg, *_dsg;
1049 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
1053 list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) {
1054 list_del(&dsg->node);
1061 static void pl08x_unmap_buffers(struct pl08x_txd *txd)
1063 struct device *dev = txd->vd.tx.chan->device->dev;
1064 struct pl08x_sg *dsg;
1066 if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1067 if (txd->vd.tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1068 list_for_each_entry(dsg, &txd->dsg_list, node)
1069 dma_unmap_single(dev, dsg->src_addr, dsg->len,
1072 list_for_each_entry(dsg, &txd->dsg_list, node)
1073 dma_unmap_page(dev, dsg->src_addr, dsg->len,
1077 if (!(txd->vd.tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1078 if (txd->vd.tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1079 list_for_each_entry(dsg, &txd->dsg_list, node)
1080 dma_unmap_single(dev, dsg->dst_addr, dsg->len,
1083 list_for_each_entry(dsg, &txd->dsg_list, node)
1084 dma_unmap_page(dev, dsg->dst_addr, dsg->len,
1089 static void pl08x_desc_free(struct virt_dma_desc *vd)
1091 struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
1092 struct pl08x_dma_chan *plchan = to_pl08x_chan(vd->tx.chan);
1093 struct pl08x_driver_data *pl08x = plchan->host;
1094 unsigned long flags;
1097 pl08x_unmap_buffers(txd);
1100 pl08x_release_mux(plchan);
1102 spin_lock_irqsave(&pl08x->lock, flags);
1103 pl08x_free_txd(plchan->host, txd);
1104 spin_unlock_irqrestore(&pl08x->lock, flags);
1107 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
1108 struct pl08x_dma_chan *plchan)
1111 struct pl08x_txd *txd;
1113 vchan_get_all_descriptors(&plchan->vc, &head);
1115 while (!list_empty(&head)) {
1116 txd = list_first_entry(&head, struct pl08x_txd, vd.node);
1117 list_del(&txd->vd.node);
1118 pl08x_desc_free(&txd->vd);
1123 * The DMA ENGINE API
1125 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
1130 static void pl08x_free_chan_resources(struct dma_chan *chan)
1134 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1135 struct dma_chan *chan, unsigned long flags)
1137 struct dma_async_tx_descriptor *retval = NULL;
1143 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1144 * If slaves are relying on interrupts to signal completion this function
1145 * must not be called with interrupts disabled.
1147 static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
1148 dma_cookie_t cookie, struct dma_tx_state *txstate)
1150 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1151 struct virt_dma_desc *vd;
1152 unsigned long flags;
1153 enum dma_status ret;
1156 ret = dma_cookie_status(chan, cookie, txstate);
1157 if (ret == DMA_SUCCESS)
1161 * There's no point calculating the residue if there's
1162 * no txstate to store the value.
1165 if (plchan->state == PL08X_CHAN_PAUSED)
1170 spin_lock_irqsave(&plchan->vc.lock, flags);
1171 ret = dma_cookie_status(chan, cookie, txstate);
1172 if (ret != DMA_SUCCESS) {
1173 vd = vchan_find_desc(&plchan->vc, cookie);
1175 /* On the issued list, so hasn't been processed yet */
1176 struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
1177 struct pl08x_sg *dsg;
1179 list_for_each_entry(dsg, &txd->dsg_list, node)
1182 bytes = pl08x_getbytes_chan(plchan);
1185 spin_unlock_irqrestore(&plchan->vc.lock, flags);
1188 * This cookie not complete yet
1189 * Get number of bytes left in the active transactions and queue
1191 dma_set_residue(txstate, bytes);
1193 if (plchan->state == PL08X_CHAN_PAUSED && ret == DMA_IN_PROGRESS)
1196 /* Whether waiting or running, we're in progress */
1200 /* PrimeCell DMA extension */
1201 struct burst_table {
1206 static const struct burst_table burst_sizes[] = {
1209 .reg = PL080_BSIZE_256,
1213 .reg = PL080_BSIZE_128,
1217 .reg = PL080_BSIZE_64,
1221 .reg = PL080_BSIZE_32,
1225 .reg = PL080_BSIZE_16,
1229 .reg = PL080_BSIZE_8,
1233 .reg = PL080_BSIZE_4,
1237 .reg = PL080_BSIZE_1,
1242 * Given the source and destination available bus masks, select which
1243 * will be routed to each port. We try to have source and destination
1244 * on separate ports, but always respect the allowable settings.
1246 static u32 pl08x_select_bus(u8 src, u8 dst)
1250 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1251 cctl |= PL080_CONTROL_DST_AHB2;
1252 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1253 cctl |= PL080_CONTROL_SRC_AHB2;
1258 static u32 pl08x_cctl(u32 cctl)
1260 cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1261 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1262 PL080_CONTROL_PROT_MASK);
1264 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1265 return cctl | PL080_CONTROL_PROT_SYS;
1268 static u32 pl08x_width(enum dma_slave_buswidth width)
1271 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1272 return PL080_WIDTH_8BIT;
1273 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1274 return PL080_WIDTH_16BIT;
1275 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1276 return PL080_WIDTH_32BIT;
1282 static u32 pl08x_burst(u32 maxburst)
1286 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1287 if (burst_sizes[i].burstwords <= maxburst)
1290 return burst_sizes[i].reg;
1293 static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan,
1294 enum dma_slave_buswidth addr_width, u32 maxburst)
1296 u32 width, burst, cctl = 0;
1298 width = pl08x_width(addr_width);
1302 cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
1303 cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
1306 * If this channel will only request single transfers, set this
1307 * down to ONE element. Also select one element if no maxburst
1310 if (plchan->cd->single)
1313 burst = pl08x_burst(maxburst);
1314 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1315 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1317 return pl08x_cctl(cctl);
1320 static int dma_set_runtime_config(struct dma_chan *chan,
1321 struct dma_slave_config *config)
1323 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1328 /* Reject definitely invalid configurations */
1329 if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
1330 config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
1333 plchan->cfg = *config;
1339 * Slave transactions callback to the slave device to allow
1340 * synchronization of slave DMA signals with the DMAC enable
1342 static void pl08x_issue_pending(struct dma_chan *chan)
1344 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1345 unsigned long flags;
1347 spin_lock_irqsave(&plchan->vc.lock, flags);
1348 if (vchan_issue_pending(&plchan->vc)) {
1349 if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING)
1350 pl08x_phy_alloc_and_start(plchan);
1352 spin_unlock_irqrestore(&plchan->vc.lock, flags);
1355 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1356 struct pl08x_txd *txd)
1358 struct pl08x_driver_data *pl08x = plchan->host;
1361 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1363 unsigned long flags;
1365 spin_lock_irqsave(&plchan->vc.lock, flags);
1366 pl08x_free_txd(pl08x, txd);
1367 spin_unlock_irqrestore(&plchan->vc.lock, flags);
1374 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
1376 struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
1379 INIT_LIST_HEAD(&txd->dsg_list);
1381 /* Always enable error and terminal interrupts */
1382 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1383 PL080_CONFIG_TC_IRQ_MASK;
1389 * Initialize a descriptor to be used by memcpy submit
1391 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1392 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1393 size_t len, unsigned long flags)
1395 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1396 struct pl08x_driver_data *pl08x = plchan->host;
1397 struct pl08x_txd *txd;
1398 struct pl08x_sg *dsg;
1401 txd = pl08x_get_txd(plchan);
1403 dev_err(&pl08x->adev->dev,
1404 "%s no memory for descriptor\n", __func__);
1408 dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
1410 pl08x_free_txd(pl08x, txd);
1411 dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n",
1415 list_add_tail(&dsg->node, &txd->dsg_list);
1417 dsg->src_addr = src;
1418 dsg->dst_addr = dest;
1421 /* Set platform data for m2m */
1422 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1423 txd->cctl = pl08x->pd->memcpy_channel.cctl_memcpy &
1424 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1426 /* Both to be incremented or the code will break */
1427 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1429 if (pl08x->vd->dualmaster)
1430 txd->cctl |= pl08x_select_bus(pl08x->mem_buses,
1433 ret = pl08x_prep_channel_resources(plchan, txd);
1437 return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
1440 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1441 struct dma_chan *chan, struct scatterlist *sgl,
1442 unsigned int sg_len, enum dma_transfer_direction direction,
1443 unsigned long flags, void *context)
1445 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1446 struct pl08x_driver_data *pl08x = plchan->host;
1447 struct pl08x_txd *txd;
1448 struct pl08x_sg *dsg;
1449 struct scatterlist *sg;
1450 enum dma_slave_buswidth addr_width;
1451 dma_addr_t slave_addr;
1453 u8 src_buses, dst_buses;
1456 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1457 __func__, sg_dma_len(sgl), plchan->name);
1459 txd = pl08x_get_txd(plchan);
1461 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1466 * Set up addresses, the PrimeCell configured address
1467 * will take precedence since this may configure the
1468 * channel target address dynamically at runtime.
1470 if (direction == DMA_MEM_TO_DEV) {
1471 cctl = PL080_CONTROL_SRC_INCR;
1472 slave_addr = plchan->cfg.dst_addr;
1473 addr_width = plchan->cfg.dst_addr_width;
1474 maxburst = plchan->cfg.dst_maxburst;
1475 src_buses = pl08x->mem_buses;
1476 dst_buses = plchan->cd->periph_buses;
1477 } else if (direction == DMA_DEV_TO_MEM) {
1478 cctl = PL080_CONTROL_DST_INCR;
1479 slave_addr = plchan->cfg.src_addr;
1480 addr_width = plchan->cfg.src_addr_width;
1481 maxburst = plchan->cfg.src_maxburst;
1482 src_buses = plchan->cd->periph_buses;
1483 dst_buses = pl08x->mem_buses;
1485 pl08x_free_txd(pl08x, txd);
1486 dev_err(&pl08x->adev->dev,
1487 "%s direction unsupported\n", __func__);
1491 cctl |= pl08x_get_cctl(plchan, addr_width, maxburst);
1493 pl08x_free_txd(pl08x, txd);
1494 dev_err(&pl08x->adev->dev,
1495 "DMA slave configuration botched?\n");
1499 txd->cctl = cctl | pl08x_select_bus(src_buses, dst_buses);
1501 if (plchan->cfg.device_fc)
1502 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
1503 PL080_FLOW_PER2MEM_PER;
1505 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER :
1508 txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1510 ret = pl08x_request_mux(plchan);
1512 pl08x_free_txd(pl08x, txd);
1513 dev_dbg(&pl08x->adev->dev,
1514 "unable to mux for transfer on %s due to platform restrictions\n",
1519 dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n",
1520 plchan->signal, plchan->name);
1522 /* Assign the flow control signal to this channel */
1523 if (direction == DMA_MEM_TO_DEV)
1524 txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT;
1526 txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT;
1528 for_each_sg(sgl, sg, sg_len, tmp) {
1529 dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
1531 pl08x_release_mux(plchan);
1532 pl08x_free_txd(pl08x, txd);
1533 dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
1537 list_add_tail(&dsg->node, &txd->dsg_list);
1539 dsg->len = sg_dma_len(sg);
1540 if (direction == DMA_MEM_TO_DEV) {
1541 dsg->src_addr = sg_dma_address(sg);
1542 dsg->dst_addr = slave_addr;
1544 dsg->src_addr = slave_addr;
1545 dsg->dst_addr = sg_dma_address(sg);
1549 ret = pl08x_prep_channel_resources(plchan, txd);
1553 return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
1556 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1559 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1560 struct pl08x_driver_data *pl08x = plchan->host;
1561 unsigned long flags;
1564 /* Controls applicable to inactive channels */
1565 if (cmd == DMA_SLAVE_CONFIG) {
1566 return dma_set_runtime_config(chan,
1567 (struct dma_slave_config *)arg);
1571 * Anything succeeds on channels with no physical allocation and
1572 * no queued transfers.
1574 spin_lock_irqsave(&plchan->vc.lock, flags);
1575 if (!plchan->phychan && !plchan->at) {
1576 spin_unlock_irqrestore(&plchan->vc.lock, flags);
1581 case DMA_TERMINATE_ALL:
1582 plchan->state = PL08X_CHAN_IDLE;
1584 if (plchan->phychan) {
1586 * Mark physical channel as free and free any slave
1589 pl08x_phy_free(plchan);
1591 /* Dequeue jobs and free LLIs */
1593 pl08x_desc_free(&plchan->at->vd);
1596 /* Dequeue jobs not yet fired as well */
1597 pl08x_free_txd_list(pl08x, plchan);
1600 pl08x_pause_phy_chan(plchan->phychan);
1601 plchan->state = PL08X_CHAN_PAUSED;
1604 pl08x_resume_phy_chan(plchan->phychan);
1605 plchan->state = PL08X_CHAN_RUNNING;
1608 /* Unknown command */
1613 spin_unlock_irqrestore(&plchan->vc.lock, flags);
1618 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1620 struct pl08x_dma_chan *plchan;
1621 char *name = chan_id;
1623 /* Reject channels for devices not bound to this driver */
1624 if (chan->device->dev->driver != &pl08x_amba_driver.drv)
1627 plchan = to_pl08x_chan(chan);
1629 /* Check that the channel is not taken! */
1630 if (!strcmp(plchan->name, name))
1637 * Just check that the device is there and active
1638 * TODO: turn this bit on/off depending on the number of physical channels
1639 * actually used, if it is zero... well shut it off. That will save some
1640 * power. Cut the clock at the same time.
1642 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1644 /* The Nomadik variant does not have the config register */
1645 if (pl08x->vd->nomadik)
1647 writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
1650 static irqreturn_t pl08x_irq(int irq, void *dev)
1652 struct pl08x_driver_data *pl08x = dev;
1653 u32 mask = 0, err, tc, i;
1655 /* check & clear - ERR & TC interrupts */
1656 err = readl(pl08x->base + PL080_ERR_STATUS);
1658 dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n",
1660 writel(err, pl08x->base + PL080_ERR_CLEAR);
1662 tc = readl(pl08x->base + PL080_TC_STATUS);
1664 writel(tc, pl08x->base + PL080_TC_CLEAR);
1669 for (i = 0; i < pl08x->vd->channels; i++) {
1670 if (((1 << i) & err) || ((1 << i) & tc)) {
1671 /* Locate physical channel */
1672 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1673 struct pl08x_dma_chan *plchan = phychan->serving;
1674 struct pl08x_txd *tx;
1677 dev_err(&pl08x->adev->dev,
1678 "%s Error TC interrupt on unused channel: 0x%08x\n",
1683 spin_lock(&plchan->vc.lock);
1688 * This descriptor is done, release its mux
1691 pl08x_release_mux(plchan);
1693 vchan_cookie_complete(&tx->vd);
1696 * And start the next descriptor (if any),
1697 * otherwise free this channel.
1699 if (vchan_next_desc(&plchan->vc))
1700 pl08x_start_next_txd(plchan);
1702 pl08x_phy_free(plchan);
1704 spin_unlock(&plchan->vc.lock);
1710 return mask ? IRQ_HANDLED : IRQ_NONE;
1713 static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
1716 chan->name = chan->cd->bus_id;
1717 chan->cfg.src_addr = chan->cd->addr;
1718 chan->cfg.dst_addr = chan->cd->addr;
1722 * Initialise the DMAC memcpy/slave channels.
1723 * Make a local wrapper to hold required data
1725 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1726 struct dma_device *dmadev, unsigned int channels, bool slave)
1728 struct pl08x_dma_chan *chan;
1731 INIT_LIST_HEAD(&dmadev->channels);
1734 * Register as many many memcpy as we have physical channels,
1735 * we won't always be able to use all but the code will have
1736 * to cope with that situation.
1738 for (i = 0; i < channels; i++) {
1739 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1741 dev_err(&pl08x->adev->dev,
1742 "%s no memory for channel\n", __func__);
1747 chan->state = PL08X_CHAN_IDLE;
1751 chan->cd = &pl08x->pd->slave_channels[i];
1752 pl08x_dma_slave_init(chan);
1754 chan->cd = &pl08x->pd->memcpy_channel;
1755 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1761 dev_dbg(&pl08x->adev->dev,
1762 "initialize virtual channel \"%s\"\n",
1765 chan->vc.desc_free = pl08x_desc_free;
1766 vchan_init(&chan->vc, dmadev);
1768 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1769 i, slave ? "slave" : "memcpy");
1773 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1775 struct pl08x_dma_chan *chan = NULL;
1776 struct pl08x_dma_chan *next;
1778 list_for_each_entry_safe(chan,
1779 next, &dmadev->channels, vc.chan.device_node) {
1780 list_del(&chan->vc.chan.device_node);
1785 #ifdef CONFIG_DEBUG_FS
1786 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1789 case PL08X_CHAN_IDLE:
1791 case PL08X_CHAN_RUNNING:
1793 case PL08X_CHAN_PAUSED:
1795 case PL08X_CHAN_WAITING:
1800 return "UNKNOWN STATE";
1803 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1805 struct pl08x_driver_data *pl08x = s->private;
1806 struct pl08x_dma_chan *chan;
1807 struct pl08x_phy_chan *ch;
1808 unsigned long flags;
1811 seq_printf(s, "PL08x physical channels:\n");
1812 seq_printf(s, "CHANNEL:\tUSER:\n");
1813 seq_printf(s, "--------\t-----\n");
1814 for (i = 0; i < pl08x->vd->channels; i++) {
1815 struct pl08x_dma_chan *virt_chan;
1817 ch = &pl08x->phy_chans[i];
1819 spin_lock_irqsave(&ch->lock, flags);
1820 virt_chan = ch->serving;
1822 seq_printf(s, "%d\t\t%s%s\n",
1824 virt_chan ? virt_chan->name : "(none)",
1825 ch->locked ? " LOCKED" : "");
1827 spin_unlock_irqrestore(&ch->lock, flags);
1830 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1831 seq_printf(s, "CHANNEL:\tSTATE:\n");
1832 seq_printf(s, "--------\t------\n");
1833 list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) {
1834 seq_printf(s, "%s\t\t%s\n", chan->name,
1835 pl08x_state_str(chan->state));
1838 seq_printf(s, "\nPL08x virtual slave channels:\n");
1839 seq_printf(s, "CHANNEL:\tSTATE:\n");
1840 seq_printf(s, "--------\t------\n");
1841 list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) {
1842 seq_printf(s, "%s\t\t%s\n", chan->name,
1843 pl08x_state_str(chan->state));
1849 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1851 return single_open(file, pl08x_debugfs_show, inode->i_private);
1854 static const struct file_operations pl08x_debugfs_operations = {
1855 .open = pl08x_debugfs_open,
1857 .llseek = seq_lseek,
1858 .release = single_release,
1861 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1863 /* Expose a simple debugfs interface to view all clocks */
1864 (void) debugfs_create_file(dev_name(&pl08x->adev->dev),
1865 S_IFREG | S_IRUGO, NULL, pl08x,
1866 &pl08x_debugfs_operations);
1870 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1875 static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
1877 struct pl08x_driver_data *pl08x;
1878 const struct vendor_data *vd = id->data;
1882 ret = amba_request_regions(adev, NULL);
1886 /* Create the driver state holder */
1887 pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL);
1893 /* Initialize memcpy engine */
1894 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1895 pl08x->memcpy.dev = &adev->dev;
1896 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1897 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1898 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1899 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1900 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1901 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1902 pl08x->memcpy.device_control = pl08x_control;
1904 /* Initialize slave engine */
1905 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1906 pl08x->slave.dev = &adev->dev;
1907 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1908 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1909 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1910 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1911 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1912 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1913 pl08x->slave.device_control = pl08x_control;
1915 /* Get the platform data */
1916 pl08x->pd = dev_get_platdata(&adev->dev);
1918 dev_err(&adev->dev, "no platform data supplied\n");
1919 goto out_no_platdata;
1922 /* Assign useful pointers to the driver state */
1926 /* By default, AHB1 only. If dualmaster, from platform */
1927 pl08x->lli_buses = PL08X_AHB1;
1928 pl08x->mem_buses = PL08X_AHB1;
1929 if (pl08x->vd->dualmaster) {
1930 pl08x->lli_buses = pl08x->pd->lli_buses;
1931 pl08x->mem_buses = pl08x->pd->mem_buses;
1934 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1935 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1936 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1939 goto out_no_lli_pool;
1942 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1945 goto out_no_ioremap;
1948 /* Turn on the PL08x */
1949 pl08x_ensure_on(pl08x);
1951 /* Attach the interrupt handler */
1952 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1953 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1955 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1956 DRIVER_NAME, pl08x);
1958 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1959 __func__, adev->irq[0]);
1963 /* Initialize physical channels */
1964 pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)),
1966 if (!pl08x->phy_chans) {
1967 dev_err(&adev->dev, "%s failed to allocate "
1968 "physical channel holders\n",
1970 goto out_no_phychans;
1973 for (i = 0; i < vd->channels; i++) {
1974 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1977 ch->base = pl08x->base + PL080_Cx_BASE(i);
1978 spin_lock_init(&ch->lock);
1981 * Nomadik variants can have channels that are locked
1982 * down for the secure world only. Lock up these channels
1983 * by perpetually serving a dummy virtual channel.
1988 val = readl(ch->base + PL080_CH_CONFIG);
1989 if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {
1990 dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i);
1995 dev_dbg(&adev->dev, "physical channel %d is %s\n",
1996 i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1999 /* Register as many memcpy channels as there are physical channels */
2000 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
2001 pl08x->vd->channels, false);
2003 dev_warn(&pl08x->adev->dev,
2004 "%s failed to enumerate memcpy channels - %d\n",
2008 pl08x->memcpy.chancnt = ret;
2010 /* Register slave channels */
2011 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
2012 pl08x->pd->num_slave_channels, true);
2014 dev_warn(&pl08x->adev->dev,
2015 "%s failed to enumerate slave channels - %d\n",
2019 pl08x->slave.chancnt = ret;
2021 ret = dma_async_device_register(&pl08x->memcpy);
2023 dev_warn(&pl08x->adev->dev,
2024 "%s failed to register memcpy as an async device - %d\n",
2026 goto out_no_memcpy_reg;
2029 ret = dma_async_device_register(&pl08x->slave);
2031 dev_warn(&pl08x->adev->dev,
2032 "%s failed to register slave as an async device - %d\n",
2034 goto out_no_slave_reg;
2037 amba_set_drvdata(adev, pl08x);
2038 init_pl08x_debugfs(pl08x);
2039 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2040 amba_part(adev), amba_rev(adev),
2041 (unsigned long long)adev->res.start, adev->irq[0]);
2046 dma_async_device_unregister(&pl08x->memcpy);
2048 pl08x_free_virtual_channels(&pl08x->slave);
2050 pl08x_free_virtual_channels(&pl08x->memcpy);
2052 kfree(pl08x->phy_chans);
2054 free_irq(adev->irq[0], pl08x);
2056 iounmap(pl08x->base);
2058 dma_pool_destroy(pl08x->pool);
2063 amba_release_regions(adev);
2067 /* PL080 has 8 channels and the PL080 have just 2 */
2068 static struct vendor_data vendor_pl080 = {
2073 static struct vendor_data vendor_nomadik = {
2079 static struct vendor_data vendor_pl081 = {
2081 .dualmaster = false,
2084 static struct amba_id pl08x_ids[] = {
2089 .data = &vendor_pl080,
2095 .data = &vendor_pl081,
2097 /* Nomadik 8815 PL080 variant */
2101 .data = &vendor_nomadik,
2106 MODULE_DEVICE_TABLE(amba, pl08x_ids);
2108 static struct amba_driver pl08x_amba_driver = {
2109 .drv.name = DRIVER_NAME,
2110 .id_table = pl08x_ids,
2111 .probe = pl08x_probe,
2114 static int __init pl08x_init(void)
2117 retval = amba_driver_register(&pl08x_amba_driver);
2119 printk(KERN_WARNING DRIVER_NAME
2120 "failed to register as an AMBA device (%d)\n",
2124 subsys_initcall(pl08x_init);