drivers/char/agp/uninorth-agp.c

   1 /*
   2  * UniNorth AGPGART routines.
   3  */
   4 #include <linux/module.h>
   5 #include <linux/pci.h>
   6 #include <linux/init.h>
   7 #include <linux/pagemap.h>
   8 #include <linux/agp_backend.h>
   9 #include <linux/delay.h>
  10 #include <asm/uninorth.h>
  11 #include <asm/pci-bridge.h>
  12 #include <asm/prom.h>
  13 #include <asm/pmac_feature.h>
  14 #include "agp.h"
  15
  16 /*
  17  * NOTES for uninorth3 (G5 AGP) supports :
  18  *
  19  * There maybe also possibility to have bigger cache line size for
  20  * agp (see pmac_pci.c and look for cache line). Need to be investigated
  21  * by someone.
  22  *
  23  * PAGE size are hardcoded but this may change, see asm/page.h.
  24  *
  25  * Jerome Glisse <j.glisse@gmail.com>
  26  */
  27 static int uninorth_rev;
  28 static int is_u3;
  29
  30 #define DEFAULT_APERTURE_SIZE 256
  31 #define DEFAULT_APERTURE_STRING "256"
  32 static char *aperture = NULL;
  33
  34 static int uninorth_fetch_size(void)
  35 {
  36         int i, size = 0;
  37         struct aper_size_info_32 *values =
  38             A_SIZE_32(agp_bridge->driver->aperture_sizes);
  39
  40         if (aperture) {
  41                 char *save = aperture;
  42
  43                 size = memparse(aperture, &aperture) >> 20;
  44                 aperture = save;
  45
  46                 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++)
  47                         if (size == values[i].size)
  48                                 break;
  49
  50                 if (i == agp_bridge->driver->num_aperture_sizes) {
  51                         dev_err(&agp_bridge->dev->dev, "invalid aperture size, "
  52                                 "using default\n");
  53                         size = 0;
  54                         aperture = NULL;
  55                 }
  56         }
  57
  58         if (!size) {
  59                 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++)
  60                         if (values[i].size == DEFAULT_APERTURE_SIZE)
  61                                 break;
  62         }
  63
  64         agp_bridge->previous_size =
  65             agp_bridge->current_size = (void *)(values + i);
  66         agp_bridge->aperture_size_idx = i;
  67         return values[i].size;
  68 }
  69
  70 static void uninorth_tlbflush(struct agp_memory *mem)
  71 {
  72         u32 ctrl = UNI_N_CFG_GART_ENABLE;
  73
  74         if (is_u3)
  75                 ctrl |= U3_N_CFG_GART_PERFRD;
  76         pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
  77                                ctrl | UNI_N_CFG_GART_INVAL);
  78         pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl);
  79
  80         if (uninorth_rev <= 0x30) {
  81                 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
  82                                        ctrl | UNI_N_CFG_GART_2xRESET);
  83                 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
  84                                        ctrl);
  85         }
  86 }
  87
  88 static void uninorth_cleanup(void)
  89 {
  90         u32 tmp;
  91
  92         pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, &tmp);
  93         if (!(tmp & UNI_N_CFG_GART_ENABLE))
  94                 return;
  95         tmp |= UNI_N_CFG_GART_INVAL;
  96         pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, tmp);
  97         pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 0);
  98
  99         if (uninorth_rev <= 0x30) {
 100                 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
 101                                        UNI_N_CFG_GART_2xRESET);
 102                 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
 103                                        0);
 104         }
 105 }
 106
 107 static int uninorth_configure(void)
 108 {
 109         struct aper_size_info_32 *current_size;
 110
 111         current_size = A_SIZE_32(agp_bridge->current_size);
 112
 113         dev_info(&agp_bridge->dev->dev, "configuring for size idx: %d\n",
 114                  current_size->size_value);
 115
 116         /* aperture size and gatt addr */
 117         pci_write_config_dword(agp_bridge->dev,
 118                 UNI_N_CFG_GART_BASE,
 119                 (agp_bridge->gatt_bus_addr & 0xfffff000)
 120                         | current_size->size_value);
 121
 122         /* HACK ALERT
 123          * UniNorth seem to be buggy enough not to handle properly when
 124          * the AGP aperture isn't mapped at bus physical address 0
 125          */
 126         agp_bridge->gart_bus_addr = 0;
 127 #ifdef CONFIG_PPC64
 128         /* Assume U3 or later on PPC64 systems */
 129         /* high 4 bits of GART physical address go in UNI_N_CFG_AGP_BASE */
 130         pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE,
 131                                (agp_bridge->gatt_bus_addr >> 32) & 0xf);
 132 #else
 133         pci_write_config_dword(agp_bridge->dev,
 134                 UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr);
 135 #endif
 136
 137         if (is_u3) {
 138                 pci_write_config_dword(agp_bridge->dev,
 139                                        UNI_N_CFG_GART_DUMMY_PAGE,
 140                                        agp_bridge->scratch_page_real >> 12);
 141         }
 142
 143         return 0;
 144 }
 145
 146 static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start,
 147                                 int type)
 148 {
 149         int i, j, num_entries;
 150         void *temp;
 151         int mask_type;
 152
 153         temp = agp_bridge->current_size;
 154         num_entries = A_SIZE_32(temp)->num_entries;
 155
 156         if (type != mem->type)
 157                 return -EINVAL;
 158
 159         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 160         if (mask_type != 0) {
 161                 /* We know nothing of memory types */
 162                 return -EINVAL;
 163         }
 164
 165         if ((pg_start + mem->page_count) > num_entries)
 166                 return -EINVAL;
 167
 168         j = pg_start;
 169
 170         while (j < (pg_start + mem->page_count)) {
 171                 if (agp_bridge->gatt_table[j])
 172                         return -EBUSY;
 173                 j++;
 174         }
 175
 176         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 177                 agp_bridge->gatt_table[j] =
 178                         cpu_to_le32((page_to_phys(mem->pages[i]) & 0xFFFFF000UL) | 0x1UL);
 179                 flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])),
 180                                    (unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000);
 181         }
 182         (void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]);
 183         mb();
 184         flush_dcache_range((unsigned long)&agp_bridge->gatt_table[pg_start],
 185                 (unsigned long)&agp_bridge->gatt_table[pg_start + mem->page_count]);
 186
 187         uninorth_tlbflush(mem);
 188         return 0;
 189 }
 190
 191 static int u3_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
 192 {
 193         int i, num_entries;
 194         void *temp;
 195         u32 *gp;
 196         int mask_type;
 197
 198         temp = agp_bridge->current_size;
 199         num_entries = A_SIZE_32(temp)->num_entries;
 200
 201         if (type != mem->type)
 202                 return -EINVAL;
 203
 204         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 205         if (mask_type != 0) {
 206                 /* We know nothing of memory types */
 207                 return -EINVAL;
 208         }
 209
 210         if ((pg_start + mem->page_count) > num_entries)
 211                 return -EINVAL;
 212
 213         gp = (u32 *) &agp_bridge->gatt_table[pg_start];
 214         for (i = 0; i < mem->page_count; ++i) {
 215                 if (gp[i]) {
 216                         dev_info(&agp_bridge->dev->dev,
 217                                  "u3_insert_memory: entry 0x%x occupied (%x)\n",
 218                                  i, gp[i]);
 219                         return -EBUSY;
 220                 }
 221         }
 222
 223         for (i = 0; i < mem->page_count; i++) {
 224                 gp[i] = (page_to_phys(mem->pages[i]) >> PAGE_SHIFT) | 0x80000000UL;
 225                 flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])),
 226                                    (unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000);
 227         }
 228         mb();
 229         flush_dcache_range((unsigned long)gp, (unsigned long) &gp[i]);
 230         uninorth_tlbflush(mem);
 231
 232         return 0;
 233 }
 234
 235 int u3_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
 236 {
 237         size_t i;
 238         u32 *gp;
 239
 240         if (type != 0 || mem->type != 0)
 241                 /* We know nothing of memory types */
 242                 return -EINVAL;
 243
 244         gp = (u32 *) &agp_bridge->gatt_table[pg_start];
 245         for (i = 0; i < mem->page_count; ++i)
 246                 gp[i] = 0;
 247         mb();
 248         flush_dcache_range((unsigned long)gp, (unsigned long) &gp[i]);
 249         uninorth_tlbflush(mem);
 250
 251         return 0;
 252 }
 253
 254 static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 255 {
 256         u32 command, scratch, status;
 257         int timeout;
 258
 259         pci_read_config_dword(bridge->dev,
 260                               bridge->capndx + PCI_AGP_STATUS,
 261                               &status);
 262
 263         command = agp_collect_device_status(bridge, mode, status);
 264         command |= PCI_AGP_COMMAND_AGP;
 265
 266         if (uninorth_rev == 0x21) {
 267                 /*
 268                  * Darwin disable AGP 4x on this revision, thus we
 269                  * may assume it's broken. This is an AGP2 controller.
 270                  */
 271                 command &= ~AGPSTAT2_4X;
 272         }
 273
 274         if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) {
 275                 /*
 276                  * We need to to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1,
 277                  * 2.2 and 2.3, Darwin do so.
 278                  */
 279                 if ((command >> AGPSTAT_RQ_DEPTH_SHIFT) > 7)
 280                         command = (command & ~AGPSTAT_RQ_DEPTH)
 281                                 | (7 << AGPSTAT_RQ_DEPTH_SHIFT);
 282         }
 283
 284         uninorth_tlbflush(NULL);
 285
 286         timeout = 0;
 287         do {
 288                 pci_write_config_dword(bridge->dev,
 289                                        bridge->capndx + PCI_AGP_COMMAND,
 290                                        command);
 291                 pci_read_config_dword(bridge->dev,
 292                                       bridge->capndx + PCI_AGP_COMMAND,
 293                                        &scratch);
 294         } while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000);
 295         if ((scratch & PCI_AGP_COMMAND_AGP) == 0)
 296                 dev_err(&bridge->dev->dev, "can't write UniNorth AGP "
 297                         "command register\n");
 298
 299         if (uninorth_rev >= 0x30) {
 300                 /* This is an AGP V3 */
 301                 agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0);
 302         } else {
 303                 /* AGP V2 */
 304                 agp_device_command(command, false);
 305         }
 306
 307         uninorth_tlbflush(NULL);
 308 }
 309
 310 #ifdef CONFIG_PM
 311 /*
 312  * These Power Management routines are _not_ called by the normal PCI PM layer,
 313  * but directly by the video driver through function pointers in the device
 314  * tree.
 315  */
 316 static int agp_uninorth_suspend(struct pci_dev *pdev)
 317 {
 318         struct agp_bridge_data *bridge;
 319         u32 cmd;
 320         u8 agp;
 321         struct pci_dev *device = NULL;
 322
 323         bridge = agp_find_bridge(pdev);
 324         if (bridge == NULL)
 325                 return -ENODEV;
 326
 327         /* Only one suspend supported */
 328         if (bridge->dev_private_data)
 329                 return 0;
 330
 331         /* turn off AGP on the video chip, if it was enabled */
 332         for_each_pci_dev(device) {
 333                 /* Don't touch the bridge yet, device first */
 334                 if (device == pdev)
 335                         continue;
 336                 /* Only deal with devices on the same bus here, no Mac has a P2P
 337                  * bridge on the AGP port, and mucking around the entire PCI
 338                  * tree is source of problems on some machines because of a bug
 339                  * in some versions of pci_find_capability() when hitting a dead
 340                  * device
 341                  */
 342                 if (device->bus != pdev->bus)
 343                         continue;
 344                 agp = pci_find_capability(device, PCI_CAP_ID_AGP);
 345                 if (!agp)
 346                         continue;
 347                 pci_read_config_dword(device, agp + PCI_AGP_COMMAND, &cmd);
 348                 if (!(cmd & PCI_AGP_COMMAND_AGP))
 349                         continue;
 350                 dev_info(&pdev->dev, "disabling AGP on device %s\n",
 351                          pci_name(device));
 352                 cmd &= ~PCI_AGP_COMMAND_AGP;
 353                 pci_write_config_dword(device, agp + PCI_AGP_COMMAND, cmd);
 354         }
 355
 356         /* turn off AGP on the bridge */
 357         agp = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 358         pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd);
 359         bridge->dev_private_data = (void *)(long)cmd;
 360         if (cmd & PCI_AGP_COMMAND_AGP) {
 361                 dev_info(&pdev->dev, "disabling AGP on bridge\n");
 362                 cmd &= ~PCI_AGP_COMMAND_AGP;
 363                 pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, cmd);
 364         }
 365         /* turn off the GART */
 366         uninorth_cleanup();
 367
 368         return 0;
 369 }
 370
 371 static int agp_uninorth_resume(struct pci_dev *pdev)
 372 {
 373         struct agp_bridge_data *bridge;
 374         u32 command;
 375
 376         bridge = agp_find_bridge(pdev);
 377         if (bridge == NULL)
 378                 return -ENODEV;
 379
 380         command = (long)bridge->dev_private_data;
 381         bridge->dev_private_data = NULL;
 382         if (!(command & PCI_AGP_COMMAND_AGP))
 383                 return 0;
 384
 385         uninorth_agp_enable(bridge, command);
 386
 387         return 0;
 388 }
 389 #endif /* CONFIG_PM */
 390
 391 static int uninorth_create_gatt_table(struct agp_bridge_data *bridge)
 392 {
 393         char *table;
 394         char *table_end;
 395         int size;
 396         int page_order;
 397         int num_entries;
 398         int i;
 399         void *temp;
 400         struct page *page;
 401
 402         /* We can't handle 2 level gatt's */
 403         if (bridge->driver->size_type == LVL2_APER_SIZE)
 404                 return -EINVAL;
 405
 406         table = NULL;
 407         i = bridge->aperture_size_idx;
 408         temp = bridge->current_size;
 409         size = page_order = num_entries = 0;
 410
 411         do {
 412                 size = A_SIZE_32(temp)->size;
 413                 page_order = A_SIZE_32(temp)->page_order;
 414                 num_entries = A_SIZE_32(temp)->num_entries;
 415
 416                 table = (char *) __get_free_pages(GFP_KERNEL, page_order);
 417
 418                 if (table == NULL) {
 419                         i++;
 420                         bridge->current_size = A_IDX32(bridge);
 421                 } else {
 422                         bridge->aperture_size_idx = i;
 423                 }
 424         } while (!table && (i < bridge->driver->num_aperture_sizes));
 425
 426         if (table == NULL)
 427                 return -ENOMEM;
 428
 429         table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
 430
 431         for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
 432                 SetPageReserved(page);
 433
 434         bridge->gatt_table_real = (u32 *) table;
 435         bridge->gatt_table = (u32 *)table;
 436         bridge->gatt_bus_addr = virt_to_gart(table);
 437
 438         for (i = 0; i < num_entries; i++)
 439                 bridge->gatt_table[i] = 0;
 440
 441         flush_dcache_range((unsigned long)table, (unsigned long)table_end);
 442
 443         return 0;
 444 }
 445
 446 static int uninorth_free_gatt_table(struct agp_bridge_data *bridge)
 447 {
 448         int page_order;
 449         char *table, *table_end;
 450         void *temp;
 451         struct page *page;
 452
 453         temp = bridge->current_size;
 454         page_order = A_SIZE_32(temp)->page_order;
 455
 456         /* Do not worry about freeing memory, because if this is
 457          * called, then all agp memory is deallocated and removed
 458          * from the table.
 459          */
 460
 461         table = (char *) bridge->gatt_table_real;
 462         table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
 463
 464         for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
 465                 ClearPageReserved(page);
 466
 467         free_pages((unsigned long) bridge->gatt_table_real, page_order);
 468
 469         return 0;
 470 }
 471
 472 void null_cache_flush(void)
 473 {
 474         mb();
 475 }
 476
 477 /* Setup function */
 478
 479 static const struct aper_size_info_32 uninorth_sizes[] =
 480 {
 481         {256, 65536, 6, 64},
 482         {128, 32768, 5, 32},
 483         {64, 16384, 4, 16},
 484         {32, 8192, 3, 8},
 485         {16, 4096, 2, 4},
 486         {8, 2048, 1, 2},
 487         {4, 1024, 0, 1}
 488 };
 489
 490 /*
 491  * Not sure that u3 supports that high aperture sizes but it
 492  * would strange if it did not :)
 493  */
 494 static const struct aper_size_info_32 u3_sizes[] =
 495 {
 496         {512, 131072, 7, 128},
 497         {256, 65536, 6, 64},
 498         {128, 32768, 5, 32},
 499         {64, 16384, 4, 16},
 500         {32, 8192, 3, 8},
 501         {16, 4096, 2, 4},
 502         {8, 2048, 1, 2},
 503         {4, 1024, 0, 1}
 504 };
 505
 506 const struct agp_bridge_driver uninorth_agp_driver = {
 507         .owner                  = THIS_MODULE,
 508         .aperture_sizes         = (void *)uninorth_sizes,
 509         .size_type              = U32_APER_SIZE,
 510         .num_aperture_sizes     = ARRAY_SIZE(uninorth_sizes),
 511         .configure              = uninorth_configure,
 512         .fetch_size             = uninorth_fetch_size,
 513         .cleanup                = uninorth_cleanup,
 514         .tlb_flush              = uninorth_tlbflush,
 515         .mask_memory            = agp_generic_mask_memory,
 516         .masks                  = NULL,
 517         .cache_flush            = null_cache_flush,
 518         .agp_enable             = uninorth_agp_enable,
 519         .create_gatt_table      = uninorth_create_gatt_table,
 520         .free_gatt_table        = uninorth_free_gatt_table,
 521         .insert_memory          = uninorth_insert_memory,
 522         .remove_memory          = agp_generic_remove_memory,
 523         .alloc_by_type          = agp_generic_alloc_by_type,
 524         .free_by_type           = agp_generic_free_by_type,
 525         .agp_alloc_page         = agp_generic_alloc_page,
 526         .agp_alloc_pages        = agp_generic_alloc_pages,
 527         .agp_destroy_page       = agp_generic_destroy_page,
 528         .agp_destroy_pages      = agp_generic_destroy_pages,
 529         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
 530         .cant_use_aperture      = true,
 531 };
 532
 533 const struct agp_bridge_driver u3_agp_driver = {
 534         .owner                  = THIS_MODULE,
 535         .aperture_sizes         = (void *)u3_sizes,
 536         .size_type              = U32_APER_SIZE,
 537         .num_aperture_sizes     = ARRAY_SIZE(u3_sizes),
 538         .configure              = uninorth_configure,
 539         .fetch_size             = uninorth_fetch_size,
 540         .cleanup                = uninorth_cleanup,
 541         .tlb_flush              = uninorth_tlbflush,
 542         .mask_memory            = agp_generic_mask_memory,
 543         .masks                  = NULL,
 544         .cache_flush            = null_cache_flush,
 545         .agp_enable             = uninorth_agp_enable,
 546         .create_gatt_table      = uninorth_create_gatt_table,
 547         .free_gatt_table        = uninorth_free_gatt_table,
 548         .insert_memory          = u3_insert_memory,
 549         .remove_memory          = u3_remove_memory,
 550         .alloc_by_type          = agp_generic_alloc_by_type,
 551         .free_by_type           = agp_generic_free_by_type,
 552         .agp_alloc_page         = agp_generic_alloc_page,
 553         .agp_alloc_pages        = agp_generic_alloc_pages,
 554         .agp_destroy_page       = agp_generic_destroy_page,
 555         .agp_destroy_pages      = agp_generic_destroy_pages,
 556         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
 557         .cant_use_aperture      = true,
 558         .needs_scratch_page     = true,
 559 };
 560
 561 static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = {
 562         {
 563                 .device_id      = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
 564                 .chipset_name   = "UniNorth",
 565         },
 566         {
 567                 .device_id      = PCI_DEVICE_ID_APPLE_UNI_N_AGP_P,
 568                 .chipset_name   = "UniNorth/Pangea",
 569         },
 570         {
 571                 .device_id      = PCI_DEVICE_ID_APPLE_UNI_N_AGP15,
 572                 .chipset_name   = "UniNorth 1.5",
 573         },
 574         {
 575                 .device_id      = PCI_DEVICE_ID_APPLE_UNI_N_AGP2,
 576                 .chipset_name   = "UniNorth 2",
 577         },
 578         {
 579                 .device_id      = PCI_DEVICE_ID_APPLE_U3_AGP,
 580                 .chipset_name   = "U3",
 581         },
 582         {
 583                 .device_id      = PCI_DEVICE_ID_APPLE_U3L_AGP,
 584                 .chipset_name   = "U3L",
 585         },
 586         {
 587                 .device_id      = PCI_DEVICE_ID_APPLE_U3H_AGP,
 588                 .chipset_name   = "U3H",
 589         },
 590         {
 591                 .device_id      = PCI_DEVICE_ID_APPLE_IPID2_AGP,
 592                 .chipset_name   = "UniNorth/Intrepid2",
 593         },
 594 };
 595
 596 static int __devinit agp_uninorth_probe(struct pci_dev *pdev,
 597                                         const struct pci_device_id *ent)
 598 {
 599         struct agp_device_ids *devs = uninorth_agp_device_ids;
 600         struct agp_bridge_data *bridge;
 601         struct device_node *uninorth_node;
 602         u8 cap_ptr;
 603         int j;
 604
 605         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 606         if (cap_ptr == 0)
 607                 return -ENODEV;
 608
 609         /* probe for known chipsets */
 610         for (j = 0; devs[j].chipset_name != NULL; ++j) {
 611                 if (pdev->device == devs[j].device_id) {
 612                         dev_info(&pdev->dev, "Apple %s chipset\n",
 613                                  devs[j].chipset_name);
 614                         goto found;
 615                 }
 616         }
 617
 618         dev_err(&pdev->dev, "unsupported Apple chipset [%04x/%04x]\n",
 619                 pdev->vendor, pdev->device);
 620         return -ENODEV;
 621
 622  found:
 623         /* Set revision to 0 if we could not read it. */
 624         uninorth_rev = 0;
 625         is_u3 = 0;
 626         /* Locate core99 Uni-N */
 627         uninorth_node = of_find_node_by_name(NULL, "uni-n");
 628         /* Locate G5 u3 */
 629         if (uninorth_node == NULL) {
 630                 is_u3 = 1;
 631                 uninorth_node = of_find_node_by_name(NULL, "u3");
 632         }
 633         if (uninorth_node) {
 634                 const int *revprop = of_get_property(uninorth_node,
 635                                 "device-rev", NULL);
 636                 if (revprop != NULL)
 637                         uninorth_rev = *revprop & 0x3f;
 638                 of_node_put(uninorth_node);
 639         }
 640
 641 #ifdef CONFIG_PM
 642         /* Inform platform of our suspend/resume caps */
 643         pmac_register_agp_pm(pdev, agp_uninorth_suspend, agp_uninorth_resume);
 644 #endif
 645
 646         /* Allocate & setup our driver */
 647         bridge = agp_alloc_bridge();
 648         if (!bridge)
 649                 return -ENOMEM;
 650
 651         if (is_u3)
 652                 bridge->driver = &u3_agp_driver;
 653         else
 654                 bridge->driver = &uninorth_agp_driver;
 655
 656         bridge->dev = pdev;
 657         bridge->capndx = cap_ptr;
 658         bridge->flags = AGP_ERRATA_FASTWRITES;
 659
 660         /* Fill in the mode register */
 661         pci_read_config_dword(pdev, cap_ptr+PCI_AGP_STATUS, &bridge->mode);
 662
 663         pci_set_drvdata(pdev, bridge);
 664         return agp_add_bridge(bridge);
 665 }
 666
 667 static void __devexit agp_uninorth_remove(struct pci_dev *pdev)
 668 {
 669         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 670
 671 #ifdef CONFIG_PM
 672         /* Inform platform of our suspend/resume caps */
 673         pmac_register_agp_pm(pdev, NULL, NULL);
 674 #endif
 675
 676         agp_remove_bridge(bridge);
 677         agp_put_bridge(bridge);
 678 }
 679
 680 static struct pci_device_id agp_uninorth_pci_table[] = {
 681         {
 682         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 683         .class_mask     = ~0,
 684         .vendor         = PCI_VENDOR_ID_APPLE,
 685         .device         = PCI_ANY_ID,
 686         .subvendor      = PCI_ANY_ID,
 687         .subdevice      = PCI_ANY_ID,
 688         },
 689         { }
 690 };
 691
 692 MODULE_DEVICE_TABLE(pci, agp_uninorth_pci_table);
 693
 694 static struct pci_driver agp_uninorth_pci_driver = {
 695         .name           = "agpgart-uninorth",
 696         .id_table       = agp_uninorth_pci_table,
 697         .probe          = agp_uninorth_probe,
 698         .remove         = agp_uninorth_remove,
 699 };
 700
 701 static int __init agp_uninorth_init(void)
 702 {
 703         if (agp_off)
 704                 return -EINVAL;
 705         return pci_register_driver(&agp_uninorth_pci_driver);
 706 }
 707
 708 static void __exit agp_uninorth_cleanup(void)
 709 {
 710         pci_unregister_driver(&agp_uninorth_pci_driver);
 711 }
 712
 713 module_init(agp_uninorth_init);
 714 module_exit(agp_uninorth_cleanup);
 715
 716 module_param(aperture, charp, 0);
 717 MODULE_PARM_DESC(aperture,
 718                  "Aperture size, must be power of two between 4MB and an\n"
 719                  "\t\tupper limit specific to the UniNorth revision.\n"
 720                  "\t\tDefault: " DEFAULT_APERTURE_STRING "M");
 721
 722 MODULE_AUTHOR("Ben Herrenschmidt & Paul Mackerras");
 723 MODULE_LICENSE("GPL");