drivers/ata/sata_sx4.c

   1 /*
   2  *  sata_sx4.c - Promise SATA
   3  *
   4  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2003-2004 Red Hat, Inc.
   9  *
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; see the file COPYING.  If not, write to
  23  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  *
  26  *  libata documentation is available via 'make {ps|pdf}docs',
  27  *  as Documentation/DocBook/libata.*
  28  *
  29  *  Hardware documentation available under NDA.
  30  *
  31  */
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/pci.h>
  36 #include <linux/init.h>
  37 #include <linux/blkdev.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/sched.h>
  41 #include <linux/device.h>
  42 #include <scsi/scsi_host.h>
  43 #include <scsi/scsi_cmnd.h>
  44 #include <linux/libata.h>
  45 #include "sata_promise.h"
  46
  47 #define DRV_NAME        "sata_sx4"
  48 #define DRV_VERSION     "0.9"
  49
  50
  51 enum {
  52         PDC_PRD_TBL             = 0x44, /* Direct command DMA table addr */
  53
  54         PDC_PKT_SUBMIT          = 0x40, /* Command packet pointer addr */
  55         PDC_HDMA_PKT_SUBMIT     = 0x100, /* Host DMA packet pointer addr */
  56         PDC_INT_SEQMASK         = 0x40, /* Mask of asserted SEQ INTs */
  57         PDC_HDMA_CTLSTAT        = 0x12C, /* Host DMA control / status */
  58
  59         PDC_20621_SEQCTL        = 0x400,
  60         PDC_20621_SEQMASK       = 0x480,
  61         PDC_20621_GENERAL_CTL   = 0x484,
  62         PDC_20621_PAGE_SIZE     = (32 * 1024),
  63
  64         /* chosen, not constant, values; we design our own DIMM mem map */
  65         PDC_20621_DIMM_WINDOW   = 0x0C, /* page# for 32K DIMM window */
  66         PDC_20621_DIMM_BASE     = 0x00200000,
  67         PDC_20621_DIMM_DATA     = (64 * 1024),
  68         PDC_DIMM_DATA_STEP      = (256 * 1024),
  69         PDC_DIMM_WINDOW_STEP    = (8 * 1024),
  70         PDC_DIMM_HOST_PRD       = (6 * 1024),
  71         PDC_DIMM_HOST_PKT       = (128 * 0),
  72         PDC_DIMM_HPKT_PRD       = (128 * 1),
  73         PDC_DIMM_ATA_PKT        = (128 * 2),
  74         PDC_DIMM_APKT_PRD       = (128 * 3),
  75         PDC_DIMM_HEADER_SZ      = PDC_DIMM_APKT_PRD + 128,
  76         PDC_PAGE_WINDOW         = 0x40,
  77         PDC_PAGE_DATA           = PDC_PAGE_WINDOW +
  78                                   (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
  79         PDC_PAGE_SET            = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
  80
  81         PDC_CHIP0_OFS           = 0xC0000, /* offset of chip #0 */
  82
  83         PDC_20621_ERR_MASK      = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
  84                                   (1<<23),
  85
  86         board_20621             = 0,    /* FastTrak S150 SX4 */
  87
  88         PDC_RESET               = (1 << 11), /* HDMA reset */
  89
  90         PDC_MAX_HDMA            = 32,
  91         PDC_HDMA_Q_MASK         = (PDC_MAX_HDMA - 1),
  92
  93         PDC_DIMM0_SPD_DEV_ADDRESS     = 0x50,
  94         PDC_DIMM1_SPD_DEV_ADDRESS     = 0x51,
  95         PDC_MAX_DIMM_MODULE           = 0x02,
  96         PDC_I2C_CONTROL_OFFSET        = 0x48,
  97         PDC_I2C_ADDR_DATA_OFFSET      = 0x4C,
  98         PDC_DIMM0_CONTROL_OFFSET      = 0x80,
  99         PDC_DIMM1_CONTROL_OFFSET      = 0x84,
 100         PDC_SDRAM_CONTROL_OFFSET      = 0x88,
 101         PDC_I2C_WRITE                 = 0x00000000,
 102         PDC_I2C_READ                  = 0x00000040,
 103         PDC_I2C_START                 = 0x00000080,
 104         PDC_I2C_MASK_INT              = 0x00000020,
 105         PDC_I2C_COMPLETE              = 0x00010000,
 106         PDC_I2C_NO_ACK                = 0x00100000,
 107         PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
 108         PDC_DIMM_SPD_SUBADDRESS_END   = 0x7F,
 109         PDC_DIMM_SPD_ROW_NUM          = 3,
 110         PDC_DIMM_SPD_COLUMN_NUM       = 4,
 111         PDC_DIMM_SPD_MODULE_ROW       = 5,
 112         PDC_DIMM_SPD_TYPE             = 11,
 113         PDC_DIMM_SPD_FRESH_RATE       = 12,
 114         PDC_DIMM_SPD_BANK_NUM         = 17,
 115         PDC_DIMM_SPD_CAS_LATENCY      = 18,
 116         PDC_DIMM_SPD_ATTRIBUTE        = 21,
 117         PDC_DIMM_SPD_ROW_PRE_CHARGE   = 27,
 118         PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
 119         PDC_DIMM_SPD_RAS_CAS_DELAY    = 29,
 120         PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
 121         PDC_DIMM_SPD_SYSTEM_FREQ      = 126,
 122         PDC_CTL_STATUS                = 0x08,
 123         PDC_DIMM_WINDOW_CTLR          = 0x0C,
 124         PDC_TIME_CONTROL              = 0x3C,
 125         PDC_TIME_PERIOD               = 0x40,
 126         PDC_TIME_COUNTER              = 0x44,
 127         PDC_GENERAL_CTLR              = 0x484,
 128         PCI_PLL_INIT                  = 0x8A531824,
 129         PCI_X_TCOUNT                  = 0xEE1E5CFF
 130 };
 131
 132
 133 struct pdc_port_priv {
 134         u8                      dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
 135         u8                      *pkt;
 136         dma_addr_t              pkt_dma;
 137 };
 138
 139 struct pdc_host_priv {
 140         void                    __iomem *dimm_mmio;
 141
 142         unsigned int            doing_hdma;
 143         unsigned int            hdma_prod;
 144         unsigned int            hdma_cons;
 145         struct {
 146                 struct ata_queued_cmd *qc;
 147                 unsigned int    seq;
 148                 unsigned long   pkt_ofs;
 149         } hdma[32];
 150 };
 151
 152
 153 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
 154 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance);
 155 static void pdc_eng_timeout(struct ata_port *ap);
 156 static void pdc_20621_phy_reset (struct ata_port *ap);
 157 static int pdc_port_start(struct ata_port *ap);
 158 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
 159 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
 160 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
 161 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
 162 static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
 163 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
 164                                       u32 device, u32 subaddr, u32 *pdata);
 165 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
 166 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
 167 #ifdef ATA_VERBOSE_DEBUG
 168 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
 169                                    void *psource, u32 offset, u32 size);
 170 #endif
 171 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
 172                                  void *psource, u32 offset, u32 size);
 173 static void pdc20621_irq_clear(struct ata_port *ap);
 174 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
 175
 176
 177 static struct scsi_host_template pdc_sata_sht = {
 178         .module                 = THIS_MODULE,
 179         .name                   = DRV_NAME,
 180         .ioctl                  = ata_scsi_ioctl,
 181         .queuecommand           = ata_scsi_queuecmd,
 182         .can_queue              = ATA_DEF_QUEUE,
 183         .this_id                = ATA_SHT_THIS_ID,
 184         .sg_tablesize           = LIBATA_MAX_PRD,
 185         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 186         .emulated               = ATA_SHT_EMULATED,
 187         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 188         .proc_name              = DRV_NAME,
 189         .dma_boundary           = ATA_DMA_BOUNDARY,
 190         .slave_configure        = ata_scsi_slave_config,
 191         .slave_destroy          = ata_scsi_slave_destroy,
 192         .bios_param             = ata_std_bios_param,
 193 };
 194
 195 static const struct ata_port_operations pdc_20621_ops = {
 196         .port_disable           = ata_port_disable,
 197         .tf_load                = pdc_tf_load_mmio,
 198         .tf_read                = ata_tf_read,
 199         .check_status           = ata_check_status,
 200         .exec_command           = pdc_exec_command_mmio,
 201         .dev_select             = ata_std_dev_select,
 202         .phy_reset              = pdc_20621_phy_reset,
 203         .qc_prep                = pdc20621_qc_prep,
 204         .qc_issue               = pdc20621_qc_issue_prot,
 205         .data_xfer              = ata_mmio_data_xfer,
 206         .eng_timeout            = pdc_eng_timeout,
 207         .irq_handler            = pdc20621_interrupt,
 208         .irq_clear              = pdc20621_irq_clear,
 209         .port_start             = pdc_port_start,
 210 };
 211
 212 static const struct ata_port_info pdc_port_info[] = {
 213         /* board_20621 */
 214         {
 215                 .sht            = &pdc_sata_sht,
 216                 .flags          = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 217                                   ATA_FLAG_SRST | ATA_FLAG_MMIO |
 218                                   ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING,
 219                 .pio_mask       = 0x1f, /* pio0-4 */
 220                 .mwdma_mask     = 0x07, /* mwdma0-2 */
 221                 .udma_mask      = 0x7f, /* udma0-6 ; FIXME */
 222                 .port_ops       = &pdc_20621_ops,
 223         },
 224
 225 };
 226
 227 static const struct pci_device_id pdc_sata_pci_tbl[] = {
 228         { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
 229
 230         { }     /* terminate list */
 231 };
 232
 233 static struct pci_driver pdc_sata_pci_driver = {
 234         .name                   = DRV_NAME,
 235         .id_table               = pdc_sata_pci_tbl,
 236         .probe                  = pdc_sata_init_one,
 237         .remove                 = ata_pci_remove_one,
 238 };
 239
 240
 241 static int pdc_port_start(struct ata_port *ap)
 242 {
 243         struct device *dev = ap->host->dev;
 244         struct pdc_port_priv *pp;
 245         int rc;
 246
 247         rc = ata_port_start(ap);
 248         if (rc)
 249                 return rc;
 250
 251         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
 252         if (!pp)
 253                 return -ENOMEM;
 254
 255         pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
 256         if (!pp->pkt)
 257                 return -ENOMEM;
 258
 259         ap->private_data = pp;
 260
 261         return 0;
 262 }
 263
 264 static void pdc_20621_phy_reset (struct ata_port *ap)
 265 {
 266         VPRINTK("ENTER\n");
 267         ap->cbl = ATA_CBL_SATA;
 268         ata_port_probe(ap);
 269         ata_bus_reset(ap);
 270 }
 271
 272 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
 273                                            unsigned int portno,
 274                                            unsigned int total_len)
 275 {
 276         u32 addr;
 277         unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
 278         u32 *buf32 = (u32 *) buf;
 279
 280         /* output ATA packet S/G table */
 281         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 282                (PDC_DIMM_DATA_STEP * portno);
 283         VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
 284         buf32[dw] = cpu_to_le32(addr);
 285         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 286
 287         VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
 288                 PDC_20621_DIMM_BASE +
 289                        (PDC_DIMM_WINDOW_STEP * portno) +
 290                        PDC_DIMM_APKT_PRD,
 291                 buf32[dw], buf32[dw + 1]);
 292 }
 293
 294 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
 295                                             unsigned int portno,
 296                                             unsigned int total_len)
 297 {
 298         u32 addr;
 299         unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
 300         u32 *buf32 = (u32 *) buf;
 301
 302         /* output Host DMA packet S/G table */
 303         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 304                (PDC_DIMM_DATA_STEP * portno);
 305
 306         buf32[dw] = cpu_to_le32(addr);
 307         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 308
 309         VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
 310                 PDC_20621_DIMM_BASE +
 311                        (PDC_DIMM_WINDOW_STEP * portno) +
 312                        PDC_DIMM_HPKT_PRD,
 313                 buf32[dw], buf32[dw + 1]);
 314 }
 315
 316 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
 317                                             unsigned int devno, u8 *buf,
 318                                             unsigned int portno)
 319 {
 320         unsigned int i, dw;
 321         u32 *buf32 = (u32 *) buf;
 322         u8 dev_reg;
 323
 324         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 325                                (PDC_DIMM_WINDOW_STEP * portno) +
 326                                PDC_DIMM_APKT_PRD;
 327         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 328
 329         i = PDC_DIMM_ATA_PKT;
 330
 331         /*
 332          * Set up ATA packet
 333          */
 334         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 335                 buf[i++] = PDC_PKT_READ;
 336         else if (tf->protocol == ATA_PROT_NODATA)
 337                 buf[i++] = PDC_PKT_NODATA;
 338         else
 339                 buf[i++] = 0;
 340         buf[i++] = 0;                   /* reserved */
 341         buf[i++] = portno + 1;          /* seq. id */
 342         buf[i++] = 0xff;                /* delay seq. id */
 343
 344         /* dimm dma S/G, and next-pkt */
 345         dw = i >> 2;
 346         if (tf->protocol == ATA_PROT_NODATA)
 347                 buf32[dw] = 0;
 348         else
 349                 buf32[dw] = cpu_to_le32(dimm_sg);
 350         buf32[dw + 1] = 0;
 351         i += 8;
 352
 353         if (devno == 0)
 354                 dev_reg = ATA_DEVICE_OBS;
 355         else
 356                 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
 357
 358         /* select device */
 359         buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
 360         buf[i++] = dev_reg;
 361
 362         /* device control register */
 363         buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
 364         buf[i++] = tf->ctl;
 365
 366         return i;
 367 }
 368
 369 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
 370                                      unsigned int portno)
 371 {
 372         unsigned int dw;
 373         u32 tmp, *buf32 = (u32 *) buf;
 374
 375         unsigned int host_sg = PDC_20621_DIMM_BASE +
 376                                (PDC_DIMM_WINDOW_STEP * portno) +
 377                                PDC_DIMM_HOST_PRD;
 378         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 379                                (PDC_DIMM_WINDOW_STEP * portno) +
 380                                PDC_DIMM_HPKT_PRD;
 381         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 382         VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
 383
 384         dw = PDC_DIMM_HOST_PKT >> 2;
 385
 386         /*
 387          * Set up Host DMA packet
 388          */
 389         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 390                 tmp = PDC_PKT_READ;
 391         else
 392                 tmp = 0;
 393         tmp |= ((portno + 1 + 4) << 16);        /* seq. id */
 394         tmp |= (0xff << 24);                    /* delay seq. id */
 395         buf32[dw + 0] = cpu_to_le32(tmp);
 396         buf32[dw + 1] = cpu_to_le32(host_sg);
 397         buf32[dw + 2] = cpu_to_le32(dimm_sg);
 398         buf32[dw + 3] = 0;
 399
 400         VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
 401                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
 402                         PDC_DIMM_HOST_PKT,
 403                 buf32[dw + 0],
 404                 buf32[dw + 1],
 405                 buf32[dw + 2],
 406                 buf32[dw + 3]);
 407 }
 408
 409 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
 410 {
 411         struct scatterlist *sg;
 412         struct ata_port *ap = qc->ap;
 413         struct pdc_port_priv *pp = ap->private_data;
 414         void __iomem *mmio = ap->host->mmio_base;
 415         struct pdc_host_priv *hpriv = ap->host->private_data;
 416         void __iomem *dimm_mmio = hpriv->dimm_mmio;
 417         unsigned int portno = ap->port_no;
 418         unsigned int i, idx, total_len = 0, sgt_len;
 419         u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
 420
 421         WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
 422
 423         VPRINTK("ata%u: ENTER\n", ap->id);
 424
 425         /* hard-code chip #0 */
 426         mmio += PDC_CHIP0_OFS;
 427
 428         /*
 429          * Build S/G table
 430          */
 431         idx = 0;
 432         ata_for_each_sg(sg, qc) {
 433                 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
 434                 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
 435                 total_len += sg_dma_len(sg);
 436         }
 437         buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
 438         sgt_len = idx * 4;
 439
 440         /*
 441          * Build ATA, host DMA packets
 442          */
 443         pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 444         pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
 445
 446         pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 447         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 448
 449         if (qc->tf.flags & ATA_TFLAG_LBA48)
 450                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 451         else
 452                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 453
 454         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 455
 456         /* copy three S/G tables and two packets to DIMM MMIO window */
 457         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 458                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 459         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
 460                     PDC_DIMM_HOST_PRD,
 461                     &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
 462
 463         /* force host FIFO dump */
 464         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 465
 466         readl(dimm_mmio);       /* MMIO PCI posting flush */
 467
 468         VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
 469 }
 470
 471 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
 472 {
 473         struct ata_port *ap = qc->ap;
 474         struct pdc_port_priv *pp = ap->private_data;
 475         void __iomem *mmio = ap->host->mmio_base;
 476         struct pdc_host_priv *hpriv = ap->host->private_data;
 477         void __iomem *dimm_mmio = hpriv->dimm_mmio;
 478         unsigned int portno = ap->port_no;
 479         unsigned int i;
 480
 481         VPRINTK("ata%u: ENTER\n", ap->id);
 482
 483         /* hard-code chip #0 */
 484         mmio += PDC_CHIP0_OFS;
 485
 486         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 487
 488         if (qc->tf.flags & ATA_TFLAG_LBA48)
 489                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 490         else
 491                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 492
 493         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 494
 495         /* copy three S/G tables and two packets to DIMM MMIO window */
 496         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 497                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 498
 499         /* force host FIFO dump */
 500         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 501
 502         readl(dimm_mmio);       /* MMIO PCI posting flush */
 503
 504         VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
 505 }
 506
 507 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
 508 {
 509         switch (qc->tf.protocol) {
 510         case ATA_PROT_DMA:
 511                 pdc20621_dma_prep(qc);
 512                 break;
 513         case ATA_PROT_NODATA:
 514                 pdc20621_nodata_prep(qc);
 515                 break;
 516         default:
 517                 break;
 518         }
 519 }
 520
 521 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
 522                                  unsigned int seq,
 523                                  u32 pkt_ofs)
 524 {
 525         struct ata_port *ap = qc->ap;
 526         struct ata_host *host = ap->host;
 527         void __iomem *mmio = host->mmio_base;
 528
 529         /* hard-code chip #0 */
 530         mmio += PDC_CHIP0_OFS;
 531
 532         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 533         readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 534
 535         writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
 536         readl(mmio + PDC_HDMA_PKT_SUBMIT);      /* flush */
 537 }
 538
 539 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
 540                                 unsigned int seq,
 541                                 u32 pkt_ofs)
 542 {
 543         struct ata_port *ap = qc->ap;
 544         struct pdc_host_priv *pp = ap->host->private_data;
 545         unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
 546
 547         if (!pp->doing_hdma) {
 548                 __pdc20621_push_hdma(qc, seq, pkt_ofs);
 549                 pp->doing_hdma = 1;
 550                 return;
 551         }
 552
 553         pp->hdma[idx].qc = qc;
 554         pp->hdma[idx].seq = seq;
 555         pp->hdma[idx].pkt_ofs = pkt_ofs;
 556         pp->hdma_prod++;
 557 }
 558
 559 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
 560 {
 561         struct ata_port *ap = qc->ap;
 562         struct pdc_host_priv *pp = ap->host->private_data;
 563         unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
 564
 565         /* if nothing on queue, we're done */
 566         if (pp->hdma_prod == pp->hdma_cons) {
 567                 pp->doing_hdma = 0;
 568                 return;
 569         }
 570
 571         __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
 572                              pp->hdma[idx].pkt_ofs);
 573         pp->hdma_cons++;
 574 }
 575
 576 #ifdef ATA_VERBOSE_DEBUG
 577 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
 578 {
 579         struct ata_port *ap = qc->ap;
 580         unsigned int port_no = ap->port_no;
 581         struct pdc_host_priv *hpriv = ap->host->private_data;
 582         void *dimm_mmio = hpriv->dimm_mmio;
 583
 584         dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
 585         dimm_mmio += PDC_DIMM_HOST_PKT;
 586
 587         printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
 588         printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
 589         printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
 590         printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
 591 }
 592 #else
 593 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
 594 #endif /* ATA_VERBOSE_DEBUG */
 595
 596 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
 597 {
 598         struct ata_port *ap = qc->ap;
 599         struct ata_host *host = ap->host;
 600         unsigned int port_no = ap->port_no;
 601         void __iomem *mmio = host->mmio_base;
 602         unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 603         u8 seq = (u8) (port_no + 1);
 604         unsigned int port_ofs;
 605
 606         /* hard-code chip #0 */
 607         mmio += PDC_CHIP0_OFS;
 608
 609         VPRINTK("ata%u: ENTER\n", ap->id);
 610
 611         wmb();                  /* flush PRD, pkt writes */
 612
 613         port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 614
 615         /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
 616         if (rw && qc->tf.protocol == ATA_PROT_DMA) {
 617                 seq += 4;
 618
 619                 pdc20621_dump_hdma(qc);
 620                 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
 621                 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
 622                         port_ofs + PDC_DIMM_HOST_PKT,
 623                         port_ofs + PDC_DIMM_HOST_PKT,
 624                         seq);
 625         } else {
 626                 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 627                 readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 628
 629                 writel(port_ofs + PDC_DIMM_ATA_PKT,
 630                        (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 631                 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 632                 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
 633                         port_ofs + PDC_DIMM_ATA_PKT,
 634                         port_ofs + PDC_DIMM_ATA_PKT,
 635                         seq);
 636         }
 637 }
 638
 639 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
 640 {
 641         switch (qc->tf.protocol) {
 642         case ATA_PROT_DMA:
 643         case ATA_PROT_NODATA:
 644                 pdc20621_packet_start(qc);
 645                 return 0;
 646
 647         case ATA_PROT_ATAPI_DMA:
 648                 BUG();
 649                 break;
 650
 651         default:
 652                 break;
 653         }
 654
 655         return ata_qc_issue_prot(qc);
 656 }
 657
 658 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
 659                                           struct ata_queued_cmd *qc,
 660                                           unsigned int doing_hdma,
 661                                           void __iomem *mmio)
 662 {
 663         unsigned int port_no = ap->port_no;
 664         unsigned int port_ofs =
 665                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 666         u8 status;
 667         unsigned int handled = 0;
 668
 669         VPRINTK("ENTER\n");
 670
 671         if ((qc->tf.protocol == ATA_PROT_DMA) &&        /* read */
 672             (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
 673
 674                 /* step two - DMA from DIMM to host */
 675                 if (doing_hdma) {
 676                         VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
 677                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 678                         /* get drive status; clear intr; complete txn */
 679                         qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
 680                         ata_qc_complete(qc);
 681                         pdc20621_pop_hdma(qc);
 682                 }
 683
 684                 /* step one - exec ATA command */
 685                 else {
 686                         u8 seq = (u8) (port_no + 1 + 4);
 687                         VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
 688                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 689
 690                         /* submit hdma pkt */
 691                         pdc20621_dump_hdma(qc);
 692                         pdc20621_push_hdma(qc, seq,
 693                                            port_ofs + PDC_DIMM_HOST_PKT);
 694                 }
 695                 handled = 1;
 696
 697         } else if (qc->tf.protocol == ATA_PROT_DMA) {   /* write */
 698
 699                 /* step one - DMA from host to DIMM */
 700                 if (doing_hdma) {
 701                         u8 seq = (u8) (port_no + 1);
 702                         VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
 703                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 704
 705                         /* submit ata pkt */
 706                         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 707                         readl(mmio + PDC_20621_SEQCTL + (seq * 4));
 708                         writel(port_ofs + PDC_DIMM_ATA_PKT,
 709                                (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 710                         readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 711                 }
 712
 713                 /* step two - execute ATA command */
 714                 else {
 715                         VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
 716                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 717                         /* get drive status; clear intr; complete txn */
 718                         qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
 719                         ata_qc_complete(qc);
 720                         pdc20621_pop_hdma(qc);
 721                 }
 722                 handled = 1;
 723
 724         /* command completion, but no data xfer */
 725         } else if (qc->tf.protocol == ATA_PROT_NODATA) {
 726
 727                 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 728                 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
 729                 qc->err_mask |= ac_err_mask(status);
 730                 ata_qc_complete(qc);
 731                 handled = 1;
 732
 733         } else {
 734                 ap->stats.idle_irq++;
 735         }
 736
 737         return handled;
 738 }
 739
 740 static void pdc20621_irq_clear(struct ata_port *ap)
 741 {
 742         struct ata_host *host = ap->host;
 743         void __iomem *mmio = host->mmio_base;
 744
 745         mmio += PDC_CHIP0_OFS;
 746
 747         readl(mmio + PDC_20621_SEQMASK);
 748 }
 749
 750 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance)
 751 {
 752         struct ata_host *host = dev_instance;
 753         struct ata_port *ap;
 754         u32 mask = 0;
 755         unsigned int i, tmp, port_no;
 756         unsigned int handled = 0;
 757         void __iomem *mmio_base;
 758
 759         VPRINTK("ENTER\n");
 760
 761         if (!host || !host->mmio_base) {
 762                 VPRINTK("QUICK EXIT\n");
 763                 return IRQ_NONE;
 764         }
 765
 766         mmio_base = host->mmio_base;
 767
 768         /* reading should also clear interrupts */
 769         mmio_base += PDC_CHIP0_OFS;
 770         mask = readl(mmio_base + PDC_20621_SEQMASK);
 771         VPRINTK("mask == 0x%x\n", mask);
 772
 773         if (mask == 0xffffffff) {
 774                 VPRINTK("QUICK EXIT 2\n");
 775                 return IRQ_NONE;
 776         }
 777         mask &= 0xffff;         /* only 16 tags possible */
 778         if (!mask) {
 779                 VPRINTK("QUICK EXIT 3\n");
 780                 return IRQ_NONE;
 781         }
 782
 783         spin_lock(&host->lock);
 784
 785         for (i = 1; i < 9; i++) {
 786                 port_no = i - 1;
 787                 if (port_no > 3)
 788                         port_no -= 4;
 789                 if (port_no >= host->n_ports)
 790                         ap = NULL;
 791                 else
 792                         ap = host->ports[port_no];
 793                 tmp = mask & (1 << i);
 794                 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
 795                 if (tmp && ap &&
 796                     !(ap->flags & ATA_FLAG_DISABLED)) {
 797                         struct ata_queued_cmd *qc;
 798
 799                         qc = ata_qc_from_tag(ap, ap->active_tag);
 800                         if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
 801                                 handled += pdc20621_host_intr(ap, qc, (i > 4),
 802                                                               mmio_base);
 803                 }
 804         }
 805
 806         spin_unlock(&host->lock);
 807
 808         VPRINTK("mask == 0x%x\n", mask);
 809
 810         VPRINTK("EXIT\n");
 811
 812         return IRQ_RETVAL(handled);
 813 }
 814
 815 static void pdc_eng_timeout(struct ata_port *ap)
 816 {
 817         u8 drv_stat;
 818         struct ata_host *host = ap->host;
 819         struct ata_queued_cmd *qc;
 820         unsigned long flags;
 821
 822         DPRINTK("ENTER\n");
 823
 824         spin_lock_irqsave(&host->lock, flags);
 825
 826         qc = ata_qc_from_tag(ap, ap->active_tag);
 827
 828         switch (qc->tf.protocol) {
 829         case ATA_PROT_DMA:
 830         case ATA_PROT_NODATA:
 831                 ata_port_printk(ap, KERN_ERR, "command timeout\n");
 832                 qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
 833                 break;
 834
 835         default:
 836                 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 837
 838                 ata_port_printk(ap, KERN_ERR,
 839                                 "unknown timeout, cmd 0x%x stat 0x%x\n",
 840                                 qc->tf.command, drv_stat);
 841
 842                 qc->err_mask |= ac_err_mask(drv_stat);
 843                 break;
 844         }
 845
 846         spin_unlock_irqrestore(&host->lock, flags);
 847         ata_eh_qc_complete(qc);
 848         DPRINTK("EXIT\n");
 849 }
 850
 851 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
 852 {
 853         WARN_ON (tf->protocol == ATA_PROT_DMA ||
 854                  tf->protocol == ATA_PROT_NODATA);
 855         ata_tf_load(ap, tf);
 856 }
 857
 858
 859 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
 860 {
 861         WARN_ON (tf->protocol == ATA_PROT_DMA ||
 862                  tf->protocol == ATA_PROT_NODATA);
 863         ata_exec_command(ap, tf);
 864 }
 865
 866
 867 static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
 868 {
 869         port->cmd_addr          = base;
 870         port->data_addr         = base;
 871         port->feature_addr      =
 872         port->error_addr        = base + 0x4;
 873         port->nsect_addr        = base + 0x8;
 874         port->lbal_addr         = base + 0xc;
 875         port->lbam_addr         = base + 0x10;
 876         port->lbah_addr         = base + 0x14;
 877         port->device_addr       = base + 0x18;
 878         port->command_addr      =
 879         port->status_addr       = base + 0x1c;
 880         port->altstatus_addr    =
 881         port->ctl_addr          = base + 0x38;
 882 }
 883
 884
 885 #ifdef ATA_VERBOSE_DEBUG
 886 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
 887                                    u32 offset, u32 size)
 888 {
 889         u32 window_size;
 890         u16 idx;
 891         u8 page_mask;
 892         long dist;
 893         void __iomem *mmio = pe->mmio_base;
 894         struct pdc_host_priv *hpriv = pe->private_data;
 895         void __iomem *dimm_mmio = hpriv->dimm_mmio;
 896
 897         /* hard-code chip #0 */
 898         mmio += PDC_CHIP0_OFS;
 899
 900         page_mask = 0x00;
 901         window_size = 0x2000 * 4; /* 32K byte uchar size */
 902         idx = (u16) (offset / window_size);
 903
 904         writel(0x01, mmio + PDC_GENERAL_CTLR);
 905         readl(mmio + PDC_GENERAL_CTLR);
 906         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 907         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 908
 909         offset -= (idx * window_size);
 910         idx++;
 911         dist = ((long) (window_size - (offset + size))) >= 0 ? size :
 912                 (long) (window_size - offset);
 913         memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
 914                       dist);
 915
 916         psource += dist;
 917         size -= dist;
 918         for (; (long) size >= (long) window_size ;) {
 919                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 920                 readl(mmio + PDC_GENERAL_CTLR);
 921                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 922                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 923                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 924                               window_size / 4);
 925                 psource += window_size;
 926                 size -= window_size;
 927                 idx ++;
 928         }
 929
 930         if (size) {
 931                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 932                 readl(mmio + PDC_GENERAL_CTLR);
 933                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 934                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 935                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 936                               size / 4);
 937         }
 938 }
 939 #endif
 940
 941
 942 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
 943                                  u32 offset, u32 size)
 944 {
 945         u32 window_size;
 946         u16 idx;
 947         u8 page_mask;
 948         long dist;
 949         void __iomem *mmio = pe->mmio_base;
 950         struct pdc_host_priv *hpriv = pe->private_data;
 951         void __iomem *dimm_mmio = hpriv->dimm_mmio;
 952
 953         /* hard-code chip #0 */
 954         mmio += PDC_CHIP0_OFS;
 955
 956         page_mask = 0x00;
 957         window_size = 0x2000 * 4;       /* 32K byte uchar size */
 958         idx = (u16) (offset / window_size);
 959
 960         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 961         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 962         offset -= (idx * window_size);
 963         idx++;
 964         dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
 965                 (long) (window_size - offset);
 966         memcpy_toio(dimm_mmio + offset / 4, psource, dist);
 967         writel(0x01, mmio + PDC_GENERAL_CTLR);
 968         readl(mmio + PDC_GENERAL_CTLR);
 969
 970         psource += dist;
 971         size -= dist;
 972         for (; (long) size >= (long) window_size ;) {
 973                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 974                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 975                 memcpy_toio(dimm_mmio, psource, window_size / 4);
 976                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 977                 readl(mmio + PDC_GENERAL_CTLR);
 978                 psource += window_size;
 979                 size -= window_size;
 980                 idx ++;
 981         }
 982
 983         if (size) {
 984                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 985                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 986                 memcpy_toio(dimm_mmio, psource, size / 4);
 987                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 988                 readl(mmio + PDC_GENERAL_CTLR);
 989         }
 990 }
 991
 992
 993 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
 994                                       u32 subaddr, u32 *pdata)
 995 {
 996         void __iomem *mmio = pe->mmio_base;
 997         u32 i2creg  = 0;
 998         u32 status;
 999         u32 count =0;
1000
1001         /* hard-code chip #0 */
1002         mmio += PDC_CHIP0_OFS;
1003
1004         i2creg |= device << 24;
1005         i2creg |= subaddr << 16;
1006
1007         /* Set the device and subaddress */
1008         writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1009         readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1010
1011         /* Write Control to perform read operation, mask int */
1012         writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1013                mmio + PDC_I2C_CONTROL_OFFSET);
1014
1015         for (count = 0; count <= 1000; count ++) {
1016                 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1017                 if (status & PDC_I2C_COMPLETE) {
1018                         status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1019                         break;
1020                 } else if (count == 1000)
1021                         return 0;
1022         }
1023
1024         *pdata = (status >> 8) & 0x000000ff;
1025         return 1;
1026 }
1027
1028
1029 static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1030 {
1031         u32 data=0 ;
1032         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1033                              PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1034                 if (data == 100)
1035                         return 100;
1036         } else
1037                 return 0;
1038
1039         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1040                 if(data <= 0x75)
1041                         return 133;
1042         } else
1043                 return 0;
1044
1045         return 0;
1046 }
1047
1048
1049 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1050 {
1051         u32 spd0[50];
1052         u32 data = 0;
1053         int size, i;
1054         u8 bdimmsize;
1055         void __iomem *mmio = pe->mmio_base;
1056         static const struct {
1057                 unsigned int reg;
1058                 unsigned int ofs;
1059         } pdc_i2c_read_data [] = {
1060                 { PDC_DIMM_SPD_TYPE, 11 },
1061                 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1062                 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1063                 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1064                 { PDC_DIMM_SPD_ROW_NUM, 3 },
1065                 { PDC_DIMM_SPD_BANK_NUM, 17 },
1066                 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1067                 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1068                 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1069                 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1070                 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1071                 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1072         };
1073
1074         /* hard-code chip #0 */
1075         mmio += PDC_CHIP0_OFS;
1076
1077         for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1078                 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1079                                   pdc_i2c_read_data[i].reg,
1080                                   &spd0[pdc_i2c_read_data[i].ofs]);
1081
1082         data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1083         data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1084                 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1085         data |= (((((spd0[29] > spd0[28])
1086                     ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1087         data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1088
1089         if (spd0[18] & 0x08)
1090                 data |= ((0x03) << 14);
1091         else if (spd0[18] & 0x04)
1092                 data |= ((0x02) << 14);
1093         else if (spd0[18] & 0x01)
1094                 data |= ((0x01) << 14);
1095         else
1096                 data |= (0 << 14);
1097
1098         /*
1099            Calculate the size of bDIMMSize (power of 2) and
1100            merge the DIMM size by program start/end address.
1101         */
1102
1103         bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1104         size = (1 << bdimmsize) >> 20;  /* size = xxx(MB) */
1105         data |= (((size / 16) - 1) << 16);
1106         data |= (0 << 23);
1107         data |= 8;
1108         writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1109         readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1110         return size;
1111 }
1112
1113
1114 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1115 {
1116         u32 data, spd0;
1117         int error, i;
1118         void __iomem *mmio = pe->mmio_base;
1119
1120         /* hard-code chip #0 */
1121         mmio += PDC_CHIP0_OFS;
1122
1123         /*
1124           Set To Default : DIMM Module Global Control Register (0x022259F1)
1125           DIMM Arbitration Disable (bit 20)
1126           DIMM Data/Control Output Driving Selection (bit12 - bit15)
1127           Refresh Enable (bit 17)
1128         */
1129
1130         data = 0x022259F1;
1131         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1132         readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1133
1134         /* Turn on for ECC */
1135         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1136                           PDC_DIMM_SPD_TYPE, &spd0);
1137         if (spd0 == 0x02) {
1138                 data |= (0x01 << 16);
1139                 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1140                 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1141                 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1142         }
1143
1144         /* DIMM Initialization Select/Enable (bit 18/19) */
1145         data &= (~(1<<18));
1146         data |= (1<<19);
1147         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1148
1149         error = 1;
1150         for (i = 1; i <= 10; i++) {   /* polling ~5 secs */
1151                 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1152                 if (!(data & (1<<19))) {
1153                         error = 0;
1154                         break;
1155                 }
1156                 msleep(i*100);
1157         }
1158         return error;
1159 }
1160
1161
1162 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1163 {
1164         int speed, size, length;
1165         u32 addr,spd0,pci_status;
1166         u32 tmp=0;
1167         u32 time_period=0;
1168         u32 tcount=0;
1169         u32 ticks=0;
1170         u32 clock=0;
1171         u32 fparam=0;
1172         void __iomem *mmio = pe->mmio_base;
1173
1174         /* hard-code chip #0 */
1175         mmio += PDC_CHIP0_OFS;
1176
1177         /* Initialize PLL based upon PCI Bus Frequency */
1178
1179         /* Initialize Time Period Register */
1180         writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1181         time_period = readl(mmio + PDC_TIME_PERIOD);
1182         VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1183
1184         /* Enable timer */
1185         writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1186         readl(mmio + PDC_TIME_CONTROL);
1187
1188         /* Wait 3 seconds */
1189         msleep(3000);
1190
1191         /*
1192            When timer is enabled, counter is decreased every internal
1193            clock cycle.
1194         */
1195
1196         tcount = readl(mmio + PDC_TIME_COUNTER);
1197         VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1198
1199         /*
1200            If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1201            register should be >= (0xffffffff - 3x10^8).
1202         */
1203         if(tcount >= PCI_X_TCOUNT) {
1204                 ticks = (time_period - tcount);
1205                 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1206
1207                 clock = (ticks / 300000);
1208                 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1209
1210                 clock = (clock * 33);
1211                 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1212
1213                 /* PLL F Param (bit 22:16) */
1214                 fparam = (1400000 / clock) - 2;
1215                 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1216
1217                 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1218                 pci_status = (0x8a001824 | (fparam << 16));
1219         } else
1220                 pci_status = PCI_PLL_INIT;
1221
1222         /* Initialize PLL. */
1223         VPRINTK("pci_status: 0x%x\n", pci_status);
1224         writel(pci_status, mmio + PDC_CTL_STATUS);
1225         readl(mmio + PDC_CTL_STATUS);
1226
1227         /*
1228            Read SPD of DIMM by I2C interface,
1229            and program the DIMM Module Controller.
1230         */
1231         if (!(speed = pdc20621_detect_dimm(pe))) {
1232                 printk(KERN_ERR "Detect Local DIMM Fail\n");
1233                 return 1;       /* DIMM error */
1234         }
1235         VPRINTK("Local DIMM Speed = %d\n", speed);
1236
1237         /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1238         size = pdc20621_prog_dimm0(pe);
1239         VPRINTK("Local DIMM Size = %dMB\n",size);
1240
1241         /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1242         if (pdc20621_prog_dimm_global(pe)) {
1243                 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1244                 return 1;
1245         }
1246
1247 #ifdef ATA_VERBOSE_DEBUG
1248         {
1249                 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1250                                 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1251                                  '1','.','1','0',
1252                                 '9','8','0','3','1','6','1','2',0,0};
1253                 u8 test_parttern2[40] = {0};
1254
1255                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1256                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1257
1258                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1259                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1260                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1261                        test_parttern2[1], &(test_parttern2[2]));
1262                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1263                                        40);
1264                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1265                        test_parttern2[1], &(test_parttern2[2]));
1266
1267                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1268                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1269                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1270                        test_parttern2[1], &(test_parttern2[2]));
1271         }
1272 #endif
1273
1274         /* ECC initiliazation. */
1275
1276         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1277                           PDC_DIMM_SPD_TYPE, &spd0);
1278         if (spd0 == 0x02) {
1279                 VPRINTK("Start ECC initialization\n");
1280                 addr = 0;
1281                 length = size * 1024 * 1024;
1282                 while (addr < length) {
1283                         pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1284                                              sizeof(u32));
1285                         addr += sizeof(u32);
1286                 }
1287                 VPRINTK("Finish ECC initialization\n");
1288         }
1289         return 0;
1290 }
1291
1292
1293 static void pdc_20621_init(struct ata_probe_ent *pe)
1294 {
1295         u32 tmp;
1296         void __iomem *mmio = pe->mmio_base;
1297
1298         /* hard-code chip #0 */
1299         mmio += PDC_CHIP0_OFS;
1300
1301         /*
1302          * Select page 0x40 for our 32k DIMM window
1303          */
1304         tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1305         tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1306         writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1307
1308         /*
1309          * Reset Host DMA
1310          */
1311         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1312         tmp |= PDC_RESET;
1313         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1314         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1315
1316         udelay(10);
1317
1318         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1319         tmp &= ~PDC_RESET;
1320         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1321         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1322 }
1323
1324 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1325 {
1326         static int printed_version;
1327         struct ata_probe_ent *probe_ent;
1328         unsigned long base;
1329         void __iomem *mmio_base;
1330         void __iomem *dimm_mmio;
1331         struct pdc_host_priv *hpriv;
1332         unsigned int board_idx = (unsigned int) ent->driver_data;
1333         int rc;
1334
1335         if (!printed_version++)
1336                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1337
1338         rc = pcim_enable_device(pdev);
1339         if (rc)
1340                 return rc;
1341
1342         rc = pci_request_regions(pdev, DRV_NAME);
1343         if (rc) {
1344                 pcim_pin_device(pdev);
1345                 return rc;
1346         }
1347
1348         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1349         if (rc)
1350                 return rc;
1351         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1352         if (rc)
1353                 return rc;
1354
1355         probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
1356         if (probe_ent == NULL)
1357                 return -ENOMEM;
1358
1359         probe_ent->dev = pci_dev_to_dev(pdev);
1360         INIT_LIST_HEAD(&probe_ent->node);
1361
1362         mmio_base = pcim_iomap(pdev, 3, 0);
1363         if (mmio_base == NULL)
1364                 return -ENOMEM;
1365         base = (unsigned long) mmio_base;
1366
1367         hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1368         if (!hpriv)
1369                 return -ENOMEM;
1370
1371         dimm_mmio = pcim_iomap(pdev, 4, 0);
1372         if (!dimm_mmio)
1373                 return -ENOMEM;
1374
1375         hpriv->dimm_mmio = dimm_mmio;
1376
1377         probe_ent->sht          = pdc_port_info[board_idx].sht;
1378         probe_ent->port_flags   = pdc_port_info[board_idx].flags;
1379         probe_ent->pio_mask     = pdc_port_info[board_idx].pio_mask;
1380         probe_ent->mwdma_mask   = pdc_port_info[board_idx].mwdma_mask;
1381         probe_ent->udma_mask    = pdc_port_info[board_idx].udma_mask;
1382         probe_ent->port_ops     = pdc_port_info[board_idx].port_ops;
1383
1384         probe_ent->irq = pdev->irq;
1385         probe_ent->irq_flags = IRQF_SHARED;
1386         probe_ent->mmio_base = mmio_base;
1387
1388         probe_ent->private_data = hpriv;
1389         base += PDC_CHIP0_OFS;
1390
1391         probe_ent->n_ports = 4;
1392         pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1393         pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1394         pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1395         pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1396
1397         pci_set_master(pdev);
1398
1399         /* initialize adapter */
1400         /* initialize local dimm */
1401         if (pdc20621_dimm_init(probe_ent))
1402                 return -ENOMEM;
1403         pdc_20621_init(probe_ent);
1404
1405         if (!ata_device_add(probe_ent))
1406                 return -ENODEV;
1407
1408         devm_kfree(&pdev->dev, probe_ent);
1409         return 0;
1410 }
1411
1412
1413 static int __init pdc_sata_init(void)
1414 {
1415         return pci_register_driver(&pdc_sata_pci_driver);
1416 }
1417
1418
1419 static void __exit pdc_sata_exit(void)
1420 {
1421         pci_unregister_driver(&pdc_sata_pci_driver);
1422 }
1423
1424
1425 MODULE_AUTHOR("Jeff Garzik");
1426 MODULE_DESCRIPTION("Promise SATA low-level driver");
1427 MODULE_LICENSE("GPL");
1428 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1429 MODULE_VERSION(DRV_VERSION);
1430
1431 module_init(pdc_sata_init);
1432 module_exit(pdc_sata_exit);