2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public License
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
22 * Hardware information only available under NDA.
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <scsi/scsi.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
37 #define DRV_NAME "pata_pdc2027x"
38 #define DRV_VERSION "0.74-ac5"
42 #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
44 #define PDPRINTK(fmt, args...)
51 PDC_100_MHZ = 100000000,
52 PDC_133_MHZ = 133333333,
56 PDC_GLOBAL_CTL = 0x1108,
59 PDC_BYTE_COUNT = 0x1120,
63 static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
64 static void pdc2027x_error_handler(struct ata_port *ap);
65 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
66 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
67 static void pdc2027x_post_set_mode(struct ata_port *ap);
68 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
71 * ATA Timing Tables based on 133MHz controller clock.
72 * These tables are only used when the controller is in 133MHz clock.
73 * If the controller is in 100MHz clock, the ASIC hardware will
74 * set the timing registers automatically when "set feature" command
75 * is issued to the device. However, if the controller clock is 133MHz,
76 * the following tables must be used.
78 static struct pdc2027x_pio_timing {
79 u8 value0, value1, value2;
80 } pdc2027x_pio_timing_tbl [] = {
81 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
82 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
83 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
84 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
85 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
88 static struct pdc2027x_mdma_timing {
90 } pdc2027x_mdma_timing_tbl [] = {
91 { 0xdf, 0x5f }, /* MDMA mode 0 */
92 { 0x6b, 0x27 }, /* MDMA mode 1 */
93 { 0x69, 0x25 }, /* MDMA mode 2 */
96 static struct pdc2027x_udma_timing {
97 u8 value0, value1, value2;
98 } pdc2027x_udma_timing_tbl [] = {
99 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
100 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
101 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
102 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
103 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
104 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
105 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
108 static const struct pci_device_id pdc2027x_pci_tbl[] = {
109 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
110 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
111 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
112 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
113 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
117 { } /* terminate list */
120 static struct pci_driver pdc2027x_pci_driver = {
122 .id_table = pdc2027x_pci_tbl,
123 .probe = pdc2027x_init_one,
124 .remove = ata_pci_remove_one,
127 static struct scsi_host_template pdc2027x_sht = {
128 .module = THIS_MODULE,
130 .ioctl = ata_scsi_ioctl,
131 .queuecommand = ata_scsi_queuecmd,
132 .can_queue = ATA_DEF_QUEUE,
133 .this_id = ATA_SHT_THIS_ID,
134 .sg_tablesize = LIBATA_MAX_PRD,
135 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
136 .emulated = ATA_SHT_EMULATED,
137 .use_clustering = ATA_SHT_USE_CLUSTERING,
138 .proc_name = DRV_NAME,
139 .dma_boundary = ATA_DMA_BOUNDARY,
140 .slave_configure = ata_scsi_slave_config,
141 .slave_destroy = ata_scsi_slave_destroy,
142 .bios_param = ata_std_bios_param,
145 static struct ata_port_operations pdc2027x_pata100_ops = {
146 .port_disable = ata_port_disable,
148 .tf_load = ata_tf_load,
149 .tf_read = ata_tf_read,
150 .check_status = ata_check_status,
151 .exec_command = ata_exec_command,
152 .dev_select = ata_std_dev_select,
154 .check_atapi_dma = pdc2027x_check_atapi_dma,
155 .bmdma_setup = ata_bmdma_setup,
156 .bmdma_start = ata_bmdma_start,
157 .bmdma_stop = ata_bmdma_stop,
158 .bmdma_status = ata_bmdma_status,
159 .qc_prep = ata_qc_prep,
160 .qc_issue = ata_qc_issue_prot,
161 .data_xfer = ata_mmio_data_xfer,
163 .freeze = ata_bmdma_freeze,
164 .thaw = ata_bmdma_thaw,
165 .error_handler = pdc2027x_error_handler,
166 .post_internal_cmd = ata_bmdma_post_internal_cmd,
168 .irq_handler = ata_interrupt,
169 .irq_clear = ata_bmdma_irq_clear,
171 .port_start = ata_port_start,
174 static struct ata_port_operations pdc2027x_pata133_ops = {
175 .port_disable = ata_port_disable,
176 .set_piomode = pdc2027x_set_piomode,
177 .set_dmamode = pdc2027x_set_dmamode,
178 .post_set_mode = pdc2027x_post_set_mode,
180 .tf_load = ata_tf_load,
181 .tf_read = ata_tf_read,
182 .check_status = ata_check_status,
183 .exec_command = ata_exec_command,
184 .dev_select = ata_std_dev_select,
186 .check_atapi_dma = pdc2027x_check_atapi_dma,
187 .bmdma_setup = ata_bmdma_setup,
188 .bmdma_start = ata_bmdma_start,
189 .bmdma_stop = ata_bmdma_stop,
190 .bmdma_status = ata_bmdma_status,
191 .qc_prep = ata_qc_prep,
192 .qc_issue = ata_qc_issue_prot,
193 .data_xfer = ata_mmio_data_xfer,
195 .freeze = ata_bmdma_freeze,
196 .thaw = ata_bmdma_thaw,
197 .error_handler = pdc2027x_error_handler,
198 .post_internal_cmd = ata_bmdma_post_internal_cmd,
200 .irq_handler = ata_interrupt,
201 .irq_clear = ata_bmdma_irq_clear,
203 .port_start = ata_port_start,
206 static struct ata_port_info pdc2027x_port_info[] = {
209 .sht = &pdc2027x_sht,
210 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
212 .pio_mask = 0x1f, /* pio0-4 */
213 .mwdma_mask = 0x07, /* mwdma0-2 */
214 .udma_mask = ATA_UDMA5, /* udma0-5 */
215 .port_ops = &pdc2027x_pata100_ops,
219 .sht = &pdc2027x_sht,
220 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
222 .pio_mask = 0x1f, /* pio0-4 */
223 .mwdma_mask = 0x07, /* mwdma0-2 */
224 .udma_mask = ATA_UDMA6, /* udma0-6 */
225 .port_ops = &pdc2027x_pata133_ops,
229 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
230 MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
231 MODULE_LICENSE("GPL");
232 MODULE_VERSION(DRV_VERSION);
233 MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
236 * port_mmio - Get the MMIO address of PDC2027x extended registers
238 * @offset: offset from mmio base
240 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
242 return ap->host->mmio_base + ap->port_no * 0x100 + offset;
246 * dev_mmio - Get the MMIO address of PDC2027x extended registers
249 * @offset: offset from mmio base
251 static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
253 u8 adj = (adev->devno) ? 0x08 : 0x00;
254 return port_mmio(ap, offset) + adj;
258 * pdc2027x_pata_cbl_detect - Probe host controller cable detect info
259 * @ap: Port for which cable detect info is desired
261 * Read 80c cable indicator from Promise extended register.
262 * This register is latched when the system is reset.
265 * None (inherited from caller).
267 static void pdc2027x_cbl_detect(struct ata_port *ap)
271 /* check cable detect results */
272 cgcr = readl(port_mmio(ap, PDC_GLOBAL_CTL));
273 if (cgcr & (1 << 26))
276 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
278 ap->cbl = ATA_CBL_PATA80;
282 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
283 ap->cbl = ATA_CBL_PATA40;
284 ap->udma_mask &= ATA_UDMA_MASK_40C;
288 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
291 static inline int pdc2027x_port_enabled(struct ata_port *ap)
293 return readb(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
297 * pdc2027x_prereset - prereset for PATA host controller
300 * Probeinit including cable detection.
303 * None (inherited from caller).
306 static int pdc2027x_prereset(struct ata_port *ap)
308 /* Check whether port enabled */
309 if (!pdc2027x_port_enabled(ap))
311 pdc2027x_cbl_detect(ap);
312 return ata_std_prereset(ap);
316 * pdc2027x_error_handler - Perform reset on PATA port and classify
319 * Reset PATA phy and classify attached devices.
322 * None (inherited from caller).
325 static void pdc2027x_error_handler(struct ata_port *ap)
327 ata_bmdma_drive_eh(ap, pdc2027x_prereset, ata_std_softreset, NULL, ata_std_postreset);
331 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
332 * @ap: Port to configure
334 * @pio: PIO mode, 0 - 4
336 * Set PIO mode for device.
339 * None (inherited from caller).
342 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
344 unsigned int pio = adev->pio_mode - XFER_PIO_0;
347 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
351 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
356 /* Set the PIO timing registers using value table for 133MHz */
357 PDPRINTK("Set pio regs... \n");
359 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
361 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
362 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
363 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
365 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
367 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
368 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
370 PDPRINTK("Set pio regs done\n");
372 PDPRINTK("Set to pio mode[%u] \n", pio);
376 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
377 * @ap: Port to configure
379 * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
381 * Set UDMA mode for device.
384 * None (inherited from caller).
386 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
388 unsigned int dma_mode = adev->dma_mode;
391 if ((dma_mode >= XFER_UDMA_0) &&
392 (dma_mode <= XFER_UDMA_6)) {
393 /* Set the UDMA timing registers with value table for 133MHz */
394 unsigned int udma_mode = dma_mode & 0x07;
396 if (dma_mode == XFER_UDMA_2) {
399 * If tHOLD is '1', the hardware will add half clock for data hold time.
400 * This code segment seems to be no effect. tHOLD will be overwritten below.
402 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
403 writel(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
406 PDPRINTK("Set udma regs... \n");
408 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
410 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
411 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
412 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
413 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
415 PDPRINTK("Set udma regs done\n");
417 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
419 } else if ((dma_mode >= XFER_MW_DMA_0) &&
420 (dma_mode <= XFER_MW_DMA_2)) {
421 /* Set the MDMA timing registers with value table for 133MHz */
422 unsigned int mdma_mode = dma_mode & 0x07;
424 PDPRINTK("Set mdma regs... \n");
425 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
428 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
429 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
431 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
432 PDPRINTK("Set mdma regs done\n");
434 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
436 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
441 * pdc2027x_post_set_mode - Set the timing registers back to correct values.
442 * @ap: Port to configure
444 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
445 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
446 * This function overwrites the possibly incorrect values set by the hardware to be correct.
448 static void pdc2027x_post_set_mode(struct ata_port *ap)
452 for (i = 0; i < ATA_MAX_DEVICES; i++) {
453 struct ata_device *dev = &ap->device[i];
455 if (ata_dev_enabled(dev)) {
457 pdc2027x_set_piomode(ap, dev);
460 * Enable prefetch if the device support PIO only.
462 if (dev->xfer_shift == ATA_SHIFT_PIO) {
463 u32 ctcr1 = readl(dev_mmio(ap, dev, PDC_CTCR1));
465 writel(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
467 PDPRINTK("Turn on prefetch\n");
469 pdc2027x_set_dmamode(ap, dev);
476 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
477 * @qc: Metadata associated with taskfile to check
480 * None (inherited from caller).
482 * RETURNS: 0 when ATAPI DMA can be used
485 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
487 struct scsi_cmnd *cmd = qc->scsicmd;
488 u8 *scsicmd = cmd->cmnd;
489 int rc = 1; /* atapi dma off by default */
492 * This workaround is from Promise's GPL driver.
493 * If ATAPI DMA is used for commands not in the
494 * following white list, say MODE_SENSE and REQUEST_SENSE,
495 * pdc2027x might hit the irq lost problem.
497 switch (scsicmd[0]) {
504 case 0xad: /* READ_DVD_STRUCTURE */
505 case 0xbe: /* READ_CD */
506 /* ATAPI DMA is ok */
517 * pdc_read_counter - Read the ctr counter
518 * @probe_ent: for the port address
521 static long pdc_read_counter(struct ata_probe_ent *probe_ent)
525 u32 bccrl, bccrh, bccrlv, bccrhv;
528 bccrl = readl(probe_ent->mmio_base + PDC_BYTE_COUNT) & 0xffff;
529 bccrh = readl(probe_ent->mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff;
532 /* Read the counter values again for verification */
533 bccrlv = readl(probe_ent->mmio_base + PDC_BYTE_COUNT) & 0xffff;
534 bccrhv = readl(probe_ent->mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff;
537 counter = (bccrh << 15) | bccrl;
539 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
540 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
543 * The 30-bit decreasing counter are read by 2 pieces.
544 * Incorrect value may be read when both bccrh and bccrl are changing.
545 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
547 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
549 PDPRINTK("rereading counter\n");
557 * adjust_pll - Adjust the PLL input clock in Hz.
559 * @pdc_controller: controller specific information
560 * @probe_ent: For the port address
561 * @pll_clock: The input of PLL in HZ
563 static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsigned int board_idx)
567 long pll_clock_khz = pll_clock / 1000;
568 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
569 long ratio = pout_required / pll_clock_khz;
573 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
574 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
579 PDPRINTK("pout_required is %ld\n", pout_required);
581 /* Show the current clock value of PLL control register
582 * (maybe already configured by the firmware)
584 pll_ctl = readw(probe_ent->mmio_base + PDC_PLL_CTL);
586 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
590 * Calculate the ratio of F, R and OD
591 * POUT = (F + 2) / (( R + 2) * NO)
593 if (ratio < 8600L) { /* 8.6x */
594 /* Using NO = 0x01, R = 0x0D */
596 } else if (ratio < 12900L) { /* 12.9x */
597 /* Using NO = 0x01, R = 0x08 */
599 } else if (ratio < 16100L) { /* 16.1x */
600 /* Using NO = 0x01, R = 0x06 */
602 } else if (ratio < 64000L) { /* 64x */
606 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
610 F = (ratio * (R+2)) / 1000 - 2;
612 if (unlikely(F < 0 || F > 127)) {
614 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
618 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
620 pll_ctl = (R << 8) | F;
622 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
624 writew(pll_ctl, probe_ent->mmio_base + PDC_PLL_CTL);
625 readw(probe_ent->mmio_base + PDC_PLL_CTL); /* flush */
627 /* Wait the PLL circuit to be stable */
632 * Show the current clock value of PLL control register
633 * (maybe configured by the firmware)
635 pll_ctl = readw(probe_ent->mmio_base + PDC_PLL_CTL);
637 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
644 * detect_pll_input_clock - Detect the PLL input clock in Hz.
645 * @probe_ent: for the port address
646 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
647 * Half of the PCI clock.
649 static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent)
652 long start_count, end_count;
655 /* Read current counter value */
656 start_count = pdc_read_counter(probe_ent);
658 /* Start the test mode */
659 scr = readl(probe_ent->mmio_base + PDC_SYS_CTL);
660 PDPRINTK("scr[%X]\n", scr);
661 writel(scr | (0x01 << 14), probe_ent->mmio_base + PDC_SYS_CTL);
662 readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */
664 /* Let the counter run for 100 ms. */
667 /* Read the counter values again */
668 end_count = pdc_read_counter(probe_ent);
670 /* Stop the test mode */
671 scr = readl(probe_ent->mmio_base + PDC_SYS_CTL);
672 PDPRINTK("scr[%X]\n", scr);
673 writel(scr & ~(0x01 << 14), probe_ent->mmio_base + PDC_SYS_CTL);
674 readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */
676 /* calculate the input clock in Hz */
677 pll_clock = (start_count - end_count) * 10;
679 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
680 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
686 * pdc_hardware_init - Initialize the hardware.
687 * @pdev: instance of pci_dev found
688 * @pdc_controller: controller specific information
689 * @pe: for the port address
691 static int pdc_hardware_init(struct pci_dev *pdev, struct ata_probe_ent *pe, unsigned int board_idx)
696 * Detect PLL input clock rate.
697 * On some system, where PCI bus is running at non-standard clock rate.
698 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
699 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
701 pll_clock = pdc_detect_pll_input_clock(pe);
703 if (pll_clock < 0) /* counter overflow? Try again. */
704 pll_clock = pdc_detect_pll_input_clock(pe);
706 dev_printk(KERN_INFO, &pdev->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
708 /* Adjust PLL control register */
709 pdc_adjust_pll(pe, pll_clock, board_idx);
715 * pdc_ata_setup_port - setup the mmio address
716 * @port: ata ioports to setup
717 * @base: base address
719 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
722 port->data_addr = base;
724 port->error_addr = base + 0x05;
725 port->nsect_addr = base + 0x0a;
726 port->lbal_addr = base + 0x0f;
727 port->lbam_addr = base + 0x10;
728 port->lbah_addr = base + 0x15;
729 port->device_addr = base + 0x1a;
731 port->status_addr = base + 0x1f;
732 port->altstatus_addr =
733 port->ctl_addr = base + 0x81a;
737 * pdc2027x_init_one - PCI probe function
738 * Called when an instance of PCI adapter is inserted.
739 * This function checks whether the hardware is supported,
740 * initialize hardware and register an instance of ata_host to
741 * libata by providing struct ata_probe_ent and ata_device_add().
742 * (implements struct pci_driver.probe() )
744 * @pdev: instance of pci_dev found
745 * @ent: matching entry in the id_tbl[]
747 static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
749 static int printed_version;
750 unsigned int board_idx = (unsigned int) ent->driver_data;
752 struct ata_probe_ent *probe_ent;
754 void __iomem *mmio_base;
757 if (!printed_version++)
758 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
760 rc = pcim_enable_device(pdev);
764 rc = pci_request_regions(pdev, DRV_NAME);
768 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
772 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
776 /* Prepare the probe entry */
777 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
778 if (probe_ent == NULL)
781 probe_ent->dev = pci_dev_to_dev(pdev);
782 INIT_LIST_HEAD(&probe_ent->node);
784 mmio_base = pcim_iomap(pdev, 5, 0);
788 base = (unsigned long) mmio_base;
790 probe_ent->sht = pdc2027x_port_info[board_idx].sht;
791 probe_ent->port_flags = pdc2027x_port_info[board_idx].flags;
792 probe_ent->pio_mask = pdc2027x_port_info[board_idx].pio_mask;
793 probe_ent->mwdma_mask = pdc2027x_port_info[board_idx].mwdma_mask;
794 probe_ent->udma_mask = pdc2027x_port_info[board_idx].udma_mask;
795 probe_ent->port_ops = pdc2027x_port_info[board_idx].port_ops;
797 probe_ent->irq = pdev->irq;
798 probe_ent->irq_flags = SA_SHIRQ;
799 probe_ent->mmio_base = mmio_base;
801 pdc_ata_setup_port(&probe_ent->port[0], base + 0x17c0);
802 probe_ent->port[0].bmdma_addr = base + 0x1000;
803 pdc_ata_setup_port(&probe_ent->port[1], base + 0x15c0);
804 probe_ent->port[1].bmdma_addr = base + 0x1008;
806 probe_ent->n_ports = 2;
808 pci_set_master(pdev);
809 //pci_enable_intx(pdev);
811 /* initialize adapter */
812 if (pdc_hardware_init(pdev, probe_ent, board_idx) != 0)
815 if (!ata_device_add(probe_ent))
818 devm_kfree(&pdev->dev, probe_ent);
823 * pdc2027x_init - Called after this module is loaded into the kernel.
825 static int __init pdc2027x_init(void)
827 return pci_register_driver(&pdc2027x_pci_driver);
831 * pdc2027x_exit - Called before this module unloaded from the kernel
833 static void __exit pdc2027x_exit(void)
835 pci_unregister_driver(&pdc2027x_pci_driver);
838 module_init(pdc2027x_init);
839 module_exit(pdc2027x_exit);