2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
69 /* board IDs for specific chipsets in alphabetical order */
76 board_ahci_sb700, /* for SB700 and SB800 */
80 board_ahci_mcp_linux = board_ahci_mcp65,
81 board_ahci_mcp67 = board_ahci_mcp65,
82 board_ahci_mcp73 = board_ahci_mcp65,
83 board_ahci_mcp79 = board_ahci_mcp77,
86 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
87 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
94 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
95 static int ahci_pci_device_resume(struct pci_dev *pdev);
98 static struct scsi_host_template ahci_sht = {
102 static struct ata_port_operations ahci_vt8251_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_vt8251_hardreset,
107 static struct ata_port_operations ahci_p5wdh_ops = {
108 .inherits = &ahci_ops,
109 .hardreset = ahci_p5wdh_hardreset,
112 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114 static struct ata_port_operations ahci_avn_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_avn_hardreset,
119 static const struct ata_port_info ahci_port_info[] = {
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
128 [board_ahci_ign_iferr] =
130 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
136 [board_ahci_nomsi] = {
137 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
138 .flags = AHCI_FLAG_COMMON,
139 .pio_mask = ATA_PIO4,
140 .udma_mask = ATA_UDMA6,
141 .port_ops = &ahci_ops,
143 [board_ahci_noncq] = {
144 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
150 [board_ahci_nosntf] =
152 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
158 [board_ahci_yes_fbs] =
160 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
168 .flags = AHCI_FLAG_COMMON,
169 .pio_mask = ATA_PIO4,
170 .udma_mask = ATA_UDMA6,
171 .port_ops = &ahci_avn_ops,
175 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
177 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
178 .pio_mask = ATA_PIO4,
179 .udma_mask = ATA_UDMA6,
180 .port_ops = &ahci_ops,
184 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
188 .port_ops = &ahci_ops,
192 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
193 .flags = AHCI_FLAG_COMMON,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_ops,
200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
201 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
202 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_ops,
209 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
210 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
211 AHCI_HFLAG_32BIT_ONLY),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_pmp_retry_srst_ops,
217 [board_ahci_sb700] = /* for SB700 and SB800 */
219 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_pmp_retry_srst_ops,
225 [board_ahci_vt8251] =
227 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
228 .flags = AHCI_FLAG_COMMON,
229 .pio_mask = ATA_PIO4,
230 .udma_mask = ATA_UDMA6,
231 .port_ops = &ahci_vt8251_ops,
235 static const struct pci_device_id ahci_pci_tbl[] = {
237 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
238 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
239 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
240 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
241 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
242 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
243 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
244 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
245 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
246 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
247 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
248 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
249 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
250 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
251 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
252 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
254 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
255 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
256 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
257 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
258 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
259 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
260 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
261 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
262 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
263 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
264 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
265 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
266 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
267 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
268 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
269 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
270 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
271 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
272 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
273 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
274 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
275 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
276 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
277 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
278 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
279 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
280 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
281 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
282 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
283 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
284 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
285 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
286 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
287 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
288 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
289 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
290 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
291 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
292 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
293 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
294 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
295 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
296 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
297 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
298 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
299 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
300 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
301 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
302 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
303 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
304 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
305 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
307 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
308 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
309 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
310 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
311 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
312 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
313 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
314 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
315 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
316 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
317 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
318 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
319 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
320 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
321 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
322 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
323 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
324 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
325 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
326 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
327 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
328 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
329 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
330 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
331 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
332 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
333 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
334 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
335 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
336 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
337 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
338 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
339 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
341 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
342 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
343 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
344 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
345 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
346 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
347 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
348 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
349 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
350 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
351 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
352 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
353 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
354 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
355 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
356 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
358 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
359 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
360 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
361 /* JMicron 362B and 362C have an AHCI function with IDE class code */
362 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
363 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
366 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
367 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
368 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
369 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
370 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
371 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
372 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
375 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
376 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
377 /* AMD is using RAID class only for ahci controllers */
378 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
379 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
382 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
383 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
386 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
387 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
388 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
389 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
390 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
391 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
392 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
393 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
394 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
395 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
396 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
397 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
398 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
399 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
400 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
401 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
402 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
403 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
404 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
405 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
406 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
407 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
408 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
409 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
410 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
411 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
412 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
413 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
414 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
415 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
416 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
417 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
418 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
419 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
420 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
421 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
422 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
423 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
424 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
425 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
426 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
427 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
428 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
429 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
430 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
431 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
432 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
433 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
434 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
435 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
436 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
437 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
438 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
439 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
440 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
441 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
442 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
443 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
444 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
445 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
446 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
447 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
448 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
449 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
450 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
451 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
452 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
453 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
454 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
455 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
456 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
457 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
458 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
459 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
460 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
461 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
462 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
463 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
464 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
465 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
466 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
467 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
468 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
469 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
472 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
473 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
474 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
476 /* ST Microelectronics */
477 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
480 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
481 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
482 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
483 .class = PCI_CLASS_STORAGE_SATA_AHCI,
484 .class_mask = 0xffffff,
485 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
486 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
487 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
488 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
489 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
490 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
491 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
492 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
493 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
494 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
495 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
496 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
497 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
498 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
499 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
500 .driver_data = board_ahci_yes_fbs },
501 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
502 .driver_data = board_ahci_yes_fbs },
503 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
504 .driver_data = board_ahci_yes_fbs },
505 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
506 .driver_data = board_ahci_yes_fbs },
507 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
508 .driver_data = board_ahci_yes_fbs },
511 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
512 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
515 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
516 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
517 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
518 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
521 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
522 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
524 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
525 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
528 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
530 /* Generic, PCI class code for AHCI */
531 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
532 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
534 { } /* terminate list */
538 static struct pci_driver ahci_pci_driver = {
540 .id_table = ahci_pci_tbl,
541 .probe = ahci_init_one,
542 .remove = ata_pci_remove_one,
544 .suspend = ahci_pci_device_suspend,
545 .resume = ahci_pci_device_resume,
549 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
550 static int marvell_enable;
552 static int marvell_enable = 1;
554 module_param(marvell_enable, int, 0644);
555 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
558 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
559 struct ahci_host_priv *hpriv)
561 unsigned int force_port_map = 0;
562 unsigned int mask_port_map = 0;
564 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
565 dev_info(&pdev->dev, "JMB361 has only one port\n");
570 * Temporary Marvell 6145 hack: PATA port presence
571 * is asserted through the standard AHCI port
572 * presence register, as bit 4 (counting from 0)
574 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
575 if (pdev->device == 0x6121)
580 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
583 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
587 static int ahci_pci_reset_controller(struct ata_host *host)
589 struct pci_dev *pdev = to_pci_dev(host->dev);
591 ahci_reset_controller(host);
593 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
594 struct ahci_host_priv *hpriv = host->private_data;
598 pci_read_config_word(pdev, 0x92, &tmp16);
599 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
600 tmp16 |= hpriv->port_map;
601 pci_write_config_word(pdev, 0x92, tmp16);
608 static void ahci_pci_init_controller(struct ata_host *host)
610 struct ahci_host_priv *hpriv = host->private_data;
611 struct pci_dev *pdev = to_pci_dev(host->dev);
612 void __iomem *port_mmio;
616 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
617 if (pdev->device == 0x6121)
621 port_mmio = __ahci_port_base(host, mv);
623 writel(0, port_mmio + PORT_IRQ_MASK);
626 tmp = readl(port_mmio + PORT_IRQ_STAT);
627 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
629 writel(tmp, port_mmio + PORT_IRQ_STAT);
632 ahci_init_controller(host);
635 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
636 unsigned long deadline)
638 struct ata_port *ap = link->ap;
644 ahci_stop_engine(ap);
646 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
647 deadline, &online, NULL);
649 ahci_start_engine(ap);
651 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
653 /* vt8251 doesn't clear BSY on signature FIS reception,
654 * request follow-up softreset.
656 return online ? -EAGAIN : rc;
659 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
660 unsigned long deadline)
662 struct ata_port *ap = link->ap;
663 struct ahci_port_priv *pp = ap->private_data;
664 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
665 struct ata_taskfile tf;
669 ahci_stop_engine(ap);
671 /* clear D2H reception area to properly wait for D2H FIS */
672 ata_tf_init(link->device, &tf);
674 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
676 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
677 deadline, &online, NULL);
679 ahci_start_engine(ap);
681 /* The pseudo configuration device on SIMG4726 attached to
682 * ASUS P5W-DH Deluxe doesn't send signature FIS after
683 * hardreset if no device is attached to the first downstream
684 * port && the pseudo device locks up on SRST w/ PMP==0. To
685 * work around this, wait for !BSY only briefly. If BSY isn't
686 * cleared, perform CLO and proceed to IDENTIFY (achieved by
687 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
689 * Wait for two seconds. Devices attached to downstream port
690 * which can't process the following IDENTIFY after this will
691 * have to be reset again. For most cases, this should
692 * suffice while making probing snappish enough.
695 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
698 ahci_kick_engine(ap);
704 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
706 * It has been observed with some SSDs that the timing of events in the
707 * link synchronization phase can leave the port in a state that can not
708 * be recovered by a SATA-hard-reset alone. The failing signature is
709 * SStatus.DET stuck at 1 ("Device presence detected but Phy
710 * communication not established"). It was found that unloading and
711 * reloading the driver when this problem occurs allows the drive
712 * connection to be recovered (DET advanced to 0x3). The critical
713 * component of reloading the driver is that the port state machines are
714 * reset by bouncing "port enable" in the AHCI PCS configuration
715 * register. So, reproduce that effect by bouncing a port whenever we
716 * see DET==1 after a reset.
718 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
719 unsigned long deadline)
721 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
722 struct ata_port *ap = link->ap;
723 struct ahci_port_priv *pp = ap->private_data;
724 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
725 unsigned long tmo = deadline - jiffies;
726 struct ata_taskfile tf;
732 ahci_stop_engine(ap);
734 for (i = 0; i < 2; i++) {
737 int port = ap->port_no;
738 struct ata_host *host = ap->host;
739 struct pci_dev *pdev = to_pci_dev(host->dev);
741 /* clear D2H reception area to properly wait for D2H FIS */
742 ata_tf_init(link->device, &tf);
743 tf.command = ATA_BUSY;
744 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
746 rc = sata_link_hardreset(link, timing, deadline, &online,
749 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
750 (sstatus & 0xf) != 1)
753 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
756 pci_read_config_word(pdev, 0x92, &val);
758 pci_write_config_word(pdev, 0x92, val);
759 ata_msleep(ap, 1000);
761 pci_write_config_word(pdev, 0x92, val);
765 ahci_start_engine(ap);
768 *class = ahci_dev_classify(ap);
770 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
776 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
778 struct ata_host *host = dev_get_drvdata(&pdev->dev);
779 struct ahci_host_priv *hpriv = host->private_data;
780 void __iomem *mmio = hpriv->mmio;
783 if (mesg.event & PM_EVENT_SUSPEND &&
784 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
786 "BIOS update required for suspend/resume\n");
790 if (mesg.event & PM_EVENT_SLEEP) {
791 /* AHCI spec rev1.1 section 8.3.3:
792 * Software must disable interrupts prior to requesting a
793 * transition of the HBA to D3 state.
795 ctl = readl(mmio + HOST_CTL);
797 writel(ctl, mmio + HOST_CTL);
798 readl(mmio + HOST_CTL); /* flush */
801 return ata_pci_device_suspend(pdev, mesg);
804 static int ahci_pci_device_resume(struct pci_dev *pdev)
806 struct ata_host *host = dev_get_drvdata(&pdev->dev);
809 rc = ata_pci_device_do_resume(pdev);
813 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
814 rc = ahci_pci_reset_controller(host);
818 ahci_pci_init_controller(host);
821 ata_host_resume(host);
827 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
832 * If the device fixup already set the dma_mask to some non-standard
833 * value, don't extend it here. This happens on STA2X11, for example.
835 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
839 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
840 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
842 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
845 "64-bit DMA enable failed\n");
850 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
852 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
855 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
858 "32-bit consistent DMA enable failed\n");
865 static void ahci_pci_print_info(struct ata_host *host)
867 struct pci_dev *pdev = to_pci_dev(host->dev);
871 pci_read_config_word(pdev, 0x0a, &cc);
872 if (cc == PCI_CLASS_STORAGE_IDE)
874 else if (cc == PCI_CLASS_STORAGE_SATA)
876 else if (cc == PCI_CLASS_STORAGE_RAID)
881 ahci_print_info(host, scc_s);
884 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
885 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
886 * support PMP and the 4726 either directly exports the device
887 * attached to the first downstream port or acts as a hardware storage
888 * controller and emulate a single ATA device (can be RAID 0/1 or some
889 * other configuration).
891 * When there's no device attached to the first downstream port of the
892 * 4726, "Config Disk" appears, which is a pseudo ATA device to
893 * configure the 4726. However, ATA emulation of the device is very
894 * lame. It doesn't send signature D2H Reg FIS after the initial
895 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
897 * The following function works around the problem by always using
898 * hardreset on the port and not depending on receiving signature FIS
899 * afterward. If signature FIS isn't received soon, ATA class is
900 * assumed without follow-up softreset.
902 static void ahci_p5wdh_workaround(struct ata_host *host)
904 static struct dmi_system_id sysids[] = {
906 .ident = "P5W DH Deluxe",
908 DMI_MATCH(DMI_SYS_VENDOR,
909 "ASUSTEK COMPUTER INC"),
910 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
915 struct pci_dev *pdev = to_pci_dev(host->dev);
917 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
918 dmi_check_system(sysids)) {
919 struct ata_port *ap = host->ports[1];
922 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
924 ap->ops = &ahci_p5wdh_ops;
925 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
929 /* only some SB600 ahci controllers can do 64bit DMA */
930 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
932 static const struct dmi_system_id sysids[] = {
934 * The oldest version known to be broken is 0901 and
935 * working is 1501 which was released on 2007-10-26.
936 * Enable 64bit DMA on 1501 and anything newer.
938 * Please read bko#9412 for more info.
941 .ident = "ASUS M2A-VM",
943 DMI_MATCH(DMI_BOARD_VENDOR,
944 "ASUSTeK Computer INC."),
945 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
947 .driver_data = "20071026", /* yyyymmdd */
950 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
953 * BIOS versions earlier than 1.5 had the Manufacturer DMI
954 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
955 * This spelling mistake was fixed in BIOS version 1.5, so
956 * 1.5 and later have the Manufacturer as
957 * "MICRO-STAR INTERNATIONAL CO.,LTD".
958 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
960 * BIOS versions earlier than 1.9 had a Board Product Name
961 * DMI field of "MS-7376". This was changed to be
962 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
963 * match on DMI_BOARD_NAME of "MS-7376".
966 .ident = "MSI K9A2 Platinum",
968 DMI_MATCH(DMI_BOARD_VENDOR,
970 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
974 * All BIOS versions for the Asus M3A support 64bit DMA.
975 * (all release versions from 0301 to 1206 were tested)
980 DMI_MATCH(DMI_BOARD_VENDOR,
981 "ASUSTeK Computer INC."),
982 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
987 const struct dmi_system_id *match;
988 int year, month, date;
991 match = dmi_first_match(sysids);
992 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
996 if (!match->driver_data)
999 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1000 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1002 if (strcmp(buf, match->driver_data) >= 0)
1005 dev_warn(&pdev->dev,
1006 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1012 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1016 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1018 static const struct dmi_system_id broken_systems[] = {
1020 .ident = "HP Compaq nx6310",
1022 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1023 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1025 /* PCI slot number of the controller */
1026 .driver_data = (void *)0x1FUL,
1029 .ident = "HP Compaq 6720s",
1031 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1032 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1034 /* PCI slot number of the controller */
1035 .driver_data = (void *)0x1FUL,
1038 { } /* terminate list */
1040 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1043 unsigned long slot = (unsigned long)dmi->driver_data;
1044 /* apply the quirk only to on-board controllers */
1045 return slot == PCI_SLOT(pdev->devfn);
1051 static bool ahci_broken_suspend(struct pci_dev *pdev)
1053 static const struct dmi_system_id sysids[] = {
1055 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1056 * to the harddisk doesn't become online after
1057 * resuming from STR. Warn and fail suspend.
1059 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1061 * Use dates instead of versions to match as HP is
1062 * apparently recycling both product and version
1065 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1070 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1071 DMI_MATCH(DMI_PRODUCT_NAME,
1072 "HP Pavilion dv4 Notebook PC"),
1074 .driver_data = "20090105", /* F.30 */
1079 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1080 DMI_MATCH(DMI_PRODUCT_NAME,
1081 "HP Pavilion dv5 Notebook PC"),
1083 .driver_data = "20090506", /* F.16 */
1088 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1089 DMI_MATCH(DMI_PRODUCT_NAME,
1090 "HP Pavilion dv6 Notebook PC"),
1092 .driver_data = "20090423", /* F.21 */
1097 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1098 DMI_MATCH(DMI_PRODUCT_NAME,
1099 "HP HDX18 Notebook PC"),
1101 .driver_data = "20090430", /* F.23 */
1104 * Acer eMachines G725 has the same problem. BIOS
1105 * V1.03 is known to be broken. V3.04 is known to
1106 * work. Between, there are V1.06, V2.06 and V3.03
1107 * that we don't have much idea about. For now,
1108 * blacklist anything older than V3.04.
1110 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1115 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1116 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1118 .driver_data = "20091216", /* V3.04 */
1120 { } /* terminate list */
1122 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1123 int year, month, date;
1126 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1129 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1130 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1132 return strcmp(buf, dmi->driver_data) < 0;
1135 static bool ahci_broken_online(struct pci_dev *pdev)
1137 #define ENCODE_BUSDEVFN(bus, slot, func) \
1138 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1139 static const struct dmi_system_id sysids[] = {
1141 * There are several gigabyte boards which use
1142 * SIMG5723s configured as hardware RAID. Certain
1143 * 5723 firmware revisions shipped there keep the link
1144 * online but fail to answer properly to SRST or
1145 * IDENTIFY when no device is attached downstream
1146 * causing libata to retry quite a few times leading
1147 * to excessive detection delay.
1149 * As these firmwares respond to the second reset try
1150 * with invalid device signature, considering unknown
1151 * sig as offline works around the problem acceptably.
1154 .ident = "EP45-DQ6",
1156 DMI_MATCH(DMI_BOARD_VENDOR,
1157 "Gigabyte Technology Co., Ltd."),
1158 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1160 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1163 .ident = "EP45-DS5",
1165 DMI_MATCH(DMI_BOARD_VENDOR,
1166 "Gigabyte Technology Co., Ltd."),
1167 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1169 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1171 { } /* terminate list */
1173 #undef ENCODE_BUSDEVFN
1174 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1180 val = (unsigned long)dmi->driver_data;
1182 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1185 #ifdef CONFIG_ATA_ACPI
1186 static void ahci_gtf_filter_workaround(struct ata_host *host)
1188 static const struct dmi_system_id sysids[] = {
1190 * Aspire 3810T issues a bunch of SATA enable commands
1191 * via _GTF including an invalid one and one which is
1192 * rejected by the device. Among the successful ones
1193 * is FPDMA non-zero offset enable which when enabled
1194 * only on the drive side leads to NCQ command
1195 * failures. Filter it out.
1198 .ident = "Aspire 3810T",
1200 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1201 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1203 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1207 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1208 unsigned int filter;
1214 filter = (unsigned long)dmi->driver_data;
1215 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1216 filter, dmi->ident);
1218 for (i = 0; i < host->n_ports; i++) {
1219 struct ata_port *ap = host->ports[i];
1220 struct ata_link *link;
1221 struct ata_device *dev;
1223 ata_for_each_link(link, ap, EDGE)
1224 ata_for_each_dev(dev, link, ALL)
1225 dev->gtf_filter |= filter;
1229 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1233 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1235 unsigned int board_id = ent->driver_data;
1236 struct ata_port_info pi = ahci_port_info[board_id];
1237 const struct ata_port_info *ppi[] = { &pi, NULL };
1238 struct device *dev = &pdev->dev;
1239 struct ahci_host_priv *hpriv;
1240 struct ata_host *host;
1242 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1246 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1248 ata_print_version_once(&pdev->dev, DRV_VERSION);
1250 /* The AHCI driver can only drive the SATA ports, the PATA driver
1251 can drive them all so if both drivers are selected make sure
1252 AHCI stays out of the way */
1253 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1257 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1258 * ahci, use ata_generic instead.
1260 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1261 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1262 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1263 pdev->subsystem_device == 0xcb89)
1266 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1267 * At the moment, we can only use the AHCI mode. Let the users know
1268 * that for SAS drives they're out of luck.
1270 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1271 dev_info(&pdev->dev,
1272 "PDC42819 can only drive SATA devices with this driver\n");
1274 /* Both Connext and Enmotus devices use non-standard BARs */
1275 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1276 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1277 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1278 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1280 /* acquire resources */
1281 rc = pcim_enable_device(pdev);
1285 /* AHCI controllers often implement SFF compatible interface.
1286 * Grab all PCI BARs just in case.
1288 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1290 pcim_pin_device(pdev);
1294 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1295 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1298 /* ICH6s share the same PCI ID for both piix and ahci
1299 * modes. Enabling ahci mode while MAP indicates
1300 * combined mode is a bad idea. Yield to ata_piix.
1302 pci_read_config_byte(pdev, ICH_MAP, &map);
1304 dev_info(&pdev->dev,
1305 "controller is in combined mode, can't enable AHCI mode\n");
1310 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1313 hpriv->flags |= (unsigned long)pi.private_data;
1315 /* MCP65 revision A1 and A2 can't do MSI */
1316 if (board_id == board_ahci_mcp65 &&
1317 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1318 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1320 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1321 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1322 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1324 /* only some SB600s can do 64bit DMA */
1325 if (ahci_sb600_enable_64bit(pdev))
1326 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1328 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1331 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1333 /* save initial config */
1334 ahci_pci_save_initial_config(pdev, hpriv);
1337 if (hpriv->cap & HOST_CAP_NCQ) {
1338 pi.flags |= ATA_FLAG_NCQ;
1340 * Auto-activate optimization is supposed to be
1341 * supported on all AHCI controllers indicating NCQ
1342 * capability, but it seems to be broken on some
1343 * chipsets including NVIDIAs.
1345 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1346 pi.flags |= ATA_FLAG_FPDMA_AA;
1349 if (hpriv->cap & HOST_CAP_PMP)
1350 pi.flags |= ATA_FLAG_PMP;
1352 ahci_set_em_messages(hpriv, &pi);
1354 if (ahci_broken_system_poweroff(pdev)) {
1355 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1356 dev_info(&pdev->dev,
1357 "quirky BIOS, skipping spindown on poweroff\n");
1360 if (ahci_broken_suspend(pdev)) {
1361 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1362 dev_warn(&pdev->dev,
1363 "BIOS update required for suspend/resume\n");
1366 if (ahci_broken_online(pdev)) {
1367 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1368 dev_info(&pdev->dev,
1369 "online status unreliable, applying workaround\n");
1372 /* CAP.NP sometimes indicate the index of the last enabled
1373 * port, at other times, that of the last possible port, so
1374 * determining the maximum port number requires looking at
1375 * both CAP.NP and port_map.
1377 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1379 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1382 host->private_data = hpriv;
1384 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1385 host->flags |= ATA_HOST_PARALLEL_SCAN;
1387 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1389 if (pi.flags & ATA_FLAG_EM)
1390 ahci_reset_em(host);
1392 for (i = 0; i < host->n_ports; i++) {
1393 struct ata_port *ap = host->ports[i];
1395 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1396 ata_port_pbar_desc(ap, ahci_pci_bar,
1397 0x100 + ap->port_no * 0x80, "port");
1399 /* set enclosure management message type */
1400 if (ap->flags & ATA_FLAG_EM)
1401 ap->em_message_type = hpriv->em_msg_type;
1404 /* disabled/not-implemented port */
1405 if (!(hpriv->port_map & (1 << i)))
1406 ap->ops = &ata_dummy_port_ops;
1409 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1410 ahci_p5wdh_workaround(host);
1412 /* apply gtf filter quirk */
1413 ahci_gtf_filter_workaround(host);
1415 /* initialize adapter */
1416 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1420 rc = ahci_pci_reset_controller(host);
1424 ahci_pci_init_controller(host);
1425 ahci_pci_print_info(host);
1427 pci_set_master(pdev);
1428 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1432 static int __init ahci_init(void)
1434 return pci_register_driver(&ahci_pci_driver);
1437 static void __exit ahci_exit(void)
1439 pci_unregister_driver(&ahci_pci_driver);
1443 MODULE_AUTHOR("Jeff Garzik");
1444 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1445 MODULE_LICENSE("GPL");
1446 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1447 MODULE_VERSION(DRV_VERSION);
1449 module_init(ahci_init);
1450 module_exit(ahci_exit);