2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
42 #include <asm/perf_event.h>
46 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 #define __ex_clear(x, reg) \
48 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
50 MODULE_AUTHOR("Qumranet");
51 MODULE_LICENSE("GPL");
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
72 static int __read_mostly yield_on_hlt = 1;
73 module_param(yield_on_hlt, bool, S_IRUGO);
75 static int __read_mostly fasteoi = 1;
76 module_param(fasteoi, bool, S_IRUGO);
79 * If nested=1, nested virtualization is supported, i.e., guests may use
80 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
81 * use VMX instructions.
83 static int __read_mostly nested = 0;
84 module_param(nested, bool, S_IRUGO);
86 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
87 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
88 #define KVM_GUEST_CR0_MASK \
89 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
90 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
91 (X86_CR0_WP | X86_CR0_NE)
92 #define KVM_VM_CR0_ALWAYS_ON \
93 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
94 #define KVM_CR4_GUEST_OWNED_BITS \
95 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
98 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
99 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
101 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
104 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
105 * ple_gap: upper bound on the amount of time between two successive
106 * executions of PAUSE in a loop. Also indicate if ple enabled.
107 * According to test, this time is usually smaller than 128 cycles.
108 * ple_window: upper bound on the amount of time a guest is allowed to execute
109 * in a PAUSE loop. Tests indicate that most spinlocks are held for
110 * less than 2^12 cycles
111 * Time is measured based on a counter that runs at the same rate as the TSC,
112 * refer SDM volume 3b section 21.6.13 & 22.1.3.
114 #define KVM_VMX_DEFAULT_PLE_GAP 128
115 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
116 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
117 module_param(ple_gap, int, S_IRUGO);
119 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
120 module_param(ple_window, int, S_IRUGO);
122 #define NR_AUTOLOAD_MSRS 8
123 #define VMCS02_POOL_SIZE 1
132 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
133 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
134 * loaded on this CPU (so we can clear them if the CPU goes down).
140 struct list_head loaded_vmcss_on_cpu_link;
143 struct shared_msr_entry {
150 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
151 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
152 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
153 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
154 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
155 * More than one of these structures may exist, if L1 runs multiple L2 guests.
156 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
157 * underlying hardware which will be used to run L2.
158 * This structure is packed to ensure that its layout is identical across
159 * machines (necessary for live migration).
160 * If there are changes in this struct, VMCS12_REVISION must be changed.
162 typedef u64 natural_width;
163 struct __packed vmcs12 {
164 /* According to the Intel spec, a VMCS region must start with the
165 * following two fields. Then follow implementation-specific data.
170 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
171 u32 padding[7]; /* room for future expansion */
176 u64 vm_exit_msr_store_addr;
177 u64 vm_exit_msr_load_addr;
178 u64 vm_entry_msr_load_addr;
180 u64 virtual_apic_page_addr;
181 u64 apic_access_addr;
183 u64 guest_physical_address;
184 u64 vmcs_link_pointer;
185 u64 guest_ia32_debugctl;
188 u64 guest_ia32_perf_global_ctrl;
195 u64 host_ia32_perf_global_ctrl;
196 u64 padding64[8]; /* room for future expansion */
198 * To allow migration of L1 (complete with its L2 guests) between
199 * machines of different natural widths (32 or 64 bit), we cannot have
200 * unsigned long fields with no explict size. We use u64 (aliased
201 * natural_width) instead. Luckily, x86 is little-endian.
203 natural_width cr0_guest_host_mask;
204 natural_width cr4_guest_host_mask;
205 natural_width cr0_read_shadow;
206 natural_width cr4_read_shadow;
207 natural_width cr3_target_value0;
208 natural_width cr3_target_value1;
209 natural_width cr3_target_value2;
210 natural_width cr3_target_value3;
211 natural_width exit_qualification;
212 natural_width guest_linear_address;
213 natural_width guest_cr0;
214 natural_width guest_cr3;
215 natural_width guest_cr4;
216 natural_width guest_es_base;
217 natural_width guest_cs_base;
218 natural_width guest_ss_base;
219 natural_width guest_ds_base;
220 natural_width guest_fs_base;
221 natural_width guest_gs_base;
222 natural_width guest_ldtr_base;
223 natural_width guest_tr_base;
224 natural_width guest_gdtr_base;
225 natural_width guest_idtr_base;
226 natural_width guest_dr7;
227 natural_width guest_rsp;
228 natural_width guest_rip;
229 natural_width guest_rflags;
230 natural_width guest_pending_dbg_exceptions;
231 natural_width guest_sysenter_esp;
232 natural_width guest_sysenter_eip;
233 natural_width host_cr0;
234 natural_width host_cr3;
235 natural_width host_cr4;
236 natural_width host_fs_base;
237 natural_width host_gs_base;
238 natural_width host_tr_base;
239 natural_width host_gdtr_base;
240 natural_width host_idtr_base;
241 natural_width host_ia32_sysenter_esp;
242 natural_width host_ia32_sysenter_eip;
243 natural_width host_rsp;
244 natural_width host_rip;
245 natural_width paddingl[8]; /* room for future expansion */
246 u32 pin_based_vm_exec_control;
247 u32 cpu_based_vm_exec_control;
248 u32 exception_bitmap;
249 u32 page_fault_error_code_mask;
250 u32 page_fault_error_code_match;
251 u32 cr3_target_count;
252 u32 vm_exit_controls;
253 u32 vm_exit_msr_store_count;
254 u32 vm_exit_msr_load_count;
255 u32 vm_entry_controls;
256 u32 vm_entry_msr_load_count;
257 u32 vm_entry_intr_info_field;
258 u32 vm_entry_exception_error_code;
259 u32 vm_entry_instruction_len;
261 u32 secondary_vm_exec_control;
262 u32 vm_instruction_error;
264 u32 vm_exit_intr_info;
265 u32 vm_exit_intr_error_code;
266 u32 idt_vectoring_info_field;
267 u32 idt_vectoring_error_code;
268 u32 vm_exit_instruction_len;
269 u32 vmx_instruction_info;
276 u32 guest_ldtr_limit;
278 u32 guest_gdtr_limit;
279 u32 guest_idtr_limit;
280 u32 guest_es_ar_bytes;
281 u32 guest_cs_ar_bytes;
282 u32 guest_ss_ar_bytes;
283 u32 guest_ds_ar_bytes;
284 u32 guest_fs_ar_bytes;
285 u32 guest_gs_ar_bytes;
286 u32 guest_ldtr_ar_bytes;
287 u32 guest_tr_ar_bytes;
288 u32 guest_interruptibility_info;
289 u32 guest_activity_state;
290 u32 guest_sysenter_cs;
291 u32 host_ia32_sysenter_cs;
292 u32 padding32[8]; /* room for future expansion */
293 u16 virtual_processor_id;
294 u16 guest_es_selector;
295 u16 guest_cs_selector;
296 u16 guest_ss_selector;
297 u16 guest_ds_selector;
298 u16 guest_fs_selector;
299 u16 guest_gs_selector;
300 u16 guest_ldtr_selector;
301 u16 guest_tr_selector;
302 u16 host_es_selector;
303 u16 host_cs_selector;
304 u16 host_ss_selector;
305 u16 host_ds_selector;
306 u16 host_fs_selector;
307 u16 host_gs_selector;
308 u16 host_tr_selector;
312 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
313 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
314 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
316 #define VMCS12_REVISION 0x11e57ed0
319 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
320 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
321 * current implementation, 4K are reserved to avoid future complications.
323 #define VMCS12_SIZE 0x1000
325 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
327 struct list_head list;
329 struct loaded_vmcs vmcs02;
333 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
334 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
337 /* Has the level1 guest done vmxon? */
340 /* The guest-physical address of the current VMCS L1 keeps for L2 */
342 /* The host-usable pointer to the above */
343 struct page *current_vmcs12_page;
344 struct vmcs12 *current_vmcs12;
346 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
347 struct list_head vmcs02_pool;
349 u64 vmcs01_tsc_offset;
350 /* L2 must run next, and mustn't decide to exit to L1. */
351 bool nested_run_pending;
353 * Guest pages referred to in vmcs02 with host-physical pointers, so
354 * we must keep them pinned while L2 runs.
356 struct page *apic_access_page;
360 struct kvm_vcpu vcpu;
361 unsigned long host_rsp;
364 bool nmi_known_unmasked;
366 u32 idt_vectoring_info;
368 struct shared_msr_entry *guest_msrs;
372 u64 msr_host_kernel_gs_base;
373 u64 msr_guest_kernel_gs_base;
376 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
377 * non-nested (L1) guest, it always points to vmcs01. For a nested
378 * guest (L2), it points to a different VMCS.
380 struct loaded_vmcs vmcs01;
381 struct loaded_vmcs *loaded_vmcs;
382 bool __launched; /* temporary, used in vmx_vcpu_run */
383 struct msr_autoload {
385 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
386 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
390 u16 fs_sel, gs_sel, ldt_sel;
391 int gs_ldt_reload_needed;
392 int fs_reload_needed;
397 struct kvm_save_segment {
402 } tr, es, ds, fs, gs;
405 u32 bitmask; /* 4 bits per segment (1 bit per field) */
406 struct kvm_save_segment seg[8];
409 bool emulation_required;
411 /* Support for vnmi-less CPUs */
412 int soft_vnmi_blocked;
414 s64 vnmi_blocked_time;
419 /* Support for a guest hypervisor (nested VMX) */
420 struct nested_vmx nested;
423 enum segment_cache_field {
432 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
434 return container_of(vcpu, struct vcpu_vmx, vcpu);
437 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
438 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
439 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
440 [number##_HIGH] = VMCS12_OFFSET(name)+4
442 static unsigned short vmcs_field_to_offset_table[] = {
443 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
444 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
445 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
446 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
447 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
448 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
449 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
450 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
451 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
452 FIELD(HOST_ES_SELECTOR, host_es_selector),
453 FIELD(HOST_CS_SELECTOR, host_cs_selector),
454 FIELD(HOST_SS_SELECTOR, host_ss_selector),
455 FIELD(HOST_DS_SELECTOR, host_ds_selector),
456 FIELD(HOST_FS_SELECTOR, host_fs_selector),
457 FIELD(HOST_GS_SELECTOR, host_gs_selector),
458 FIELD(HOST_TR_SELECTOR, host_tr_selector),
459 FIELD64(IO_BITMAP_A, io_bitmap_a),
460 FIELD64(IO_BITMAP_B, io_bitmap_b),
461 FIELD64(MSR_BITMAP, msr_bitmap),
462 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
463 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
464 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
465 FIELD64(TSC_OFFSET, tsc_offset),
466 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
467 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
468 FIELD64(EPT_POINTER, ept_pointer),
469 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
470 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
471 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
472 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
473 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
474 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
475 FIELD64(GUEST_PDPTR0, guest_pdptr0),
476 FIELD64(GUEST_PDPTR1, guest_pdptr1),
477 FIELD64(GUEST_PDPTR2, guest_pdptr2),
478 FIELD64(GUEST_PDPTR3, guest_pdptr3),
479 FIELD64(HOST_IA32_PAT, host_ia32_pat),
480 FIELD64(HOST_IA32_EFER, host_ia32_efer),
481 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
482 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
483 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
484 FIELD(EXCEPTION_BITMAP, exception_bitmap),
485 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
486 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
487 FIELD(CR3_TARGET_COUNT, cr3_target_count),
488 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
489 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
490 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
491 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
492 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
493 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
494 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
495 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
496 FIELD(TPR_THRESHOLD, tpr_threshold),
497 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
498 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
499 FIELD(VM_EXIT_REASON, vm_exit_reason),
500 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
501 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
502 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
503 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
504 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
505 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
506 FIELD(GUEST_ES_LIMIT, guest_es_limit),
507 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
508 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
509 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
510 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
511 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
512 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
513 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
514 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
515 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
516 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
517 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
518 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
519 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
520 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
521 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
522 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
523 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
524 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
525 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
526 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
527 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
528 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
529 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
530 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
531 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
532 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
533 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
534 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
535 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
536 FIELD(EXIT_QUALIFICATION, exit_qualification),
537 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
538 FIELD(GUEST_CR0, guest_cr0),
539 FIELD(GUEST_CR3, guest_cr3),
540 FIELD(GUEST_CR4, guest_cr4),
541 FIELD(GUEST_ES_BASE, guest_es_base),
542 FIELD(GUEST_CS_BASE, guest_cs_base),
543 FIELD(GUEST_SS_BASE, guest_ss_base),
544 FIELD(GUEST_DS_BASE, guest_ds_base),
545 FIELD(GUEST_FS_BASE, guest_fs_base),
546 FIELD(GUEST_GS_BASE, guest_gs_base),
547 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
548 FIELD(GUEST_TR_BASE, guest_tr_base),
549 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
550 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
551 FIELD(GUEST_DR7, guest_dr7),
552 FIELD(GUEST_RSP, guest_rsp),
553 FIELD(GUEST_RIP, guest_rip),
554 FIELD(GUEST_RFLAGS, guest_rflags),
555 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
556 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
557 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
558 FIELD(HOST_CR0, host_cr0),
559 FIELD(HOST_CR3, host_cr3),
560 FIELD(HOST_CR4, host_cr4),
561 FIELD(HOST_FS_BASE, host_fs_base),
562 FIELD(HOST_GS_BASE, host_gs_base),
563 FIELD(HOST_TR_BASE, host_tr_base),
564 FIELD(HOST_GDTR_BASE, host_gdtr_base),
565 FIELD(HOST_IDTR_BASE, host_idtr_base),
566 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
567 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
568 FIELD(HOST_RSP, host_rsp),
569 FIELD(HOST_RIP, host_rip),
571 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
573 static inline short vmcs_field_to_offset(unsigned long field)
575 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
577 return vmcs_field_to_offset_table[field];
580 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
582 return to_vmx(vcpu)->nested.current_vmcs12;
585 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
587 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
588 if (is_error_page(page)) {
589 kvm_release_page_clean(page);
595 static void nested_release_page(struct page *page)
597 kvm_release_page_dirty(page);
600 static void nested_release_page_clean(struct page *page)
602 kvm_release_page_clean(page);
605 static u64 construct_eptp(unsigned long root_hpa);
606 static void kvm_cpu_vmxon(u64 addr);
607 static void kvm_cpu_vmxoff(void);
608 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
609 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
611 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
612 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
614 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
615 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
617 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
618 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
620 static unsigned long *vmx_io_bitmap_a;
621 static unsigned long *vmx_io_bitmap_b;
622 static unsigned long *vmx_msr_bitmap_legacy;
623 static unsigned long *vmx_msr_bitmap_longmode;
625 static bool cpu_has_load_ia32_efer;
626 static bool cpu_has_load_perf_global_ctrl;
628 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
629 static DEFINE_SPINLOCK(vmx_vpid_lock);
631 static struct vmcs_config {
635 u32 pin_based_exec_ctrl;
636 u32 cpu_based_exec_ctrl;
637 u32 cpu_based_2nd_exec_ctrl;
642 static struct vmx_capability {
647 #define VMX_SEGMENT_FIELD(seg) \
648 [VCPU_SREG_##seg] = { \
649 .selector = GUEST_##seg##_SELECTOR, \
650 .base = GUEST_##seg##_BASE, \
651 .limit = GUEST_##seg##_LIMIT, \
652 .ar_bytes = GUEST_##seg##_AR_BYTES, \
655 static struct kvm_vmx_segment_field {
660 } kvm_vmx_segment_fields[] = {
661 VMX_SEGMENT_FIELD(CS),
662 VMX_SEGMENT_FIELD(DS),
663 VMX_SEGMENT_FIELD(ES),
664 VMX_SEGMENT_FIELD(FS),
665 VMX_SEGMENT_FIELD(GS),
666 VMX_SEGMENT_FIELD(SS),
667 VMX_SEGMENT_FIELD(TR),
668 VMX_SEGMENT_FIELD(LDTR),
671 static u64 host_efer;
673 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
676 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
677 * away by decrementing the array size.
679 static const u32 vmx_msr_index[] = {
681 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
683 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
685 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
687 static inline bool is_page_fault(u32 intr_info)
689 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
690 INTR_INFO_VALID_MASK)) ==
691 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
694 static inline bool is_no_device(u32 intr_info)
696 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
697 INTR_INFO_VALID_MASK)) ==
698 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
701 static inline bool is_invalid_opcode(u32 intr_info)
703 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
704 INTR_INFO_VALID_MASK)) ==
705 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
708 static inline bool is_external_interrupt(u32 intr_info)
710 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
711 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
714 static inline bool is_machine_check(u32 intr_info)
716 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
717 INTR_INFO_VALID_MASK)) ==
718 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
721 static inline bool cpu_has_vmx_msr_bitmap(void)
723 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
726 static inline bool cpu_has_vmx_tpr_shadow(void)
728 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
731 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
733 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
736 static inline bool cpu_has_secondary_exec_ctrls(void)
738 return vmcs_config.cpu_based_exec_ctrl &
739 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
742 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
744 return vmcs_config.cpu_based_2nd_exec_ctrl &
745 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
748 static inline bool cpu_has_vmx_flexpriority(void)
750 return cpu_has_vmx_tpr_shadow() &&
751 cpu_has_vmx_virtualize_apic_accesses();
754 static inline bool cpu_has_vmx_ept_execute_only(void)
756 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
759 static inline bool cpu_has_vmx_eptp_uncacheable(void)
761 return vmx_capability.ept & VMX_EPTP_UC_BIT;
764 static inline bool cpu_has_vmx_eptp_writeback(void)
766 return vmx_capability.ept & VMX_EPTP_WB_BIT;
769 static inline bool cpu_has_vmx_ept_2m_page(void)
771 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
774 static inline bool cpu_has_vmx_ept_1g_page(void)
776 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
779 static inline bool cpu_has_vmx_ept_4levels(void)
781 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
784 static inline bool cpu_has_vmx_invept_individual_addr(void)
786 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
789 static inline bool cpu_has_vmx_invept_context(void)
791 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
794 static inline bool cpu_has_vmx_invept_global(void)
796 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
799 static inline bool cpu_has_vmx_invvpid_single(void)
801 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
804 static inline bool cpu_has_vmx_invvpid_global(void)
806 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
809 static inline bool cpu_has_vmx_ept(void)
811 return vmcs_config.cpu_based_2nd_exec_ctrl &
812 SECONDARY_EXEC_ENABLE_EPT;
815 static inline bool cpu_has_vmx_unrestricted_guest(void)
817 return vmcs_config.cpu_based_2nd_exec_ctrl &
818 SECONDARY_EXEC_UNRESTRICTED_GUEST;
821 static inline bool cpu_has_vmx_ple(void)
823 return vmcs_config.cpu_based_2nd_exec_ctrl &
824 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
827 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
829 return flexpriority_enabled && irqchip_in_kernel(kvm);
832 static inline bool cpu_has_vmx_vpid(void)
834 return vmcs_config.cpu_based_2nd_exec_ctrl &
835 SECONDARY_EXEC_ENABLE_VPID;
838 static inline bool cpu_has_vmx_rdtscp(void)
840 return vmcs_config.cpu_based_2nd_exec_ctrl &
841 SECONDARY_EXEC_RDTSCP;
844 static inline bool cpu_has_virtual_nmis(void)
846 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
849 static inline bool cpu_has_vmx_wbinvd_exit(void)
851 return vmcs_config.cpu_based_2nd_exec_ctrl &
852 SECONDARY_EXEC_WBINVD_EXITING;
855 static inline bool report_flexpriority(void)
857 return flexpriority_enabled;
860 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
862 return vmcs12->cpu_based_vm_exec_control & bit;
865 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
867 return (vmcs12->cpu_based_vm_exec_control &
868 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
869 (vmcs12->secondary_vm_exec_control & bit);
872 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
873 struct kvm_vcpu *vcpu)
875 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
878 static inline bool is_exception(u32 intr_info)
880 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
881 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
884 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
885 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
886 struct vmcs12 *vmcs12,
887 u32 reason, unsigned long qualification);
889 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
893 for (i = 0; i < vmx->nmsrs; ++i)
894 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
899 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
905 } operand = { vpid, 0, gva };
907 asm volatile (__ex(ASM_VMX_INVVPID)
908 /* CF==1 or ZF==1 --> rc = -1 */
910 : : "a"(&operand), "c"(ext) : "cc", "memory");
913 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
917 } operand = {eptp, gpa};
919 asm volatile (__ex(ASM_VMX_INVEPT)
920 /* CF==1 or ZF==1 --> rc = -1 */
921 "; ja 1f ; ud2 ; 1:\n"
922 : : "a" (&operand), "c" (ext) : "cc", "memory");
925 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
929 i = __find_msr_index(vmx, msr);
931 return &vmx->guest_msrs[i];
935 static void vmcs_clear(struct vmcs *vmcs)
937 u64 phys_addr = __pa(vmcs);
940 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
941 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
944 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
948 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
950 vmcs_clear(loaded_vmcs->vmcs);
951 loaded_vmcs->cpu = -1;
952 loaded_vmcs->launched = 0;
955 static void vmcs_load(struct vmcs *vmcs)
957 u64 phys_addr = __pa(vmcs);
960 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
961 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
964 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
968 static void __loaded_vmcs_clear(void *arg)
970 struct loaded_vmcs *loaded_vmcs = arg;
971 int cpu = raw_smp_processor_id();
973 if (loaded_vmcs->cpu != cpu)
974 return; /* vcpu migration can race with cpu offline */
975 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
976 per_cpu(current_vmcs, cpu) = NULL;
977 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
978 loaded_vmcs_init(loaded_vmcs);
981 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
983 if (loaded_vmcs->cpu != -1)
984 smp_call_function_single(
985 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
988 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
993 if (cpu_has_vmx_invvpid_single())
994 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
997 static inline void vpid_sync_vcpu_global(void)
999 if (cpu_has_vmx_invvpid_global())
1000 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1003 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1005 if (cpu_has_vmx_invvpid_single())
1006 vpid_sync_vcpu_single(vmx);
1008 vpid_sync_vcpu_global();
1011 static inline void ept_sync_global(void)
1013 if (cpu_has_vmx_invept_global())
1014 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1017 static inline void ept_sync_context(u64 eptp)
1020 if (cpu_has_vmx_invept_context())
1021 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1027 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1030 if (cpu_has_vmx_invept_individual_addr())
1031 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1034 ept_sync_context(eptp);
1038 static __always_inline unsigned long vmcs_readl(unsigned long field)
1040 unsigned long value;
1042 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1043 : "=a"(value) : "d"(field) : "cc");
1047 static __always_inline u16 vmcs_read16(unsigned long field)
1049 return vmcs_readl(field);
1052 static __always_inline u32 vmcs_read32(unsigned long field)
1054 return vmcs_readl(field);
1057 static __always_inline u64 vmcs_read64(unsigned long field)
1059 #ifdef CONFIG_X86_64
1060 return vmcs_readl(field);
1062 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1066 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1068 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1069 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1073 static void vmcs_writel(unsigned long field, unsigned long value)
1077 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1078 : "=q"(error) : "a"(value), "d"(field) : "cc");
1079 if (unlikely(error))
1080 vmwrite_error(field, value);
1083 static void vmcs_write16(unsigned long field, u16 value)
1085 vmcs_writel(field, value);
1088 static void vmcs_write32(unsigned long field, u32 value)
1090 vmcs_writel(field, value);
1093 static void vmcs_write64(unsigned long field, u64 value)
1095 vmcs_writel(field, value);
1096 #ifndef CONFIG_X86_64
1098 vmcs_writel(field+1, value >> 32);
1102 static void vmcs_clear_bits(unsigned long field, u32 mask)
1104 vmcs_writel(field, vmcs_readl(field) & ~mask);
1107 static void vmcs_set_bits(unsigned long field, u32 mask)
1109 vmcs_writel(field, vmcs_readl(field) | mask);
1112 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1114 vmx->segment_cache.bitmask = 0;
1117 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1121 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1123 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1124 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1125 vmx->segment_cache.bitmask = 0;
1127 ret = vmx->segment_cache.bitmask & mask;
1128 vmx->segment_cache.bitmask |= mask;
1132 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1134 u16 *p = &vmx->segment_cache.seg[seg].selector;
1136 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1137 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1141 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1143 ulong *p = &vmx->segment_cache.seg[seg].base;
1145 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1146 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1150 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1152 u32 *p = &vmx->segment_cache.seg[seg].limit;
1154 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1155 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1159 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1161 u32 *p = &vmx->segment_cache.seg[seg].ar;
1163 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1164 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1168 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1172 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1173 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1174 if ((vcpu->guest_debug &
1175 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1176 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1177 eb |= 1u << BP_VECTOR;
1178 if (to_vmx(vcpu)->rmode.vm86_active)
1181 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1182 if (vcpu->fpu_active)
1183 eb &= ~(1u << NM_VECTOR);
1185 /* When we are running a nested L2 guest and L1 specified for it a
1186 * certain exception bitmap, we must trap the same exceptions and pass
1187 * them to L1. When running L2, we will only handle the exceptions
1188 * specified above if L1 did not want them.
1190 if (is_guest_mode(vcpu))
1191 eb |= get_vmcs12(vcpu)->exception_bitmap;
1193 vmcs_write32(EXCEPTION_BITMAP, eb);
1196 static void clear_atomic_switch_msr_special(unsigned long entry,
1199 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1200 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1203 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1206 struct msr_autoload *m = &vmx->msr_autoload;
1210 if (cpu_has_load_ia32_efer) {
1211 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1212 VM_EXIT_LOAD_IA32_EFER);
1216 case MSR_CORE_PERF_GLOBAL_CTRL:
1217 if (cpu_has_load_perf_global_ctrl) {
1218 clear_atomic_switch_msr_special(
1219 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1220 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1226 for (i = 0; i < m->nr; ++i)
1227 if (m->guest[i].index == msr)
1233 m->guest[i] = m->guest[m->nr];
1234 m->host[i] = m->host[m->nr];
1235 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1236 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1239 static void add_atomic_switch_msr_special(unsigned long entry,
1240 unsigned long exit, unsigned long guest_val_vmcs,
1241 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1243 vmcs_write64(guest_val_vmcs, guest_val);
1244 vmcs_write64(host_val_vmcs, host_val);
1245 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1246 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1249 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1250 u64 guest_val, u64 host_val)
1253 struct msr_autoload *m = &vmx->msr_autoload;
1257 if (cpu_has_load_ia32_efer) {
1258 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1259 VM_EXIT_LOAD_IA32_EFER,
1262 guest_val, host_val);
1266 case MSR_CORE_PERF_GLOBAL_CTRL:
1267 if (cpu_has_load_perf_global_ctrl) {
1268 add_atomic_switch_msr_special(
1269 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1270 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1271 GUEST_IA32_PERF_GLOBAL_CTRL,
1272 HOST_IA32_PERF_GLOBAL_CTRL,
1273 guest_val, host_val);
1279 for (i = 0; i < m->nr; ++i)
1280 if (m->guest[i].index == msr)
1283 if (i == NR_AUTOLOAD_MSRS) {
1284 printk_once(KERN_WARNING"Not enough mst switch entries. "
1285 "Can't add msr %x\n", msr);
1287 } else if (i == m->nr) {
1289 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1290 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1293 m->guest[i].index = msr;
1294 m->guest[i].value = guest_val;
1295 m->host[i].index = msr;
1296 m->host[i].value = host_val;
1299 static void reload_tss(void)
1302 * VT restores TR but not its size. Useless.
1304 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1305 struct desc_struct *descs;
1307 descs = (void *)gdt->address;
1308 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1312 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1317 guest_efer = vmx->vcpu.arch.efer;
1320 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1323 ignore_bits = EFER_NX | EFER_SCE;
1324 #ifdef CONFIG_X86_64
1325 ignore_bits |= EFER_LMA | EFER_LME;
1326 /* SCE is meaningful only in long mode on Intel */
1327 if (guest_efer & EFER_LMA)
1328 ignore_bits &= ~(u64)EFER_SCE;
1330 guest_efer &= ~ignore_bits;
1331 guest_efer |= host_efer & ignore_bits;
1332 vmx->guest_msrs[efer_offset].data = guest_efer;
1333 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1335 clear_atomic_switch_msr(vmx, MSR_EFER);
1336 /* On ept, can't emulate nx, and must switch nx atomically */
1337 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1338 guest_efer = vmx->vcpu.arch.efer;
1339 if (!(guest_efer & EFER_LMA))
1340 guest_efer &= ~EFER_LME;
1341 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1348 static unsigned long segment_base(u16 selector)
1350 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1351 struct desc_struct *d;
1352 unsigned long table_base;
1355 if (!(selector & ~3))
1358 table_base = gdt->address;
1360 if (selector & 4) { /* from ldt */
1361 u16 ldt_selector = kvm_read_ldt();
1363 if (!(ldt_selector & ~3))
1366 table_base = segment_base(ldt_selector);
1368 d = (struct desc_struct *)(table_base + (selector & ~7));
1369 v = get_desc_base(d);
1370 #ifdef CONFIG_X86_64
1371 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1372 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1377 static inline unsigned long kvm_read_tr_base(void)
1380 asm("str %0" : "=g"(tr));
1381 return segment_base(tr);
1384 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1386 struct vcpu_vmx *vmx = to_vmx(vcpu);
1389 if (vmx->host_state.loaded)
1392 vmx->host_state.loaded = 1;
1394 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1395 * allow segment selectors with cpl > 0 or ti == 1.
1397 vmx->host_state.ldt_sel = kvm_read_ldt();
1398 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1399 savesegment(fs, vmx->host_state.fs_sel);
1400 if (!(vmx->host_state.fs_sel & 7)) {
1401 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1402 vmx->host_state.fs_reload_needed = 0;
1404 vmcs_write16(HOST_FS_SELECTOR, 0);
1405 vmx->host_state.fs_reload_needed = 1;
1407 savesegment(gs, vmx->host_state.gs_sel);
1408 if (!(vmx->host_state.gs_sel & 7))
1409 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1411 vmcs_write16(HOST_GS_SELECTOR, 0);
1412 vmx->host_state.gs_ldt_reload_needed = 1;
1415 #ifdef CONFIG_X86_64
1416 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1417 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1419 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1420 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1423 #ifdef CONFIG_X86_64
1424 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1425 if (is_long_mode(&vmx->vcpu))
1426 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1428 for (i = 0; i < vmx->save_nmsrs; ++i)
1429 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1430 vmx->guest_msrs[i].data,
1431 vmx->guest_msrs[i].mask);
1434 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1436 if (!vmx->host_state.loaded)
1439 ++vmx->vcpu.stat.host_state_reload;
1440 vmx->host_state.loaded = 0;
1441 #ifdef CONFIG_X86_64
1442 if (is_long_mode(&vmx->vcpu))
1443 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1445 if (vmx->host_state.gs_ldt_reload_needed) {
1446 kvm_load_ldt(vmx->host_state.ldt_sel);
1447 #ifdef CONFIG_X86_64
1448 load_gs_index(vmx->host_state.gs_sel);
1450 loadsegment(gs, vmx->host_state.gs_sel);
1453 if (vmx->host_state.fs_reload_needed)
1454 loadsegment(fs, vmx->host_state.fs_sel);
1456 #ifdef CONFIG_X86_64
1457 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1459 if (__thread_has_fpu(current))
1461 load_gdt(&__get_cpu_var(host_gdt));
1464 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1467 __vmx_load_host_state(vmx);
1472 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1473 * vcpu mutex is already taken.
1475 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1477 struct vcpu_vmx *vmx = to_vmx(vcpu);
1478 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1481 kvm_cpu_vmxon(phys_addr);
1482 else if (vmx->loaded_vmcs->cpu != cpu)
1483 loaded_vmcs_clear(vmx->loaded_vmcs);
1485 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1486 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1487 vmcs_load(vmx->loaded_vmcs->vmcs);
1490 if (vmx->loaded_vmcs->cpu != cpu) {
1491 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1492 unsigned long sysenter_esp;
1494 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1495 local_irq_disable();
1496 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1497 &per_cpu(loaded_vmcss_on_cpu, cpu));
1501 * Linux uses per-cpu TSS and GDT, so set these when switching
1504 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1505 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1507 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1508 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1509 vmx->loaded_vmcs->cpu = cpu;
1513 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1515 __vmx_load_host_state(to_vmx(vcpu));
1516 if (!vmm_exclusive) {
1517 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1523 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1527 if (vcpu->fpu_active)
1529 vcpu->fpu_active = 1;
1530 cr0 = vmcs_readl(GUEST_CR0);
1531 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1532 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1533 vmcs_writel(GUEST_CR0, cr0);
1534 update_exception_bitmap(vcpu);
1535 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1536 if (is_guest_mode(vcpu))
1537 vcpu->arch.cr0_guest_owned_bits &=
1538 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1539 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1542 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1545 * Return the cr0 value that a nested guest would read. This is a combination
1546 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1547 * its hypervisor (cr0_read_shadow).
1549 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1551 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1552 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1554 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1556 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1557 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1560 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1562 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1563 * set this *before* calling this function.
1565 vmx_decache_cr0_guest_bits(vcpu);
1566 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1567 update_exception_bitmap(vcpu);
1568 vcpu->arch.cr0_guest_owned_bits = 0;
1569 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1570 if (is_guest_mode(vcpu)) {
1572 * L1's specified read shadow might not contain the TS bit,
1573 * so now that we turned on shadowing of this bit, we need to
1574 * set this bit of the shadow. Like in nested_vmx_run we need
1575 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1576 * up-to-date here because we just decached cr0.TS (and we'll
1577 * only update vmcs12->guest_cr0 on nested exit).
1579 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1580 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1581 (vcpu->arch.cr0 & X86_CR0_TS);
1582 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1584 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1587 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1589 unsigned long rflags, save_rflags;
1591 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1592 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1593 rflags = vmcs_readl(GUEST_RFLAGS);
1594 if (to_vmx(vcpu)->rmode.vm86_active) {
1595 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1596 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1597 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1599 to_vmx(vcpu)->rflags = rflags;
1601 return to_vmx(vcpu)->rflags;
1604 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1606 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1607 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1608 to_vmx(vcpu)->rflags = rflags;
1609 if (to_vmx(vcpu)->rmode.vm86_active) {
1610 to_vmx(vcpu)->rmode.save_rflags = rflags;
1611 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1613 vmcs_writel(GUEST_RFLAGS, rflags);
1616 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1618 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1621 if (interruptibility & GUEST_INTR_STATE_STI)
1622 ret |= KVM_X86_SHADOW_INT_STI;
1623 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1624 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1629 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1631 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1632 u32 interruptibility = interruptibility_old;
1634 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1636 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1637 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1638 else if (mask & KVM_X86_SHADOW_INT_STI)
1639 interruptibility |= GUEST_INTR_STATE_STI;
1641 if ((interruptibility != interruptibility_old))
1642 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1645 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1649 rip = kvm_rip_read(vcpu);
1650 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1651 kvm_rip_write(vcpu, rip);
1653 /* skipping an emulated instruction also counts */
1654 vmx_set_interrupt_shadow(vcpu, 0);
1657 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1659 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1660 * explicitly skip the instruction because if the HLT state is set, then
1661 * the instruction is already executing and RIP has already been
1663 if (!yield_on_hlt &&
1664 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1665 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1669 * KVM wants to inject page-faults which it got to the guest. This function
1670 * checks whether in a nested guest, we need to inject them to L1 or L2.
1671 * This function assumes it is called with the exit reason in vmcs02 being
1672 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1675 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1677 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1679 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1680 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1683 nested_vmx_vmexit(vcpu);
1687 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1688 bool has_error_code, u32 error_code,
1691 struct vcpu_vmx *vmx = to_vmx(vcpu);
1692 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1694 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1695 nested_pf_handled(vcpu))
1698 if (has_error_code) {
1699 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1700 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1703 if (vmx->rmode.vm86_active) {
1705 if (kvm_exception_is_soft(nr))
1706 inc_eip = vcpu->arch.event_exit_inst_len;
1707 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1708 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1712 if (kvm_exception_is_soft(nr)) {
1713 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1714 vmx->vcpu.arch.event_exit_inst_len);
1715 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1717 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1719 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1720 vmx_clear_hlt(vcpu);
1723 static bool vmx_rdtscp_supported(void)
1725 return cpu_has_vmx_rdtscp();
1729 * Swap MSR entry in host/guest MSR entry array.
1731 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1733 struct shared_msr_entry tmp;
1735 tmp = vmx->guest_msrs[to];
1736 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1737 vmx->guest_msrs[from] = tmp;
1741 * Set up the vmcs to automatically save and restore system
1742 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1743 * mode, as fiddling with msrs is very expensive.
1745 static void setup_msrs(struct vcpu_vmx *vmx)
1747 int save_nmsrs, index;
1748 unsigned long *msr_bitmap;
1750 vmx_load_host_state(vmx);
1752 #ifdef CONFIG_X86_64
1753 if (is_long_mode(&vmx->vcpu)) {
1754 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1756 move_msr_up(vmx, index, save_nmsrs++);
1757 index = __find_msr_index(vmx, MSR_LSTAR);
1759 move_msr_up(vmx, index, save_nmsrs++);
1760 index = __find_msr_index(vmx, MSR_CSTAR);
1762 move_msr_up(vmx, index, save_nmsrs++);
1763 index = __find_msr_index(vmx, MSR_TSC_AUX);
1764 if (index >= 0 && vmx->rdtscp_enabled)
1765 move_msr_up(vmx, index, save_nmsrs++);
1767 * MSR_STAR is only needed on long mode guests, and only
1768 * if efer.sce is enabled.
1770 index = __find_msr_index(vmx, MSR_STAR);
1771 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1772 move_msr_up(vmx, index, save_nmsrs++);
1775 index = __find_msr_index(vmx, MSR_EFER);
1776 if (index >= 0 && update_transition_efer(vmx, index))
1777 move_msr_up(vmx, index, save_nmsrs++);
1779 vmx->save_nmsrs = save_nmsrs;
1781 if (cpu_has_vmx_msr_bitmap()) {
1782 if (is_long_mode(&vmx->vcpu))
1783 msr_bitmap = vmx_msr_bitmap_longmode;
1785 msr_bitmap = vmx_msr_bitmap_legacy;
1787 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1792 * reads and returns guest's timestamp counter "register"
1793 * guest_tsc = host_tsc + tsc_offset -- 21.3
1795 static u64 guest_read_tsc(void)
1797 u64 host_tsc, tsc_offset;
1800 tsc_offset = vmcs_read64(TSC_OFFSET);
1801 return host_tsc + tsc_offset;
1805 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1806 * counter, even if a nested guest (L2) is currently running.
1808 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1810 u64 host_tsc, tsc_offset;
1813 tsc_offset = is_guest_mode(vcpu) ?
1814 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1815 vmcs_read64(TSC_OFFSET);
1816 return host_tsc + tsc_offset;
1820 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1821 * ioctl. In this case the call-back should update internal vmx state to make
1822 * the changes effective.
1824 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1826 /* Nothing to do here */
1830 * writes 'offset' into guest's timestamp counter offset register
1832 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1834 if (is_guest_mode(vcpu)) {
1836 * We're here if L1 chose not to trap WRMSR to TSC. According
1837 * to the spec, this should set L1's TSC; The offset that L1
1838 * set for L2 remains unchanged, and still needs to be added
1839 * to the newly set TSC to get L2's TSC.
1841 struct vmcs12 *vmcs12;
1842 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1843 /* recalculate vmcs02.TSC_OFFSET: */
1844 vmcs12 = get_vmcs12(vcpu);
1845 vmcs_write64(TSC_OFFSET, offset +
1846 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1847 vmcs12->tsc_offset : 0));
1849 vmcs_write64(TSC_OFFSET, offset);
1853 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1855 u64 offset = vmcs_read64(TSC_OFFSET);
1856 vmcs_write64(TSC_OFFSET, offset + adjustment);
1857 if (is_guest_mode(vcpu)) {
1858 /* Even when running L2, the adjustment needs to apply to L1 */
1859 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1863 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1865 return target_tsc - native_read_tsc();
1868 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1870 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1871 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1875 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1876 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1877 * all guests if the "nested" module option is off, and can also be disabled
1878 * for a single guest by disabling its VMX cpuid bit.
1880 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1882 return nested && guest_cpuid_has_vmx(vcpu);
1886 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1887 * returned for the various VMX controls MSRs when nested VMX is enabled.
1888 * The same values should also be used to verify that vmcs12 control fields are
1889 * valid during nested entry from L1 to L2.
1890 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1891 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1892 * bit in the high half is on if the corresponding bit in the control field
1893 * may be on. See also vmx_control_verify().
1894 * TODO: allow these variables to be modified (downgraded) by module options
1897 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1898 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1899 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1900 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1901 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1902 static __init void nested_vmx_setup_ctls_msrs(void)
1905 * Note that as a general rule, the high half of the MSRs (bits in
1906 * the control fields which may be 1) should be initialized by the
1907 * intersection of the underlying hardware's MSR (i.e., features which
1908 * can be supported) and the list of features we want to expose -
1909 * because they are known to be properly supported in our code.
1910 * Also, usually, the low half of the MSRs (bits which must be 1) can
1911 * be set to 0, meaning that L1 may turn off any of these bits. The
1912 * reason is that if one of these bits is necessary, it will appear
1913 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1914 * fields of vmcs01 and vmcs02, will turn these bits off - and
1915 * nested_vmx_exit_handled() will not pass related exits to L1.
1916 * These rules have exceptions below.
1919 /* pin-based controls */
1921 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1922 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1924 nested_vmx_pinbased_ctls_low = 0x16 ;
1925 nested_vmx_pinbased_ctls_high = 0x16 |
1926 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1927 PIN_BASED_VIRTUAL_NMIS;
1930 nested_vmx_exit_ctls_low = 0;
1931 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1932 #ifdef CONFIG_X86_64
1933 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1935 nested_vmx_exit_ctls_high = 0;
1938 /* entry controls */
1939 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1940 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1941 nested_vmx_entry_ctls_low = 0;
1942 nested_vmx_entry_ctls_high &=
1943 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1945 /* cpu-based controls */
1946 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1947 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1948 nested_vmx_procbased_ctls_low = 0;
1949 nested_vmx_procbased_ctls_high &=
1950 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1951 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1952 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1953 CPU_BASED_CR3_STORE_EXITING |
1954 #ifdef CONFIG_X86_64
1955 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1957 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1958 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1959 CPU_BASED_RDPMC_EXITING |
1960 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1962 * We can allow some features even when not supported by the
1963 * hardware. For example, L1 can specify an MSR bitmap - and we
1964 * can use it to avoid exits to L1 - even when L0 runs L2
1965 * without MSR bitmaps.
1967 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1969 /* secondary cpu-based controls */
1970 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1971 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1972 nested_vmx_secondary_ctls_low = 0;
1973 nested_vmx_secondary_ctls_high &=
1974 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1977 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1980 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1982 return ((control & high) | low) == control;
1985 static inline u64 vmx_control_msr(u32 low, u32 high)
1987 return low | ((u64)high << 32);
1991 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1992 * also let it use VMX-specific MSRs.
1993 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1994 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1995 * like all other MSRs).
1997 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1999 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2000 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2002 * According to the spec, processors which do not support VMX
2003 * should throw a #GP(0) when VMX capability MSRs are read.
2005 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2009 switch (msr_index) {
2010 case MSR_IA32_FEATURE_CONTROL:
2013 case MSR_IA32_VMX_BASIC:
2015 * This MSR reports some information about VMX support. We
2016 * should return information about the VMX we emulate for the
2017 * guest, and the VMCS structure we give it - not about the
2018 * VMX support of the underlying hardware.
2020 *pdata = VMCS12_REVISION |
2021 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2022 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2024 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2025 case MSR_IA32_VMX_PINBASED_CTLS:
2026 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2027 nested_vmx_pinbased_ctls_high);
2029 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2030 case MSR_IA32_VMX_PROCBASED_CTLS:
2031 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2032 nested_vmx_procbased_ctls_high);
2034 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2035 case MSR_IA32_VMX_EXIT_CTLS:
2036 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2037 nested_vmx_exit_ctls_high);
2039 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2040 case MSR_IA32_VMX_ENTRY_CTLS:
2041 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2042 nested_vmx_entry_ctls_high);
2044 case MSR_IA32_VMX_MISC:
2048 * These MSRs specify bits which the guest must keep fixed (on or off)
2049 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2050 * We picked the standard core2 setting.
2052 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2053 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2054 case MSR_IA32_VMX_CR0_FIXED0:
2055 *pdata = VMXON_CR0_ALWAYSON;
2057 case MSR_IA32_VMX_CR0_FIXED1:
2060 case MSR_IA32_VMX_CR4_FIXED0:
2061 *pdata = VMXON_CR4_ALWAYSON;
2063 case MSR_IA32_VMX_CR4_FIXED1:
2066 case MSR_IA32_VMX_VMCS_ENUM:
2069 case MSR_IA32_VMX_PROCBASED_CTLS2:
2070 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2071 nested_vmx_secondary_ctls_high);
2073 case MSR_IA32_VMX_EPT_VPID_CAP:
2074 /* Currently, no nested ept or nested vpid */
2084 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2086 if (!nested_vmx_allowed(vcpu))
2089 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2090 /* TODO: the right thing. */
2093 * No need to treat VMX capability MSRs specially: If we don't handle
2094 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2100 * Reads an msr value (of 'msr_index') into 'pdata'.
2101 * Returns 0 on success, non-0 otherwise.
2102 * Assumes vcpu_load() was already called.
2104 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2107 struct shared_msr_entry *msr;
2110 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2114 switch (msr_index) {
2115 #ifdef CONFIG_X86_64
2117 data = vmcs_readl(GUEST_FS_BASE);
2120 data = vmcs_readl(GUEST_GS_BASE);
2122 case MSR_KERNEL_GS_BASE:
2123 vmx_load_host_state(to_vmx(vcpu));
2124 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2128 return kvm_get_msr_common(vcpu, msr_index, pdata);
2130 data = guest_read_tsc();
2132 case MSR_IA32_SYSENTER_CS:
2133 data = vmcs_read32(GUEST_SYSENTER_CS);
2135 case MSR_IA32_SYSENTER_EIP:
2136 data = vmcs_readl(GUEST_SYSENTER_EIP);
2138 case MSR_IA32_SYSENTER_ESP:
2139 data = vmcs_readl(GUEST_SYSENTER_ESP);
2142 if (!to_vmx(vcpu)->rdtscp_enabled)
2144 /* Otherwise falls through */
2146 vmx_load_host_state(to_vmx(vcpu));
2147 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2149 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2151 vmx_load_host_state(to_vmx(vcpu));
2155 return kvm_get_msr_common(vcpu, msr_index, pdata);
2163 * Writes msr value into into the appropriate "register".
2164 * Returns 0 on success, non-0 otherwise.
2165 * Assumes vcpu_load() was already called.
2167 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2169 struct vcpu_vmx *vmx = to_vmx(vcpu);
2170 struct shared_msr_entry *msr;
2173 switch (msr_index) {
2175 vmx_load_host_state(vmx);
2176 ret = kvm_set_msr_common(vcpu, msr_index, data);
2178 #ifdef CONFIG_X86_64
2180 vmx_segment_cache_clear(vmx);
2181 vmcs_writel(GUEST_FS_BASE, data);
2184 vmx_segment_cache_clear(vmx);
2185 vmcs_writel(GUEST_GS_BASE, data);
2187 case MSR_KERNEL_GS_BASE:
2188 vmx_load_host_state(vmx);
2189 vmx->msr_guest_kernel_gs_base = data;
2192 case MSR_IA32_SYSENTER_CS:
2193 vmcs_write32(GUEST_SYSENTER_CS, data);
2195 case MSR_IA32_SYSENTER_EIP:
2196 vmcs_writel(GUEST_SYSENTER_EIP, data);
2198 case MSR_IA32_SYSENTER_ESP:
2199 vmcs_writel(GUEST_SYSENTER_ESP, data);
2202 kvm_write_tsc(vcpu, data);
2204 case MSR_IA32_CR_PAT:
2205 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2206 vmcs_write64(GUEST_IA32_PAT, data);
2207 vcpu->arch.pat = data;
2210 ret = kvm_set_msr_common(vcpu, msr_index, data);
2213 if (!vmx->rdtscp_enabled)
2215 /* Check reserved bit, higher 32 bits should be zero */
2216 if ((data >> 32) != 0)
2218 /* Otherwise falls through */
2220 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2222 msr = find_msr_entry(vmx, msr_index);
2224 vmx_load_host_state(vmx);
2228 ret = kvm_set_msr_common(vcpu, msr_index, data);
2234 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2236 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2239 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2242 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2244 case VCPU_EXREG_PDPTR:
2246 ept_save_pdptrs(vcpu);
2253 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2255 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2256 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2258 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2260 update_exception_bitmap(vcpu);
2263 static __init int cpu_has_kvm_support(void)
2265 return cpu_has_vmx();
2268 static __init int vmx_disabled_by_bios(void)
2272 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2273 if (msr & FEATURE_CONTROL_LOCKED) {
2274 /* launched w/ TXT and VMX disabled */
2275 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2278 /* launched w/o TXT and VMX only enabled w/ TXT */
2279 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2280 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2281 && !tboot_enabled()) {
2282 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2283 "activate TXT before enabling KVM\n");
2286 /* launched w/o TXT and VMX disabled */
2287 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2288 && !tboot_enabled())
2295 static void kvm_cpu_vmxon(u64 addr)
2297 asm volatile (ASM_VMX_VMXON_RAX
2298 : : "a"(&addr), "m"(addr)
2302 static int hardware_enable(void *garbage)
2304 int cpu = raw_smp_processor_id();
2305 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2308 if (read_cr4() & X86_CR4_VMXE)
2311 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2312 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2314 test_bits = FEATURE_CONTROL_LOCKED;
2315 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2316 if (tboot_enabled())
2317 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2319 if ((old & test_bits) != test_bits) {
2320 /* enable and lock */
2321 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2323 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2325 if (vmm_exclusive) {
2326 kvm_cpu_vmxon(phys_addr);
2330 store_gdt(&__get_cpu_var(host_gdt));
2335 static void vmclear_local_loaded_vmcss(void)
2337 int cpu = raw_smp_processor_id();
2338 struct loaded_vmcs *v, *n;
2340 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2341 loaded_vmcss_on_cpu_link)
2342 __loaded_vmcs_clear(v);
2346 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2349 static void kvm_cpu_vmxoff(void)
2351 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2354 static void hardware_disable(void *garbage)
2356 if (vmm_exclusive) {
2357 vmclear_local_loaded_vmcss();
2360 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2363 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2364 u32 msr, u32 *result)
2366 u32 vmx_msr_low, vmx_msr_high;
2367 u32 ctl = ctl_min | ctl_opt;
2369 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2371 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2372 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2374 /* Ensure minimum (required) set of control bits are supported. */
2382 static __init bool allow_1_setting(u32 msr, u32 ctl)
2384 u32 vmx_msr_low, vmx_msr_high;
2386 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2387 return vmx_msr_high & ctl;
2390 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2392 u32 vmx_msr_low, vmx_msr_high;
2393 u32 min, opt, min2, opt2;
2394 u32 _pin_based_exec_control = 0;
2395 u32 _cpu_based_exec_control = 0;
2396 u32 _cpu_based_2nd_exec_control = 0;
2397 u32 _vmexit_control = 0;
2398 u32 _vmentry_control = 0;
2400 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2401 opt = PIN_BASED_VIRTUAL_NMIS;
2402 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2403 &_pin_based_exec_control) < 0)
2407 #ifdef CONFIG_X86_64
2408 CPU_BASED_CR8_LOAD_EXITING |
2409 CPU_BASED_CR8_STORE_EXITING |
2411 CPU_BASED_CR3_LOAD_EXITING |
2412 CPU_BASED_CR3_STORE_EXITING |
2413 CPU_BASED_USE_IO_BITMAPS |
2414 CPU_BASED_MOV_DR_EXITING |
2415 CPU_BASED_USE_TSC_OFFSETING |
2416 CPU_BASED_MWAIT_EXITING |
2417 CPU_BASED_MONITOR_EXITING |
2418 CPU_BASED_INVLPG_EXITING;
2421 min |= CPU_BASED_HLT_EXITING;
2423 opt = CPU_BASED_TPR_SHADOW |
2424 CPU_BASED_USE_MSR_BITMAPS |
2425 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2426 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2427 &_cpu_based_exec_control) < 0)
2429 #ifdef CONFIG_X86_64
2430 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2431 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2432 ~CPU_BASED_CR8_STORE_EXITING;
2434 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2436 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2437 SECONDARY_EXEC_WBINVD_EXITING |
2438 SECONDARY_EXEC_ENABLE_VPID |
2439 SECONDARY_EXEC_ENABLE_EPT |
2440 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2441 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2442 SECONDARY_EXEC_RDTSCP;
2443 if (adjust_vmx_controls(min2, opt2,
2444 MSR_IA32_VMX_PROCBASED_CTLS2,
2445 &_cpu_based_2nd_exec_control) < 0)
2448 #ifndef CONFIG_X86_64
2449 if (!(_cpu_based_2nd_exec_control &
2450 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2451 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2453 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2454 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2456 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2457 CPU_BASED_CR3_STORE_EXITING |
2458 CPU_BASED_INVLPG_EXITING);
2459 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2460 vmx_capability.ept, vmx_capability.vpid);
2464 #ifdef CONFIG_X86_64
2465 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2467 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2468 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2469 &_vmexit_control) < 0)
2473 opt = VM_ENTRY_LOAD_IA32_PAT;
2474 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2475 &_vmentry_control) < 0)
2478 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2480 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2481 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2484 #ifdef CONFIG_X86_64
2485 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2486 if (vmx_msr_high & (1u<<16))
2490 /* Require Write-Back (WB) memory type for VMCS accesses. */
2491 if (((vmx_msr_high >> 18) & 15) != 6)
2494 vmcs_conf->size = vmx_msr_high & 0x1fff;
2495 vmcs_conf->order = get_order(vmcs_config.size);
2496 vmcs_conf->revision_id = vmx_msr_low;
2498 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2499 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2500 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2501 vmcs_conf->vmexit_ctrl = _vmexit_control;
2502 vmcs_conf->vmentry_ctrl = _vmentry_control;
2504 cpu_has_load_ia32_efer =
2505 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2506 VM_ENTRY_LOAD_IA32_EFER)
2507 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2508 VM_EXIT_LOAD_IA32_EFER);
2510 cpu_has_load_perf_global_ctrl =
2511 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2512 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2513 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2514 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2517 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2518 * but due to arrata below it can't be used. Workaround is to use
2519 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2521 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2526 * BC86,AAY89,BD102 (model 44)
2530 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2531 switch (boot_cpu_data.x86_model) {
2537 cpu_has_load_perf_global_ctrl = false;
2538 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2539 "does not work properly. Using workaround\n");
2549 static struct vmcs *alloc_vmcs_cpu(int cpu)
2551 int node = cpu_to_node(cpu);
2555 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2558 vmcs = page_address(pages);
2559 memset(vmcs, 0, vmcs_config.size);
2560 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2564 static struct vmcs *alloc_vmcs(void)
2566 return alloc_vmcs_cpu(raw_smp_processor_id());
2569 static void free_vmcs(struct vmcs *vmcs)
2571 free_pages((unsigned long)vmcs, vmcs_config.order);
2575 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2577 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2579 if (!loaded_vmcs->vmcs)
2581 loaded_vmcs_clear(loaded_vmcs);
2582 free_vmcs(loaded_vmcs->vmcs);
2583 loaded_vmcs->vmcs = NULL;
2586 static void free_kvm_area(void)
2590 for_each_possible_cpu(cpu) {
2591 free_vmcs(per_cpu(vmxarea, cpu));
2592 per_cpu(vmxarea, cpu) = NULL;
2596 static __init int alloc_kvm_area(void)
2600 for_each_possible_cpu(cpu) {
2603 vmcs = alloc_vmcs_cpu(cpu);
2609 per_cpu(vmxarea, cpu) = vmcs;
2614 static __init int hardware_setup(void)
2616 if (setup_vmcs_config(&vmcs_config) < 0)
2619 if (boot_cpu_has(X86_FEATURE_NX))
2620 kvm_enable_efer_bits(EFER_NX);
2622 if (!cpu_has_vmx_vpid())
2625 if (!cpu_has_vmx_ept() ||
2626 !cpu_has_vmx_ept_4levels()) {
2628 enable_unrestricted_guest = 0;
2631 if (!cpu_has_vmx_unrestricted_guest())
2632 enable_unrestricted_guest = 0;
2634 if (!cpu_has_vmx_flexpriority())
2635 flexpriority_enabled = 0;
2637 if (!cpu_has_vmx_tpr_shadow())
2638 kvm_x86_ops->update_cr8_intercept = NULL;
2640 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2641 kvm_disable_largepages();
2643 if (!cpu_has_vmx_ple())
2647 nested_vmx_setup_ctls_msrs();
2649 return alloc_kvm_area();
2652 static __exit void hardware_unsetup(void)
2657 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2659 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2661 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2662 vmcs_write16(sf->selector, save->selector);
2663 vmcs_writel(sf->base, save->base);
2664 vmcs_write32(sf->limit, save->limit);
2665 vmcs_write32(sf->ar_bytes, save->ar);
2667 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2669 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2673 static void enter_pmode(struct kvm_vcpu *vcpu)
2675 unsigned long flags;
2676 struct vcpu_vmx *vmx = to_vmx(vcpu);
2678 vmx->emulation_required = 1;
2679 vmx->rmode.vm86_active = 0;
2681 vmx_segment_cache_clear(vmx);
2683 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2684 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2685 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2686 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2688 flags = vmcs_readl(GUEST_RFLAGS);
2689 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2690 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2691 vmcs_writel(GUEST_RFLAGS, flags);
2693 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2694 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2696 update_exception_bitmap(vcpu);
2698 if (emulate_invalid_guest_state)
2701 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2702 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2703 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2704 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2706 vmx_segment_cache_clear(vmx);
2708 vmcs_write16(GUEST_SS_SELECTOR, 0);
2709 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2711 vmcs_write16(GUEST_CS_SELECTOR,
2712 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2713 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2716 static gva_t rmode_tss_base(struct kvm *kvm)
2718 if (!kvm->arch.tss_addr) {
2719 struct kvm_memslots *slots;
2722 slots = kvm_memslots(kvm);
2723 base_gfn = slots->memslots[0].base_gfn +
2724 kvm->memslots->memslots[0].npages - 3;
2725 return base_gfn << PAGE_SHIFT;
2727 return kvm->arch.tss_addr;
2730 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2732 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2734 save->selector = vmcs_read16(sf->selector);
2735 save->base = vmcs_readl(sf->base);
2736 save->limit = vmcs_read32(sf->limit);
2737 save->ar = vmcs_read32(sf->ar_bytes);
2738 vmcs_write16(sf->selector, save->base >> 4);
2739 vmcs_write32(sf->base, save->base & 0xffff0);
2740 vmcs_write32(sf->limit, 0xffff);
2741 vmcs_write32(sf->ar_bytes, 0xf3);
2742 if (save->base & 0xf)
2743 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2744 " aligned when entering protected mode (seg=%d)",
2748 static void enter_rmode(struct kvm_vcpu *vcpu)
2750 unsigned long flags;
2751 struct vcpu_vmx *vmx = to_vmx(vcpu);
2753 if (enable_unrestricted_guest)
2756 vmx->emulation_required = 1;
2757 vmx->rmode.vm86_active = 1;
2760 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2761 * vcpu. Call it here with phys address pointing 16M below 4G.
2763 if (!vcpu->kvm->arch.tss_addr) {
2764 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2765 "called before entering vcpu\n");
2766 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2767 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2768 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2771 vmx_segment_cache_clear(vmx);
2773 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2774 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2775 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2777 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2778 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2780 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2781 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2783 flags = vmcs_readl(GUEST_RFLAGS);
2784 vmx->rmode.save_rflags = flags;
2786 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2788 vmcs_writel(GUEST_RFLAGS, flags);
2789 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2790 update_exception_bitmap(vcpu);
2792 if (emulate_invalid_guest_state)
2793 goto continue_rmode;
2795 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2796 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2797 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2799 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2800 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2801 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2802 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2803 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2805 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2806 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2807 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2808 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2811 kvm_mmu_reset_context(vcpu);
2814 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2816 struct vcpu_vmx *vmx = to_vmx(vcpu);
2817 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2823 * Force kernel_gs_base reloading before EFER changes, as control
2824 * of this msr depends on is_long_mode().
2826 vmx_load_host_state(to_vmx(vcpu));
2827 vcpu->arch.efer = efer;
2828 if (efer & EFER_LMA) {
2829 vmcs_write32(VM_ENTRY_CONTROLS,
2830 vmcs_read32(VM_ENTRY_CONTROLS) |
2831 VM_ENTRY_IA32E_MODE);
2834 vmcs_write32(VM_ENTRY_CONTROLS,
2835 vmcs_read32(VM_ENTRY_CONTROLS) &
2836 ~VM_ENTRY_IA32E_MODE);
2838 msr->data = efer & ~EFER_LME;
2843 #ifdef CONFIG_X86_64
2845 static void enter_lmode(struct kvm_vcpu *vcpu)
2849 vmx_segment_cache_clear(to_vmx(vcpu));
2851 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2852 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2853 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2855 vmcs_write32(GUEST_TR_AR_BYTES,
2856 (guest_tr_ar & ~AR_TYPE_MASK)
2857 | AR_TYPE_BUSY_64_TSS);
2859 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2862 static void exit_lmode(struct kvm_vcpu *vcpu)
2864 vmcs_write32(VM_ENTRY_CONTROLS,
2865 vmcs_read32(VM_ENTRY_CONTROLS)
2866 & ~VM_ENTRY_IA32E_MODE);
2867 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2872 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2874 vpid_sync_context(to_vmx(vcpu));
2876 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2878 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2882 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2884 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2886 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2887 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2890 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2892 if (enable_ept && is_paging(vcpu))
2893 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2894 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2897 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2899 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2901 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2902 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2905 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2907 if (!test_bit(VCPU_EXREG_PDPTR,
2908 (unsigned long *)&vcpu->arch.regs_dirty))
2911 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2912 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2913 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2914 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2915 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2919 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2921 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2922 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2923 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2924 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2925 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2928 __set_bit(VCPU_EXREG_PDPTR,
2929 (unsigned long *)&vcpu->arch.regs_avail);
2930 __set_bit(VCPU_EXREG_PDPTR,
2931 (unsigned long *)&vcpu->arch.regs_dirty);
2934 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2936 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2938 struct kvm_vcpu *vcpu)
2940 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2941 vmx_decache_cr3(vcpu);
2942 if (!(cr0 & X86_CR0_PG)) {
2943 /* From paging/starting to nonpaging */
2944 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2945 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2946 (CPU_BASED_CR3_LOAD_EXITING |
2947 CPU_BASED_CR3_STORE_EXITING));
2948 vcpu->arch.cr0 = cr0;
2949 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2950 } else if (!is_paging(vcpu)) {
2951 /* From nonpaging to paging */
2952 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2953 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2954 ~(CPU_BASED_CR3_LOAD_EXITING |
2955 CPU_BASED_CR3_STORE_EXITING));
2956 vcpu->arch.cr0 = cr0;
2957 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2960 if (!(cr0 & X86_CR0_WP))
2961 *hw_cr0 &= ~X86_CR0_WP;
2964 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2966 struct vcpu_vmx *vmx = to_vmx(vcpu);
2967 unsigned long hw_cr0;
2969 if (enable_unrestricted_guest)
2970 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2971 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2973 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2975 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2978 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2981 #ifdef CONFIG_X86_64
2982 if (vcpu->arch.efer & EFER_LME) {
2983 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2985 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2991 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2993 if (!vcpu->fpu_active)
2994 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2996 vmcs_writel(CR0_READ_SHADOW, cr0);
2997 vmcs_writel(GUEST_CR0, hw_cr0);
2998 vcpu->arch.cr0 = cr0;
2999 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3002 static u64 construct_eptp(unsigned long root_hpa)
3006 /* TODO write the value reading from MSR */
3007 eptp = VMX_EPT_DEFAULT_MT |
3008 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3009 eptp |= (root_hpa & PAGE_MASK);
3014 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3016 unsigned long guest_cr3;
3021 eptp = construct_eptp(cr3);
3022 vmcs_write64(EPT_POINTER, eptp);
3023 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3024 vcpu->kvm->arch.ept_identity_map_addr;
3025 ept_load_pdptrs(vcpu);
3028 vmx_flush_tlb(vcpu);
3029 vmcs_writel(GUEST_CR3, guest_cr3);
3032 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3034 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3035 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3037 if (cr4 & X86_CR4_VMXE) {
3039 * To use VMXON (and later other VMX instructions), a guest
3040 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3041 * So basically the check on whether to allow nested VMX
3044 if (!nested_vmx_allowed(vcpu))
3046 } else if (to_vmx(vcpu)->nested.vmxon)
3049 vcpu->arch.cr4 = cr4;
3051 if (!is_paging(vcpu)) {
3052 hw_cr4 &= ~X86_CR4_PAE;
3053 hw_cr4 |= X86_CR4_PSE;
3054 } else if (!(cr4 & X86_CR4_PAE)) {
3055 hw_cr4 &= ~X86_CR4_PAE;
3059 vmcs_writel(CR4_READ_SHADOW, cr4);
3060 vmcs_writel(GUEST_CR4, hw_cr4);
3064 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3065 struct kvm_segment *var, int seg)
3067 struct vcpu_vmx *vmx = to_vmx(vcpu);
3068 struct kvm_save_segment *save;
3071 if (vmx->rmode.vm86_active
3072 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3073 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3074 || seg == VCPU_SREG_GS)
3075 && !emulate_invalid_guest_state) {
3077 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3078 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3079 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3080 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3081 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3084 var->selector = save->selector;
3085 var->base = save->base;
3086 var->limit = save->limit;
3088 if (seg == VCPU_SREG_TR
3089 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3090 goto use_saved_rmode_seg;
3092 var->base = vmx_read_guest_seg_base(vmx, seg);
3093 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3094 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3095 ar = vmx_read_guest_seg_ar(vmx, seg);
3096 use_saved_rmode_seg:
3097 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3099 var->type = ar & 15;
3100 var->s = (ar >> 4) & 1;
3101 var->dpl = (ar >> 5) & 3;
3102 var->present = (ar >> 7) & 1;
3103 var->avl = (ar >> 12) & 1;
3104 var->l = (ar >> 13) & 1;
3105 var->db = (ar >> 14) & 1;
3106 var->g = (ar >> 15) & 1;
3107 var->unusable = (ar >> 16) & 1;
3110 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3112 struct kvm_segment s;
3114 if (to_vmx(vcpu)->rmode.vm86_active) {
3115 vmx_get_segment(vcpu, &s, seg);
3118 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3121 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3123 if (!is_protmode(vcpu))
3126 if (!is_long_mode(vcpu)
3127 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3130 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3133 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3135 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3136 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3137 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3139 return to_vmx(vcpu)->cpl;
3143 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3150 ar = var->type & 15;
3151 ar |= (var->s & 1) << 4;
3152 ar |= (var->dpl & 3) << 5;
3153 ar |= (var->present & 1) << 7;
3154 ar |= (var->avl & 1) << 12;
3155 ar |= (var->l & 1) << 13;
3156 ar |= (var->db & 1) << 14;
3157 ar |= (var->g & 1) << 15;
3159 if (ar == 0) /* a 0 value means unusable */
3160 ar = AR_UNUSABLE_MASK;
3165 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3166 struct kvm_segment *var, int seg)
3168 struct vcpu_vmx *vmx = to_vmx(vcpu);
3169 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3172 vmx_segment_cache_clear(vmx);
3174 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3175 vmcs_write16(sf->selector, var->selector);
3176 vmx->rmode.tr.selector = var->selector;
3177 vmx->rmode.tr.base = var->base;
3178 vmx->rmode.tr.limit = var->limit;
3179 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3182 vmcs_writel(sf->base, var->base);
3183 vmcs_write32(sf->limit, var->limit);
3184 vmcs_write16(sf->selector, var->selector);
3185 if (vmx->rmode.vm86_active && var->s) {
3187 * Hack real-mode segments into vm86 compatibility.
3189 if (var->base == 0xffff0000 && var->selector == 0xf000)
3190 vmcs_writel(sf->base, 0xf0000);
3193 ar = vmx_segment_access_rights(var);
3196 * Fix the "Accessed" bit in AR field of segment registers for older
3198 * IA32 arch specifies that at the time of processor reset the
3199 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3200 * is setting it to 0 in the usedland code. This causes invalid guest
3201 * state vmexit when "unrestricted guest" mode is turned on.
3202 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3203 * tree. Newer qemu binaries with that qemu fix would not need this
3206 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3207 ar |= 0x1; /* Accessed */
3209 vmcs_write32(sf->ar_bytes, ar);
3210 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3213 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3215 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3217 *db = (ar >> 14) & 1;
3218 *l = (ar >> 13) & 1;
3221 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3223 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3224 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3227 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3229 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3230 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3233 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3235 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3236 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3239 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3241 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3242 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3245 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3247 struct kvm_segment var;
3250 vmx_get_segment(vcpu, &var, seg);
3251 ar = vmx_segment_access_rights(&var);
3253 if (var.base != (var.selector << 4))
3255 if (var.limit != 0xffff)
3263 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3265 struct kvm_segment cs;
3266 unsigned int cs_rpl;
3268 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3269 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3273 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3277 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3278 if (cs.dpl > cs_rpl)
3281 if (cs.dpl != cs_rpl)
3287 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3291 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3293 struct kvm_segment ss;
3294 unsigned int ss_rpl;
3296 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3297 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3301 if (ss.type != 3 && ss.type != 7)
3305 if (ss.dpl != ss_rpl) /* DPL != RPL */
3313 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3315 struct kvm_segment var;
3318 vmx_get_segment(vcpu, &var, seg);
3319 rpl = var.selector & SELECTOR_RPL_MASK;
3327 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3328 if (var.dpl < rpl) /* DPL < RPL */
3332 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3338 static bool tr_valid(struct kvm_vcpu *vcpu)
3340 struct kvm_segment tr;
3342 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3346 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3348 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3356 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3358 struct kvm_segment ldtr;
3360 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3364 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3374 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3376 struct kvm_segment cs, ss;
3378 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3379 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3381 return ((cs.selector & SELECTOR_RPL_MASK) ==
3382 (ss.selector & SELECTOR_RPL_MASK));
3386 * Check if guest state is valid. Returns true if valid, false if
3388 * We assume that registers are always usable
3390 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3392 /* real mode guest state checks */
3393 if (!is_protmode(vcpu)) {
3394 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3396 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3398 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3400 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3402 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3404 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3407 /* protected mode guest state checks */
3408 if (!cs_ss_rpl_check(vcpu))
3410 if (!code_segment_valid(vcpu))
3412 if (!stack_segment_valid(vcpu))
3414 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3416 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3418 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3420 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3422 if (!tr_valid(vcpu))
3424 if (!ldtr_valid(vcpu))
3428 * - Add checks on RIP
3429 * - Add checks on RFLAGS
3435 static int init_rmode_tss(struct kvm *kvm)
3439 int r, idx, ret = 0;
3441 idx = srcu_read_lock(&kvm->srcu);
3442 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3443 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3446 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3447 r = kvm_write_guest_page(kvm, fn++, &data,
3448 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3451 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3454 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3458 r = kvm_write_guest_page(kvm, fn, &data,
3459 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3466 srcu_read_unlock(&kvm->srcu, idx);
3470 static int init_rmode_identity_map(struct kvm *kvm)
3473 pfn_t identity_map_pfn;
3478 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3479 printk(KERN_ERR "EPT: identity-mapping pagetable "
3480 "haven't been allocated!\n");
3483 if (likely(kvm->arch.ept_identity_pagetable_done))
3486 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3487 idx = srcu_read_lock(&kvm->srcu);
3488 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3491 /* Set up identity-mapping pagetable for EPT in real mode */
3492 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3493 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3494 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3495 r = kvm_write_guest_page(kvm, identity_map_pfn,
3496 &tmp, i * sizeof(tmp), sizeof(tmp));
3500 kvm->arch.ept_identity_pagetable_done = true;
3503 srcu_read_unlock(&kvm->srcu, idx);
3507 static void seg_setup(int seg)
3509 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3512 vmcs_write16(sf->selector, 0);
3513 vmcs_writel(sf->base, 0);
3514 vmcs_write32(sf->limit, 0xffff);
3515 if (enable_unrestricted_guest) {
3517 if (seg == VCPU_SREG_CS)
3518 ar |= 0x08; /* code segment */
3522 vmcs_write32(sf->ar_bytes, ar);
3525 static int alloc_apic_access_page(struct kvm *kvm)
3527 struct kvm_userspace_memory_region kvm_userspace_mem;
3530 mutex_lock(&kvm->slots_lock);
3531 if (kvm->arch.apic_access_page)
3533 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3534 kvm_userspace_mem.flags = 0;
3535 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3536 kvm_userspace_mem.memory_size = PAGE_SIZE;
3537 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3541 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3543 mutex_unlock(&kvm->slots_lock);
3547 static int alloc_identity_pagetable(struct kvm *kvm)
3549 struct kvm_userspace_memory_region kvm_userspace_mem;
3552 mutex_lock(&kvm->slots_lock);
3553 if (kvm->arch.ept_identity_pagetable)
3555 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3556 kvm_userspace_mem.flags = 0;
3557 kvm_userspace_mem.guest_phys_addr =
3558 kvm->arch.ept_identity_map_addr;
3559 kvm_userspace_mem.memory_size = PAGE_SIZE;
3560 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3564 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3565 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3567 mutex_unlock(&kvm->slots_lock);
3571 static void allocate_vpid(struct vcpu_vmx *vmx)
3578 spin_lock(&vmx_vpid_lock);
3579 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3580 if (vpid < VMX_NR_VPIDS) {
3582 __set_bit(vpid, vmx_vpid_bitmap);
3584 spin_unlock(&vmx_vpid_lock);
3587 static void free_vpid(struct vcpu_vmx *vmx)
3591 spin_lock(&vmx_vpid_lock);
3593 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3594 spin_unlock(&vmx_vpid_lock);
3597 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3599 int f = sizeof(unsigned long);
3601 if (!cpu_has_vmx_msr_bitmap())
3605 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3606 * have the write-low and read-high bitmap offsets the wrong way round.
3607 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3609 if (msr <= 0x1fff) {
3610 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3611 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3612 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3614 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3615 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3619 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3622 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3623 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3627 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3628 * will not change in the lifetime of the guest.
3629 * Note that host-state that does change is set elsewhere. E.g., host-state
3630 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3632 static void vmx_set_constant_host_state(void)
3638 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3639 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3640 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3642 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3643 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3644 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3645 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3646 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3648 native_store_idt(&dt);
3649 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3651 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3652 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3654 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3655 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3656 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3657 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3659 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3660 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3661 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3665 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3667 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3669 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3670 if (is_guest_mode(&vmx->vcpu))
3671 vmx->vcpu.arch.cr4_guest_owned_bits &=
3672 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3673 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3676 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3678 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3679 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3680 exec_control &= ~CPU_BASED_TPR_SHADOW;
3681 #ifdef CONFIG_X86_64
3682 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3683 CPU_BASED_CR8_LOAD_EXITING;
3687 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3688 CPU_BASED_CR3_LOAD_EXITING |
3689 CPU_BASED_INVLPG_EXITING;
3690 return exec_control;
3693 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3695 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3696 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3697 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3699 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3701 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3702 enable_unrestricted_guest = 0;
3704 if (!enable_unrestricted_guest)
3705 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3707 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3708 return exec_control;
3711 static void ept_set_mmio_spte_mask(void)
3714 * EPT Misconfigurations can be generated if the value of bits 2:0
3715 * of an EPT paging-structure entry is 110b (write/execute).
3716 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3719 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3723 * Sets up the vmcs for emulated real mode.
3725 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3727 #ifdef CONFIG_X86_64
3733 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3734 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3736 if (cpu_has_vmx_msr_bitmap())
3737 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3739 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3742 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3743 vmcs_config.pin_based_exec_ctrl);
3745 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3747 if (cpu_has_secondary_exec_ctrls()) {
3748 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3749 vmx_secondary_exec_control(vmx));
3753 vmcs_write32(PLE_GAP, ple_gap);
3754 vmcs_write32(PLE_WINDOW, ple_window);
3757 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3758 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3759 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3761 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3762 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
3763 vmx_set_constant_host_state();
3764 #ifdef CONFIG_X86_64
3765 rdmsrl(MSR_FS_BASE, a);
3766 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3767 rdmsrl(MSR_GS_BASE, a);
3768 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3770 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3771 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3774 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3775 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3776 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3777 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3778 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3780 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3781 u32 msr_low, msr_high;
3783 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3784 host_pat = msr_low | ((u64) msr_high << 32);
3785 /* Write the default value follow host pat */
3786 vmcs_write64(GUEST_IA32_PAT, host_pat);
3787 /* Keep arch.pat sync with GUEST_IA32_PAT */
3788 vmx->vcpu.arch.pat = host_pat;
3791 for (i = 0; i < NR_VMX_MSR; ++i) {
3792 u32 index = vmx_msr_index[i];
3793 u32 data_low, data_high;
3796 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3798 if (wrmsr_safe(index, data_low, data_high) < 0)
3800 vmx->guest_msrs[j].index = i;
3801 vmx->guest_msrs[j].data = 0;
3802 vmx->guest_msrs[j].mask = -1ull;
3806 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3808 /* 22.2.1, 20.8.1 */
3809 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3811 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3812 set_cr4_guest_host_mask(vmx);
3814 kvm_write_tsc(&vmx->vcpu, 0);
3819 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3821 struct vcpu_vmx *vmx = to_vmx(vcpu);
3825 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3827 vmx->rmode.vm86_active = 0;
3829 vmx->soft_vnmi_blocked = 0;
3831 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3832 kvm_set_cr8(&vmx->vcpu, 0);
3833 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3834 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3835 msr |= MSR_IA32_APICBASE_BSP;
3836 kvm_set_apic_base(&vmx->vcpu, msr);
3838 ret = fx_init(&vmx->vcpu);
3842 vmx_segment_cache_clear(vmx);
3844 seg_setup(VCPU_SREG_CS);
3846 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3847 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3849 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3850 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3851 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3853 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3854 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3857 seg_setup(VCPU_SREG_DS);
3858 seg_setup(VCPU_SREG_ES);
3859 seg_setup(VCPU_SREG_FS);
3860 seg_setup(VCPU_SREG_GS);
3861 seg_setup(VCPU_SREG_SS);
3863 vmcs_write16(GUEST_TR_SELECTOR, 0);
3864 vmcs_writel(GUEST_TR_BASE, 0);
3865 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3866 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3868 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3869 vmcs_writel(GUEST_LDTR_BASE, 0);
3870 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3871 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3873 vmcs_write32(GUEST_SYSENTER_CS, 0);
3874 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3875 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3877 vmcs_writel(GUEST_RFLAGS, 0x02);
3878 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3879 kvm_rip_write(vcpu, 0xfff0);
3881 kvm_rip_write(vcpu, 0);
3882 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3884 vmcs_writel(GUEST_DR7, 0x400);
3886 vmcs_writel(GUEST_GDTR_BASE, 0);
3887 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3889 vmcs_writel(GUEST_IDTR_BASE, 0);
3890 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3892 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3893 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3894 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3896 /* Special registers */
3897 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3901 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3903 if (cpu_has_vmx_tpr_shadow()) {
3904 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3905 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3906 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3907 __pa(vmx->vcpu.arch.apic->regs));
3908 vmcs_write32(TPR_THRESHOLD, 0);
3911 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3912 vmcs_write64(APIC_ACCESS_ADDR,
3913 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3916 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3918 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3919 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3920 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3921 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3922 vmx_set_cr4(&vmx->vcpu, 0);
3923 vmx_set_efer(&vmx->vcpu, 0);
3924 vmx_fpu_activate(&vmx->vcpu);
3925 update_exception_bitmap(&vmx->vcpu);
3927 vpid_sync_context(vmx);
3931 /* HACK: Don't enable emulation on guest boot/reset */
3932 vmx->emulation_required = 0;
3939 * In nested virtualization, check if L1 asked to exit on external interrupts.
3940 * For most existing hypervisors, this will always return true.
3942 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3944 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3945 PIN_BASED_EXT_INTR_MASK;
3948 static void enable_irq_window(struct kvm_vcpu *vcpu)
3950 u32 cpu_based_vm_exec_control;
3951 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3952 /* We can get here when nested_run_pending caused
3953 * vmx_interrupt_allowed() to return false. In this case, do
3954 * nothing - the interrupt will be injected later.
3958 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3959 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3960 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3963 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3965 u32 cpu_based_vm_exec_control;
3967 if (!cpu_has_virtual_nmis()) {
3968 enable_irq_window(vcpu);
3972 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3973 enable_irq_window(vcpu);
3976 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3977 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3978 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3981 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3983 struct vcpu_vmx *vmx = to_vmx(vcpu);
3985 int irq = vcpu->arch.interrupt.nr;
3987 trace_kvm_inj_virq(irq);
3989 ++vcpu->stat.irq_injections;
3990 if (vmx->rmode.vm86_active) {
3992 if (vcpu->arch.interrupt.soft)
3993 inc_eip = vcpu->arch.event_exit_inst_len;
3994 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3995 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3998 intr = irq | INTR_INFO_VALID_MASK;
3999 if (vcpu->arch.interrupt.soft) {
4000 intr |= INTR_TYPE_SOFT_INTR;
4001 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4002 vmx->vcpu.arch.event_exit_inst_len);
4004 intr |= INTR_TYPE_EXT_INTR;
4005 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4006 vmx_clear_hlt(vcpu);
4009 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4011 struct vcpu_vmx *vmx = to_vmx(vcpu);
4013 if (is_guest_mode(vcpu))
4016 if (!cpu_has_virtual_nmis()) {
4018 * Tracking the NMI-blocked state in software is built upon
4019 * finding the next open IRQ window. This, in turn, depends on
4020 * well-behaving guests: They have to keep IRQs disabled at
4021 * least as long as the NMI handler runs. Otherwise we may
4022 * cause NMI nesting, maybe breaking the guest. But as this is
4023 * highly unlikely, we can live with the residual risk.
4025 vmx->soft_vnmi_blocked = 1;
4026 vmx->vnmi_blocked_time = 0;
4029 ++vcpu->stat.nmi_injections;
4030 vmx->nmi_known_unmasked = false;
4031 if (vmx->rmode.vm86_active) {
4032 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4033 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4036 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4037 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4038 vmx_clear_hlt(vcpu);
4041 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4043 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4046 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4047 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4048 | GUEST_INTR_STATE_NMI));
4051 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4053 if (!cpu_has_virtual_nmis())
4054 return to_vmx(vcpu)->soft_vnmi_blocked;
4055 if (to_vmx(vcpu)->nmi_known_unmasked)
4057 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4060 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4062 struct vcpu_vmx *vmx = to_vmx(vcpu);
4064 if (!cpu_has_virtual_nmis()) {
4065 if (vmx->soft_vnmi_blocked != masked) {
4066 vmx->soft_vnmi_blocked = masked;
4067 vmx->vnmi_blocked_time = 0;
4070 vmx->nmi_known_unmasked = !masked;
4072 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4073 GUEST_INTR_STATE_NMI);
4075 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4076 GUEST_INTR_STATE_NMI);
4080 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4082 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4083 struct vmcs12 *vmcs12;
4084 if (to_vmx(vcpu)->nested.nested_run_pending)
4086 nested_vmx_vmexit(vcpu);
4087 vmcs12 = get_vmcs12(vcpu);
4088 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4089 vmcs12->vm_exit_intr_info = 0;
4090 /* fall through to normal code, but now in L1, not L2 */
4093 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4094 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4095 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4098 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4101 struct kvm_userspace_memory_region tss_mem = {
4102 .slot = TSS_PRIVATE_MEMSLOT,
4103 .guest_phys_addr = addr,
4104 .memory_size = PAGE_SIZE * 3,
4108 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4111 kvm->arch.tss_addr = addr;
4112 if (!init_rmode_tss(kvm))
4118 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4119 int vec, u32 err_code)
4122 * Instruction with address size override prefix opcode 0x67
4123 * Cause the #SS fault with 0 error code in VM86 mode.
4125 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4126 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4129 * Forward all other exceptions that are valid in real mode.
4130 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4131 * the required debugging infrastructure rework.
4135 if (vcpu->guest_debug &
4136 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4138 kvm_queue_exception(vcpu, vec);
4142 * Update instruction length as we may reinject the exception
4143 * from user space while in guest debugging mode.
4145 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4146 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4147 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4158 kvm_queue_exception(vcpu, vec);
4165 * Trigger machine check on the host. We assume all the MSRs are already set up
4166 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4167 * We pass a fake environment to the machine check handler because we want
4168 * the guest to be always treated like user space, no matter what context
4169 * it used internally.
4171 static void kvm_machine_check(void)
4173 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4174 struct pt_regs regs = {
4175 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4176 .flags = X86_EFLAGS_IF,
4179 do_machine_check(®s, 0);
4183 static int handle_machine_check(struct kvm_vcpu *vcpu)
4185 /* already handled by vcpu_run */
4189 static int handle_exception(struct kvm_vcpu *vcpu)
4191 struct vcpu_vmx *vmx = to_vmx(vcpu);
4192 struct kvm_run *kvm_run = vcpu->run;
4193 u32 intr_info, ex_no, error_code;
4194 unsigned long cr2, rip, dr6;
4196 enum emulation_result er;
4198 vect_info = vmx->idt_vectoring_info;
4199 intr_info = vmx->exit_intr_info;
4201 if (is_machine_check(intr_info))
4202 return handle_machine_check(vcpu);
4204 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4205 !is_page_fault(intr_info)) {
4206 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4207 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4208 vcpu->run->internal.ndata = 2;
4209 vcpu->run->internal.data[0] = vect_info;
4210 vcpu->run->internal.data[1] = intr_info;
4214 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4215 return 1; /* already handled by vmx_vcpu_run() */
4217 if (is_no_device(intr_info)) {
4218 vmx_fpu_activate(vcpu);
4222 if (is_invalid_opcode(intr_info)) {
4223 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4224 if (er != EMULATE_DONE)
4225 kvm_queue_exception(vcpu, UD_VECTOR);
4230 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4231 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4232 if (is_page_fault(intr_info)) {
4233 /* EPT won't cause page fault directly */
4235 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4236 trace_kvm_page_fault(cr2, error_code);
4238 if (kvm_event_needs_reinjection(vcpu))
4239 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4240 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4243 if (vmx->rmode.vm86_active &&
4244 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4246 if (vcpu->arch.halt_request) {
4247 vcpu->arch.halt_request = 0;
4248 return kvm_emulate_halt(vcpu);
4253 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4256 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4257 if (!(vcpu->guest_debug &
4258 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4259 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4260 kvm_queue_exception(vcpu, DB_VECTOR);
4263 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4264 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4268 * Update instruction length as we may reinject #BP from
4269 * user space while in guest debugging mode. Reading it for
4270 * #DB as well causes no harm, it is not used in that case.
4272 vmx->vcpu.arch.event_exit_inst_len =
4273 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4274 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4275 rip = kvm_rip_read(vcpu);
4276 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4277 kvm_run->debug.arch.exception = ex_no;
4280 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4281 kvm_run->ex.exception = ex_no;
4282 kvm_run->ex.error_code = error_code;
4288 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4290 ++vcpu->stat.irq_exits;
4294 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4296 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4300 static int handle_io(struct kvm_vcpu *vcpu)
4302 unsigned long exit_qualification;
4303 int size, in, string;
4306 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4307 string = (exit_qualification & 16) != 0;
4308 in = (exit_qualification & 8) != 0;
4310 ++vcpu->stat.io_exits;
4313 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4315 port = exit_qualification >> 16;
4316 size = (exit_qualification & 7) + 1;
4317 skip_emulated_instruction(vcpu);
4319 return kvm_fast_pio_out(vcpu, size, port);
4323 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4326 * Patch in the VMCALL instruction:
4328 hypercall[0] = 0x0f;
4329 hypercall[1] = 0x01;
4330 hypercall[2] = 0xc1;
4333 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4334 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4336 if (to_vmx(vcpu)->nested.vmxon &&
4337 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4340 if (is_guest_mode(vcpu)) {
4342 * We get here when L2 changed cr0 in a way that did not change
4343 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4344 * but did change L0 shadowed bits. This can currently happen
4345 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4346 * loading) while pretending to allow the guest to change it.
4348 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4349 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4351 vmcs_writel(CR0_READ_SHADOW, val);
4354 return kvm_set_cr0(vcpu, val);
4357 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4359 if (is_guest_mode(vcpu)) {
4360 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4361 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4363 vmcs_writel(CR4_READ_SHADOW, val);
4366 return kvm_set_cr4(vcpu, val);
4369 /* called to set cr0 as approriate for clts instruction exit. */
4370 static void handle_clts(struct kvm_vcpu *vcpu)
4372 if (is_guest_mode(vcpu)) {
4374 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4375 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4376 * just pretend it's off (also in arch.cr0 for fpu_activate).
4378 vmcs_writel(CR0_READ_SHADOW,
4379 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4380 vcpu->arch.cr0 &= ~X86_CR0_TS;
4382 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4385 static int handle_cr(struct kvm_vcpu *vcpu)
4387 unsigned long exit_qualification, val;
4392 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4393 cr = exit_qualification & 15;
4394 reg = (exit_qualification >> 8) & 15;
4395 switch ((exit_qualification >> 4) & 3) {
4396 case 0: /* mov to cr */
4397 val = kvm_register_read(vcpu, reg);
4398 trace_kvm_cr_write(cr, val);
4401 err = handle_set_cr0(vcpu, val);
4402 kvm_complete_insn_gp(vcpu, err);
4405 err = kvm_set_cr3(vcpu, val);
4406 kvm_complete_insn_gp(vcpu, err);
4409 err = handle_set_cr4(vcpu, val);
4410 kvm_complete_insn_gp(vcpu, err);
4413 u8 cr8_prev = kvm_get_cr8(vcpu);
4414 u8 cr8 = kvm_register_read(vcpu, reg);
4415 err = kvm_set_cr8(vcpu, cr8);
4416 kvm_complete_insn_gp(vcpu, err);
4417 if (irqchip_in_kernel(vcpu->kvm))
4419 if (cr8_prev <= cr8)
4421 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4428 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4429 skip_emulated_instruction(vcpu);
4430 vmx_fpu_activate(vcpu);
4432 case 1: /*mov from cr*/
4435 val = kvm_read_cr3(vcpu);
4436 kvm_register_write(vcpu, reg, val);
4437 trace_kvm_cr_read(cr, val);
4438 skip_emulated_instruction(vcpu);
4441 val = kvm_get_cr8(vcpu);
4442 kvm_register_write(vcpu, reg, val);
4443 trace_kvm_cr_read(cr, val);
4444 skip_emulated_instruction(vcpu);
4449 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4450 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4451 kvm_lmsw(vcpu, val);
4453 skip_emulated_instruction(vcpu);
4458 vcpu->run->exit_reason = 0;
4459 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4460 (int)(exit_qualification >> 4) & 3, cr);
4464 static int handle_dr(struct kvm_vcpu *vcpu)
4466 unsigned long exit_qualification;
4469 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4470 if (!kvm_require_cpl(vcpu, 0))
4472 dr = vmcs_readl(GUEST_DR7);
4475 * As the vm-exit takes precedence over the debug trap, we
4476 * need to emulate the latter, either for the host or the
4477 * guest debugging itself.
4479 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4480 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4481 vcpu->run->debug.arch.dr7 = dr;
4482 vcpu->run->debug.arch.pc =
4483 vmcs_readl(GUEST_CS_BASE) +
4484 vmcs_readl(GUEST_RIP);
4485 vcpu->run->debug.arch.exception = DB_VECTOR;
4486 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4489 vcpu->arch.dr7 &= ~DR7_GD;
4490 vcpu->arch.dr6 |= DR6_BD;
4491 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4492 kvm_queue_exception(vcpu, DB_VECTOR);
4497 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4498 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4499 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4500 if (exit_qualification & TYPE_MOV_FROM_DR) {
4502 if (!kvm_get_dr(vcpu, dr, &val))
4503 kvm_register_write(vcpu, reg, val);
4505 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4506 skip_emulated_instruction(vcpu);
4510 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4512 vmcs_writel(GUEST_DR7, val);
4515 static int handle_cpuid(struct kvm_vcpu *vcpu)
4517 kvm_emulate_cpuid(vcpu);
4521 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4523 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4526 if (vmx_get_msr(vcpu, ecx, &data)) {
4527 trace_kvm_msr_read_ex(ecx);
4528 kvm_inject_gp(vcpu, 0);
4532 trace_kvm_msr_read(ecx, data);
4534 /* FIXME: handling of bits 32:63 of rax, rdx */
4535 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4536 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4537 skip_emulated_instruction(vcpu);
4541 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4543 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4544 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4545 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4547 if (vmx_set_msr(vcpu, ecx, data) != 0) {
4548 trace_kvm_msr_write_ex(ecx, data);
4549 kvm_inject_gp(vcpu, 0);
4553 trace_kvm_msr_write(ecx, data);
4554 skip_emulated_instruction(vcpu);
4558 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4560 kvm_make_request(KVM_REQ_EVENT, vcpu);
4564 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4566 u32 cpu_based_vm_exec_control;
4568 /* clear pending irq */
4569 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4570 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4571 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4573 kvm_make_request(KVM_REQ_EVENT, vcpu);
4575 ++vcpu->stat.irq_window_exits;
4578 * If the user space waits to inject interrupts, exit as soon as
4581 if (!irqchip_in_kernel(vcpu->kvm) &&
4582 vcpu->run->request_interrupt_window &&
4583 !kvm_cpu_has_interrupt(vcpu)) {
4584 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4590 static int handle_halt(struct kvm_vcpu *vcpu)
4592 skip_emulated_instruction(vcpu);
4593 return kvm_emulate_halt(vcpu);
4596 static int handle_vmcall(struct kvm_vcpu *vcpu)
4598 skip_emulated_instruction(vcpu);
4599 kvm_emulate_hypercall(vcpu);
4603 static int handle_invd(struct kvm_vcpu *vcpu)
4605 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4608 static int handle_invlpg(struct kvm_vcpu *vcpu)
4610 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4612 kvm_mmu_invlpg(vcpu, exit_qualification);
4613 skip_emulated_instruction(vcpu);
4617 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4619 skip_emulated_instruction(vcpu);
4620 kvm_emulate_wbinvd(vcpu);
4624 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4626 u64 new_bv = kvm_read_edx_eax(vcpu);
4627 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4629 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4630 skip_emulated_instruction(vcpu);
4634 static int handle_apic_access(struct kvm_vcpu *vcpu)
4636 if (likely(fasteoi)) {
4637 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4638 int access_type, offset;
4640 access_type = exit_qualification & APIC_ACCESS_TYPE;
4641 offset = exit_qualification & APIC_ACCESS_OFFSET;
4643 * Sane guest uses MOV to write EOI, with written value
4644 * not cared. So make a short-circuit here by avoiding
4645 * heavy instruction emulation.
4647 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4648 (offset == APIC_EOI)) {
4649 kvm_lapic_set_eoi(vcpu);
4650 skip_emulated_instruction(vcpu);
4654 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4657 static int handle_task_switch(struct kvm_vcpu *vcpu)
4659 struct vcpu_vmx *vmx = to_vmx(vcpu);
4660 unsigned long exit_qualification;
4661 bool has_error_code = false;
4664 int reason, type, idt_v;
4666 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4667 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4669 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4671 reason = (u32)exit_qualification >> 30;
4672 if (reason == TASK_SWITCH_GATE && idt_v) {
4674 case INTR_TYPE_NMI_INTR:
4675 vcpu->arch.nmi_injected = false;
4676 vmx_set_nmi_mask(vcpu, true);
4678 case INTR_TYPE_EXT_INTR:
4679 case INTR_TYPE_SOFT_INTR:
4680 kvm_clear_interrupt_queue(vcpu);
4682 case INTR_TYPE_HARD_EXCEPTION:
4683 if (vmx->idt_vectoring_info &
4684 VECTORING_INFO_DELIVER_CODE_MASK) {
4685 has_error_code = true;
4687 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4690 case INTR_TYPE_SOFT_EXCEPTION:
4691 kvm_clear_exception_queue(vcpu);
4697 tss_selector = exit_qualification;
4699 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4700 type != INTR_TYPE_EXT_INTR &&
4701 type != INTR_TYPE_NMI_INTR))
4702 skip_emulated_instruction(vcpu);
4704 if (kvm_task_switch(vcpu, tss_selector, reason,
4705 has_error_code, error_code) == EMULATE_FAIL) {
4706 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4707 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4708 vcpu->run->internal.ndata = 0;
4712 /* clear all local breakpoint enable flags */
4713 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4716 * TODO: What about debug traps on tss switch?
4717 * Are we supposed to inject them and update dr6?
4723 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4725 unsigned long exit_qualification;
4729 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4731 if (exit_qualification & (1 << 6)) {
4732 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4736 gla_validity = (exit_qualification >> 7) & 0x3;
4737 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4738 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4739 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4740 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4741 vmcs_readl(GUEST_LINEAR_ADDRESS));
4742 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4743 (long unsigned int)exit_qualification);
4744 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4745 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4749 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4750 trace_kvm_page_fault(gpa, exit_qualification);
4751 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4754 static u64 ept_rsvd_mask(u64 spte, int level)
4759 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4760 mask |= (1ULL << i);
4763 /* bits 7:3 reserved */
4765 else if (level == 2) {
4766 if (spte & (1ULL << 7))
4767 /* 2MB ref, bits 20:12 reserved */
4770 /* bits 6:3 reserved */
4777 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4780 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4782 /* 010b (write-only) */
4783 WARN_ON((spte & 0x7) == 0x2);
4785 /* 110b (write/execute) */
4786 WARN_ON((spte & 0x7) == 0x6);
4788 /* 100b (execute-only) and value not supported by logical processor */
4789 if (!cpu_has_vmx_ept_execute_only())
4790 WARN_ON((spte & 0x7) == 0x4);
4794 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4796 if (rsvd_bits != 0) {
4797 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4798 __func__, rsvd_bits);
4802 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4803 u64 ept_mem_type = (spte & 0x38) >> 3;
4805 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4806 ept_mem_type == 7) {
4807 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4808 __func__, ept_mem_type);
4815 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4818 int nr_sptes, i, ret;
4821 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4823 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4824 if (likely(ret == 1))
4825 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4830 /* It is the real ept misconfig */
4831 printk(KERN_ERR "EPT: Misconfiguration.\n");
4832 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4834 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4836 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4837 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4839 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4840 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4845 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4847 u32 cpu_based_vm_exec_control;
4849 /* clear pending NMI */
4850 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4851 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4852 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4853 ++vcpu->stat.nmi_window_exits;
4854 kvm_make_request(KVM_REQ_EVENT, vcpu);
4859 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4861 struct vcpu_vmx *vmx = to_vmx(vcpu);
4862 enum emulation_result err = EMULATE_DONE;
4865 bool intr_window_requested;
4867 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4868 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4870 while (!guest_state_valid(vcpu)) {
4871 if (intr_window_requested
4872 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4873 return handle_interrupt_window(&vmx->vcpu);
4875 err = emulate_instruction(vcpu, 0);
4877 if (err == EMULATE_DO_MMIO) {
4882 if (err != EMULATE_DONE)
4885 if (vcpu->arch.halt_request) {
4886 vcpu->arch.halt_request = 0;
4887 ret = kvm_emulate_halt(vcpu);
4891 if (signal_pending(current))
4897 vmx->emulation_required = 0;
4903 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4904 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4906 static int handle_pause(struct kvm_vcpu *vcpu)
4908 skip_emulated_instruction(vcpu);
4909 kvm_vcpu_on_spin(vcpu);
4914 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4916 kvm_queue_exception(vcpu, UD_VECTOR);
4921 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4922 * We could reuse a single VMCS for all the L2 guests, but we also want the
4923 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4924 * allows keeping them loaded on the processor, and in the future will allow
4925 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4926 * every entry if they never change.
4927 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4928 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4930 * The following functions allocate and free a vmcs02 in this pool.
4933 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4934 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4936 struct vmcs02_list *item;
4937 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4938 if (item->vmptr == vmx->nested.current_vmptr) {
4939 list_move(&item->list, &vmx->nested.vmcs02_pool);
4940 return &item->vmcs02;
4943 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4944 /* Recycle the least recently used VMCS. */
4945 item = list_entry(vmx->nested.vmcs02_pool.prev,
4946 struct vmcs02_list, list);
4947 item->vmptr = vmx->nested.current_vmptr;
4948 list_move(&item->list, &vmx->nested.vmcs02_pool);
4949 return &item->vmcs02;
4952 /* Create a new VMCS */
4953 item = (struct vmcs02_list *)
4954 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4957 item->vmcs02.vmcs = alloc_vmcs();
4958 if (!item->vmcs02.vmcs) {
4962 loaded_vmcs_init(&item->vmcs02);
4963 item->vmptr = vmx->nested.current_vmptr;
4964 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4965 vmx->nested.vmcs02_num++;
4966 return &item->vmcs02;
4969 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4970 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4972 struct vmcs02_list *item;
4973 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4974 if (item->vmptr == vmptr) {
4975 free_loaded_vmcs(&item->vmcs02);
4976 list_del(&item->list);
4978 vmx->nested.vmcs02_num--;
4984 * Free all VMCSs saved for this vcpu, except the one pointed by
4985 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4986 * currently used, if running L2), and vmcs01 when running L2.
4988 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4990 struct vmcs02_list *item, *n;
4991 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4992 if (vmx->loaded_vmcs != &item->vmcs02)
4993 free_loaded_vmcs(&item->vmcs02);
4994 list_del(&item->list);
4997 vmx->nested.vmcs02_num = 0;
4999 if (vmx->loaded_vmcs != &vmx->vmcs01)
5000 free_loaded_vmcs(&vmx->vmcs01);
5004 * Emulate the VMXON instruction.
5005 * Currently, we just remember that VMX is active, and do not save or even
5006 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5007 * do not currently need to store anything in that guest-allocated memory
5008 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5009 * argument is different from the VMXON pointer (which the spec says they do).
5011 static int handle_vmon(struct kvm_vcpu *vcpu)
5013 struct kvm_segment cs;
5014 struct vcpu_vmx *vmx = to_vmx(vcpu);
5016 /* The Intel VMX Instruction Reference lists a bunch of bits that
5017 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5018 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5019 * Otherwise, we should fail with #UD. We test these now:
5021 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5022 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5023 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5024 kvm_queue_exception(vcpu, UD_VECTOR);
5028 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5029 if (is_long_mode(vcpu) && !cs.l) {
5030 kvm_queue_exception(vcpu, UD_VECTOR);
5034 if (vmx_get_cpl(vcpu)) {
5035 kvm_inject_gp(vcpu, 0);
5039 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5040 vmx->nested.vmcs02_num = 0;
5042 vmx->nested.vmxon = true;
5044 skip_emulated_instruction(vcpu);
5049 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5050 * for running VMX instructions (except VMXON, whose prerequisites are
5051 * slightly different). It also specifies what exception to inject otherwise.
5053 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5055 struct kvm_segment cs;
5056 struct vcpu_vmx *vmx = to_vmx(vcpu);
5058 if (!vmx->nested.vmxon) {
5059 kvm_queue_exception(vcpu, UD_VECTOR);
5063 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5064 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5065 (is_long_mode(vcpu) && !cs.l)) {
5066 kvm_queue_exception(vcpu, UD_VECTOR);
5070 if (vmx_get_cpl(vcpu)) {
5071 kvm_inject_gp(vcpu, 0);
5079 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5080 * just stops using VMX.
5082 static void free_nested(struct vcpu_vmx *vmx)
5084 if (!vmx->nested.vmxon)
5086 vmx->nested.vmxon = false;
5087 if (vmx->nested.current_vmptr != -1ull) {
5088 kunmap(vmx->nested.current_vmcs12_page);
5089 nested_release_page(vmx->nested.current_vmcs12_page);
5090 vmx->nested.current_vmptr = -1ull;
5091 vmx->nested.current_vmcs12 = NULL;
5093 /* Unpin physical memory we referred to in current vmcs02 */
5094 if (vmx->nested.apic_access_page) {
5095 nested_release_page(vmx->nested.apic_access_page);
5096 vmx->nested.apic_access_page = 0;
5099 nested_free_all_saved_vmcss(vmx);
5102 /* Emulate the VMXOFF instruction */
5103 static int handle_vmoff(struct kvm_vcpu *vcpu)
5105 if (!nested_vmx_check_permission(vcpu))
5107 free_nested(to_vmx(vcpu));
5108 skip_emulated_instruction(vcpu);
5113 * Decode the memory-address operand of a vmx instruction, as recorded on an
5114 * exit caused by such an instruction (run by a guest hypervisor).
5115 * On success, returns 0. When the operand is invalid, returns 1 and throws
5118 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5119 unsigned long exit_qualification,
5120 u32 vmx_instruction_info, gva_t *ret)
5123 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5124 * Execution", on an exit, vmx_instruction_info holds most of the
5125 * addressing components of the operand. Only the displacement part
5126 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5127 * For how an actual address is calculated from all these components,
5128 * refer to Vol. 1, "Operand Addressing".
5130 int scaling = vmx_instruction_info & 3;
5131 int addr_size = (vmx_instruction_info >> 7) & 7;
5132 bool is_reg = vmx_instruction_info & (1u << 10);
5133 int seg_reg = (vmx_instruction_info >> 15) & 7;
5134 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5135 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5136 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5137 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5140 kvm_queue_exception(vcpu, UD_VECTOR);
5144 /* Addr = segment_base + offset */
5145 /* offset = base + [index * scale] + displacement */
5146 *ret = vmx_get_segment_base(vcpu, seg_reg);
5148 *ret += kvm_register_read(vcpu, base_reg);
5150 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5151 *ret += exit_qualification; /* holds the displacement */
5153 if (addr_size == 1) /* 32 bit */
5157 * TODO: throw #GP (and return 1) in various cases that the VM*
5158 * instructions require it - e.g., offset beyond segment limit,
5159 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5160 * address, and so on. Currently these are not checked.
5166 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5167 * set the success or error code of an emulated VMX instruction, as specified
5168 * by Vol 2B, VMX Instruction Reference, "Conventions".
5170 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5172 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5173 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5174 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5177 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5179 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5180 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5181 X86_EFLAGS_SF | X86_EFLAGS_OF))
5185 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5186 u32 vm_instruction_error)
5188 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5190 * failValid writes the error number to the current VMCS, which
5191 * can't be done there isn't a current VMCS.
5193 nested_vmx_failInvalid(vcpu);
5196 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5197 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5198 X86_EFLAGS_SF | X86_EFLAGS_OF))
5200 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5203 /* Emulate the VMCLEAR instruction */
5204 static int handle_vmclear(struct kvm_vcpu *vcpu)
5206 struct vcpu_vmx *vmx = to_vmx(vcpu);
5209 struct vmcs12 *vmcs12;
5211 struct x86_exception e;
5213 if (!nested_vmx_check_permission(vcpu))
5216 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5217 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5220 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5221 sizeof(vmptr), &e)) {
5222 kvm_inject_page_fault(vcpu, &e);
5226 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5227 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5228 skip_emulated_instruction(vcpu);
5232 if (vmptr == vmx->nested.current_vmptr) {
5233 kunmap(vmx->nested.current_vmcs12_page);
5234 nested_release_page(vmx->nested.current_vmcs12_page);
5235 vmx->nested.current_vmptr = -1ull;
5236 vmx->nested.current_vmcs12 = NULL;
5239 page = nested_get_page(vcpu, vmptr);
5242 * For accurate processor emulation, VMCLEAR beyond available
5243 * physical memory should do nothing at all. However, it is
5244 * possible that a nested vmx bug, not a guest hypervisor bug,
5245 * resulted in this case, so let's shut down before doing any
5248 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5251 vmcs12 = kmap(page);
5252 vmcs12->launch_state = 0;
5254 nested_release_page(page);
5256 nested_free_vmcs02(vmx, vmptr);
5258 skip_emulated_instruction(vcpu);
5259 nested_vmx_succeed(vcpu);
5263 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5265 /* Emulate the VMLAUNCH instruction */
5266 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5268 return nested_vmx_run(vcpu, true);
5271 /* Emulate the VMRESUME instruction */
5272 static int handle_vmresume(struct kvm_vcpu *vcpu)
5275 return nested_vmx_run(vcpu, false);
5278 enum vmcs_field_type {
5279 VMCS_FIELD_TYPE_U16 = 0,
5280 VMCS_FIELD_TYPE_U64 = 1,
5281 VMCS_FIELD_TYPE_U32 = 2,
5282 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5285 static inline int vmcs_field_type(unsigned long field)
5287 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5288 return VMCS_FIELD_TYPE_U32;
5289 return (field >> 13) & 0x3 ;
5292 static inline int vmcs_field_readonly(unsigned long field)
5294 return (((field >> 10) & 0x3) == 1);
5298 * Read a vmcs12 field. Since these can have varying lengths and we return
5299 * one type, we chose the biggest type (u64) and zero-extend the return value
5300 * to that size. Note that the caller, handle_vmread, might need to use only
5301 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5302 * 64-bit fields are to be returned).
5304 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5305 unsigned long field, u64 *ret)
5307 short offset = vmcs_field_to_offset(field);
5313 p = ((char *)(get_vmcs12(vcpu))) + offset;
5315 switch (vmcs_field_type(field)) {
5316 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5317 *ret = *((natural_width *)p);
5319 case VMCS_FIELD_TYPE_U16:
5322 case VMCS_FIELD_TYPE_U32:
5325 case VMCS_FIELD_TYPE_U64:
5329 return 0; /* can never happen. */
5334 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5335 * used before) all generate the same failure when it is missing.
5337 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5339 struct vcpu_vmx *vmx = to_vmx(vcpu);
5340 if (vmx->nested.current_vmptr == -1ull) {
5341 nested_vmx_failInvalid(vcpu);
5342 skip_emulated_instruction(vcpu);
5348 static int handle_vmread(struct kvm_vcpu *vcpu)
5350 unsigned long field;
5352 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5353 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5356 if (!nested_vmx_check_permission(vcpu) ||
5357 !nested_vmx_check_vmcs12(vcpu))
5360 /* Decode instruction info and find the field to read */
5361 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5362 /* Read the field, zero-extended to a u64 field_value */
5363 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5364 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5365 skip_emulated_instruction(vcpu);
5369 * Now copy part of this value to register or memory, as requested.
5370 * Note that the number of bits actually copied is 32 or 64 depending
5371 * on the guest's mode (32 or 64 bit), not on the given field's length.
5373 if (vmx_instruction_info & (1u << 10)) {
5374 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5377 if (get_vmx_mem_address(vcpu, exit_qualification,
5378 vmx_instruction_info, &gva))
5380 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5381 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5382 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5385 nested_vmx_succeed(vcpu);
5386 skip_emulated_instruction(vcpu);
5391 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5393 unsigned long field;
5395 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5396 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5399 /* The value to write might be 32 or 64 bits, depending on L1's long
5400 * mode, and eventually we need to write that into a field of several
5401 * possible lengths. The code below first zero-extends the value to 64
5402 * bit (field_value), and then copies only the approriate number of
5403 * bits into the vmcs12 field.
5405 u64 field_value = 0;
5406 struct x86_exception e;
5408 if (!nested_vmx_check_permission(vcpu) ||
5409 !nested_vmx_check_vmcs12(vcpu))
5412 if (vmx_instruction_info & (1u << 10))
5413 field_value = kvm_register_read(vcpu,
5414 (((vmx_instruction_info) >> 3) & 0xf));
5416 if (get_vmx_mem_address(vcpu, exit_qualification,
5417 vmx_instruction_info, &gva))
5419 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5420 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5421 kvm_inject_page_fault(vcpu, &e);
5427 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5428 if (vmcs_field_readonly(field)) {
5429 nested_vmx_failValid(vcpu,
5430 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5431 skip_emulated_instruction(vcpu);
5435 offset = vmcs_field_to_offset(field);
5437 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5438 skip_emulated_instruction(vcpu);
5441 p = ((char *) get_vmcs12(vcpu)) + offset;
5443 switch (vmcs_field_type(field)) {
5444 case VMCS_FIELD_TYPE_U16:
5445 *(u16 *)p = field_value;
5447 case VMCS_FIELD_TYPE_U32:
5448 *(u32 *)p = field_value;
5450 case VMCS_FIELD_TYPE_U64:
5451 *(u64 *)p = field_value;
5453 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5454 *(natural_width *)p = field_value;
5457 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5458 skip_emulated_instruction(vcpu);
5462 nested_vmx_succeed(vcpu);
5463 skip_emulated_instruction(vcpu);
5467 /* Emulate the VMPTRLD instruction */
5468 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5470 struct vcpu_vmx *vmx = to_vmx(vcpu);
5473 struct x86_exception e;
5475 if (!nested_vmx_check_permission(vcpu))
5478 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5479 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5482 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5483 sizeof(vmptr), &e)) {
5484 kvm_inject_page_fault(vcpu, &e);
5488 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5489 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5490 skip_emulated_instruction(vcpu);
5494 if (vmx->nested.current_vmptr != vmptr) {
5495 struct vmcs12 *new_vmcs12;
5497 page = nested_get_page(vcpu, vmptr);
5499 nested_vmx_failInvalid(vcpu);
5500 skip_emulated_instruction(vcpu);
5503 new_vmcs12 = kmap(page);
5504 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5506 nested_release_page_clean(page);
5507 nested_vmx_failValid(vcpu,
5508 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5509 skip_emulated_instruction(vcpu);
5512 if (vmx->nested.current_vmptr != -1ull) {
5513 kunmap(vmx->nested.current_vmcs12_page);
5514 nested_release_page(vmx->nested.current_vmcs12_page);
5517 vmx->nested.current_vmptr = vmptr;
5518 vmx->nested.current_vmcs12 = new_vmcs12;
5519 vmx->nested.current_vmcs12_page = page;
5522 nested_vmx_succeed(vcpu);
5523 skip_emulated_instruction(vcpu);
5527 /* Emulate the VMPTRST instruction */
5528 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5530 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5531 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5533 struct x86_exception e;
5535 if (!nested_vmx_check_permission(vcpu))
5538 if (get_vmx_mem_address(vcpu, exit_qualification,
5539 vmx_instruction_info, &vmcs_gva))
5541 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5542 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5543 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5545 kvm_inject_page_fault(vcpu, &e);
5548 nested_vmx_succeed(vcpu);
5549 skip_emulated_instruction(vcpu);
5554 * The exit handlers return 1 if the exit was handled fully and guest execution
5555 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5556 * to be done to userspace and return 0.
5558 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5559 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5560 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5561 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5562 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5563 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5564 [EXIT_REASON_CR_ACCESS] = handle_cr,
5565 [EXIT_REASON_DR_ACCESS] = handle_dr,
5566 [EXIT_REASON_CPUID] = handle_cpuid,
5567 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5568 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5569 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5570 [EXIT_REASON_HLT] = handle_halt,
5571 [EXIT_REASON_INVD] = handle_invd,
5572 [EXIT_REASON_INVLPG] = handle_invlpg,
5573 [EXIT_REASON_VMCALL] = handle_vmcall,
5574 [EXIT_REASON_VMCLEAR] = handle_vmclear,
5575 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
5576 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
5577 [EXIT_REASON_VMPTRST] = handle_vmptrst,
5578 [EXIT_REASON_VMREAD] = handle_vmread,
5579 [EXIT_REASON_VMRESUME] = handle_vmresume,
5580 [EXIT_REASON_VMWRITE] = handle_vmwrite,
5581 [EXIT_REASON_VMOFF] = handle_vmoff,
5582 [EXIT_REASON_VMON] = handle_vmon,
5583 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5584 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5585 [EXIT_REASON_WBINVD] = handle_wbinvd,
5586 [EXIT_REASON_XSETBV] = handle_xsetbv,
5587 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5588 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5589 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5590 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5591 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5592 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5593 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
5596 static const int kvm_vmx_max_exit_handlers =
5597 ARRAY_SIZE(kvm_vmx_exit_handlers);
5600 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5601 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5602 * disinterest in the current event (read or write a specific MSR) by using an
5603 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5605 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5606 struct vmcs12 *vmcs12, u32 exit_reason)
5608 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5611 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5615 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5616 * for the four combinations of read/write and low/high MSR numbers.
5617 * First we need to figure out which of the four to use:
5619 bitmap = vmcs12->msr_bitmap;
5620 if (exit_reason == EXIT_REASON_MSR_WRITE)
5622 if (msr_index >= 0xc0000000) {
5623 msr_index -= 0xc0000000;
5627 /* Then read the msr_index'th bit from this bitmap: */
5628 if (msr_index < 1024*8) {
5630 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5631 return 1 & (b >> (msr_index & 7));
5633 return 1; /* let L1 handle the wrong parameter */
5637 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5638 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5639 * intercept (via guest_host_mask etc.) the current event.
5641 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5642 struct vmcs12 *vmcs12)
5644 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5645 int cr = exit_qualification & 15;
5646 int reg = (exit_qualification >> 8) & 15;
5647 unsigned long val = kvm_register_read(vcpu, reg);
5649 switch ((exit_qualification >> 4) & 3) {
5650 case 0: /* mov to cr */
5653 if (vmcs12->cr0_guest_host_mask &
5654 (val ^ vmcs12->cr0_read_shadow))
5658 if ((vmcs12->cr3_target_count >= 1 &&
5659 vmcs12->cr3_target_value0 == val) ||
5660 (vmcs12->cr3_target_count >= 2 &&
5661 vmcs12->cr3_target_value1 == val) ||
5662 (vmcs12->cr3_target_count >= 3 &&
5663 vmcs12->cr3_target_value2 == val) ||
5664 (vmcs12->cr3_target_count >= 4 &&
5665 vmcs12->cr3_target_value3 == val))
5667 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5671 if (vmcs12->cr4_guest_host_mask &
5672 (vmcs12->cr4_read_shadow ^ val))
5676 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5682 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5683 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5686 case 1: /* mov from cr */
5689 if (vmcs12->cpu_based_vm_exec_control &
5690 CPU_BASED_CR3_STORE_EXITING)
5694 if (vmcs12->cpu_based_vm_exec_control &
5695 CPU_BASED_CR8_STORE_EXITING)
5702 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5703 * cr0. Other attempted changes are ignored, with no exit.
5705 if (vmcs12->cr0_guest_host_mask & 0xe &
5706 (val ^ vmcs12->cr0_read_shadow))
5708 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5709 !(vmcs12->cr0_read_shadow & 0x1) &&
5718 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5719 * should handle it ourselves in L0 (and then continue L2). Only call this
5720 * when in is_guest_mode (L2).
5722 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5724 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5725 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5726 struct vcpu_vmx *vmx = to_vmx(vcpu);
5727 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5729 if (vmx->nested.nested_run_pending)
5732 if (unlikely(vmx->fail)) {
5733 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5734 vmcs_read32(VM_INSTRUCTION_ERROR));
5738 switch (exit_reason) {
5739 case EXIT_REASON_EXCEPTION_NMI:
5740 if (!is_exception(intr_info))
5742 else if (is_page_fault(intr_info))
5744 return vmcs12->exception_bitmap &
5745 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5746 case EXIT_REASON_EXTERNAL_INTERRUPT:
5748 case EXIT_REASON_TRIPLE_FAULT:
5750 case EXIT_REASON_PENDING_INTERRUPT:
5751 case EXIT_REASON_NMI_WINDOW:
5753 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5754 * (aka Interrupt Window Exiting) only when L1 turned it on,
5755 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5756 * Same for NMI Window Exiting.
5759 case EXIT_REASON_TASK_SWITCH:
5761 case EXIT_REASON_CPUID:
5763 case EXIT_REASON_HLT:
5764 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5765 case EXIT_REASON_INVD:
5767 case EXIT_REASON_INVLPG:
5768 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5769 case EXIT_REASON_RDPMC:
5770 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5771 case EXIT_REASON_RDTSC:
5772 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5773 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5774 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5775 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5776 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5777 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5779 * VMX instructions trap unconditionally. This allows L1 to
5780 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5783 case EXIT_REASON_CR_ACCESS:
5784 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5785 case EXIT_REASON_DR_ACCESS:
5786 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5787 case EXIT_REASON_IO_INSTRUCTION:
5788 /* TODO: support IO bitmaps */
5790 case EXIT_REASON_MSR_READ:
5791 case EXIT_REASON_MSR_WRITE:
5792 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5793 case EXIT_REASON_INVALID_STATE:
5795 case EXIT_REASON_MWAIT_INSTRUCTION:
5796 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5797 case EXIT_REASON_MONITOR_INSTRUCTION:
5798 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5799 case EXIT_REASON_PAUSE_INSTRUCTION:
5800 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5801 nested_cpu_has2(vmcs12,
5802 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5803 case EXIT_REASON_MCE_DURING_VMENTRY:
5805 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5807 case EXIT_REASON_APIC_ACCESS:
5808 return nested_cpu_has2(vmcs12,
5809 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5810 case EXIT_REASON_EPT_VIOLATION:
5811 case EXIT_REASON_EPT_MISCONFIG:
5813 case EXIT_REASON_WBINVD:
5814 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5815 case EXIT_REASON_XSETBV:
5822 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5824 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5825 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5829 * The guest has exited. See if we can fix it or if we need userspace
5832 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5834 struct vcpu_vmx *vmx = to_vmx(vcpu);
5835 u32 exit_reason = vmx->exit_reason;
5836 u32 vectoring_info = vmx->idt_vectoring_info;
5838 /* If guest state is invalid, start emulating */
5839 if (vmx->emulation_required && emulate_invalid_guest_state)
5840 return handle_invalid_guest_state(vcpu);
5843 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5844 * we did not inject a still-pending event to L1 now because of
5845 * nested_run_pending, we need to re-enable this bit.
5847 if (vmx->nested.nested_run_pending)
5848 kvm_make_request(KVM_REQ_EVENT, vcpu);
5850 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5851 exit_reason == EXIT_REASON_VMRESUME))
5852 vmx->nested.nested_run_pending = 1;
5854 vmx->nested.nested_run_pending = 0;
5856 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5857 nested_vmx_vmexit(vcpu);
5861 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5862 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5863 vcpu->run->fail_entry.hardware_entry_failure_reason
5868 if (unlikely(vmx->fail)) {
5869 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5870 vcpu->run->fail_entry.hardware_entry_failure_reason
5871 = vmcs_read32(VM_INSTRUCTION_ERROR);
5875 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5876 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5877 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5878 exit_reason != EXIT_REASON_TASK_SWITCH))
5879 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5880 "(0x%x) and exit reason is 0x%x\n",
5881 __func__, vectoring_info, exit_reason);
5883 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5884 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5885 get_vmcs12(vcpu), vcpu)))) {
5886 if (vmx_interrupt_allowed(vcpu)) {
5887 vmx->soft_vnmi_blocked = 0;
5888 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5889 vcpu->arch.nmi_pending) {
5891 * This CPU don't support us in finding the end of an
5892 * NMI-blocked window if the guest runs with IRQs
5893 * disabled. So we pull the trigger after 1 s of
5894 * futile waiting, but inform the user about this.
5896 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5897 "state on VCPU %d after 1 s timeout\n",
5898 __func__, vcpu->vcpu_id);
5899 vmx->soft_vnmi_blocked = 0;
5903 if (exit_reason < kvm_vmx_max_exit_handlers
5904 && kvm_vmx_exit_handlers[exit_reason])
5905 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5907 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5908 vcpu->run->hw.hardware_exit_reason = exit_reason;
5913 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5915 if (irr == -1 || tpr < irr) {
5916 vmcs_write32(TPR_THRESHOLD, 0);
5920 vmcs_write32(TPR_THRESHOLD, irr);
5923 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5927 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5928 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5931 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5932 exit_intr_info = vmx->exit_intr_info;
5934 /* Handle machine checks before interrupts are enabled */
5935 if (is_machine_check(exit_intr_info))
5936 kvm_machine_check();
5938 /* We need to handle NMIs before interrupts are enabled */
5939 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5940 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5941 kvm_before_handle_nmi(&vmx->vcpu);
5943 kvm_after_handle_nmi(&vmx->vcpu);
5947 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5952 bool idtv_info_valid;
5954 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5956 if (cpu_has_virtual_nmis()) {
5957 if (vmx->nmi_known_unmasked)
5960 * Can't use vmx->exit_intr_info since we're not sure what
5961 * the exit reason is.
5963 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5964 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5965 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5967 * SDM 3: 27.7.1.2 (September 2008)
5968 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5969 * a guest IRET fault.
5970 * SDM 3: 23.2.2 (September 2008)
5971 * Bit 12 is undefined in any of the following cases:
5972 * If the VM exit sets the valid bit in the IDT-vectoring
5973 * information field.
5974 * If the VM exit is due to a double fault.
5976 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5977 vector != DF_VECTOR && !idtv_info_valid)
5978 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5979 GUEST_INTR_STATE_NMI);
5981 vmx->nmi_known_unmasked =
5982 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5983 & GUEST_INTR_STATE_NMI);
5984 } else if (unlikely(vmx->soft_vnmi_blocked))
5985 vmx->vnmi_blocked_time +=
5986 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5989 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5990 u32 idt_vectoring_info,
5991 int instr_len_field,
5992 int error_code_field)
5996 bool idtv_info_valid;
5998 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6000 vmx->vcpu.arch.nmi_injected = false;
6001 kvm_clear_exception_queue(&vmx->vcpu);
6002 kvm_clear_interrupt_queue(&vmx->vcpu);
6004 if (!idtv_info_valid)
6007 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6009 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6010 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6013 case INTR_TYPE_NMI_INTR:
6014 vmx->vcpu.arch.nmi_injected = true;
6016 * SDM 3: 27.7.1.2 (September 2008)
6017 * Clear bit "block by NMI" before VM entry if a NMI
6020 vmx_set_nmi_mask(&vmx->vcpu, false);
6022 case INTR_TYPE_SOFT_EXCEPTION:
6023 vmx->vcpu.arch.event_exit_inst_len =
6024 vmcs_read32(instr_len_field);
6026 case INTR_TYPE_HARD_EXCEPTION:
6027 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6028 u32 err = vmcs_read32(error_code_field);
6029 kvm_queue_exception_e(&vmx->vcpu, vector, err);
6031 kvm_queue_exception(&vmx->vcpu, vector);
6033 case INTR_TYPE_SOFT_INTR:
6034 vmx->vcpu.arch.event_exit_inst_len =
6035 vmcs_read32(instr_len_field);
6037 case INTR_TYPE_EXT_INTR:
6038 kvm_queue_interrupt(&vmx->vcpu, vector,
6039 type == INTR_TYPE_SOFT_INTR);
6046 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6048 if (is_guest_mode(&vmx->vcpu))
6050 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6051 VM_EXIT_INSTRUCTION_LEN,
6052 IDT_VECTORING_ERROR_CODE);
6055 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6057 if (is_guest_mode(vcpu))
6059 __vmx_complete_interrupts(to_vmx(vcpu),
6060 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6061 VM_ENTRY_INSTRUCTION_LEN,
6062 VM_ENTRY_EXCEPTION_ERROR_CODE);
6064 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6067 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6070 struct perf_guest_switch_msr *msrs;
6072 msrs = perf_guest_get_msrs(&nr_msrs);
6077 for (i = 0; i < nr_msrs; i++)
6078 if (msrs[i].host == msrs[i].guest)
6079 clear_atomic_switch_msr(vmx, msrs[i].msr);
6081 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6085 #ifdef CONFIG_X86_64
6093 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6095 struct vcpu_vmx *vmx = to_vmx(vcpu);
6097 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6098 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6099 if (vmcs12->idt_vectoring_info_field &
6100 VECTORING_INFO_VALID_MASK) {
6101 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6102 vmcs12->idt_vectoring_info_field);
6103 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6104 vmcs12->vm_exit_instruction_len);
6105 if (vmcs12->idt_vectoring_info_field &
6106 VECTORING_INFO_DELIVER_CODE_MASK)
6107 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6108 vmcs12->idt_vectoring_error_code);
6112 /* Record the guest's net vcpu time for enforced NMI injections. */
6113 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6114 vmx->entry_time = ktime_get();
6116 /* Don't enter VMX if guest state is invalid, let the exit handler
6117 start emulation until we arrive back to a valid state */
6118 if (vmx->emulation_required && emulate_invalid_guest_state)
6121 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6122 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6123 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6124 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6126 /* When single-stepping over STI and MOV SS, we must clear the
6127 * corresponding interruptibility bits in the guest state. Otherwise
6128 * vmentry fails as it then expects bit 14 (BS) in pending debug
6129 * exceptions being set, but that's not correct for the guest debugging
6131 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6132 vmx_set_interrupt_shadow(vcpu, 0);
6134 atomic_switch_perf_msrs(vmx);
6136 vmx->__launched = vmx->loaded_vmcs->launched;
6138 /* Store host registers */
6139 "push %%"R"dx; push %%"R"bp;"
6140 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6142 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6144 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6145 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6147 /* Reload cr2 if changed */
6148 "mov %c[cr2](%0), %%"R"ax \n\t"
6149 "mov %%cr2, %%"R"dx \n\t"
6150 "cmp %%"R"ax, %%"R"dx \n\t"
6152 "mov %%"R"ax, %%cr2 \n\t"
6154 /* Check if vmlaunch of vmresume is needed */
6155 "cmpl $0, %c[launched](%0) \n\t"
6156 /* Load guest registers. Don't clobber flags. */
6157 "mov %c[rax](%0), %%"R"ax \n\t"
6158 "mov %c[rbx](%0), %%"R"bx \n\t"
6159 "mov %c[rdx](%0), %%"R"dx \n\t"
6160 "mov %c[rsi](%0), %%"R"si \n\t"
6161 "mov %c[rdi](%0), %%"R"di \n\t"
6162 "mov %c[rbp](%0), %%"R"bp \n\t"
6163 #ifdef CONFIG_X86_64
6164 "mov %c[r8](%0), %%r8 \n\t"
6165 "mov %c[r9](%0), %%r9 \n\t"
6166 "mov %c[r10](%0), %%r10 \n\t"
6167 "mov %c[r11](%0), %%r11 \n\t"
6168 "mov %c[r12](%0), %%r12 \n\t"
6169 "mov %c[r13](%0), %%r13 \n\t"
6170 "mov %c[r14](%0), %%r14 \n\t"
6171 "mov %c[r15](%0), %%r15 \n\t"
6173 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6175 /* Enter guest mode */
6176 "jne .Llaunched \n\t"
6177 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6178 "jmp .Lkvm_vmx_return \n\t"
6179 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6180 ".Lkvm_vmx_return: "
6181 /* Save guest registers, load host registers, keep flags */
6182 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6184 "mov %%"R"ax, %c[rax](%0) \n\t"
6185 "mov %%"R"bx, %c[rbx](%0) \n\t"
6186 "pop"Q" %c[rcx](%0) \n\t"
6187 "mov %%"R"dx, %c[rdx](%0) \n\t"
6188 "mov %%"R"si, %c[rsi](%0) \n\t"
6189 "mov %%"R"di, %c[rdi](%0) \n\t"
6190 "mov %%"R"bp, %c[rbp](%0) \n\t"
6191 #ifdef CONFIG_X86_64
6192 "mov %%r8, %c[r8](%0) \n\t"
6193 "mov %%r9, %c[r9](%0) \n\t"
6194 "mov %%r10, %c[r10](%0) \n\t"
6195 "mov %%r11, %c[r11](%0) \n\t"
6196 "mov %%r12, %c[r12](%0) \n\t"
6197 "mov %%r13, %c[r13](%0) \n\t"
6198 "mov %%r14, %c[r14](%0) \n\t"
6199 "mov %%r15, %c[r15](%0) \n\t"
6201 "mov %%cr2, %%"R"ax \n\t"
6202 "mov %%"R"ax, %c[cr2](%0) \n\t"
6204 "pop %%"R"bp; pop %%"R"dx \n\t"
6205 "setbe %c[fail](%0) \n\t"
6206 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6207 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6208 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6209 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6210 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6211 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6212 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6213 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6214 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6215 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6216 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6217 #ifdef CONFIG_X86_64
6218 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6219 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6220 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6221 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6222 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6223 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6224 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6225 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6227 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6228 [wordsize]"i"(sizeof(ulong))
6230 , R"ax", R"bx", R"di", R"si"
6231 #ifdef CONFIG_X86_64
6232 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6236 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6237 | (1 << VCPU_EXREG_RFLAGS)
6238 | (1 << VCPU_EXREG_CPL)
6239 | (1 << VCPU_EXREG_PDPTR)
6240 | (1 << VCPU_EXREG_SEGMENTS)
6241 | (1 << VCPU_EXREG_CR3));
6242 vcpu->arch.regs_dirty = 0;
6244 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6246 if (is_guest_mode(vcpu)) {
6247 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6248 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6249 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6250 vmcs12->idt_vectoring_error_code =
6251 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6252 vmcs12->vm_exit_instruction_len =
6253 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6257 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6258 vmx->loaded_vmcs->launched = 1;
6260 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6261 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6263 vmx_complete_atomic_exit(vmx);
6264 vmx_recover_nmi_blocking(vmx);
6265 vmx_complete_interrupts(vmx);
6271 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6273 struct vcpu_vmx *vmx = to_vmx(vcpu);
6276 free_loaded_vmcs(vmx->loaded_vmcs);
6278 kfree(vmx->guest_msrs);
6279 kvm_vcpu_uninit(vcpu);
6280 kmem_cache_free(kvm_vcpu_cache, vmx);
6283 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6286 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6290 return ERR_PTR(-ENOMEM);
6294 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6298 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6300 if (!vmx->guest_msrs) {
6304 vmx->loaded_vmcs = &vmx->vmcs01;
6305 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6306 if (!vmx->loaded_vmcs->vmcs)
6309 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6310 loaded_vmcs_init(vmx->loaded_vmcs);
6315 vmx_vcpu_load(&vmx->vcpu, cpu);
6316 vmx->vcpu.cpu = cpu;
6317 err = vmx_vcpu_setup(vmx);
6318 vmx_vcpu_put(&vmx->vcpu);
6322 if (vm_need_virtualize_apic_accesses(kvm))
6323 err = alloc_apic_access_page(kvm);
6328 if (!kvm->arch.ept_identity_map_addr)
6329 kvm->arch.ept_identity_map_addr =
6330 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6332 if (alloc_identity_pagetable(kvm) != 0)
6334 if (!init_rmode_identity_map(kvm))
6338 vmx->nested.current_vmptr = -1ull;
6339 vmx->nested.current_vmcs12 = NULL;
6344 free_vmcs(vmx->loaded_vmcs->vmcs);
6346 kfree(vmx->guest_msrs);
6348 kvm_vcpu_uninit(&vmx->vcpu);
6351 kmem_cache_free(kvm_vcpu_cache, vmx);
6352 return ERR_PTR(err);
6355 static void __init vmx_check_processor_compat(void *rtn)
6357 struct vmcs_config vmcs_conf;
6360 if (setup_vmcs_config(&vmcs_conf) < 0)
6362 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6363 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6364 smp_processor_id());
6369 static int get_ept_level(void)
6371 return VMX_EPT_DEFAULT_GAW + 1;
6374 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6378 /* For VT-d and EPT combination
6379 * 1. MMIO: always map as UC
6381 * a. VT-d without snooping control feature: can't guarantee the
6382 * result, try to trust guest.
6383 * b. VT-d with snooping control feature: snooping control feature of
6384 * VT-d engine can guarantee the cache correctness. Just set it
6385 * to WB to keep consistent with host. So the same as item 3.
6386 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6387 * consistent with host MTRR
6390 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6391 else if (vcpu->kvm->arch.iommu_domain &&
6392 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6393 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6394 VMX_EPT_MT_EPTE_SHIFT;
6396 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6402 static int vmx_get_lpage_level(void)
6404 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6405 return PT_DIRECTORY_LEVEL;
6407 /* For shadow and EPT supported 1GB page */
6408 return PT_PDPE_LEVEL;
6411 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6413 struct kvm_cpuid_entry2 *best;
6414 struct vcpu_vmx *vmx = to_vmx(vcpu);
6417 vmx->rdtscp_enabled = false;
6418 if (vmx_rdtscp_supported()) {
6419 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6420 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6421 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6422 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6423 vmx->rdtscp_enabled = true;
6425 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6426 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6433 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6435 if (func == 1 && nested)
6436 entry->ecx |= bit(X86_FEATURE_VMX);
6440 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6441 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6442 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6443 * guest in a way that will both be appropriate to L1's requests, and our
6444 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6445 * function also has additional necessary side-effects, like setting various
6446 * vcpu->arch fields.
6448 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6450 struct vcpu_vmx *vmx = to_vmx(vcpu);
6453 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6454 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6455 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6456 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6457 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6458 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6459 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6460 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6461 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6462 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6463 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6464 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6465 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6466 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6467 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6468 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6469 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6470 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6471 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6472 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6473 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6474 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6475 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6476 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6477 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6478 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6479 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6480 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6481 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6482 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6483 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6484 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6485 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6486 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6487 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6488 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6490 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6491 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6492 vmcs12->vm_entry_intr_info_field);
6493 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6494 vmcs12->vm_entry_exception_error_code);
6495 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6496 vmcs12->vm_entry_instruction_len);
6497 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6498 vmcs12->guest_interruptibility_info);
6499 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6500 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6501 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6502 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6503 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6504 vmcs12->guest_pending_dbg_exceptions);
6505 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6506 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6508 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6510 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6511 (vmcs_config.pin_based_exec_ctrl |
6512 vmcs12->pin_based_vm_exec_control));
6515 * Whether page-faults are trapped is determined by a combination of
6516 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6517 * If enable_ept, L0 doesn't care about page faults and we should
6518 * set all of these to L1's desires. However, if !enable_ept, L0 does
6519 * care about (at least some) page faults, and because it is not easy
6520 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6521 * to exit on each and every L2 page fault. This is done by setting
6522 * MASK=MATCH=0 and (see below) EB.PF=1.
6523 * Note that below we don't need special code to set EB.PF beyond the
6524 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6525 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6526 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6528 * A problem with this approach (when !enable_ept) is that L1 may be
6529 * injected with more page faults than it asked for. This could have
6530 * caused problems, but in practice existing hypervisors don't care.
6531 * To fix this, we will need to emulate the PFEC checking (on the L1
6532 * page tables), using walk_addr(), when injecting PFs to L1.
6534 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6535 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6536 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6537 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6539 if (cpu_has_secondary_exec_ctrls()) {
6540 u32 exec_control = vmx_secondary_exec_control(vmx);
6541 if (!vmx->rdtscp_enabled)
6542 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6543 /* Take the following fields only from vmcs12 */
6544 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6545 if (nested_cpu_has(vmcs12,
6546 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6547 exec_control |= vmcs12->secondary_vm_exec_control;
6549 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6551 * Translate L1 physical address to host physical
6552 * address for vmcs02. Keep the page pinned, so this
6553 * physical address remains valid. We keep a reference
6554 * to it so we can release it later.
6556 if (vmx->nested.apic_access_page) /* shouldn't happen */
6557 nested_release_page(vmx->nested.apic_access_page);
6558 vmx->nested.apic_access_page =
6559 nested_get_page(vcpu, vmcs12->apic_access_addr);
6561 * If translation failed, no matter: This feature asks
6562 * to exit when accessing the given address, and if it
6563 * can never be accessed, this feature won't do
6566 if (!vmx->nested.apic_access_page)
6568 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6570 vmcs_write64(APIC_ACCESS_ADDR,
6571 page_to_phys(vmx->nested.apic_access_page));
6574 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6579 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6580 * Some constant fields are set here by vmx_set_constant_host_state().
6581 * Other fields are different per CPU, and will be set later when
6582 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6584 vmx_set_constant_host_state();
6587 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6588 * entry, but only if the current (host) sp changed from the value
6589 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6590 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6591 * here we just force the write to happen on entry.
6595 exec_control = vmx_exec_control(vmx); /* L0's desires */
6596 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6597 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6598 exec_control &= ~CPU_BASED_TPR_SHADOW;
6599 exec_control |= vmcs12->cpu_based_vm_exec_control;
6601 * Merging of IO and MSR bitmaps not currently supported.
6602 * Rather, exit every time.
6604 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6605 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6606 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6608 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6610 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6611 * bitwise-or of what L1 wants to trap for L2, and what we want to
6612 * trap. Note that CR0.TS also needs updating - we do this later.
6614 update_exception_bitmap(vcpu);
6615 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6616 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6618 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6619 vmcs_write32(VM_EXIT_CONTROLS,
6620 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6621 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6622 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6624 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6625 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6626 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6627 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6630 set_cr4_guest_host_mask(vmx);
6632 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6633 vmcs_write64(TSC_OFFSET,
6634 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6636 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6640 * Trivially support vpid by letting L2s share their parent
6641 * L1's vpid. TODO: move to a more elaborate solution, giving
6642 * each L2 its own vpid and exposing the vpid feature to L1.
6644 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6645 vmx_flush_tlb(vcpu);
6648 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6649 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6650 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6651 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6653 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6654 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6655 vmx_set_efer(vcpu, vcpu->arch.efer);
6658 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6659 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6660 * The CR0_READ_SHADOW is what L2 should have expected to read given
6661 * the specifications by L1; It's not enough to take
6662 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6663 * have more bits than L1 expected.
6665 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6666 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6668 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6669 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6671 /* shadow page tables on either EPT or shadow page tables */
6672 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6673 kvm_mmu_reset_context(vcpu);
6675 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6676 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6680 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6681 * for running an L2 nested guest.
6683 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6685 struct vmcs12 *vmcs12;
6686 struct vcpu_vmx *vmx = to_vmx(vcpu);
6688 struct loaded_vmcs *vmcs02;
6690 if (!nested_vmx_check_permission(vcpu) ||
6691 !nested_vmx_check_vmcs12(vcpu))
6694 skip_emulated_instruction(vcpu);
6695 vmcs12 = get_vmcs12(vcpu);
6698 * The nested entry process starts with enforcing various prerequisites
6699 * on vmcs12 as required by the Intel SDM, and act appropriately when
6700 * they fail: As the SDM explains, some conditions should cause the
6701 * instruction to fail, while others will cause the instruction to seem
6702 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6703 * To speed up the normal (success) code path, we should avoid checking
6704 * for misconfigurations which will anyway be caught by the processor
6705 * when using the merged vmcs02.
6707 if (vmcs12->launch_state == launch) {
6708 nested_vmx_failValid(vcpu,
6709 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6710 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6714 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6715 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6716 /*TODO: Also verify bits beyond physical address width are 0*/
6717 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6721 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6722 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6723 /*TODO: Also verify bits beyond physical address width are 0*/
6724 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6728 if (vmcs12->vm_entry_msr_load_count > 0 ||
6729 vmcs12->vm_exit_msr_load_count > 0 ||
6730 vmcs12->vm_exit_msr_store_count > 0) {
6731 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6733 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6737 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6738 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6739 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6740 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6741 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6742 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6743 !vmx_control_verify(vmcs12->vm_exit_controls,
6744 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6745 !vmx_control_verify(vmcs12->vm_entry_controls,
6746 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6748 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6752 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6753 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6754 nested_vmx_failValid(vcpu,
6755 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6759 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6760 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6761 nested_vmx_entry_failure(vcpu, vmcs12,
6762 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6765 if (vmcs12->vmcs_link_pointer != -1ull) {
6766 nested_vmx_entry_failure(vcpu, vmcs12,
6767 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6772 * We're finally done with prerequisite checking, and can start with
6776 vmcs02 = nested_get_current_vmcs02(vmx);
6780 enter_guest_mode(vcpu);
6782 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6785 vmx->loaded_vmcs = vmcs02;
6787 vmx_vcpu_load(vcpu, cpu);
6791 vmcs12->launch_state = 1;
6793 prepare_vmcs02(vcpu, vmcs12);
6796 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6797 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6798 * returned as far as L1 is concerned. It will only return (and set
6799 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6805 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6806 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6807 * This function returns the new value we should put in vmcs12.guest_cr0.
6808 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6809 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6810 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6811 * didn't trap the bit, because if L1 did, so would L0).
6812 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6813 * been modified by L2, and L1 knows it. So just leave the old value of
6814 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6815 * isn't relevant, because if L0 traps this bit it can set it to anything.
6816 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6817 * changed these bits, and therefore they need to be updated, but L0
6818 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6819 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6821 static inline unsigned long
6822 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6825 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6826 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6827 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6828 vcpu->arch.cr0_guest_owned_bits));
6831 static inline unsigned long
6832 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6835 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6836 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6837 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6838 vcpu->arch.cr4_guest_owned_bits));
6842 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6843 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6844 * and this function updates it to reflect the changes to the guest state while
6845 * L2 was running (and perhaps made some exits which were handled directly by L0
6846 * without going back to L1), and to reflect the exit reason.
6847 * Note that we do not have to copy here all VMCS fields, just those that
6848 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6849 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6850 * which already writes to vmcs12 directly.
6852 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6854 /* update guest state fields: */
6855 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6856 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6858 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6859 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6860 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6861 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6863 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6864 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6865 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6866 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6867 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6868 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6869 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6870 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6871 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6872 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6873 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6874 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6875 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6876 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6877 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6878 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6879 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6880 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6881 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6882 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6883 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6884 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6885 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6886 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6887 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6888 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6889 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6890 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6891 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6892 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6893 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6894 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6895 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6896 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6897 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6898 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6900 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6901 vmcs12->guest_interruptibility_info =
6902 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6903 vmcs12->guest_pending_dbg_exceptions =
6904 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6906 /* TODO: These cannot have changed unless we have MSR bitmaps and
6907 * the relevant bit asks not to trap the change */
6908 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6909 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6910 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6911 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6912 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6913 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6915 /* update exit information fields: */
6917 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6918 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6920 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6921 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6922 vmcs12->idt_vectoring_info_field =
6923 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6924 vmcs12->idt_vectoring_error_code =
6925 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6926 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6927 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6929 /* clear vm-entry fields which are to be cleared on exit */
6930 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6931 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6935 * A part of what we need to when the nested L2 guest exits and we want to
6936 * run its L1 parent, is to reset L1's guest state to the host state specified
6938 * This function is to be called not only on normal nested exit, but also on
6939 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6940 * Failures During or After Loading Guest State").
6941 * This function should be called when the active VMCS is L1's (vmcs01).
6943 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6945 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6946 vcpu->arch.efer = vmcs12->host_ia32_efer;
6947 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6948 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6950 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6951 vmx_set_efer(vcpu, vcpu->arch.efer);
6953 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6954 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6956 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6957 * actually changed, because it depends on the current state of
6958 * fpu_active (which may have changed).
6959 * Note that vmx_set_cr0 refers to efer set above.
6961 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6963 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6964 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6965 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6967 update_exception_bitmap(vcpu);
6968 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6969 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6972 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6973 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6975 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6976 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6978 /* shadow page tables on either EPT or shadow page tables */
6979 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6980 kvm_mmu_reset_context(vcpu);
6984 * Trivially support vpid by letting L2s share their parent
6985 * L1's vpid. TODO: move to a more elaborate solution, giving
6986 * each L2 its own vpid and exposing the vpid feature to L1.
6988 vmx_flush_tlb(vcpu);
6992 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6993 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6994 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6995 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6996 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6997 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6998 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6999 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7000 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7001 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7002 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7003 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7004 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7005 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7006 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7008 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7009 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7010 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7011 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7012 vmcs12->host_ia32_perf_global_ctrl);
7016 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7017 * and modify vmcs12 to make it see what it would expect to see there if
7018 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7020 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7022 struct vcpu_vmx *vmx = to_vmx(vcpu);
7024 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7026 leave_guest_mode(vcpu);
7027 prepare_vmcs12(vcpu, vmcs12);
7030 vmx->loaded_vmcs = &vmx->vmcs01;
7032 vmx_vcpu_load(vcpu, cpu);
7036 /* if no vmcs02 cache requested, remove the one we used */
7037 if (VMCS02_POOL_SIZE == 0)
7038 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7040 load_vmcs12_host_state(vcpu, vmcs12);
7042 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7043 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7045 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7048 /* Unpin physical memory we referred to in vmcs02 */
7049 if (vmx->nested.apic_access_page) {
7050 nested_release_page(vmx->nested.apic_access_page);
7051 vmx->nested.apic_access_page = 0;
7055 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7056 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7057 * success or failure flag accordingly.
7059 if (unlikely(vmx->fail)) {
7061 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7063 nested_vmx_succeed(vcpu);
7067 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7068 * 23.7 "VM-entry failures during or after loading guest state" (this also
7069 * lists the acceptable exit-reason and exit-qualification parameters).
7070 * It should only be called before L2 actually succeeded to run, and when
7071 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7073 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7074 struct vmcs12 *vmcs12,
7075 u32 reason, unsigned long qualification)
7077 load_vmcs12_host_state(vcpu, vmcs12);
7078 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7079 vmcs12->exit_qualification = qualification;
7080 nested_vmx_succeed(vcpu);
7083 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7084 struct x86_instruction_info *info,
7085 enum x86_intercept_stage stage)
7087 return X86EMUL_CONTINUE;
7090 static struct kvm_x86_ops vmx_x86_ops = {
7091 .cpu_has_kvm_support = cpu_has_kvm_support,
7092 .disabled_by_bios = vmx_disabled_by_bios,
7093 .hardware_setup = hardware_setup,
7094 .hardware_unsetup = hardware_unsetup,
7095 .check_processor_compatibility = vmx_check_processor_compat,
7096 .hardware_enable = hardware_enable,
7097 .hardware_disable = hardware_disable,
7098 .cpu_has_accelerated_tpr = report_flexpriority,
7100 .vcpu_create = vmx_create_vcpu,
7101 .vcpu_free = vmx_free_vcpu,
7102 .vcpu_reset = vmx_vcpu_reset,
7104 .prepare_guest_switch = vmx_save_host_state,
7105 .vcpu_load = vmx_vcpu_load,
7106 .vcpu_put = vmx_vcpu_put,
7108 .set_guest_debug = set_guest_debug,
7109 .get_msr = vmx_get_msr,
7110 .set_msr = vmx_set_msr,
7111 .get_segment_base = vmx_get_segment_base,
7112 .get_segment = vmx_get_segment,
7113 .set_segment = vmx_set_segment,
7114 .get_cpl = vmx_get_cpl,
7115 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7116 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7117 .decache_cr3 = vmx_decache_cr3,
7118 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7119 .set_cr0 = vmx_set_cr0,
7120 .set_cr3 = vmx_set_cr3,
7121 .set_cr4 = vmx_set_cr4,
7122 .set_efer = vmx_set_efer,
7123 .get_idt = vmx_get_idt,
7124 .set_idt = vmx_set_idt,
7125 .get_gdt = vmx_get_gdt,
7126 .set_gdt = vmx_set_gdt,
7127 .set_dr7 = vmx_set_dr7,
7128 .cache_reg = vmx_cache_reg,
7129 .get_rflags = vmx_get_rflags,
7130 .set_rflags = vmx_set_rflags,
7131 .fpu_activate = vmx_fpu_activate,
7132 .fpu_deactivate = vmx_fpu_deactivate,
7134 .tlb_flush = vmx_flush_tlb,
7136 .run = vmx_vcpu_run,
7137 .handle_exit = vmx_handle_exit,
7138 .skip_emulated_instruction = skip_emulated_instruction,
7139 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7140 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7141 .patch_hypercall = vmx_patch_hypercall,
7142 .set_irq = vmx_inject_irq,
7143 .set_nmi = vmx_inject_nmi,
7144 .queue_exception = vmx_queue_exception,
7145 .cancel_injection = vmx_cancel_injection,
7146 .interrupt_allowed = vmx_interrupt_allowed,
7147 .nmi_allowed = vmx_nmi_allowed,
7148 .get_nmi_mask = vmx_get_nmi_mask,
7149 .set_nmi_mask = vmx_set_nmi_mask,
7150 .enable_nmi_window = enable_nmi_window,
7151 .enable_irq_window = enable_irq_window,
7152 .update_cr8_intercept = update_cr8_intercept,
7154 .set_tss_addr = vmx_set_tss_addr,
7155 .get_tdp_level = get_ept_level,
7156 .get_mt_mask = vmx_get_mt_mask,
7158 .get_exit_info = vmx_get_exit_info,
7160 .get_lpage_level = vmx_get_lpage_level,
7162 .cpuid_update = vmx_cpuid_update,
7164 .rdtscp_supported = vmx_rdtscp_supported,
7166 .set_supported_cpuid = vmx_set_supported_cpuid,
7168 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7170 .set_tsc_khz = vmx_set_tsc_khz,
7171 .write_tsc_offset = vmx_write_tsc_offset,
7172 .adjust_tsc_offset = vmx_adjust_tsc_offset,
7173 .compute_tsc_offset = vmx_compute_tsc_offset,
7174 .read_l1_tsc = vmx_read_l1_tsc,
7176 .set_tdp_cr3 = vmx_set_cr3,
7178 .check_intercept = vmx_check_intercept,
7181 static int __init vmx_init(void)
7185 rdmsrl_safe(MSR_EFER, &host_efer);
7187 for (i = 0; i < NR_VMX_MSR; ++i)
7188 kvm_define_shared_msr(i, vmx_msr_index[i]);
7190 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7191 if (!vmx_io_bitmap_a)
7194 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7195 if (!vmx_io_bitmap_b) {
7200 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7201 if (!vmx_msr_bitmap_legacy) {
7206 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7207 if (!vmx_msr_bitmap_longmode) {
7213 * Allow direct access to the PC debug port (it is often used for I/O
7214 * delays, but the vmexits simply slow things down).
7216 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7217 clear_bit(0x80, vmx_io_bitmap_a);
7219 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7221 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7222 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7224 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7226 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7227 __alignof__(struct vcpu_vmx), THIS_MODULE);
7231 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7232 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7233 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7234 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7235 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7236 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7239 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7240 VMX_EPT_EXECUTABLE_MASK);
7241 ept_set_mmio_spte_mask();
7249 free_page((unsigned long)vmx_msr_bitmap_longmode);
7251 free_page((unsigned long)vmx_msr_bitmap_legacy);
7253 free_page((unsigned long)vmx_io_bitmap_b);
7255 free_page((unsigned long)vmx_io_bitmap_a);
7259 static void __exit vmx_exit(void)
7261 free_page((unsigned long)vmx_msr_bitmap_legacy);
7262 free_page((unsigned long)vmx_msr_bitmap_longmode);
7263 free_page((unsigned long)vmx_io_bitmap_b);
7264 free_page((unsigned long)vmx_io_bitmap_a);
7269 module_init(vmx_init)
7270 module_exit(vmx_exit)