96515957ba824c0bcecaa3756679258102ae7366
[pandora-kernel.git] / arch / x86 / kvm / mmu.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * MMU support
8  *
9  * Copyright (C) 2006 Qumranet, Inc.
10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11  *
12  * Authors:
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Avi Kivity   <avi@qumranet.com>
15  *
16  * This work is licensed under the terms of the GNU GPL, version 2.  See
17  * the COPYING file in the top-level directory.
18  *
19  */
20
21 #include "irq.h"
22 #include "mmu.h"
23 #include "x86.h"
24 #include "kvm_cache_regs.h"
25 #include "cpuid.h"
26
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
30 #include <linux/mm.h>
31 #include <linux/highmem.h>
32 #include <linux/module.h>
33 #include <linux/swap.h>
34 #include <linux/hugetlb.h>
35 #include <linux/compiler.h>
36 #include <linux/srcu.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39
40 #include <asm/page.h>
41 #include <asm/cmpxchg.h>
42 #include <asm/io.h>
43 #include <asm/vmx.h>
44
45 /*
46  * When setting this variable to true it enables Two-Dimensional-Paging
47  * where the hardware walks 2 page tables:
48  * 1. the guest-virtual to guest-physical
49  * 2. while doing 1. it walks guest-physical to host-physical
50  * If the hardware supports that we don't need to do shadow paging.
51  */
52 bool tdp_enabled = false;
53
54 enum {
55         AUDIT_PRE_PAGE_FAULT,
56         AUDIT_POST_PAGE_FAULT,
57         AUDIT_PRE_PTE_WRITE,
58         AUDIT_POST_PTE_WRITE,
59         AUDIT_PRE_SYNC,
60         AUDIT_POST_SYNC
61 };
62
63 #undef MMU_DEBUG
64
65 #ifdef MMU_DEBUG
66
67 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
68 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
69
70 #else
71
72 #define pgprintk(x...) do { } while (0)
73 #define rmap_printk(x...) do { } while (0)
74
75 #endif
76
77 #ifdef MMU_DEBUG
78 static bool dbg = 0;
79 module_param(dbg, bool, 0644);
80 #endif
81
82 #ifndef MMU_DEBUG
83 #define ASSERT(x) do { } while (0)
84 #else
85 #define ASSERT(x)                                                       \
86         if (!(x)) {                                                     \
87                 printk(KERN_WARNING "assertion failed %s:%d: %s\n",     \
88                        __FILE__, __LINE__, #x);                         \
89         }
90 #endif
91
92 #define PTE_PREFETCH_NUM                8
93
94 #define PT_FIRST_AVAIL_BITS_SHIFT 10
95 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96
97 #define PT64_LEVEL_BITS 9
98
99 #define PT64_LEVEL_SHIFT(level) \
100                 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101
102 #define PT64_INDEX(address, level)\
103         (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
104
105
106 #define PT32_LEVEL_BITS 10
107
108 #define PT32_LEVEL_SHIFT(level) \
109                 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110
111 #define PT32_LVL_OFFSET_MASK(level) \
112         (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
113                                                 * PT32_LEVEL_BITS))) - 1))
114
115 #define PT32_INDEX(address, level)\
116         (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
117
118
119 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
120 #define PT64_DIR_BASE_ADDR_MASK \
121         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
122 #define PT64_LVL_ADDR_MASK(level) \
123         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
124                                                 * PT64_LEVEL_BITS))) - 1))
125 #define PT64_LVL_OFFSET_MASK(level) \
126         (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
127                                                 * PT64_LEVEL_BITS))) - 1))
128
129 #define PT32_BASE_ADDR_MASK PAGE_MASK
130 #define PT32_DIR_BASE_ADDR_MASK \
131         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
132 #define PT32_LVL_ADDR_MASK(level) \
133         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
134                                             * PT32_LEVEL_BITS))) - 1))
135
136 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
137                         | shadow_x_mask | shadow_nx_mask)
138
139 #define ACC_EXEC_MASK    1
140 #define ACC_WRITE_MASK   PT_WRITABLE_MASK
141 #define ACC_USER_MASK    PT_USER_MASK
142 #define ACC_ALL          (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143
144 #include <trace/events/kvm.h>
145
146 #define CREATE_TRACE_POINTS
147 #include "mmutrace.h"
148
149 #define SPTE_HOST_WRITEABLE     (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
150 #define SPTE_MMU_WRITEABLE      (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151
152 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153
154 /* make pte_list_desc fit well in cache line */
155 #define PTE_LIST_EXT 3
156
157 struct pte_list_desc {
158         u64 *sptes[PTE_LIST_EXT];
159         struct pte_list_desc *more;
160 };
161
162 struct kvm_shadow_walk_iterator {
163         u64 addr;
164         hpa_t shadow_addr;
165         u64 *sptep;
166         int level;
167         unsigned index;
168 };
169
170 #define for_each_shadow_entry(_vcpu, _addr, _walker)    \
171         for (shadow_walk_init(&(_walker), _vcpu, _addr);        \
172              shadow_walk_okay(&(_walker));                      \
173              shadow_walk_next(&(_walker)))
174
175 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte)     \
176         for (shadow_walk_init(&(_walker), _vcpu, _addr);                \
177              shadow_walk_okay(&(_walker)) &&                            \
178                 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; });  \
179              __shadow_walk_next(&(_walker), spte))
180
181 static struct kmem_cache *pte_list_desc_cache;
182 static struct kmem_cache *mmu_page_header_cache;
183 static struct percpu_counter kvm_total_used_mmu_pages;
184
185 static u64 __read_mostly shadow_nx_mask;
186 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
187 static u64 __read_mostly shadow_user_mask;
188 static u64 __read_mostly shadow_accessed_mask;
189 static u64 __read_mostly shadow_dirty_mask;
190 static u64 __read_mostly shadow_mmio_mask;
191
192 static void mmu_spte_set(u64 *sptep, u64 spte);
193 static void mmu_free_roots(struct kvm_vcpu *vcpu);
194
195 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
196 {
197         shadow_mmio_mask = mmio_mask;
198 }
199 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
200
201 /*
202  * the low bit of the generation number is always presumed to be zero.
203  * This disables mmio caching during memslot updates.  The concept is
204  * similar to a seqcount but instead of retrying the access we just punt
205  * and ignore the cache.
206  *
207  * spte bits 3-11 are used as bits 1-9 of the generation number,
208  * the bits 52-61 are used as bits 10-19 of the generation number.
209  */
210 #define MMIO_SPTE_GEN_LOW_SHIFT         2
211 #define MMIO_SPTE_GEN_HIGH_SHIFT        52
212
213 #define MMIO_GEN_SHIFT                  20
214 #define MMIO_GEN_LOW_SHIFT              10
215 #define MMIO_GEN_LOW_MASK               ((1 << MMIO_GEN_LOW_SHIFT) - 2)
216 #define MMIO_GEN_MASK                   ((1 << MMIO_GEN_SHIFT) - 1)
217 #define MMIO_MAX_GEN                    ((1 << MMIO_GEN_SHIFT) - 1)
218
219 static u64 generation_mmio_spte_mask(unsigned int gen)
220 {
221         u64 mask;
222
223         WARN_ON(gen > MMIO_MAX_GEN);
224
225         mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
226         mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
227         return mask;
228 }
229
230 static unsigned int get_mmio_spte_generation(u64 spte)
231 {
232         unsigned int gen;
233
234         spte &= ~shadow_mmio_mask;
235
236         gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
237         gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
238         return gen;
239 }
240
241 static unsigned int kvm_current_mmio_generation(struct kvm *kvm)
242 {
243         return kvm_memslots(kvm)->generation & MMIO_GEN_MASK;
244 }
245
246 static void mark_mmio_spte(struct kvm *kvm, u64 *sptep, u64 gfn,
247                            unsigned access)
248 {
249         unsigned int gen = kvm_current_mmio_generation(kvm);
250         u64 mask = generation_mmio_spte_mask(gen);
251
252         access &= ACC_WRITE_MASK | ACC_USER_MASK;
253         mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
254
255         trace_mark_mmio_spte(sptep, gfn, access, gen);
256         mmu_spte_set(sptep, mask);
257 }
258
259 static bool is_mmio_spte(u64 spte)
260 {
261         return (spte & shadow_mmio_mask) == shadow_mmio_mask;
262 }
263
264 static gfn_t get_mmio_spte_gfn(u64 spte)
265 {
266         u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
267         return (spte & ~mask) >> PAGE_SHIFT;
268 }
269
270 static unsigned get_mmio_spte_access(u64 spte)
271 {
272         u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
273         return (spte & ~mask) & ~PAGE_MASK;
274 }
275
276 static bool set_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
277                           pfn_t pfn, unsigned access)
278 {
279         if (unlikely(is_noslot_pfn(pfn))) {
280                 mark_mmio_spte(kvm, sptep, gfn, access);
281                 return true;
282         }
283
284         return false;
285 }
286
287 static bool check_mmio_spte(struct kvm *kvm, u64 spte)
288 {
289         unsigned int kvm_gen, spte_gen;
290
291         kvm_gen = kvm_current_mmio_generation(kvm);
292         spte_gen = get_mmio_spte_generation(spte);
293
294         trace_check_mmio_spte(spte, kvm_gen, spte_gen);
295         return likely(kvm_gen == spte_gen);
296 }
297
298 static inline u64 rsvd_bits(int s, int e)
299 {
300         return ((1ULL << (e - s + 1)) - 1) << s;
301 }
302
303 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
304                 u64 dirty_mask, u64 nx_mask, u64 x_mask)
305 {
306         shadow_user_mask = user_mask;
307         shadow_accessed_mask = accessed_mask;
308         shadow_dirty_mask = dirty_mask;
309         shadow_nx_mask = nx_mask;
310         shadow_x_mask = x_mask;
311 }
312 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
313
314 static int is_cpuid_PSE36(void)
315 {
316         return 1;
317 }
318
319 static int is_nx(struct kvm_vcpu *vcpu)
320 {
321         return vcpu->arch.efer & EFER_NX;
322 }
323
324 static int is_shadow_present_pte(u64 pte)
325 {
326         return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
327 }
328
329 static int is_large_pte(u64 pte)
330 {
331         return pte & PT_PAGE_SIZE_MASK;
332 }
333
334 static int is_rmap_spte(u64 pte)
335 {
336         return is_shadow_present_pte(pte);
337 }
338
339 static int is_last_spte(u64 pte, int level)
340 {
341         if (level == PT_PAGE_TABLE_LEVEL)
342                 return 1;
343         if (is_large_pte(pte))
344                 return 1;
345         return 0;
346 }
347
348 static pfn_t spte_to_pfn(u64 pte)
349 {
350         return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
351 }
352
353 static gfn_t pse36_gfn_delta(u32 gpte)
354 {
355         int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
356
357         return (gpte & PT32_DIR_PSE36_MASK) << shift;
358 }
359
360 #ifdef CONFIG_X86_64
361 static void __set_spte(u64 *sptep, u64 spte)
362 {
363         *sptep = spte;
364 }
365
366 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
367 {
368         *sptep = spte;
369 }
370
371 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
372 {
373         return xchg(sptep, spte);
374 }
375
376 static u64 __get_spte_lockless(u64 *sptep)
377 {
378         return ACCESS_ONCE(*sptep);
379 }
380
381 static bool __check_direct_spte_mmio_pf(u64 spte)
382 {
383         /* It is valid if the spte is zapped. */
384         return spte == 0ull;
385 }
386 #else
387 union split_spte {
388         struct {
389                 u32 spte_low;
390                 u32 spte_high;
391         };
392         u64 spte;
393 };
394
395 static void count_spte_clear(u64 *sptep, u64 spte)
396 {
397         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
398
399         if (is_shadow_present_pte(spte))
400                 return;
401
402         /* Ensure the spte is completely set before we increase the count */
403         smp_wmb();
404         sp->clear_spte_count++;
405 }
406
407 static void __set_spte(u64 *sptep, u64 spte)
408 {
409         union split_spte *ssptep, sspte;
410
411         ssptep = (union split_spte *)sptep;
412         sspte = (union split_spte)spte;
413
414         ssptep->spte_high = sspte.spte_high;
415
416         /*
417          * If we map the spte from nonpresent to present, We should store
418          * the high bits firstly, then set present bit, so cpu can not
419          * fetch this spte while we are setting the spte.
420          */
421         smp_wmb();
422
423         ssptep->spte_low = sspte.spte_low;
424 }
425
426 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
427 {
428         union split_spte *ssptep, sspte;
429
430         ssptep = (union split_spte *)sptep;
431         sspte = (union split_spte)spte;
432
433         ssptep->spte_low = sspte.spte_low;
434
435         /*
436          * If we map the spte from present to nonpresent, we should clear
437          * present bit firstly to avoid vcpu fetch the old high bits.
438          */
439         smp_wmb();
440
441         ssptep->spte_high = sspte.spte_high;
442         count_spte_clear(sptep, spte);
443 }
444
445 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
446 {
447         union split_spte *ssptep, sspte, orig;
448
449         ssptep = (union split_spte *)sptep;
450         sspte = (union split_spte)spte;
451
452         /* xchg acts as a barrier before the setting of the high bits */
453         orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
454         orig.spte_high = ssptep->spte_high;
455         ssptep->spte_high = sspte.spte_high;
456         count_spte_clear(sptep, spte);
457
458         return orig.spte;
459 }
460
461 /*
462  * The idea using the light way get the spte on x86_32 guest is from
463  * gup_get_pte(arch/x86/mm/gup.c).
464  *
465  * An spte tlb flush may be pending, because kvm_set_pte_rmapp
466  * coalesces them and we are running out of the MMU lock.  Therefore
467  * we need to protect against in-progress updates of the spte.
468  *
469  * Reading the spte while an update is in progress may get the old value
470  * for the high part of the spte.  The race is fine for a present->non-present
471  * change (because the high part of the spte is ignored for non-present spte),
472  * but for a present->present change we must reread the spte.
473  *
474  * All such changes are done in two steps (present->non-present and
475  * non-present->present), hence it is enough to count the number of
476  * present->non-present updates: if it changed while reading the spte,
477  * we might have hit the race.  This is done using clear_spte_count.
478  */
479 static u64 __get_spte_lockless(u64 *sptep)
480 {
481         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
482         union split_spte spte, *orig = (union split_spte *)sptep;
483         int count;
484
485 retry:
486         count = sp->clear_spte_count;
487         smp_rmb();
488
489         spte.spte_low = orig->spte_low;
490         smp_rmb();
491
492         spte.spte_high = orig->spte_high;
493         smp_rmb();
494
495         if (unlikely(spte.spte_low != orig->spte_low ||
496               count != sp->clear_spte_count))
497                 goto retry;
498
499         return spte.spte;
500 }
501
502 static bool __check_direct_spte_mmio_pf(u64 spte)
503 {
504         union split_spte sspte = (union split_spte)spte;
505         u32 high_mmio_mask = shadow_mmio_mask >> 32;
506
507         /* It is valid if the spte is zapped. */
508         if (spte == 0ull)
509                 return true;
510
511         /* It is valid if the spte is being zapped. */
512         if (sspte.spte_low == 0ull &&
513             (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
514                 return true;
515
516         return false;
517 }
518 #endif
519
520 static bool spte_is_locklessly_modifiable(u64 spte)
521 {
522         return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
523                 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
524 }
525
526 static bool spte_has_volatile_bits(u64 spte)
527 {
528         /*
529          * Always atomicly update spte if it can be updated
530          * out of mmu-lock, it can ensure dirty bit is not lost,
531          * also, it can help us to get a stable is_writable_pte()
532          * to ensure tlb flush is not missed.
533          */
534         if (spte_is_locklessly_modifiable(spte))
535                 return true;
536
537         if (!shadow_accessed_mask)
538                 return false;
539
540         if (!is_shadow_present_pte(spte))
541                 return false;
542
543         if ((spte & shadow_accessed_mask) &&
544               (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
545                 return false;
546
547         return true;
548 }
549
550 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
551 {
552         return (old_spte & bit_mask) && !(new_spte & bit_mask);
553 }
554
555 /* Rules for using mmu_spte_set:
556  * Set the sptep from nonpresent to present.
557  * Note: the sptep being assigned *must* be either not present
558  * or in a state where the hardware will not attempt to update
559  * the spte.
560  */
561 static void mmu_spte_set(u64 *sptep, u64 new_spte)
562 {
563         WARN_ON(is_shadow_present_pte(*sptep));
564         __set_spte(sptep, new_spte);
565 }
566
567 /* Rules for using mmu_spte_update:
568  * Update the state bits, it means the mapped pfn is not changged.
569  *
570  * Whenever we overwrite a writable spte with a read-only one we
571  * should flush remote TLBs. Otherwise rmap_write_protect
572  * will find a read-only spte, even though the writable spte
573  * might be cached on a CPU's TLB, the return value indicates this
574  * case.
575  */
576 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
577 {
578         u64 old_spte = *sptep;
579         bool ret = false;
580
581         WARN_ON(!is_rmap_spte(new_spte));
582
583         if (!is_shadow_present_pte(old_spte)) {
584                 mmu_spte_set(sptep, new_spte);
585                 return ret;
586         }
587
588         if (!spte_has_volatile_bits(old_spte))
589                 __update_clear_spte_fast(sptep, new_spte);
590         else
591                 old_spte = __update_clear_spte_slow(sptep, new_spte);
592
593         /*
594          * For the spte updated out of mmu-lock is safe, since
595          * we always atomicly update it, see the comments in
596          * spte_has_volatile_bits().
597          */
598         if (spte_is_locklessly_modifiable(old_spte) &&
599               !is_writable_pte(new_spte))
600                 ret = true;
601
602         if (!shadow_accessed_mask)
603                 return ret;
604
605         if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
606                 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
607         if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
608                 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
609
610         return ret;
611 }
612
613 /*
614  * Rules for using mmu_spte_clear_track_bits:
615  * It sets the sptep from present to nonpresent, and track the
616  * state bits, it is used to clear the last level sptep.
617  */
618 static int mmu_spte_clear_track_bits(u64 *sptep)
619 {
620         pfn_t pfn;
621         u64 old_spte = *sptep;
622
623         if (!spte_has_volatile_bits(old_spte))
624                 __update_clear_spte_fast(sptep, 0ull);
625         else
626                 old_spte = __update_clear_spte_slow(sptep, 0ull);
627
628         if (!is_rmap_spte(old_spte))
629                 return 0;
630
631         pfn = spte_to_pfn(old_spte);
632
633         /*
634          * KVM does not hold the refcount of the page used by
635          * kvm mmu, before reclaiming the page, we should
636          * unmap it from mmu first.
637          */
638         WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn)));
639
640         if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
641                 kvm_set_pfn_accessed(pfn);
642         if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
643                 kvm_set_pfn_dirty(pfn);
644         return 1;
645 }
646
647 /*
648  * Rules for using mmu_spte_clear_no_track:
649  * Directly clear spte without caring the state bits of sptep,
650  * it is used to set the upper level spte.
651  */
652 static void mmu_spte_clear_no_track(u64 *sptep)
653 {
654         __update_clear_spte_fast(sptep, 0ull);
655 }
656
657 static u64 mmu_spte_get_lockless(u64 *sptep)
658 {
659         return __get_spte_lockless(sptep);
660 }
661
662 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
663 {
664         /*
665          * Prevent page table teardown by making any free-er wait during
666          * kvm_flush_remote_tlbs() IPI to all active vcpus.
667          */
668         local_irq_disable();
669         vcpu->mode = READING_SHADOW_PAGE_TABLES;
670         /*
671          * Make sure a following spte read is not reordered ahead of the write
672          * to vcpu->mode.
673          */
674         smp_mb();
675 }
676
677 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
678 {
679         /*
680          * Make sure the write to vcpu->mode is not reordered in front of
681          * reads to sptes.  If it does, kvm_commit_zap_page() can see us
682          * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
683          */
684         smp_mb();
685         vcpu->mode = OUTSIDE_GUEST_MODE;
686         local_irq_enable();
687 }
688
689 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
690                                   struct kmem_cache *base_cache, int min)
691 {
692         void *obj;
693
694         if (cache->nobjs >= min)
695                 return 0;
696         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
697                 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
698                 if (!obj)
699                         return -ENOMEM;
700                 cache->objects[cache->nobjs++] = obj;
701         }
702         return 0;
703 }
704
705 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
706 {
707         return cache->nobjs;
708 }
709
710 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
711                                   struct kmem_cache *cache)
712 {
713         while (mc->nobjs)
714                 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
715 }
716
717 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
718                                        int min)
719 {
720         void *page;
721
722         if (cache->nobjs >= min)
723                 return 0;
724         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
725                 page = (void *)__get_free_page(GFP_KERNEL);
726                 if (!page)
727                         return -ENOMEM;
728                 cache->objects[cache->nobjs++] = page;
729         }
730         return 0;
731 }
732
733 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
734 {
735         while (mc->nobjs)
736                 free_page((unsigned long)mc->objects[--mc->nobjs]);
737 }
738
739 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
740 {
741         int r;
742
743         r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
744                                    pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
745         if (r)
746                 goto out;
747         r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
748         if (r)
749                 goto out;
750         r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
751                                    mmu_page_header_cache, 4);
752 out:
753         return r;
754 }
755
756 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
757 {
758         mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
759                                 pte_list_desc_cache);
760         mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
761         mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
762                                 mmu_page_header_cache);
763 }
764
765 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
766 {
767         void *p;
768
769         BUG_ON(!mc->nobjs);
770         p = mc->objects[--mc->nobjs];
771         return p;
772 }
773
774 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
775 {
776         return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
777 }
778
779 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
780 {
781         kmem_cache_free(pte_list_desc_cache, pte_list_desc);
782 }
783
784 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
785 {
786         if (!sp->role.direct)
787                 return sp->gfns[index];
788
789         return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
790 }
791
792 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
793 {
794         if (sp->role.direct)
795                 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
796         else
797                 sp->gfns[index] = gfn;
798 }
799
800 /*
801  * Return the pointer to the large page information for a given gfn,
802  * handling slots that are not large page aligned.
803  */
804 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
805                                               struct kvm_memory_slot *slot,
806                                               int level)
807 {
808         unsigned long idx;
809
810         idx = gfn_to_index(gfn, slot->base_gfn, level);
811         return &slot->arch.lpage_info[level - 2][idx];
812 }
813
814 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
815 {
816         struct kvm_memory_slot *slot;
817         struct kvm_lpage_info *linfo;
818         int i;
819
820         slot = gfn_to_memslot(kvm, gfn);
821         for (i = PT_DIRECTORY_LEVEL;
822              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
823                 linfo = lpage_info_slot(gfn, slot, i);
824                 linfo->write_count += 1;
825         }
826         kvm->arch.indirect_shadow_pages++;
827 }
828
829 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
830 {
831         struct kvm_memory_slot *slot;
832         struct kvm_lpage_info *linfo;
833         int i;
834
835         slot = gfn_to_memslot(kvm, gfn);
836         for (i = PT_DIRECTORY_LEVEL;
837              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
838                 linfo = lpage_info_slot(gfn, slot, i);
839                 linfo->write_count -= 1;
840                 WARN_ON(linfo->write_count < 0);
841         }
842         kvm->arch.indirect_shadow_pages--;
843 }
844
845 static int has_wrprotected_page(struct kvm *kvm,
846                                 gfn_t gfn,
847                                 int level)
848 {
849         struct kvm_memory_slot *slot;
850         struct kvm_lpage_info *linfo;
851
852         slot = gfn_to_memslot(kvm, gfn);
853         if (slot) {
854                 linfo = lpage_info_slot(gfn, slot, level);
855                 return linfo->write_count;
856         }
857
858         return 1;
859 }
860
861 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
862 {
863         unsigned long page_size;
864         int i, ret = 0;
865
866         page_size = kvm_host_page_size(kvm, gfn);
867
868         for (i = PT_PAGE_TABLE_LEVEL;
869              i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
870                 if (page_size >= KVM_HPAGE_SIZE(i))
871                         ret = i;
872                 else
873                         break;
874         }
875
876         return ret;
877 }
878
879 static struct kvm_memory_slot *
880 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
881                             bool no_dirty_log)
882 {
883         struct kvm_memory_slot *slot;
884
885         slot = gfn_to_memslot(vcpu->kvm, gfn);
886         if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
887               (no_dirty_log && slot->dirty_bitmap))
888                 slot = NULL;
889
890         return slot;
891 }
892
893 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
894 {
895         return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
896 }
897
898 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
899 {
900         int host_level, level, max_level;
901
902         host_level = host_mapping_level(vcpu->kvm, large_gfn);
903
904         if (host_level == PT_PAGE_TABLE_LEVEL)
905                 return host_level;
906
907         max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
908
909         for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
910                 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
911                         break;
912
913         return level - 1;
914 }
915
916 /*
917  * Pte mapping structures:
918  *
919  * If pte_list bit zero is zero, then pte_list point to the spte.
920  *
921  * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
922  * pte_list_desc containing more mappings.
923  *
924  * Returns the number of pte entries before the spte was added or zero if
925  * the spte was not added.
926  *
927  */
928 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
929                         unsigned long *pte_list)
930 {
931         struct pte_list_desc *desc;
932         int i, count = 0;
933
934         if (!*pte_list) {
935                 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
936                 *pte_list = (unsigned long)spte;
937         } else if (!(*pte_list & 1)) {
938                 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
939                 desc = mmu_alloc_pte_list_desc(vcpu);
940                 desc->sptes[0] = (u64 *)*pte_list;
941                 desc->sptes[1] = spte;
942                 *pte_list = (unsigned long)desc | 1;
943                 ++count;
944         } else {
945                 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
946                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
947                 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
948                         desc = desc->more;
949                         count += PTE_LIST_EXT;
950                 }
951                 if (desc->sptes[PTE_LIST_EXT-1]) {
952                         desc->more = mmu_alloc_pte_list_desc(vcpu);
953                         desc = desc->more;
954                 }
955                 for (i = 0; desc->sptes[i]; ++i)
956                         ++count;
957                 desc->sptes[i] = spte;
958         }
959         return count;
960 }
961
962 static void
963 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
964                            int i, struct pte_list_desc *prev_desc)
965 {
966         int j;
967
968         for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
969                 ;
970         desc->sptes[i] = desc->sptes[j];
971         desc->sptes[j] = NULL;
972         if (j != 0)
973                 return;
974         if (!prev_desc && !desc->more)
975                 *pte_list = (unsigned long)desc->sptes[0];
976         else
977                 if (prev_desc)
978                         prev_desc->more = desc->more;
979                 else
980                         *pte_list = (unsigned long)desc->more | 1;
981         mmu_free_pte_list_desc(desc);
982 }
983
984 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
985 {
986         struct pte_list_desc *desc;
987         struct pte_list_desc *prev_desc;
988         int i;
989
990         if (!*pte_list) {
991                 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
992                 BUG();
993         } else if (!(*pte_list & 1)) {
994                 rmap_printk("pte_list_remove:  %p 1->0\n", spte);
995                 if ((u64 *)*pte_list != spte) {
996                         printk(KERN_ERR "pte_list_remove:  %p 1->BUG\n", spte);
997                         BUG();
998                 }
999                 *pte_list = 0;
1000         } else {
1001                 rmap_printk("pte_list_remove:  %p many->many\n", spte);
1002                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
1003                 prev_desc = NULL;
1004                 while (desc) {
1005                         for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
1006                                 if (desc->sptes[i] == spte) {
1007                                         pte_list_desc_remove_entry(pte_list,
1008                                                                desc, i,
1009                                                                prev_desc);
1010                                         return;
1011                                 }
1012                         prev_desc = desc;
1013                         desc = desc->more;
1014                 }
1015                 pr_err("pte_list_remove: %p many->many\n", spte);
1016                 BUG();
1017         }
1018 }
1019
1020 typedef void (*pte_list_walk_fn) (u64 *spte);
1021 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
1022 {
1023         struct pte_list_desc *desc;
1024         int i;
1025
1026         if (!*pte_list)
1027                 return;
1028
1029         if (!(*pte_list & 1))
1030                 return fn((u64 *)*pte_list);
1031
1032         desc = (struct pte_list_desc *)(*pte_list & ~1ul);
1033         while (desc) {
1034                 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
1035                         fn(desc->sptes[i]);
1036                 desc = desc->more;
1037         }
1038 }
1039
1040 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
1041                                     struct kvm_memory_slot *slot)
1042 {
1043         unsigned long idx;
1044
1045         idx = gfn_to_index(gfn, slot->base_gfn, level);
1046         return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1047 }
1048
1049 /*
1050  * Take gfn and return the reverse mapping to it.
1051  */
1052 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
1053 {
1054         struct kvm_memory_slot *slot;
1055
1056         slot = gfn_to_memslot(kvm, gfn);
1057         return __gfn_to_rmap(gfn, level, slot);
1058 }
1059
1060 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1061 {
1062         struct kvm_mmu_memory_cache *cache;
1063
1064         cache = &vcpu->arch.mmu_pte_list_desc_cache;
1065         return mmu_memory_cache_free_objects(cache);
1066 }
1067
1068 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1069 {
1070         struct kvm_mmu_page *sp;
1071         unsigned long *rmapp;
1072
1073         sp = page_header(__pa(spte));
1074         kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1075         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1076         return pte_list_add(vcpu, spte, rmapp);
1077 }
1078
1079 static void rmap_remove(struct kvm *kvm, u64 *spte)
1080 {
1081         struct kvm_mmu_page *sp;
1082         gfn_t gfn;
1083         unsigned long *rmapp;
1084
1085         sp = page_header(__pa(spte));
1086         gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1087         rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1088         pte_list_remove(spte, rmapp);
1089 }
1090
1091 /*
1092  * Used by the following functions to iterate through the sptes linked by a
1093  * rmap.  All fields are private and not assumed to be used outside.
1094  */
1095 struct rmap_iterator {
1096         /* private fields */
1097         struct pte_list_desc *desc;     /* holds the sptep if not NULL */
1098         int pos;                        /* index of the sptep */
1099 };
1100
1101 /*
1102  * Iteration must be started by this function.  This should also be used after
1103  * removing/dropping sptes from the rmap link because in such cases the
1104  * information in the itererator may not be valid.
1105  *
1106  * Returns sptep if found, NULL otherwise.
1107  */
1108 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1109 {
1110         if (!rmap)
1111                 return NULL;
1112
1113         if (!(rmap & 1)) {
1114                 iter->desc = NULL;
1115                 return (u64 *)rmap;
1116         }
1117
1118         iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1119         iter->pos = 0;
1120         return iter->desc->sptes[iter->pos];
1121 }
1122
1123 /*
1124  * Must be used with a valid iterator: e.g. after rmap_get_first().
1125  *
1126  * Returns sptep if found, NULL otherwise.
1127  */
1128 static u64 *rmap_get_next(struct rmap_iterator *iter)
1129 {
1130         if (iter->desc) {
1131                 if (iter->pos < PTE_LIST_EXT - 1) {
1132                         u64 *sptep;
1133
1134                         ++iter->pos;
1135                         sptep = iter->desc->sptes[iter->pos];
1136                         if (sptep)
1137                                 return sptep;
1138                 }
1139
1140                 iter->desc = iter->desc->more;
1141
1142                 if (iter->desc) {
1143                         iter->pos = 0;
1144                         /* desc->sptes[0] cannot be NULL */
1145                         return iter->desc->sptes[iter->pos];
1146                 }
1147         }
1148
1149         return NULL;
1150 }
1151
1152 static void drop_spte(struct kvm *kvm, u64 *sptep)
1153 {
1154         if (mmu_spte_clear_track_bits(sptep))
1155                 rmap_remove(kvm, sptep);
1156 }
1157
1158
1159 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1160 {
1161         if (is_large_pte(*sptep)) {
1162                 WARN_ON(page_header(__pa(sptep))->role.level ==
1163                         PT_PAGE_TABLE_LEVEL);
1164                 drop_spte(kvm, sptep);
1165                 --kvm->stat.lpages;
1166                 return true;
1167         }
1168
1169         return false;
1170 }
1171
1172 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1173 {
1174         if (__drop_large_spte(vcpu->kvm, sptep))
1175                 kvm_flush_remote_tlbs(vcpu->kvm);
1176 }
1177
1178 /*
1179  * Write-protect on the specified @sptep, @pt_protect indicates whether
1180  * spte write-protection is caused by protecting shadow page table.
1181  *
1182  * Note: write protection is difference between drity logging and spte
1183  * protection:
1184  * - for dirty logging, the spte can be set to writable at anytime if
1185  *   its dirty bitmap is properly set.
1186  * - for spte protection, the spte can be writable only after unsync-ing
1187  *   shadow page.
1188  *
1189  * Return true if tlb need be flushed.
1190  */
1191 static bool spte_write_protect(struct kvm *kvm, u64 *sptep, bool pt_protect)
1192 {
1193         u64 spte = *sptep;
1194
1195         if (!is_writable_pte(spte) &&
1196               !(pt_protect && spte_is_locklessly_modifiable(spte)))
1197                 return false;
1198
1199         rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1200
1201         if (pt_protect)
1202                 spte &= ~SPTE_MMU_WRITEABLE;
1203         spte = spte & ~PT_WRITABLE_MASK;
1204
1205         return mmu_spte_update(sptep, spte);
1206 }
1207
1208 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1209                                  bool pt_protect)
1210 {
1211         u64 *sptep;
1212         struct rmap_iterator iter;
1213         bool flush = false;
1214
1215         for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1216                 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1217
1218                 flush |= spte_write_protect(kvm, sptep, pt_protect);
1219                 sptep = rmap_get_next(&iter);
1220         }
1221
1222         return flush;
1223 }
1224
1225 /**
1226  * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1227  * @kvm: kvm instance
1228  * @slot: slot to protect
1229  * @gfn_offset: start of the BITS_PER_LONG pages we care about
1230  * @mask: indicates which pages we should protect
1231  *
1232  * Used when we do not need to care about huge page mappings: e.g. during dirty
1233  * logging we do not have any such mappings.
1234  */
1235 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1236                                      struct kvm_memory_slot *slot,
1237                                      gfn_t gfn_offset, unsigned long mask)
1238 {
1239         unsigned long *rmapp;
1240
1241         while (mask) {
1242                 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1243                                       PT_PAGE_TABLE_LEVEL, slot);
1244                 __rmap_write_protect(kvm, rmapp, false);
1245
1246                 /* clear the first set bit */
1247                 mask &= mask - 1;
1248         }
1249 }
1250
1251 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1252 {
1253         struct kvm_memory_slot *slot;
1254         unsigned long *rmapp;
1255         int i;
1256         bool write_protected = false;
1257
1258         slot = gfn_to_memslot(kvm, gfn);
1259
1260         for (i = PT_PAGE_TABLE_LEVEL;
1261              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1262                 rmapp = __gfn_to_rmap(gfn, i, slot);
1263                 write_protected |= __rmap_write_protect(kvm, rmapp, true);
1264         }
1265
1266         return write_protected;
1267 }
1268
1269 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1270                            struct kvm_memory_slot *slot, unsigned long data)
1271 {
1272         u64 *sptep;
1273         struct rmap_iterator iter;
1274         int need_tlb_flush = 0;
1275
1276         while ((sptep = rmap_get_first(*rmapp, &iter))) {
1277                 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1278                 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1279
1280                 drop_spte(kvm, sptep);
1281                 need_tlb_flush = 1;
1282         }
1283
1284         return need_tlb_flush;
1285 }
1286
1287 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1288                              struct kvm_memory_slot *slot, unsigned long data)
1289 {
1290         u64 *sptep;
1291         struct rmap_iterator iter;
1292         int need_flush = 0;
1293         u64 new_spte;
1294         pte_t *ptep = (pte_t *)data;
1295         pfn_t new_pfn;
1296
1297         WARN_ON(pte_huge(*ptep));
1298         new_pfn = pte_pfn(*ptep);
1299
1300         for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1301                 BUG_ON(!is_shadow_present_pte(*sptep));
1302                 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1303
1304                 need_flush = 1;
1305
1306                 if (pte_write(*ptep)) {
1307                         drop_spte(kvm, sptep);
1308                         sptep = rmap_get_first(*rmapp, &iter);
1309                 } else {
1310                         new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1311                         new_spte |= (u64)new_pfn << PAGE_SHIFT;
1312
1313                         new_spte &= ~PT_WRITABLE_MASK;
1314                         new_spte &= ~SPTE_HOST_WRITEABLE;
1315                         new_spte &= ~shadow_accessed_mask;
1316
1317                         mmu_spte_clear_track_bits(sptep);
1318                         mmu_spte_set(sptep, new_spte);
1319                         sptep = rmap_get_next(&iter);
1320                 }
1321         }
1322
1323         if (need_flush)
1324                 kvm_flush_remote_tlbs(kvm);
1325
1326         return 0;
1327 }
1328
1329 static int kvm_handle_hva_range(struct kvm *kvm,
1330                                 unsigned long start,
1331                                 unsigned long end,
1332                                 unsigned long data,
1333                                 int (*handler)(struct kvm *kvm,
1334                                                unsigned long *rmapp,
1335                                                struct kvm_memory_slot *slot,
1336                                                unsigned long data))
1337 {
1338         int j;
1339         int ret = 0;
1340         struct kvm_memslots *slots;
1341         struct kvm_memory_slot *memslot;
1342
1343         slots = kvm_memslots(kvm);
1344
1345         kvm_for_each_memslot(memslot, slots) {
1346                 unsigned long hva_start, hva_end;
1347                 gfn_t gfn_start, gfn_end;
1348
1349                 hva_start = max(start, memslot->userspace_addr);
1350                 hva_end = min(end, memslot->userspace_addr +
1351                                         (memslot->npages << PAGE_SHIFT));
1352                 if (hva_start >= hva_end)
1353                         continue;
1354                 /*
1355                  * {gfn(page) | page intersects with [hva_start, hva_end)} =
1356                  * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1357                  */
1358                 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1359                 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1360
1361                 for (j = PT_PAGE_TABLE_LEVEL;
1362                      j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1363                         unsigned long idx, idx_end;
1364                         unsigned long *rmapp;
1365
1366                         /*
1367                          * {idx(page_j) | page_j intersects with
1368                          *  [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1369                          */
1370                         idx = gfn_to_index(gfn_start, memslot->base_gfn, j);
1371                         idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j);
1372
1373                         rmapp = __gfn_to_rmap(gfn_start, j, memslot);
1374
1375                         for (; idx <= idx_end; ++idx)
1376                                 ret |= handler(kvm, rmapp++, memslot, data);
1377                 }
1378         }
1379
1380         return ret;
1381 }
1382
1383 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1384                           unsigned long data,
1385                           int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1386                                          struct kvm_memory_slot *slot,
1387                                          unsigned long data))
1388 {
1389         return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1390 }
1391
1392 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1393 {
1394         return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1395 }
1396
1397 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1398 {
1399         return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1400 }
1401
1402 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1403 {
1404         kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1405 }
1406
1407 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1408                          struct kvm_memory_slot *slot, unsigned long data)
1409 {
1410         u64 *sptep;
1411         struct rmap_iterator uninitialized_var(iter);
1412         int young = 0;
1413
1414         /*
1415          * In case of absence of EPT Access and Dirty Bits supports,
1416          * emulate the accessed bit for EPT, by checking if this page has
1417          * an EPT mapping, and clearing it if it does. On the next access,
1418          * a new EPT mapping will be established.
1419          * This has some overhead, but not as much as the cost of swapping
1420          * out actively used pages or breaking up actively used hugepages.
1421          */
1422         if (!shadow_accessed_mask) {
1423                 young = kvm_unmap_rmapp(kvm, rmapp, slot, data);
1424                 goto out;
1425         }
1426
1427         for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1428              sptep = rmap_get_next(&iter)) {
1429                 BUG_ON(!is_shadow_present_pte(*sptep));
1430
1431                 if (*sptep & shadow_accessed_mask) {
1432                         young = 1;
1433                         clear_bit((ffs(shadow_accessed_mask) - 1),
1434                                  (unsigned long *)sptep);
1435                 }
1436         }
1437 out:
1438         /* @data has hva passed to kvm_age_hva(). */
1439         trace_kvm_age_page(data, slot, young);
1440         return young;
1441 }
1442
1443 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1444                               struct kvm_memory_slot *slot, unsigned long data)
1445 {
1446         u64 *sptep;
1447         struct rmap_iterator iter;
1448         int young = 0;
1449
1450         /*
1451          * If there's no access bit in the secondary pte set by the
1452          * hardware it's up to gup-fast/gup to set the access bit in
1453          * the primary pte or in the page structure.
1454          */
1455         if (!shadow_accessed_mask)
1456                 goto out;
1457
1458         for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1459              sptep = rmap_get_next(&iter)) {
1460                 BUG_ON(!is_shadow_present_pte(*sptep));
1461
1462                 if (*sptep & shadow_accessed_mask) {
1463                         young = 1;
1464                         break;
1465                 }
1466         }
1467 out:
1468         return young;
1469 }
1470
1471 #define RMAP_RECYCLE_THRESHOLD 1000
1472
1473 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1474 {
1475         unsigned long *rmapp;
1476         struct kvm_mmu_page *sp;
1477
1478         sp = page_header(__pa(spte));
1479
1480         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1481
1482         kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0);
1483         kvm_flush_remote_tlbs(vcpu->kvm);
1484 }
1485
1486 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1487 {
1488         return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp);
1489 }
1490
1491 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1492 {
1493         return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1494 }
1495
1496 #ifdef MMU_DEBUG
1497 static int is_empty_shadow_page(u64 *spt)
1498 {
1499         u64 *pos;
1500         u64 *end;
1501
1502         for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1503                 if (is_shadow_present_pte(*pos)) {
1504                         printk(KERN_ERR "%s: %p %llx\n", __func__,
1505                                pos, *pos);
1506                         return 0;
1507                 }
1508         return 1;
1509 }
1510 #endif
1511
1512 /*
1513  * This value is the sum of all of the kvm instances's
1514  * kvm->arch.n_used_mmu_pages values.  We need a global,
1515  * aggregate version in order to make the slab shrinker
1516  * faster
1517  */
1518 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1519 {
1520         kvm->arch.n_used_mmu_pages += nr;
1521         percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1522 }
1523
1524 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1525 {
1526         ASSERT(is_empty_shadow_page(sp->spt));
1527         hlist_del(&sp->hash_link);
1528         list_del(&sp->link);
1529         free_page((unsigned long)sp->spt);
1530         if (!sp->role.direct)
1531                 free_page((unsigned long)sp->gfns);
1532         kmem_cache_free(mmu_page_header_cache, sp);
1533 }
1534
1535 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1536 {
1537         return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1538 }
1539
1540 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1541                                     struct kvm_mmu_page *sp, u64 *parent_pte)
1542 {
1543         if (!parent_pte)
1544                 return;
1545
1546         pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1547 }
1548
1549 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1550                                        u64 *parent_pte)
1551 {
1552         pte_list_remove(parent_pte, &sp->parent_ptes);
1553 }
1554
1555 static void drop_parent_pte(struct kvm_mmu_page *sp,
1556                             u64 *parent_pte)
1557 {
1558         mmu_page_remove_parent_pte(sp, parent_pte);
1559         mmu_spte_clear_no_track(parent_pte);
1560 }
1561
1562 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1563                                                u64 *parent_pte, int direct)
1564 {
1565         struct kvm_mmu_page *sp;
1566
1567         sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1568         sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1569         if (!direct)
1570                 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1571         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1572
1573         /*
1574          * The active_mmu_pages list is the FIFO list, do not move the
1575          * page until it is zapped. kvm_zap_obsolete_pages depends on
1576          * this feature. See the comments in kvm_zap_obsolete_pages().
1577          */
1578         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1579         sp->parent_ptes = 0;
1580         mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1581         kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1582         return sp;
1583 }
1584
1585 static void mark_unsync(u64 *spte);
1586 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1587 {
1588         pte_list_walk(&sp->parent_ptes, mark_unsync);
1589 }
1590
1591 static void mark_unsync(u64 *spte)
1592 {
1593         struct kvm_mmu_page *sp;
1594         unsigned int index;
1595
1596         sp = page_header(__pa(spte));
1597         index = spte - sp->spt;
1598         if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1599                 return;
1600         if (sp->unsync_children++)
1601                 return;
1602         kvm_mmu_mark_parents_unsync(sp);
1603 }
1604
1605 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1606                                struct kvm_mmu_page *sp)
1607 {
1608         return 1;
1609 }
1610
1611 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1612 {
1613 }
1614
1615 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1616                                  struct kvm_mmu_page *sp, u64 *spte,
1617                                  const void *pte)
1618 {
1619         WARN_ON(1);
1620 }
1621
1622 #define KVM_PAGE_ARRAY_NR 16
1623
1624 struct kvm_mmu_pages {
1625         struct mmu_page_and_offset {
1626                 struct kvm_mmu_page *sp;
1627                 unsigned int idx;
1628         } page[KVM_PAGE_ARRAY_NR];
1629         unsigned int nr;
1630 };
1631
1632 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1633                          int idx)
1634 {
1635         int i;
1636
1637         if (sp->unsync)
1638                 for (i=0; i < pvec->nr; i++)
1639                         if (pvec->page[i].sp == sp)
1640                                 return 0;
1641
1642         pvec->page[pvec->nr].sp = sp;
1643         pvec->page[pvec->nr].idx = idx;
1644         pvec->nr++;
1645         return (pvec->nr == KVM_PAGE_ARRAY_NR);
1646 }
1647
1648 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1649                            struct kvm_mmu_pages *pvec)
1650 {
1651         int i, ret, nr_unsync_leaf = 0;
1652
1653         for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1654                 struct kvm_mmu_page *child;
1655                 u64 ent = sp->spt[i];
1656
1657                 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1658                         goto clear_child_bitmap;
1659
1660                 child = page_header(ent & PT64_BASE_ADDR_MASK);
1661
1662                 if (child->unsync_children) {
1663                         if (mmu_pages_add(pvec, child, i))
1664                                 return -ENOSPC;
1665
1666                         ret = __mmu_unsync_walk(child, pvec);
1667                         if (!ret)
1668                                 goto clear_child_bitmap;
1669                         else if (ret > 0)
1670                                 nr_unsync_leaf += ret;
1671                         else
1672                                 return ret;
1673                 } else if (child->unsync) {
1674                         nr_unsync_leaf++;
1675                         if (mmu_pages_add(pvec, child, i))
1676                                 return -ENOSPC;
1677                 } else
1678                          goto clear_child_bitmap;
1679
1680                 continue;
1681
1682 clear_child_bitmap:
1683                 __clear_bit(i, sp->unsync_child_bitmap);
1684                 sp->unsync_children--;
1685                 WARN_ON((int)sp->unsync_children < 0);
1686         }
1687
1688
1689         return nr_unsync_leaf;
1690 }
1691
1692 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1693                            struct kvm_mmu_pages *pvec)
1694 {
1695         if (!sp->unsync_children)
1696                 return 0;
1697
1698         mmu_pages_add(pvec, sp, 0);
1699         return __mmu_unsync_walk(sp, pvec);
1700 }
1701
1702 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1703 {
1704         WARN_ON(!sp->unsync);
1705         trace_kvm_mmu_sync_page(sp);
1706         sp->unsync = 0;
1707         --kvm->stat.mmu_unsync;
1708 }
1709
1710 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1711                                     struct list_head *invalid_list);
1712 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1713                                     struct list_head *invalid_list);
1714
1715 /*
1716  * NOTE: we should pay more attention on the zapped-obsolete page
1717  * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1718  * since it has been deleted from active_mmu_pages but still can be found
1719  * at hast list.
1720  *
1721  * for_each_gfn_indirect_valid_sp has skipped that kind of page and
1722  * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
1723  * all the obsolete pages.
1724  */
1725 #define for_each_gfn_sp(_kvm, _sp, _gfn)                                \
1726         hlist_for_each_entry(_sp,                                       \
1727           &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1728                 if ((_sp)->gfn != (_gfn)) {} else
1729
1730 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn)                 \
1731         for_each_gfn_sp(_kvm, _sp, _gfn)                                \
1732                 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1733
1734 /* @sp->gfn should be write-protected at the call site */
1735 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1736                            struct list_head *invalid_list, bool clear_unsync)
1737 {
1738         if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1739                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1740                 return 1;
1741         }
1742
1743         if (clear_unsync)
1744                 kvm_unlink_unsync_page(vcpu->kvm, sp);
1745
1746         if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1747                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1748                 return 1;
1749         }
1750
1751         kvm_mmu_flush_tlb(vcpu);
1752         return 0;
1753 }
1754
1755 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1756                                    struct kvm_mmu_page *sp)
1757 {
1758         LIST_HEAD(invalid_list);
1759         int ret;
1760
1761         ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1762         if (ret)
1763                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1764
1765         return ret;
1766 }
1767
1768 #ifdef CONFIG_KVM_MMU_AUDIT
1769 #include "mmu_audit.c"
1770 #else
1771 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1772 static void mmu_audit_disable(void) { }
1773 #endif
1774
1775 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1776                          struct list_head *invalid_list)
1777 {
1778         return __kvm_sync_page(vcpu, sp, invalid_list, true);
1779 }
1780
1781 /* @gfn should be write-protected at the call site */
1782 static void kvm_sync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
1783 {
1784         struct kvm_mmu_page *s;
1785         LIST_HEAD(invalid_list);
1786         bool flush = false;
1787
1788         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1789                 if (!s->unsync)
1790                         continue;
1791
1792                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1793                 kvm_unlink_unsync_page(vcpu->kvm, s);
1794                 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1795                         (vcpu->arch.mmu.sync_page(vcpu, s))) {
1796                         kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1797                         continue;
1798                 }
1799                 flush = true;
1800         }
1801
1802         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1803         if (flush)
1804                 kvm_mmu_flush_tlb(vcpu);
1805 }
1806
1807 struct mmu_page_path {
1808         struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1809         unsigned int idx[PT64_ROOT_LEVEL-1];
1810 };
1811
1812 #define for_each_sp(pvec, sp, parents, i)                       \
1813                 for (i = mmu_pages_next(&pvec, &parents, -1),   \
1814                         sp = pvec.page[i].sp;                   \
1815                         i < pvec.nr && ({ sp = pvec.page[i].sp; 1;});   \
1816                         i = mmu_pages_next(&pvec, &parents, i))
1817
1818 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1819                           struct mmu_page_path *parents,
1820                           int i)
1821 {
1822         int n;
1823
1824         for (n = i+1; n < pvec->nr; n++) {
1825                 struct kvm_mmu_page *sp = pvec->page[n].sp;
1826
1827                 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1828                         parents->idx[0] = pvec->page[n].idx;
1829                         return n;
1830                 }
1831
1832                 parents->parent[sp->role.level-2] = sp;
1833                 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1834         }
1835
1836         return n;
1837 }
1838
1839 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1840 {
1841         struct kvm_mmu_page *sp;
1842         unsigned int level = 0;
1843
1844         do {
1845                 unsigned int idx = parents->idx[level];
1846
1847                 sp = parents->parent[level];
1848                 if (!sp)
1849                         return;
1850
1851                 --sp->unsync_children;
1852                 WARN_ON((int)sp->unsync_children < 0);
1853                 __clear_bit(idx, sp->unsync_child_bitmap);
1854                 level++;
1855         } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1856 }
1857
1858 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1859                                struct mmu_page_path *parents,
1860                                struct kvm_mmu_pages *pvec)
1861 {
1862         parents->parent[parent->role.level-1] = NULL;
1863         pvec->nr = 0;
1864 }
1865
1866 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1867                               struct kvm_mmu_page *parent)
1868 {
1869         int i;
1870         struct kvm_mmu_page *sp;
1871         struct mmu_page_path parents;
1872         struct kvm_mmu_pages pages;
1873         LIST_HEAD(invalid_list);
1874
1875         kvm_mmu_pages_init(parent, &parents, &pages);
1876         while (mmu_unsync_walk(parent, &pages)) {
1877                 bool protected = false;
1878
1879                 for_each_sp(pages, sp, parents, i)
1880                         protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1881
1882                 if (protected)
1883                         kvm_flush_remote_tlbs(vcpu->kvm);
1884
1885                 for_each_sp(pages, sp, parents, i) {
1886                         kvm_sync_page(vcpu, sp, &invalid_list);
1887                         mmu_pages_clear_parents(&parents);
1888                 }
1889                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1890                 cond_resched_lock(&vcpu->kvm->mmu_lock);
1891                 kvm_mmu_pages_init(parent, &parents, &pages);
1892         }
1893 }
1894
1895 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1896 {
1897         int i;
1898
1899         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1900                 sp->spt[i] = 0ull;
1901 }
1902
1903 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1904 {
1905         sp->write_flooding_count = 0;
1906 }
1907
1908 static void clear_sp_write_flooding_count(u64 *spte)
1909 {
1910         struct kvm_mmu_page *sp =  page_header(__pa(spte));
1911
1912         __clear_sp_write_flooding_count(sp);
1913 }
1914
1915 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1916 {
1917         return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1918 }
1919
1920 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1921                                              gfn_t gfn,
1922                                              gva_t gaddr,
1923                                              unsigned level,
1924                                              int direct,
1925                                              unsigned access,
1926                                              u64 *parent_pte)
1927 {
1928         union kvm_mmu_page_role role;
1929         unsigned quadrant;
1930         struct kvm_mmu_page *sp;
1931         bool need_sync = false;
1932
1933         role = vcpu->arch.mmu.base_role;
1934         role.level = level;
1935         role.direct = direct;
1936         if (role.direct)
1937                 role.cr4_pae = 0;
1938         role.access = access;
1939         if (!vcpu->arch.mmu.direct_map
1940             && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1941                 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1942                 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1943                 role.quadrant = quadrant;
1944         }
1945         for_each_gfn_sp(vcpu->kvm, sp, gfn) {
1946                 if (is_obsolete_sp(vcpu->kvm, sp))
1947                         continue;
1948
1949                 if (!need_sync && sp->unsync)
1950                         need_sync = true;
1951
1952                 if (sp->role.word != role.word)
1953                         continue;
1954
1955                 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1956                         break;
1957
1958                 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1959                 if (sp->unsync_children) {
1960                         kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1961                         kvm_mmu_mark_parents_unsync(sp);
1962                 } else if (sp->unsync)
1963                         kvm_mmu_mark_parents_unsync(sp);
1964
1965                 __clear_sp_write_flooding_count(sp);
1966                 trace_kvm_mmu_get_page(sp, false);
1967                 return sp;
1968         }
1969         ++vcpu->kvm->stat.mmu_cache_miss;
1970         sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1971         if (!sp)
1972                 return sp;
1973         sp->gfn = gfn;
1974         sp->role = role;
1975         hlist_add_head(&sp->hash_link,
1976                 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1977         if (!direct) {
1978                 if (rmap_write_protect(vcpu->kvm, gfn))
1979                         kvm_flush_remote_tlbs(vcpu->kvm);
1980                 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1981                         kvm_sync_pages(vcpu, gfn);
1982
1983                 account_shadowed(vcpu->kvm, gfn);
1984         }
1985         sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1986         init_shadow_page_table(sp);
1987         trace_kvm_mmu_get_page(sp, true);
1988         return sp;
1989 }
1990
1991 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1992                              struct kvm_vcpu *vcpu, u64 addr)
1993 {
1994         iterator->addr = addr;
1995         iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1996         iterator->level = vcpu->arch.mmu.shadow_root_level;
1997
1998         if (iterator->level == PT64_ROOT_LEVEL &&
1999             vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2000             !vcpu->arch.mmu.direct_map)
2001                 --iterator->level;
2002
2003         if (iterator->level == PT32E_ROOT_LEVEL) {
2004                 iterator->shadow_addr
2005                         = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2006                 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2007                 --iterator->level;
2008                 if (!iterator->shadow_addr)
2009                         iterator->level = 0;
2010         }
2011 }
2012
2013 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2014 {
2015         if (iterator->level < PT_PAGE_TABLE_LEVEL)
2016                 return false;
2017
2018         iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2019         iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2020         return true;
2021 }
2022
2023 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2024                                u64 spte)
2025 {
2026         if (is_last_spte(spte, iterator->level)) {
2027                 iterator->level = 0;
2028                 return;
2029         }
2030
2031         iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2032         --iterator->level;
2033 }
2034
2035 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2036 {
2037         return __shadow_walk_next(iterator, *iterator->sptep);
2038 }
2039
2040 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp, bool accessed)
2041 {
2042         u64 spte;
2043
2044         BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK ||
2045                         VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2046
2047         spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
2048                shadow_user_mask | shadow_x_mask;
2049
2050         if (accessed)
2051                 spte |= shadow_accessed_mask;
2052
2053         mmu_spte_set(sptep, spte);
2054 }
2055
2056 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2057                                    unsigned direct_access)
2058 {
2059         if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2060                 struct kvm_mmu_page *child;
2061
2062                 /*
2063                  * For the direct sp, if the guest pte's dirty bit
2064                  * changed form clean to dirty, it will corrupt the
2065                  * sp's access: allow writable in the read-only sp,
2066                  * so we should update the spte at this point to get
2067                  * a new sp with the correct access.
2068                  */
2069                 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2070                 if (child->role.access == direct_access)
2071                         return;
2072
2073                 drop_parent_pte(child, sptep);
2074                 kvm_flush_remote_tlbs(vcpu->kvm);
2075         }
2076 }
2077
2078 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2079                              u64 *spte)
2080 {
2081         u64 pte;
2082         struct kvm_mmu_page *child;
2083
2084         pte = *spte;
2085         if (is_shadow_present_pte(pte)) {
2086                 if (is_last_spte(pte, sp->role.level)) {
2087                         drop_spte(kvm, spte);
2088                         if (is_large_pte(pte))
2089                                 --kvm->stat.lpages;
2090                 } else {
2091                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2092                         drop_parent_pte(child, spte);
2093                 }
2094                 return true;
2095         }
2096
2097         if (is_mmio_spte(pte))
2098                 mmu_spte_clear_no_track(spte);
2099
2100         return false;
2101 }
2102
2103 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2104                                          struct kvm_mmu_page *sp)
2105 {
2106         unsigned i;
2107
2108         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2109                 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2110 }
2111
2112 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2113 {
2114         mmu_page_remove_parent_pte(sp, parent_pte);
2115 }
2116
2117 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2118 {
2119         u64 *sptep;
2120         struct rmap_iterator iter;
2121
2122         while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2123                 drop_parent_pte(sp, sptep);
2124 }
2125
2126 static int mmu_zap_unsync_children(struct kvm *kvm,
2127                                    struct kvm_mmu_page *parent,
2128                                    struct list_head *invalid_list)
2129 {
2130         int i, zapped = 0;
2131         struct mmu_page_path parents;
2132         struct kvm_mmu_pages pages;
2133
2134         if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2135                 return 0;
2136
2137         kvm_mmu_pages_init(parent, &parents, &pages);
2138         while (mmu_unsync_walk(parent, &pages)) {
2139                 struct kvm_mmu_page *sp;
2140
2141                 for_each_sp(pages, sp, parents, i) {
2142                         kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2143                         mmu_pages_clear_parents(&parents);
2144                         zapped++;
2145                 }
2146                 kvm_mmu_pages_init(parent, &parents, &pages);
2147         }
2148
2149         return zapped;
2150 }
2151
2152 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2153                                     struct list_head *invalid_list)
2154 {
2155         int ret;
2156
2157         trace_kvm_mmu_prepare_zap_page(sp);
2158         ++kvm->stat.mmu_shadow_zapped;
2159         ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2160         kvm_mmu_page_unlink_children(kvm, sp);
2161         kvm_mmu_unlink_parents(kvm, sp);
2162
2163         if (!sp->role.invalid && !sp->role.direct)
2164                 unaccount_shadowed(kvm, sp->gfn);
2165
2166         if (sp->unsync)
2167                 kvm_unlink_unsync_page(kvm, sp);
2168         if (!sp->root_count) {
2169                 /* Count self */
2170                 ret++;
2171                 list_move(&sp->link, invalid_list);
2172                 kvm_mod_used_mmu_pages(kvm, -1);
2173         } else {
2174                 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2175
2176                 /*
2177                  * The obsolete pages can not be used on any vcpus.
2178                  * See the comments in kvm_mmu_invalidate_zap_all_pages().
2179                  */
2180                 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2181                         kvm_reload_remote_mmus(kvm);
2182         }
2183
2184         sp->role.invalid = 1;
2185         return ret;
2186 }
2187
2188 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2189                                     struct list_head *invalid_list)
2190 {
2191         struct kvm_mmu_page *sp, *nsp;
2192
2193         if (list_empty(invalid_list))
2194                 return;
2195
2196         /*
2197          * wmb: make sure everyone sees our modifications to the page tables
2198          * rmb: make sure we see changes to vcpu->mode
2199          */
2200         smp_mb();
2201
2202         /*
2203          * Wait for all vcpus to exit guest mode and/or lockless shadow
2204          * page table walks.
2205          */
2206         kvm_flush_remote_tlbs(kvm);
2207
2208         list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2209                 WARN_ON(!sp->role.invalid || sp->root_count);
2210                 kvm_mmu_free_page(sp);
2211         }
2212 }
2213
2214 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2215                                         struct list_head *invalid_list)
2216 {
2217         struct kvm_mmu_page *sp;
2218
2219         if (list_empty(&kvm->arch.active_mmu_pages))
2220                 return false;
2221
2222         sp = list_entry(kvm->arch.active_mmu_pages.prev,
2223                         struct kvm_mmu_page, link);
2224         kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2225
2226         return true;
2227 }
2228
2229 /*
2230  * Changing the number of mmu pages allocated to the vm
2231  * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2232  */
2233 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2234 {
2235         LIST_HEAD(invalid_list);
2236
2237         spin_lock(&kvm->mmu_lock);
2238
2239         if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2240                 /* Need to free some mmu pages to achieve the goal. */
2241                 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2242                         if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2243                                 break;
2244
2245                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2246                 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2247         }
2248
2249         kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2250
2251         spin_unlock(&kvm->mmu_lock);
2252 }
2253
2254 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2255 {
2256         struct kvm_mmu_page *sp;
2257         LIST_HEAD(invalid_list);
2258         int r;
2259
2260         pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2261         r = 0;
2262         spin_lock(&kvm->mmu_lock);
2263         for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2264                 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2265                          sp->role.word);
2266                 r = 1;
2267                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2268         }
2269         kvm_mmu_commit_zap_page(kvm, &invalid_list);
2270         spin_unlock(&kvm->mmu_lock);
2271
2272         return r;
2273 }
2274 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2275
2276 /*
2277  * The function is based on mtrr_type_lookup() in
2278  * arch/x86/kernel/cpu/mtrr/generic.c
2279  */
2280 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2281                          u64 start, u64 end)
2282 {
2283         int i;
2284         u64 base, mask;
2285         u8 prev_match, curr_match;
2286         int num_var_ranges = KVM_NR_VAR_MTRR;
2287
2288         if (!mtrr_state->enabled)
2289                 return 0xFF;
2290
2291         /* Make end inclusive end, instead of exclusive */
2292         end--;
2293
2294         /* Look in fixed ranges. Just return the type as per start */
2295         if (mtrr_state->have_fixed && (start < 0x100000)) {
2296                 int idx;
2297
2298                 if (start < 0x80000) {
2299                         idx = 0;
2300                         idx += (start >> 16);
2301                         return mtrr_state->fixed_ranges[idx];
2302                 } else if (start < 0xC0000) {
2303                         idx = 1 * 8;
2304                         idx += ((start - 0x80000) >> 14);
2305                         return mtrr_state->fixed_ranges[idx];
2306                 } else if (start < 0x1000000) {
2307                         idx = 3 * 8;
2308                         idx += ((start - 0xC0000) >> 12);
2309                         return mtrr_state->fixed_ranges[idx];
2310                 }
2311         }
2312
2313         /*
2314          * Look in variable ranges
2315          * Look of multiple ranges matching this address and pick type
2316          * as per MTRR precedence
2317          */
2318         if (!(mtrr_state->enabled & 2))
2319                 return mtrr_state->def_type;
2320
2321         prev_match = 0xFF;
2322         for (i = 0; i < num_var_ranges; ++i) {
2323                 unsigned short start_state, end_state;
2324
2325                 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2326                         continue;
2327
2328                 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2329                        (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2330                 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2331                        (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2332
2333                 start_state = ((start & mask) == (base & mask));
2334                 end_state = ((end & mask) == (base & mask));
2335                 if (start_state != end_state)
2336                         return 0xFE;
2337
2338                 if ((start & mask) != (base & mask))
2339                         continue;
2340
2341                 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2342                 if (prev_match == 0xFF) {
2343                         prev_match = curr_match;
2344                         continue;
2345                 }
2346
2347                 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2348                     curr_match == MTRR_TYPE_UNCACHABLE)
2349                         return MTRR_TYPE_UNCACHABLE;
2350
2351                 if ((prev_match == MTRR_TYPE_WRBACK &&
2352                      curr_match == MTRR_TYPE_WRTHROUGH) ||
2353                     (prev_match == MTRR_TYPE_WRTHROUGH &&
2354                      curr_match == MTRR_TYPE_WRBACK)) {
2355                         prev_match = MTRR_TYPE_WRTHROUGH;
2356                         curr_match = MTRR_TYPE_WRTHROUGH;
2357                 }
2358
2359                 if (prev_match != curr_match)
2360                         return MTRR_TYPE_UNCACHABLE;
2361         }
2362
2363         if (prev_match != 0xFF)
2364                 return prev_match;
2365
2366         return mtrr_state->def_type;
2367 }
2368
2369 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2370 {
2371         u8 mtrr;
2372
2373         mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2374                              (gfn << PAGE_SHIFT) + PAGE_SIZE);
2375         if (mtrr == 0xfe || mtrr == 0xff)
2376                 mtrr = MTRR_TYPE_WRBACK;
2377         return mtrr;
2378 }
2379 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2380
2381 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2382 {
2383         trace_kvm_mmu_unsync_page(sp);
2384         ++vcpu->kvm->stat.mmu_unsync;
2385         sp->unsync = 1;
2386
2387         kvm_mmu_mark_parents_unsync(sp);
2388 }
2389
2390 static void kvm_unsync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
2391 {
2392         struct kvm_mmu_page *s;
2393
2394         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2395                 if (s->unsync)
2396                         continue;
2397                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2398                 __kvm_unsync_page(vcpu, s);
2399         }
2400 }
2401
2402 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2403                                   bool can_unsync)
2404 {
2405         struct kvm_mmu_page *s;
2406         bool need_unsync = false;
2407
2408         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2409                 if (!can_unsync)
2410                         return 1;
2411
2412                 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2413                         return 1;
2414
2415                 if (!s->unsync)
2416                         need_unsync = true;
2417         }
2418         if (need_unsync)
2419                 kvm_unsync_pages(vcpu, gfn);
2420         return 0;
2421 }
2422
2423 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2424                     unsigned pte_access, int level,
2425                     gfn_t gfn, pfn_t pfn, bool speculative,
2426                     bool can_unsync, bool host_writable)
2427 {
2428         u64 spte;
2429         int ret = 0;
2430
2431         if (set_mmio_spte(vcpu->kvm, sptep, gfn, pfn, pte_access))
2432                 return 0;
2433
2434         spte = PT_PRESENT_MASK;
2435         if (!speculative)
2436                 spte |= shadow_accessed_mask;
2437
2438         if (pte_access & ACC_EXEC_MASK)
2439                 spte |= shadow_x_mask;
2440         else
2441                 spte |= shadow_nx_mask;
2442
2443         if (pte_access & ACC_USER_MASK)
2444                 spte |= shadow_user_mask;
2445
2446         if (level > PT_PAGE_TABLE_LEVEL)
2447                 spte |= PT_PAGE_SIZE_MASK;
2448         if (tdp_enabled)
2449                 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2450                         kvm_is_mmio_pfn(pfn));
2451
2452         if (host_writable)
2453                 spte |= SPTE_HOST_WRITEABLE;
2454         else
2455                 pte_access &= ~ACC_WRITE_MASK;
2456
2457         spte |= (u64)pfn << PAGE_SHIFT;
2458
2459         if (pte_access & ACC_WRITE_MASK) {
2460
2461                 /*
2462                  * Other vcpu creates new sp in the window between
2463                  * mapping_level() and acquiring mmu-lock. We can
2464                  * allow guest to retry the access, the mapping can
2465                  * be fixed if guest refault.
2466                  */
2467                 if (level > PT_PAGE_TABLE_LEVEL &&
2468                     has_wrprotected_page(vcpu->kvm, gfn, level))
2469                         goto done;
2470
2471                 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2472
2473                 /*
2474                  * Optimization: for pte sync, if spte was writable the hash
2475                  * lookup is unnecessary (and expensive). Write protection
2476                  * is responsibility of mmu_get_page / kvm_sync_page.
2477                  * Same reasoning can be applied to dirty page accounting.
2478                  */
2479                 if (!can_unsync && is_writable_pte(*sptep))
2480                         goto set_pte;
2481
2482                 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2483                         pgprintk("%s: found shadow page for %llx, marking ro\n",
2484                                  __func__, gfn);
2485                         ret = 1;
2486                         pte_access &= ~ACC_WRITE_MASK;
2487                         spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2488                 }
2489         }
2490
2491         if (pte_access & ACC_WRITE_MASK)
2492                 mark_page_dirty(vcpu->kvm, gfn);
2493
2494 set_pte:
2495         if (mmu_spte_update(sptep, spte))
2496                 kvm_flush_remote_tlbs(vcpu->kvm);
2497 done:
2498         return ret;
2499 }
2500
2501 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2502                          unsigned pte_access, int write_fault, int *emulate,
2503                          int level, gfn_t gfn, pfn_t pfn, bool speculative,
2504                          bool host_writable)
2505 {
2506         int was_rmapped = 0;
2507         int rmap_count;
2508
2509         pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2510                  *sptep, write_fault, gfn);
2511
2512         if (is_rmap_spte(*sptep)) {
2513                 /*
2514                  * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2515                  * the parent of the now unreachable PTE.
2516                  */
2517                 if (level > PT_PAGE_TABLE_LEVEL &&
2518                     !is_large_pte(*sptep)) {
2519                         struct kvm_mmu_page *child;
2520                         u64 pte = *sptep;
2521
2522                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2523                         drop_parent_pte(child, sptep);
2524                         kvm_flush_remote_tlbs(vcpu->kvm);
2525                 } else if (pfn != spte_to_pfn(*sptep)) {
2526                         pgprintk("hfn old %llx new %llx\n",
2527                                  spte_to_pfn(*sptep), pfn);
2528                         drop_spte(vcpu->kvm, sptep);
2529                         kvm_flush_remote_tlbs(vcpu->kvm);
2530                 } else
2531                         was_rmapped = 1;
2532         }
2533
2534         if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2535               true, host_writable)) {
2536                 if (write_fault)
2537                         *emulate = 1;
2538                 kvm_mmu_flush_tlb(vcpu);
2539         }
2540
2541         if (unlikely(is_mmio_spte(*sptep) && emulate))
2542                 *emulate = 1;
2543
2544         pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2545         pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2546                  is_large_pte(*sptep)? "2MB" : "4kB",
2547                  *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2548                  *sptep, sptep);
2549         if (!was_rmapped && is_large_pte(*sptep))
2550                 ++vcpu->kvm->stat.lpages;
2551
2552         if (is_shadow_present_pte(*sptep)) {
2553                 if (!was_rmapped) {
2554                         rmap_count = rmap_add(vcpu, sptep, gfn);
2555                         if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2556                                 rmap_recycle(vcpu, sptep, gfn);
2557                 }
2558         }
2559
2560         kvm_release_pfn_clean(pfn);
2561 }
2562
2563 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2564                                      bool no_dirty_log)
2565 {
2566         struct kvm_memory_slot *slot;
2567
2568         slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2569         if (!slot)
2570                 return KVM_PFN_ERR_FAULT;
2571
2572         return gfn_to_pfn_memslot_atomic(slot, gfn);
2573 }
2574
2575 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2576                                     struct kvm_mmu_page *sp,
2577                                     u64 *start, u64 *end)
2578 {
2579         struct page *pages[PTE_PREFETCH_NUM];
2580         unsigned access = sp->role.access;
2581         int i, ret;
2582         gfn_t gfn;
2583
2584         gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2585         if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2586                 return -1;
2587
2588         ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2589         if (ret <= 0)
2590                 return -1;
2591
2592         for (i = 0; i < ret; i++, gfn++, start++)
2593                 mmu_set_spte(vcpu, start, access, 0, NULL,
2594                              sp->role.level, gfn, page_to_pfn(pages[i]),
2595                              true, true);
2596
2597         return 0;
2598 }
2599
2600 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2601                                   struct kvm_mmu_page *sp, u64 *sptep)
2602 {
2603         u64 *spte, *start = NULL;
2604         int i;
2605
2606         WARN_ON(!sp->role.direct);
2607
2608         i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2609         spte = sp->spt + i;
2610
2611         for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2612                 if (is_shadow_present_pte(*spte) || spte == sptep) {
2613                         if (!start)
2614                                 continue;
2615                         if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2616                                 break;
2617                         start = NULL;
2618                 } else if (!start)
2619                         start = spte;
2620         }
2621 }
2622
2623 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2624 {
2625         struct kvm_mmu_page *sp;
2626
2627         /*
2628          * Since it's no accessed bit on EPT, it's no way to
2629          * distinguish between actually accessed translations
2630          * and prefetched, so disable pte prefetch if EPT is
2631          * enabled.
2632          */
2633         if (!shadow_accessed_mask)
2634                 return;
2635
2636         sp = page_header(__pa(sptep));
2637         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2638                 return;
2639
2640         __direct_pte_prefetch(vcpu, sp, sptep);
2641 }
2642
2643 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2644                         int map_writable, int level, gfn_t gfn, pfn_t pfn,
2645                         bool prefault)
2646 {
2647         struct kvm_shadow_walk_iterator iterator;
2648         struct kvm_mmu_page *sp;
2649         int emulate = 0;
2650         gfn_t pseudo_gfn;
2651
2652         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2653                 return 0;
2654
2655         for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2656                 if (iterator.level == level) {
2657                         mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2658                                      write, &emulate, level, gfn, pfn,
2659                                      prefault, map_writable);
2660                         direct_pte_prefetch(vcpu, iterator.sptep);
2661                         ++vcpu->stat.pf_fixed;
2662                         break;
2663                 }
2664
2665                 drop_large_spte(vcpu, iterator.sptep);
2666                 if (!is_shadow_present_pte(*iterator.sptep)) {
2667                         u64 base_addr = iterator.addr;
2668
2669                         base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2670                         pseudo_gfn = base_addr >> PAGE_SHIFT;
2671                         sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2672                                               iterator.level - 1,
2673                                               1, ACC_ALL, iterator.sptep);
2674
2675                         link_shadow_page(iterator.sptep, sp, true);
2676                 }
2677         }
2678         return emulate;
2679 }
2680
2681 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2682 {
2683         siginfo_t info;
2684
2685         info.si_signo   = SIGBUS;
2686         info.si_errno   = 0;
2687         info.si_code    = BUS_MCEERR_AR;
2688         info.si_addr    = (void __user *)address;
2689         info.si_addr_lsb = PAGE_SHIFT;
2690
2691         send_sig_info(SIGBUS, &info, tsk);
2692 }
2693
2694 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2695 {
2696         /*
2697          * Do not cache the mmio info caused by writing the readonly gfn
2698          * into the spte otherwise read access on readonly gfn also can
2699          * caused mmio page fault and treat it as mmio access.
2700          * Return 1 to tell kvm to emulate it.
2701          */
2702         if (pfn == KVM_PFN_ERR_RO_FAULT)
2703                 return 1;
2704
2705         if (pfn == KVM_PFN_ERR_HWPOISON) {
2706                 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2707                 return 0;
2708         }
2709
2710         return -EFAULT;
2711 }
2712
2713 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2714                                         gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2715 {
2716         pfn_t pfn = *pfnp;
2717         gfn_t gfn = *gfnp;
2718         int level = *levelp;
2719
2720         /*
2721          * Check if it's a transparent hugepage. If this would be an
2722          * hugetlbfs page, level wouldn't be set to
2723          * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2724          * here.
2725          */
2726         if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2727             level == PT_PAGE_TABLE_LEVEL &&
2728             PageTransCompound(pfn_to_page(pfn)) &&
2729             !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2730                 unsigned long mask;
2731                 /*
2732                  * mmu_notifier_retry was successful and we hold the
2733                  * mmu_lock here, so the pmd can't become splitting
2734                  * from under us, and in turn
2735                  * __split_huge_page_refcount() can't run from under
2736                  * us and we can safely transfer the refcount from
2737                  * PG_tail to PG_head as we switch the pfn to tail to
2738                  * head.
2739                  */
2740                 *levelp = level = PT_DIRECTORY_LEVEL;
2741                 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2742                 VM_BUG_ON((gfn & mask) != (pfn & mask));
2743                 if (pfn & mask) {
2744                         gfn &= ~mask;
2745                         *gfnp = gfn;
2746                         kvm_release_pfn_clean(pfn);
2747                         pfn &= ~mask;
2748                         kvm_get_pfn(pfn);
2749                         *pfnp = pfn;
2750                 }
2751         }
2752 }
2753
2754 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2755                                 pfn_t pfn, unsigned access, int *ret_val)
2756 {
2757         bool ret = true;
2758
2759         /* The pfn is invalid, report the error! */
2760         if (unlikely(is_error_pfn(pfn))) {
2761                 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2762                 goto exit;
2763         }
2764
2765         if (unlikely(is_noslot_pfn(pfn)))
2766                 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2767
2768         ret = false;
2769 exit:
2770         return ret;
2771 }
2772
2773 static bool page_fault_can_be_fast(u32 error_code)
2774 {
2775         /*
2776          * Do not fix the mmio spte with invalid generation number which
2777          * need to be updated by slow page fault path.
2778          */
2779         if (unlikely(error_code & PFERR_RSVD_MASK))
2780                 return false;
2781
2782         /*
2783          * #PF can be fast only if the shadow page table is present and it
2784          * is caused by write-protect, that means we just need change the
2785          * W bit of the spte which can be done out of mmu-lock.
2786          */
2787         if (!(error_code & PFERR_PRESENT_MASK) ||
2788               !(error_code & PFERR_WRITE_MASK))
2789                 return false;
2790
2791         return true;
2792 }
2793
2794 static bool
2795 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2796                         u64 *sptep, u64 spte)
2797 {
2798         gfn_t gfn;
2799
2800         WARN_ON(!sp->role.direct);
2801
2802         /*
2803          * The gfn of direct spte is stable since it is calculated
2804          * by sp->gfn.
2805          */
2806         gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2807
2808         if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2809                 mark_page_dirty(vcpu->kvm, gfn);
2810
2811         return true;
2812 }
2813
2814 /*
2815  * Return value:
2816  * - true: let the vcpu to access on the same address again.
2817  * - false: let the real page fault path to fix it.
2818  */
2819 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2820                             u32 error_code)
2821 {
2822         struct kvm_shadow_walk_iterator iterator;
2823         struct kvm_mmu_page *sp;
2824         bool ret = false;
2825         u64 spte = 0ull;
2826
2827         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2828                 return false;
2829
2830         if (!page_fault_can_be_fast(error_code))
2831                 return false;
2832
2833         walk_shadow_page_lockless_begin(vcpu);
2834         for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2835                 if (!is_shadow_present_pte(spte) || iterator.level < level)
2836                         break;
2837
2838         /*
2839          * If the mapping has been changed, let the vcpu fault on the
2840          * same address again.
2841          */
2842         if (!is_rmap_spte(spte)) {
2843                 ret = true;
2844                 goto exit;
2845         }
2846
2847         sp = page_header(__pa(iterator.sptep));
2848         if (!is_last_spte(spte, sp->role.level))
2849                 goto exit;
2850
2851         /*
2852          * Check if it is a spurious fault caused by TLB lazily flushed.
2853          *
2854          * Need not check the access of upper level table entries since
2855          * they are always ACC_ALL.
2856          */
2857          if (is_writable_pte(spte)) {
2858                 ret = true;
2859                 goto exit;
2860         }
2861
2862         /*
2863          * Currently, to simplify the code, only the spte write-protected
2864          * by dirty-log can be fast fixed.
2865          */
2866         if (!spte_is_locklessly_modifiable(spte))
2867                 goto exit;
2868
2869         /*
2870          * Do not fix write-permission on the large spte since we only dirty
2871          * the first page into the dirty-bitmap in fast_pf_fix_direct_spte()
2872          * that means other pages are missed if its slot is dirty-logged.
2873          *
2874          * Instead, we let the slow page fault path create a normal spte to
2875          * fix the access.
2876          *
2877          * See the comments in kvm_arch_commit_memory_region().
2878          */
2879         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2880                 goto exit;
2881
2882         /*
2883          * Currently, fast page fault only works for direct mapping since
2884          * the gfn is not stable for indirect shadow page.
2885          * See Documentation/virtual/kvm/locking.txt to get more detail.
2886          */
2887         ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte);
2888 exit:
2889         trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2890                               spte, ret);
2891         walk_shadow_page_lockless_end(vcpu);
2892
2893         return ret;
2894 }
2895
2896 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2897                          gva_t gva, pfn_t *pfn, bool write, bool *writable);
2898 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
2899
2900 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2901                          gfn_t gfn, bool prefault)
2902 {
2903         int r;
2904         int level;
2905         int force_pt_level;
2906         pfn_t pfn;
2907         unsigned long mmu_seq;
2908         bool map_writable, write = error_code & PFERR_WRITE_MASK;
2909
2910         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2911         if (likely(!force_pt_level)) {
2912                 level = mapping_level(vcpu, gfn);
2913                 /*
2914                  * This path builds a PAE pagetable - so we can map
2915                  * 2mb pages at maximum. Therefore check if the level
2916                  * is larger than that.
2917                  */
2918                 if (level > PT_DIRECTORY_LEVEL)
2919                         level = PT_DIRECTORY_LEVEL;
2920
2921                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2922         } else
2923                 level = PT_PAGE_TABLE_LEVEL;
2924
2925         if (fast_page_fault(vcpu, v, level, error_code))
2926                 return 0;
2927
2928         mmu_seq = vcpu->kvm->mmu_notifier_seq;
2929         smp_rmb();
2930
2931         if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2932                 return 0;
2933
2934         if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2935                 return r;
2936
2937         spin_lock(&vcpu->kvm->mmu_lock);
2938         if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
2939                 goto out_unlock;
2940         make_mmu_pages_available(vcpu);
2941         if (likely(!force_pt_level))
2942                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2943         r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2944                          prefault);
2945         spin_unlock(&vcpu->kvm->mmu_lock);
2946
2947
2948         return r;
2949
2950 out_unlock:
2951         spin_unlock(&vcpu->kvm->mmu_lock);
2952         kvm_release_pfn_clean(pfn);
2953         return 0;
2954 }
2955
2956
2957 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2958 {
2959         int i;
2960         struct kvm_mmu_page *sp;
2961         LIST_HEAD(invalid_list);
2962
2963         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2964                 return;
2965
2966         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2967             (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2968              vcpu->arch.mmu.direct_map)) {
2969                 hpa_t root = vcpu->arch.mmu.root_hpa;
2970
2971                 spin_lock(&vcpu->kvm->mmu_lock);
2972                 sp = page_header(root);
2973                 --sp->root_count;
2974                 if (!sp->root_count && sp->role.invalid) {
2975                         kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2976                         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2977                 }
2978                 spin_unlock(&vcpu->kvm->mmu_lock);
2979                 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2980                 return;
2981         }
2982
2983         spin_lock(&vcpu->kvm->mmu_lock);
2984         for (i = 0; i < 4; ++i) {
2985                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2986
2987                 if (root) {
2988                         root &= PT64_BASE_ADDR_MASK;
2989                         sp = page_header(root);
2990                         --sp->root_count;
2991                         if (!sp->root_count && sp->role.invalid)
2992                                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2993                                                          &invalid_list);
2994                 }
2995                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2996         }
2997         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2998         spin_unlock(&vcpu->kvm->mmu_lock);
2999         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3000 }
3001
3002 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3003 {
3004         int ret = 0;
3005
3006         if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3007                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3008                 ret = 1;
3009         }
3010
3011         return ret;
3012 }
3013
3014 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3015 {
3016         struct kvm_mmu_page *sp;
3017         unsigned i;
3018
3019         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3020                 spin_lock(&vcpu->kvm->mmu_lock);
3021                 make_mmu_pages_available(vcpu);
3022                 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
3023                                       1, ACC_ALL, NULL);
3024                 ++sp->root_count;
3025                 spin_unlock(&vcpu->kvm->mmu_lock);
3026                 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3027         } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3028                 for (i = 0; i < 4; ++i) {
3029                         hpa_t root = vcpu->arch.mmu.pae_root[i];
3030
3031                         ASSERT(!VALID_PAGE(root));
3032                         spin_lock(&vcpu->kvm->mmu_lock);
3033                         make_mmu_pages_available(vcpu);
3034                         sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3035                                               i << 30,
3036                                               PT32_ROOT_LEVEL, 1, ACC_ALL,
3037                                               NULL);
3038                         root = __pa(sp->spt);
3039                         ++sp->root_count;
3040                         spin_unlock(&vcpu->kvm->mmu_lock);
3041                         vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3042                 }
3043                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3044         } else
3045                 BUG();
3046
3047         return 0;
3048 }
3049
3050 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3051 {
3052         struct kvm_mmu_page *sp;
3053         u64 pdptr, pm_mask;
3054         gfn_t root_gfn;
3055         int i;
3056
3057         root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3058
3059         if (mmu_check_root(vcpu, root_gfn))
3060                 return 1;
3061
3062         /*
3063          * Do we shadow a long mode page table? If so we need to
3064          * write-protect the guests page table root.
3065          */
3066         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3067                 hpa_t root = vcpu->arch.mmu.root_hpa;
3068
3069                 ASSERT(!VALID_PAGE(root));
3070
3071                 spin_lock(&vcpu->kvm->mmu_lock);
3072                 make_mmu_pages_available(vcpu);
3073                 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3074                                       0, ACC_ALL, NULL);
3075                 root = __pa(sp->spt);
3076                 ++sp->root_count;
3077                 spin_unlock(&vcpu->kvm->mmu_lock);
3078                 vcpu->arch.mmu.root_hpa = root;
3079                 return 0;
3080         }
3081
3082         /*
3083          * We shadow a 32 bit page table. This may be a legacy 2-level
3084          * or a PAE 3-level page table. In either case we need to be aware that
3085          * the shadow page table may be a PAE or a long mode page table.
3086          */
3087         pm_mask = PT_PRESENT_MASK;
3088         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3089                 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3090
3091         for (i = 0; i < 4; ++i) {
3092                 hpa_t root = vcpu->arch.mmu.pae_root[i];
3093
3094                 ASSERT(!VALID_PAGE(root));
3095                 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3096                         pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3097                         if (!is_present_gpte(pdptr)) {
3098                                 vcpu->arch.mmu.pae_root[i] = 0;
3099                                 continue;
3100                         }
3101                         root_gfn = pdptr >> PAGE_SHIFT;
3102                         if (mmu_check_root(vcpu, root_gfn))
3103                                 return 1;
3104                 }
3105                 spin_lock(&vcpu->kvm->mmu_lock);
3106                 make_mmu_pages_available(vcpu);
3107                 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3108                                       PT32_ROOT_LEVEL, 0,
3109                                       ACC_ALL, NULL);
3110                 root = __pa(sp->spt);
3111                 ++sp->root_count;
3112                 spin_unlock(&vcpu->kvm->mmu_lock);
3113
3114                 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3115         }
3116         vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3117
3118         /*
3119          * If we shadow a 32 bit page table with a long mode page
3120          * table we enter this path.
3121          */
3122         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3123                 if (vcpu->arch.mmu.lm_root == NULL) {
3124                         /*
3125                          * The additional page necessary for this is only
3126                          * allocated on demand.
3127                          */
3128
3129                         u64 *lm_root;
3130
3131                         lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3132                         if (lm_root == NULL)
3133                                 return 1;
3134
3135                         lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3136
3137                         vcpu->arch.mmu.lm_root = lm_root;
3138                 }
3139
3140                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3141         }
3142
3143         return 0;
3144 }
3145
3146 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3147 {
3148         if (vcpu->arch.mmu.direct_map)
3149                 return mmu_alloc_direct_roots(vcpu);
3150         else
3151                 return mmu_alloc_shadow_roots(vcpu);
3152 }
3153
3154 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3155 {
3156         int i;
3157         struct kvm_mmu_page *sp;
3158
3159         if (vcpu->arch.mmu.direct_map)
3160                 return;
3161
3162         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3163                 return;
3164
3165         vcpu_clear_mmio_info(vcpu, ~0ul);
3166         kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3167         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3168                 hpa_t root = vcpu->arch.mmu.root_hpa;
3169                 sp = page_header(root);
3170                 mmu_sync_children(vcpu, sp);
3171                 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3172                 return;
3173         }
3174         for (i = 0; i < 4; ++i) {
3175                 hpa_t root = vcpu->arch.mmu.pae_root[i];
3176
3177                 if (root && VALID_PAGE(root)) {
3178                         root &= PT64_BASE_ADDR_MASK;
3179                         sp = page_header(root);
3180                         mmu_sync_children(vcpu, sp);
3181                 }
3182         }
3183         kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3184 }
3185
3186 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3187 {
3188         spin_lock(&vcpu->kvm->mmu_lock);
3189         mmu_sync_roots(vcpu);
3190         spin_unlock(&vcpu->kvm->mmu_lock);
3191 }
3192 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3193
3194 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3195                                   u32 access, struct x86_exception *exception)
3196 {
3197         if (exception)
3198                 exception->error_code = 0;
3199         return vaddr;
3200 }
3201
3202 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3203                                          u32 access,
3204                                          struct x86_exception *exception)
3205 {
3206         if (exception)
3207                 exception->error_code = 0;
3208         return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
3209 }
3210
3211 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3212 {
3213         if (direct)
3214                 return vcpu_match_mmio_gpa(vcpu, addr);
3215
3216         return vcpu_match_mmio_gva(vcpu, addr);
3217 }
3218
3219
3220 /*
3221  * On direct hosts, the last spte is only allows two states
3222  * for mmio page fault:
3223  *   - It is the mmio spte
3224  *   - It is zapped or it is being zapped.
3225  *
3226  * This function completely checks the spte when the last spte
3227  * is not the mmio spte.
3228  */
3229 static bool check_direct_spte_mmio_pf(u64 spte)
3230 {
3231         return __check_direct_spte_mmio_pf(spte);
3232 }
3233
3234 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3235 {
3236         struct kvm_shadow_walk_iterator iterator;
3237         u64 spte = 0ull;
3238
3239         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3240                 return spte;
3241
3242         walk_shadow_page_lockless_begin(vcpu);
3243         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3244                 if (!is_shadow_present_pte(spte))
3245                         break;
3246         walk_shadow_page_lockless_end(vcpu);
3247
3248         return spte;
3249 }
3250
3251 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3252 {
3253         u64 spte;
3254
3255         if (quickly_check_mmio_pf(vcpu, addr, direct))
3256                 return RET_MMIO_PF_EMULATE;
3257
3258         spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3259
3260         if (is_mmio_spte(spte)) {
3261                 gfn_t gfn = get_mmio_spte_gfn(spte);
3262                 unsigned access = get_mmio_spte_access(spte);
3263
3264                 if (!check_mmio_spte(vcpu->kvm, spte))
3265                         return RET_MMIO_PF_INVALID;
3266
3267                 if (direct)
3268                         addr = 0;
3269
3270                 trace_handle_mmio_page_fault(addr, gfn, access);
3271                 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3272                 return RET_MMIO_PF_EMULATE;
3273         }
3274
3275         /*
3276          * It's ok if the gva is remapped by other cpus on shadow guest,
3277          * it's a BUG if the gfn is not a mmio page.
3278          */
3279         if (direct && !check_direct_spte_mmio_pf(spte))
3280                 return RET_MMIO_PF_BUG;
3281
3282         /*
3283          * If the page table is zapped by other cpus, let CPU fault again on
3284          * the address.
3285          */
3286         return RET_MMIO_PF_RETRY;
3287 }
3288 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3289
3290 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3291                                   u32 error_code, bool direct)
3292 {
3293         int ret;
3294
3295         ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3296         WARN_ON(ret == RET_MMIO_PF_BUG);
3297         return ret;
3298 }
3299
3300 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3301                                 u32 error_code, bool prefault)
3302 {
3303         gfn_t gfn;
3304         int r;
3305
3306         pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3307
3308         if (unlikely(error_code & PFERR_RSVD_MASK)) {
3309                 r = handle_mmio_page_fault(vcpu, gva, error_code, true);
3310
3311                 if (likely(r != RET_MMIO_PF_INVALID))
3312                         return r;
3313         }
3314
3315         r = mmu_topup_memory_caches(vcpu);
3316         if (r)
3317                 return r;
3318
3319         ASSERT(vcpu);
3320         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3321
3322         gfn = gva >> PAGE_SHIFT;
3323
3324         return nonpaging_map(vcpu, gva & PAGE_MASK,
3325                              error_code, gfn, prefault);
3326 }
3327
3328 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3329 {
3330         struct kvm_arch_async_pf arch;
3331
3332         arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3333         arch.gfn = gfn;
3334         arch.direct_map = vcpu->arch.mmu.direct_map;
3335         arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3336
3337         return kvm_setup_async_pf(vcpu, gva, gfn_to_hva(vcpu->kvm, gfn), &arch);
3338 }
3339
3340 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3341 {
3342         if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3343                      kvm_event_needs_reinjection(vcpu)))
3344                 return false;
3345
3346         return kvm_x86_ops->interrupt_allowed(vcpu);
3347 }
3348
3349 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3350                          gva_t gva, pfn_t *pfn, bool write, bool *writable)
3351 {
3352         bool async;
3353
3354         *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3355
3356         if (!async)
3357                 return false; /* *pfn has correct page already */
3358
3359         if (!prefault && can_do_async_pf(vcpu)) {
3360                 trace_kvm_try_async_get_page(gva, gfn);
3361                 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3362                         trace_kvm_async_pf_doublefault(gva, gfn);
3363                         kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3364                         return true;
3365                 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3366                         return true;
3367         }
3368
3369         *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3370
3371         return false;
3372 }
3373
3374 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3375                           bool prefault)
3376 {
3377         pfn_t pfn;
3378         int r;
3379         int level;
3380         int force_pt_level;
3381         gfn_t gfn = gpa >> PAGE_SHIFT;
3382         unsigned long mmu_seq;
3383         int write = error_code & PFERR_WRITE_MASK;
3384         bool map_writable;
3385
3386         ASSERT(vcpu);
3387         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3388
3389         if (unlikely(error_code & PFERR_RSVD_MASK)) {
3390                 r = handle_mmio_page_fault(vcpu, gpa, error_code, true);
3391
3392                 if (likely(r != RET_MMIO_PF_INVALID))
3393                         return r;
3394         }
3395
3396         r = mmu_topup_memory_caches(vcpu);
3397         if (r)
3398                 return r;
3399
3400         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3401         if (likely(!force_pt_level)) {
3402                 level = mapping_level(vcpu, gfn);
3403                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3404         } else
3405                 level = PT_PAGE_TABLE_LEVEL;
3406
3407         if (fast_page_fault(vcpu, gpa, level, error_code))
3408                 return 0;
3409
3410         mmu_seq = vcpu->kvm->mmu_notifier_seq;
3411         smp_rmb();
3412
3413         if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3414                 return 0;
3415
3416         if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3417                 return r;
3418
3419         spin_lock(&vcpu->kvm->mmu_lock);
3420         if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3421                 goto out_unlock;
3422         make_mmu_pages_available(vcpu);
3423         if (likely(!force_pt_level))
3424                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3425         r = __direct_map(vcpu, gpa, write, map_writable,
3426                          level, gfn, pfn, prefault);
3427         spin_unlock(&vcpu->kvm->mmu_lock);
3428
3429         return r;
3430
3431 out_unlock:
3432         spin_unlock(&vcpu->kvm->mmu_lock);
3433         kvm_release_pfn_clean(pfn);
3434         return 0;
3435 }
3436
3437 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3438                                    struct kvm_mmu *context)
3439 {
3440         context->page_fault = nonpaging_page_fault;
3441         context->gva_to_gpa = nonpaging_gva_to_gpa;
3442         context->sync_page = nonpaging_sync_page;
3443         context->invlpg = nonpaging_invlpg;
3444         context->update_pte = nonpaging_update_pte;
3445         context->root_level = 0;
3446         context->shadow_root_level = PT32E_ROOT_LEVEL;
3447         context->root_hpa = INVALID_PAGE;
3448         context->direct_map = true;
3449         context->nx = false;
3450 }
3451
3452 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3453 {
3454         ++vcpu->stat.tlb_flush;
3455         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3456 }
3457 EXPORT_SYMBOL_GPL(kvm_mmu_flush_tlb);
3458
3459 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3460 {
3461         mmu_free_roots(vcpu);
3462 }
3463
3464 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3465 {
3466         return kvm_read_cr3(vcpu);
3467 }
3468
3469 static void inject_page_fault(struct kvm_vcpu *vcpu,
3470                               struct x86_exception *fault)
3471 {
3472         vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3473 }
3474
3475 static bool sync_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
3476                            unsigned access, int *nr_present)
3477 {
3478         if (unlikely(is_mmio_spte(*sptep))) {
3479                 if (gfn != get_mmio_spte_gfn(*sptep)) {
3480                         mmu_spte_clear_no_track(sptep);
3481                         return true;
3482                 }
3483
3484                 (*nr_present)++;
3485                 mark_mmio_spte(kvm, sptep, gfn, access);
3486                 return true;
3487         }
3488
3489         return false;
3490 }
3491
3492 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3493 {
3494         unsigned index;
3495
3496         index = level - 1;
3497         index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3498         return mmu->last_pte_bitmap & (1 << index);
3499 }
3500
3501 #define PTTYPE_EPT 18 /* arbitrary */
3502 #define PTTYPE PTTYPE_EPT
3503 #include "paging_tmpl.h"
3504 #undef PTTYPE
3505
3506 #define PTTYPE 64
3507 #include "paging_tmpl.h"
3508 #undef PTTYPE
3509
3510 #define PTTYPE 32
3511 #include "paging_tmpl.h"
3512 #undef PTTYPE
3513
3514 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3515                                   struct kvm_mmu *context)
3516 {
3517         int maxphyaddr = cpuid_maxphyaddr(vcpu);
3518         u64 exb_bit_rsvd = 0;
3519         u64 gbpages_bit_rsvd = 0;
3520
3521         context->bad_mt_xwr = 0;
3522
3523         if (!context->nx)
3524                 exb_bit_rsvd = rsvd_bits(63, 63);
3525         if (!guest_cpuid_has_gbpages(vcpu))
3526                 gbpages_bit_rsvd = rsvd_bits(7, 7);
3527         switch (context->root_level) {
3528         case PT32_ROOT_LEVEL:
3529                 /* no rsvd bits for 2 level 4K page table entries */
3530                 context->rsvd_bits_mask[0][1] = 0;
3531                 context->rsvd_bits_mask[0][0] = 0;
3532                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3533
3534                 if (!is_pse(vcpu)) {
3535                         context->rsvd_bits_mask[1][1] = 0;
3536                         break;
3537                 }
3538
3539                 if (is_cpuid_PSE36())
3540                         /* 36bits PSE 4MB page */
3541                         context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3542                 else
3543                         /* 32 bits PSE 4MB page */
3544                         context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3545                 break;
3546         case PT32E_ROOT_LEVEL:
3547                 context->rsvd_bits_mask[0][2] =
3548                         rsvd_bits(maxphyaddr, 63) |
3549                         rsvd_bits(5, 8) | rsvd_bits(1, 2);      /* PDPTE */
3550                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3551                         rsvd_bits(maxphyaddr, 62);      /* PDE */
3552                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3553                         rsvd_bits(maxphyaddr, 62);      /* PTE */
3554                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3555                         rsvd_bits(maxphyaddr, 62) |
3556                         rsvd_bits(13, 20);              /* large page */
3557                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3558                 break;
3559         case PT64_ROOT_LEVEL:
3560                 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3561                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 7);
3562                 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3563                         gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51);
3564                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3565                         rsvd_bits(maxphyaddr, 51);
3566                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3567                         rsvd_bits(maxphyaddr, 51);
3568                 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3569                 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3570                         gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
3571                         rsvd_bits(13, 29);
3572                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3573                         rsvd_bits(maxphyaddr, 51) |
3574                         rsvd_bits(13, 20);              /* large page */
3575                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3576                 break;
3577         }
3578 }
3579
3580 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
3581                 struct kvm_mmu *context, bool execonly)
3582 {
3583         int maxphyaddr = cpuid_maxphyaddr(vcpu);
3584         int pte;
3585
3586         context->rsvd_bits_mask[0][3] =
3587                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
3588         context->rsvd_bits_mask[0][2] =
3589                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3590         context->rsvd_bits_mask[0][1] =
3591                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3592         context->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
3593
3594         /* large page */
3595         context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3596         context->rsvd_bits_mask[1][2] =
3597                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
3598         context->rsvd_bits_mask[1][1] =
3599                 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
3600         context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3601
3602         for (pte = 0; pte < 64; pte++) {
3603                 int rwx_bits = pte & 7;
3604                 int mt = pte >> 3;
3605                 if (mt == 0x2 || mt == 0x3 || mt == 0x7 ||
3606                                 rwx_bits == 0x2 || rwx_bits == 0x6 ||
3607                                 (rwx_bits == 0x4 && !execonly))
3608                         context->bad_mt_xwr |= (1ull << pte);
3609         }
3610 }
3611
3612 void update_permission_bitmask(struct kvm_vcpu *vcpu,
3613                 struct kvm_mmu *mmu, bool ept)
3614 {
3615         unsigned bit, byte, pfec;
3616         u8 map;
3617         bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0;
3618
3619         cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3620         cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
3621         for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3622                 pfec = byte << 1;
3623                 map = 0;
3624                 wf = pfec & PFERR_WRITE_MASK;
3625                 uf = pfec & PFERR_USER_MASK;
3626                 ff = pfec & PFERR_FETCH_MASK;
3627                 /*
3628                  * PFERR_RSVD_MASK bit is set in PFEC if the access is not
3629                  * subject to SMAP restrictions, and cleared otherwise. The
3630                  * bit is only meaningful if the SMAP bit is set in CR4.
3631                  */
3632                 smapf = !(pfec & PFERR_RSVD_MASK);
3633                 for (bit = 0; bit < 8; ++bit) {
3634                         x = bit & ACC_EXEC_MASK;
3635                         w = bit & ACC_WRITE_MASK;
3636                         u = bit & ACC_USER_MASK;
3637
3638                         if (!ept) {
3639                                 /* Not really needed: !nx will cause pte.nx to fault */
3640                                 x |= !mmu->nx;
3641                                 /* Allow supervisor writes if !cr0.wp */
3642                                 w |= !is_write_protection(vcpu) && !uf;
3643                                 /* Disallow supervisor fetches of user code if cr4.smep */
3644                                 x &= !(cr4_smep && u && !uf);
3645
3646                                 /*
3647                                  * SMAP:kernel-mode data accesses from user-mode
3648                                  * mappings should fault. A fault is considered
3649                                  * as a SMAP violation if all of the following
3650                                  * conditions are ture:
3651                                  *   - X86_CR4_SMAP is set in CR4
3652                                  *   - An user page is accessed
3653                                  *   - Page fault in kernel mode
3654                                  *   - if CPL = 3 or X86_EFLAGS_AC is clear
3655                                  *
3656                                  *   Here, we cover the first three conditions.
3657                                  *   The fourth is computed dynamically in
3658                                  *   permission_fault() and is in smapf.
3659                                  *
3660                                  *   Also, SMAP does not affect instruction
3661                                  *   fetches, add the !ff check here to make it
3662                                  *   clearer.
3663                                  */
3664                                 smap = cr4_smap && u && !uf && !ff;
3665                         } else
3666                                 /* Not really needed: no U/S accesses on ept  */
3667                                 u = 1;
3668
3669                         fault = (ff && !x) || (uf && !u) || (wf && !w) ||
3670                                 (smapf && smap);
3671                         map |= fault << bit;
3672                 }
3673                 mmu->permissions[byte] = map;
3674         }
3675 }
3676
3677 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3678 {
3679         u8 map;
3680         unsigned level, root_level = mmu->root_level;
3681         const unsigned ps_set_index = 1 << 2;  /* bit 2 of index: ps */
3682
3683         if (root_level == PT32E_ROOT_LEVEL)
3684                 --root_level;
3685         /* PT_PAGE_TABLE_LEVEL always terminates */
3686         map = 1 | (1 << ps_set_index);
3687         for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3688                 if (level <= PT_PDPE_LEVEL
3689                     && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3690                         map |= 1 << (ps_set_index | (level - 1));
3691         }
3692         mmu->last_pte_bitmap = map;
3693 }
3694
3695 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
3696                                          struct kvm_mmu *context,
3697                                          int level)
3698 {
3699         context->nx = is_nx(vcpu);
3700         context->root_level = level;
3701
3702         reset_rsvds_bits_mask(vcpu, context);
3703         update_permission_bitmask(vcpu, context, false);
3704         update_last_pte_bitmap(vcpu, context);
3705
3706         ASSERT(is_pae(vcpu));
3707         context->page_fault = paging64_page_fault;
3708         context->gva_to_gpa = paging64_gva_to_gpa;
3709         context->sync_page = paging64_sync_page;
3710         context->invlpg = paging64_invlpg;
3711         context->update_pte = paging64_update_pte;
3712         context->shadow_root_level = level;
3713         context->root_hpa = INVALID_PAGE;
3714         context->direct_map = false;
3715 }
3716
3717 static void paging64_init_context(struct kvm_vcpu *vcpu,
3718                                   struct kvm_mmu *context)
3719 {
3720         paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3721 }
3722
3723 static void paging32_init_context(struct kvm_vcpu *vcpu,
3724                                   struct kvm_mmu *context)
3725 {
3726         context->nx = false;
3727         context->root_level = PT32_ROOT_LEVEL;
3728
3729         reset_rsvds_bits_mask(vcpu, context);
3730         update_permission_bitmask(vcpu, context, false);
3731         update_last_pte_bitmap(vcpu, context);
3732
3733         context->page_fault = paging32_page_fault;
3734         context->gva_to_gpa = paging32_gva_to_gpa;
3735         context->sync_page = paging32_sync_page;
3736         context->invlpg = paging32_invlpg;
3737         context->update_pte = paging32_update_pte;
3738         context->shadow_root_level = PT32E_ROOT_LEVEL;
3739         context->root_hpa = INVALID_PAGE;
3740         context->direct_map = false;
3741 }
3742
3743 static void paging32E_init_context(struct kvm_vcpu *vcpu,
3744                                    struct kvm_mmu *context)
3745 {
3746         paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3747 }
3748
3749 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3750 {
3751         struct kvm_mmu *context = vcpu->arch.walk_mmu;
3752
3753         context->base_role.word = 0;
3754         context->page_fault = tdp_page_fault;
3755         context->sync_page = nonpaging_sync_page;
3756         context->invlpg = nonpaging_invlpg;
3757         context->update_pte = nonpaging_update_pte;
3758         context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3759         context->root_hpa = INVALID_PAGE;
3760         context->direct_map = true;
3761         context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3762         context->get_cr3 = get_cr3;
3763         context->get_pdptr = kvm_pdptr_read;
3764         context->inject_page_fault = kvm_inject_page_fault;
3765
3766         if (!is_paging(vcpu)) {
3767                 context->nx = false;
3768                 context->gva_to_gpa = nonpaging_gva_to_gpa;
3769                 context->root_level = 0;
3770         } else if (is_long_mode(vcpu)) {
3771                 context->nx = is_nx(vcpu);
3772                 context->root_level = PT64_ROOT_LEVEL;
3773                 reset_rsvds_bits_mask(vcpu, context);
3774                 context->gva_to_gpa = paging64_gva_to_gpa;
3775         } else if (is_pae(vcpu)) {
3776                 context->nx = is_nx(vcpu);
3777                 context->root_level = PT32E_ROOT_LEVEL;
3778                 reset_rsvds_bits_mask(vcpu, context);
3779                 context->gva_to_gpa = paging64_gva_to_gpa;
3780         } else {
3781                 context->nx = false;
3782                 context->root_level = PT32_ROOT_LEVEL;
3783                 reset_rsvds_bits_mask(vcpu, context);
3784                 context->gva_to_gpa = paging32_gva_to_gpa;
3785         }
3786
3787         update_permission_bitmask(vcpu, context, false);
3788         update_last_pte_bitmap(vcpu, context);
3789 }
3790
3791 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3792 {
3793         bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3794         ASSERT(vcpu);
3795         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3796
3797         if (!is_paging(vcpu))
3798                 nonpaging_init_context(vcpu, context);
3799         else if (is_long_mode(vcpu))
3800                 paging64_init_context(vcpu, context);
3801         else if (is_pae(vcpu))
3802                 paging32E_init_context(vcpu, context);
3803         else
3804                 paging32_init_context(vcpu, context);
3805
3806         vcpu->arch.mmu.base_role.nxe = is_nx(vcpu);
3807         vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3808         vcpu->arch.mmu.base_role.cr0_wp  = is_write_protection(vcpu);
3809         vcpu->arch.mmu.base_role.smep_andnot_wp
3810                 = smep && !is_write_protection(vcpu);
3811 }
3812 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3813
3814 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
3815                 bool execonly)
3816 {
3817         ASSERT(vcpu);
3818         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3819
3820         context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3821
3822         context->nx = true;
3823         context->page_fault = ept_page_fault;
3824         context->gva_to_gpa = ept_gva_to_gpa;
3825         context->sync_page = ept_sync_page;
3826         context->invlpg = ept_invlpg;
3827         context->update_pte = ept_update_pte;
3828         context->root_level = context->shadow_root_level;
3829         context->root_hpa = INVALID_PAGE;
3830         context->direct_map = false;
3831
3832         update_permission_bitmask(vcpu, context, true);
3833         reset_rsvds_bits_mask_ept(vcpu, context, execonly);
3834 }
3835 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
3836
3837 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
3838 {
3839         kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);